Design and Verification of LTSSM in USB 3.

0
Kamini Jha Ajit. B. Patil Deepti.S. Khurge
Electronics and Telecommunication Electronics and Telecommunication Electronics and Telecommunication
Engineering Engineering Engineering
Pimpri Chinchwad College Of Pimpri Chinchwad College Of Pimpri Chinchwad College Of
Engineering Engineering Engineering
Pune Pune Pune
jhakamini120@gmail.com abpatil1212@yahoo.co.in deepti_pachu@yahoo.com

Abstract— At present as technology is increasing rapidly , • USB 3.0: It was Released in November 2008 with
communication have become an important part of digital featured data transfer rate of 5 GBit/s. It is also called
world. The fact that exchange of data is increasing with a Superspeed Bus.
greater reliability of high performance and processing speed
the USB protocol engine have made an attempt to establish II. USB 3.0 ARCHITECTURE OVERVIEW
itself in the field of digital communications with all of the
necessary protocol layers with excellent features and USB 3.0, otherwise called Super Speed USB, is the following
specifications which enable the flow of data very smoothly. The developmental period of the Universal Serial Bus after 1.0
architecture for USB 3.0 provided will increase the USB and 2.0, the best and omnipresent interface standard at any
overall speed and performance with having layered protocol point made. It keeps on growing in limit, speed, and
architecture. USB 3.0, LTSSM includes the physical and link compactness giving information rate of 5 Gbit/s..Thus, this
layer which includes greater superspeed functionality than the Super Speed USB has much more improvements than Hi-
previous version. USB 3.0 protocol is used generally for Speed USB (USB2.0). The following improvement indicates
connecting PCs to peripheral devices, supporting data improvement in its features:
transferring rate of 5 Gbit/s . In this paper design of LTSSM
which consists of 12 link states has been explained. Also
Verification of LTTSM has been done using System Verilog. • Increased transfer speed
All simulations are done using Mentor Graphics Tool. • Advanced power consumption features
Functional verification for LTSSM has been done. • Improved bandwidth
• Increased maximum bus utilization
Keywords— USB 3.0, Physical Layer, PHY, MAC, LTSSM
• Backward USB 2.0 compatibility[1]

I. INTRODUCTION
The use of many digital peripherals for exchange of data
between the computing devices is been increasing day to
day which leads to the design of USB protocol which have
many advantages over the other peripheral protocols. For
Several considerations like ease-of-use, Port expansion etc .
USB 3.0 came into existence and provided a data rate of 5
Gbits/s. User Application media like audio, video, voice
have full support to the protocol to most of PC’s
peripherals, etc and other computing devices. The USB is
still the answer to connectivity for consumer electronics,
PC and mobile architectures. It has features like
bidirectional, fast, dynamically attachable and low-cost
interface fulfilling the requirement of interconnection[2].
Earlier Versions of USB Specification:

• USB 1.0: It was Released in January 1996 with

highlighted supporting information rates of 1.5Mbit/s
(Low-Bandwidth) and 12Mbit/s (Full Bandwidth). Its has
impediments like not allowing for extension of cables or
pass through monitors because of timing and power
confinements. Fig. 1. USB 3.0 Architecture Diagram [4]
• USB 1.1: It was Released in September 1998. It has
restrictions like Fixed issues recognized in USB variant USB 3.0 Superspeed Bus Architecture consists of Host that
1.0, for the most part relating to hubs. is used to initiate transfer , hubs for interconnection of 1 or
• USB 2.0: It was Released in April 2000. In contrast with more devices and devices that respond to transfer. USB 3.0
prior adaptations it included High most extreme data has star tiered topology with single host at level 1 and hubs
transfer capacity of 480 Mbit/s presently called Hi - are at lower level/tiers to provide bus connectivity [2].
Speed.

978-1-5386-5257-2/18/$31.00©2018IEEE
 It is a dual bus architecture which has backward and management and connectivity ,Consisting of 12 different
forward compatibility. Figure 1 represents USB 3.0 link states with various functionalities.
architecture which has USB 2.0 in parallel. USB 3.0 is also There are four operational link states such as U0, U1, U2,
called as superspeed bus due to data transferring rate of 5 and U3. Then the link states such as Polling, Rx. Detect,
Gbit/s. Hot Reset and Recovery are introduced for link training and
initialization. The next states are Compliance Mode and
USB 3.0 communication model consists of physical
Loopback which are introduced for transmitter compliance
layer, link layer and protocol layer. The physical layer
test and bit error test .More two states are there which are
handles low level PCI express and signalling. The link layer
Superspeed_Disable,Superspeed_Inactive[1].
includes successful link transfer between two link states. It
The LTSSM state diagram for 12 link states is shown in Fig. 3.
consists of 12 link states. The protocol layer function is to
1.SS_Disable:
define rules for communication between host and device.
Superspeed Disable is the state in which receiver
USB 3.0 communication model is shown in Figure 2. termination is removed and Superspeed connectivity is
All communication happens on the link, no interface is disabled.In this state SS connectivity is disabled and acts as
implied between each layer. Application and driver software USB 2.0[1].
communicate with device endpoints using end-to-end transfers. 2.SS_Inactive
1. Protocol Layer SS_Inactive states that link state has failed SS operation.
Software schedules transactions as sequences of token – During this state SS_Inactive.disconnect.detect performs far
data– handshake packets. End –to-end flow control allows end receiver termination detection..In this state a port shall
device endpoints to inform the host of buffer availability. exit to Rx_Detect upon detection of absence of a far end
receiver.
2. Link Layer 3.Rx_Detect
Operates under control of Protocol layer and is responsible for Rx_Detect detects the presence of superspeed partner. From
reliability of link. Processes all inbound /outbound packets, this state a port shall transition to polling upon detection of
including packet framing and CRC generation and checking. a far end receiver.
Manages Link Training, link flow control, and error It has three substates.Rx_Detect_Reset is a state designed
recovery and other maintenance tasks. for two ports to synchronize their operation on warm reset.
Rx_Detect_Active detects the presence of a superspeed
3. Physical Layer link partner.Rx_Detect_Quiet in this state port has disabled
Handles byte scrambling, encoding and serialization receiver termination detection.
required for SS transmission.

Fig 3. LTSSM State Diagram[4]

4.Polling
Fig2. USB 3.0 Communication Layers Polling is the state designed for link training and
III. LTSSM OVERVIEW initialization. In Polling state LFPS handshake takes place
Link Training and Status State Machine (LTSSM) in link between two ports before SS training starts . Bit_Lock,
layer is a state machine defined for lower power Symbol_lock and Rx_Equilization are also achieved.

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)
It consists of Five subsets, dumped and compared for equivalence once the execution is
over. The testbench environment includes different types of
1. Polling.LFPS environments to be developed for effectively verifying the
2. Polling.RxEq design under verification.
3. Polling.Active Figure 4 shows the LTSSM verification plan.It consists of
4. Polling.configuration Stimulus, Generator, scoreboard, Driver, monitor, DUT.
5. Polling.Idle 1. Sequencer
5.Compliance Mode Sequencer is an object that defines a set of transactions
This mode is used to test the transmitter for compliance to to be executed and controls the execution of other
voltage and timing specifications. In this state the port sequences.
shallwait until its Tx DC common mode voltage meets the
voltage specification. 2. Driver
It is the component responsible for executing or
6.U0 processing transactions and provides stimuli to the
In this state packets are transmitted and receive. Port can design-under-test (DUT).
move from U0 to lower power state such as U1 when it 3. Monitor
receives successful entry sequence command LG0_U1 for This block continuously monitors the DUT signals and
achieving more power consumption .Similarly is for U1 and bus functions.
U2. 4. Scoreboard
Driver requests are transferred to the scoreboard via
7.U1 monitor block.
In U1 state no packets are transferred so it achieves more
power consumtion. Port moves from U1 to appropriate state V.RESULTS
upon directed.The port directs from U1 to recovery upon The results shown below give the idea of Link Training and
successful completion of LFPS handshake. initialization and its working with waveform and transcript
8.U2 window.
In this state more power saving opurtunities are there. In this LTSSM is a state machine defined for lower power
state more power is saved compare to U1. management and connectivity consisting of 12 different link
states with various functionalities such as receiver detection,
9.U3 handshake ,power management.
In this state link is put into suspend state. In this state The Figure 5 waveform shows 12 different link states. First is
extreme power is saved in comparison to other states hot_reset state 4’h8 .After hot_reset state SS_Inactive state
10.Recovery 4’h1 is achieved.If Receiver is detected Rx_detect 4’h2 state is
Recovery state means to retain the link or to perform Hot_Reset achieved.After detection of the presence of superspeed link
or to switch back to Loopback mode. It should meet the partner , the link training process will be started superspeed
transmitter specifications.Port will move from Recovery state to transmitters and receivers between two link partners are
other state upon directed.It has three substates trained in polling state.
,active,configuration and idle.

11.LoopBack
In this state test and fault isolation are done . It includes
BitError Rate Test(BERT) state machine. Port moves from
LoopBack to other state upon directed.

12.Hot_Reset
Hot_Reset. State is initiated by downstream port. It resets
whole operation. After reset signal is asserted it transmits TS2
ordered sets.

IV. SYSTEM VERILOG ENVIRONMENT

System Verilog Hardware Descriptive Language has been
used for Verification. Object Oriented Programming (OOP)
technique is applied in verification environment of System
Verilog.Verification flow starts with understanding the
architecture specification of the design under verification.
Once the architecture is well understood then comes the
verification plan.The Verification plan consists of Base
Packet , Stimulus Generator,Driver ,monitor and Fig. 4 Environment Plan
preparation of some testcase scenarios.Figure 4 explains
flow diagram for Verification. Performs functional
verification in a static manner using functional model.Using
Static Environment the results of DUT and model are

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)
 VBUS and its results are shown on scoreboard. All the
Simulations are done using Mentor graphics tool.
REFERENCES
[1] M.Sukhanya.,T.ChandraKumar, K.Gavaskar, and Iqbalur. Rahman
Rokon, “Design and Verification of LTSSM in USB 3.0 Link Layer
using System Verilog",ICSCN, IEEE 2017
[2] Rohit Kumar, “Design and Verification of USB 3.0 Link Layer
(LTSSM)”, IJCSIT, International Journal of Computer Science and
Information Technologies, Vol. 5, 2014.
[3] A B M Najmul. Karim, Mohammad. Anas, Tasha. Afreen, and Iqbalur.
Rahman Rokon, “FPGA Implementation of USB 3.0 (Super-Speed
Bus) Function IP Protocol using Verilog HDL", ICPESA 2013.
[4] “Universal Serial Bus 3.0 Specification”, Revision 1.0,
[5] “Universal Serial Bus 2.0 Specification”, Revision 1.0,
[6] Krunal Kapadiya , “Verification of USB 3.0 Device IP using UVM
Fig. 5. LTSSM Wavefor ",International Journal of Engineering Research and Applications
IJERA 2013.
[7] Arpit Patel, “UVM Based Verification Environment for USB 3.0
Physical layer and LTSSM of Link layer ",International Journal on
Recent and Innovation Trends in Computing and Communication.
[8] Donovan (Don) Anderson, “Introduction to USB 3.0",Mindshare.
[9] KanikaSahni,KiranRawat,SujataPandey,Jyoti Rawat, “Design and
Verification of 8b/10b Encoder/Decoder for USB 3.0
applications",IEEE International Conference on Computer,
Communication and Control (IC4-2015)
[10] Verilog HDL by Sameer Palnitkar.
[11] Julien Saadé1 , Frédéric Pétrot , André Picco, Joel Huloux, Abdelaziz
Goulahsen , “A System-Level Overview and Comparison of Three
High-Speed Serial Links: USB 3.0, PCI Express 2.0 and LLI 1.0",IEEE
2013.

Fig. 6 Transcript Window

The Transcript window shows different link states values like
first states reser value is 1000.After these state next link state
is Rx_detect which is 0001.It also shows values of clk,rst and
other signals.

The Constrained Randomization Technique is applied for

the inputs of the LTSSM and the verification environment is
developed by using System Verilog. Constrained Random
cases cover the all possible combinations of data as well as
scenarios in a random manner, constrained for valid
combinations. In the Scoreboard, the link states in the DUT
will be compared with the reference model part created in
the scoreboard and it is verified that the actual link state and
the expected link state in the reference model obtained are
same.

VI .CONCLUSION
As the technology is being improved with respect to the
field of application used for, USB 3.0 is an important
communication protocol used for application such as audio
and video streaming. The Link layer has been successfully
designed. All LTSSM states such as SS.Disabled,
SS.Inactive, Rx.Detect, Polling,Compliance Mode, U0, U1,
U2, U3, Recovery, Loopback and Hot Reset transitions
occur based on the inputs such as LGOU1, LGOU2,
LGOU3, LFPS Handshake, Warm Reset, Error, Low
Impedance Rx_Termination, Idle, Timeout, Loop Back and

2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA)