Full Laptop Repair Guide

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Laptop Chip Level Repair Guide 2
Contents:
Chapter 1: The Introduction of Laptop Repair
1.1 The Level of Laptop Computer Maintenance/Repair ……………………..12
1.2 The Basic Knowledge You Must Know Before Starting to Repair Laptop.14
Chapter 2: Original & OEM Laptop Mainboard Part Numbers

2.1 Quanta …………………………………………………………………….17
2.2 Compal ……………………………………………………………………18
2.3 Wistron ……………………………………………………………………19
2.4 Inventec …………………………………………………………………...19
2.5 Pegatron …………………………………………………………………...20
2.6 Samsung …………………………………………………………………...21
2.7 Apple ………………………………………………………………………22
2.8 Other Manufacturers ……………………………………………………....22
Chapter 3: The Architecture of The Laptop Mainboard

3.1 The Architecture of Intel Double Bridges (GM/PM45 and below) .... .......25
3.2 The Architecture of Intel Single Bridge (above HM55)..............................26
3.3 The Architecture of AMD Double Bridges (RS780)...................................29
3.4 The Architecture of AMD Single Bridge (A70).......................................... 29
3.5 The Architecture of nVIDIA Double Bridges (C51M)................................30
3.6 The Architecture of nVIDIA Single Bridge (MCP67)................................ 30
Chapter 4: The Explanation of Nouns and Common Concepts of

Laptop Maintenance
4.1 Power Supply and Signal............................................................................. 35
4.2 High Level and Low Level...........................................................................37
4.3 Jump and Pulse.......................................................................................... ..37
4.4 The Clock Signal..........................................................................................38
http://www.XiuFix.com/laptop-chip-level-repair/
4.5 Reset Signal................................................................................................. 39

4.6 Power Good Signal.................................................................................... ..39
4.7 Open Signal (Start-up Signal) ……..............................................................40
4.8 Chip Select Signal.........................................................................................41
4.9 The Explanation of The Signal Name/Symbol for Laptop Mainboard
Manufactures………..………………………………………………………... 41
• 4.9.1 Wistron........................................................................................... 41
• 4.9.2 Quanta..............................................................................................43
• 4.9.3 Asus.................................................................................................45
• 4.9.4 Compal............................................................................................48
• 4.9.5 DELL...............................................................................................49
• 4.9.6 Apple...............................................................................................51
• 4.9.7 Inventec...........................................................................................52
• 4.9.8 ThinkPad (IBM)..............................................................................53
Chapter 5: The Basic Application Circuit of Electronic

Components
5.1 The Basic Application Circuit of Capacitor.................................................57
5.2 The Basic Application Circuit of The Resistance .......................................59
5.3 The Basic Application Circuit of The Diode................................................62
5.4 The Basic Application Circuit of Transistor.................................................66
5.5 The Basic Application Circuit of The Field-Effect Tube (MOSFET)......... 68
5.6 The Basic Application Circuit of The Gate Circuit......................................69
5.7 The Basic Application Circuit of The Comparator.......................................71
5.8 The Basic Application Circuit of The Converter..........................................72
5.9 The Basic Application Circuit of The Voltage Regulator............................73
Chapter 6: The Use of the Circuit Diagram and the Point Bitmap
(BoardView)
6.1 The Use of The Circuit Diagram..................................................................75
6.2 The Use of The Common Point Bitmap (BoardView Software) .................80
Chapter 7: Introduction of EC and BIOS…89

7.1 The Working Conditions and Functions of EC............................................91
7.2 The Functions and Working Conditions of BIOS........................................94
Chapter 8: The Basic Working Process of Laptop Computer

8.1 The general process of Laptop computer................................................... 101
8.1.1 Hard Starting Process and Intel Chipset Standard Timing......................102
8.1.2 The Soft Start Process..............................................................................107
8.2 About ACPI Specification..........................................................................111
8.2.1 ACPI Summarize.....................................................................................111
8.2.2 G (Global) State of ACPI.........................................................................112
8.2.3 D (Device) State of ACPI........................................................................112
8.2.4 S (Sleeping) State of ACPI......................................................................113
8.2.5 C State of ACPI.......................................................................................114
8.2.6 The Power and The Control Signal of ACPI...........................................115
8.3 Clock, PWRGD and The Reset Circuit......................................................116
8.3.1 The Clock Circuit.....................................................................................116
8.3.2 PWRGD and The Reset Circuit...............................................................122
Chapter 9: The Explanation of PWM Circuit

9.1 The Introduction of PWM Circuit..............................................................126
9.1.1 Introduction to PWM Working Principle ……………….......................126
9.1.2 The Meaning of Common English Abbreviation in PWM Circuit. ........130
9.1.3 The Boot-Strap Circuit ............................................................................130
9.1.4 Output Voltage Regulation Circuit .........................................................132
9.1.5 The Voltage Detection Circuit.................................................................132
9.1.6 The Current Detection Circuit.................................................................134
9.1.7 The Working Mode..................................................................................135
9.2 Analysis of The Standby Power Chip.........................................................137
9.2.1 Analysis of MAX8734A..........................................................................137
9.2.2 Analysis of TPS51125.............................................................................148
9.2.3 Analysis of RT8206A/RT8206B.............................................................155
9.3 Analysis of The Memory Power Supply Chip............................................162
9.3.1 Analysis of ISL88550A...........................................................................162
9.3.2 Analysis of RT8207.................................................................................168
9.4 Analysis of the Bridge/BUS Power Supply Chip.......................................172
9.4.1 Analysis of The Single PWM Controller RT8209...................................172
9.4.2 Analysis of The Dual PWM Controller TPS51124.................................175
9.5 Analysis of CPU Core Power Supply.........................................................178
9.51 The Features of CPU VCORE Power Supply..........................................178
9.5.2 Analysis of MAX8770.............................................................................180
9.5.3 Analysis of ISL6260................................................................................192
9.5.4 Analysis of Commonly Used Chip ISL95831 by HM65 Mainboard .....200
9.5.5 Analysis of Commonly Used Chip ISL6265 by AMD Platform ............215
Chapter 10: Analysis of Quanta OEM Laptop Mainboard Circuit

10.1 Analysis of Quanta CT6 RTC Circuit.......................................................225
10.2 Analysis of Quanta CT6 Protective Isolation Circuit...............................227
10.3 Analysis of Quanta CT6 Power-On Sequence Circuit.............................232
10.4 Analysis of Quanta ZQ5 (Acer as4733z) Protective Isolation Circuit….250
10.5 Analysis of Quanta AX1 Protective Isolation Circuit..............................255
Chapter 11: Analysis of Wistron OEM Laptop Mainboard

Circuit
11.1 Analysis of Wistron HBU16-1.2 Protective Isolation Circuit..................261
11.2 Analysis of Wistron HBU16-1.2 Standby Circuit....................................267
Chapter 12: Analysis of Compal OEM Laptop Mainboard Circuit

12.1 Analysis of Compal LA-5891P Protective Isolation and The Standby
Circuit...............................................................................................................274
12.2 Analysis of Compal LA-6631P Protective Isolation Circuit....................290
12.3 Analysis of Compal LA-6751P Protective Isolation Circuit....................295
Chapter 13: Analysis of Inventec OEM Laptop Mainboard

Circuit
13.1 Analysis of Inventec DosXX Dunkel 1.0 Protective Isolation Circuit.....300
13.2 Analysis of Inventec DosXX Dunkel 1.0 Standby Circuit.......................305
13.3 Analysis of Inventec Feature Circuit........................................................309
13.3.1 Analysis of OCP Circuit .......................................................................309
13.3.2 Analysis of Big OR GATE Circuit........................................................316
Chapter 14: Analysis of INTEL PCH Power on Sequence (i3/i5/i7)

14.1 About Intel ME and Intel AMT................................................................319
14.2 Analysis of Intel HM55 Series Chipset Timing Sequence.......................325
14.3 Analysis of The Chipset Timing Sequence Above Intel HM65
Series ……………………….…………………………………………….......328
Chapter 15: Analysis of ASUS K42JR (HM5x) Timing Sequence

15.1 The Standby State ....................................................................................333
15.2 Trigger......................................................................................................346
15.3 The Boot State..........................................................................................347
15.4 Clock, PG and Reset ................................................................................359
Chapter 16: Analysis of Apple A1286 (HM5x) Timing Sequence

16.1 G3 State....................................................................................................362
16.2 RTC Circuit.............................................................................................. 370
16.3 S5 State.....................................................................................................371
16.4 Trigger......................................................................................................378
16.5 S3 and S0 State........................................................................................ 379
16.6 The Clock, PG and The Reset.................................................................. 393
Chapter 17: Analysis of DELL N4110 (HM6x) Timing Sequence

17.1 G3 State.................................................................................................... 398
17.2 Trigger..................................................................................................... 408
17.3 The Standby and The Memory Power Supply of The Bridge..................408
17.4 S0 state......................................................................................................411
17.5 PG and The Clock.....................................................................................416
17.6 CPU Core Power Supply..........................................................................419
17.7 Reset..........................................................................................................424
17.8 The Graphic Card Power Supply..............................................................425
Chapter 18: Analysis of ThinkPad (IBM) T410 Timing Sequence

18.1 G3 State.....................................................................................................427
18.2 S5 State.....................................................................................................442
18.3 AMT..........................................................................................................451
18.4 Trigger......................................................................................................455
18.5 S3 and S0 State........................................................................................ 456
18.6 The Clock, PG and Reset......................................................................... 463
18.7 The Battery Charge Circuit.......................................................................468
Chapter 19: Analysis of AMD Platform Timing Sequence

19.1 The Standard Timing Sequence of nVIDIA.............................................478
19.2 The Explanation of nVIDIA Chipset Timing Sequence (MSI MS-
16352)……………………………………………………………………….. 481
19.3 The Standard Timing Sequence of AMD Chipset....................................501
19.4 The Timing Sequence of AMD Chipset (ACER 4235, Quanta ZQE)......503
19.5 The Explanation of AMD A70M (Lenovo G485, Compal LA-8681P)...506
19.5.1 RTC Circuit............................................................................................506
19.5.2 Protective Isolation Circuit....................................................................508
19.5.3 The Standby Power Supply................................................................... 512
19.5.4 The Trigger Switch............................................................................... 519
19.5.5 Produce Power Supply...........................................................................521
19.5.6 APU Power Supply................................................................................528
19.5.7 Clock, PG and Reset..............................................................................529
19.5.8 The Independent Graphics Working Timing Sequence.........................534
Chapter 20: Analysis of the Laptop Battery Charging Circuit

20.1 Analysis of Charging Chip MAX1772 Used Usually Under Intel 1965GM
Platform ……………………………………………………………………...542
20.1.1 The Name and The Definition of The Pin............................................ 543
20.1.2 Application Circuit............................................................................... 546
20.2 Analysis of The Charging Chip ISL88731 Used Usually by The Intel
GM45…………………………………………………...…………………… 549
20.2.1 The Name and The Pin Definition of ISL88731................................... 550
20.2.2 The Typical Application Diagram.........................................................553
Chapter 21: Maintenance of Common Failures

21.1 Short Trouble (Short Circuit Problem) ...................................................556
21.2 Do Not Trigger Fault................................................................................560
21.3 Power Down Fault................................................................................... 564
21.4 Not Running Fault (NO Error Code) ...................................................... 567
21.5 The Maintenance of Common Code........................................................ 574
21.6 The Screen Shows Fault...........................................................................581
21.7 The Sound Card Fault.............................................................................. 587
21.8 USB Fault................................................................................................ 591
21.9 The Network Card Fault...........................................................................592
21.10 SATA Interface Fault............................................................................. 595
21.11 The Fan Interface Fault...........................................................................597
21.12 Crash Fault..............................................................................................599
Chapter 22: Example of Maintenance (Laptop Repair Cases)

22.1 The example of maintenance about don't boot fault
Example 1 IBM T61 cannot boot.................................................................... 600
Example 2 Lenovo G480 inflow water, which cause cannot boot.................. 602
Example 3 lightning strike cause the Lenovo Z360 does not boot.................. 605
Example 4 IBM R60 no standby.................................. ................................... 610
Example 5 ASUS A42J with multiple fault..................................................... 615
Example 6 ASUS K42JR no standby...............................................................619
Example 7 Acer Aspire 4738G powered off....................................................620
Example 8 ASUS K42JR Powered off.............................................................622
Example 9 SONY NS90HS cannot boot after lightning strike........................ 624
Example 10 Lenovo Xuri 410M power off......................................................626
Example 11 DELL N4030 I3 not trigger......................................................... 628
Example 12 Toshiba L500 cannot boot........................................................... 631
Example 13 Samsung R23 cannot boot........................................................... 638
22.2 The example of the breakdown maintenance about not bright
Example 14 Lenovo G460 do not run code..................................................... 641
Example 15 DELL V130 no display after powering on.................................. 644
Example 16 Samsung R428 no display after powering on.............................. 645
Example 17 Inventec HP511 no display and powered down...........................648
Example 18 eMachines D725 inflow water, which cause no light...................651
Example 19 Lenovo G470 no CPU voltage..................................................... 654
Example 20 Lenovo Y430 no clock and no display ....................................... 656
Example 21 Acer 5750G starting up but not display....................................... 657
22.3 The fault maintenance examples of power down
Example 22 used the oscilloscope to repair the fault of power down of Lenovo
G450 ……………………………………………………………………..…..659
Example 23 Lenovo G550 the standby is abnormal and power down............ 661
Example 24 HP 4411S power down when enter into the system.................... 664
Example 25 Acer Aspire 4310 power down.................................................... 667
Example 26 Lenovo Zhao yang E43G power down after triggering............... 671
Example 27 HP 510 power down repeatedly and restart after starting up.......672
Example 28 Lenovo V450 power down when stating up................................ 674
Example 29 HP 4411 Power down repeatedly after starting up...................... 676
22.4 The maintenance examples of other faults
Example 30 ASUS A8E large short circuit when install battery..................... 678
Example 31 Lenovo s10.2 dark screen ........................................................... 682
BONUSES:
1) How to Clear ME Region (Intel Management Engine Fix
Tutorial).
2) Bypass Discrete Graphic Chip and change to UMA Graphic
type. System will more stable and save battery.
3) Laptop Mainboard BoardView Software and their Schematic
Diagrams.
Note:
The above Bonuses information was inside the Bonus Page not inside this
ebook. So you can download all these valuable information from Bonus Page
there.
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from this information. Most of the repair tips and solution given should only be
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Thank You for Contribution

Thank you very much to Mr. Kent Liew. Where he gave me this
opportunity to write this ebook and appreciate where he has helped me a
lot in this project.
Author of this ebook

Mr. Eric Huang (China)
Note: Some words meaning in this ebook

Tube = MOSFET or Transistor
Partial pressure = Divider
Triode= Transistor
Resistance= Resistor (some time is mean the resistance, too)
Motherboard = Mainboard
Plate number = Model number
Top tube = High-side of MOSFET
Low or down tube= Low-side of MOSFET
Light= Power on (some time also means screen got display)
Universal meter = Multimeter
Chapter 1
The Introduction of Laptop
Repair
The laptop computer also called as: Laptop, Notebook Computer, Portable, NB
and etc. Nowadays, the laptop computer repair business still maintain in the
market now. But the desktop computer repair market percentage is huge drop
when compare to laptop computer.
1.1: The Level of Laptop Computer

Maintenance/Repair
1) Application Level Laptop Maintenance
This level of laptop repair is more on the software and system OS installed. For
example:
 Install Operation System (OS)

 Install sound card, network card, Bluetooth, graphic card and etc
hardware drivers.
 Upgrade BIOS
 And etc.
2) Board Level Laptop Maintenance
This level of laptop repair is more on the swap board. For example:
 Replace CPU (Processor), including the CPU heat sink & fan.
 Replace Hard disk
 Replace Battery
 Upgrade/Replace RAM
 Replace Keyboard
 Replace Screen
 Replace WIFI card
 And etc.
In this level of laptop repair, the repairer must have the basic knowledge on
electronic. For example on how to use the multimeter to testing/measure voltage
& ohm values.
3) Components Level Laptop Maintenance
In this level of laptop repair, the repairer must know how to use the multimeter,
Oscilloscope, DC Regulated Power Supply, Soldering Workstation, BGA
machine and etc.
The repairer can repair laptop mainboard with replace the electronic
components to solve the laptop mainboard problem. For example electronic
components:
 Resistor, Capacitor, Transistor/MOSFET

 Inductor
 IC chip
 South & North Bridge
 Discrete Graphic BGA chip & etc.
4) Signal Level Laptop Mainboard Maintenance
Signals level laptop repair is an advance level of component level laptop repair.
This is a top level or laptop repair. You need to know the knowledge on the
above 1), 2) & and 3). For example, know how to read the schematic diagram,
for signal level laptop level repair, you must know how to measure and analysis
the signals of the mainboard. So the perfect laptop repair solution is:
Components Level + Signal Level repair!
1.2: The Basic Knowledge You Must Know

Before Starting to Repair Laptop
1) The basic electronic repair knowledge you must know:
a) The analogue and digital circuits.

b) What are the opened circuit, short circuit, leakage circuit and etc.
c) For the laptop repairer, you must know what’s the “signal” and “timing
sequence”.
I. Signal = When a laptop mainboard working, it will sends and

receives different data and commands to control the circuits. So the
signal is very important for a laptop mainboard to working
properly.
II. Timing Sequence = The meaning of Timing Sequence is as the

name of “Timing” and the “Sequence”. When a laptop mainboard
supply an AC to it, press power button until it start-up/opening
successfully to working. At the same time mainboard each circuit
will sends and receives the signals in between their correct timing
and sequence, to successfully start-up/open the mainboard and
ready to use by the user. The timing sequence is important, and
must need to follow. If one of the step missing or incorrect timing,
it will cause the mainboard not working. Even the markets have
many brands laptop, but all or most of them are just using the Intel
or AMD platform chipset only. So the same chipset is using the
same timing sequence to work. And then we can just learn these
two main chipset timing sequence, we can handle and repair the
laptop easily.
2) Know how to testing electronic components
As a laptop repairer, you must know what type of electronic component it is and
know how to testing an electronic component with using the proper tools &
equipment.
3) Know the structure of laptop
Need to know the structure of laptop before repair it. For example, how to
proper dismantle the laptop and the correct maintenance steps.
4) Know how to operation the testing equipment properly
Need to know the proper way on how to use the multimeter, soldering iron
(soldering workstation), diagnostic card, DC regulated power supply,
oscilloscope, BGA and etc. Also need to know how to avoid the electro-static
damage the laptop mainboard. So it will help the laptop repairer to increase their
successful rate in laptop repair.
Chapter 2
Original & OEM Laptop
Mainboard Part Numbers
All branded laptop computer like Acer, Dell, HP, Lenovo and etc, they are not
manufacture their laptop mainboard/motherboard. All of them are using the
third party company design laptop mainboard to build their own brand laptop
computer. This is because the branded computer company they want to earn
more money and cut the cost to build a laptop computer.
The entire third party laptop computer mainboard manufacturer called it as an

OEM company/manufacturer. What is the difference to OEM (Original
Equipment Manufacturer) and ODM (Original Design Manufacturer) company?
The OEM company is responsible to manufacture the product, but not include
the product design and research. But the ODM company is do all these thing, so
the branded computer company just put their brand name and model into this
laptop as their new model of laptop computer. For example the ODM product
manufacture by ECS G550 is using in different brands and models of laptop
computer like TCL610, ChangCheng E2000, FangZheng T5800D and etc.
We can say most of the laptop computer company is using the OEM and ODM
product to build their laptop computer now. All these OEM & ODM laptop
production company are from Taiwan and their manufacturer base is in China.
The popular OEM & ODM company like: Compal, QUANTA, Wistron,
Inventec and Pegatron. These OEM company have a huge market percentage on
production of laptop mainboard. The second line OEM manufacturer like:
MITAC, Clevo, FIC, MSI, ECS, Flextronics, Foxconn, Topstar and etc.
In the laptop maintenance, we can see different brands and models of laptop
computer send to repair. After dismantle the laptop and found it different brands
and models of laptop, but they also use the same laptop mainboard. So their
mainboard circuits, timing sequence and repairing steps also the same. We need
to know how to identify the laptop mainboard part number and their OEM
manufacturer by which company.
2.1: Quanta
QUANTA is one the top OEM laptop mainboard manufacturer. Their OEM
laptop mainboard is using by big laptop computer company like: Dell, HP,
Lenovo, Apple and etc.
The Quanta OEM laptop mainboard part number is starting from DA or DAO.
Their part number is DA or DAO and in between MB with 3 digits or 4 digits.
The Quanta mainboard p/n model CH3 is shown in figure 2-1. In this model of
laptop mainboard schematic diagram, you can find the “PROJECT: CH3” on
bottom right there, as shown in figure 2-2.
Figure 2-1: Quanta CH3 mainboard part number
Figure 2-2: Quanta CH3 mainboard schematic marking label
2.2: COMPAL
Compal is the second top of the OEM laptop mainboard manufacturer. Their
OEM laptop mainboard is using by big laptop computer company like: Dell, HP,
Lenovo, Toshiba and etc.
The Compal OEM laptop mainboard part number is starting from LA, for
example LA-4112, LA-3301P and etc. The part number starting from LS is a
small transfer board. The Compal LA-3301P laptop mainboard part number is
shown in figure 2-3. In the figure 2-3 mainboard schematic diagram, you can
find “LA-3301P” at the bottom right corner there, as shown in figure 2-4.
Figure 2-3: Compal LA-3301P mainboard part number
Figure 2-4: Compal LA-3301P schematic marking label
2.3: Wistron
Wistron is the predecessor of Acer DMS (Design, Manufacture & Service)
department. After 2001, it is independent from Acer company and become Acer
top 3 company. Their OEM laptop mainboard is using by big laptop computer
company like: Acer, Dell, HP, Lenovo and etc.
As shown in figure 2-5, the Wistron OEM laptop mainboard PCB part number
is starting from 05234, SHIBA is project name, 48.4F701.031 is project code.
The Wistron laptop mainboard need to match the above 3 things then it is call a
correct laptop mainboard.
Figure 2-5: Wistron SHIBA laptop mainboard
2.4: Inventec
Inventec was founded in year 1975. Their OEM laptop mainboard is using by
big laptop computer company like: Acer, Benq, HP, TCL, Toshiba and etc.
The Wistron OEM laptop mainboard PCB part number is starting from 6050A.
The Wistron laptop mainboard part number and schematic diagram model
number usually is not match. Need to use the manufacturer root file name to
find the correct part number and model number. Figure 2-6 is Inventec
6050A2030501 laptop mainboard and brand model is HP NX6325.
Figure 2-6: Inventec 6050A2030501Laptop Mainboard
2.5: Pegatron
Pegatron is the subsidiary company from ASUS since 2008. Their OEM laptop
mainboard is using by laptop computer company like: ASUS. Their laptop
mainboard have PCB logo as ASUS and PEGATRON.
As shown in figure 2-7 (a) is the PEGATRON H24Z laptop mainboard and
figure 2-7 (b) is the ASUS K43SV laptop mainboard.
Figure 2-7 (a)
Figure 2-7 (b): Pegatron & ASUS laptop mainboard models
2.6: Samsung
Samsung laptop mainboard is manufacture, design and research by Samsung.
The Samsung laptop mainboard PCB part number is starting from “BA41-”. For
example, the Samsung BA41-00478A laptop mainboard is shown in figure 2-8.
Figure 2-8: Samsung BA41-00478A laptop mainboard
2.7: Apple
Apple laptop computer mainboard their model number marking code is quite
small and hard to find it. The figure 2-9 is an Apple 820-2523-B laptop
mainboard model number.
Figure 2-9: Apple 820-2523-B laptop mainboard
2.8: Other Manufacturers

Introduce other OEM laptop mainboard manufacturers:
1) Micro-Star
The Micro-Star laptop mainboard PCB part number is starting from MS- xxxxx.
For example, the Micro-Star MS-6001 laptop mainboard is shown in figure 2-10.
Figure 2-10: Micro-Star MS-6001 laptop mainboard
2) Foxconn
The Foxconn laptop mainboard usually is using by big laptop computer
company like: Apple, SONY and etc. Their laptop mainboard PCB model/part
number is starting from MS. The figure 2-11 is MSS1 model laptop mainboard,
version 1.1. But this model laptop mainboard is OEM for SONY, so their PCB
can find the Sony model number: MBX-155.
Figure 2-11: Foxconn model MSS1 laptop mainboard
3) ECS
The figure 2-12 is the ECS G510 model laptop mainboard.
Figure 2-12: ECS model G510 laptop mainboard
4) MITAC
The MITAC laptop mainboard usually is using by big laptop computer
company like: Benq and etc. Their laptop mainboard PCB model/part number is
starting from 4-digits number is shown in figure 2-13.
Figure 2-13: Mitac 8640 and 8599 model laptop mainboard
5) CLEVO
The Clevo laptop mainboard usually is using by big laptop computer company
like: BuyNow and etc. Their laptop mainboard PCB model/part number is
starting from 1 character and follows by 3 numbers and last by 1 character. For
example: D400S, D410E, D900K, M720T, M540J and etc. The figure 2-14 is a
Clevo M55V0 model laptop mainboard.
Figure 2-14: Clevo M55V0 laptop mainboard
Chapter 3
The Architecture of the
Laptop Mainboard
Now the chipset used by the mainstream laptop on the market is only two
manufacturers. The Intel and AMD Intel is the absolute dominance. Once the
most popular nVlDlA has quit the chipset industry in 2010, on the market, the
notebook computer products with nVIDlA chipset are few.
3.1: The Architecture of Intel Double Bridges

(GM/PM45 and below)
The Intel Double Bridge architecture includes the 855-GM/PM45 chipset. In the
Intel Double Bridge architecture, their CPU & North Bridge both are connected
through the FSB (Front Side Bus) and the North Bridge also control the
memory, PCI-E 16X discrete graphics card and display output interface.
The North Bridge and South Bridge bus connected is called as HUBLINK
before. But it is renamed to DMI (Direct Media Interface) now and their
transmission speed increased much faster.
The South Bridge is control peripheral extension interface, mainly in the

following:
USB: Devices on the USB line are USB interface, camera, Bluetooth and etc.
Audio card: MODEM and the audio card are on the same line.
SATA: Hard Disk and CD/DVD-ROM.
IDE: (Early) Hard Disk and CD/DVD-ROM.
PCI-E device: Network card, Card Reader, Expansion card, Mini PCI-E slot &
etc.
EC (Embedded Controller): The name of lines connected to the South Bridge

is LPC (Low Pin Count: means one of the bus with a small number of
pin-out). The devices controlled by EC are Keyboard, Touch Pad, BIOS
& etc. (Some of the mainboard BIOS and EC may work by the same LPC
bus or connected the South Bridge directly via SPI bus).
The architecture of Intel GM45 is as shown in figure 3-1.
3.2: The Architecture of Intel Single Bridge

(above HM55)
After Intel 5 series chipset developmental, it becomes the bridge call PCH, and
that’s to say the North Bridge integrated into the CPU. In the architecture of
single bridge, CPU main control memory and PCI-E 16X discrete graphics card
and the integrated graphics is also integrated within CPU.
The bus that CPU and PCH Bridge connected to, are FDI (Flexible Display
Interface) and DMI bus.
PCH control USB, PCI-E IX SATA, audio card and other peripheral device.
The connection of PCH and EC is still using LPC bus devices under EC remain
unchanged. It was nothing that in the architecture of Intel single bridge.
Although CPU integrated the graphics card, but the display signal output is not
usually output by itself, and after transmitted to PCH through FDI bus, then
completed output by PCH. It’s different from the next AMD single architecture.
The architecture of Intel HM75 chipset is as shown in figure 3-2.
Figure 3-1: The architecture of Intel GM45
Figure 3-2: The architecture of Intel HM75 chipset
3.3: The Architecture of AMD Double Bridges

(RS780)
Because the AMD chipset uses AMD 638-pin CPU, so CPU can manage
memory directly. The North Bridge manages all PCI-E devices, its difference
from Intel double bridge, please remember. The North Bridge also integrated
the graphics card, and is responsible to output display signal.
The South Bridge manage audio card, USB, SATA, EC and etc, and the devices
under EC remain unchanged.
Here to mention, the BIOS has a variety of work bus, some work through X-
BUS under EC and some work through LPC bus connected in parallel with EC
and some work through SPI bus connected South Bridge independently. This is
not much associated with the architecture actually.
The architecture of AMD RS780 is as shown in figure 3-3.
3.4: The Architecture of AMD Single Bridge

(A70)
After AMD chipset A45 (mobile version is A50) development, it changed to the
single bridge called FCH. There are a lot of similarities with Intel single bridge.
The bridge and devices managed by EC are almost the same, so no longer
elaborated. The CPU of AMD also integrated the graphics card called APU. But
it can output the display signal directly and it’s difference with the architecture
of Intel single bridge.
The architecture of AMD A70 chipset is as shown in figure 3-4.
3.5: The Architecture of nVIDIA Double

Bridges (C51M)
nVIDIA is very famous for graphics card and chipset, but they didn’t product
PC chipset anymore. In the desktop computer, there are many single bridge
chipset and double bridge chipset, but in the laptop, there are using many
double bridge.
In the architecture of nVIDIA double bridge, CPU uses AMD 638 and it can
manage memory directly. The North Bridge is responsible to manage all PCI-E
devices and output the display signal on integrated graphics card. It is
accordance with AMD double bridge architecture. Devices managed by South
Bridge and EC are not big difference with AMD double bridge.
The architecture of nVIDIA C51M chipset is as shown in figure-3-5.
3.6: The Architecture of nVIDIA Single Bridge

(MCP67)
In the architecture of nVIDIA single bridge , their memory managed by CPU
and the other is managed by the Bridge, the large heat release of the bridge and
it is easy to weld.
The architecture of nVIDIA MCP67 chipset is as shown in figure 3-6.
Figure 3-3: The architecture of AMD RS780
Figure 3-4: The architecture of AMD A70 chipset
Figure 3-5: The architecture of nVIDIA C51M chipset
Figure 3-6: The architecture of nVIDIA MCP67 chipset
Chapter 4
The Common Concepts of
Laptop and Noun
Explanation
About laptop mainboard maintenance it is often involving some professional

terminologies of the circuit and signal. To understand the schematic circuit
diagram and learn to repair well we must understand these concepts first.
4.1: Power Supply and Signal

On the mainboard, some places have 5V voltage, we called 5V power supply.
And some places also have 5V voltage, we called signal, so what’s the
difference between them?
1. Power Supply
Power supply is an output current of the voltage and current is large. During
working, the voltage cannot be set higher or lower. If the power supply is low,
it’s short circuit. In general, set high is not allowed.
The power supply is providing the power to the devices, it’s marking name as:
VCC, VDD, VCC3, VDDQ, VTT, VBAT, 5VALW, +3VO or etc.
The circuit symbol of power supply is shown in figure 4-1.
Figure 4-1: The circuit symbol of power supply
In the circuit diagram of Apple products, the power supply us generally

beginning with PP and haven’t other special symbol as shown in 4-2
Figure 4-2: Apple product circuit symbol of power supply
The Grounding is to form a loop for power supply. Without grounding, it is no

current will flow through the devices. The marking names are VSS and GND.
The circuit symbol of grounding is shown in figure 4-3.
Figure 4-3: The circuit symbol of grounding
2. Signal
In theory, the voltage signal only considers the voltage change and current is
low. In the working process of the mainboard, it can be set higher or lower at
any time according to the needs. The arrow of signal in the circuit diagram
below is not representing the flow of signal completely. It is because of the
schematic diagram designer when drawing the circuit in unprofessional skill.
The circuit diagram of signal is shown in figure 4-4.
Figure 4-4: The circuit diagram of signal
4.2: High Level and Low Level

In the digital logic circuit, the low level is represented by “0”, and the high level
is represented by “1”. The high and low level in the circuit needs to be decided
by the circuit, not to be limited to a certain value. But in general, 0V is low level
and 3.3V is high level.
4.3: Jump and Pulse

From high level jump to a low level also called the falling edge, shown in figure
4-5.
Figure 4-5: The falling edge waveform
From low level jump to low then jump to high also called rising edge, as shown
in figure 4-6.
Figure 4-6: The rising edge waveform
From high jump to low then jump to high also called high-low-high pulse
waveform is as shown in figure 4-7.
Figure 4-7: The high-low-high pulse waveform
4.4: The Clock Signal

The clock signal CLK (CLOCK) is to provide a benchmark for the digital
circuit work, so that each connected device unified work pace. The basic unit of
the clock is Hz (Hertz). There is a main clock generating circuit on the
mainboard. The function of this circuit is to provide the clock for all devices on
the mainboard. For different devices, the clock circuit will send different
frequency, such as to the frequency of CPU is more than 100Mhz, to PCI device
is 33MHz, to PCI-E device is 100MHZ , to USB controller (integrated in the
South Bridge internal) is 48 Mhz. But the two connected devices must have the
same clock frequency and voltage to communicate. For example, memory and
North Bridge need the same clock and voltage to transmit signal normally. After
main board powering on normal and also the clock chip work normal, then the
clock signal can be measured correctly. We can use the oscilloscope or
multimeter to measure the clock signal.
The clock signal of clock chip benchmark- 14MHz is shown in figure 4-8.
Figure 4-8: The clock signal of clock chip benchmark- 14MHz
4.5: Reset Signal

The literal meaning of reset signal (RST) is a restart/new signal. When power
on laptop, it will reset automatically and jump from low level to high level;
during normal operation, press the reset button, it will from high level to jump
to the low level then back to high level. For example, for PCI, from 3.3V to
jump to 0V, after that to 3.3V, that’s mean it is a normal reset jump. Reset
signal is generally expressed as ***RST#, such as PCIRST#, CPURST#,
IDERST# and so on.
In short, the reset can only be momentary low level, but when the mainboard
works normally, the reset is high level. We said not reset usually refers to no
reset voltage, which is the measurement point voltage of the reset signal is 0V.
The 3.3V platform reset from the South Bridge, after dividing into 1.1V as the
CPU reset, shown in figure 4-9.
Figure 4-9: The circuit of the CPU reset
4.6: The Power Good Signal

The power good signal PG (POWERGOOD) is used to describe the normal
power supply is usually active high. For example, after sending the CPU voltage
normally, then the CPU power supply chip can send PG signal. The common
abbreviations of PG signal are PD, PWRGD, POK, PWRG, VTTPWRGD,
CPUPWRGD and so on.
For example the RT8205 chip, when it is working normally, then it will send
SPOK, is shown in figure 4-10.
Figure 4-10: PG signal diagram
4.7: Open Signal (or Start-up Signal)

Some chip called it as EN (Enable), the high level represents the open signal.
But some chip called SHDN#, namely SHUTDOWN, “#” represents active –
low level. It means that signal is closed when it’s low level. So to open it or
laptop mainboard power on, it must be high level.
We need to emphasize that we must be combined to full name in English of

signal to understand signal with “#” (when active-low level), some signal with
“#”, when it’s low level the mainboard can work normally. For example, signal
VR-PWRGD-CK410# in figure 4-11, sending the low level to open the clock
chip after power supply is normal.
But some signal with “#”, the mainboard working normally must be high. For
example 1999_SHDN# shown in figure 4-12 is the low level control signal for
closing MAX1999.
Figure 4-11:VR_PWRGD signal Figure 4-12: 1999_SHDN signal
Timing is through EN, PG and other signals to achieve control.
4.8: Chip Select Signal

CS is the Chip Select short form. When many of the chips on the same bus, then
it is need a signal to distinguish data and address on bus managed by which chip.
So we need a chip select signal to control it. Chip Select signal is common in
BIOS chip with symbol CS#, and “#” represents active-low level. It’s sent by
CPU, from the North Bridge to the South Bridge and finally reaches to the
BIOS. It exist or not, which can initially judge whether the North Bridge, South
Bridge and CPU to work or not. And also whether BIOS information is
destroyed SPI BIOS pin shown in figure 4-13 and pin-1 CS# is the BIOS chip
select signal.
Figure 4-13: SPI BIOS pins
4.9: The Explanation of Common Signal

Name/Symbol for Laptop Mainboard
Manufacturers
4.9.1 Wistron
Some of common signals names about Wistron Laptop Mainboard shown in
table 4-1.
Signal Names/Symbols Description

AD+ The first voltage that the power
adapter converts.
DCBATOUT Common point
+3VL 3.3V linear power supply, supply

voltage to EC.
DCIN Power supply input for charging chip.
ACIN Power adapter detection input for

charging chip.
ACAV-IN Power adapter detection output for

charging chip.
PWR-S5-EN A control signal used to open standby

voltage of South Bridge.
+5VALM, +3VALM The standby power supply of South

Bridge
AD_IN# , AC_IN# The power adapter detection signal to

EC, the low level represents that the
adapter is inserted.
KBC-PWR-BTN# Press the on/off switch to produce the

trigger signal to EC.
LID_CLOSE# Close cover switch
CLK_EN# After CPU power supply being

normal, send the low level that can be
used to open the clock.
G792-RST# The high level s4end by the

temperature control chip when the
temperature is normal.
CK-PWRGD After the South Bridge receiving

VRMPWRGD, sent this signal as high
level for opening the clock.
Table 4-1 The list of some common signal names/symbols about Wistron
4.9.2 Quanta
Some of common signals names/symbols about Quanta Mainboard shown in
table 4-2.

VIN The common point voltage
ACIN, ACOK Power Adapter detection
3V_AL, 5V_AL, VL 3V, 5V Linear power supply
+3VPCU, +5VPCU EC Standby power supply
3V_S5 The voltage under the condition of S5;

The South Bridge power supply;
Opened by EC after Trigger switch.
+3VSUS, +5VSUS The voltage under the condition of S3;

Memory power supply; Sent by EC
and opened by SUSON.
NBSWON# Trigger signal for power on; Press the

power on key to produce high-low-
high signal to EC.
DNBSWON# EC sent high-low-high effective

trigger signal to the South Bridge
PWRBTN#.
SLP_S3#, SLP_S4# ACPI controller signal sent by the

South Bridge is used to opening
voltage when the power is turned on,
and it also used to shutting off voltage
when the power is turned off.
S5_ON The opening signal of the South

Bridge standby voltage sent by EC; Its
use to convert the PCU to voltage S5.
SUSON After EC receiving SLP_S5# from the

South Bridge, then producing S3
voltage opening signal.
MAINON After EC receiving SLP_S3# from the

South Bridge, after that producing S3
voltage opening signal.
VR_ON The CPU core voltage opening signal

sent by EC.
HWPG By the PG Logic and all power supply

except the CPU core power supply.
PWROK_EC After EC received high level HWPG

signal, delay producing the
PWROK_EC signal.
DELAY_VR_PWG CPU core voltage power-good signal.
VR-PWRGD-CK410# CPU core voltage power managed the

clock open signal from chip; Active
low level.
CK_PWRGD The South Bridge sent CL-PWRGD
open clock chip after receiving
VRMPWRGD.
CPUPWRGD In the South Bridge internal, PWROK

pin and VRMPWRGD pin signal
through the logic generated
CPUPWRGD.
PLTRST# The platform reset signal; After the

South Bridge sending CPUPWRGD
signal, through the delay buffer sent
PLTRST#.
PCIRST# The PCI reset; Used for resetting the

device on the PCI bus when powered
on; Making the device work from an
initial state.
CPURST# CPU reset signal; The North Bridge

sent CPURST# to CPU after received
PLTRST#.
BL/C# Represents high level, low battery

(only for battery mode).
D/C# Inverse relationship with ACIN (Just

for mainboard with D/C# signal, where
the mainboard is without BL/C#
signal).
Table 4-2 The List of some common signal names/symbols about Quanta
Mainboard
4.9.3 ASUS
Some of common signals names/symbols ASUS Laptop Mainboard shown in
table 4-3.

AC_BAT_SYS The common point voltage
ACIN Power adapter detection
+5VAO 5V linear voltage
+3VAO 3V linear voltage
+5VA +5VAO renamed to +5VA after

jumper.
+3VA +3VAO renamed to +3VA after

jumper JP8101.
+3VA_EC +3VA renamed to +3VA_EC after

through the inductance; As the EC
standby power supply.
+5VO 5V standby voltage in S5dormant

state.
+3VO 3V standby voltage in S5dormant

state.
+5VSUS +5VO renamed to +5VSUS after

jumper.
+3VSUS +3VO renamed to +3VSUS after

jumper.
VSUS_ON SUS voltage open signal.
SUS_PWRGD SUS voltage power-good signal; Send

to EC.
PM_RSMRST# The reset signal of the South Bridge

ACPI controller; Can be understood
that the South Bridge standby voltage
is normal when received this signal.
PWRSW_EC# Laptop boot-up trigger signal.
PM_PWRBTN# After receiving PWRSW_EC, EC sent

PM_PWRBTN# effective trigger to
the South Bridge PWRBTN# pin.
SUSC_ON, SUSC_PWR S3 voltage open signal.
SUSB_ON, SUSB#_PWR S0 voltage open signal.
ALL_SYSTEM_PWRGD Generated by memory power supply,

Bridge power supply, bus power
supply, graphics card power supply
and PG signal logic.
CPU_VRON EC delayed 99ms to send VR_ON

after sending SUSB_ON; For opening
CPU core voltage.
EC_CLK_EN EC sent VRMPWRGD to the South

Bridge pin to inform the South Bridge
that CPU core voltage is normal.
CLK_PWRGD The South Bridge generated

CLK_PWRGD to IC clock after
receiving VRMPWRGD; For opening
the clock signal.
PM_PWROK After receiving

ALL_SYSTEM_PWRGD, EC delayed
sending PW_PWROK.
H_CPURST# The North Bridge sent H_CPURST#

to CPU after receiving PLTRST#
signal.
GATE_PWR_SW# The booth trigger signal.
LID_SW# Close-lid sleep switch signal; When

the machine is closed, this signal is
low level.
LID_KBC# The close-lid sleep switch detection

signal for EC.
KBCRSM The keyboard wake-up signal.
FORCE_OFF# The forced shutdown signal;

Generated by the under voltage
protection circuit.
HW_PROTECT# CPU over temperature protection

signal.
OTP_RESET# CPU over temperature indication

signal.
Table 4-3 The List of some common signal names/symbols about ASUS Laptop
Mainboard
4.9.4 Compal
Some of common signal names about Compal shown in table 4-4.

B+ Common point voltage.
PACIN The detection output signal is inserted

to the adapter; The high level
represents that the adapter is inserted.
VL 5V linear power supply.
+3VALW, +5VALW Inserting the adapter, that is the

opened voltage.
ON/OFFBTN# Press power on key signal.
ON/OFF# The trigger signal sent by boot trigger

circuit to EC.
PBTNOUT# The boot trigger signal sent by EC to

the South Bridge.
SYSON S3 voltage open signal.
SUSP# S0 voltage open signal.
+VCCP The working voltage of CPU front side

bus; This voltage distributes in CPU,
the North Bridge, and the South
Bridge.
+CPU_CORE CPU core voltage.
VGATE CPU core voltage power-good signal.
ICH_POK PWROS for the South Bridge; Inform

the South Bridge system voltage
power good.
BCLK The front side bus clock signal.
SUS_STAT# Sent by the South Bridge; The low

level indicates that the system will be
in power-down (save power) mode.
Table 4-4 The list of some common signal names/symbols about Compal
4.9.5 DELL
Some of common signal names about Dell shown in table 4-5.

RTC_CELL The mainboard button battery voltage.
+DC_IN Power Adapter voltage input.
+PWR_SRC The common point voltage.
ALWON EC sent a ALWON signal to the

system power supply chip to
open/start-up the system power supply.
THERM_STP# Overheat protection signal; Active-low

level.
ACAV_IN The Power Adapter detection signal.
POWER_SW# A low voltage signal generated by the

power switch or keyboard and EC chip
receives this boot signal.
SUS_ON After receiving the trigger signal, EC

sent SUS_ON to use to open the South
Bridge standby power supply and
memory main power supply.
RUN_ON EC sent open S0 state voltage.
GFX_ON Open discrete graphics card power
supply.
_VCC_GFX_CORE The discrete graphic card core power

supply.
+0.9V_DDR_VTTP Memory VTT power supply.
RUNPWROK The PGD signal of all RUN power

convergence to this signal.
SUSPWROK The reset signal of all SUS power

brings together to generate the
SUSPWROK signal.
+VCCP_1P05VP The front side bus power supply:

1.05V.
PGD_IN One of the conditions of that CPU

power supply chip sent CLK_EN#,
PGOOD and others.
CLK_ENABLE# The open signal of clock chip: Active-

low level.
H_PWRGOOD PGD reset signal sent by the South

Bridge to CPU.
H_RESET# The North Bridge sent CPU reset

signal.
+VCHGR Charging output voltage.
+SBATT Auxiliary/Sub battery power supply

terminal.
+PBATT Main battery power supply terminal.
SBAT_PRES# Detection of insert the auxiliary

battery.
PBAT_PRES# Detection of insert main battery.
IMVP_VR_ON Open CPU power supply.
IMVP_PWRGD Power supply good signal sent by CPU

power supply chip.
Table 4-5 The list of some common signal names/symbols about Dell
4.9.6 Apple
Some of common signal names about Apple shown in table 4-6.

=PP3V42_G3H_REG 3.42V power supply in the condition
of G3 equivalent to the linear power
supply of other machine.
=PP3V3_S5_REG 3.3V power supply in the condition of

S5 provided the standby voltage to the
South Bridge and others.
PP3V3_G3_SB_RTC 3.3V power supply of the South

Bridge RTC circuit.
=PPBUSA_G3H Common point voltage.
PM_BATLOW_L The indicator signal of low battery

voltage; Active-low level.
1V8S3_RUNSS S3 state voltage (memory supply) of

1.8V open signal.
ALL_SYS_PWRGD Convergence from all power supply

good signal except CPU power supply.
VR_PWRGOOD_DELAY The power good signal sent by CPU

power supply after generating CPU
voltage normally and it will delay to
send the power-good.
VR_PWRGD_CK505_L The lower level signal of open clock;

After CPU power supply chip
generating CPU voltage normally, it
will send the low level signal to open
clock.
SMC_BC_ACOK The Adapter detection signal; Active –

high level.
SMC_ADAPTER_EN The high-level signal output by SMC

after receiving the adapter detection
signal.
SMC_BATT_CHG_EN The charging enable signal sent by

SMC; Active-high level.
ACPRN Low level ACPRN signal sent by

charging chip after the adapter is
detected.
ONEWIRE_EN ONEWIRE enable signal; For the

adapter to identify circuit (the power
connector LED green light).
Table 4-6 The list of some common signal names/symbols about Apple
4.9.7 Inventec
Some of common signal names about Inventec shown in table 4-7.

+VADP Power adapter voltage.
ADP_EN# Power adapter enable signal; Active

low level.
ADP_PRES Adapter detection output voltage; It
can be use to open the system power

supply directly.
+VBATR Common point voltage.
+3VAL, +5VAL Linear power supply.
PWR_SWIN_3# The signal sent by trigger switch to EC

chip.
KBC_PW_ON The power signal; It is sent by EC after

EC receiving trigger switch; It is use to
open the system standby power supply
under the battery mode (backup
battery).
VCCI_POR#3 The initial reset signal of EC.
+V3A, +V5A Power supply of standby system.
LIMIT_SIGNAL The power adapter connector

intermediate pin; Power identification
signal.
OCP Over-current protection.
Table 4-7 The list of some common signal names/symbols about Inventec
4.9.8 ThinkPad (IBM)

Some of common signal names about ThinkPad (IBM) show in table 4-8.

DOCK_PWR20_F The power adapter voltage.
CV20 The voltage between adapter and

common point.
VINT20 The common point.
DISCHARGE Forced to close adapter; Battery

discharge signal.
-PWRSHUTDOWN Over-Temperature and Under-voltage

protection signal; Use to isolate the
adapter.
VCC3SW 3.3V voltage; Output by TB chip; Pull-

up –PWRSHUTDOWN; To supply
power to the Lenovo chip.
-EXTPWR The adapter detection signal; Output

by charging chip; Active low level.
-EXTPWR_ASIC The adapter detection input signal of

the Lenovo chip.
-EXTPWR_H8 The adapter detection input signal of

H8S.
VL5 The 5V linear voltage; Generated by

the standby chip.
DCIN_DRV The spacer tube use to control the

adapter; Fully turn-on the adapter
spacer tube at high level.
BAT_DRV The spacer tube uses to control the

battery; Isolated the battery in a low
level. Turn-on the battery at high level.
M1_ON The high level signal of standby

voltage sent by Lenovo chip for
opening the South Bridge.
VCC5M 5V standby voltage of the South

Bridge.
VCC3M 3.3V standby voltage of the South

Bridge; It is also the power supply of
H8S.
TH_DET Multiple Thermistors connected in

series; Detect temperature; When the
temperature is normal, this pin is lower
than 0.5V.
ACDET The adapter of the charging chip

detects input pin.
SWPWRG The standby voltage power good

signal of the Lenovo chip.
VREGIN20 The voltage with a small current

generated after the adapter or battery
accessing to or connected; The power
supply of TB chip.
BAT_VOLT VREGIN20 voltage detection pin; The

threshold voltage is 2.9V.
MPWRG After TB chip detected VCC3M,

VCC5M voltages are normal, sent the
PG signal to South Bridge RSMRST#.
-H8-RESET The reset signal sent by Lenovo chip

to H8S.
VDD15 After TB chip detects M voltage is

normal, bootstrap boost 15V; To
provide power to xx_DRV of TB chip
output.
VCPIN28 After TB chip detects M voltage is

normal, bootstrap boost 28V (is 25V in
fact); Use to driving and protecting the
isolating circuit with N-channel FET.
A_ON A voltage is turned on (S3 voltage,

such as memory power supply).
B_ON B voltage is turned on (S0 voltage,
such as the bus power supply).
B_DRV B voltage drive signal; Sent by TB

chip.
BPWRG Power-good signal; Sent by TB chip

after detecting VCC3B, CVCC5B
normal.
AMT_ON ME module voltage is turned on.
SLP_M# Sent by the South Bridge; Use to

control the opening of AMT power
supply.
AMTPWRG AMT power-good.
-PWRSWITCH, -PWRSW Power switch signal.
BATMON_EN Battery voltage monitoring enable.
M_BATVOLT Main battery voltage feedback.
M1_DRV, M2_DRV Main battery charging and discharging

driving signal.
BAT_CRG Battery large current charge control

switch.
CHARGE_OUT12 12.6V charging voltage control output

by charging chip.
M_TRCL The main battery trickle charging

control switch.
S_TRCL The auxiliary/sub battery trickle

charging control switch.
Table 4-8 The list of some common signal names/symbols about ThinkPad
(IBM)
Chapter 5
The Basic Application
Circuit of Electronic
Components
Electronic components of laptop are resistors, capacitors, diodes, transistors,

field-effect-transistors, gate circuit, comparator, voltage regulator and so on.
They are the most changeful when use in the circuit. For the people who have
just touched with laptop repair, it’s quite difficult to understand a basic
electronic circuit. It makes the circuit-based become a stumbling block for
maintenance people. This chapter mainly introduces the basic application of the
electronic components in the circuit, and does not include the understanding and
measurement of components. If the reader is not familiar with the understanding
and measurement of components, can refer to the relevant basic book, there are
many of such books on the market.
5.1: The Basic Application Circuit of Capacitor
l. Filter capacitor
Filter capacitor used in the power rectifier circuit and used to filter out the AC
components. It requires that larger capacitance adopts the high-capacity
tantalum capacitor, and smaller capacitance adopts SMD capacitor. PC9 (K
PC89x PC93 in figure 5-1 are 330uF tantalum capacitor.
Figure 5-1: Filter Capacitor
2. Coupling capacitor
Coupling capacitor usually adopts chip capacitor, used on the signal line of PCI-
E and SATA, the feature is in series in the signal circuit, the role is used to
isolate DC and ensure the transmission of high-speed signals. As shown in
figure 5-2, four parallel capacitors are the coupling capacitor, and both ends are
thin lines.
3. Resonant capacitor
Resonant capacitor is only used in the crystal oscillator circuit, the general
capacitance is tens of pF, and respectively connected between two pins of the
crystal oscillator and ground, the parameters of the resonant capacitor will affect
the resonance frequency and the output amplitude of the crystal oscillator.
Resonant capacitor adopts chip capacitor, as shown in figure 5-3. C180 and
C181 are the resonant capacitor.
Figure 5-2: Coupling Capacitor
Figure 5-3: Resonant Capacitor
5.2: The Basic Application Circuit of Resistor

The application of resistance in the board circuit is mainly pull-up resistance,
pull- down resistance, protective resistance and thermal resistance.
l. The pull-down and Pull Up resistance

In general, the resistance connected the voltage is the pull-up resistance (in
figure 5-4) and the resistance connected the grounding is the pull-down
resistance (in figure 5-5).Pull-up is to clamp uncertain signal at a high level
through a resistance, the resistance works current-limited effect at the same time.
And pull-down is in the same way.
Figure 5-4: Pull-up resistance Figure 5-5: Pull-down resistance
The application of pull-up and pull-down resistance shown in figure 5-6: When
R206 is installed and R205 is not installed, the INTVRMEN is high level, open
the internal voltage regulator of ICH7 (the default value); when R205 is
installed, R206 is not installed, INTVRMEN is low level, close the internal
voltage regulator of ICH7.
Figure 5-6: Pull-up and pull-down resistance
The voltage division circuit: Both the existence of the pull-up, and the existence of the
pull-down, that constitutes a voltage division circuit, as shown in figure 5-7. The
formula of series partial pressure is:
VA=VTotal/(R1+R2)*R2
RC delay circuit (shown in figure 5-8):+VCC_RTC charge C1704 first through R

1701, the RTCRST# voltage will slowly raise, and the time required that it rises to
equal with +VCC_RTC voltage is the delayed time. A simple calculation of the
delayed time can be used R*C, such as 20KΩ * l uF= 20ms.
Figure 5-7: The voltage division circuit Figure 5-8: RC delay circuit
2. Protective resistance
Figure 5-9: Protective resistance picture
The protective resistance plays the role in protective effect. When the circuit
load becomes large, beyond the range of resistance can afford, resistance will be
open circuit make the corresponding circuit to stop working and as to achieve
the purpose of protecting the components. The resistance of protective resistor
is generally below 10Ω. In the figure 5- 9, R243 is the protective resistor.
3. Thermal resistance
The thermal resistance is divided into two: “The higher the temperature, the
lower the resistance" (NTC, the negative temperature coefficient) and "The
higher the temperature, the higher the resistance" (PTC, the positive temperature
coefficient). The thermal resistance shown in figure 5-10, but we cannot
distinguish NTC or PTC from the physical.
Figure 5-10: The thermal resistance
5.3: The Basic Application Circuit of The Diode

The forward voltage drop of the common silicon is 0.7V and the germanium
diode is 0.3V. In the figure 5-11, the positive electrode is on the left. The
negative electrode is on the right, 3.3V input from the left, if it has, a silicon
tube 2.6V will be output from the right.
Figure 5-11: Diode
l. OR Gate application of diode (shown in figure 5-12)

Power failure with 3V BAT power supply, after plugging with 5VALW power
supply, in order to save battery power, can ensure that VCCRTC always have
electricity. Such diodes are generally composite diodes, the material object
shown in figure 5-13.
Figure 5-12: OR gate application of Diode
Figure 5-13: Composite Diode Physical Map
2. AND Gate application of diode(shown in figure 5-14)
As long as any signal at the left end of the diode has low level, diode will
conduct, pull HWPG low.
Figure 5-14: AND gate application of diode
3. Clamping applications of diode (shown in figure 5-15)
Figure 5-15: Clamping of application diode
(l) VIN voltage (assumed to be 18.5V) after resistance PR29, PR28 series
partial pressure, the Voltage after partial pressure is 7.6V.
(2) Now the positive electrode voltage of PD9 is 7.6V, the negative electrode
voltage is 3.3V, so the positive electrode is greater than the negative electrode,
and over the conduction voltage drop 0.7V.
Figure 5-16: Anti-Static clamping diode
(3) PD9 conduction, the diode cathode is only higher than the negative electrode
0.7V after conducting, so the A point voltage is clamped to about 4V. Clamping
diodes are generally next to the USB interface or VGA interface, used to
prevent static electricity, shown in figure 5-16.
4. Voltage stabilizing diode

When the diode reverse voltage to a certain value, the reverse current will
suddenly increase, which is called the breakdown phenomenon. In the state of
breakdown, the current through the tube changes a lot and the voltage of both
ends of the tube is almost constantly using this feature; it can achieve voltage
regulation, which is called the voltage stabilizing diode. In the figure 5-17,
U9000 is 2.5V voltage stabilizing diode, when the negative voltage applied is
more than the regulated value, then the reverse breakdown current will appear,
so the voltage of both ends can be fixed. R9000 is the limit current resistance,
and the reverse breakdown current of the voltage stabilizing diode in between
5mA~ 40mA.
Figure 5-17: Voltage Stabilizing Diode
In the figure 5-18, PD12 is 5.1V voltage stabilizing diode, when VS is 19V,
applied to the negative, can be broken down, the voltage reaching the positive is
remaining 13.9V, and after the partial pressure of PR87 and PR90 to send chip 6
pin SHDN# as open, the purpose is to limit VS minimum voltage. Only VS
exceeds a certain value, the partial pressure after the reverse breakdown can
meet the rising edge threshold value of SHDN#.
Figure 5-18: Example of the Stabilizing Diode
5.4: The Basic Application Circuit of Transistor

In the laptop circuit, the main application of the transistor is switching action: E
pole of NPN transistor connects ground: when B pole input high level, C pole is
low level; when B pole input low level. C pole is high level. Specific content as
follows:
Common NPN type: when VB> VE 0.7V, B-E is conducted, and C-E is also
conducted.
Common PNP type: when VB<VE 0.7V, E-B is conducted, and E-C is also
conducted.
In the figure 5-19, when a point is high level 0.7V or more applied to B pole of
transistor via resistance, then the transistor C-E will be conducted, and Y output
low level.
In the figure 5-20, PQ41 is the digital NPN transistor with inner zone resistance,
ifs same as the common transistor, also has the feature of high level conduction
and low level cut- off. However, the voltage of B pole must be greater than the
voltage of E voltage for a certain value. About this value, you need to check the
relevant data sheet. According to the manual, the conduction voltage is:
VI (on) =1.9V, as shown in figure 5-21.
Figure 5-19: The application of common transistor
Figure 5-20: The application of the digital transistor

Figure 5-22, is the application of transistor switching action: only when +VLDT
voltage is greater than 0.7V, added to the B pole of PQ26, making it to be
conduction; pull the B pole of PQ25 low, PQ25 is cut-off; +3VRUN pull
VLDT-PG up directly, generating high level to send to rear pole.
Figure 5-21: The screenshot of DTC144EUA data manual
Figure 5-22: The application of the transistor switching action
5.5: The Basic Application Circuit of Field-

Effect Tube (MOSFET)
The switching application of the field-effect tube shown in figure 5-23 .When
S5-ON is high level (above 2V), PQ68 is conducted, Y is pulled to the ground;
when S5-ON is low level, PQ68 is cut-off, Y is pulled on 5V by 5VPCU.
Figure 5-23: The switching of the Field-Effect-Transistor (Tube)
In the figure 5-24,when SUSON is high level,PQ70 is conducted, pull down the
G pole of PQ73, PQ73 is cut-off; +15V pull SUSD up on 15V, to send to the G
pole of PQ56and PQ76;PQ56 and PQ76 can be conducted completely,
generating 3VSUS, 5VSUS(the condition of N channel MOS full conduction:
VG>VS 4.5V or more).
Figure 5-24: Example of application of field-effect-tube
5.6: The Basic Application Circuit of Gate

Circuit
l. NOT gate
In the figure 5-25,U27 is the NOT gate: when DGPU_SELECT# is high
level,U27 outputs a low level of IGPU_SELECT#;when DGPU_SELECT#
inputs level, IGPU_SELECT outputs high level.
Figure 5-25: The application of the NOT gate
2. AND gate
The application of the AND gate shown in figure 5-26: only when EC_PWROK
and IMVP_PWRGD are high level then U25 can output high level of
SYS_PWROK.
Figure 5-26: The application of the AND gate
3. Three-state gate
The application of the three-state gate shown in figure 5-27:only when OE is

low level, the output level is consistent with the input level(equal to the
follower);when OE is high level, no matter what state the input is, the output is
always keep high impedance state. But in the figure 5-27, OE has been forced to
ground, so it's no difference between this circuit and follower in the level logic.
Figure 5-27: The application of the three-state gate
5.7: The Basic Application Circuit of

Comparator
Basic application of comparator shown in figure 5-28, the 3V battery is added to
the inverting input of the comparator, compared with the voltage of VIN partial
pressure. When VIN is greater than 15.67V,the voltage of partial pressure will
be higher than 3V,the comparator open drain output (7 pin and PU48
comparator internal are disconnect),RSMVCC3 pulls up ACIN to be high level
to the chip; when VIN is less than 15. 67V, the comparator will output low level
(7 pin and 4 pin internal are short circuit), ACIN is pulled to the ground.
Figure 5-28: The application of the comparator
CPU overheating protection circuit shown in figure 5-29.The comparator 6 pin

is divided into 2.5V by +5VALM.At the room temperature, the resistance of
PHI is l0k +SVS partial pressure through PHI and PR 161, applied to the
comparator 5 feet, will be less than 2.5V of comparator 6 pin. The comparator
output low level. Make PQ39 cut-off. MAINPWON is not pulled down, at the
same time, because the comparator output low level, leading to PR167PR 163
series, and form series with PR 161, so that the 2 pin voltage of PHI is pulled
down again.
Figure 5-29: The comparator in a temperature control circuit

When the temperature of PHI increases, the resistance is reduced to less than
2.55k^, the voltage of the comparator Spin achieved will be higher than 2.5V of
6 pin, the comparator outputs 5V high level, make PQ39 conduct, pull down
MAINPWON, the system power supply is shut down; at the same time, the high
level comparator output, making PR167s PR163 and PHI be series, thus pull up
the 2 pin voltage of PHI again. This PR167 is the hysteresis resistance, the
author called it as "fence resistance". The role is to make the CPU temperature
protection value not stay at a point, such as 90 degrees over temperature
protection, 50 degrees to return to normal.
5.8: The Basic Application Circuit of The

Converter
Multiplexer (MUX) is used in the second generation dual graphics switching
circuits is the control signal, when S is low, Bo connects A, when S is high, Bi
connects A, as shown in figure 5-30.
Figure 5-30: The definition of converter chip
5.9: The Basic Application of The Voltage

Regulator
As shown in figure 5-31, U8100 is low dropout regulator (LDO), which input
power supply from 1 pin, output voltage from 5 pin, two resistances connected
by 4 pin control high-low of the output voltage, the reference voltage is 1.24V.
3 pin is the open signal of chip, high level opens output and low level stops
output. The calculation formula of output voltage is:
VOUT =VFB x ( l+R8114/R8104 )
Figure 5-31: The voltage regulator
The voltage regulator in figure 5-32 is common in the memory VTT power
supply,+3VALW is the control voltage of chip, VIN is the input voltage,
REFEN is partial pressure of+1.5V to 0.75V,the conditions are satisfied, the
chip output +0.75VSP from 4 pin. This chip is mainly used for the current
amplification, can provide 1.5A current.
Figure 5-32: Common voltage regulator in memory VTT power supply
There is also a commonly used voltage regulator 431L, as shown in figure 5-

33,is the 1.24V precision voltage regulator:+3VPCU current limiting through
R139,and stable output reference voltage of 1.24V through 431 L(C and R
connected together, as a voltage regulator diode).
Figure 5-33: Precision voltage regulator 431L
Chapter 6
The Use of the Circuit
Diagram and the Point
Bitmap (BoardView)
The circuit diagram reflects the structure and working principle of the electronic
circuit directly, so it is generally used in the design and analysis of the circuit.
The electronic file format of laptop motherboard circuit diagram is *.PDF, a
circuit diagram usually have dozens of pages to hundreds of pages, their ligature
is horizontal and cross, and varied in form, beginners often do not know from
where to start and how to read it. Understanding the motherboard diagram
circuit is a threshold for maintenance personnel to further improve. We must
have a certain basic knowledge. In addition, because the component on the
laptop motherboard is too dense, even understand the principle in the circuit
diagram; it is also quite difficult to find the damaged components in the real
object. Some manufacturers did not even print components position number,
which requires maintenance personnel must know how to use the point position
diagram, in order to identify the location of components quickly and accurately.
6.1: The Use of the Circuit Diagram

The file format of laptop circuit diagram is *.pdf. We can use Adobe Reader or
Foxit software to open this file. When you open a drawing, in general, the first
page is a schema or directory, as shown in figure 6-1.
Figure 6-1: Architecture diagram
The figure marked the page where each function module, for example, CPU
occupies page 4 and page 5.If you want to view the page with CPU, you can
input the page number in the following page frame as shown in figure 6-2.
Figure 6-2: Page input box
In the figure 6-3, CLK_CPU and CLK_CPU_BCLK through the resistance, no

longer regarded as the same signal, but to be regarded as two signals.
Figure 6-3: screenshot of the clock signal
The pin name of components and the signal named by manufacturer cannot be
considered the same concept, as shown in figure 6-4, PLTRST# is the pin name
of C26 pin, but PLT_RST# is the signal named by manufacturer. Check where
the signal connected to, you should find the PLT_RST#. Figure 6-5 is the test
point T83 for factory testing use.
Figure 6-4: PLT_RST# signal diagram
Figure 6-5: Circuit symbol diagram of the test point

Jumper point/isolation point usually connected with tin directly, convenient to
the troubleshooting, the circuit symbol shown in figure 6-6.
Figure 6-6 circuit symbol diagram of the isolation point
Figure 6-7: is the physical map of the isolation point
* or @ is printed on the device, indicating that the device is not installed in the
board of the current version. NO STUFF also indicates that there is no
installation. Not installed, it represents that both ends are disconnected, as
shown in table 6-1:
Table 6-1: The list of some parts of the mainboard is not installed
If the parts are not installed, but cannot be disconnected, then add the "short"
words, or connected with a straight line, as show in figure 6-8.
Figure 6-8 circuit diagram of parts direct connection
The signal back with "#' "-L" or the front with "-", etc., indicates that the signal
is active- low level. The word of "efficient" needs to be considered carefully,
and need to combine with the English front of "#" to understand. As shown in
figure 6-9, in fact. PERST# and 2231_SHDN# signals are high level in the boot
state, but did not conflict with the expression of "active-low level".
Figure 6-9: Active-low level signal circuit diagram
In the common drawings, the digital followed by signal, indicates the page the
signal connected to, but in the product drawing of IBM and Apple, as shown in
figure 6- 10,75D3 and others indicate the place that the signal connected to page
75 coordinate position D-3,positioning is more accurate, it¡®s convenient to
find signal.
Figure 6-10: Screenshot of Apple product circuit
In addition, the direction of the arrow represents the trend of the signal, as
shown in figure 6-1 but due to the randomness of drawing staff, leading to not
believe all.
Figure 6-11: Screenshot of the signal
When the line is crossed, only the point indicates that the line is connected
together is as shown in figure 6-12.
In the figure 6-13, the signal is the same kind of signal line, will be drawn
together, to another page, then separate, not to say that these signal lines are
connected actually.
Figure 6-12: The circuit diagram of cross connected and disconnected
Figure 6-13: The similar signal circuit diagram
6.2: The Use of Common Point Bitmap

(BoardView Software)
l. CASTW----*.1st
CASTW is the point position figure used by IBM, the most outstanding
characteristics of this point position figure is that we can see the actual direction
of signal. The red indicates that the signal is in the current layer, and the yellow
indicates that the signal is in the other layer. Here "the other layer" refers to the
other side of PCB and also refers to the middle layer of PCB. Here is the
common use operations and shortcut menu shown in figure 6-14.
Figure 6-14: The screenshot of IBM BoardView software (point position figure)
2. Test Link------*.brd
The point position figure of Landrex corresponds to the file format of BRD.
Common operations are as below: click C key to find components(also supports
three components);click R key to find signal; double-click the left mouse button
to enlarge; click the right mouse button to shrink; click R key to rotate the
screen; click the space key to page. The specific operation can be viewed
through "help" menu. Note the operation example of figure 6-15~figure 6-21,
the signal found by clicking N key is "+15V" voltage. Voltage is also regard as
a signal (or network).
Figure 6-15: The operation drawing 1 of Landrex point position figure
Figure 6-22: The schematic diagram 8 of empty pins
When we click to select the pin of components, the name of signal will be
shown in the below status bar. As shown in figure 6-22. A common operation is:
when the welding plate appears the phenomenon of PIN dropping, we can refer
to the point position figure, to check which PIN need to fill PIN and which don't
need to fill.
3. Boardview------*.brd *bdv *bv

The software of Boardview point position figure is used in the file of Tuo Fu
(program BoardViewR4, the file format is *.brd), Hong Han (program
BoardView, the file format is *.bdv), Wei Yang (program Board View 1.3, the
file format is *.bv) and other company. The screenshot of Tuo Fu
BoardViewR4 shown in figure 6-23, press the shortcut key "D" to find the
components. Press the shortcut key "N" to find the signal.
Figure 6-23: The interface map of Tuo Fu point position figure

The screenshot of Hong Han shown in figure 6-24, press the shortcut key "D" to
find the components. Press the shortcut key "E" to find the signal.
Figure 6-24: The interface map of Hong Han point position figure
The screenshot of Wei Yang B View 1.3 shown in figure 6-25, press the
shortcut key "C" to find the components. Press the shortcut key "E" to find the
signal.
Figure 6-25: The interface map of Wei Yang point position figure
4. TSICT------*.asc
TSICT software is generally used by ASUS. Gigabyte also uses it. The common
operations are as below.
Click the "models" menu to load the file, if there are contents in the BOM box.
Selected it and click the OK button is as shown in figure 6-26.
Figure 6-26: The schematic map of TSICT point position figure opening files
Input the device label in the input box on the left bottom to find the device;
click "TOP" and "Bottom" to select the positive and negative side of the
mainboard is as shown in figure 6-27.
Figure 6-27: The interface of TSICT point position figure finding the device
The mouse will be stopped on the device. Select "display connected devices and
PAD” to find connected point from the context menu is as shown in figure 6-28.
Figure 6-28: The operation example of ASUS point position figure
Click the right key in the blank position, and click Net query, you can find the
signal, as shown in figure 6-29.
Figure 6-29: ASUS point position figure finding the signal
If you move the bitmap, and cannot find, you can click AUTO to automatically
return to the initial state, as shown in figure 6-30.
Figure 6-30 the position map of AUTO key
Chapter 7
The Introduction of EC and
BIOS
EC (Embedded Controller) is a 16-bit single chip microcomputer. Which is

featured in laptop, it is because of the use of EC, reflecting an important
difference between laptop and desktop.
In desktop, the keyboard and the mouse are independent of the system host is
generally connected with the host system by PS/2 or USB interface. But in the
laptop, in order to achieve the purpose of portability, it's necessary to use the
built-in keyboard (matrix decoding keyboard) and the built-in mouse (such as
the touchpad, TrackPoint are built-in mouse device).So the laptop needs a
special keyboard controller. The special EC of the laptop is equipped with this
feature.
Moreover, a most important problem in design of notebook is to make the
system more power, increase the battery life, it must have good heat dispersion
performance. And try to minimize the system noise. According to the
temperature to control the stalling of CPU fan, laptop power management, such
as laptop computer into standby or shutdown, the electric power dispatching of
the external power supply system, power detection of intelligent battery,
charging and discharging task, as well as some practical shortcut buttons. These
important functions are accomplished by EC.
In fact EC of the laptop is an extension of the traditional KBC (Keyboard
Controller), equipped with two part function of KBC and embedded control, so
EC is also called as KBC. EC is widely used in the design of laptop with
intelligent power-saving function. It undertakes task of laptop built-in keyboard
touchpad, laptop battery intelligent charging and discharging management and
temperature monitoring and others.EC plays an important role in design of
portable, intelligent personalized of the laptop.
EC interior has a certain capacity of Flash to store the EC code. The position of
EC in the system is not next to the North and South Bridge, in the process of
open system.EC control the timing sequence of most of important signal. In
laptop, no matter in the boot or shutdown state, EC is always open, unless the
battery and adapter completely removed.
In the shutdown state.EC has kept running, and waiting for the user's boot
information. And after the boot, EC continue to control the keyboard controller
charging indicator light and fan and other device, and even control the system
standby, sleep and other state.
BIOS is the abbreviation of "Basic Input Output System" in English. And the
Chinese name is "basic input/output system" after literal translation. In fact, it is
a group of program curing to a ROM chip on the computer motherboard, holds
the most important basic input/output program, the system settings information,
self-check program after booting and the system self-triggered program of the
computer. Its main function is to provide the lowest level and the most direct
hardware setup and control for the computer.
It should be noted that although the BIOS is referred to the program curing in
the ROM, but in maintenance, we usually called the ROM chip curing the
program as BIOS.
Figure 7-1 is the physical map of EC and BlOS. A large square chip is EC. A
small rectangle chip is BIOS.
Figure 7-1: The physical map of EC and BIOS
7.1: The Working Conditions and Functions of

EC
l. The basic working condition of EC
(l)Standby power supply: the name of EC standby power supply is usually
VCCCK AVCCx VCCA, etc., a small number of EC standby power supply is
VBAT.
(2)Standby lock: it’s usually an external 32.768 kHz crystal before, now most is
free of crystals.
(3)Standby reset the most beginning of the EC reset signal, which name is
usually ECRST WRST#, VCC_POR# etc. The reset of SMSC H8S is RES*.
(4)Program: EC need to get the corresponding program, configure the GP1O pin,
then to Work. The program may be stored in the EC. Also may be stored in the
ROM under EC.
2. The bus communicated EC and the South Bridge

EC connects with the South Bridge by LPC (Low Pin Count) bus.
VCC3: the power supply of LPC bus, 3.3V.
LPCCLK: LPC CLOCK provides 33MHz frequency for LPC, about 1.6V.
LRESET#: LPC reset signal, 3.3V.
LPC_AD [0:3]: address data complex line. These four signals are used to
transmit the address and data of LPC bus.
LPC_FRAME#: the cycle frame of LPC, when this signal is active, indicates
the start or end of a cycle of LPC.
3. EC controls LCD backlight

LID_SW#: lid-close switch. There are two functions of LID_SW#: in shutdown
state, this signal is used for EC to determine whether it can turn on; pull down
this signal after starting up, which can turn off the backlight. Commonly, now is
using the Hall component (magnetic sensor, Hall Effect) to control this signal.
LCD_BACKOFF: backlight control
LCD_BL_PWM: brightness control.
4. EC manages the battery charging

(1) Pre-charge
If the battery voltage is less than 0.9V, it is determined that the battery has been
damaged, will not charge the battery, because charging the damaged battery
may cause safety problems, such as the explosion or burning.
When the battery voltage is lower than the discharge end voltage(3V) and
greater than 0.9V,with 1/10 current of the constant current charging current to
charge with small current, and the time is short, generally for a few minutes. If
you use a large current to charge the battery with full discharge, it will damage
the battery.
(2) Constant current charging

When the battery voltage is greater than a certain threshold, it will be the
constant current charging, and the feature is constant current Most of the energy
of the battery (80%) is stored at this stage for a long time. The charge current is
generally controlled at an appropriate value, if the value is too large, which will
affect the charging efficiency, and the capacity will be reduced after full.
(3) Constant voltage charging

When the battery voltage reaches the end voltage of the charging, the battery is
charged with constant voltage, and the feature is that the battery voltage is kept
constant. The charging current is gradually smaller. When the current is less
than 1/10 of constant current charging current, charging end, the battery
capacity will be fully replenished.
(4) Trickle charge

When the charging current is less than 1/10 of the value of constant current
charging, the charging current is close to 0, which is the trickle charge. And the
feature is the battery voltage constant. The purpose is to supplement the self-
discharge of the battery; the self-discharge rate off the lithium battery is usually
5%~10% per month.
5. How to judge whether EC comes with the program

EC needs the program (EC CODE) configuration to complete its various work.
The program may be stored in its internal ROM, also may be stored in the
motherboard BIOS. If the EC comes with the program, when doing
maintenance, you must find the same motherboard to disassemble. If EC not
comes with the program, you can find the same type of chip to replace. How to
judge whether EC comes with the program?
First, observe the appearance, EC with stickers > marked on the surface is
usually bring their own procedures.EC in the figure 7-1 not comes with the
program, and EC in the figure 7-2 comes with the program.
Figure 7-2: EC comes with the program
Second, observe the architecture, in machines can be repaired on the current

market, there are four kinds of connection ways for EC and BIOS, as shown in
figure 7-3.
Figure 7-3: The relational graph of EC and BIOS
Firstly, BIOS connects to EC through X-BUS and SPI bus, and then EC
connects to the South Bridge through LPC, in general, in this case, EC code is
placed in the BIOS, that is share a chip with BIOS.
Secondly, BIOS connects to the South Bridge through SPI bus, there is not
ROM under EC, it uses its own internal ROM. Common in ThinkPad and Apple,
some models of the latest Lenovo also use this way.
Thirdly, the main BIOS connects to the South Bridge through SPI bus, hang a
SPI ROM chip under EC for storing EC CODE, such EC is not comes with the
program.
Fourthly, EC and the South Bridge connect BIOS through SPI bus, such EC is
not comes with program.
7.2: The Function and Working Conditions of

BIOS
BIOS is the program to provide the lowest level and the most direct hardware
control in the computer system. It controls the input device and output device of
the computer system, and is a hub connected the software program and
hardware device. For the PC, B1OS includes the controlling keyboard, display
screen, disk drive, serial communication device and some other functions of the
code. The computer technology develops into today, there are all kinds of new
technologies, many of the techniques of software part is to use BIOS to manage
and accomplish. For example, PnP technology (Plug and Play) is accomplished
by adding PnP module in the BIOS.
Again, the hot swap technology also transmit the hot swap information to the
configuration management program of BIOS by the system BIOS, and
reconfigured(such as interruption, DMA channel and other allocation) by the
program, In fact, the hot swap technology is also PnP technology.
In addition to the motherboard, on the other device, such as network card,

graphics card, MODEM, digital camera, hard disk and so on, are also have the
so-called BIOS, some SCSI cards and some interface cards with special
function also have its own BIOS. For example, BIOS on the graphics card is
used to complete the communication between the graphics card and the
motherboard. The start and using of the hard disk also needs HDD BIOS to
complete.
In the process of the boot, the mainboard BIOS will call and execute these
additional BIOS program complete the initialization of this hardware. So
theoretically speaking, each kind of hardware can have its own BIOS. But too
many BIOS, it will not only increase the cost, and will lead to compatibility
problems, therefore, in general, integrated the standardized device in the
motherboard, for those unique specification of manufacturers, appears with the
form of additional BIOS. These BIOS on the external and the motherboard
BIOS using Flash ROM as BIOS ROM chip, also easy to upgrade, to modify its
defects and enhance its compatibility.
l. The function of BIOS

(l) POST power on self-test: after the computer power-on, POST (Power On
Self-Test) program check each device in the system. Usually complete POST
includes to test CPU, 640KB basic memory, more than 1MB of extended
memory, ROM, CMOS, memory, serial and parallel graphics card soft and hard
disk and keyboard, once found the problem during self-test, the system will give
message or whistle warning,
(2) BIOS system start the bootstrap program: after the system finishing POST
self-test, ROM BIOS according to the boot sequence stored in the system
CMOS settings to search the soft and hard disk drives and CD-ROM, network
server and others for booting drive effectively, read the operating system boot
record, then give the system control power to the boot record, and completed
the sequence boot of the system by the boot record.
(3) Interrupt service routine: responsible for the allocation of the motherboard
hardware interrupt number assigned.
(4) Program settings: refers to enter the CMOS settings after booting.
2. BIOS capacity identification

For example, the model of SST 39VF040, three digits with underlined are
different, representing different capacity:
001/010/100: 1M=128KB
002/020/200: 2Mb=256KB
004/040/400: 4Mb=512KB
008/080/800: 8M=1MB
160: 16Mb=2MB
320: 32Mb=4MB
640: 64Mb=8MB
Note: 8b (bit) =1B (byte)
3. The package type of BIOS

There are many kinds of BIOS package, the specific as follows.
(1) TSOP48
BIOS with TSOP48 package are under EC, through X-BUS, the material object
Figure 7-4: BIOS with TSOP48 package
The definition of BIOS pins is shown in figure 7-5.
AO~A18: the address line DO~D15: the data line CE#: Chip select
VCC: Power Supply 3.3V OE#: output enable WE#: write enable
RESET#: reset VSS: ground connection
Figure 7-5: The definition of BIOS pins with TSOP48 package
(2) TSOP40
BIOS with TSOP40 package are generally X-BLJS bus, the material object
shown in figure 7-6, and the definition of pin shown in figure 7-7.
Figure 7-6 the material object of BIOS with TSOP40 package
Figure 7-7 the definition of X-BUS BIOS pin with TSOP40
(3) TSOP32
BIOS with TSOP32 are generally X-BUS bus, pin function is similar to
TSOP40, the definition of pin shown in figure 7-8.
Figure 7-8 the definition of X-BUS BIOS pin with TSOP32 package
(4) PLCC32
BIOS with PLCC32 package are also X-BUS bus in the laptop, the definition of
pin shown in figure 7-9, and the material object shown in figure 7-10.
CS#: chip select OE#: enable WE#: write enable VCC: power
supply pin GND: ground AO~A17: the address signal line DO~D7: the
data signal line
Figure 7-9: The definition of X-BUS BIOS pin with PLCC32 package
Figure 7-10: The material object of BIOS with PLCC32 package
(5) SOPS8
BIOS with 8 pin are SPI bus, the definition of pin shown in figure 7-11, the
material object shown in figure 7-12.
CS#: chip select SO: serial signal output WP#:write protection

GND: ground SI: serial signal input SCLK: serial clock
HOLD: pause VCC: power supply
Figure 7-11: The definition of SPI bus BIOS pin
Figure 7-12: The material object of SPI bus BIOS
(6) SOP16
BIOS used by IBM X200 part of the model uses 16 pin SPI bus, the definition
of pin shown in figure 7-13,the material object shown in figure 7-14.The
definition of pin is similar to 8 pin SPI,NC is Not Connected.
Figure 7-13 the definition of SPI bus 16pin BIOS

Figure 7-14 the material object of SPI bus 16 pin BIOS
Chapter 8
The Basic Working Process
of Laptop Computer
As professional laptop computer maintenance, personnel, in addition to have a

certain basic knowledge, also need to understand the working process and Intel
chipset standard timing of the laptop and other maintenance theories knowledge.
This chapter focuses on the boot process and Intel standard timing.
8.1: The General Boot Process of Laptop

Computer
The working process of the laptop follows a certain sequence. In the repair of
the laptop, in most cases, Timing applied on the power-on part in the system
boot, so also called Power Sequence. Mainly refers to a laptop motherboard
having done from standby to CPU get RESET signal. So literally, timing is time
and sequence. The motherboard from standby to power-on, and then to CPU
work, we feel just a short time.is almost a second, but in the work of the
motherboard, it will happen a lot of things in a second, from the standby voltage
producing.to press the switch, and to the motherboard received the switch signal,
then to send out each working voltage. And the motherboard made so much
action; it will strictly obey an established order, that is to say, in the process of
these steps, if the first step isn't completed. Then the next step is not start. And
there is a strict time requirement between each step, some will be accurate to a
few milliseconds, for example, PWRGD Signal generation requires that each
voltage stabilize about 5ms will be sent.
From the above introduction, we can see that the timing has very important
significance for the normal working of a motherboard, the most common fault,
such as no electricity, no boot and others, there have an important relationship
with the timing. It can be said that if you master the timing, then you have a
basic idea of maintenance for all kinds of faults of the laptop.
8.1.1 Hard starting process and Intel chipset standard

timing
1. Hard starting process in general.
The boot process of the laptop with Intel chipset (below series 4) is as follows:
(a) Without any electrical equipment supply power (no battery and no power),
through 3V button battery to produce VCCRTC to supply RTC circuit of the
South bridge, to keep the operation of the internal time and save the CMOS
information.
(b) After plugging in the battery or adapter, produce the common point.
(c) Then produce the EC standby power supply (usually linear voltage), after
the standby power supply is normal, EC supply power to crystal oscillator to
produce the EC standby clock, the standby power supply delay produce EC
reset, EC reads the program configuration own pin(BIOS chip select waveform
as shown in figure 8-1).
Figure 8-1: BIOS chip select waveform
(d) If EC detected the power adapter, it will automatically send a signal to open
the standby power supply of the South bridge (VCCSUS3_3, V5REF_SUS),
and send RSMRST# signal to the South bridge to notice the South bridge that
the standby voltage is normal; if EC is not detected the adapter (battery mode),
EC need to receive the switch trigger signal, then will open the South bridge
standby power supply, to save power.
(e) Press the switch, after EC receiving the switch signal, delayed send a high-
low-high boot signal to the South bridge PWRBTN# pin.
(f) After the standby condition of the South Bridge is normal and receiving
PWRBTN# signal, raising SLP_S5#, SLP_S4#, and SLP_S3 #signal in turn.
(g) SLP_S5# or SLP_S4# control the production of the memory main power
supply etc,SLP_S3#control the production of the bridge power supply. The bus
power supply (VCCP), the independent graphics power supply etc. (some is
controlled directly by SLP signal. And some is controlled by EC after SLP
sending to ECX
(h) EC delay send signal or other circuit switching to open CPU core voltage
(VCORE).Thus, the voltage of the machine has been fully opened.
(i) After CPU power supply being normal, CPU power management chip send
PG to the South Bridge VRMPWRGD pin at last.
(j) After CPU power supply being normal, open the clock chip through the
conversion circuit then produce various clocks.
(k) The South bridge received the power supply, clock, VRMPWRGD, and
received EC or power supply circuit delay conversion PWROK, the South
bridge will send CPUPWRGD to inform CPU that its core voltage has been
successfully opened, and send PLTRST# and PCIRST# signal at the same time.
(l) After the North bridge receiving PLTRST#, send CPURST# signal to CPU,
then CPU officially start to work.
The above is the hard start process of the laptop. In the process of hard start we
can divide the power supply of the laptop into 4 levels.
(1) G3 power: voltage generated just plug the power, generally supply to power
switch and EC, is usually produced by linear way.
(2) S5 power: the standby voltage of the South bridge, supply to VCCSUS3_3
of the South Bridge, power in the state of power off is usually produced by
PWM way.
(3) S3 power: the power supply of the memory, the power in the state of S3
sleeping.
(4) SO power: the main power supply to the normal operation of the machine
also called RUN power, including the bridge main power supply, the bus power
supply, CPU power supply and others.
Sometimes, 3V, 5V produced by PWM way under the condition of G3 or S5 are

also called the system power supply. For example, Quanta series PCU voltage is
the system power supply. But it exits under the condition of G3.And for
example: ASUS A8E South bridge standby voltage is produced by PWM way it
is the system power supply.
2. Intel
The Intel chipset standard timing as figure 8-2 is Intel chipset standard sequence
diagram.
Figure 8-2: Intel Series-4 Chipset Standard Sequence Diagram
According to the sequence diagram shown in figure, 8-2 is explained as follows.
(1) System State

G3: the power of the whole system are closed.
(2) The interpretation of the signals
 VCCRTC: the power supply of the South bridge RTC circuit, 3V, supply
power to CMOS chip (RAM) inside the South Bridge.
 RTCRST#: the reset signal of the South bridge RTC circuit, 3 V.1CH9
added another RTC reset signal later, the name is SRTCRST#.
 32.768 kHz: after the South Bridge receiving VCCRTC and RTCRST #,
supply power to the crystal oscillator. The crystal oscillator running. The
voltage of two pins of the crystal oscillator is 0.1-0.5 V.
 V5REF_SUS:5V standby voltage.
 VCCSUS3_3: 3.3V standby voltage.
 VCCSUS1_05: The South Bridge internally produced the power supply
1.05V for itself, not to consider this voltage when we analyze the timing.
 RSMRST#: inform the South Bridge that 3.3V standby voltage is normal.
The external circuit controls voltage 3.3V.
 SUSCLK: after the South bridge receiving RSMRST#, then send the
32kHz clock, most machines do not use, it can be ignored.
 PWRBTN#: POWER BUTTON, 3.3V-0-3.3V pulse signal.
 SLP_S5#: 3.3V, the control signal when the South Bridge exit the power
off state.
 SLP_S4#: 3.3V, the control signal when the South Bridge exit the
dormant state. (Usually just use S5# or S4#, used to control the
production of the memory power supply, and another is idle.)
 SLP_S3#: 3.3V, the control signal when the South bridge exit the
sleeping state. (usually used to control the bridge power supply, the bus
power supply, the independent graphics power supply, CPU power
supply etc.)
 VDIMM: the memory power supply.
 VCORE/VCC: refers to the bridge power supply, the bus power supply,
the independent power supply, CPU power supply etc.
 VRMPWRGD: inform the South Bridge that CPU power supply is
normal, 3.3V. CLK GEN: the clock chip starts to work, send various
clock.
 PWROK: inform the South bridge that power supply is normal

(SLP_S3# complete task), 3.3V. CPUPWRGD: The South Bridge sends
PG to CPU, 1.05V.
 PLTRST#: the platform reset, the South bridge send the first reset, 3.3V
is generally sent to the North bridge, EC, MINI slot etc.
 PCIRST#: PCI reset, the South bridge send the second resettle 3.3V
computer is not usually used.
 CPURST#: after the North bridge receiving PLTRST#, send the reset of
CPU, 1.05V.
8.1.2 The soft start process

Next to the Intel Bridge (such as GM45) as an example, see CPURST#,
addressing process of CPU and power-on self-test process. In the process of the
computer hard start, CPURST reset signal is sent and keep a low level of a
certain time, when the power supply circuit has been stable, then removed the
RESRT low level and keep a high level, CPU start to work, the hard start
finished, and start to the soft start.
1) CPU will check FSB front bus line is busy or not through the DBSY# signal
of the interface circuit. When DBSY# is low level, it means that FSB bus is
busy, only released it, CPU will be the next step work; when DBSY# is high
level, it means that FSB is not busy, CPU will through ADS# address strobe
signal line to tell the North Bridge ready to send the data.
ADS waveform is as shown in figure 8-3.
2) After the North bridge receiving this signal, if it’s in good condition and has
been ready, the North bridge will send a low level of H_TRDY# to CPU, told
the CPU is ready, and can receive the data. Then CPU will through A31~AO
send FFFFOH address signal, which is a jump instruction in the BIOS.AO-A31
to FSB front bus interface of the North Bridge, through FSB frequency
conversion. Level conversion and address decoding send to the North Bridge.
After the North, bridge receiving CPU addressing instruction. Through DMI,
bus sends to the South Bridge.
The North bridge and the South bridge DMI bus consists of 16 lines, point to
point transmission, signal lines including DMI _RXP(0:3), DMI_RXN(0:3),
DMI_RXN(0:3), DMI_TXN(0:3), as shown in figure 8-4.
Figure 8-3: ADS# Waveform
Figure 8-4: DMI bus signal diagram

3) After the South Bridge receiving the addressing instruction of the North
Bridge. Then start to search BIOS, first search whether there is BIOS on the PCI
bus (see figure 8- 5).When there is no BIOS on PCI bus. According to the PCI
bus signal set to determine where BIOS is. If the BIOS is under EC, after the
South Bridge through PCI decoding module, then to communicate with EC on
the LPC bus. When EC receiving the addressing instruction, after that through
X-BUS or SPI bus to BIOS. BIOS returns the data to the CPU, CPU running
POST self-check program in the BIOS, and start self-check action.
Figure 8-5: BIOS location settings
The key signal to determine whether PCI bus action: PCI_FRAME# (Cycle
Frame).
PCI frame period signal is low level; it means that PCI bus start work. And
when it is high level, it means that PCI bus is not to work.
The key signal to determine whether LPC bus action: LPC_FRAME# (LPC
frame period).
The key signal to determine whether BIOS action: CS# (chip select).Selected
when low level, and is not selected when high level.
4) After CPU reading BIOS self-test correctly, and then start to execute the
process of POST instruction.
(a) When CPU addressing is normal, received POST self-test program returned
by BIOS, then start initialized the chipset(the South bridge and the North
bridge),and also initialized PCI-E bus(independent graphics).
(b) After the South Bridge initializing, grab the memory through SMBUS bus to
be initialized, the waveform is shown in figure 8-6.
(c) After the memory self-test finishing, BIOS stores the self-test program into
the memory.
(d) Then called the BIOS program from the memory to test each device one by
one, such as the keyboard controller, network cards, sound cards etc.
(e) Testing the graphics cards, find BIOS of the graphics cards, and call them to
complete the initialization of the graphics cards.
(f) The graphics cards starts to read the screen information through ED1D bus
(shown in figure 8-7), after reading the screen, then sends a signal to open the
screen power supply and backlight.
Figure 8-6: SMBUS waveform of the memory
Figure 8-7: EDID waveform
(g) Display the boot picture, and start to test the extended memory and give the
corresponding address.
(h) Test some standard equipment, including hard disk, CD drives, serial ports,
parallel ports, floppy drive etc.
(i) After testing the standard equipment, the plug and play code supported by
the system will start to test and configure the plug and play equipment in the
system, and distributes the interrupt address, DMA channel and I/O port and
other resources for this equipment.
(j) After all hardware testing and being assigned the interrupts address, that is,
all the hardware set up a hardware system, then it will generate a ESCD file (it
is the method that the system BIOS exchange hardware configuration
information for the operation system, the data is in CMOS), CPU will compare
the generated ESCD with the last ESCD if finds the difference, it will update
the data in ESCD.
(k) After updating ESCD, CPU will complete POST and the interrupt service
routine. Then carry out the bootstrap program of the system. The boot code of
the system BIOS start the operating system according to the boot sequence
specified by users, find the boot files in the starting device first then write in the
memory, BIOS give the control power of the computer to the boot files. The
operation system guided by the boot files, such as Windows XP, Windows 7
and so on.
8.2: About ACPI Specification
8.2.1 ACPI summarize
ACPI (Advanced Configuration & Power Interface) is the standard of the

advanced configuration and the power interface. Before ACPI proposed, the
universal power management standard is APM with a BIOS level developed by
Microsoft. ACPI is to replace the previous APM.
ACPI is jointly developed by Intel, Microsoft, Toshiba, is to have a common
power management interface between the operating system and the hardware,
and to improve the disunity interface developed by the different manufacturers
on the power management before.
From Windows 98/SE, Windows ME and Windows 2000, Windows XP starting
to support ACPI. From the laptops to the desktops and servers are included in
this specification.
ACPI can make the system to enter a low power consumption of "sleep state",
such as standby and sleep; the purpose is to control the power consumption of
the computer.
All state of ACPI can be divided into G (Global), D (Device), S (Sleeping), C
(CPU).
8.2.2 G (Global) State of ACPI

Global refers to all system, and can be divided into the following 4 kinds.
1) GO: Working state. The user program can be executed normally. But the
device dynamically allocates their own state. When not used this device. This
device can enter other non-operating state. Under this state, the system responds
the external events in real time. And the machine cannot be disassembled and
assembled under this state.
2) G1: Sleeping state. Under this condition, the system consumes less power,
and no user's program is executed. The system looks like in the shutdown state.
Because the display screen is turned off at this time. As long as any wake-up
activation events message into the system, it will soon be restored to a working
state. Under this state, the machine cannot be disassembled and assembled.
3) G2/S5: Soft Off state. System only keeps very little power under this state, no
users and the operating system programs are executed. The state takes a long
time to return to a working state. Under this state, the machine cannot be
disassembled and assembled.
4) G3: Mechanical Off state. Under this state, the power of the whole system is
closed, there is no current through the system, and the system can only reopen
the power supply switch to active. Under this state, the power consumption is
zero.
8.2.3 D (Device) State

Device refers to some devices, such as modems. Hard drives, CD-ROM, etc.
also can be divided into the following 4 kinds.
1) DO: Fully On. The normal working state.
2) Dl: It can save less power consumption; the device function with keeping
activities is much more than which in D2 state. The device itself determines this
state. And some devices cannot enter into the Dl state.
3) D2: Some functions are shut down; it can save a lot of power. The device
itself determines this state; some devices cannot enter into the D2 state.
4) D3: Off. The power of the device under this state is completely removed, so
the next time when the power is supplied once again, it needs the operating
system to make a setting again. Under this state, the device does not decode the
addressing line. This state needs the longest wake-up time. All devices can enter
into this state.
8.2.4 S (Sleeping) State of ACPI

S state means Sleeping, and refers the system enter into the sleeping state in G1,
also can be divided into SO, S1, S2, S3, S4, S5.
1) SO: In fact, this is our normal working state, all devices are fully open, and
the power consumption is generally more than 80 W.
2) SI: CPU internal clock has been shut down under this state, but the contents
of the system (CPU, Cache, chipset) are not lost, the other parts are still
working normally. At this time, the power consumption is generally below 30W.
In fact, some of CPU cooling software is developed in this working principle.
3) S2: Similar to SI, at this time. CPU is in the state of stop, the content of CPU
and Cache has been lost, and the bus clock is also shut down, but the rest of the
device is still running.
4) S3:This is STR(Suspend to RAM) we familiar with, in addition to the

information of the memory, the content of CPU, Cache, chipset is lost the
content of the memory is provided by the hardware, the power service data is
exist. The power consumption is less than 10W at this time.
5) S4: is also called STD (Suspend to Disk), the system main power supply is
shut down, but the system information will stored in the hard disk. By the
operating system implementation after Windows 2000, all the data of the
memory saved to hiberfil.sys file in the hard disk, the hard disk is not charged.
6) S5:A11 devices are shut down. Which is soft shutdown, the power
consumption is closed to 0.
The most commonly used is the S3 state, that is Suspend to RAM state, referred
to STR.As the name implies, STR is that to save the data of the working state
before the system entering STR into the memory. Under the state of STR, the
power still continues to supply the power for the most necessary devices, such
as memory, to ensure that the data is not lost, while other devices are in a closed
state, the power consumption of the system is very low. Once we press the
power button, the system will be awakened immediately read the data from the
memory and return to before working state of STR. The read-write speed of the
memory is very fast, so users feel that it takes just a few seconds to enter and
leave STR state. And S4 state, that is, STD, the data is stored in the hard disk.
Because the read/write speed of the hard disk is much slower than the memory,
so it does not so fast like STR in using.
8.2.5 C State of ACPI

The C state of ACPI refers to the state of CPU, and can be divided into the
following 5 kinds.
1) C0: the normal working state of CPU.
2) C1: CPU suspends work automatically, the software is completely unaffected
under this state, and there is a minimum time to wake up. The hardware wake-
up time in this state must be small enough, so the operating software can
completely ignore the hardware wake-up time in this state when determine
whether use this device or not.
3) C2: Similar to Cl, the South bridge send STPCLK# to CPU, and stop CPU
internal clock, but CPU continues to monitor the consistency of the bus and
cache. The sequence of CO-C2-CO is shown in figure 8-8.
Figure 8-8: The sequence of C0-C2-C0
5) C4: Similar to C3 sleeping state, after the South Bridge sending STP_CPU
and closing CPU clock, the South bridge send DPRSLPVR and DPRSTP#
signal to CPU power management chip, to close the CPU core voltage. The
sequence of CO-C4-CO is shown in figure 8-10.
Figure 8-10: The sequence of C0-C4-C0
8.2.6 The power and the control signal of ACPI
1) 3VSB:3.3V standby voltage, supply the power to the wake-up of ACPI

controller, the network card, PCI and others in the South bridge.3SVSB is the
customary name, the name of each manufacture is different, but the same
chipset, the name in the South bridge is the same.
The standard name of 3VSB in the three chipset: Intel is VCCSUS3_3; nVIDIA
is +3.3V_DUAL; AMD is S5_3.3V or VDDIO_33_S.
2) RSMRST#: the normal signal of the standby voltage. The voltage is 3.3V.
The name of RSMRST# in the three chipset: lintel and AMD are RSMRST;
nVIDIA id PWRGD SB.
3) SLP_S3#, SLP_S4#, SLP_S5#: the signal of the low level control enter
S3,S4,S5state.Forexample,the system is in the state of SO when running
normally, three signals should be invalid, is 3.3V. SUSB#, SUSC# and others
are similar to SLP_S*# signal. The state of the sleep signal in each sleeping
state is shown in figure 8-11.
Figure 8-11: The state of the sleep signal in each sleeping state
PWRBTN#: Power Button. At shutdown, pull low PWRBTN# signal, ACPI
will set high SLP_S5#> SLP_S4#^ SLP_S3# to 3.3V in turn. If PWRBTN#
continues being the low level for 4s, the system will be forced into the S5 state.
8.3: Clock, PWRGD and The Reset Circuit

If we analogy to the each device of the computer system is a group of people,
then the clock chip is like a password. But this is not a password, is the group
with integrated multiple password. It provides the different frequency to the
main system chip and the slot on the motherboard, but there will have the same
frequency between connected devices, then it can exchange data information
normally between these chips. PG and the reset in this section are for the South
Bridge. One is the working condition of the South Bridge. And another is the
affair the South Bridge done after getting this working condition.
8.3.1 The clock circuit
1. The working condition of the clock chip.

1) As shown in figure 8-12, the working condition of the clock chip is following:
The power supply: +3VS produces +CLK_VDD> +CLK_VDD1 through L16
and L32 and provides 3.3V, +1.05V produces +CLK_VDDSRC through L15
and provides 1.05V.
2) The open signal CK_PWRGD/PD#: the high-level 3.3V opened.
3) 14.318MHz reference crystal Y2.

4) CPUJSTOP^ PCI_STOP#: CPU and PCI clock stop instructions needs to be
the high level when working normally.
5) SMBCLK SMBDATA system management bus: used to transfer BIOS
instructions.
6) FSLA> FSLB> FSLC frequency selection: according to the different CPU to
produce the different front bus clock.
2. GM45 -The clock signal distribution of GM45 chipset

The clock signal distribution of GM 45 chipset is shown in figure 8-12, the
specific is following.
1) CLK_CPU_BCLK, CLK_CPU_BCLK# of 71, 70 pin is the front bus clock
that the clock chip send to CPU, more than 100MHz, the specific value is set by
FSA/FSB/FSC.
2) CLK_MCH_BCLK> CLK_MCH_BCLK# of 68,67 pin is the front bus clock
that the clock chip send to the North bridge, more than 100MHz,the specific is
set by FSA/FSB/FSC.
3) 24,25,28,29 pin is the set display clock that the clock chip sends to the North
bridge, 96MHz and 100MHz.
4) 32, 33 pin is the SATA controller clock that the clock chip sends to the South
Bridge, 100MHz.
5) 35, 36 pin is the PCI-E module clock that the clock chip sends to the South
Bridge, 100MHz.
6) 57, 56 pin is 100MHz core clock that the clock chip sends to the North
Bridge.
7) 44, 45 pin is 100MHz clock that the clock chip sends to MIMI PCI-E slot,
used for wireless network cards, etc.
8) 48.47 pin is 100MHz clock that the clock chip sends to the onboard card.
9) 15 pin is 33MHz clock that the clock chip sends to the EC chip.
10) 17 pin is 33MHz clock that the clock chip sends to the South Bridge, used
in the reset circuit in the South Bridge.
11) 20 pin is 48MHz clock that the clock chip sends to the SD card reader chip
and USB controller in the South Bridge.
12) 7 pin is 14.328MHz reference clock that the clock chip sends to the South
Bridge.
13) 58, 43, 46, 21 pin is the request signal of each clock, the low level is
effective.
Figure 8-12: The clock signal distribution of GM45 chipset
3. HM55 The clock signal distribution of HM55 chipset
The clock signal distribution of HM55 is shown in figure 8-13, the

characteristic is that the clock chip is just sent to PCH clock, and then sent out
each clock by PCH to other devices. If it supports the display stand, the display
set supports DVI/DP/HDMI/e-DP interface. The bridge needs 25MHz crystal.
Figure 8-13
4. The clock signal distribution of above HM65 chipset

The clock signal distribution of above HM65 chipset is shown in figure 8-14,
the characteristic is that it must be 25MHz crystal when the bridge integrates the
clock chip.
Figure 8-14: The clock signal distribution of above HM65 chipset
5. AMD- The clock signal distribution of AMD double bridge chipset
The clock signal distribution of AMD double bridge chipset is shown in figure
8-15, the clock chip sends each clock, but is just not responsible for sending
33MHz clock, 33MHz clock is sent by the South bridge.
Figure 8-15: The clock signal distribution of AMD double bridge chipset
6. AMD- The clock signal distribution of AMD single bridge
The clock signal distribution of AMD single bridge is shown in figure 8-16, the
characteristic is | that the bridge integrates the clock chip.
Figure 8-16: The clock signal distribution of AMD single bridge chipset
7. nVIDIA- The clock signal distribution of nVIDIA chipset
The clock signal distribution of nVIDIA chipset is shown in figure 8-17; the
characteristic is that the bridge integrates the clock.
Figure 8-17: The clock signal distribution of nVIDIA chipset
8.3.2 PWRGD and the reset circuit

The explanation of VRMPWRGD, PWROK, CPUPWRGD, PLTRST#,
PCIRST# signal in the South Bridge is following:
VRMPWRGD: this signal should be connected to the PWRGD signal of CPU

power supply chip, used to indicate that the CPU core voltage is stable. This
signal phase with PWROK signal is in the South Bridge. The text of
VRMPWRGD pin definition is shown in figure 8-18.
VRMPWRGD I
VRM Power Good: This should be connected to be the
processor’s VRM is stable. This signal is internally
ANDed with the PWROK input.
Figure 8-18: The screenshot the text about VRMPWRGD pin definition
PWROK: when the signal is effective, PWROK inform that all power of ICH
has been generated ' and stable for 99ms, PCICLK has been stable for
1ms.When PWROK becomes lower level, ICH produces PLTRST# with low
level. Note: PWROK must be inactive for three RTCCLK clock cycles at least.
The screenshot of the text about PWROK pin definition is shown in figure 8-19.
CPUPWRGD: CPU power good, this signal should be connected to
PWRGOOD pin of the processor, indicates that CPU power supply is effective.
This is an output signal, formed by the phase of PWROK and VRMPWRGD.
The text of CPUPWRGD pin definition is shown in figure 8-20.
Figure 8-19: The screenshot of the text about PWROK pin definition
Figure 8-20: The screenshot of the text about CPUPWRGD pin definition
PLTRST#: ICH produces PLTRST# signal to reset all devices (such as SIO,
FWH, LAN, GMCH, TPM, etc.) on the entire hardware platform. When
PWROK and VRMPWRGD are high level, ICH will delay 1ms and drive
PLTRST# to be high level. The text of PLTRST# pin definition is shown in
figure 8-21.
Figure 8-21: The screenshot of the text about PLTRST# pin definition
PCIRST#: This is the second reset signal, which is produced by the PLTRST#
delayed buffer. The text of PCIRST# pin definition is show in figure 8-22.
Figure 8-22: The screenshot of the text about PCIRST# pin definition
At last, after the RST1N# pin (the pin definition is shown in figure 8-23) of the
North bridge receiving PLTRST# sent by the South bridge. Delayed 1ms send
CPURST# to CPU, to complete the hard start. HCPURST# pin definition is
Figure 8-23: The screenshot of the text RSTIN# pin definition
Figure 8-24: The screenshot of the text about HCPURST# pin definition
The sequence of the reset circuit is as shown in figure 8-25.
Figure 8-25: The sequence of the reset circuit
Chapter 9
The Explanation of PWM
Circuit
PWM is that pulse width modulation; it is a very effective technique of using

the digital output of the microprocessor to control the artificial circuit, is widely
used in many fields from measurement, communication to power control and
transformation. This way is used in most of the power supply circuit in the
laptop. Compared with the linear regulated power supply, the PWM circuit has
the advantages of high efficiency, high output power, but also has the
disadvantages of complex circuit.
9.1: The Introduction of PWM Circuit

The PWM circuit in the laptop motherboard is generally composed of PWM
chip, MOS, the coil, and the capacitance.
9.1.1 Introduction to PWM Working Principle
The brief introduction of the working principle of PWM regulates the output
voltage by adjusting the effective pulse period T1, which accounts for the
proportion of the entire pulse period T (duty cycle).As the figure 9-1 an
example, the validity period of the highest voltage amplitude is about 5V, the
duty ratio is about 50%, so the output voltage is 5V x 50%=2.5V.
Figure 9-1: PWM waveform
1. PWM The working principle of PWM power supply
The principle of PWM power supply circuit is shown in figure 9-2,PWM chip
controls the high speed switch of the upper and lower tube to adjust the voltage,
when the upper tube is opened, the VIN passes through the upper tube to charge
LC energy storage circuit and supply power to the rear; the chip through FB
monitor to charge full, then closes the top tube, and opens the down tube, forms
the discharge circuit of LE energy circuit, and continues to supply power to the
rear.T1 in the figure is the open state,T2 is the closed state, as long as control
the duty cycle of T1,then it can control the height of output voltage.
Figure 9-2: The principle figure of PWM power supply circuit
2. PWM The working process of PWM power supply

The specific working process of PWM power supply can be subdivided into
four stages:
(1) Before T1, the dead time, the top tube and down tube are cut off, at this time,
the top and down tube drive signals are low level and two tubes are cut off.
(2) The period of timeT1, the top tube drive signal is high level. The down tube
drive signal is low level, at this time, the top tube is conducted, and the down
tube is cut off. VIN voltage through the D-S pole of the top tube and L1, then
Figure 9-3: The waveform of the top and down tube drive signal
Flows through the load, and flows to the ground finally, when the current flows
through the inductance, produces the positive on the left and the negative on the
right induced voltage on the inductance. Figure 9-3: the waveform of the top
and down tube drive signal.
(3) The period of time T1~~T2, at this time, closes the top tube. The current
flowed through the inductance disappeared suddenly, because of the inductive
effect of the inductance, both ends of the inductance will produce a reverse
voltage, the direction of this voltage is the positive on the right and The
negative on the left. The enlarged drawing of the top and down tube signal
waveform is shown in figure 9-3, after UGATE becoming to be low, LGATE
will be driven to be high after delaying time, and this period of time is also the
dead time.
(4) The period of time T2, at this time, the top tube drive is low level, and the
down tube drive is high level. So the top tube is cut off, the down tube is
conducted, the induced voltage with the positive on the right and the negative
on the left inducted on the inductance through the right end of L1 to the load,
flows through the S-D pole of the down tube, then flows to the negative
terminal of the voltage, that is the left end of L1.
The real object of the single phase PWM circuit is shown in figure 9-4,is
usually used for the memory power supply, the bridge power supply, the bus
power supply, the graphics card power supply and others.
Figure 9-4: The real object of the single-phase PWM circuit
The real object of the multiphase PWM circuit is shown in figure 9-5, is usually
used for the CPU core power supply.
Figure 9-5: The real object of the multiphase PWM circuit
9.1.2 The meaning of common English abbreviation in

PWM circuit
SKIP, SKIPSEL: the work mode setting.
TON, RT, FS: the frequency setting (set the frequency by the resistance
connecting the ground or the power supply).
BOOT, BST, BOOST: boot-strap pin, the power source of the G pole of the
top tube.
UGATE, DH, HDRV, DRVH: the top tube drive.
LGATE, DL, LDRV, DRVL: the down tube drive.
FB: the feedback-adjusting pin.
COMP: feedback compensation, correct the error of the feedback circuit.
OUT, VOUT, VO: output voltage detection input pin.
PHASE, SW, LX: the phase pin, connects the S pole of the top tube/the D pole
of the down tube/the inductance, forms the loop with BOOT, and some can be
the current detection.
CSP/CSN: the current detection pin.
ILIM, TRIP, CS: the over current protection threshold value sorting, the
limited current setting.
* Notes: “tube” is meaning the MOSFET.
9.1.3 The boot-strap circuit

In the PWM power, the top tube is usually N channel, the output voltage is from
the common point. Because the power chip is limited to the driving ability of
the top tube, and almost all of the chips are used the boot-strap circuit to
improve the driving ability and the name of boot-strap pin are usually BOOT,
BST, BOOST. PWM circuit using the method of boot-strap is shown in figure
9-6.
As the figure 9-6 an example, explains the principle of boot-strap:

B+ of 19V supplies power to the high-end tube PQ5, at this time, the G pole is
no power, so the S pole outputs OV. At the same time, B+ of 19V is input to
PU3,the internal produces the linear voltage VL with 5V,through the internal
diode supplies power to BOOT1, if skips the pressure drop, it’s still 5V,added to
1 pin of PC33,to charge it, the capacitor stored 5V voltage.
BOOT1 of 5V supplies the power to UGATE1, sends the high level about 5V, is
sent to the G pole of PQ5, at this time, the G pole of the moment PQ5 is 5V, the
S pole is 0V, the channel of PQ5 can be conducted completely, 19V flows
through PQ5 and PL4 to charge PC35, the voltage output by PQ5 is gradually
increased.
Figure 9-6: PWM circuit using the boot-strap method
When the voltage output by PQ5 is gradually increased, if this voltage is 2V,
and 2V is added to 2 pin of the capacitance PC33 at the same time, because of
the feature of the capacitance. it just stores the power with 5V,at this time, adds
2V,so,the left of the capacitance (that is BOOT1) will become to be 7V,and 7V
continues to supply power to UGATE1, the G pole of PQ5 will also become to
be 7V,keeps PQ5 VG>Vs, and is higher than 4.5V,PQ5 keeps conducted
completely, the voltage of the S pole will also follow to rise, adds again to PC33.
So, we can measured the square wave with the highest 19V and the lowest 0V
on the left of PL4.Because the power of the capacitance PC33 always not be
discharged, the voltage of BOOT1 will forever be higher than the left of PL4 to
5V, that is 19+5=24V, the waveform of UGATE1 is also that the lowest is OV,
and the highest is 24V.
9.1.4 Output voltage regulation circuit

As shown in figure 9-7, through two sampling resistance connected by FB
feedback pin dividing into voltage, compared with the internal reference voltage,
so as to realize the output voltage regulation. The computational formula is:
VOUT= FB x (1+R1/R2)
If FB=0.8V, R1 is equal to R2, then Vout=1.6V
Figure 9-7
9.1.5 The voltage detection circuit

PWM power needs to detect at any time that if the output voltage meets the
required standard, avoids that the output voltage is too high or the output
voltage is too low. In the figure 9-8, OUT pin is used for the output voltage
detection.
Figure 9-8: The figure of the voltage and current detection circuit
When the output voltage is over voltage, the chip internal uses OVP (over
voltage protection); when the output voltage is too low, the chip internal uses
UVP (low-voltage protection). The 3.3V of standby voltage over-voltage
protection waveform is shown in figure 9-9.
Figure 9-9: The 3.3V of standby voltage over-voltage protection waveform
9.1.6 The current detection circuit
Figure 9-10: The figure of the current detection
PWM power needs to detect the output current at any time .When its over-
current, the chip internal starts using OCP (over-current protection) mechanism.
There are two methods of detecting current: As shown in figure 9-8, PWM chip
can detect the current through CSH, CSL pin: series a milliohm resistance, CSH
detects the resistance input end voltage; CSL detects the resistance output end
voltage. To calculate the differential pressure at both ends of the resistance,
divides the resistance value to get the current, the computational formula is:
I= (CSH-CSL)/R
The figure of the current detection as shown in figure 9-10, no CSH and CSL
chip, it can detect through the down tube between PHASE pin and PGND pin:
after the down tube conducting, the resistance value is dozens of milliohm,
detects conducted voltage drop of the down tube to get the current. By this
method to detect the current, it’s not very precise. During calculating, we should
use the maximum value of the worst case in the data manual of the field effect
transistor, and considers that the resistance value after the field effect transistor
conducting will be increased with the rising of the temperature, so it’s also need
the certain allowance. The benefit of this way is reliable, and it is the non-
destructive over-current detection.
When the output voltage is over or the output current flows through, the chip
will use the internal output discharging mode. In this mode, the top tube G pole
driver signal is turned off to be 0V low level, the G pole driver signal of the
down tube is driven to 5V high level, at this time, the top tube is cut off, the
down tube continues to be conducted, the charge stored on the output filter
capacitance is quickly discharged to the ground through the down tube, the
output voltage is closed.
Special reminder: in the PWM circuit, is strictly prohibited to remove the chip
then power up. The G pole of the top tube is suspended, which will cause that
VIN is added to the rear stage directly, and burns the components.
9.1.7 The working mode

In the laptop, most of PWM power 1C can work in the different two modes,
PWM mode and SKIP (pulse separation mode), the purpose is to adapt to
different sleep state. and outputs the different current (output voltage
constant).There is SKIP# in the chip, is used to realize the mode switch, when
SKIP# is low, the chip works in the pulse separation mode(SKIP mode),at this
time, the output current is small, such as 3V standby voltage, it just needs to
work in the SKIP mode when in the standby mode. But after powering on, the
output current of 3V standby voltage must be increased, because some of the
system voltage at this time is from the 3V standby voltage conversion, so that
the output current must be increased, SKIP#(usually controlled by SLP_S3#
sent by ICH) of the chip is high. The chip works in PWM mode, the output
voltage is constant, but the output current is greatly increased.
1. PWM, PWM mode

In PWM mode, the voltage load capacity is strong, the output current is large.
The waveform in PWM mode is shown in figure 9-11,the frequency is
299.4kHz.
2. SKIP# mode (pulse separation mode)

Within the unit time, the less of the PWM waveform, it will smaller the output
current. The waveform in SK1P# mode is shown in figure 9-12; the frequency is
just 34.63 kHz.
Figure 9-11: The waveform in PWM mode
Figure 9-12: The waveform in SKIP mode
9.2: Analysis of The Standby Power Chip
Figure 9-13: The pin name of MAX8734A (the top view)
9.2.1 Analysis of MAX8734A

MAX8734A (is in common use with MAX 1999) is the standby power chip
with high efficiency and four of the output produced by MAXIM company to
use for the laptop. The main features: not need the current detection resistance;
1.5% output voltage accuracy; supplies the linear output with 3.3V and 5V; the
maximum current with 100mA; can output two path of PWM power supply:
3.3V and 5V; the operating voltage range of 4.5~24V; the choice of the pulse
mode and PWM mode; over-voltage and under- voltage protection.
1. MAX8734A pins description
Table 9-1: The definition of the pin function of MAX8734A
(Pins) ----- (Description) of MAX8734A

(1) the vacant pin
(2) the power good, open drain output. If the output of any path is forbidden
or the output is 10% lower than the standard value, PGOOD is pulled low.
(3) 3.3V SMPS enable input.ON3 connects to REF, 3.3VSMPS will start
after 5V SMPS being stable.
(4) 5V SMPS enable input.ON5 connects to REF,5V SMPS will start after
3.3V SMPS being stable.
(5) 3.3V SMPS current limit adjustment
(6) Shutdown control input. The main switch of the chip is the opening of
the linear voltage.
(7) 3.3V SMPS feedback input.FB3 connects GND to choose the fixed
output 3.3V, FB3 connects to the resistance divider between OUT3 and GND, it
can achieve the adjustable output of 2~5.5V.
(8) 2V reference voltage output. It can only provide 100 current, and it will
lead to lower output accuracy with REF load.
(9) 5V SMPS feedback input.FB5 connects GND to choose the fixed output
5V, and connects FB5 to the resistance divider between OUTS and GND, it can
achieve the adjustable output of 2~5.5V.
(10) Over-voltage and under-voltage protection enable pin. When PRO#
connects VCC, forbids the protection.PRO# connects the ground, then opens the
protection function
(11) 5V SMPS limit current regulation.
(12) Low noise mode control. When SKIP# connects the ground, works in
the idle mode, when SKIP# connects VCC, works in the PWM mode. When
SKIP# connects REF or is vacant, works in the ultrasonic mode.
(13) Frequency selective input. When TON connects VCC, chooses

200/300 kHz working mode, when it connects the ground, chooses
400/500kHz working mode (respectively corresponding the switching
frequency of 5V, 3.3V SMPS)
(14) The bootstrap capacitor connection terminal of 5V SMPS
(15) The inductance connected 5V SMPS. It¡®s the internal low-end power
supply rail of DH5.LX5 is the current detection input of 5V SMPS
(16) The high-end G pole driver of 5V SMPS
(17) The analog supply voltage input of PWM core. It needs a 1 capacitor
bypass
(18) 5V linear regulation output. It can provide 100 current. If the voltage of
OUTS end is higher than the LDO5 switch threshold, then LDO5 regulator is
turned-off, and LDO5 connects to OUT5 through a small resistance.
(19) The low-end tube G pole driver of 5V SMPS
(20) The main power input
(21) 5V SMPS output voltage detection input. When the voltage of this pin
is higher than 4.56V,it will replace the internal LDO5 output.
(22) 3.3V SMPS output voltage detection input. When the voltage of this pin
is higher than 2.91 V,it will replace the internal LDO3 output.
(23) Ground connection
(24) The low-end G pole driver of 3.3V SMPS
(25) 3.3V linear regulator output. It can provide 100mA current lf the
voltage of OUT3 terminal is higher than the LDO3 switch threshold, then
LDO3 regulator is turned-off and LDO3 connects to OUT3 through a small
resistance.
(26) The high-end G pole driver of 3.3V SMPS
(27) The inductance connected 3.3V SMPS. It’s the current detection input
of 3.3V SMPS
(28) The bootstrap capacitor connection terminal of 3.3V SMPS
The electrical features of SHDN# threshold value in the MAX8734A data

manual are described as shown in figure 9-14.
Figure 9-14: The screenshot of the description of the electrical features of

SHDN# threshold value of MAX8734A.
HDN# input threshold value level: the lowest value of the rising edge is 1.2V,
usually is 1.6V, the maximum is 2.0V.
SHDN# input threshold value level: the lowest value of the falling edge is
0.96V, usually is 1.00V, the maximum is 1.04V.
In the MAX8734A data manual, the electrical features of ON3 and ON5
threshold value is described as shown in figure 9-15.
Figure 9-15
Explanation:
ON3 and ON5 input voltage: when its less than0.8V, .the switching power
supply is turned off.
ON3 and ON5 input voltage: when it is 1.7~2.3V, delays start.
ON3 and ON5 input voltage: when it’s higher than 2.4V, opens directly.
In the MAX8734A data manual, the electrical features of over-voltage
protection threshold value described as shown in figure 9-16. When the output
voltage is higher than the set voltage to a certain value, then it will start the
over-voltage protection: the minimum value is 8%.usually is 11%, the
maximum value is 14%. For example, sets to be 3.3V, achieves 3.3+3.3*11% =
3.663V, then the chip to protect.
Figure 9-16: The screenshot of the description of the electrical features of the
over-voltage protection in the MAX8734A data manual.
In the MAX8734A data manual, the electrical features of the output under-
voltage protection threshold value described as shown in figure 9-17.If the
output voltage can only reach 70%(the common value) of the set voltage, then it
will start the under-voltage protection.
under-voltage protection threshold value in the MAX8734A data manual
The switching circuit of OUT, LDO5 and OUT3, LDO3 is shown in figure 9-18:
when OUT5/3 is higher than 4.56/2.91 V, it will replace the internal linear
voltage output.
2. Output voltage regulation
FB3/FB5 connects to the ground; you can choose a fixed output 3.3V and SV. If
FB3/FB5 connects to the resistance divider between OUT3/OUT5 and the
ground, then it can adjust the output in the range of 2~5.5V.The specific
calculation formula is VOUT=VFB x (R1+R2)/R2, is shown in figure 9-19
Figure 9-18: The switching graph of OUTx and LDOx of MAX8734A
Figure 9-19: The output voltage regulation diagram of MAX8734A
The typical application diagram is shown in figure 9-20.
3. General workflow
First,V+ inputs, V+ through the resistance divider input or the high level sent by
the external acts the open for SHDN#,MAX8734A will produce LDO5,the
internal structure is shown in figure 9-21.
Figure 9-20: The typical application diagram of MAX8734A
Figure 9-21: The internal block diagram of MAX8734A
LDO5 supplies power to VCC, is shown in figure 9-22. After VCC input being
sent MAX8734A, the chips produce 2V reference voltage REF, is shown in
figure 9-23.
Figure 9-22: The relationship between LDO5 of MAX8734A with VCC
Figure 9-23: The production of the reference voltage of MAX8734A
After REF being stable, outputs the linear voltage LDO3 of 3.3V.The timing
sequence waveform of V+, LDO5, LDO3 is shown in figure 9-24.
Figure 9-24: The timing sequence of the linear voltage of MAX8734A

ON5 connects VCC,ON3 connects REF, is shown in figure 9-25,so,the chip
produces PWM power supply of 5V first, after being stable, then produces
PWM power supply of 3.3V.
FB3 and FB5 are connected the ground, is shown in figure 9-26,chooses the
fixed output 3.3V and 5V.After all outputs being stable, the chip open drain
outputs PGOOD finally, is pulled up by the VCC through look.
Figure 9-25: The origin of the opening signal
Figure 9-26: FB setting
4. Control timing relationship (Power-up Sequencing)

The original of MAX8734A control timing relationship in English is shown in
table 9-2.
Table 9-2: MAX8734A Power-Up Sequencing

Explanation:
If SHDN# is low level, then, no matter what ON3 and ON5 is, the linear 5V,
linear 3V, 5V switching power supply and 3V switching power supply will be
closed, there is no output.
If SHDN# is higher than 2.4V, and ON3 and ON5 are low level, the linear 5V
and linear 3V will be opened (the linear 3V will start after REF being stable),
5V and 3V switching power supply are closed.
If SHDN# is higher than 2.4V, ON3 and ON5 are high level, LDO5, LDO3, 5V
switching power supply and 3V switching power supply will be opened, there is
a voltage output.
If SHDN# is higher than 2.4V, ON3 is low level, ON5 is high level, the linear
5V, the linear 3V and 5V switching power supply are opened, and 3V switching
power supply is closed.
If SHDN# is higher than 2.4V,ON3 is high level,ON5 connects REF pin, the
linear 5V,the linear 3V and 3V switching power supply are opened,5V
switching power supply will start after 3V being stable.
If SHDN# is higher than 2.4V,ON3 connects REF pin,ON5 is high level, the
linear 5V,the linear 3V and 5V switching power supply are opened,3V
switching power supply will start after 5V being stable.
If SHDN# is higher than 2.4V, ON3 is high level, ON5 is low level, the linear
5V,the linear 3V and 3V switching power supply are opened,5V switching
power supply is closed.
9.2.2 Analysis of TPS51125

TPS51125 is an economical and efficiency dual channel synchronous buck
controller produced by TI in the US to use for the standby voltage of the laptop.
The voltage is 5.5~28V,the output voltage is 2~5.5V adjustable, with 5V and
3.3V two path of 100mA linear voltage output and 2V reference voltage output
with internal error l%, integrates the over-voltage, under-voltage and over-
current protection, with the function of over- heat protection. It provides VCLK
output of 270 kHz to use to drive the external bootstrap circuit, in the case of no
reduction in the working efficiency of the main converter to generate the gate
drive voltage for the rear power conversion switch. TPSS 1125 supports
efficient, fast transient response and provides a combination of enable signal.
Out-of-Audio™ mode light load operation realizes low noise, and its efficiency
is higher than the traditional mandatory PWM.
The introduction of the pin definition and the common pin of TPS51125 is
Figure 9-27: The name of the pin of TPS51125 (the top view)
1. The definition of TPS51125

Table 9-3: The pins definition of TPS51125
(Pins) ---------- (Descriptions) of TPS51125
(1) Channel 1 open and current limit set pin. The direct grounding closes the
output, sets the threshold value of the over-current through the resistance
grounding
(2) the feedback of channel 1
(3) 2V reference voltage output
(4) the frequency setting
(5) the feedback of channel 2
(6) channel 2 open and current limit pin. The direct grounding closed the
output, sets the threshold value of the over-current through the resistance
grounding
(7) channel 2 output voltage detection. The function: (1) voltage detection; (2)
is used to replace the linear voltage
(8) the linear voltage output of 3.3V
(9) the starting pin of channel 2, boot-strap terminal
(10) the top tube drive of channel 2
(11) the phase pin of channel 2.Function: (1) the top tube conducts the loop;
(2) the current detection
(12) the down tube drive of channel 2.
(13) the main starting signal. Function: (1) open the linear when its vacant,
ready to open VCLK and PWM; (2)only open the linear when through the
resistance grounding, close VCLK and ready to open PWM; (3)direct grounding,
close the whole chip.
(14) PWM mode and pulse mode select pin
(15) ground connection
(16) the main power supply input, is the origin of the linear voltage power
supply
(17) the linear voltage output of 5V
(18) the frequency output of 270 kHz, is used for the boot-strap circuit of
15V|
(19) the down tube drive of channel 1
(20) the phase pin of channel 1 .Function; (1) the top tube conducts the loop;
(2) the current detection
(21) the top tube drive of channel 1
(22) the starting pin of channel 1, the boot-strap terminal

(23) the power good output, open drain output
(24) the voltage detection of channel 1 .Function: (1)voltage detection;(2)is
used to replace the linear voltage
In the TPS51125 data manual, the threshold value of EN0 described as shown in
figure 9- 28:when the voltage of EN0 is less than 0.4V,the chip will be closed;
when the voltage of ENO is higher than 0.8V,opens the linear and closes VCLK;
when the voltage of EN0 is higher than 2.4V,opens the linear and VCLK.
Figure 9-28: The screenshot of the description of electrical features of EN0

threshold value in the TPS51125 data manual
In the TPS51125 data manual, the threshold value of ENTRIP# described as

shown in figure 9-29: the minimum value of the turn-off level threshold value
of ENTRIP1 and ENTRIP2 is 350mV, the general value is 400mV, the
maximum value is 450mV; the minimum value of the hysteresis is 10mV,
which means that the minimum value of the open level is 360mV, the general
value is 30mV, that is 430mV, the maximum value is 60mVthat is 510mV.
Figure 9-29: The screenshot of the description of the electrical features of EN

pin threshold value of TPS51125
Figure 9-30: The equivalent circuit of the ENTRIPx in the chip
TPS51125 produces REF first, then produces VREG*, is shown in figure 9-

31,after EN being produced, VIN converts to be VREF first, then VREF is input
to the inverted input terminal of the comparator of VREG5 and VREG3,controls
the production of VREG5 and VREG3. In the TPS51125 data manual, the
electrical features of VCLK described as shown in figure 9-32: VCLK is the
waveform of 270 kHz, is 4.92V in the high level, and is 0.06V in the low level
(the typical value).
Figure 9-31: The internal schematic diagram of the production of VREF and
VREG* in the TPS51125 data manual

VCLK in the TPS51125
The schematic diagram of the boot-strap of TPS51125 VCLK is shown in

figure 9- 33.First,VCLK is low level,VO1 charges Cl through DO,5V.When
VCLK comes,4.92V add 5V(ignore the diode voltage drop) is IOV. The voltage
of 10V flows through Dl and C3 voltage rectifier filter, then charges C2 through
D2.Add again is 15V,outputs 15V(the measured voltage is between 12~ 14V)
through D4 and C3 rectifier filter.
Figure 9-33: The boot-strap circuit of 15V
2. The open signal control relationship

The original table in English of the open signal control relationship of
TPS51125 is shown in figure 9-4.
Table 9-4: The signal control relationship of TPS51125 (Enabling State)
Explanation:
When EN0 is ground connection, no matter what the state of ENTRIP1 and
ENTR1P2 is, VREF, VREG5, VREG3, channel 1, channel 2 and VCLK are
closed.
When EN0 is ground connection through the resistance, and ENTRIP1 and
ENTRIP1 are low level, VREF, VREG5, VREG3 are opened, channel 1,
channel 2, VCLK are closed.
When EN0 is ground connection through the resistance, ENTRIPl is high,
ENTRIP2 is low, channel 2 and VCLK are closed, others are opened.
When EN0 is ground connection through the resistance, ENTRIPl is low,
ENTRIP2 is high, channel 1 and VCLK are closed, others are opened.
When EN0 is ground connection through the resistance, ENTRIPl and
ENTRIP2 are high, VCLK is closed, and others are opened.
When EN0 is vacant, ENTRIPl and ENTRIP2 are low, two channels and VCLK
are closed, others are opened.
When EN0 is vacant, ENTRAP1 is high, ENTRIP2 is low, only channel 2 is
closed, and others are opened.
When EN0 is vacant, ENTRIPl is low, ENTRIP2 is high, channel 1 and VCLK
are closed, others are opened.
When EN0 is vacant, ENTRIP 1 and ENTRIP2 are high, all of them are opened.
9.2.3 Analysis of RT8206A/RT8206B

Analysis of RT8206A/RT8206B RT8206A/RT8206B is the standby power
supply chip produced by RichTek, the internal of the chip includes a linear
voltage regulator module, which provides the output of 5V 70mA.It can provide
a fixed output the adjustable voltage of 3.3V and 5V or 2V to 5.5V.The range of
the main power supply input:6~25V.
1. The introduction of the pin definition and the common pin

The top view of the pin name of RT8206A/RT8206B is shown in figure 9-34.
Figure 9-34: The pin name of RT8206A/B (the top view)
The definition pin function of RT8206A/B is shown in table 9-5.
Table 9-5: The pin definition of RT8206A/B (Functional Pin Description)
(Pins)------------ (Description) of RT8206A/B

1 2.0V reference voltage output terminal
2 the switching frequency setting terminal, connects VCC (200kHz/250kHz),

connects REF(300kHz/375kHz),connects GND (400kHz/500kHz)
3 the switching power supply input, connects the capacitor of 1 u F directly
with the ground
4 LDO module open signal input, in the high level, LDO/REF is
opened, in the low level, LDO/REF is closed
5 the vacant pin
6 the input of the chip main power supply
7 5V 70mA LDO voltage output, after the system power supply 5V being
produced, LDO module is closed, and through internal switch of 1.5 converts
to 5V power supply produced by external SMPS
8 the vacant pin
9 the voltage output by connecting 5V SMPS.is used to convert LDO voltage
output
10 SMPS 1 output voltage detection
11 SMPS1 feedback input. When FB1 connects to VCC or the ground wire,
SMPS 1 is the fixed output 5V voltage mode; when FBI connects to the
resistance partial pressure between VOUTl and the ground, you can set the
output voltage to be 2~5.5V
12 SMPS1 output current threshold setting
13 SMPS1 power good signal output, when SMPS1 output voltage is less
than the standard 7.5%,this signal becomes to be the low level
14 SMPS1 enable signal input. If EN1 is high level, SMPSl is opened, if its
low level, SMPS 1 is closed. If connects to REF,SMPS1 is opened after SMPS2
working
15 high-end OSFET driver signal output terminal
16 the connecting end of SMPS1 output inductance
17 the connecting end of SMPS 1 boost capacitor
18 the output terminal of low-end MOSFET driver signal
19 the input terminal of 5V power supply

20 the connecting end of 14V boost feedback; (RT8206B) is vacant pin
21 ground terminal
22 ground terminal
23 the output terminal of low-end MOSFET driver signal
24 the connecting end of SMPS2 boost capacitor
25 the connection of SMPS2 output inductance
26 the output terminal of high-end MOSFET driver signal
27 the input terminal of SMPS2 enable signal
28 the output terminal of SMPS2 power good signal
29 SMPS working mode setting end. Connect the ground: custom mode.
Connect REF: ultrasonic mode. Connect VCC: PWM mode
30 SMPS2 output voltage detection
31 SMPS2 output current threshold setting
32 SMPS2 feedback input. When connects FB2 to VCC or the ground
wire,SMPS2 is the fixed output 3.3V voltage mode .connects FB2 to the
resistance partial pressure between VOUT2 and the ground, you can set the
output voltage to be 2~5.5V
In the RT8206 data manual, the threshold value of ENx and ENLDO described
as shown in figure 9-35.
Figure 9-35: The screenshot of the description of the electrical features of ENx
and ENLDO threshold value of RT8206
The explanation is below:
When ENx is less than 0.8V,closes SMPS; between 1.8~2.3V,delay starts; when
its higher than 2.5V,opens SMPS.
ENLDO, the minimum value of the rising edge(from low level to high level) is
1.2V,the typical value is 1.6V,the maximum value is 2.0V.
ENLDO, the minimum value of the falling edge(from high level to low level) is
0.49V,the typical value is IV. the maximum value is 1.06V.
2. Control timing sequence
The original in English of control timing sequence of RT8206A/RT8206B is

shown in table 9-6.
Table 9-6: The control timing sequence of RT8206A_B
Explanation:
When ENLDO is low, no matter what the state of EN1 and EN2 is, LDO and
3V, 5V switching power supply is closed.
When ENLDO is high lever more than 2V.EN1 and EN2 are low level, LDO is
output after REF being stable, 5V, 3V switching power supply are closed.
When ENLDO is higher level more than 2V, EN1 is low, EN2 connects REF
pin, LDO is output after REF being stable, 5V, 3V switching power supply are
closed.
When ENLDO is high level more than 2V, EN1 is low, EN2 is high XDO is
output after REF being stable, 5V switching power supply is closed, 3V
switching power supply is opened.
When ENLDO is high level more than 2V, EN1 connects REF pin, EN2 is low,
LDO is output after REF being stable, 5V, 3V switching power supply are
closed.
When ENLDO is high level more than 2V, EN1 connects REF pin, EN2 also
connects REF pin, LDO is output after REF being stable, 5V, 3V switching
power supply are closed.
When ENLDO is high level more than 2V,EN1 connects REF pin,EN2 is high,
LDO is output after REF being stable,3V is opened directly,5V is output after
3V being stable.
When ENLDO is high level more than 2V, EN1 is high, EN2 is low, LDO is
output after REF being stable, 5V is opened, 3V is closed.
When ENLDO is high level more than 2V, EN1 is high, EN2 connects REF pin,
LDO is output after REF being stable.SV is opened directly, 3V is output after
5V being stable.
When ENLDO is high level more than 2V, EN1 is high, EN2 is also high, LDO
is output after REF being stable, 5V, 3V are opened directly.
9.3: Analysis of The Memory Power Supply

Chip
9.3.1 Analysis of ISL88550A

Analysis of ISL88550A Used for the power supply chip ISL88550A of the
memory power supply, it can output one path of PWM (the memory main
power supply) and two path of LDO (the memory REF power supply and VTT
power supply).
1. The introduction of the pin definition and common pin

The name of the pin of ISL88550A is shown in figure 9-36.
Figure 9-36: The name of the pins of ISL88550A (the top view)
Table 9-7: The table of the pins definition of ISL88550A
(Pins) --------- (Description) of ISL88550A

1 frequency selection: TON connects AVDD (200 kHz), when it¡®s in vacant,
connects REF (450 kHz), connects the ground (600 kHz)
2 over-voltage/under-voltage protection control input. Connects AVDD (open

the over- voltage protection and the discharging mode, open the under-voltage
protection).When It’s in vacant (open the over-voltage protection and the
discharging mode, close the under-voltage protection), connects REF (close the
over-voltage protection and the discharging mode, open the over-voltage
protection), connects the ground (close the over-voltage protection and the
discharging mode, close the under-voltage protection)
3 2V reference voltage output
4 the limiting current setting
5 PWM power good
6 LDO power good
7 when STBY# is low, VTT will be closed, is the high resistance state
8 soft start
9 VTT voltage detection input
10 the terminal reference voltage, the value is the same with VTT
11 ground connection
12 the terminal voltage output, connects to VTTS to keep it to be half of

VREFIN
13 the input voltage of VTT voltage regulator, in the application of the

memory power
supply, will usually connect it to PWM output terminal
14 the external reference voltage input, is used to adjust VTT and VTTR, the
voltage output by them is the half of REFIN
15 the feedback of PWM. When it connects AVDD, fix output 1.8V,when

it connects the ground, fix output 2.5V.If its adjusted by the resistance partial
pressure, it can output the voltage between 0.7~3.5V
16 the output voltage detection input of PWM
17 the main power supply input the range of 2~25V
18 the top tube driver of PWM
19 the phase pin of PWM. the function of the top tube drive loop and the
current detection
20 the boot-strap terminal

21 the down tube driver of PWM
22 the power supply of the chip .the origin of the driving force of the down
tube
25 the working mode setting. when it connects AVDD, low noise forced
PWM mode, when connects the ground, jump pulse mode
26 the main power supply of LDO and PWM
27 turn-off the control input A, the rising edge clear fault latch, connects the
high level open chip
28 the test pin
The control relationship between SHDN# and STBY# of ISL8850A is shown in

table 9-8.
Table 9-8: The open signal control relationship of ISL88550A
Explanation:
When SHDNA# connects the ground, no matter what the state of STBY# is,
PWM,VTTR are closed, VTT is also closed(discharge to 0V).
When SHDNA# connects AVDD,STBY# connects the ground, PWM and
VTTR are opened, VTT will be closed(the high resistance state).
When SHDNA# and STBY connects AVDD,PWM,VTT,VTTR are opened.
2. The typical application

The typical application of ISL88550A is shown in figure 9-37.
Figure 9-37: The typical of ISL88550A
The specific working process:

1) 5V supplies power to 22V, 4.5 ~25V supplies power to 17 pin.
2) 3 pin produces 2V reference voltage.
3) The south bridge sends the high level of SLP_S5#SLP_S4#to 27-pin
SHDNA#
4) PWM is opened, outputs VDDQ, 1.8V (FB connects AVDD, sets to be the
fixed output 1.8V).
5) VDDQ is returned to OUT detection, the chip outputs POK 1; at same time,
VDDQ supplies power to REFIN.
6) Output VTTR, the voltage is the half of REFIN, that is 0.9V(as shown in
figure 9- 39,after REFIN entering the chip, through two of 10kΩ resistance
series divides into the voltage to be 0.9V,then outputs VTTR with 0.9V through
voltage follower).At the same time, the chip outputs POK2.
7) The South Bridge sends the high level of SLP_S3# to STBY# pin.
8) Outputs a voltage from the external to 13 pin VTTI as the power supply of
VTT regulator.
9) Outputs VTT, the voltage is the half of REFIN, 0.9V.
Figure 9-38: The screen shot of the internal relationship of REFIN and VTT,
VTTR of ISL88550A
9.3.2 Analysis of RT8207

Another common memory power supply chip RT8207,is also responsible to
output three paths of power supply: the memory main power supply, the
memory REF voltage, the memory VTT voltage, the pin definition is shown in
table 9-9.
Table 9-9: The pin definition of RT8207 (Functional Pin Description)
(Pins) ----------- (Descripton) of RT8207

1 the ground pin of the internal integrated VTT regulator
2 the voltage detection input pin of VTT output
3 the ground connection

4 output discharging mode setting pin. Connect to VDDDQ trace discharge;
connect to the ground, the non-trace discharge; connect to VDD, not discharge
5 VTTREF voltage output pin, is sent to the memory reference voltage

6 the diode emulation mode open pin. Connect to VDD to open the diode
emulation mode; connect to the ground, is always working in the forced CCM
mode
7 the vacant pin
8 the reference input pin of VTT and VTTREF. The output voltage of VTT
and VTTREF is the half of VDDQ. If FB connects VDD or GND,VDDQ can be
acted as the output voltage feedback input pin
9 VDDQ (PWM) output voltage-setting pin. Connects to GND, outputs 1.5V;
connects to VDD, outputs 1.8V; it can set the adjustable output voltage between
0.75 ~ 3.3V through the resistance partial pressure
10 SLP_S3# sent by the South Bridge, is used to control the output of VTT
11 SLP_S5# sent by the South Bridge, is used to control the output of PWM
and VTTREF
12 connects to VIN through a resistance. Sets the frequency
13 the open drain output pin of the power good, it means that PWM control
output VDDQ voltage has normal
14 the power supply
15 the power supply
16 connects to VDD through a resistance, sets the limited current
17 the vacant pin
18 the ground connection (the ground connection of the driver of the down
tube)
19 the down tube drive
20 the phase pin; it can be used as the current detection pin: detects the
current through the detection of the pressure drop of the down tube.
21 the top tube drive
22 the boot-strap pin
23 the power supply of the regulator of VTT
24 the output of VTT
The typical application of RT8207 is shown in figure 9-39.
Figure 9-39: The typical application of RT8207

The original in English of the control logical relationship between S3 and S5 of
RT8207 is shown in table 9-9.
Table 9-9: The control logic relationship of RT8207
Explanation:
In the S0 state,S3 is high,S5 is high ------VDDQ,VTTREF,VTT are opened.

In the S3 state,S3 is low,S5 is high ------VDDQ and VTTREF are opened, VTT
is closed(the high resistance state).
In the S4/S5 state, S3 and S5 are low ------VDDQ,VTTREF and VTT are
closed(discharge to the ground).
The working process of RT8207 is shown in figure 9-40.
Figure 9-40: The working process of RT8207
9.4: Analysis of The Bridge/Bus Power Supply

Chip
The bridge power supply and the bus power supply chip is relatively simple, is
usually used a single PWM or dual PWM controller.
9.4.1 Analysis of the single PWM controller RT8209
The common single PWM controller RT8209 can be used for the bridge power
supply, bus power supply, the memory main power supply and other circuits.
Note: RT series chip body usually do not have a real model, only the product
code. For example, RT8209BGQW, the chip body is only the word "A0=", is
shown in figure 9- 41.About the actual type recognition of this series chip, you
need to download the packaging file of RT chip, at present the latest version of
the new efferent is 2009,the name of this field is
Richtek_Marking_Code_090424.PDF, you can download in their official
website.
Figure 9-41: The marking code of RT8209 series chip body
The definition of the RT8209 series chip is shown in figure 9-42.
Figure 9-42: The pin definition of RT8209 series chip (the top view)
The important pin: in addition to the PWM related pin, the power supply pin
VDD,VDDP are usually connected to 5V,CS is the current limit set, TON is the
frequency setting, the definition of the open pin EN/DEM is the start using/the
diode emulation mode control input(the threshold value of EN/DEM in RT8209
data manual described as shown in figure 9-43).Connected to VDD, is the diode
emulation mode, connected to the GND turn off chip, is CMM(the continuous
current) mode when its vacant. Generally, It¡®s the vacant state during working,
and is the ground state when it’s turned off.

EN/DEM pin threshold value in RT8209 data manual
The application of RT8209A/B/C is shown in figure 9-44,the description of the

working process is below.
1) The power supply inputs 4.5 ~5.5V to VDD,VDDP pin, pulls up TON pin
through the resistance to set the frequency, and pulls down CS pin through the
resistance to set the limited current.
2) EN inputs the high level. Or the external circuit is disconnected, makes it to

be vacant.
3) Starts PWM, outputs VOUT.

4) Detect the voltage from VOUT pin.
5) Open drain output PGOOD, is pulled up to be the high level by VDDP.
Figure 9-44: The application of RT8209A/B/C
9.4.2 Analysis of The Dual PWM Controller TPS51124
Figure 9-45
The input voltage range of the dual PWM power supply chip TPS51124 which
is commonly used in the bridge power supply and the bus power supply is from
3V to 28V, and the output voltage range is from 0.76V to 5.5V.
The pin name of TPS51124 is shown in figure 9-45.
The explanation of the important pin: 15 pin and 16 pin are the power supply,4
pin is the frequency selection, from 5 pin to 14 pin, are the first path of PWM
power supply control, the 1 pin,2 pin and from 17 pin to 24 pin, are the second
path of PWM power supply control, TRIP1/TRIP2 sets respectively the over-
current limit of the two path of PWM.EN1/EN2 opens respectively the two
path of PWM.
In the TPS51124 data manual, the power supply range of V5IN and
V5FIIT described as shown in figure 9-46: the power supply range of
V5IN and V5FIIT is from 4.5V to 5.5V.
Figure 9-46: The screenshot of description of the power supply range of V5IN
and V5FIIT in the TPS51124 data manual
In the TPS51124 data manual, the threshold value of EN described as shown in

figure 9- 47,the lowest threshold value of EN is 1 V ,is usually 1.3V,the
maximum is 1.5V.
Figure 9-47: The screenshot of the description of the electrical feature of EN pin
threshold value in the TPS51124 data manual
In the TPS51124 data manual, the frequency setting described as shown in

figure 9-48.
Figure 9-48: The screenshot of the description of the frequency setting of

TPS51124
When TONSEL is the ground connection, the first path of PWM works in 240
kHz, the second path of PWM works in 300 kHz.
When TONSEL is vacant, the first path of PWM works in 300 kHz, the second
path of PWM works in 360 kHz.
When TONSEL connects V5FIIT, the first path of PWM works in 360 kHz, the
second path of PWM works in 420 kHz.
In the TPS51124 data manual, the electrical features of FB pin described as

shown in figure 9-49.1n the SKIP mode, the reference value of FB voltage
regulation is 764mV,in the PWM mode, the reference value is 758mV.the error
precision is about 0.9% in 25oC,the error precision is about 1.3% in 0~85oC,and
the error precision is about 1.6% in -40~85oC.
Figure 9-49: The screenshot of the description of the electrical features of FB

pin reference value in the TPS51124 data manual
The typical application of TPS51124 is shown in figure 9-50.
Figure 9-50: The typical application of TPS51124
The description of the working process is below.

1) The power supply outputs 4.5~5.5V to 15 pin and 16 pin.
2) EN1 or EN2 input
3) Starts the first path of PWM or the second path of PWM.
4) Detect the voltage from VO1 or VO2.
5) Open drain output PGOOD1 or PGOOD2.
9.5: Analysis of CPU Core Power Supply

CPU generally requires a number of power supply, for example, CPU of 478
needs three kinds of power supply, the first generation 13/15/17 needs five
kinds of power supply, but only VCC pin is the core power supply. In this
section, we mainly explain the working principle of several common CPU core
power supply chip.
9.5.1 The features of CPU VCORE power supply
The multiphase output is that the output of multiple current sources are
connected together, supplies power to CPU, which meets the demands of CPU
large current. The real object of two-phase CPU power supply is shown in
figure 9-51.
Since the working voltage required by CPU at the different times is different, so
it needs the control way to adapt automatically the requirements of the different
CPU on the voltage, that is, the VID control of the output voltage.
VID is the voltage identification technology, loaded with different CPU, it will
produce the different voltage.
VID can be divided into PVID (parallel VID) and SVID (serial VID).
Figure 9-51: The real object of two-phase CPU power supply
AMD early and before Intel 5 series chipset (HM55, etc), are all belong to
PVID. The basic principle is that, sets 4~8 VID recognition pin on the CPU, and
through the high and low level values preset in these recognition pin, to form a
group of VID recognition signal, when its high level on VID recognition pin,
then is the 1 state of the binary, and when it’s the low level on the VID
recognition pin, is the 0 state of the binary according to the combination of
these 1 and 0,forms the group of the most basic machine language signal, and is
transmitted to the power management chip in the CPU power supply circuit by
CPU, according to the VID signal, the power management chip adjusts the duty
cycle of the output pulse signal, which forces the DC voltage output by CPU
power supply circuit to be consistent with the value represented by pre-set VID.
Intel company developed the corresponding voltage regulation module design

specifications for each CPU produced at different time, starts from the Prescott
core microprocessor, the voltage regulation specification used VRD (Voltage
Regulation Down) to name, in the laptop, uses the Voltage Mobile Positioning,
the VID digit, the voltage regulation accuracy and the voltage regulation range
in the various version of the power supply design specification are not the same.
VID with this mode can "cheat" the CPU to come out by loading the dummy
load. After loading the dummy load, connects one or more VID signal of
VIDO~VID7 to the ground, at this time,VIDO~VID7 pin of the power IC gets
the new voltage combination, according to this different combination, the power
IC will control to send the corresponding voltage. That is to say, let CPU '
power supply chip mistakenly assume that the true CPU is loading.
Starting from AM2+ CPU,CPU contains two pans of the voltage(AMD calls it
to be Dual-Plane),one is the core voltage of CPU, one is the voltage of the
North bridge integrated in CPU.A group of parallel VID control modules cannot
asynchronous control these two voltages at the same time. Unless provides a
group of parallel VID again to control the voltage of the North bridge in CPU,
but this will be more complex. So AMD launched a new generation of voltage
regulation module specification, using serial VID (SVID) mode to solve this
problem. Serial VID is a type of bus protocol. From the hardware point of view,
the required external interface is from the previous VIDO ~VID5 a total of 6
becoming into SVC (serial clock), SVD (serial data), it's very simple. However,
because the serial VID is the bus-working mode, so it needs the cooperation of
the software. But it also means that the operability adjusted latter will be
stronger. Most of the previous AMD motherboard used PVI/SVI compatible of
PWM controller in order to compatible with AM2/AM2+/AM3.
Intel integrated the display core in Core i3/i5/i7 matched with 5 series platform,
in order to control these two groups of power supply better, so provides two
groups of PVID interface to control respectively the core voltage of CPU and
the display core voltage. These two groups of voltages are accord with the
specification of Intel VRD 11.1.which is more complex.
Starting from 6 series platform, Intel imports VRD12 specification, that is the
serial VID mode, it’s exactly the same with AMD SVI mode. There are three
lines of SVID of Intel platform: SVD (serial VID data), (SVC serial VID clock),
ALERT# (warning signal).
9.5.2 Analysis of MAX8770

MAX8770 is the control chip produced by MAXIM company, which is used for
the CPU core power supply, in accordance with the IMVP-6 specification, the
main features are as follow.
• Support two-phase CPU power supply.

• Support 7 bit VID, the output voltage is adjusted from 0V to 1.5000V.
• Support for dynamic phase adjustment and sleep.
• Integrated driver 1C.
• With power, ready (PWRGD) output and clock enable (CLKEN#) output.
• With the power monitoring and over-heat protection.
• Support 4~26V input voltage range.
• Output over-voltage protection. The pin name of MAX8770 is shown in
figure 9-52, the real object of MAX8770 is shown in figure 9-53.
Figure 9-52: The pin name of MAX8770
Figure 9-53: The real object of MAX8770

The definition of MAX8770 is shown in table 9-11.
Table 9-11: The pin definition of MAX8770
(Pins) -------- (Description) of MAX8770

l. the output of the clock enables logic signal. When the output voltage
detected from FB pin reaches the specified value, this pin outputs the effective
logic low level.
2. the power good signal of the open drain output. When the output voltage
detected from FB pin reaches the specified value, this pin open drain outputs the
high level.
3. this low voltage logic signal and DPRSLPVR commonly set the power
mode. If PSI# is low, then enter the PWM mode of N-l phase. When PSI# is
high, then recovery the PWM mode of N phase.
4. power monitor output
5. the open drain output pin of the internal comparator. When the voltage of
THRM terminal is less than 1.5V (30%VCC),VRHOT# is pulled low. It’s the
high resistance at shutdown
6. the input terminal of the internal comparator. Connects one end of the
thermistor (usually is NTC) to the ground, and another end to THRM, and
through a resistance to VCC at the same time. By selecting the proper device, at
the required temperature, the voltage of THRM end is reduced to less than 1.5V.
7. the voltage slew rate(is the rate of voltage swing)control pin. TIME
connects a resistance to the ground, used to set the internal slew rate. The
application of the voltage slew rate contains: the chip enter or exit the pulse
interval mode, the chip enter VID MODE from BOOTMODE. For the soft start
and shutdown process, the chip reduced automatically the slew rate to 1/8.
8. the switching frequency setting pin. The switching frequency is set by a
resistance connecting to the power supply end and the TON end.
9. the capacitor connection of the voltage integrator.
10. the current balance compensation
11. 2.0V reference voltage output, through a maximum of 1uF capacitor
bypass to the ground. REF can provide 500 uA current to the external loads.
12. the feedback input. The external resistance capacitance element is used
for detecting the output voltage.
13. the negative of the inductance input end of the feedback bypass. Connects
to GND of the load end in general.
14. the positive input end of the second phase output current detection. This
pin must be connected to the positive end of the output current sense resistor.
Connects the PIN pin to VCC, the second phase is closed.
15. The negative input end of the second phase output current detection. This
pin must be connected to the negative end of the output current sense resistor.
Under the case of the DC inductance of the output inductance being used as the
output current detection resistance, this pin is connected to the output filter
capacitor
16. the negative input end of the first phase output current detection. This pin
must be connected to the negative end of the output current sense resistor.
Under the case of the DC inductance of the output inductance being used as the
output current detection resistance, this pin is connected to the output filter
capacitor
17. the positive input end of the first phase output current detection. This pin
must be connected to the positive end of the output current sense resistor.
Connects this PIN pin to VCC, the first phase is closed
18. simulated ground
19. the controller power supply pin. Connects the voltage end of
4.5~5.5V,through a minimum of 1uF bypass capacitor to connect to the ground
20. the boost resistor connection end of the second phase. It can set up the
open signal for the top tube on the DH2 through this signal, when the down tube
is turned on, the internal switch between VDD and BST2 charges the boost
capacitor
21. the output end of the top tube drive signal of the second phase. The
voltage values is changed between LX2 and BST2.Its low in shutdown.
22. the connection end of the output inductance of the second phase. It sets
up the opening voltage on the DH2 for the top tube, acts as the input end of the
zero crossing comparator of the second phase at the same time
23. The second phase power ground. It’s the ground end ofDL2.It acts as the
input end of the zero crossing comparator of the second phase at the same time.
24. The output end of the down tube drive signal of the second phase. The
voltage value is changed between VDD and GND.DL2 is high in the shutdown.
When the output voltage is abnormal, it has been forced to be high. It also is
low in the small load mode, until detecting the inductance current 9PGND2-
LX2) zero crossing
25. The power supply pin of the down tube drive of each phase. It acts as the
charging source of the boost capacitor of each phase at the same time. This pin
connects to the voltage source of 4.5~5.5V
26. the output end of the down tube drive signal of the first phase. The
voltage values are changed between VDD and GND.DL1 is high in the
shutdown. When the output voltage is abnormal, it has been forced to be high. It
also is low in the small load mode, until detecting the inductance current
(PGND1-LX1) zero crossing
27. the power ground of the first phase. Its the ground end of DLl. It acts as
the input end of the zero crossing comparator of the first phase at the same time.
28. the connection end of the output inductance of the first phase. It sets up
the opening voltage on DH1 for the top tube, acts as the input end of the zero
crossing comparator of the first phase at the same time
29. the output end of the top tube drive signal of the first phase. The voltage
values is changed between LX1 and BSTl. Its low in shutdown
30. the connection end of the boost resistance of the first phase. It can set up
the open signal on DH1 for the top tube through this signal, when the down tube
is opened, the internal switch between VDD and BST1 charges the boost
capacitor
31~37. the input end of the low voltage VID digital signal.D0~D6 does not
pull up in IC. The digital logic signal is directly connected to the relevant
interface of CPU. The output voltage is controlled by VID. When VID is high,
its turned off. When VID changes from high to other value, IC starts to start the
timing sequence immediately
38. the voltage open signal. When it connects VCC, uses the default mode.
When it connects GND, the chip enters into the close mode. During starting. the
output voltage ramp slowly to the start voltage(the voltage slew rate is 1/8).
When the voltage is closed, uses the same voltage slew rate to decline. The
voltage of SHDN# pin can't be more than 13V,at this time, OVP and UVP
protection of the chip internal are closed
39. The input end of the depth sleeps control. This signal and PSI# signal set
commonly the power mode.
40. The deep sleep awaken signal. When this signal is low, it means that CPU
is in a deep sleep state.
In the MAX8770 chip, the combination of DPRSLPVR and PSI# sets the power
mode is shown in figure 9-54.
Figure 9-54: The screenshot of the original of combination DPRSLRVR and

RSI# setting in the information of MAX8770 chip
When DPRSLPVR is high, PSI# is low, the chip working mode is that the
current is very small, the 1 phase jump pulse.
When DPRSLPVR is high, PSI# is high, the chip works in the 3A small current
mode, the 1 phase jump pulse.
When DPRSLPVR is low, PSI# is low, the chip works in the PWM mode of 1
phase, the current is moderate.
When DPRSLPVR is low, PSI# is high, the chip works in the PWM mode of
the full phase, the maximum current output.
The over-voltage protection: IC will detect if the output voltage meets the OVP
standard or not in real. When the output voltage is higher than the value of the
output voltage current VID corresponding 300mV(the typical value, is shown in
figure 9-55),or is higher than 1.8V in the pulse interval mode, IC starts OVP
protection. When OVP is low in the multiphase mode(DPRSLPVR is low and
PSI# is high),IC pulls DL1 and DL2 high immediately, and pulls DH1 and DH2
low. It makes the down tube driving signal duty ratio is 100%,the down tube is
emptying the output capacitor rapidly, the using output voltage is pulled low.
over-voltage threshold value in MAX8770 data manual
The over-voltage protection when the output voltage is less than the output
voltage value 400mV(the typical value, is shown in figure 9-56) that VID
corresponding to, IC starts SHUTDOWN timing sequence and sets the fault
latch until the output voltage as low as OV. At this time, IC will be forced to
pull high DL1 and DL2, and pull DH1 and DH2 low. Pull the SHDN# voltage
clamp or VCC voltage down to less than 0.5V to clear the fault latch, and re-
activate IC.
over-voltage protection threshold value in the MAX8770 data manual
The operating voltage range of VCC and VDD is shown in figure 9-57.
Figure 9-57: The screenshot of the description of the electrical features of VCC
pin and VDD pin threshold value in the MAX8770 data manual
As shown in figure 9-58,is the screenshot of the description of the electrical
features of the key signal threshold value of MAX8770, SHDN and
DPRSLPVR are the high level(the maximum value) when its higher than
2.3V,VIDO ~ VID6, PSI and DPRSTP are the high level(the minimum value)
when its higher than 0.67V,are the low level (the maximum value) when its less
than 0.33V
key signal threshold value in the Max8770 data manual
VID voltage corresponding of 1MVP-6 specification is shown in table 9-12.
For example: when D~D0 are the low level, the output voltage is 1.5000V;when
D6 is the low level,D5~D0 are the high level, the output voltage is 0.7125V;
when D6~D0 are the high level, the output voltage is 0V.
Table 9-12: The table-1 of VID corresponding of IMVP-6
The application circuit of MAX8770 is shown in figure 9-59, several key

working conditions are indicated in the figure:
Figure 9-59: The typical application figure of MAX8770
The timing sequence of MAX8770 starting and closing is shown in figure 9-60.
Figure 9-60: The MAX8770 starting and closing timing sequence

1) First the chip gets the power supply, the internal will pull up CLKEN# to be
high level.
2) Then, the external sends the high level of the open signal SF1DN#.
3) VCORE soft starts to a certain voltage range first (the starting speed is 1/8 of
the TIME
4) Pin resistance setting the slew rate, forced PWM mode.
5) The chip starts to decode VID signal sent by CPU. VCORE starts to the
corresponding voltage set by VID.
6) After CPU soft start being normal, delays 60¦
Ìs to set CLKEN# low.
7) After CPU power supply achieving the voltage set by VID, delays 5ms to set
PWRGD high (MAX8770 has not the PHASEGD signal).
8) SHDN# changes to be low level.
9) VCORE, CLKEN# and PWRGD are turned into the invalid state, PWM
restores the forced PWM mode, VID stops decoding.
10) When there is not VCC, CLKEN# also a change to be low level, the chip is
outage.
9.5.3 Analysis of ISL6260

ISL6260 is the CPU power supply chip confirmed the IMVP-6 specification; its
main features are as follows:
• Precise multiphase kernel voltage regulator, supports for three-phase

power supply, is programmable;
• 7 bit of VID input recognition;
• Support a variety of methods of the current detection;
• Support PSI#;
• Temperature monitoring;
• Not integrated driver chip. The pin name of ISL6260 is shown in figure
9-61.
Figure 9-61: The pins name of ISL6260 (the top view)
The definition of the ISL6260 is shown in table 9-13.
Table 9-13: The pins definition of ISL6260
(Pins) ----------- (Description) of ISL6260

l. low loading current input indication; is effective in the low level.ISL6260
can be used to close the PWM2
2. the high level input means that VCCP and VCC_MCH has been normal.
this signal is the precondition of CLK_EN# and PGOOD sent by ISL6260
3. through 147k bias resistance connect the ground. set the internal
reference current
4. over-heat indication output, is effective in the low level
5. connecting to the negative temperature coefficient thermistor; As the part
of the VR_TT# circuit
6. through a single capacitor set the maximum voltage conversion rate (the
slew rate. the range of the voltage increasing within 1 s, its the time that the
square-wave voltage rising from the trough to the crest needs. the units are
usually V/s, V/ms and V/ s)
7. the over-current setting input pin
8. through the resistance connect COMP to set the switch frequency
9. the error compensation; which is connected to the output end of the
internal error amplifier
10. the feedback pin, which is connected to the inverting input end of the
internal error amplifier
11. the output of the differential amplifier
12. the voltage detection, the plus end
13. the voltage detection, the negative end
14. the output end of the internal attenuation amplifier
15. the inverting input end of the internal attenuation amplifier
16. the input end of the output voltage detection
17. the total current detection
18. the power supply input
19. grounding
20. 5V power supply input
21 . the third phase current detection
22 . the second phase current detection
23 . the first phase current detection
24. the forced continuous conduction mode enable pin(forced PWM mode) of
the driver chip
25 . the third phase PWM output

26. the second phase PWM output
27. the first phase PWM output
28~34. the voltage recognition input pin
35. the opening signal, is effective in the high level
36. the high level means that its in the deep sleep mode
37. the low level means that its in the deep sleep mode
38. the opening signal of the clock chip; is effective in the low level. After
PGD_IN and VCORE being normal, then it will output
39. 3.3V power supply of CLK_EN# circuit
40. the power good. Open drain output, it needs to be pulled up by the
external
The original screenshot of the description of the electrical features of several
key signals threshold value of ISL6260 is shown in figure 9-62,the minimum of
the rising edge threshold value of VR_ON,DPRSLPVR and PGD_IN is
2.3V,the maximum of the falling edge threshold value is IV; the minimum of
the rising edge threshold value of VK)0- VID6,PSI# and DPRSTP# is 0.7V,the
maximum of the falling edge threshold value is 0.3V.
Figure 9-62: The original screenshot of the description of the electrical features
of VR_ON and other key signals threshold value of ISL6260
As shown in figure 9-63, when all VID of ISL6260 are OV, the maximum of
the output voltage of VCC_CORE is 1.5V; when VID is 1100000, the output
voltage of VCC_CORE is 0.3V, when all VID are 1V, VCC_CORE outputs 0V.
Figure 9-63: The original screenshot of the decoding range of ISL6260VID

PGD_IN mainly controls PGOOD logic circuit, is shown in figure 9-64, after
CPU power supply being normal. The logic circuit of PGOOD needs to receive
PGD_ FN, then it will send PGOOD, and sends to the logic circuit of
CLK_EN# at the same time, the circuit of CLK_EN# must receive the power
supply of 3V3, then it will send CLK_ EN#. So, no PGD_IN will not cause no
CPU power supply it will only cause no output of PGOOD, no 3V3 will not
cause PGOOD does not output it will only cause CLK_EN# does not output low
level. The simplified application diagram and the key pin of ISL6260 are shown
in figure 9-65.
Figure 9-64: The internal logic figure of PGOOD and CLK_EN# of ISL6260
Figure 9-65: The simplified application diagram and the key pin of ISL6260
Note:
(1.) = The chip main power supply
(2.) = Temperature measurement and over-temperature instruction
(3.) = VIDs
(4.) = Sleep and Energy-saving control
(5.) = Opening (start-up)
(6.) = The voltage detection
(7.) = The condition of PGOOD
(8.) = CLK_EN# module power supply
(9.) = First phase square waveform output
(10.) = The current detection

(11.) = Second phase square waveform output
(13.) = Third phase square waveform output
(15.) = The total current detection
(16.) = Driver chip power supply
(17.) = CPU voltage output
Figure 9-66: The start timing sequence of ISL6260

The start timing sequence of ISL6260 is shown in figure 9-66.
1) The chip gets the power supply first, including VDD and VIN.
2) The high level of VR_ON sent from the external.
3) After delaying 100us, the chip starts soft start
4) VCORE to 1.2V, the starting speed is 2mV/us.
5) After VCORE starting to 1.2V and PGD_IN is high, the chip will send low
level of CLK EN#. The chip decodes VID, drives VCORE to the voltage set
by VID according to IMVP-6 standard, the starting speed is 10mV/us.
6) 7ms later, the chip outputs PGOOD signal.
9.5.4 Analysis of commonly used chip ISL95831 by HM65

mainboard
ISL95831 is the controller supported three phase CPU core power supply and 1
phase integrated graphics power supply, is mainly used for HM6x and above
platform of Intel, in compliance with the IMVP-7/VR12 specification^ TQFN
packaged, 48 pin. The main features are as follow:
• Support dual output; The first path of the voltage regulator can be
configured as 3 phase, 2 phase and single phase; the second path of the
voltage regulator supports a single phase output.
• Two path of output shared SVID control.
• Integrated three driver chips (the first path has two, the second path has
one).
• Support kinds of methods of current measurement.
• Support the over-heat and over-current protection.
The pin name of ISL9583 1 is shown in figure 9-67.
Figure 9-67: The pin description of ISL95831
The pin definition of ISL95831 is shown in table 9-14.
Table 9-14: The pin definition of ISL95831

1. this pin is connected to the COMPG by a resistance to set the switching
frequency of the voltage regulator 2(8k Ω resistance is about 300kHz)
2. the analogue output. The output current and the current of the voltage
regulator 2 forms a certain proportion
3. the open drain output pin of the power good. Indicates that the voltage
regulator 2 has normal. The external needs to be pulled up by the resistance
4,5,6. the communication bus between CPU and the power management chip.
Serial VID bus
7. the enable pin of the controller. The high level is turned on.
8. the open drain output of the power good. Indicates that the voltage
regulator 1 has normal. The external needs to be pulled up by the resistance
9. the analog output. The output current and the current of the voltage
regulator 1 forms a certain proportion
10. over-heat indication signal
11. connects the ground through a negative temperature coefficient thermistor.
used to monitor the temperature of the voltage regulator 1
12. connects this pin to COMP through a resistance to set the switching
frequency of the voltage regulator l(8k resistance is about 300kHzi
13. the output end of the error amplifier of the first path of the voltage
regulation
14. the inverting input end of the error amplifier of the voltage regulator 1
15. when the voltage regulator 1 is configured as a 3 phase, is used to detect
the current of the third phase. When its configured as 2 phase. The internal
connects the switch of FB2 and FB, is used to adjust the precision of the
compensation voltage regulator l. When its configured as 1 phase, the switch is
invalid
16. the second phase current detection of the voltage regulator 1
17. the first phase curer.: detection of the voltage regulator 1
18. the input end of the voltage detection of the voltage regulator 1
19 . the loop end of the voltage detection of the voltage regulator 1
20, 21. the input pin of the droop current detection of the first path of
regulator
22. 5v power supply 23.the power supply
24. the maximum output current of the voltage regulator 1 and VBOOT
voltage of the two path of regulator are configured by the resistance connecting
to the ground
25. the first phase boot-strap pin of the voltage regulator l. Through a
resistance connects the PHASE pin of the first phase
26.the first phase of the top tube drive signal of the voltage regulator 1
27. the first phase of the top tube driver loop of the voltage regulator
1,connects the S pole of the top tube, the D pole of the down tube and the output
inductance
28. the first phase of the down tube driver loop of the voltage regulator
1.connects to the S pole of the down tube
29 . the first phase of the down tube drive signal of the voltage regulator 1
30. the third phase of the square wave output of the voltage regulator l. When
it connects to 5V, disable the third phase
31. the power supply of the internal driver chip. connects to +5V,at least is 1
uF
decoupling capacitors
32. the second phase of the down tube drive signal of the voltage regulator 1
33. the second phase of the down tube driver loop of the voltage regulator l,
connects to the S pole of the down tube
34. the second phase of the top tube driver loop of the voltage regulator
1,connects the S pole of the top tube. the D pole of the down tube and the output
inductance
35. the second phase of the top tube drive signal of the voltage regulator 1
36. the second phase of the boot-strap pin of the voltage regulator 1.Connects
the PARSE pin of the second phase through a capacitor
37. the down tube drive signal of the voltage regulator 2
38. the top tube driver loop of the voltage regulator 2,connects the S pole of
the top tube, the D pole of the down tube and the output inductance
39. the top tube drive signal of the voltage regulator 2
40. the boot-strap pin of the voltage regulator 2.Connects the PHASEG pin
through a capacitor
41. the maximum output current and the maximum limit temperature of the
two regulators are configured by a resistance connecting the ground
42 . through a negative temperature coefficient thermistor, used to monitor the

Temperature of the voltage regulator 2
43, 44. the input pin of the droop current detection of the second path of
the regulator, when ISUMNG is connected to 5V. it will disable the second path
of the voltage regulator
45. the loop end of the voltage detection of the voltage regulator 2
46. the input end of the voltage detection of the voltage regulator 2
47. the inverting input end of the error amplifier of the voltage regulator 2
48. the output end of the error amplifier of the second path of the voltage
regulation
In the ISL95831 data manual, the screenshot of the description of the input level
threshold value of VR_ON is shown in figure 9-68,the maximum value of
VR_ON in the low level is 0.3V,in the ISL95831HRTZ,the minimum value of
VR_ON in the high level is 0.7V,in the ISL95831IRTZ,the minimum value of
VR_ON in the high level is 0.75V.

VR_ON threshold value in the ISL95831 data manual
The simplified application circuit of ISL95831 is shown in figure 9-69.
Figure 9-69: The simplified application figure of ISL95831
The configuration of PROG1 pin of ISL95831 is shown in table 9-15.
Table 9-15: The configuration of PROG1 in the ISL95831 data manual
Give some examples to explain:
When PROG l pin connects the ground through 0Ω resistance, the voltage of
Vboot is 0V. When CPU power supply outputs three-phase, two-phase and one-
phase. The maximum current are respectively 99A, 66A and 33A.
When PROG1 connects the ground through 24.15kΩ, or infinitely resistance,

the voltage of Vboot is 1.1V. When CPU power supply outputs three-phase, two-
phase and single-phase, the maximum are respectively 99A, 66A and 33A.
The configuration of PROG2 of ISL95831 is shown in table 9-16.
When PROG2 connects the ground through 0Ω resistance, the value of the over-
temperature protection of the chip is 120oC, the maximum of the output current
of the second path of the voltage regulator is 33A.
When PROG2 pin connects the ground through 24.15kΩ or infinitely resistance,
the value of the over-temperature protection of the chip is 95oC, the maximum
value of the output current of the second path of the voltage regulator is 33A.
The waveform of SVID is shown in figure 9-70.the channel 1 is SCK, the

channel 2 is SVD.
The configuration of PROG2 of ISL95831 is shown in table 9-16.
When PROG2 connects the ground through 0Ω resistance, the value of the over-
temperature protection of the chip is 120oC, the maximum of the output current
of the second path of the voltage regulator is 33A.
When PROG2 pin connects the ground through 24.15kΩ or infinitely resistance,
the value of the over-temperature protection of the chip is 95oC,the maximum
value of the output current of the second path of the voltage regulator is 33A.
The waveform of SVID is shown in figure 9-70.the channel 1 is SCK, the

channel 2 is SVD.
Table 9-16: The configuration of PROG pin in the ISL95831 data manual
The starting timing sequence of ISL95831 is shown in figure 9-71.
Figure 9-70: The waveform of SVID
Figure 9-71: The starting timing sequence of ISL95831
The starting procedure of ISL95831:

1) ISL95831 gets VDD and VIN, the chip power on reset(POR),to enter the
standby state. the threshold value of VDD is 4.5V(the maximum value),the
threshold value of VTN is 4.35V(the maximum value).
2) ISL95831 get the opening signal VR_ON, when the voltage value of this pin
reaches to 0.7V(the minimum value of ISL95831FIRTZ),starts soft start.
3) The internal DAC voltage starts to rise as the slope of 2.5mV/us
4) When DAC voltage rises to the value set by the RPROG1 resistance, the soft
start is over.
5) ISL95831 open drain outputs PGOOD, and pulls ALERT# low to send to
CPU.
6) CPU sends a serial VID signal to ISL95831.
7) According to the serial VTD signal setting, ISL95831 adjusts and outputs the
CPU core power supply to the corresponding value (VID setting is shown in
table 9-17).
8) After the core voltage being normal, ISL95831 again pulls ALERT# low,
means that the voltage has been normal.
9) When the chip again received the corresponding SVID signal of control
second of power supply, the chip outputs an integrated graphics (UMA) power
supply.
Table 9-17: The standard table of serial VIN decoding of ISL95831
9.5.5 Analysis of commonly used chip ISL6265 by AMD

platform
ISL6265 is commonly used in the motherboard of AMD CPU, as the output

control of the CPU core power supply and VDDNB power supply. The size of
chip is 6mm*6mm, QFN48 packaged.
The pin name of ISL6265 is shown in figure 9-72.
Figure 9-72: The pin name of ISL6265 (the top view)
The pin definition of ISL6265 is shown in table 9-18.
Table 9-18: The pin definition of ISL6265

l. the external connects the resistance to the ground programming DC
current source. If this pin is 1.2V, VFIX mode is closed; if this pin is pulled up
to be 3.3V, VFIX mode is opened. DAC decoder analyzes the input information
of SVC and SVD, OFS function is closed; if this pin is pulled up to be 5V, OFS
and VFIX are closed
2. the power good signal, open drain output, needs to be pulled up by the
external. then it will be high level
3. the system power good signal input. When this pin is high, SVID
interface is active, I2C protocol is running. When this pin is low, the input state
of SVC,SVD and VFIXEN decides PRE-PWROK METAL YID or YFIX mode
voltage. Before ISL6265 sent the high level of PGOOD, this pin must be low
4. serial VID identification pin data signal, connects with AMD processor
5. serial VID identification pin clock pin, connects with AMD processor
6. the enable signal input, when its high level,ISL6265 is opened
7. connects the 117kΩ resistance to the ground, sets the internal reference
current
8. the over-current of CORE_0 and CORE_1 setting signal input
9. CORE_0 differential amplification output
10. CORE_0 feedback input, to the input end of the internal CORE_0 error
amplifier
11. CORE_0 controller error amplifier output
12. from this pin connecting the resistance to COMPO to set the
switch frequency, for example, 6.81kΩ is 300kHz
13. the positive input of CORE_0 current detection

14. the negative input of CORE_0 current detection
15 .CORE_0 voltage detection input
16. the input loop of CORE_0 voltage detection
17. The input loop of CORE_1 voltage detection

18. CORE_1 voltage detection input
19. CORE_1 differential amplification output
20. CORE_1 feedback input, to the input end of the internal CORE_1 error
amplifier
21. CORE_1 controller error amplifier output
22. from this pin connecting the resistance to COMF1 to set the switch
frequency of the chip, for example,6.81kΩ is 300kHz
23. the positive input of CORE_1 current detection
24. the negative input of CORE_1 current detection
25. CORE_1 boot-strap end
26. CORE_1 high-end MOSFET driver signal output
27. CORE_1 phase pin, connects the output inductance. This pin is the loop
of the high-end tube drive signal
28. the ground terminal
29. CORE _1 low-end MOSFET driver signal output
30. the internal MOSFET driver power supply, connects the external 5V
power supply voltage input
31. CORE_0 low-end MOSFET driver signal output
33. CORE _0 phase pin, connects the output inductance. This pin is the loop
of the high-end tube drive signal
34. CORE_0 high-end MOSFET driver signal output
35. CORE_0 boot-strap end
36. the boot-strap end of NB power supply
37. the high-end MOSFET driver signal output of NB power supply
38. the phase pin of NB power supply, connects the output inductance. This
pin is the loop of the high-end tube drive signal
39. the low-end MOSFET driver signal output of NB power supply
41. the over-current protection setting of NB power supply
42 . the voltage feedback of NB power supply
43. the voltage feedback input of NB power supply
44. the switch frequency setting end of NB power supply, for example, 22.1
kΩ is set to be 260kHz
45. the error amplification input of NB power supply
46. the feedback input of NB power supply
47. 5V power supply input, external connection of a decoupling capacitor

with 0.1 uF
48. the chip power supply input pin; is used to improve the transient
performance
The important pin threshold voltage of ISL6265:

When VCC input voltage is higher than 4.35V(the typical value),is shown in
figure 9- 73, the chip implements POR (Power-On Reset).When VCC input
voltage is less than 4.1V (typical value), the chip stops working.
Figure 9-73: The screenshot of the description of the electrical features of VCC
threshold value in ISL6265 data manual
The typical value of the low level of threshold value of EN pin of ISL6265 is
1.35V,the high level of threshold value is 2V(typical value),is shown in figure
9-74.
Figure 9-74: The screenshot of the description of the electrical features of EN

threshold value in ISL6265 data manual
The input low level of threshold value of PWROK pin of ISL6265 is usually
0.65V,the high level of threshold value is usually 0.9V,is shown in figure 9-75.

PWROK threshold value in ISL6265 data manual
When PWROK is low level.ISL6265 chip does not implement SVID instruction,
but implement the corresponding voltage according to the state set by VFIXEN:
when WIXEN connects to 1.2V below or about SV. implements PRE-PWROK
METAL VID mode, the voltage configured by VID is shown in table 9-19.in
this working mode, when SVC and SVD are low level, the output voltage is
1.1V; when SVC and SVD are high level, the output is 0.8V.
Table 9-19: The ISL6265 PRE-PWROK METALVID mode decoding
Table 9-21: VFIX mode decoding
When WIXEN of ISL6265 connects to 3.3V, implements WIX mode, the

voltage configured by VID is shown in table 9-20.in this mode, when SVC and
SVD are low level the output voltage is 1.4V; when SVC and SVD are high
level, the output voltage is 0.8V.
Figure 9-76 is the typical application figure of ISL6265.
The working process of ISL6265 is shown in figure 9-77. The transverse digital
means the time, the vertical signal will change with time. As follows:
Time 1-2: VCC input. And crossed POR (4.3V),to complete the chip self-reset.
Time 2-3: SVC and SVD are pulled up or pulled low by the external, sets pre_
Metal VID code
Time 3-4: after EN changing to be the high level. VDD and VDDNB starts up,
rises to the value set by pre_ Metal VID mode.
Time 4-5: VDDPWRGF changes to be the high level. Indicates that CPU power
supply has been normal.
Time 5-6: PWROK inputs the high level, indicates that the chip ready to receive
SVI code.
Time 6-7: CPU drives SVD and SVC to start to transmit SVI instructions.
Time 7- 8: ISL6265 responds to SVI code instructions.
Time 8-9: if PWROK changes to be low, the chip stops SVI decoding
immediately, and drives CPU voltage to the value set by Pre_ PWROK Metal
VID.
Figure 9-76: The typical application figure of ISL6265
Figure 9-77: The working timing sequence figure of ISL6265
Time 9-10: PWROK changes to be high, indicates that the chip readies to
receive instructions again.
Time 10-11: SVC and SVD transmits new VID code.
Time 11-12: ISL6265 drives CPU power supply voltage to the new value set by
SVI.
Chapter 10
Analysis of QUANTA OEM
Laptop Mainboard Circuit
There have three kinds of the protective isolation circuit of Quanta, the RTC
circuit, standby circuit and the sequence of subsequent trigger power-on are
basically no difference. This chapter mainly takes CT6 as an example to explain
RTC circuit, protective isolation circuit and complete power-on sequence. In
addition, to explain the protective isolation circuit of ZQ5 and AX1.
10.1: Analysis of Quanta CT6 RTC Circuit

The RTC circuit of Quanta CT6 mainly includes the following voltage and
signal: VCCRTC, RTCRST#, 32.768kHz, INTVRME.
1. VCCRTC
The name of VCCRTC of the South Bridge still comes from VCCRTC, is
Figure 10-1: The screenshot of VCCRTC power supply about the South Bridge
The origin of VCCRTC voltage is shown in figure 10-2, when there is no

external power supply, is produced by the CMOS battery BT1 with 3V through
R196, D5; after 3VCPU producing (the principle of production is shown in 10.3
section), 3VCPU with 3.3V is added to VCCRTC through D4.due to the
characteristic of the diode, D5 will be cut-off, CMOS battery can save
electricity. In addition, the CMOS battery in this circuit is a rechargeable
battery:5VCPU produces 3.8V voltage through the partial pressure of R201 and
R203 to the B pole of Ql8,the triode Q18 will convert the voltage of 3 pin input
to 1 pin output the voltage is about 3.1 V this 3.1V is directly charged to BT1.
2. RTCRST#
In the figure 10-2,also shows the origin of the RTCRST#, that is, after
VCCRTC being normal, delay produced through R198.C220.G1 is the short
contact, CMOS discharged can be achieved.
3. 32.768kHz
In the figure 10-2, 32.768 kHz crystal, that is the South bridge connects the
crystal Y2 through RTXC1, RTCX2 pin, and get 32.768kHz frequency.
Figure 10-2: The screenshot of RTC Circuit
4. INTVRMEN
Internal Voltage Regulator Enable (INTVRMEN): This signal enables the
internal 1.05 V Suspend regulator when connected to VccRTC. When
connected to Vss. the internal regulator is disabled.
Figure 10-3: INTVRMEN
Another key RTC signal of the South Bridge is INTVRMEN, is easily

overlooked by many people. the definition of this signal in ICH7 is: Internal
Voltage Regulator Enable: This signal enables the internal 1.05 V Suspend
regulator when connected to VccRTC. When connected to Vss, the internal
regulator is disabled. If the South bridge hasn't this signal, it will lead to not
trigger fault. The origin of this signal is shown in figure 10-3,in this figure,R205
is not installed, INTVRMEN is pulled up to be high by VCCRTC through
R206.and is set to be the voltage regulator to open the internal of the South
bridge. Figure 10-3 the screenshot of INTVRMEN circuit
10.2: Analysis of Quanta CT6 Protective

Isolation Circuit
Let's look at the full figure about the protective isolation and the charging
circuit of Quanta CT6, is shown in figure 10-4.
Figure 10-4: The full figure about the protective isolation and the charging
circuit of Quanta CT6
In the figure 10-4,the production of the common point(the battery and the
adapter pass through this point together to supply the power to the system, then
this point is called the common point)voltage VIN. Need to go through PQ 15,
this P channel tube need to be conducted, and controlled by PQ4, and PQ4 is
controlled by ACOK with high level, is shown in figure 10-5.
Figure 10-4 the figure of CT6 protective isolation and the charging circuit.
Figure 10-5: The circuit where PQ4 is in

Let's look at the production of ACOK: as shown in figure 10-6, the docking
station voltage VA and the adapter interface voltage VA2 supply the power
supply pin DCIN of MAX1772, the inside of MAX1772 produces LDO voltage
5.4V and 4.096V reference voltage (shown in figure 10-7);the other path
through PR40 and PR49 divided into the voltage, then send to AC1N pin of
MAX 1772.
Figure 10-6: The circuit diagram of DCIN and ACIN of MAX1772
Figure 10-7: The internal block diagram of the LDO production of MAX1772
The detailed pin definition text of ACIN and ACOK in the MAX1772 data
manual is in the following.
ACIN: AC Detect Input. Detects when the AC adapter voltage is available for
charging.
ACOK: AC Detect Output. Open-drain output is high when ACIN is less than
REF/2.
According to the pin definition of ACIN and ACOK in MAX 1772 data manual,
when ACIN input voltage is higher than half of RET, the chip will output the
low level signal from ACOK pin. As shown in figure 10-6,VA/VA2 through the
diode divide into the voltage, then ACIN is produced, after calculation, as long
as the diode cathode is greater than 13.26V,it can make ACIN greater than
2.048V,and producing the low level of ACOK, this signal send to B pole of
PQ1,E pole of PQ1 has 5.4V linear voltage, so PQ1 is conducted, and producing
ACOK signal with 5V.
As shown in figure 10-8, ACOK with 5V is sent to PQ4,to make it to be
conducted,3 pin is grounded,VA3 through PQ5 internal resistance and PR46
divide into the voltage, after dividing into the voltage, the conducted condition
of PQ15 is satisfied; produces the common voltage VIN.
Figure 10-8: The production circuit of VIN
Note: there is a circuit to be payed attention, as shown in figure 10-9,this circuit

is valid just in the battery mode, is the battery low-voltage protection circuit.
The test conclusion by the author is:
BL/C# and D/C# in this circuit are used in combination.
Under the adapter mode, BL/C is driven as high by EC,PQ34 is always
conducted, 1 pin of the comparator PU10 is greater than 3 pin,4 pin open leak
output is pulled up as the high level by 3VPCU,and added to S pole of PQ36.At
this time, no matter whether D/C is low or high,PQ36 will not be conducted.
Under the battery mode, BL/C# is not defined by EC, the initial is low level.
When VIN voltage is normal, through the series partial pressure of PR143and
PR146 and the clamping of PD19, it's also greater than the voltage of the
comparator 1 pin the comparator 4 pin output the low level, at this time. D C
will be driven as high level by EC, make PD7 to be conducted, pull low the G
pole of PQ4.cut-off PQ4,close the isolation circuit it of the adapter. At the same
time, EC receives BL/C# with low level, indicating that the battery voltage is
enough.
Under the battery mode, when VIN voltage falls below 7.5V,the comparator 1
pin will be greater than 3 pin,4 pin output the high level, produces the high level
of BL/C#(Battery Low is valid / at the high level) through PR144,inform EC to
execute outage. And the high level of BL/C# will control PQ34 to be conducted,
continues to pull low the comparator 3 pin, and keeps the comparator + port is
greater than - port, always output the high level of BL/C#, the lock-in circuit
can realize the battery low-voltage protection function. When the adapter is
inserted again, it can be unlocked.
Figure 10-9: The low-voltage circuit diagram under the battery mode
10.3: Analysis of Quanta CT6 Power-On

Sequence Circuit
The common point VIN supplies to MAX1999,through PR79 and PR80 divide
into the voltage to SHDN, is shown in figure 10-10.According to the working
principle of MAX 1999,MAX 1999 outputs 3V_AL, 5V_AL respectively from
LDO3 pin and LDO5 pin. And 5V_AL is sent to VCC pin of the chip, as well as
ON3, ON5.When VCC is normal, it produces 2V reference voltage, and when
ON3 and ON5 are normal, MAX1999 controls two paths of PWM work,
produces 3VPCU, 5VPCU respectively. After working of the chip being normal,
open leak outputs PGOOD, and connects to HWPG.
5VPCU through PD11, PC63 and 1999_DL3 superimposing, and

outputs +10V after PD11, PC59 rectifying. +IOV produces +15V through
PD10, PC62, PC61 circuit.
Figure 10-10: MAX1999 Standby circuit
Produced 5VPCU to send to V5REF_SUS of the South bridge, is shown in

figure 10-11. 3VPCU voltage is supplied to EC, to be EC (U23) standby voltage,
is shown in figure 10- 12.
Figure 10-11: V5REF_SUS power supply of the South Bridge
Figure 10-12: EC Standby power supply
EC external 32.768 kHz crystal oscillator, supplies the clock in the state of
standby for EC is shown in figure 10-13.
Figure 10-13: EC Standby clock
3 VPCU delayed through the resistance, capacitance, supplies the reset in the
state of standby for EC PC87541, is shown in figure 10-14.
Figure 10-14: EC Standby reset
EC reads the EC code stored in the BIOS chip and configures GPIO pin through
X-BUS bus, is shown in figure 10-15 and figure 10-16. The power supply of
BIOS is 3VPCU.
Figure 10-15: X-BUS bus of EC
Figure 10-16: BIOS chip

Press the power button and produce the boot trigger NBSWON# to EC, is
Figure 10-17: EC receive the switch signal
EC sends S5_ON to produce 3V_S5 through the circuit as shown in figure 10-
18, and finally sends to VCCSUS3_3 of the South bridge.
Figure 10-18: S5_ON control circuit
Next, EC delays send RSMRST# to the South Bridge, is shown in figure 10-19.
Figure 10-19: EC sends RSMRST#

RSMRST# is sent to the South Bridge, then. after, EC meeting the
condition that ACIN,LID_EC# are high(as shown in figure 10-20:when SW1 is
not closed, LID_EC# is pulled up to be high level by 3VPCU),sends the pulse
DNBSWON#591 with "high-low-high" level, and converts to DNBSWON#
through D20 to send to PWRBTN# of the South bridge, is shown in figure 10-
21.
Figure 10-20: SW1 circuit
Figure 10-21: EC sends DNBSWON#591
Figure 10-22: South Bridge sends SLP_S*#
The South bridge standby condition RTC,cireuit,VCCSUS3_3,RSMRST# are

normal, and after receiving PWRBTN#, sends SLP_S5#,SLP_S4#,SLP_S3#
first, the SLP_S5# is not to be used.SLP_S4# renamed SUSC# through the
resistance R347,SLP_S3# renamed SUSB# through the resistance R342,is
SUSB# and SUSC# signal are sent to EC, after EC receiving SUSC# and
SUSB#, sends SUSON and MAINON successively. SUSON is sent to PU3,
after PU3 meeting the power supply of 14, 19, 22 pin and the opening of 23 pin,
outputs the memory main power supply +1.8VSUS, when the memory main
power supply is normal, open leak outputs POK, and connects to HWPG, is
Figure 10-23: The Producing circuit of the memory main power supply
Figure 10-24: SUSON control produced SUSD
SUSD is used to control PQ37 and PQ10 conducted, produces 5VSUS and
3VSUS is shown in figure 10-25.
Figure 10-25: The production of 5VSUS and 3VSUS
MAINON is used to open the following voltage:

MAINON controls to produce the memory load power supply (the memory bus
termination voltage SMDDR_VTERM),is shown in figure 10-26.This is the
production chip of the memory load power supply and the reference voltage,
after getting VIN and VCDDSSNS and S5,it will output VTTREF; and after
getting VLDOIN,S3,it will output VTT, tests the voltage of VTT by VTTSNS.
Figure 10-26: The production of the memory load power supply
MAINON send to ON1,ON2 of MAX1540,controls to produce the South bridge

main power supply with -M.5V and the front bus voltage with +1.05V,is shown
in figure 10- 27.This is a dual PWM power supply chip. the main power supply
V+, open signal ONl,ON2.When two paths of the power supply are normal,
open leak outputs PGOODl,PGOOD2,are connected to HWPG.
Figure 10-27: The production circuit of +1.5V and +1.05
MAINON produces MAIND through the circuit shown in the figure 10-28.
Figure 10-28: The production of MAIND
MAIND is used to open +5V and +3V with the state of S0, is shown in figure
10-29.
Figure 10-29: MAIND control circuit
PG signal from PCU standby power supply chip, the memory power supply
chip, the South bridge main power supply and the front bus power supply chip
connected together through the resistance to form HWPG and sent to 63 pin of
EC, is shown in figure 10- 30.1f EC don't receive this signal, it will lead to the
common fault of power down for Quanta motherboard.
Figure 10-30: EC received HWPG

After EC receiving HWPG, delays send VR_ON to 35 pin of the CPU power
supply chip, is used to open CPU power supply VCC_CORE, when the CPU
power supply is normal, then sends VR_PWRGD_CK410# with low level and
DELAY_VR_PWRGDOOD with high level, is shown in figure 10-31.
Figure 10-31: CPU power supply circuit
VR_PWRGD_CK410# opens the clock chip, and the clock chip sends each
clock is shown in figure 10-32.
Figure 10-32: The clock chip circuit

VR_PWRGD_CK410# is sent to VRMPWRGD pin of the South bridge by U42
inverted, informs the South bridge that CPU power supply has been normal at
this time, is shown in figure 10-33.
Figure 10-33: The South Bridge received VRMPWRGD
CPU power supply chip sends DELAY_VR_PWRGOOD to U29,phase with

PWROK delayed sent by EC after receiving HWPG, output 1CH_PWROK to
send to PWROK pin of the South bridge, is shown in figure 10-34.
Figure 10-34: The South Bridge received PWROK

At last, the South Bridge sends H_PWRGD from CPUPWRGD pin to CPU, is
Figure 10-35: CPU received PWRGOOD
The South bridge sends PLTRST# and PCI_RST# to each onboard chip and slot,
is shown in figure 10-36.
Figure 10-36: The South Bridge sent PLTRST# and PCIRST#

One of the paths of PLTRST# is sent to RSTIN# pin of the North Bridge,
DELAY_VR_WRGOOD is also sent to the North Bridge, is shown in figure
10-37.
Figure 10-37: The North Bridge received PG and Reset
At last the North Bridge sends H_CPURST# to CPU, is shown in figure 10-
38.After CPU receiving the reset, sends H_ADS# from HI pin to E8 pin of the
North Bridge. If we can catch this signal from T4 test point, then indicates that
the motherboard hard boot is finished, and CPU has started addressing.
Figure 10-38: The North Bridge sent CPURST#
10.4: The Analysis of Quanta ZQ5 (Acer

AS4733Z) Protective Isolation Circuit
First, the voltage of the adapter produces VA1 through PL12, is shown in figure
10-39.
Figure 10-39: Insert adapter to produce VA1
VA1 reaches the common point VIN through PD10 and PQ56,is shown in
figure 10- 40.The conducted conduction of PQ56 is that the voltage of G pole
should be low level relatively, that is, l pin and 6 pin of PQ5 should be cut off,
VA2 partial pressure to be about 9.5V through PR19 and PR17.
Figure 10-40: The producing circuit diagram of VIN
The condition of 1 pin and 6 pin of PQ5 been cut off is that 2 pin should be high
level (PNP triode), it also can be understood us 3 pin and 4 pin must be cut off
(NPN triode), so 5 pin D/C should be low level. D/C# comes from EC, when
used the adapter singly. Due to the system just connected to the power, the
subsequent stage power supply is not produced, EC has not power supply, and
D/C #is low level. So VIN can come out directly.
The means of D/C#: DISCHARGE in the high level, CHARGE in the low level.
This board just have D/C#, not BL/C#, according to the actual measurement, the
adapter is low after detecting D/C#, and is high in the battery mode. Let’s us
analysis the adapter detection circuit of EC.
VA1 supplies the power to DCIN of ISL88731 through PD1 and PR78 is shown
in figure 10-41.
Figure 10-41: VA1 supplies the power to DCIN of ISL88731
Figure 10-42
According to the internal block diagram (shown in figure 10-42) of ISL88731,

ISL88731 will produce VDDP and VREF. the description of the electrical
characteristics about the threshold value of VDDP and VREF output voltage in
the data manual is shown in the figure 10-43,the standard value of VDDP output
voltage is 5.1V,when VDDP load current is less than 30mA,the output is only
35mV error; VREF output voltage is 3.2V(the standard value).
Then, let's us look the pin definition of ACIN and ACOK. ACINL: AC Adapter
Detection Input. Connect to a resistor divider from the AC adapter output.
ACOK: AC Detect Output. This open drain output is high impedance when
ACIN is greater than 3.2V. The ACOK output remains low when the ISL88731
is powered down. Connect a 10k pull-up resistor from ACOK to VDDSMB.
Figure 10-43: The text screenshot of the electrical specification description

about the threshold value of VDDP and VREF output voltage
It means that AC is the adapter detection input pin. ACOK is the adapter
detection output pin. When the voltage of ACIN is higher than the reference
voltage 3.2V, ACOK open drain output, it can connect ACOK to VDDSMB pin
through 10kΩ resistance.
VA1 through PD1 and is divided into the voltage in series by PR149 and
PR150,then is sent to ACIN ,by calculating, the lowest voltage cannot be less
than 15.2V after VA1 through the diode PDI. The calculation of the partial
pressure is shown in figure 10-44.
Figure 10-44: The calculation of the series partial pressure
If the voltage of VA1 is not lower than the limit value, ACOK will open drain
output, 3VPCU through PR131 and is pulled up to be 3.3V, then sends to EC.
After EC receiving this signal, can keep D/C to be the low level. PQ 15 is cut
off, G pole of PQ39 is pulled up to be the high level by VIN through PR40
directly.PQ39 is cut off the battery is isolated, is shown in figure 10-45.In the
battery mode, BAT produces small current VIN through PQ39 diode, then
produces the power supply of EC.EC detects the high level of D/C# sent by the
adapter, and makes PQ15 conducted, VIN partial pressure through PR40 and
PR39, PQ39 is conducted completely.
Figure 10-45: The isolation and discharge of the battery
10.5: Analysis of Quanta AX1 Protective

Isolation Circuit
It needs to through PD20, PQ52 from the adapter CN17 to the common point
VIN; and it needs to through PQ55 from the battery CN16 to the common point,
is shown in figure 10-46.PQ52 is connected together to the G pole of PQ55, are
BATDIS_G. lf BATD1S_G is high level, PQ52 will be conducted, PQ55 will
be cut off; on the contrary, PQ52 will be cut off. PQSS will be conducted. If it
needs the adapter supply the power to the system, then BATDIS_G must be
high level and the voltage should be high enough (more than 23.5V).
Figure 10-46: VIN production circuit
Amplifier the part of the PQ52 circuit is shown in figure 10-47. There are three
conditions of BATDIS_G being high level:
(1) Pull-up voltage +VH28;
(2) ACOK# must be low level, PQ56 is cut off, and PR229 does not
participate in partial pressure;
(3) ACOK_IN can't be grounded. In the figure 10-47,if ACOK# is high, or
ACOK_ IN is low, it will cause the +VH28 partial pressure to form BATDIS_G.
the voltage is only 0.019V.
The specific calculation is shown in figure 10-48.
Figure 10-47: PQ52 circuit
Figure 10-48: Partial pressure calculation
Then, lets us analysis these three conditions:

Condition (1): +VH28 comes from PU2(P2805MF),is shown in figure 10-
29,this is the boost chip with internal integrated the boost circuit.VA of 19V
through PDO to +VAD_1,supplies to PU2,PU2 internal boost produces
+VH28.When the boost is successful .the chip open drain output 6251ACIN.
Figure 10-49: The production of +VH28

Conduction (2): ACOK# comes from the ACPRN output of ISL6251, is shown
in figure 10-50.
Figure 10-50: The source of ACOK#
According to the data manual of ISL6251, the pin definition of ACPRN is:
Open-drain output signals AC adapter is present. ACPRN pulls low when
ACSET is higher than 1.26V; and pulled high when ACSET is lower than
1.26V From the figure 10-50, +VA produces +VAD_1 through PD0, and
supplies the power to DCIN of ISL6251 through PD1, the other path is to
through PR235, PR236 partial pressure to ACSET.ISL6251 outputs
ISL6251_VDDP from VDD after receiving DCIN, the voltage is 5.07V (the
typical value), is shown in figure 10-51.
Figure 10-51: The screenshot of the description of the electrical characteristic

about VDD output threshold value in ISL6251 data manual (datasheet)
The internal principle is shown in figure 10-52, after inputting DCIN, then
output VDD. In the figure 10-50,after ISL6251 getting ACSET, it will compare
with the internal 1.26V,if ACSET is higher than 1.26V,the comparator outputs
the high level, the field- effect transistor is conducted and pulls ACPRN low, is
Figure 10-52 VDD output internal principle diagram of ISL6251
Figure 10-53: ACSET internal principle diagram of ISL6251

By calculation, the +VAD_ l voltage must be higher than 11.4V.
(According to the figure 10-49, figure 10-59,6251ACIN signal of ACSET pin
connected to the PG of the boost chip PU2, if PU2 does not succeed in boosting,
6251ACIN will also be pulled low.)
Condition (3):ACOK_IN connects to PQ9 is shown in figure 10-54.To keep

ACOK_IN not grounded, PQ9 must be cut off, and then there must have the low
level of D/C#.
Figure 10-54: ACOK_IN connection circuit

D/C# comes from EC, is shown in figure 10-55, before the common point
produced, the standby chip is not working, EC has not voltage, and is also not
working, so D/C# will not be high level; after EC getting the power supply, EC
must detect that the adapter exists (ACIN is high), then will keep D/C to be low.
If EC is not detected the adapter, D/C# will be set high by EC.
Figure 10-55: The screenshot of D/C# and ACIN of EC
The origin of the adapter test signal of EC is shown in figure 10-56. ACOK#
with low level controls PQIO conduction, converts -1SL6251__VDD to ACOK,
then through PR84, PR85 partial pressure, produces ACIN to EC as the adapter
test signal.
Figure 10-56: The production circuit of ACIN
Chapter 11
Analysis of WISTRON OEM
The circuit and sequence of Wistron are not too many features, it can also be
said that its feature is quite satisfactory. The RTC circuit is similar to those of
the Quanta, the batter}' is usually not chargeable; the power-on sequence is the
Intel 'standard sequence. This chapter is not much introduced the RTC circuit
and the power-on sequence. Mainly, to explain the protective isolation and the
standby circuit.Then.as Wistron HBLJ16-1.2 an example to analyze the
protective isolation and the standby circuit.
11.1: Analysis of Wistron HBU16-1.2 Protective

Isolation Circuit
Insert the adapter, producing AD_JK, added to the S pole of U1, though the
partial pressure of R2 and RI produced the low level of 6.3V, control U1
conducted and produced AD+ (when inserted the adapter. because EC is no
power, AD_OFF is low level; only when the system program control forced to
discharged the battery, then EC will send the high level of AD_OFF), is shown
in figure 11-1.
Figure 11-1: The screenshot of AD+ production circuit

AD+ produced the small current common point DCBATOUT through U2 body
diode, 18.3V, is shown in figure 11-2.
Figure 11-2: The production of the small current common point

AD+ is added to the G pole of U7, makes it cut off, the battery is isolated, is
Figure 11-3: The screenshot of the battery isolation circuit
AD+ supplies the power to DCIN of the charge chip U44 (MAX8731) and
divides into the voltage to ACIN, is shown in figure 11-4.
Figure 11-4: The screenshot of DCIN and ACIN circuit

When DCIN is power on, U44 outputs 5.4V MAX8731_LDO from LDO pin is
shown in figure11-5. About the figure 11-6, is the relationship between DCIN
and LDO of MAX8731 internal block diagram.
Figure 11-5: LDO output
Figure 11-6: The internal principle diagram of LDO production
In the data manual of MAX8731, the screenshot of the electrical characteristic

description about DCIN effective value is shown in figure 11-7. DCIN effective
value is 8-26V, the under-voltage lockout value is 7.4V (typical value).
Figure 11-7: The screenshot of the electrical characteristic description about

DCIN threshold value in the data manual of MAX8731
MAX8731_LDO supplies the power to VCC pin through R204, is shown in
figure 11-8.
Figure 11-8: The circuit screenshot of LDO supply power to VCC

When VCC is power on, 4.096V reference voltage REF produced by the
MAX8731 internal, is shown in figure 11-9.
The ACOK pin definition is: AC Detect Output. This open-drain output is high
impedance when ACIN is greater than REF/2. The ACOK output remains low
when the MAX8731 is powered down. Connect a 10kΩ pull up resistor from
VCC to ACOK.
ACIN compared with the half of REF in the internal, when ACIN is greater than
REF/2(2.048V), ACIN open drain output, is shown in figure 11-10.
Figure 11-9: The internal principle diagram of the production of MAX8731

reference voltage
Figure 11-10: The screenshot of ACOK output principle of MAX8731

As long as AD+ voltage is higher than 17.767V,ACIN will be greater than
2.048V,ACOK Will open drain output ACAV_IN, is shown in figure 11-11.The
calculation process is shown in figure 11-12.
Figure 11-11: The screenshot of ACOK output ACAV_IN
ACAV_IN is divided into the voltage by MAX8731_LDOto be 3.3V high level

by MAX873l_LDO. Through Q3 to produce the low level of AD_IN# to EC (as
the adapter test signal of EC), is shown in figure 11-13.
The other path controls 3-4 pin conducted of U3, makes R183 grounded. The
small current common point through R182 and R183 to form partial pressure,
and produces about 6V voltage to send to 4 pin (G pole) of U2, the S pole of U2
is 18.3V.the G pole is 6.1V,U2 channel is fully opened, AD+ directly flows to
the common point, producing the large current common point, is shown in
figure 11-14.
Figure 11-12: The screenshot of AD+ threshold value calculation
Figure 11-13: The screenshot of the adapter test signal production of EC
Figure 11-14: The screenshot of the large current common point production
circuit
11.2: Analysis of Wistron HBU 16-1.2 Standby

Circuit
After the common point voltage DCBATOUT producing, input to supply the
power to VIN of the standby chip U30.is shown in figure 11-15.
Figure 11-15: The circuit diagram of VIN supply power to U30

The standby chip is using TPS51125. When it got VIN, because ENO is grounded
through 820K resistance, set the linear voltage opened automatically, but close VCLK,
Figure 11-16: The screenshot of TPS51125 circuit
According to TPS51125, working principle analyzed in the 9.2.2 section. After

TPS51125 getting VIN and ENO, the chip outputs +3VL, and renamed to be
+3VL_KBC, is shown in figure 11-17. +3VL_KBC is supplied to EC as the
standby voltage, is shown in figure 11-18.
Figure 11-18: The screenshot of EC standby power supply

After EC getting power supply, to supply the voltage to X2, crystal oscillator starts,
and sends to EC standby clock 32.768 kHz, is shown in figure 11-19.
Figure 11-19: EC standby clock circuit
+3VL_KBC pulled up VCC_POR#, as the standby reset of EC, is shown in

figure 11-20.
Figure 11-20: The principle of EC reset production

After the standby condition of EC being satisfied, reads ROM (U25) through
SPI bus of 86,87,90,92 pin (shown in figure 11-21).ROM circuit is shown in
figure 11-22.the power supply of U25 is also came from +3VL_ KBC.
Figure 11-21: SPI bus pin of EC
Figure 11-22: The screenshot of U25 circuit
After EC reading the program normally, will configured their pin. Then EC
identifies the adapter insert test signal AD_IN# of 93 pin, is shown in figure 11-
23.
EC detects that the low level of the adapter is inserted an indication signal, then
sends automatically the high level of PWR_S5_EN, is shown in figure 11-24.
Figure 11-23: The adapter test signal of EC
Figure 11-24: E sends PWR_D5_EN

PWR_S5_EN controls Q42 conduction, Q40 and Q41 will cut off, is shown in figure
11- 25. 51125_ENTRIP1 and 51125_ENTRIP2 are cannot grounded directly, it just
can be grounded through R498 and R508.
Figure 11-25: The screenshot of the circuit controlled by PWR_S5_EN
51125_ENTRIP1 and 51225_ENTRIP2 connected to 1 pin and 6 pin of

TPS51125. According to the pin definition of TPS51125 in the 9.2.12 section, it
can open chip through the resistance grounded and as an over-current threshold
value setting. TPS51125 outputs two paths of PWM power supply, is shown
in figure 11-27: 3D3V_PWR, 5V_PWR, through isolation point respectively to
rename to be +3VALW and +5VALW.
Figure 11-26: The screenshot of 1 pin and 6 pin of TPS51125
Figure 11-27: The screenshot of the circuit of 3D3V_PWR and 5V_PWR

renamed
+3VALW and +5VALW supply respectively to VCCSUS3_3 and V5REF_SUS

of the South bridge; as the South bridge standby voltage, is shown in figure 11-
28 and figure 11- 29.
Figure 11-28: 3.3V standby voltage of the South Bridge
Figure 11-29: 5V standby voltage of the South Bridge
EC delayed send PM_RSMRST#, is shown in figure 11-30.
Figure 11-30: EC sends PM_RSMRST#
PM_RSMRST# is converted to be RSMRST#_SB, is shown in figure 11-31.
Figure 11-31: PM_RSMRST# renamed to be RSMRST#_SB
RSMRST#_SB is sent to the South Bridge, is shown in figure 11-32.
Figure 11-32: RSMRST#_SB is sent to the South Bridge
Chapter 12
Analysis of COMPAL OEM
The greatest feature of the motherboard designed by Compal is the protective
isolation and the standby circuit. the power-on sequence and the RTC circuit is
almost the standard sequence. This chapter introduces three kinds of Compal
protective isolation circuit. Then explain one of the Compal standby circuit.
12.1: Analysis of Compal LA-5891P Protective

Isolation and The Standby Circuit
In this section, takes Compal LA_5891P as an example to analyze the protective
isolation and the standby circuit.
1. The protective isolation circuit

Insert the adapter, through the power connects to PJPl, and produces VIN, 19V
through PL24, is shown in figure 12-1.The figure of Compal motherboard
power interface is shown in 12-2.
Figure 12-1: The production of VIN
Figure 12-2: Compal Mainboard power interface
VIN produces VS through the parallel connection of PD2, PR304 and PR305,
and produces Nl through PQ42 diode, changes to be CHGRTCP through PR306,
then through PR309 to produce N2 to supply the power to the pressure regulator,
PU14 outputs 3.3V of RTCVREF, is shown in figure 12-3.
Figure 12-3: The production circuit of RTCVREF
VIN compares with RTCVREF after through PR297 and PR301 diving into the
voltage, if the voltage of VIN is higher than 17.24V (make a rough calculation
after ignoring the hysteresis resistance: the results of VIN/ (PR297+PR301) x
PR301 is higher than 3.3V), the comparator will open drain output as is diving
into the voltage by VIN and through PD1 steady pressure to produce the high
level of PACIN and ACIN, is shown in figure 12-4.
Figure 12-4: The production circuit of PACIN and ACIN

If we count in the hysteresis resistance, the falling edge of the VIN voltage
threshold value is 17.525 V, the rising edge is 17.901V, is shown in figure 12-5.
Figure 12-5: The screenshot of the VIN threshold value voltage
VIN crosses PD14 and four parallel resistances, makes PQ67 conduction.
Supply power to B+, is shown in figure 12-6. (When PD14 pressure drop of
1mA, the voltage is about 0.7V, when pressure drop of 10mA, the voltage is
about 1V. You can consult the data manual of LL4148). If the value of
resistance of B+ grounded is higher than 1.35kΩ. Make a rough calculation: if
VIN is 19V, PD14 pressure drop is lV:
(19V-lV)/(250+RB+) x RB+=15.2V, so RB+ =1357Ω
So the voltage B+ got is higher than 15.2V.
Figure 12-6: Power supply in B+ production circuit

After detected the adapter, PACIN is high level, makes PQ69 conducted and
makes PR395 and PR394 to be parallel connection. the value of resistance is
138kΩ after parallel connection, B+ through PR387 and divides into the voltage
with the parallel resistance, is shown in figure 12-7.If the voltage of B+ is
higher than 15.2V (ignore the hysteresis resistance PR385), the voltage will
higher than 3.3V after dividing into the voltage, the comparator open drain
outputs, and is pulled up to be a high level by VL. ACON is not pulled low (VL
comes from the standby chip, we will analyze it in the standby circuit).
Figure 12-7: The screenshot of the ignition loop circuit
If B+ line short circuit, the value of resistance is less than 1.35kΩ,

the voltage value is pulled below 15.2V; the voltage got by the resistance
dividing into the voltage will be lower than RTCVREF voltage 3.3V,the
comparator 7 pin outputs the low level. Then ACON, MAINPWON are pulled
low. This is the power supply in advance circuit also called ignition loop.
The ignition loop is divided into three cases (ignore the hysteresis
resistance).
Figure 12-8: B+ threshold voltage setting in the adapter and battery mode
(1) When PACIN is low, PQ69 is cut off, PR394 is not grounded, does not
participate in the partial pressure circuit, B+ minimum cannot be less than 6.6V
(the battery mode).
(2) When PACIN is high, but before +5VALW produced, PQ71 is cut off, PQ69
is conducted, PR394 and PR395 being in parallel, then series partial pressure
with PR387. B+ minimum cannot be less than 15.2V (when the adapter is just
inserted).
(3) When PACIN is high.+5VALW is produced.PQ71 is conducted,PQ69 is cut

off,PR394 is not grounded, as long as B+ is not less than 6.6Y.then it can make
the comparator open drain output the high level, ACON and MAINPWON are
not pulled low(the adapter mode, the ignition has been completed).
As the figure 12-8 shown, after adding the hysteresis resistance, the detection
threshold value of B+, the adapter mode is 14.8V~15.9V.the battery mode is
6.2V~7.3V (select the intermediate value).
About Compal machine, for example to non-program controls the correction of
the battery electricity and forces to open the battery discharge, EC always
outputs the low level of ACOFF, PQ65 is cut off. PACIN is high, ACON is not
pulled low by the comparator, PQ63 obtains the G pole voltage with high level,
PQ63 is conducted, is shown in figure 12-9.
Figure 12-9: The circuit of PACIN and ACON
VIN produces P2 through the body diode of PQ51, through PR354 and PR361
then through PQ63 to be grounded, and forms partial pressure, produces about
8V voltage to add to the G pole of PQ51 and PQ52, make it conducted
completely, VIN flows to B+, the common point of the large current produced,
Figure 12-10: The production circuit of the large current B+

(1) ACON is high, and makes PQ59 conducted at the same time, PQ58 will be
cut off, and PQ56 will also be cut off.
(2) If ACON is low or PACIN is low, it will make PQ63, PR354 and PR361 not
partial pressure, P2 with 18V through PR354 to pull up the G pole of PQ51 &
PQ52, two separate tubes are cut off.
At the same time,PQ59 is cut off, the B pole of PQ58 is pulled up by VIN,PQ58
is conducted,PQ56 is also conducted,P2 flows to the C pole through the E pole
of PQ56,then added to the G pole of PQ51,PQ52,and make it cut off.
The circuit of the battery isolation and discharge is shown in figure 12-11.
In the figure 12-11, when PACIN is high, PQ61 is conducted, pulls low the
positive pole of PD12, PD12 is cut off; ACOFF is also low, PD9 is cut off; the
B pole of the triode PQ57 is pulled down to be the low level by its own
resistance, PQ57 is cut off, VIN through PR352 to pull up the G pole of PQ53,
PQ53 is cut off, the battery is isolated.
(1) If VIN is no power, the G pole of PQ53 will pulled down to the grounded by
PR352, PQ53 is conducted, the battery discharge.
(2) If VIN is power on. but PACIN is low level,PQ61 is cut off, the positive of
PD12 is pulled up to be high by PR357,PD12 is conducted,PQ57 is also
conducted, VIN through PR352 and PR356 divides into the voltage to the G
pole of PQ53,PQ53 is conducted. the battery discharge.
Figure 12-11: The battery isolation circuit

(3) If VIN is power on, PACIN is high level, but ACOFF is also high(when the
program control forces to discharge to the battery),PD9 is conducted,PQ57 will
also be conducted, VIN through I PR352 and PR356 divides into the voltage to
the G pole of PQ53,PQ53 is conducted, the battery discharge.
2. Analysis of the production of VA (the adapter mode and

the battery mode)
VS production circuit is shown in figure 12-12. Look at the following analysis.
Figure 12-12: VS production circuit

The adapter mode: VIN through PD2, then through PR304 and PR305 to
produce VS directly.
The battery mode: BATT+ through PD3 to produce Nl, sends it to 3 pin of
PQ42, it cannot be conducted to VS.
PQ42 is a P channel, the condition of conduction is: when 51ON# is the low
level, PR307 and PR308 forms partial pressure, produces relatively the low
level about 2V, at this time, the G pole is 2V, the S pole is 11V, VG<VS, PQ42
is conducted completely, producing VS.
So, in the battery mode, if VS want to be produced, it must set low to 51ON#.
51ON# connects toD12 and Q32, after pressing the switch, ON/OFFBTN# is
low, through D12 to pull 510N# low, then produces VS, is shown in figure 12-
13.
At the same time of triggering the switch, it will produce ON/OFF to send to EC,
after that, EC sends the high level of EC_ON to conduct Q32, and keep 51ON#
to be low level.
(Before triggered the boot pin of Compal, the voltage is about 17V in the
adapter mode, and the voltage is about 10V in the battery mode.)
Figure 12-13: 51ON# circuit
3. The standby circuit

The common point B+ is converted to be ISL6237_B+, supplies to 6 pin VIN
of PU16 (RT8206), is shown in figure 12-14. According to the RT8206 data
manual, the minimum k working voltage is 6V.
Figure 12-14: B+ supplies power to PU16
VS through the voltage stabilizing diode PD7 to reverse breakdown, then

divided into pressure to EN_LDO, is shown in figure 12-15(as long as VS is
higher than 7.5V, it will higher than 2.4V after reverse breakdown
PD7,EN_LDO produced after dividing into pressure can be more than the
threshold value 1.6V of 4 pin).
Figure 12-15: EN_LDO production circuit

After PU16 obtaining VIN and EN_LDO, outputs the reference voltage
2VREF_ISL6237 and the linear voltage VL, is shown in figure 12-16.
Figure 12-16: PU16 outputs LDO and VREF2

VL through PR561 to pill up ENl of RT8206, 2VREF_SL6237 is added to EN2.
According to the pin definition of TR8206, EN2 connects REF, sets that
produce +5VALW first then to produce +3VALW, is in figure 12-17.
Figure 12-17: The origin of EN1 and EN2
When MAINPWON is not pulled low by ignition circuit and also not pulled low
by temperature control circuit, ENl is high level, RT8206 opens PWM1 first to
control produce +5VALWP, after +5VALWP being stable, then RT8206 opens
PWM2 to produce +3VALWP (32 pin connects VL, 11 pin is grounded, two
path of PWM are set respectively fixed output 5V and 3.3V), is shown in figure
12-18.
Figure 12-18: RT8206 outputs two path of PWM
A path of MAINPWON connects the ignition circuit of PD15, the other path is
connected to 3,4 pin of PU30,is shown in figure 12-19.This is a CPU
temperature control circuit, when the temperature increase, the resistance value
of PH1 will decrease(NTC).When reach a certain temperature, PU30 will pull
MAINPWON low.
Figure 12-19: PU30 temperature control circuit
The standby voltage +3VALWP renamed to be +3VALW through the isolation

point, +5VALWP renamed to be +5VALW through the isolation point, is
Figure 12-20: Two voltages renamed

+3VALW supplies the power directly to EC, is shown in figure 12-21.
Figure 12-21: The standby power supply of EC

+3VALW produces +3V through the isolation point J5 to supply the standby
voltage (@ next to U14 indicates that U14 is not installed, J5 is short connected)
to the bridge, is shown in figure 12-22
Figure 12-22: +3V production circuit
+5VALW renamed to be +5V through R169 to supply to V5REF_SUS of the

bridge, is shown in figure 12-23.
After RT8206 producing +3VALWP and +5VALWP normally, open drain
outputs SPOK, is shown in figure 12-24.
Figure 12-23: The production of +5V
Figure 12-24: RT8206 outputs SPOK
SPOK controls PQ45 conducted after being pulled up to be high level by VL,
B+ through PR325 and PR327 partial pressure to control PQ44 conducted,
producing +VSBP, is shown in figure 12-25.
Figure 12-25: The production of +VSBP
After the standby voltage of EC being normal, the external crystal X1 starts
oscillator, is shown in figure 12-26.
Figure 12-26: The standby clock of EC +3VALW delays supply the reset to 37
pin, is shown in figure 12-27.
Figure 12-27: The standby reset of EC

EC starts to read the data of U31 through SPI bus of 119, 120, 126, 128,
configures GPIO pin, is shown in figure 12-28.The circuit of U31 is shown in
figure 12-29, U30 is not installed in the figure.
Figure 12-28: EC reads the pin of BIOS
Figure 12-29: The screenshot of the location of U31
The standby circuit is ready now, and then EC will wait users to trigger the
switch, and send RSMRST# & PWRBTN# to the bridge.

Isolation Circuit
About Compal motherboard, the protective isolation and the ignition circuit of
some models have another way, next, as LA-6631P (GM45 series) an example
to explain the protective isolation principle. Let's us look at the working
principle of the protective isolation circuit, is shown in figure 12-30: VIN
crosses four parallel resistances to reach PRECHG, one path of this voltage
through PD7 and PQ27 to B+ the other path through PR43 and PR47 partial
pressure to send ACSET pin of PU4(ISL6251).
Figure 12-30: The power supply in B+
In the mode of the adapter power supply, ACOFF is low, and +5VALW is not
produced,PD9 cannot make PQ28 conducted, so PQ30 will be conducted, to
make PR83 and PR86 partial pressure to form the low level relatively, the small
current B+ is produced. When the program control the battery to correct the
electricity, ACOFF is high, or after +5VALW producing normally, this circuit

will be shut down.
If B+ is short circuit, the voltage is pulled low, then PRECHG will also be
pulled low, because of the clamping action of LL4148, the voltage of PRECHG
will be higher than B+ 1V (after investigation, the voltage of LL4148 drops
1V).PRECHG through partial pressure, is sent to ACSET of PU4 (ISL6251).
The indication in the ISL6251 data manual as follows:
ACSET is an AC adapter detection input. Connect to a resistor divider from the

AC adapter output. ACPRN Open-drain output signals AC adapter is present.
ACPRN pulls low when ACSET is higher than 1.26V; and pulled high when
ACSET is lower than 1.26V.
ACSET is defined to be AC adapter test output pin.
ACPRN is defined to be open drain output pin, when ACSET is higher than
1.26V, ACPRN is pulled low, and when ACSET is less than 1.26V, ACPRN is
pulled up. that is to say, the threshold value of ACSET is 1.26V,by the
calculation of partial pressure [1.26/PR47* (PR43+PR47)], it can conclude that
PRECHG cannot be less than 18.09V.Since B+ is produced by PRECHG
through PD7,so the minimum voltage of B+ is limited to be 17.09V,is shown in
figure 12-31.
Figure 12-31: PRECHG partial pressure to ACSET
If B+ is not short circuit, the voltage of PRECHG is normal. ACSET is higher

than 1.26V, ACPRN outputs the low level, PQ26 will be cut off, PACIN obtains
the high level through PR72 and PR74 partial pressure, at the same time, the
high level of ACIN is sent to EC, is shown in figure 12-32.
Figure 12-32: The production of PACIN and ACIN
The high level of PACIN through PR63 to make PQ20B conducted, VIN
produces P2 through PQ12 body diode then through PR41 and PR50 partial
pressure to be about 8V, PQ12, PQ13 is conducted, VIN crosses the protective
isolation to produce the large current B+, is shown in figure 12-33.
Figure 12-33: The production circuit of the large current B+

When the program controls EC to correct the electricity of the battery, ACOFF
is high, PQ24 is conducted, and pulls the G pole of PQ20 low, VIN_ l makes
PQ17 conducted, P2 through the internal resistance of PQ15 partial pressure,
PQ15 is PNP tube. The voltage of the B pole is less than the E pole; E-C is
conducted, and conducts P2 to the G pole of PQ12 and PQ13 directly. Two P
channel tubes will be closed. VIN and B+ are isolated.
In addition, as shown in figure 12-34, when ACPRN is low level, PQ 10 is cut
off. VS makes PQ9 conducted through PR36,pulls the G pole of PQ8 low,PQ8
is cut off, ENTRIP1 and ENTRIP2 are not grounded (note: VS is produced
directly just in the adapter mode, and it needs to trigger the switch in the
battery mode. then it will be produced, there is no difference with LA-5891P,
not to explain. If it occurs the over- temperature, MAINPWON is low, it will
also cut off PQ9).
ENTRIP1 and ENTRIP2 of RT8205 are not grounded directly, but through the
resistance PR27, PR28 to be grounded, it can produce +3VALW, +5VALW
successfully.
Refer to RT8205 data manual (datasheet), the ENTRIP1 (Pin 1) Channel 1

enable and Current Limit setting Input. Connect resistor to GND to set the
threshold for channel 1 synchronous RDS (ON) sense. The GND- PHASE1
current-limit threshold is 1/10th the voltage seen at ENTRIP1 over 0.5V to 2V
range. There is an internal 10uA current source from VREG5 to ENTRIP1. The
logic current limit threshold is default to 200mV value if ENTRIP1 is higher
than VREG5-1V.
Figure 12-34: The Standby voltage of enable signal and the control circuit

Isolation Circuit
First, insert the adapter, output VIN, is shown in figure 12-35.
Figure 12-35: The production of VIN
VIN needs to through the circuit to reach the common point B+, is shown in
figure 12- 36.VIN through PQ301 body diode to produce P2, a little more than
18V, the conduction of PQ301 and PQ302 needs that the G pole is the low level
respectively. That is to say, there must have the high level of PACIKACON and
the low level of ACOFF (BATT_OUT is high level of PACIN, ACON and the
low level of ACOFF (BATT_OUT is high level after powering on, is not
involved in the protective isolation control) in this circuit.
Figure 12-36: The circuit of the common point production
Let's look at the origin of PACIN, ACON and ACOFF.
The origin of PACIN and ACOFF: as shown in figure 12-37, it must be the low
level of ACPRN input, then PQ316 will be cut off, 6251_VDD (ISL6251VDD
pin outputs the linear voltage 5.075V) through PR338 and PR342 partial
pressure to obtain the high level of PACIN with 3V, and produce the high level
of ACIN at the same time, ACIN is sent to EC.
Figure 12-37: The production of PACIN and ACIN

ACOFF is the low level sent by EC. Only when the system program controls the
battery forced discharge, EC will send the high level of ACOFF.
ACPRN comes from 23 pin of ISL625.is shown in figure 12-38.According to
the data manual of ISL6251, when ACSET pin is higher than 1.26V, ACPRN
will output the low level. ACSET comes from ACSETIN that VIN through
PR306 and PQ312 partial pressure to obtain.
Figure 12-38: The production of ACPRN

According to the calculation of the resistance parallel partial pressure, the
minimum voltage of VIN cannot be less than 18.09V. If it is less than this
voltage, after partial pressure, ACSETFN will be less than 1.26V, is shown in
figure 12-39.
The origin of ACON planned to use the mature ignition loop, but is not used in
this machine (@ means that the component is not installed), is shown in figure
12-40.
Figure 112-39: The calculation of VIN threshold value
Figure 12-40: The ignition loop
The origin of BATT_OUT: as shown in figure 12-42.VMB2 is the battery

interface power supply pin, 6251VREF comes from the reference voltage 2.39V
output of ISL6251.When the voltage of VMB2 is less than 9.08V, through
PR212 and PR215 partial pressure to send to 5 pin of the comparator. And it
will less than 2.39V of the comparator 6 pin, 7 pin outputs the low level, PQ201
is cut off.
Figure 12-41: BATT_OUT control circuit
At the same time, it needs the low level of BATT_LEN# sent by EC, then
PQ205 will be cut off, +3VS through PR211 to pull up BATT_ OUT to be the
high level. But +3VS is the power supply in the state of the system S0. So this
signal can control the protective isolation only in the boot state, not to analyze
at here.
Chapter 13
Analysis of INVENTEC
OEM Laptop Mainboard
Circuit
Inventec is usually OEM for HP. In this chapter, as DosXX Dunkel 1.0
(HP_6510b) an example to explain part of the circuit of Inventec, the circuit of
this type is basically completed by the independent components, EC seldom
participated in voltage control It is very meaningful for study of the circuit
analysis.
13.1: Analysis of Inventec DosXX Dunkel 1.0

Protective Isolation Circuit
The voltage +VADP of the adapter interface JACK1 needs through Q507 and
Q514 to reach the common point +VBATR, these two of field-effect tube is
controlled by ADP_EN#, BATCAL#, ACDRV#, is shown in figure 13-1.
In the figure 13-1, Q507 is P channel. It must have two conditions to conduct:
ADP_EN# is low, BATCAL# is high, and the origin of them is shown in figure
13-2.
The circuit analysis in the figure 13-2:
(1) LIMIT_SIGNAL is about 7V voltage from the adapter middle pin, +VADP
is the adapter voltage 19V,through R108 and R105,R104 partial pressure, then
gets 5.9V of 2 pin, and less than 7V of 3 pour the comparator outputs the high
level ADP_ ID, then sends to EC for adapter detection.
(2) VADP through R108, R105 and R104 partial pressure to be 4.8V to send to 5
pin is less than 7V of 6 pin, the comparator outputs the low level ADP_EN#.
(3) The low level of ADP_EN# makes Q7 cut off, ADP_ EN is high. sends to
EC, because it's no power at this time,SLP_S3#_3R is low,Q545 is cut off,
BATCAL# is pulled up to get the high level by the adapter voltage through
R9252.
Then the Q507 is conducted successfully and produces +ADPBL.
In the figure 13-1,if Q514 is conducted completely, it needs the low level of
ACDRV# sent by U5(BQ24703),the specific process is that +VADPBL in the
left side of Q514 through the body diode between the D pole and S pole and
D510 supplies the small current to the common point +VBATR, is shown in
figure 13-3.
+VBATR renamed to be +VBATP after crossing the jumper wire PAD6,

supplied to VIN of the standby power management chip TPS51120,as the main
power supply. is shown in figure 13-4.Because EN3 and EN5 of the chip is
hung in the air, according to the pin definition of TPS51120, EN3 & EN5 being
hung in the air will produce automatically VREG3 and VREG5.VREG5
retraces to supply the power to V5FILT,and produces the reference voltage with
2VREF.
Figure 13-1: The common point production circuit

(For more clear details, please check their full schematic diagram on the bonus
section)
Figure 13-2: The control circuit Q507
Figure 13-3: Te production circuit of the small current common point
Figure 13-4: TPS51120 circuit
As shown in figure 13-5, the small current +VBATR is sent to 22 pin VCC of
BQ24703 to be the power supply. +VADPBL through the resistance R27, R26,
R31 series partial pressure, and added to 5 pin of the comparator U1, to
compare with the voltage of 2VREF. If the voltage of +VADPBL is higher than
10.87V, the 7 pin of the comparator U1 will open drain output and the adapter is
inserted the detection signal ADP_PRES, is pulled up to be the high level by
+V3AL through R89 ADP_PRES through the resistance R91 to send to ACDET
pin of BQ24703, is higher than the internal threshold value 1.246V. BQ24703 is
identified to be the state of the adapter inserted. And outputs the low level of
AC_DRV#, the G pole of Q514 is conducted after getting the low level through
the resistance R565 and R575 partial pressure. the large current common point
+VBATR is produced (the comparator also outputs the charging open signal
AC_AND_CHG from 1 pin, sends to ENABLE of BQ24703, as the charging
enable signal).
Figure 13-5: The screenshot of BQ24703 circuit
13.2: Analysis of Inventec DosXX Dunkel 1.0

Standby Circuit
In the figure 13-4, the common point voltage +VBATR is supplied to the VIN
pin of the standby: voltage chip TPS51120, because EN3. EN5 is hung in the air
is set to be opened automatically internal linear steady pressure VREG3 and
VREG5.TPS51120 outputs +V3AL,+V5AL. +3AL supplied to U14 (EC,
SMC_KBC1070) as its standby power supply is shown in figure 13-6.
Figure 13-6: The standby power supply of EC
After EC power supply being normal, the external 32.768 kHz from 70-pin and
71-pin crystal oscillated, is shown in figure 13-7.
Figure 13-7: The standby clock of EC

In the figure 13-7, 77 pin of EC is the reset signal. The origin is:+V3AL through
R123 and C50 delays sent to the 2 pin high level of U10,U10 is synthetic, it will
output the high level of VCC1_POR#_3 from 4 pin, is shown in figure 13-8.
Figure 13-8: The reset production circuit of EC

The adapter is inserted the detection signal ADP_PRES to sent to U27,is shown
in figure 13-9,U27 is the OR gate, as long as there is a high level input to 1 pin
or 2 pin, it will output the high level. The high level output by the 4 pin of U27
is sent to EN1, EN2 of U28. U28 produces the standby voltage +V3A, +V5A
and supplies to VCCSUS3_3, V5REF_SUS of the South Bridge respectively.
(KBC_PW_ON is sent by EC after triggering the switch in the battery mode. In
the battery cell mode, there is no ADP_PRES, so there is no +V3A & +V5A
standby voltage in standby, it needs to be opened by KBC_PWR_ON after
triggering.)
Figure 13-9: The production of +V3A & +V5A
After the EC condition of standby being satisfied, its internal procedure

configures all of GPIO signals, output RSMRST# by GPIO07, is shown in
figure 13-10. RSMRST# phase with (connected together) the signal output by
30 pin of TPS51120 (as shown in figure 13- 9), then to/send to RSMRST# pin
of the South bridge, to inform the South bridge that the standby voltage is
normal at this time.
Figure 13-10: EC sends RSMRST#

Next, EC waits users to press the power key, then to complete the subsequent
trigger and power-on action, we will not explain.
13.3: Analysis of Inventec Feature/Special

Circuit
There is several more features of Inventec circuit, such as "OCP" circuit and
"Big OR GATE" circuit. OCP circuit is the over-current protection circuit, and
the "Big OR GATE" circuit, is the name called by the author. Let's look at the
working principle of these two special circuits.
13.3.1 Analysis of OCP circuit

As Inventec DosXX Dunkel 1.0 an example to explain OCP circuit in this
section. In the figure 13-11, +VBDC is the battery discharging port, through the
current sense resistor with 0.015Ω to make a new name +VBDCR, because the
resistance value is very small, two of voltage can be seen as the same.
(Calculated as 3 series battery connected in series, 3 x 3.7= 11 V, takes an
integer, is convenient to calculate).
Figure 13-11: The current sense resistor
In the figure 13-12, U505 is LM358, is the operational amplifier, ‘+’ is the non-
inverting input terminal, ‘-’ is the inverted input terminal. When V+>V-, outputs
VCC logic, when V+<V-, outputs GND logic. Note: GND with 4 pin is not
grounded, is connected to 11V of +VBDCR, that is to say, when V+<V- , the
output should be 11V. VCC power supply of 8 pin is from the voltage of
MAX_LX5 and +V5S lifting pressure. And produces the voltage about 16V on
the energy-storage capacitor, is higher than the GND terminal 11V to 5V, it can
satisfy the power supply requirement of the operational amplifier. ‘+’ terminal
of 3 pin is 11V of +VBDC.

It's worth noting that, the booster circuit is provided by +V5S through Q38, and
is controlled by ADP_PRES through Q39, that is to say, under the case of no
power or the adapter inserted, it cannot boost, and the operational amplifier is
not working.
The origin of the voltage of MAX_LX5 is the phase pin of+V5A voltage output
by the standby chip U28 in the figure 13-13, the square wave outputs. The
voltage of pulse crest value produced by the Q42 conducted is equal to the
voltage of +VBATP, the crest voltage is equal to 11V in the battery mode.
Figure 13-13: The origin of MAX_LX5
In the figure 13-12.the chip U504 is not 431 output by the ordinary 2.5V, is
431L of 1.24V (when ‘R’ and ‘C’ are connected together; it acts as an voltage-
regulator diode. the voltage of ‘R’ terminal is always higher than ‘A’ terminal to
1.24V). The ‘A’ terminal is also not grounded in the figure, connects +VBDCR
of 11V. So we can know that the ‘R’ terminal is A +l .24V=12.24V (VCC pin
of the operational amplifier through R516 to supply the electric power). 12.24
of REF terminal through three resistances to reach to ‘A’ terminal if there have
the differential pressure, and then there have the partial pressure:
100kΩ, 691Ω, 7.68kΩ series partial pressure, calculated that 2 pin of U505 is
11.095V. The specific calculation is:
[1.24V/(100kΩ+ 619Ω+7.68kΩ)*(619Ω+7.68kΩ) + 11V]
When the machine is normal, 11V of 3 pin is less than 11.095V of 3 pin. V+<V-,
1 pin outputs GND, is 11V through R517 to supply to the E pole of Q509,the B
pole is +VBDCR 11 V, the MOSFET is not conducted, the power amp
(following circuit) is no action.
When the power amp is short circuit, +VBDCR is pulled low. The R terminal of
431L is also lower, and then the voltage of 2 pin of the operational amplifier is
also low. When the voltage of 2 pin is less than 11V, the voltage of 3 pin of the
operational amplifier will higher than 2 pin, and outputs VCC is 16V. 16V to
the E pole of Q509 is higher than the B pole +VBDCR, then the triode
(MOSFET) is conducted. 16V will through the D17 conduction to reach to the
back comparator. The electric current calculation is 0.095V/0.015=6.3A, is the
large current.
As shown in figure 13-14,the voltage of 11 pin of the operational amplifier U2

is that +V5S through the resistance 133k Ω and 80.6kΩ resistance partial
pressure to obtain 1.88V,and through the voltage of 13 pin and 10 pin to
produce a sustaining voltage of 1.88V to 8 pin. 16V from D17 enter into 9 pin.
9 pin is higher than 8 pin, and outputs a OCP_OC of 3.3V from 14 pin.
Figure 13-14: The production circuit of OCP_OC#
One path of OCP_OC leads to EC; and another path reaches to the G pole of Q6.
Q6 is N channel field-effect tube, the high level will be conducted, OCP_OC#
will be pulled to the ground. OCP_ ON# leads to the South bridge, the South
bridge will send STPCLK# to stop the CPU internal clock after being pulled
low, makes CPU break off, and reduces the working current At this time. We
can clearly feel that the response speed of the system reduces a lot. At the same
time, OCP_OC is also controlled by PWR_GOOD_3, when PWR_GOOD_3 is
the low level, D8 is conducted, pulls OCP_OC low. That’s to say, when the
power-on sequence is not completed, OCP circuit is forbidden. Above is the
action process of OCP circuit in the battery mode. Next, it is look at OCP circuit
in the adapter mode.
In the figure, 13-15, when the voltage of LIMIT_SIGNAL becomes higher (not
original adapter) or the voltage of VBIAS reduces a certain extent. When the
voltage from Q22 conducted is higher than 1.88V, one path makes Q21
conducted, pulls the SRSET voltage low, stops charging, and another path
reaches to OCP execution circuit of U2, starts OCP_OC#.
Figure 13-15: The production of OCP_OC# in the adapter mode

LIMIT_SIGNAL is the current detection voltage of the adapter, the
manufacturer set it to be about 7V.VBIAS is the sampling voltage 5.79V got
from the adapter after through the resistance R108, R105, R104 partial pressure,
Figure 12-16: The production circuit of VBIAS
The whole OCP circuit is shown in figure 13-17.
Figure 13-17: The whole OCP circuit
13.3.2 Analysis of Big OR GATE
There have the design of "Big OR GATE" circuit (called by the author) in many
Inventec motherboard, in this section, as S-SERIES (HP_6531s) an example to
explain the "Big OR GATE" circuit. In the figure 13-18, +V3S is not pull-up
called usually.
Figure 13-18: The screenshot of the “Big OR GATE” circuit
In fact it's a node voltage, +V3S and +V5S through R130 and R131 to connect
together, and through R129 to be grounded. Then these two voltages input side
by side, and through the voltage division circuit output by a resistance. It can
calculate by the formula I1 + I2 = I3.
Calculated by the calculator: If the voltage of 3.3V and 5V is enough, then the
voltage is 2.189V after partial pressure, is shown in figure 13-19.
In the figure of circuit, the opposition terminal input of the comparator is

2VREF, thus we can calculate that +V3S cannot be less than 2.727V. The result
Figure 13-19 (left side): The computational process of the node voltage
Figure 13-20 (right side): The computational process of the threshold value of
+V3S
At the same time, we can calculate that +V5S cannot be less than 4.141V, is
shown in figure 13-21. So, this circuit is used to detect the voltage value of V3S
and V5S, in the figure 13-22. If VCCP_PG signal is low, it will cause R97 and
R129 parallel the value of resistance becomes lower (other signal is in a similar
way).
13-21: The computational process of the threshold value of +V5A
Figure 13-22: The screenshot of VCCP_PG circuit

By calculating, 10kΩ and 49.9kΩ are connected in parallel; their value of
resistance is just 8.33kΩ only. Now, even if the voltage of +V3S and +V5S is
enough, the voltage also cannot be higher than 2VREF. The actual result is just
0.674V only, is shown in figure 13-23. (In the figure, the value of resistance
synchronous reduced 1000 times).
Figure 13-23: The result of the node voltage when VCC_PG is low level
Chapter 14
Analysis of Intel PCH
Sequence (i3/i5/i7)
PCH is the platform controller hub. Intel PCH is the single bridge chipset in the
Intel company. The product of the first generation PCH is Intel 5 series, such as
Intel HM55 and so on. matches the first generation 13/15/17 CPU; the second
generation and the third generation is Intel 6 and Intel 7 series, matches the
second generation and the third generation 13/15/17 CPU, these two of
generations is almost the same, CPU is in common used. The newest fourth
generation has been released is Intel 8 series.PCH chip has all functions of the
original ICH, also has the function of management the engine of the original
MCH. It does not matter to call PCH the North Bridge or the South bridge. In
this chapter, we mainly introduce the main feature of Intel 5 series.6 series and
7 series sequence.
14.1: About Intel ME and Intel AMT

Intel ME is the Intel Management Engine, is the independent hardware inset the
North Bridge or PCH.ME firmware (ME FW) and the BIOS motherboard are
usually kept in the same chip, but they are independent mutually. The
architecture of Intel ME and ME firmware is shown in figure 14-1.
Figure 14-1: The architecture figure of Intel ME and ME firmware
Intel starts introduce the management technology called "iAMT" in ICHT. Intel
AMT (Intel Active Management Technology) is the embedded system
integrated in the chipset in effect, it does not depend the specific the operating
system. It is the biggest difference between iAMT and the remote control
software.
The embedded operating system of AMT technology integrates in the BIOS
chip, the function is realized by ME. This technology cannot to depend the real-
time status of the hardware. It can start up, maintain, shutdown independently
and other operation. Even if it’s in the system with crash, power off or blue
screen or even been closed, it can still work! Of course, it also can enter into
BIOS to operate. AMT needs to match the special server- side software to work.
Intel AMT technology can appear as a subsystem been independent of existing
operating system, because of the environment independent of the operating
system, when the operating system is broke down, the administrator can remote
monitoring and manage client-side. By this technology, the computer been
controlled also can remote manage and detect system when the operating
system is damaged or the system is broke down, or when the system goes wrong,
it can send the warning message ,to detect the software and hardware, remote
update BIOS and virus code and the operating system, even when the system is
power off, it can also manage work by the website, then it has worked out the
problem troubled IT manager: users closed the safety and management software
on the PC deliberately or by accident, which leads to unacceptable management.
These features can significantly reduce the administrative cost for the company
user.
When the system supported AMT is in the S5 sleeping state, ME module, the
clock chip Intel PHY LAN, SPI BIOS, MEMORY (CHANNEL0 DIMM0) need
to be powered on.
Inter Chipset starts from ICH8M, in the ACPI, dormant logical control signal is
added SLP_M #. The pin definition screenshot of SLP_M# is shown in figure
14-2.
Figure 14-2: The pin definition screenshot of SLP_M#

[Explanation] This signal is used to control the power of Inter AMT subsystem.
When the ME firmware does not exist, the timing step of SLP_M# is consistent
with SLP_S3# (while generating on / off). ICH8 & ICH9 also redefined the
functions of SLP_S4#, increased S4_STATE#. The pin definition screenshot of
SLP_S4# of ICH8 & ICH9 is shown in figure 14-3.
Figure 14-3: The pin definition screenshot of SLP_S4#
[Explanation] SLP_S4#: when the system is in the state of S4 &S5 sleeping, it

is used to control the switch (on/off) of the voltage controlled by itself.
Comment: when the system opens the AMT function, is used to control the
switch of the memory voltage. In the state of Ml (when the main platform is in
the state of S3~S5 and the subsystem of ME is running), SLP_S4# is forced to
be pulled up by SLP_M=.is used to open the memory voltage when the system
is in the state of AMT.
The pin definition screenshot of S4_STATE# of ICH8JCH9 is shown in figure

14-4.
Figure 14-4: The pin definition screenshot of S4_STATE#
[Explanation] the index signal of S4 state: when this signal is low level, it
means that the main platform is in the state of S4 or S5.When ME forced to pull
up SLP_S4#, this signal can be used to inform that the equipment system on-
board is in the state before S3.
It added CLPWROK from ICH starting, and renamed to be MEPWROK after 5

series chipset the 6 series chipset renamed to be APWROK. The pin definition
screenshot of MEPWROK is shown in figure 14-5.
Figure 14-5: The pin definition screenshot of MEPWROK
Explanation] ME Power Good: when this signal is effective, it means that ME

module supply has been stable.
When the AMT function is closed, the sequential relationship of each sleeping
control signal is shown in figure 14-6.After triggering, SLP_S5# is set up to be
high first, then SLP_S4# and S4_STATE# are set up to be high, SLP_S3# is set
up to be high at last, the timing sequence of SLP M# and SLP S3# is same.
Figure 14-6: When AMT function is closed, the timing sequence of each
sleeping control signal
When AMT function is opened, the timing sequence of each sleeping control
signal is shown in figure 14-7.SLP_M# is set up to be high in advance,
SLP_S4# is also set up to be high .After receiving triggering or other awakening
signal, SLP_S5# is set up to be high first, then S4_STATE# is set up to be high
to replace the original SLP_S4#, SLP_S3# is set up to be high at last.
Figure 14-7: When AMT function is opened. The timing sequence of each
sleeping control signal
When AMT function is opened, the logic of each sleeping control signal is
shown in the table 14-1.
When AMT function is opened, the system is in the state of S5 sleeping,

SLP_S4# is used to control the reservation of the memory voltage. SLP_M# is
used to control the clock chip, part of C-LINK, the reservation of Intel PHY
LAN, SPI BIOS or other voltage. We can open or shield AMT function in the
CMOS settings.
After PCH, SLP_S4# no longer follows SLP_M# to start, and cancel
S4_STATE#.When the chipset of PCH opened AMT function, only ME module,
network card and BIOS need to be supplied power.
The 5 series chipset still retains SLP_ M#, the 6 series chipset renamed it to be
SLP_A#, but it still used to control the power supply of ME module. The 5
series and 6 series chipset also add SLP_LAN#, the pin definition is shown in
figure 14-8.
Figure 14-8 the pin definition screenshot of SLP_LAN#
[Explanation] LAN subsystem sleeping control, when SLP_LAN# is ineffective.

The power of the network card must to be retained; when SLP_LAN# is
effective, the power supply of the network can be closed. When SLP_LAN# is
in the state of S0 and SLP_M#/SLP_A# is ineffective, it keeps being ineffective
all the time.
Added ACPRESENT adapter detection signal and SUS_PWR_DN_ACK signal,

Figure 14-9: The pin definition screenshot of ACPRESENT and

SUS_PWR_DN_ACK
[Explanation]
ACPRESENT: is used for the mobile system. The signal sent from EC, to indicate
that the power supply origin is alternating current or the system battery. The
high level refers to alternating current power supply.
SUS_PWRJDN_ACK: the signal sent from ME module to EC; the high level
means that it does not need to hang the power.
14.2: Analysis of Intel HM55 Series Chipset

Timing Sequence
The timing sequence of Intel 5 series chipset is shown in figure 14-10, the
explanation of the signal in the figure is below.
Figure 14-10: The timing sequence of Intel 5 series chipset
VCCRTC: 3V power supply sent from the motherboard to PCH Bridge,

supplies the power to RTC circuit of the bridge, to save the CMOS parameter.
RTCRST#/SRTCRST#: 3V high level sent from the mainboard to the bridge,

the reset signal of RTC circuit start from ICH9, there have two resets.
32.768kHz: the 32.768 kHz crystal next to the bridge, the bridge supplies the
power to the crystal, and the crystal supplies the frequency to the bridge.
VCCSUS3_3: the motherboard supplies the power to the bridge, 3.3V.

RSMRST#: the motherboard sent the ACPI reset signal with 3.3V high level to
the bridge, it means to inform the bridge that the standby voltage has been
normal at this time.
SUSCLK: the bridge sends 32.768 kHz clock if EC is built-in crystal, SUSCLK
is usually sent to EC, synchronous clock.
PWRBTN#: the bridge receives the falling edge trigger signal, 3.3V-OV-3.3V,
to inform the bridge that it can exit the sleep state.
SLP_S5#: after the bridge receiving PWRBTN#, set up SLP_S5# high to be
3.3V, it means that it exits the shutdown state.
SLP_S4#: the bridge set up SLP_S4# high to be 3.3V, it means that it exits the
sleep state.
SLP_S3#: the bridge set up SLP_S3# high to be 3.3V, it means that it exits the
standby state and enter the SO boot state.
SLP_M#: start from ICHS, added SLP_M#. It is sent by the bridge and used to
open the control signal of ME module, 3.3V.
If there have ME firmware on the mainboard, when it opens AMT function, this
signal will produce before triggered: when it closes AMT function, this signal
timing sequence is consistent with SLP_S3#.
If there have not ME firmware on the mainboard, not support AMT, SLP_M#
hung is not to be used.
SLP_LAN#: LAN subsystem sleeps control and controls the power supply of
the network card. If the Motherboard not uses Intel integrated network card, this
signal is not to be used. If the motherboard uses Intel integrated network card,
and supports network awaken, then this signal is high in the standby; when it
not supports the network awaken. This signal follows SLP_M# or SLP_S3#.
VCCME: the power supply (power supply to achieve AMT function) of ME

module, is controlled by SLP-M#. When SLP_M# is hung up (there haven't ME
module on the motherboard), VCCME uses the power supply of SO state
directly, such as the bus power supply and VCC3-3.
VDIMM: refers to the memory power supply, is controlled by SLP_S4#.
VCC: refers to the voltage in the SO state of the bridge power supply and the
bus power supply is controlled by SLP_S3#.
VCC_CPU: the motherboard sends the core power supply to CPU is also
controlled by SLP_S3#, it will delay.
SYS_PWROK: sent 3.3V high level to the bridge by CPU power management
chip is equal to VRMPWRGD.
PWROK: the motherboard sends 3.3V high level to the bridge, it means that
the voltage of S0 state is normal (the bridge an d the bus power supply).
MEPWORK: ME module power good, 3.3V. When there have ME firmware,
MEPWROK is controlled by ME module power supply; and when there haven't
ME firmware. MEPWROK connects together with PWROK.
LAN_RST#: after the network card power supply being normal, the
motherboard sent the reset signal to the network card controller of the bridge,
we can understand that it is the power good signal of the network card. If the
motherboard not uses Intel integrated network card, this signal is forced to be
grounded.
Clock Chip Outputs: the clock chip is opened and outputs each group of the
clock.
PROCPWRGD: the bridge sent PG to CPU, it means that the core voltage of
CPU is normal.
DRAMPWROK: the bridge sent PG to CPU, it means that the memory module
power supply of CPU is normal. Open drain outputs, it should be external
pulled up.
PLTRST#: the platform reset 3.3V sent by the bridge, as CPU reset by
conversing (is usually series partial pressure).
14.3: Analysis of The Chipset Timing Sequence

Above Intel HM65 Series
The timing sequence of Intel 6 series chipset is shown in figure 14-11.the
Figure 14-11: The timing sequence of Intel 6 series chipset
VCCRTC: sent 3V power supply to PCH bridge from the motherboard,

supplies the power to RTC of the bridge, to save CMOS parameter.
RTCRST#/SRTCRST#: sent 3V high level to the bridge from the motherboard,
the reset signal of RTC circuit. Start from ICH9 and there have two resets.
32.768kHz: 32.768 kHz crystal next to the bridge, the bridge supplies the power
to the crystal, and the crystal provides the frequency to the bridge.
VCCDSW3_3: the motherboard provides the deep sleep well power
supply to the bridge, 3-3V.When it not supports the deep sleep, this voltage
connects with VCCSUS3_3.
DPWROK: the motherboard sent 3.3V high level to the bridge, refers to the
VCCDSW3_3 power good, 3.3V. When it not supports the deep sleep, this
signal connects with RSMRST#.
SLP_SUS#: deep sleep state indicator signal, it can be used to open the voltage
of S5 state. Such as VCCSUS3_3.When it not supports the deep sleep,
SLP_SUS# is hung up.
VCCSUS3_3: the motherboard sent the standby power supply to the bridge,
3.3V.
RSMRST#: the motherboard sent ACPI reset signal of 3.3V high level of the
bridge, to inform the bridge that the standby voltage is ready now.
SUSCLK: the bridge sent 32.768 kHz clock, but it not necessarily be adopted
by the motherboard.
PWRBTN#: the bridge received the falling edge trigger signal,3.3V-OV-

3.3V,informed the bridge that it can exit the sleep state.
SLP_S5#: after the bridge receiving PWRBTN#, set up SLP_S5# to be 3.3V,it

means that it exits the shutdown state.
SLP_S4#: the bridge sets up SLP_S4# to be 3.3V, it means that it exits the
sleep state.
SLP_S3#: the bridge sets up SLP_S3# to be 3.3V, it means that it exits the
standby state, and Enters the SO boot state.
SLP_A#: The bridge sent the power open signal of the active sleep circuit, used
to open ME module power supply.
If there have ME firmware on the mainboard, when it opens AMT function, this
signal will produce before triggered; when it closes AMT function this signal
timing sequence is consistent with SLP_S3# .
If there haven't ME firmware, it is not support AMT, SLP_A# hung not uses.
SLP_LAN#: LAN subsystem sleeps control; controls the network card power
supply. If the motherboard not uses Intel integrated network card, this signal is
not adopted. lf the motherboard uses Intel integrated network card, and supports
the network awaken, this signal is high when it is in standby; when it not
supports the network awaken, this signal follows SLP_A# or SLP_S3#.
VCCASW: the power supply of the active sleep circuits controlled by SLP_A#.
When SLP_A# is hung up (there haven't ME firmware on the mainboard),
VCCASW adopts the power supply of S0 state directly.
VDIMM: refers to the memory power supply, is controlled by SLP_S4#.
VCC: refers to the voltage of SO state or the main power supply or others of the
bridge is controlled by SLP_S3#.
PWROK: the motherboard sent 3.3V high level to the bridge. It means that the
voltage of S0 state is ready for the bridge and the bus power supply.
APWROK: ASW power good. When it opens AMT function, APWROK is

controlled by AMT voltage, when it closes AMT function. APWROK is
consistent with PWROK.
DRAMPWROK: the bridge sent PG to CPU. Informs CPU that memory

module power supply is ready.
25MHz Crystal Osc: 6 series chipset has not available the clock chip; the
bridge added 25MHz crystal to supplied the reference frequency to the external
clock module.
PCH Output Clocks: the bridge outputs each group of clock.
PROCPWRGD: the bridge sent PG to CPU, it means that the non-core voltage
of CPU is ready.
CPU SVID: CPU_SVID is a group of signal sent to CPU power supply chip by
CPU. It is function of the standard serial bus consisted of DATA and CLK and
ALERT# signal with the function of reminder; it is used to control CPU core
voltage and the integrated graphics power supply.
After PROCPWRGD being effective, CPU sent SVID.
VCCCORE_CPU: the core voltage of CPU.
SYS_PWROK: CPU power supply chip sent 3.3V high level to the bridge it
means that CPU core voltage is ready.
PLTRST#: the bridge sent the platform reset 3.3V, as CPU reset by conversing.
The timing sequence of Intel 7 series and 8 series is almost consistent with Intel
6 series. We don't explanation it again.
Chapter 15
Analysis of ASUS K42JR
(HM5x) Timing Sequence
ASUS K42JR uses Intel 5 series chipset. We will analyze the standby and the
power-on timing sequence under the adapter mode, because RTC circuit is
almost the same, so we do not explain in this chapter.
15.1: The Standby State

First, the adapter insert, outputs A/D_DOCK_IN, is shown in figure 15-1.
Figure 15-1: The screenshot of the adapter interface circuit
AD_DOCK_IN is sent to the S pole of PQ8901,through PR8902 and PR8901 of

partial pressure into 9.5V to control PQ8901 conducted directly to produce
CHG_VCC, is shown in figure 15-2.
Figure 15-2: The production of CHG_VCC
CHG_VCC_GATE comes from the ACOK pin of the charging chip

MB39A132,is shown in figure 15-3.ACOK needs to output the low level, then it
will make CHG_PATH_19 through PR8904 and PR8906 partial pressure to get
the relative low level of 6V.
Figure 15-3: ACOK circuit

According to the internal block diagram of MB39A132, if ACOK needs to
output the low level, the internal comparator must output the high level to
conduct NPN triode. That is to say, ACIN should be higher than the threshold
value of the adapter detection, is shown in figure 15-4.
This value of the voltage is 1.25V (rising edge), in the data manual of
MB39A132 the threshold value of AC adapter detection is shown in figure 15-5.
The relationship between ACIN and ACOK is described as shown in figure 15-
6,that is to say, if ACIN is higher than 1.25V,then ACOK will output the low
level.
Figure 15-4: ACOK internal control logic of MB39A132 (left side)

Figure 15-5: The screenshot of electrical features of AC adapter detection in the
data manual of MB39A132
Figure 15-6: The part of function of the adapter defection of MB39A132

In the K42JR, the power supply VIN of the chip comes from CHG_VCC, VCC
comes from the common point is shown in figure 15-17. In the adapter mode,
VCC will not be higher than VIN, so we can think that be power supply of the
chip is VIN.
Figure 15-7: The screenshot of ACIN circuit

ACIN of the chip comes from the CHG_VCC to through the PR8911 and
PR8915 partial pressure, according to calculating, the voltage of CHG_VCC is
not less than 17.4V, ACOK will output the low level.
The low level of ACOK will make CHG_VCC_GATE partial pressure to be
established, PQ8902 conducted, and produced the large current
CHG_PATH_19V, through PR8903 to produce the common point voltage
AC_BAT_SYS, is shown in figure 15-8. At the same time, CHG_VCC will be
added to the G pole of PQ8903, PQ8903 is cut off, and the battery is isolated.
Figure 15-8: The principle figure of the battery isolation
AC_BAT_SYS enters into VIN of RT8205, through PR8117 to enter into EN

pin shown in figure 15-9.According to the working principle of RT8205, it will
produce REF, VREG3, VREG5.
Figure 15-9: RT8205 gets VIN and EN

VREG3 outputs +3VAO, through the jumper to renamed it to be +3VA is
Figure 15-10: +3VAO renamed to be +3VA

One path of +3VA through D2001 to replace CMOS battery and produce
+VCC_RTC to supply to RTC circuit of PCH, is shown in figure 15-11.
Figure 15-11: +3VA supplies the power to +VCC_RTC
Another path of +3VA through the inductance L3001 to produce +3VA+EC, is

Figure 15-13: +3VA_EC renamed to be +3VACC

+3VA_EC supplies the standby voltage to 74 pin of EC (U3001), is shown in
figure 15-14.
Figure 15-14: EC gets the standby power supply

EC supplies the power to X3001 crystal from 2 pin, the crystal oscillation sends
back the frequency to 128 pin of EC, is shown in figure 15-15.
+3VA_EC through R3023 and C3010 delays circuit to supply the reset signal to
EC, is shown in figure 15-16.This signal is controlled by FORCE_OFF#, when
it is lack of the voltage or the temperature is too high later, it will pull the reset
of EC low to realize outage.
Figure 15-16: The production circuit of EC reset
In the K42JR, EC will send the high level of VSUS_ON automatically after
receiving the standby voltage, controls PQ8105B conducted, pulls 2 pin of
PQ8105A low, then PQ8105A keeps to be cut off, ENBL signal is not grounded
and into the hung state, is shown in figure 15-17(symbol ‘@’ means that the
component is not installed).
Figure 15-17: The production circuit of ENBL
When ENBL is hung up, PD8102 will be cut off. The standby power manages
ENTRIP1 pin and ENTRIP2 pin of the chip RT8205, through R8102 and R8103
grounded to set respectively the over current threshold value of two path of
PWM as the open signal of two path of PWM at the same time, is shown in
figure 15-18. After PWM open (starts) signal of RT8205 being normal, then
outputs two path of PWM: +3VSUS and +5VSUS, to send to the standby
voltage pin of the bridge.
Figure 15-18: The production circuit of the open signal of RT8205

In addition, +5VSUS voltage and P_+5VSUS_LG_20 (comes from the down
tube G pole of 5VSUS circuit, is 0V-5V of pulse square wave) through twice
bootstrap to produce +12VSUS voltage, is shown in figure 15-19.
Figure 15-19: The production circuit of +12VSUS
RT8205 outputs+3VSUS to send to U2801 (BIOS), is shown in figure 15-20.

After BIOS getting the power supply, EC starts to read BIOS program and
configure the pin. Note: by the actual measurement, only have the instantaneous
waveform, not the continuous waveform.
After EC finish reading BIOS, it will detect the adapter, the specific is shown in
figure 15-21 :after the voltage of adapter being higher than 14.37V, through
PR8931 and PR8932 partial pressure to make PQ8907 conducted, pull
AC_IN_OC# low, to send to EC as the adapter detection signal. If EC can
identify the adapter inserted (AC_IN_OC# is low), it will keep the high level of
VSUS_ON (shown in figure 15-22); if EC doesn't detect the adapter, it will pull
VSUS_ON low, and close +3VSUS and +5VSUS, then, BIOS will be out of
voltage. In the figure 15-23, after VSUS_ON being set up automatically, it does
not identify the adapter in 750ms, VSUS_ON is pulled low.
Figure 15-20: BISO circuit
Figure 15-21: The production circuit of adapter detection signal
Figure 15-22: VSUS_ON waveform figure after detecting the adapter
Figure 15-23: VSUS_ON waveform figure when not detect the adapter
RT8205 open drain outputs SUS_PWRGD signal after the standby voltage
being stable is shown in figure 15-24.
Figure 15-24: The circuit screenshot that RT8205 outputs PG

SUS_PWRGD is pulled up to be high level by PR8602, and sent to EC at last,
to inform EC that the standby voltage is normal, is shown in figure 15-25.
Figure 15-25: The circuit screenshot that EC received SUS_PWRGD
EC sends the high level of PM_RSMRST# to PCK, informs that its standby
voltage has ready. After PCH standby condition being normal, ME module in
PCH internal outputs the high level ME_SusPwrDnAck signal, sends to EC. EC
sends ME_ACPRESENT_PCH signal to PCH, informs PCH that AC adapter
inserts at this time, is shown in figure 15- 26.
Figure 15-26: The screenshot of the signal between EC and PCH
15.2: Trigger
Users press the power key, producing the boot trigger signal PWR_SW# to 125
pin of EC, is shown in figure 15-27.
Figure 15-27: EC received PWR_SW#

EC sends PM_PWRBTN# to PWRBTN# of PCH,PCH sends SLP_S5#,
SLP_S4# and SLP_S3# ,SLP_S5# and SLP_M# are not adopted, SLP_S4# and
SLP_S3# renamed to be PM_SUSC# and PM_SUSB#, sent to EC, is shown in
figure 15-28.
Figure 15-28: The PCH trigger circuit
15.3: The Boot State

After EC receiving PM_SUSC# and PM_SUSB#, sends SUSC_EC# and
SUSB_EC#, is shown in 15-29.
Figure 15-29: EC received the power-on instruction

The high level of SUSC-EC# controls NPN transistor of PQ8504 conducted,
after 6 pin being pulled low, PNP transistor also conducted, +12VSUS flows E
to C from the transistor, to produce +12V, is shown in figure 15-30. +12V
through PR8507 send to the G pole of PQ8512, PQ8512 conducted completely,
+5VSUS converted to +5V.
Figure 15-30: SUSC_EC# control circuit
The high level of SUSC_EC# is also sent to PD9101, makes it to be cut off is
shown in figure 15-31.EN/DEM of RT8202A (PU9101) is hung up, according
to the manual of RT8202A, the hung is the open. After the power supply of
RT8202A being satisfied and EN/DEM being hung up, RT8202A controls to
output +1.5V.After +1.5V being normal, the chip open drain outputs -
1.5V_PWRGD and is pulled up to be high by +3VS produced later.
Figure 15-31: +1.5V control circuit
EC sends SUSB_EC# to PQ8503, controls to output +12VS, +12VS is added

respectively to the G pole of PQ8510, PQ8509, PQ8513, and controls to
produce +5VS, +3VS, +1.5VS, is shown in figure 15-32.
Figure 15-32: The production circuit of +5VS, +3VS and +1.5VS

5VS voltage is sent to UP7711 (PU9103) as the control voltage, after the chip
receiving +1.5V power supply and 0.75V reference voltage produced by +1.5V
partial pressure, the chip outputs 0.75VS, is shown in figure 15-33.
Figure 15-33: The production circuit of 0.75VS
EC sends the high level of SUSB_EN# to UP7706 (PU8402A) at the same time,
is used to control produce +1.8VS, then open drain outputs 1.8VS_PWRGD, is
Figure 15-34: +1.8VS control circuit

+1.5V_PWRGD and 1.8_PWRGD phase produce SYSTEM_PWRGD, is
Figure 15-35: The production circuit of SYSTEM_PWRGD

SYSTEM_PWRGD through PR8301 send to RT8202 (PU8301), control
outputs +VTT_CPU, +VTT_PCH, is shown in figure 15-36. After the voltage
production being normal, the chip sends +VTT_CPU_PWRGD.
After +VTT_CPU_PWRGD through the resistance PR8651 and PR8652 partial

pressure, produces H_VTTPWRGD to send to CPU, is shown in figure 15- 37.
+VTT_CPU_PWRGD through the inductance PL8650 renamed to be
ALL_SYSTEM_PWRGD to EC.
Figure 15-36: The production circuit of VTT_CPU & VTT_PCH
Figure 15-37: The differentiation circuit of +VTT_CPU_PWRGD

After CPU receiving +VTT_CPU and H_VTTPWRGD, sends GFX_VRON and
GFX_VID to RTS152 (PU9201A), opens the core voltage of the built-in
graphics cards +VGFX_CORE, is shown in figure 15-38.
Figure 15-38: The production circuit of the integrated graphics power supply
After ALL_SYSTEM_PWRGD being sent to EC, EC delays 99ms send CPU

core voltage open signal CPU_VRON. This signal is sent to VRON pin of
RT8856 (PU8801A), is used to open CPU core common point +VCORE. After
+VCORE production being normal, the chip outputs VRM_PWRGD and
CLK_EN#, is shown in figure 15-39.
Figure 15-39: The screenshot of CPU core voltage power supply circuit
One path of VRM_PWRGD is phased with ALL_SYSTEM_PWRGD to use to

the under voltage protection circuit for the motherboard, the specific protection
function is shown in figure 15-40, if any path of ALL_SYSTEM_PWRGD or
VRM_PWRGD is low level, PD8603 will be conducted, and pull the G pole of
PQ8601A low, PQ8601A is cut off. EC sends SUSB_EC= with 3.3V through
PR8604 to charge PC8601, according to the time constant to calculate. The G
pole of PQS601B will be higher than 3V about 2.6s lateral's enough to make
PQ8601B conducted, and pull FORCE _OFF# low. That is to say, after 2.6s, if
ALL_SYSTEM_PWRGD and VRM_PWRGD have not turned into the high
level, this circuit will pull FORCE_OFF# low, then pull EC_RST# low, to
realize mandatory outages. (FORCE_OFF# and EC_RST# connect together
through 0Ω resistance, shown in the part of EC reset circuit in 15.1).
Figure 15-40: The under voltage protection circuit
In fact, when PQ8601B acts as the function of the switch, the G pole does not
need to rise to 3.3V,the G pole threshold value of this field effect tube is about
1.2V.So, ASUS motherboard will usually power off after power on 1s more
later, which caused by this circuit. During repairing, we can adopts the means of
increasing the capacitance of PC8601, short circuit PC8601, dismantling
PQ8601 and PD8603 to get rid of the power- off protection features, and
gradually to trace each power supply. Find out the failure components cause to
powering down.
Another path of VRM_PWRGD is sent to EC. CLK EN# sends the clock circuit,
shown in the section of Analysis in 15.4.
After the power supply of PCH being normal, PCH sends the high level of
DGPU_PWR_EN# to make PD8520 cut off,+3VS pulls up
P_+VGA_VCORE_EN directly. One path of P_-VGA_VCORE_EN is sent to
EN/DEM of PU8201,to control produce the core power supply -VGA_VCORE
of the independent graphics cards, is shown in figure 15-41.After the core
power supply of the independent graphics cards being normal,PU8201 sends
VGA_VCORE_PWRGD.
Figure 15-41: The production circuit of the core power supply of the
independent graphics card (Discrete)
Another path of P_+VGA_VCORE_EN controls Q7601 conducted, makes

R7603 grounded .The G pole of Q7602 receives the low level after +3VS partial
pressure, Q7602 is conducted, and produces +3VSG, is shown in figure 15-42.
Figure 15-42: The production circuit of +3VSG
After the core power supply of the independent graphics being normal, PU8201
sends VGA_VCORE_PWRGD to UP7706 (PU8403A) to open +1 VS, is shown
in figure 15- 43.
Figure 15-43: The production circuit of +1VS

VGA_VCORE_PWRGD is also sent to PQ8560, by conversing to control
+0.75VSG, +1.5VDG, +1.8VSG, is shown in figure 15-44.
Figure 15-44: The production circuit of +0.75VSG, +1.5VSG & +1.8VSG

VGA_VCORE_PWRGD is also conversed to be PARK_PWRGD_PCH
to send to PCH, informs PCH that the graphics cards has ready at this time, is
Figure 15-45: The production circuit of PARK_PWRGD_PCH
VGA_VCORE_PWRGD is sent to Q7504 at the same time, makes it conducted,

and produces low level of PARK) PECLK_ REQ# to PCH, requests to send
100MHz bus clock of the graphics cards, is shown in figure 15-46.
Figure 15-46: The production figure of the graphic card clock request signal
15.4: Clock, PG & Reset

After +VCORE voltage production being normal, RT8856 chip outputs
CLK_EN# through CQ2 to reverse to be the high level of CLK_EN, is shown in
figure 15-47. This signal is sent to the clock IC (ICS9LPRS427) to open the
clock.
Figure 15-47: The production circuit of the clock open signal

After the clock, 1C opening work, producing each clock to PCH, then produced
each clock by PCH built-in clock to the peripheral. The block diagram of PCH
built-in clock is shown in figure 15-48.
Figure 15-48: The block diagram of PCH built-in clock

After +VCORE voltage production being normal, RT8856 chip outputs
VRM_PWRGD to EC, EC delays send PM_PWROK, is shown in figure 15-49.
Figure 15-49: EC sends PM_PWROK

PM_PWROK is conversed to be PM_PWROK_PCH, is shown in figure 15-50.
Figure 15-50: PM_PWROK renamed to be PM_PWROK_PCH
PM_PWROK_PCH is sent to MEPWROK, SYS_PWROK and PWROK pin of

PCH, is shown in figure 15-51.
Figure 15-51: PCH received three PG

After PCH receiving PWROK, sends DRAMPWROK signal to CPU; in the
PCH internal, PWROK phase with SYS_PWROK logic, to produce
PROCPWRGD to CPU. PCH sends PLTRST#, renames to be BUF_PIT_RST#,
through R0318, R0319 partial pressure to be 1.1V to CPU.PG and the reset
reception of CPU is shown in figure 15-52.
Figure 15-52: PG and Reset signal reception of CPU
Chapter 16
Analysis of APPLE A1286
Apple A1286 (K18), the mainboard part number is 820-2850, it's the product
used Intel 5 series chipset. In this chapter, detailed analysis of the standby and
power- on timing sequence of Apple laptop.
16.1: G3 State
First insert the adapter to produce PPDCIN_G3H, is shown in figure 16-1.
Figure 16-1: The adapter enters to a circuit

The adapter access socket of Apple needs a small adapter, the access of the
power head (connector) is the magnet attracting type. There have 5 contacts:
both ends are grounded, the middle most is the adapter ID information
identification and the other two roots are the positive & negative of the power
supply, the specific kind is shown in figure 16-2.
Figure 16-2: The kind of the Apple adapter

PPDCIN_G3H through the body diode of Q7080 to produce
PPDCIN_G3H_OR_PBUS is shown in figure 16-3. (In the battery mode, the battery
through the body diode of Q7055 and through the top tube Q7030 of the charging
circuit, then through the body diode of Q7085D to supply the power to
PPDCIN_G3H_OR__PBUS).
Figure 16-3: The production circuit of PPDCIN_G3H_OR_PBUS

PPDCIN_G3H_OR_PBUS supplies the power to VIN of U6990 (IT3970),and is
added to EN directly, the chip outputs PP3V42_G3H,is shown in figure 16-
4.This is a step-down switching regulator, internal integrates the booster and the
clamping diodes. The pin definition VIN means the power supply, EN means
the open, and RT means the oscillation setting. BOOST means start boot-strap
pin, SW means phase/output pin. FB means feedback, BD connects the internal
boost diode and the voltage regulator.
Figure 16-4: The production circuit of PP3V42_G3H

PP3V42_G3H supplies the power to VR5020, VR5020 outputs
PP3V3_S5_AVREF_SMC, is shown in figure 16-5.
PP3V42_G3H supplies the power to AVCC of EC, PP3V3_S5_AVREF_SMC
supplies the power to AVREF of EC, is shown in figure 16-6.
Figure 16-5: The circuit screenshot of VR5020
Figure 16-6: EC received the power supply

After EC receiving the standby power supply, to supply the power to Y5010,
and produces 20MHz clock to EC, is shown in figure 16-7.

PP3V42_G3H inputs the voltage to U5000, U5000 is a voltage detection/delay
chip, the chip through C5001 charging delayed, when the voltage rises above
the threshold value, OUT pin open drain outputs, SMC_RESET_L is pulled up
to be 3.42V by R5000 to EC reset, is shown in figure 16-8
Figure 16-8: The production circuit of EC reset
In the figure 16-8, there have a circuit of hand reset EC: when EC program is
disordered, we can achieve the mandatory reset EC through the circuit of U5001
and Q5032 (shown in figure 16-9).while pressing the left SHIFT key, the left
OPTION key and CONTROL key, sends to U5703 to produce the low level of
SMC_TPAD_RST_L. Then press the switch to produce the low level of
SMC_ONOFF_L, together with SMC_TPAD_RST_L to send to U5001,
outputs the high level of SMC_TPAD_RST, controls Q5032 conducted, and
pulls SMC_RESET_L low.
Figure 16-9: The circuit screenshot of U5703

After the EC standby power supply, clock and reset all being normal, it will
reads their own program.
When insert the adapter, PPDCIN_G3H through D7005 and R7005 to supply
the power to DCIN of the charging chip ISL6259, and through R7010 and
R7011 partial pressure to ACIN, is shown in figure 16-10. After ACIN voltage
being higher than 3.2V, ISL6259 outputs the low level of AGATE to make
Q7085 conducted, and start PWM control produce the common point
PPBUS_G3H with 12.6V(the common point voltage setting: PP3V42_G3H
through R7012 to pull up CELL to set to be 12.6V). After the charging chip
detecting that the current flowed through R7020 is higher than 0.4A (the adapter
current sense resistor R7020 voltage drop 8mV), drive SGATE is low level;
when the current is less than 0.15A (the adapter sense resistor R7020 voltage
drop 3mV), drive SGATE is high level.
Figure 16-10: The screenshot of the charging chip circuit & location
The common point production method is different with other brand machines.
In the figure 16-11, it is adopts a hybrid power supply scheme: the voltage of
the adapter needs to be regulated by the charging chip to produce a common
point, the voltage is equal to the battery voltage. The advantage is that it no
needs to change any circuit and directly support Intel core technology.
Figure 16-11: The production method for Apple Laptop Common Point
After U7000 detecting that ACIN is higher than 3.2V, it will open drain output
SMC_BC_ACOK. One path of SMC_BC_ACOK is sent to EC, means that the
adapter inserted, another path is sent to OR GATE U6901 to produce
SMC_BC_ACOK_VCC to supply the power to MAX9940 (U6900), is shown
in figure 16-12.
MAX9940 is a signal line over-voltage protector, the simple principle: DC over-

voltage protection, when EXT voltage is higher than VCC +0.26V (the
threshold value is shown in figure 16-13), the chip disconnects 4 pin and 5 pin,
that is to say,5 pin of the adapter interface J6900 isolated from SYS_ONEWIRE
of EC, to prevent damage to EC; when VCC= 0V, EXT has the protective range
of -0.7~28V; the chip can prevent ±4kV static electricity.
ONE-WIRE is a single wire serial bus, is used to transfer the adapter

information. After EC reading the parameter of the adapter through ONE-WIRE
bus, the green light on the adapter is on.
Figure 16-12: The circuit screenshot of MAX9940
Figure 16-13: The screenshot of the description of the electrical features of EXT
threshold value in the MAX9940 data manual
Figure 16-14: The internal structure of the MAX9940

Tips: ONE-wire is a unique single bus (l-Wire Bus) technology launched by the
US Maxim wholly owned subsidiaries Dallas Semiconductor Corporation,
Dallas (DALLAS SEMI CONDUCTOR).This technology is different with
SPI,PC,SCI bus, it adopts the a single signal line, it can transmit the clock and
the data, and the data transmission is bidirectional, so the single bus technology
has the advantages of simple circuit, low hard overhead, low cost, convenient
for bus expansion and maintenance, etc.
16.2: RTC Circuit

The origin of VCCRTC of this machine is supplied the power directly by
PP3V42_G3H, no CMOS battery, is shown in figure 16-15.
Figure 16-15: The power supply of VCCRTC

RTCRST# and SRTCRST# comes from the delayed of the following circuit,
other two signals of RTC circuit are INTRUDER# and INTVRMEN#, is pulled
up by 3.42V, is shown in figure 16-16.
Figure 16-16: The screenshot of RTC circuit

RTC crystal 32.768KHz of PCH is Y2810, is shown in figure 16-17.
Figure 16-17: RTC Crystal circuit
16.3: S5 State
After EC detecting that the adapter exists (SMC_BC_ACOK is high level),
sends the high level of SMC_PM_G2_EN,at the same time, it will send
SMC_ADAPTER_EN to PCH, to tell PCH that the adapter has inserted, is
Figure 16-18: EC sends SMC_PM_G2_EN signal
SMC_PM_G2_EN is sent to ENO of TPS51125 through R7272, as a linear

open, is shown in figure 16-19.The common point voltage PPBUS_G3H is sent
to 16 pin VIN as the main power supply, TPS51125 outputs two paths of linear
power supply, VREG3 and VREG5. VREG3 is not to be used, VREG5 output
voltage is PP5V_S5.
Figure 16-19: The circuit screenshot of standby power supply
PP5V_S5 through R2400 to produce PP5V_S5_PCH_V5REFSUS, is shown in

figure 16-20. PP5V_S5_PCH_V5REFSUS supplies the power to 5V standby
voltage V5REF_SUS of the bridge.
Figure 16-20: The production circuit of PP5V_S5_PCH_V5REFSUS

SC_PM_G2_EN also converted to be P3V3S5_EN, is shown in figure 16-21.
Figure 16-21: The production of P3V3S5

The high level of P3V3S5_EN controls 6-1 pin of Q7211 to be conducted,3-4
pin will be cut off,6 pin ENTRIP2 of TPS51125 will be grounded through the
resistance R7206,sets the over current protection threshold value of the second
path PWM controller, is shown in figure 16-22.
Figure 16-22: The control circuit of the standby chip ENTRIP2

TPS51125 internal supplies pull-up to ENTRIP2.partial pressure with R7206
into a high level to open the second path PWM of the chip. Produces PP3V3_S5,
is shown in figure 16-23. (There is only a 3.3V inductance power on when this
machine is in standby. And 5V inductance is no power. PP3V3_S5 is sent to
VCCSUS3_3 of PCH at last; as the standby power supply of the bridge.
After PP3V3_S5 being normal, U7940 through 5 pin to detect PP3V3_S5, is

Figure 16-23: The production circuit of PP3V3_S5
Figure 16-24: PP3V3_S5 detection circuit
According to the pin definition of TPS3808G33 (shown in figure 16-25), 5 pin

is the voltage detection pin. When this pin is less than the threshold value VIT
, RESET* is effective.
Figure 16-25: The screenshot of the pin definition of TPS3808G33
The threshold value of TPS3808G33 detection voltage is 3.07V, is shown in

figure 16.26.
Figure 16-26: The screenshot of description of the electrical features of the

voltage detection threshold value in the TPS3808G33 data manual
The high level of RSMRST_PWRGD is sent to EC, after EC receiving
RSMRST_PWRGD, sends PM_RSMRST_L to the bridge, is shown in figure
16-27.
Figure 16-27: The related circuit of RSMRST#
In the figure 16-27, there is a power-on condition of PCH: BATLOW*.This

signal is low battery indicator. When this signal is low level, PCH forced to
enter S5 state. When it works normally, it must be high level, is pulled up by
PP3V3_S5, and controlled by EC. EC needs to detect the battery, and then it
will set high PM_BATLOW_L, is shown in figure 16-28.
Figure 16-28: BATLOW# circuit trigger
16.4: Trigger
The power switch of this machine is on the keyboard, is shown in figure 16-29,
press the switch, producing the low level of pulse signal SMC_ONOFF_L.
Figure 16-29: The keyboard interface
SMC_ONFF_L is sent to J4 pin of EC, after EC receiving SMC_ONOFF_L,

sends PM_PWRBTN_L from D10 pin, is shown in figure 16-30.
Figure 16-30: EC received the trigger signal
PM_PWRBTN_L is sent to PWRBTN* pin of PCH, is shown in figure 16-31.
Figure 16-31: PCH received the trigger signal
16.5: S3 and S0 State

After the bridge receiving PM_PWRBTN_L, it will send SLP_S5#, SLP_S4#,
SLP_S3#, SLP_M#, is shown in figure 16-32. This machine not supports Intel
AMT, SLP_M# is not used.
Figure 16-32: PCH send each power-on signal

PM_SLP_S5_L is sent to EC; PM_SLP_S4_L is also sent to EC, at the same
time sent to Q7812 through converted control to produce PP3V3_S3 voltage, is
shown in figure 16- 33.

PM_SLP_S4_L also converted to be P5VS3_EN and DDRREG_EN, is shown
in figure 16-34.
Figure 16-34: PM_SLP_S4 renamed

DDRREG_EN is sent to S5 pin of TPS51116, this is a typical memory power
supply chip, and it will output PWM power supply PP1V5_S3 and
PPVTTDDR_S3, is shown in figure 16-35. After the memory main power
supply and the reference voltage being normal, TPS51116 will output
DDRREG PGOOD.
Figure 16-35: The memory power supply circuit
P5VS3_EN is converted to control 1 pin of TPS51125, is used to control

produce PP5V_S3, is shown in figure 16-36. After PP5V_S3 being normal,
TPS51125 will send P5V3V3_PGOOD (after previous PP3V3_S5 producing,
PG of TPS51125 will not output, only when 5V is normal, it will open drain
outputs PGOOD).
Figure 16-36: The production circuit of PP5V_S3
PM_SLP_S4_L is also sent to Q4690, it is used to control produce USB power

supply PP5V_S3_RTUSB_A_ILIM, PP5V_S3_RTUSB_B_ILIM, is shown in
figure 16-37.
Figure 16-37: The production circuit of USB power supply

The bridge sends SLP_S3#, it is renamed to be PM_SLP_S3_L, in addition to
EC, it is also sent to the following places.
Control the production of PP3V3_S0, is shown in figure 16-38. Control
production of PP5V_S0, is shown in figure 16-39.
Figure 16-39: The production circuit of PP5V_S0
Control to open the 3.3V network card power supply PP3V3_ENET, and
produce PM_ENET_EN, is shown in figure 16-40.Here refers only in the
condition of the function of the network awaken been closed to be used to open
the network card power supply. If open the function of network awaken, and is
in the adapter state, Q7920 will be conducted, and pull PM_ENET_EN_L low,
and open ENET voltage.
Figure 16-40: The control of the network card power supply
Controlling open U9480 to produce PP3V3_SO_DPPWR to DP interface J9400

power supply (J9400 is Mini Display Port), is shown in figure 16-41.
Figure 16-41: The production of DP interface power supply

Controlling 5315 conducted, converted the common point voltage PPBUS_G3H
to be PPBUS_G3H_VSENSE, then through partial pressure to produce
SMC_PBUS_VSENS to EC, is used to detect the common point voltage, and is
Figure 16-42: The screenshot of the common point voltage detection circuit
PM_SLP_S3_L through the resistance R3210 to pull up MEMVTT_EN, when

the subsequent platform reset PIT_RESET_L is effective, control 3 pin and 4
pin of Q3210 to be conducted, or ISOLATE_CPU_MEM_L is the high level to
control Q3200 conducted, and produces the low level of MEMVTT_EN_L to
control 6 pin and 1 pin of Q3210 cut off, MEMVTT_EN is pull up by
PM_SLP_S3_L, is sent to U7300, and U7300 receives PP0V75_S0_DDRVTT
output from VTT of 24 pin.
0
Figure 16-43: The control circuit of the memory VTT voltage

PM_SLP_S3_L will also through the circuit in the figure 16-44 to
convert to P1V8S0_EN, P1V2S0_EN, CPUVTTS0_EN and PlV5CPU_EN, is
Figure 16-44: PM_SLP_S3_L renamed
Figure 16-45: The production of P1V5CPU_EN

P1V8S0_EN is sent to U7720 to open PP1V8_S0, is shown in figure 16-46.
P1V2S0_EN is sent to U7850, makes it send the control signal of 7 pin to drive
Q7850 to produce PPlV2_S0, is shown in figure 16-47.
In the figure 16-47, the output voltage 1V2_ENET of Q7850 is output by

PM_ENET_EN controlling U7760, is shown in figure 16-48.
Figure 16-48: The production circuit of PP1V2_ENET
CPUVTTS0_EN is sent to U7600 control output PPlV05_SO, is shown in

figure 16-49.
P1V5CPU_EN is sent to U7801, controls Q7801 to convert PP1V5_S3 power

supply of the memory to be PP1V5_S3RS0 to supply the power to CPU, is
Figure 16-50: The production circuit of PP1V5_S3RS0

After the previous voltage all being normal, U7971detects PP3V3_S0,
PP1V5_S3RS0, PP1V05_S0, and after being higher than each threshold value,
RST# open drain outputs S0PGOOD_PWROK, is shown in figure 16-51.
Figure 16-51: The voltage detection circuit
S0PGOOD_PWRO phased with PG output by other power supply chip, and is

pulled up to be S0_PWR_PGOOD by PP3V3_S0, is shown in figure 16-52.
S0_PWR_GOOD is sent to U7980, phase with ALL_GFX_PGOOD pulled up
by PP3V3_S5 (R7991 did not install parts), and commonly produce
ALL_SYS_PWRGD to EC. This circuit can be called as "Big OR GATE".
Figure 16-52: The “Big OR GATE” circuit

One path of ALL_SYS_PWRGD is sent to EC, after EC receiving
ALL_SYS_PWRGD, then sends CPUIMVP_VR_ON, is shown in figure 16-53.
Figure 16-53: EC sends CPUIMVP_VR_ON
CPUIMVP_VR_ON is sent to 35 pin of U7400 TPS51621, opens the CPU

power supply PPVCORE_S0_CPU, is shown in figure 16-54. After CPU power
supply being normal, sends CPUIMVP_PGOOD and CPUIMVP_CLK_EN_L.
Figure 16-54: The production circuit of CPU power supply

In the circuit of power supply, after the bus power supply producing, supplies
power to CPU, CPU will send GFX_VR_EN to open CPU internal integrated
graphics power supply, is shown in figure 16-55.
Figure 16-55: CPU sends GFX_VR_EN
GFX_VR_EN is sent to 25 pin of U7500 TPS51981, the power supply chip

outputs the integrated graphics power supply PPVCORE_SO_GFX. After the
integrated graphics power supply being normal, the chip open drain outputs PG
but the resistance connected to this pin is not installed, it means that it does not
use this path of PG is shown in figure 16-56.
Figure 16-56: The integrated graphics power supply circuit
16.6: The Clock, PG and The Reset

After CPU power supply being normal, the power chip sends
CPUIMVP_PGOOD to send to U2850 and phase with ALL_SYS_PWRGD, to
form PM_PCH_PWRGD to send to the bridge, to three PG pins of the bridge:
SYS_PWROK, PWROK, MEPWROK(SYS_PWROK means that CPU power
supply is normal).PWROK means that other SO voltage is normal, MEPWROK
means that the voltage opened by SLP_M# is normal, but SLP_M# is not used
in this machine, so directly connected by PG of the SO voltage), is shown in
figure 16-57.
Figure 16-57: PM_PCH_PWRGD is sent to PCH

CPUIMVP_CLK_EN_L through U2790 the NAND gate inverted is sent to
U2700 clock chip to open each clock (27MHz of the clock chip is controlled by
16 pin, haven't open temporarily), is shown in figure 16-58.
Figure 16-58: The clock circuit
After PCH satisfying the power supply, the clock and PG sends
DRAMPWROK, PROCPWRGD to CPU, is shown in figure 16-59.
Figure 16-59: Send DRAMPWROK & PROCPWRGD to CPU

PCH sends PLTRST# and PCIRST#, the PCIRST is vacant and not to be used.
It is shown in figure 16-60.
Figure 16-60: PCH send the reset

PLT_RESET_L converted to each kinds of RESET, sends to onboard chip, is
shown in figure 16-61. PLT_RESET_L is also sent to U2880 to phase with
PP3V3_S0 to produce PLT_RST_BUF_L.
Figure 16-61: PLTRST_RESET_L conversion circuit

PLT_RST_BUF_L through R1125 and R1126 partial pressure to be 1.1V to
send to CPU reset pin RSTIN# is shown in figure 16-62.
Figure 16-62: CPU reset circuit

Finally, the hard reset is completed now.
Chapter 17
Analysis of DELL N4110
DELL N4110 uses Intel 6 series chipset. As this machine an example, skip RTC
circuit and explain the detailed timing sequence features of Intel 6 series.
17.1: G3 State
Insert the adapter to produce +DCIN_JACK, through FL2 to convert to be
+DC_IN to supply power to the S pole of PQ29, then partial pressure to the G
pole of PQ29, conduct PQ29 to produce +DC_IN_SS, is shown in figure 17-1.
Figure 17-1: The adapter inserted circuit
Note: there have a PS_ID signal at the DELL power interface, this signal is
different with ONE-WIRE of Apple, EC gets the adapter parameter by this
signal.PQ1 and PQ2 form the over-voltage protection circuit; when the voltage
of the adapter PSID pin is higher than 5.3V, through PR7 and PR9 partial
pressure to the B pole of PQ1, it will make PQ1 conducted, and pull the G pole
of PQ2 low, PQ2 is cut off. PS_ID and PSID pin of CN3 disconnected, EC can't
get the adapter information, resulting in failure to charge and so on.
Figure 17-2 is the anatomy picture of DELL power head for repair.
Figure 17-2: The anatomy picture of DELL power adapter head (connector) for
repair
The output interface of DELL laptop power adapter is more special: the outer
wall is the negative pole, and the inner wall is the positive pole, there is a small
needle to connect with the ID information storage chip in the power adapter.
DELL laptop identifies the model of the adapter inserted by this chip.
ID information storage chip 2929/2501/DS2501/2502 uses TO92 packaging,

there are 3 pins, and the 3 pin is empty. This chip is 512 bytes, working on
EPRON chip of ONE- WIRE, there are DELL power adapter ID, the power and
other information. This information can be accessed through the minimum
interface, such a port pin of the micro- controller. DS2501 has a registration
code graduated by the factory, which includes 48 bit unique sequence code, 8-
bit CRC check code and 8 bit family code (09h) as well as 512-bit user
programmable E-PROM. The power of 2929/2501/DS2501/2502 programming
and read the operation is from the 1-Wire communication line. Use the 1-Wire
protocol, only through a signal line and a ground line to realize the serial
transmission of the data. The voltage can't be higher than 6V during reading the
data, the voltage must be 12V during programming.
+DC_IN_SS is sent to PQ31, through the body diode to produce the small
current common point, +DC_IN_SS is also sent to the G pole of PQ27, PQ27 is
cut off, the batter is isolated, is shown in figure 17-3.At the same time,
+DC_IN_SS also supplies power to DON of PUl (ISL88731), and partial
pressure to ACIN. When DCIN has the electricity, the ISL88731 produces
88731_LDO with 5.2V. The 88731_LDO supplies power to VCC, the chip
internal produces the reference voltage 3.2V.When ACIN voltage is higher than
3.2V (+DC_IN_SS is higher than 17V), ACOK open drain outputs. Through
88731_LDO partial pressure to produce the high level ACAV_IN with 3.18V,
controls PQ3 conducted. PR13 and PR14 form the partial pressure, after that
PQ31 is conducted completely, and produces the large current common point
PWR_SRC. The common point PWR_SRC supplies power to VIN of PU7
(RT8206), and partial pressure to ONLDO, PU7 outputs +5V_ALW2 from
LDO, is shown in figure 17-4.
Figure 17-3: The production of the small current common point and the battery
isolation circuit
Figure 17-4: The production circuit of +5V_ALW2

The high level of ACAV_IN makes Q12 conducted, and pulls LATCH low,
Q13 is cut off, +5V_ALW2 pulls up 3.3V_ALW_ON, is shown in figure 17-5.
(in the battery mode, it needs press the switch to pull POWER_SW_IN0# low
and control to produce 3.3V_ALW_ON, EC sends ALW_ON again to keep it to
be the high level; USB_CHG_DET# connects to SATA+USB interface CN7, in
the power off state, as long as insert the USB device, it can produce the high
level of 3.3V_ALW_ON. After producing EC standby power supply, EC
detects that USB device is inserted, it will open the shutdown charging function
of USB.)
Figure 17-5: The introduction circuit of 3.3V_ALW_ON
3.3V_ALW_ON converts to be +3.3V_EN2 is shown in figure 17-6.

THERM_STP# is the temperature control signal: over-temperature appeared
after power on, it will pull +3.3V_EN2 low.
+3.3V_EN2 is sent to ON2 of RT8206, is used to open the second path of PWM,
and produces +3.3V_ALW, is shown in figure 17-7.
Figure 17-6: The production circuit of +3.3V_EN2
Figure 17-7: The production circuit of +3.3V_ALW

At the same time, +5V_ALW2 and DL2 (down tube drive square wave) of the
second path of PWM through twice bootstrap of PD3 and PD4 circuit to
produce +15V_ALWP, is shown in figure 17-8.
Figure 17-8: 15V bootstrap circuit
+3.3V_ALW through L3 to convert to be +3.3V_ALW_AVCC, is sent to U2

(EC), as the standby voltage, is shown in figure 17-9.
EC of this machine does not need 32.768 kHz crystal, is shown in figure 17-10.
Figure 17-9: EC gets the standby voltage (Left)

Figure 17-10: EC does not need the crystal (Right)
+3.3V_ALW through R56 and C92 delayed, produces WRST# to sent to the 14
pin of EC, as the reset signal for EC, is shown in figure 17-11.
Figure 17-11: The reset circuit of EC

EC through SPI bus of 101,102,103,105 read ROM (U1), configures their own
Figure 17-12: EC reads the program

After EC reading the program and configuring the pin, it can identify the
adapter insertion test signal of 21 pin, is shown in figure 17-13: when
ACAV_IN is low, 21 pin will be pulled low; when ACAV_TN is high, 21 pin
must be required to complete the configuration of the chip internal procedures,
then it will be high, location of R62 did not install components.
Figure 17-13: EC identified the adapter
When EC received that the presence of the adapter is been detected, then it will
send ALW_ON automatically, is shown in figure 17-14.
Figure 17-14: EC Sends ALW_ON
ALW_ON converted to be +5 V_EN1, controls PQ21conducted, then PQ20 is

conducted, +15V_ALWP through PQ20 convert to be +15V_ALW is shown in
figure 17-15.
Figure 17-15: The production circuit of +15V_ALW
+5V_EN1 is also sent to ONI of RT8206, is used to control produce +5V_ALW,

Figure 17-16: The production circuit of +5V_ALW
17.2: Trigger
Press the switch, producing the low level of POWER_SW_INO#, is shown in
figure 17- 17. POWER_SW_IN0# through D8 pulls SYS_PWR_SW# low.
Figure 17-17: The switch of trigger circuit

SYS_PWR_SW# is sent to 125 pin of EC, is shown in figure 17-18.
Figure 17-18: EC received the trigger signal
17.3: The Standby and The Memory Power

Supply of The Bridge
After EC receiving the trigger signal SYS_PWR_SW#, sends the high level of
SUS_ON, is shown in figure 17-19.
Figure 17-19: EC sends SUS_ON

SUS_ON controls PQ16B conducted, PQ16A is cut off, +15V_ALW directly
pulls up driver PQ17 and PQ23 to be conducted completely, and produces
+3.3V-SUS and +5V_SUS, is shown in figure 17-20.
Figure 17-20: One of the SUS_ON control circuit
+5V_SUS through R277 sent to V5REF_SUS of the bridge, is shown in figure

17-21.
Figure 17-21: The bridge receives V5REF_SUS standby voltage
+3V_SUS through R382 sent to the bridge as 3.3V standby voltage, is shown in
figure 17-22.
Figure 17-22: The Bridge receives 3.3V standby voltage

At the same time, because this machine does not support the depth S5
(SLP_SUS# is vacant), VCCDSW3_3 power supply directly uses +3.3V_SUS,
Figure 17-23: +3.3V_SUS is sent to VCCDSW3_3 power supply of the Bridge

SUS_ON is also sent to S5 pin of PU5 (RT8207) at the same time, is used to
control produce the memory main power supply +1.5V_SUS and the memory
reference voltage +DDR_VTTREF, is shown in figure 17-24. After RT8207
producing +1.5V_SUS normally, it open drain outputs PGOOD, is pulled up by
+3.3V_SUS to produce 1.5V_SUS_PWRGD to send to EC.
Figure 17-24: The production circuit of the memory power supply
1.5V_SUS_PWRGD is sent to EC, after EC receiving 1.5V_SUS_PWRGD,

delays send RSMRST#, is shown in figure 17-25. RSMRST# is also sent to the
deep sleep standby voltage power good signal DPWROK of the bridge and the
light sleep standby voltage power good signal (shown in figure 17-26, when it
does not support the deep sleep, they need to be connected together).After EC
detecting that LID_SW# is normal, pulls 81 pin low, through Dl pull
SIO_PWRBTN# low, this signal is sent to PWRBTN# of the bridge.
After the bridge receiving PWRBTN#, sends SLP_S5#, SLP_S4#, SLP_S3#,

SLP_A#, SLP_S4# is vacant, SLP_A# is also not used, it means that this
machine does not support Intel AMT, is shown in figure 17-26.
Figure 17-25: EC received 1.5V_SUS_PWRGD
Figure 17-26: The trigger circuit of PCH
17.4: S0 State
SLP_S5# and SLP_S3# sent by the bridge respectively renamed to be
SIO_SLP_S4# and SIO_SLP_S3#, are sent to EC. SIO_SLP_S3# is also sent to
Q7,makes it conducted, Q6 is cut off, +15V_ALW pulls up PS_S3CNTRL_S,
controls Q3 to be conducted completely, and produces +1.5V_CPU, is shown in
figure 17-27.
Figure 17-27: The production circuit of +1.5V_CPU

After EC receiving SIO_SLP_S3#, the internal phase with 1.5V_SUS_PWRGD,
and sends RUN_ON to control PQ18B conducted, PQ18A will be cut off,
+15V_ALW directly pull up the G pole of PQ22, PQ26, PQ19, transistor are
fully conducted, and produces +5V_RUN, +3.3V_RUN, +1.5V_RUN, is shown
in figure 17-28.
Figure 17-28: The voltage of RUN_ON control
RUN_ON is sent to S3 pin of RT8207 at the same time, according to the

working principle of RT8207, it will control the production of
+0.75V_DDR_VTT, is shown in figure 17-29.
Figure 17-29: RT8207 outputs +0.75V_DDR_VTT

RUN_ON is also sent to PQ9, makes it conducted, 1 pin of RT8015 through
PR63 to be grounded, do frequency setting (if PQ9 is cut off, +5V_ALW
directly pulls up the first pin of the chip, SHDN is effective, the chip off
outputs), controls PU3 to output +1.8V_RUN, is shown in figure 17-30.
Figure 17-30: The production circuit of +1.8V_RUN
RUN_ON is sent to PU9 (RT8240B), controls the production of the core power
supply and bus power supply +1.05V_PCH of the bridge, is shown in figure 17-
31. After the power supply being normal, sends 1.05V-PCH_PWRGD.
Figure 17-31: The production circuit of 1.05V_PCH
RUN_ON is sent to PU8 (TPS51461), controls to produce +VCCSA_CORE

required by CPU, is shown in figure 17-32. After the power supply being
normal, the open drain outputs VCCSA_PWRGD.
Figure 17-32: The production circuit of +VCCSA_CORE
1.05V_PCH_PWRGD phase with VCCSAVCCSA_PWRGD signal to produce

HWPG is pull up to be high level by +3.3V_SUS. One path is sent to
APWROK of the bridge, is shown in figure 17-33.
Figure 17-33: HWPG is sent to APWROK of PCH
Another path is sent to Q22,is shown in figure 17-34.This is a temperature

control circuit, the working principle rafter EMC2112 getting the power supply,
through 2-3 pin to test the temperature of VGA, through 4-5 pin to test the
temperature next to the CPU socket, through 14,15 pin to report to EC. When
the temperature rises, the chip controls +5V_FAN voltage of 17 pin and 18 pin
rise, the speed of the fan is accelerated, in order to cool down, through the 20
pin test the speed. When the temperature reaches the set limit (the set limit
temperature of 7 pin is 85oC), the chip pulls SYS_SHDN# of 8 pin low, causes
that the power supply of EC is closed, so the machine will be outage.
The third path of HWPG is sent to 66 pin of EC, is shown in figure 17-35. After
EC receiving HWPQ through H_CPUDET# of 67 pin detect that CPU is existed
(H_CPUDET# is low), then sends IMVP VR ON.
IMVP_VR_ON sent by EC is sent to CPU core power supply chip PU4

(MAX17511), is shown in figure 17-36. But CPU core power supply doesn't
appear at this time, because CPU does not send SVID to the power supply chip,
it needs to wait the subsequent PROCPWRG is sent to CPU, then CPU will
send SVID, the detailed is shown in the timing sequence figure of Intel HM65
series or more chipset.
Figure 17-34: The circuit screenshot of temperature control chip
Figure 17-36: IMVP_VR_ON is sent to the XPU power supply chip
17.5: PG and The Clock

After EC receiving HWPG and detecting CPU exits, delays send EC_PWROK
from the 82 pin, is shown in figure 17-37.
EC_PWROK is sent to PWRO of the bridge, is shown in figure 17-38. The
bridge open drain outputs PM_DRAM_PWRGD from DRAMPWROK pin.
PM_DRAM_PWRGD is pulled up to be high level by R118 and sent to U4, it
will wait SYS_PWROK sent by the subsequent circuit, and convert to be
SM_DRAMPWROK to send to CPU, is shown in figure 17-39.
Figure 17-37: EC sends EC_PWROK
Figure 17-38: PCH received PWROK and sent DRAMPWROK
Figure 17-39: The circuit screenshot location of U4
25MHz crystal of the bridge oscillated, then the bridge will read BIOS program.
The waveform of 25MHz and reading BIOS is shown in figure 17-40. Channel
1 is BIOS chip select signal; channel 2 is 25MHz clock.
After reading BIOS normally, the clock circuit in the bridge starts to work, and
sends each group of clock, is shown in figure 17-41 .CLK_CPU_BCLKN and
CLK_CPU_BCLKP are sent to CPU.
The timing sequence of reading BIOS and sending clock is shown in figure 17-
42. Channel 1 is reading BIOS, channel 2 is 100MHz clock sent by the bridge.
Figure 17-40: The timing sequence comparison of 25MHz and reading BIOS
Figure 17-41: The Bridge sends each group of clock
Figure 17-42: The timing sequence comparison of reading BISO and sending
clock
17.6 CPU Core Power Supply

After the clock integrated by the bridge working normally, the bridge starts to
send PROCPWRGD, the name is H_PWRGOOD, is shown in figure 17-43.
Figure 17-43: The bridge starts to send PROCPWRGD
The timing sequence comparison of the clock sent by the bridge and
PROCPWRGD is shown in figure 17-44.Channel 1 is PROCPWRGD, channel
2 is 100MHz clock sent by the bridge.
Figure 17-44: The timing sequence comparison of the clock sent by the bridge
and PROCPWRGD
H_PWRGOOD is sent to UNCOREPWRGOOD of CPU, is shown in figure 17-

45,it means that the power supply required by CPU, except the core power
supply and integrated graphics power supply, all of other power supply is
normal, including +1.05V_PCH, +1.8V_RUN, +1.5V_CPU, +VCCSA_CORE.
Figure 17-45: H_PWRGOOD is sent to CPU
CPU received UNCOREPWRGOOD and sent SVID, renamed respectively to

be VR_SVID_CLK, VR_SVID_DATA and VR_SVID_ALERT#, is shown in
figure 17-46.
Figure 17-46: CPU sends SVID

SVID is sent to CPU core and integrated graphics power supply chip PU4
(MAX17511GTL+) ,is shown in figure 17-47.
Figure 17-47: SVID is sent to MAX17511
MAX17511 gets the main power supply +5V_SUS and the open signal
IMVP_VR_ON, and receives SVID, then it controls the internal integrated
PWM A1, PWM A2 to produce CPU core power supply +VCC_CORE. After
CPU core power supply being normal, it open drain outputs IMVP_PWRGD
from the 19 pin POKA, and is pulled up by +3.3V_RUN, is shown in figure 17-
48.
Figure 17-48: The production circuit of CPU core power supply
One path of IMVP_PWRGD is sent to EC; another path is sent to U25, phase
with EC_PWROK sent by EC to produce SYS_PWROK, is shown in figure 17-
49.
Figure 17-49: The production circuit of SYS_PWROK

One path of SYS_PWROK is sent to U4, phase with PM_DRAM_PWRGD sent
by the bridge, to produce SM_DRAMPWROK to sent to CPU, is shown in
figure 17-50.
Figure 17-50: The circuit of SYS_PWROK phase with PM_DRAM_PWRGD

Another path of SYS_PWROK is sent to SYS_PWROK of the bridge, is shown
in figure 17-51.
Figure 17-51: The bridge received SYS_PWROK
17.7: Reset
The bridge sends PLTRST#, renames to be PCI_PLTRST#, is shown in figure
17-52.
Figure 17-52: The bridge sends PLTRST#

PCI_PLTRST# through R239 direct connection renamed to be PLTRST#, is
shown in figure 17-53.U13 does not install the component. PLTRST# is sent to
EC, CN4, R5538D001 and other chip and slot.
Figure 17-53: PCI_PLTRST# renamed to be PLTRST#

PLTRST# also through R497 and R126 partial pressure to be
CPU_PLTRST#_R with 1.1V to send to the reset pin RESET# of CPU, is
Figure 17-54: CPU received the reset
17.8: The Graphic Card Power Supply

CPU starts to work, after self-checking the memory, CPU sends SVID again to
MAX17511, to control produces the integrated graphics power supply
+VCC_GFX_CORE, is shown in figure 17-55. After the integrated graphics
power supply being normal, sends IGFX_PWRGD to EC.
Figure 17-55: The production circuit of the integrated graphic (Discrete) power
supply
The timing sequence comparison of the memory SMBUS and the production of
integrated graphics power supply is shown in figure 17-56. Channel 1 is the
memory SMBUS, channel 2 is the integrated graphics power supply. The
integrated graphics power supply rises to about lV, then drops to about 0.45V.
Figure 17-56: The timing sequence comparison of the memory SMBUS and the
integrated graphic (Discrete) power supply
About the sketch of the independent graphics power supply (about the
component position number, please refer to the circuit diagram):
After resetting, the bridge sent DGPU_PWR_EN through the circuit converted
to control PQ14 produces +3V_GFX, +3V_GFX through U11 converted out
GFX_ON to control PU2 produces the independent graphics core power supply
+VCC_DGFX_CORE; +3V_GFX also pulls up EN of PU6, and controls the
production +1 V_GFX; after PU2 working normally, then sends PG and
controls PQ12 to produce +1.5V_GFX by converted; after PU6 working
normally, then sends PG and controls PQ10 to produce +1.8V_GFX by
converted.
Chapter 18
Analysis of ThinkPad (IBM)
T410 Timing Sequence
ThinkPad, before 2005, it’s the portable computer brand of IBM PC business
division subordinate, depends on the features of firm and reliable, it enjoys very
high reputation in the industry. After Lenovo purchasing IBM PC business
division, ThinkPad is owned by Lenovo. But in the circuit design, it is still the
idea of IBM. Next as T410 is an example (QM57 chipset), to analyze the
working timing sequence of ThinkPad. Because there is no difference about
RTC circuit, we don't explain in this chapter.
18.1: G3 State
First, in the figure 18-1, insert the adapter, through Q9 to produce CV20 first,
DISCHARGE2 must be low level and -PWRSHUTDOWN must be high level,
then Q9 is conducted.
Figure 18-1: The adapter entered to a circuit

The specific process: the high level of-PWRSHUTDOWN makes Q79
conducted, the low level of DISCHARGE makes Q78 to be cut off, and the
adapter voltage through R369 added to the B pole of Q51, Q51 is also
conducted. So, the adapter voltage through R143 and R145, then through Q51
and Q79 to be grounded, series partial pressure, get the one third of 20V: about
6.7V. The S pole of Q9 is 20V, the G pole is about 6.7V, it’s enough to
conducted (the condition of P channel MOSFET conducted completely is
usually VG<VS 4.5V).
(Remark: NO_ASM in the figure means that it doesn't install the component in
IBM circuit diagram.)
DISCHARGE2 through 0Ω resistance R229 connected to DISCHARGE shown

in figure 18-2 (other components are not installed).
Figure 18-2: DISCHARGE renamed

DISCHARGE connects to H8S, and the resistance R891 is pulled down, is
shown in figure 18-3.VCC3M supplies power to H8S, before the common point
produced, H8S is no voltage, so DISCHARGE will be pulled low to be low
level by the resistance. Only H8S gets the power supply, the process control
calibrates the battery electric quantity, then H8S will send DISCHARGE, this
signal is similar to AC_OFF, AD_OFF of other machines.
Figure 18-3: H8S sends DISCHARGE
Then look at the second signal -PWRSHUTDOWN, is sent by 46 pin of U61

(open drain output), is pulled up by VCC3SW through R1101, is shown in
figure 18-4.
Figure 18-4: U61 sends –SHDN_OUT

Trace VCC3SW first, VCC3SW is from U61, is shown in figure 18-5.
Figure 18-5: U61 outputs VCC3SW

U61 is RINKAN_2, the early IBM model uses TB62501 and others the function
is resembled. About the pin definition, we can refer to TB62501. The internal
block diagram of TB62501 is shown in Figure 18-6 the output condition of
VCC3SW is that VREGIN16, BAT_VOLT, -RESET, no over-current and
under-voltage.
Figure 18-6: The internal block diagram of TB62501

In the U61 chip of T410, the name of VREGIN16 is VREGIN20, is shown in
figure 18- 5, no RESET pin, so the key are VREGIN20 and BAT_VOLT.
The origin of VREGIN20 pin and BAT_VOLT of U61is the power supply
VREGIN20, is shown in figure 18-5. Connects any one of pedestal
(DOCK_DCIN20), the adapter (DCIN_PWR20_F), the main battery (M-BAT-
PWR), the secondary cell (S-BAT- PWR), it will also produce VREGIN20, is
Figure 18-7: The production circuit of VREGIN20
VREGIN20 supplies power to U61 directly, under the case of the adapter
inserted, VREGIN20 with 20V through R522 and R559 partial pressure to be
8.2V to BAT_VOLT as the voltage detection, is shown in figure 18-8.
Figure 18-8: U61 gets VREGIN20 and BAT_VOLT

According to the data manual of TB62501, the threshold value of BAT_VOLT
is the rising edge 2.9V ±8%, the falling edge 2.5V ±5%, is shown in figure 18-9.
Figure 18-9: The screenshot of BAT_VOLT rising edge and falling edge setting
in the data manual of TB62501
That is to say just when plug in the power, the voltage of this pin must be higher
than 2.9V, then it can be converted the low level to be the high level; during
using, the voltage of this pin drops to be 2.5V, then it can be converted the high
level to be the low level. According to the computation formula of series
resistance partial pressure, worked out that the lowest VREGIN20 should not be
less than 7.06V.The result is shown in figure 18-10. In the battery mode, the
battery voltage should not be less than 7.06V, then it can start up; but when
starts up normally and use it, the battery voltage is less than 6.089V,then we
think it is under-voltage, and closed VCC3SW, turned off the power.
Figure 18-10: Calculation results of the minimum voltage of VREGIN20

After satisfying VCC3SW, then look at –PWRSHUTDOWN. As shown in
figure 18- 11,according to the internal block diagram of TB62501 chip manual,
there have two cases of U61 outputting the low level of -PWRSHUTDOWN.
The fist, the output voltage load is over-weight (short circuit, under voltage,
etc.),because the common point is no electricity at this time, the voltage output
final stages detection circuit is not working, only been powered on, if there is a
voltage does not appear, then it will cause that U61 outputs the low level of
-SHDN.
Figure 18-11: -SHDN internal control block diagram of TB62501
The second, TH_DET is abnormal. The pin of TH_DET is defined to be

connected to the thermistor (PTC). It is powered internally by VCC3SW, is
Figure18-12: TH_DET internal block diagram of TB62501

TH_DET connects 14 positive temperature coefficient of thermal resistance
(PTC, thermistor), is shown in figure 18-13.
Figure 18-13: The resistance TH_DET connected

About the electrical specification of chip is shown in figure 18-14, this pin is
higher than 0.5V, U61 will pull -PWRSHUTDOWN low.
Figure 18-14: The screenshot of the electrical specification of the TH_DET

threshold value in the data manual of TB62501
After satisfying DISCHARGE and -PWRSHUTDOWN, it can produce CV20.

CV20 through the body diode of Q36 produces the small current common point
VINT20, is shown in figure 18-15, if you want the common point current to be
higher, DCIN_DRV must be high level.
DCIN_DRV is from U61 (RINKAN_2), is shown in figure 18-16.
The condition of U61 sending the high level of DCIN_DRV: DISCHARGE and
- EXTPWR are low level : after DISCHARGE and -EXTPWR being the low
level, the internal OR GATE outputs low level, through the NOT gate phase
reversal to output the high level, makes DCIN_DRV to be high. DCIN_DRV,
BAT_DRV, M1_DRV, S1_DRV are provided drive voltage by the VIPIN24
(this machine is VCPIN28). The internal working principle of the chip
DCIN_DRV is shown in figure 18-18.BAT_DRV is the battery isolation tube
drive signal; its state is opposite to that of DCIN_DRV.
Figure 18-15: The production circuit of the common point
Figure 18-16: U61 sends DCIN_DRV
Figure 18-17: DCIN_DRV internal block diagram of TB62501
The combination of DISCHARGE and -EXTPWR can determine the state of

DCIN_DRV and BAT_DRV, is shown in figure 18-18: when DISCHARGE
and - EXTPWR are low, DCIN_DRV signal is charged to be high level,
BAT_DRV signal is discharged to be low level; DISCHARGE or -EXTPWR is
high, DCIN_DRV is discharged to be low level, BAT_DRV is charged to be
high level.
Figure 18-18: The screenshot of output condition specification of DCIN_DRV

and BAT_DRV in the data manual of TB62501
DISCHARGE has been low level, it just needs to get the low level of
-EXTPWR. Then trace the origin of-EXTPWR: after inserting the adapter, the
adapter voltage will through D87 supplies power to PVCC of BQ24741, and
through D84, R584, R227 partial pressure to ACDET, is shown in figure 18-19.
Figure 18-19: The screenshot of the adapter detection circuit of the charge chip
The charge chip BQ24741 gets the main power supply PVCC, then get ACDET
from the adapter voltage partial pressure. According to BQ24741 manual, when
ACDET is higher than 2.4V, the chip thinks that the adapter has been inserted,
and then it will output the adapter detection signal –EXTPWR. The pin
definition of PVCC, ACDET, and EXTPWR# of BQ24741 is shown in figure
18-20.
Figure 18-20: The screenshot of the related pin definition of adapter detection of
BQ24741
[Explanation]
PVCC: the main power supply of the chip, through a schottky diode connects to
the adapter, needs to place a capacitance with 0.1uF, and closes to the chip.
ACDET: the adapter detection voltage sets input pin, it can set the adapter
threshold value voltage by the methods of the resistor dividing voltage to
ACDET pin. When ACDET is higher than 0.6V and PVCC is higher than
VUVLO (8V), IADAPT current detection amplifier is effective. When ACDET
is higher than 2.4V, is mean detected the adapter. When ACDET is higher than
3.1V, the adapter is over voltage, forbid to charge; When ACDET is less than
3.1 V, it will return to be normal.
EXTPWR: the low level effective adapter detection signal, open drain outputs.
When the voltage input by ACDET pin is higher than the threshold value (2.4V)
or the current flowed through 10mΩ current detection resistance is higher than
1.25A, this pin will be pulled low. It needs to connect a resistance with 10kΩ to
pull up this pin.
One path of -EXTPWR output by BQ24741 s sent to U61, combines with

DISCHARGE to control the level of DCIN_DRV and BAT_DRV: -EXTPWR
and DISCHARGE are low, U61 will output the low level of BAT_DRV
isolation battery, is shown in figure 18- 21.Then U61 outputs the high level of
DCIN_DRV, and conducts Q36 (note: DCIN_DRV is provided the driving
voltage by VCPIN28.At this time, DCIN_DRV only closes to 20V, because it
needs to wait for 3M_ON, 5M_ON, 3MPGS, 5MPGS being normal, then
VCPIN28 boosted circuit will start, is shown in figure 18-22), adds the current
of the common point.
Figure 18-21: The battery isolation circuit
Figure 18-22: The internal block diagram of the boosted circuit
The second path through D7 converts to be -EXTPWR_EC to send to H8S (-

EXTPWR is low, through D7 pulls -EXTPWR_EC low), is shown in figure 18-
23, it means that the adapter has inserted.
Figure 18-23: The circuit screenshot of D7 location
The third path through Q65 converts to be -EXTPWR_ASIC, sends to U42

(Lenovo chip), is shown in figure 18-24. Q65 is a common N channel field
effect transistor; the conduction of it is controlled byVL5.
Figure 18-24: The adapter detection signal is sent o Lenovo chip
VL5 is output by TPS51222: the common point VINT20 is supplied to

TPS51222, EN connects -PWRSHUTDOWN again, it has been high level, so
TPS51222 will output VREG5 and VREG3,VREG3 is not used, the name of
VREG5 is VL5, is shown in figure 18-25.
Figure 18-25: The screenshot of the standby chip TPS51222
18.2: S5 State
U42 got the standby power supply VCC3SW, and also got the standby voltage
good signal (through R848 and pulled up by VCC3SW), the adapter detection -
EXTPWR_ASIC is normal, and send M1_ON from 60 pin, is shown in figure
18-26.
M1_ON through R866 and R405 converts to be VCC5M_ON and VCC3M_ON

Figure 18-27: M1_ON renamed to be VCC5M_ON & VCC3M_ON
VCC5M_ON and VCC3M_ON are sent to TPS51222, controls to produce

VCC5M_OUT and VCC3M, as the standby voltage for the bridge is shown in
figure 18- 28.VCC5M_OUT renames to be VCC5M.
Figure 18-28: The standby chip outputs two path of PWM power supply
VCC5M_ON is sent to 5M_ON and 3M_ON of U61, VCC5M and VCC3M

also supplies power to U61, is shown in figure 18-29.
Figure 18-29: U61 detection M voltage
VCC3M also supplies power to H8S, 10MHz crystal Y4 of H8S starts oscillate,
Figure 18-30: The crystal of H8S starts oscillate after getting the voltage
According to the data manual of TB61501, when U61 detects that VCC5M,
VCC3M are normal, U61 will boot-strap though 34 pin, C606, D57, and
through D64 and C336 rectification smoothing, then it will send to VCPIN28,
the actual voltage is about 25V, is shown in figure 18-31. This voltage is mainly
used to enhance the driving ability of DCIN_DRV, controls to produce the large
current common point.
Figure 18-31: The boosted circuit of U61
U61 will through the boost circuit consisted of D62, D56, D8, C115, C610,
C238 to boost VDD15, is used to drive**_DRV, such as 3B_DRV and so on, is
M1_ON will also through R1702 to convert to be 3FP_ON, is shown in figure

18- 33. 3FP_ON is sent to U61, U61 outputs 3FP_DRV from RD1_DRV,
3FP_DRV is sent to Q103, controls VCC3M to convert out VCC3FP.
U61 detect that VCC3M voltage is higher than 2.943V, VCC5M voltage is
higher than 4.461V, and delays 47.5ms to send M_PGS. The threshold value
and the timing sequence are shown in figure 18-34.
Figure 18-32: VDD15 boosted circuit
Figure 18-33: 3FP_ON control circuit

Greater than 4.461 V (Typ.) at power on stags of "VCC5M" (Rising Edge) and
lower than 4.311V (Typ.) at the shut down stage (Falling edge) after 47.5ms +/-
2.5ms.
Greater than 2.943V (Typ.) at power on stage of "VCC3M" (Rising Edge) and
lower than 2.793V (Typ.) at the shut down stage (Falling edge) after 47.5ms +/-
2.5ms.
Figure 18-34: The figure of the threshold value and the timing sequence of the
detection M voltage of TB62501
The figure 18-35 is the internal block diagram of M_PGS of U61.
Figure 18-35: The internal block diagram of M_PGS of TB62501
M_PGS open drain outputs, is pulled up to be high level by VCC3M, the name
is MPWRG is shown in figure 18-36. MPWRG is sent to RSMRST# of PCH.
Figure 18-36: U61 outputs MPWRG
MPWRG is also sent to U42 (THINKER1), is used to send EC_RST# for U42,
reset H8S, is shown in figure 18-37. Y4 starts oscillate after H8S getting the
power supply, and after receiving -EC_RST, H8S reads its own program, and
configures the pin-out.
Figure 18-37: THINKER1 chip sends the reset of H8S
After PCH receiving MPWRG sends automatically-PCH_SLP_LAN# to THINKER1,

THINKER1 sends VCCLAN_ON, is shown in figure 18-38.
Figure 18-38: THINKER1 chip sends VCCLAN_ON

One path of VCCLAN_ON is sent to the network card power supply chip U28
(VT356), this is PWM power supply chip with EGA packaging and integrated
up and down tube, after it getting the power supply VCC5M_OUT and the open
signal VCCLAN_ON, outputs VCC1R05LAN, and open drain outputs
1R05LAN_PWRG (is not used), is shown in figure 18-39.
Figure 18-39: The production of the network card power supply

VCCLAN_ON is sent to U61, U61 sends VCC3LAN_DRV (is provided the
driving voltage by VDD15), is shown in figure 18-40.
Figure 18-40: The production of VCC3LAN_DRV

VCC3LAN_DRV drives Q69 to be conducted, converts VCC3M to be
VCC3LAN, is shown in figure 18-41.
Figure 18-41: The production circuit of VCC3LAN
18.3: AMT
If open Intel AMT in CMOS, and sets it to be the second item "ON in S0, ME
Wake in S3, S4-5(AC only)" shown in figure 18-42, selects the power supply of
opening ME in the S4-5 state under the AC mode. After the standby condition
being normal and detecting that the adapter transmitted by U2 exists
AC_PRESENT signal, PCH will send automatically -PCH_SLP_M and -
AMT_ALERT, is shown in figure 18-43.
Figure 18-42: ME power supply setting

Note: the default in CMOS is that AMT is closed, that is to say, the timing
sequence of SLP_M# is synchronized with SLP_S3#. In order to tell AMT
related signal, then we list this part.
Figure 18-43The Bridge sends the signal to open ME module power supply
-PCH_SLP_M and -AMT_ALERT are sent to THINKER 1(U42), U42 sends

AMT_ON, is shown in figure 18-44.
Figure 18-44: THINKER1 chip sends AMT_ON
AMT_ON is sent to U61 (RINKAN_2), U61 sends AMT_DRV, is shown in

figure 18_45.
Figure 18-U61 sends AMT_DRV
AMT_DRV drives Q96 to convert VCC1R05LAN to be VCC1R05AMT, and

supplies power to VCCME of PCH (ME module) is shown in figure 18-46.
Figure 18-46: The production circuit of VCC1R05AMT
After VCC1R05AMT being normal, and through partial pressure sends to 4 pin
detection of U80. After the voltage reaching the standard, U80 open drain
outputs MEPWRG is pulled up by VCC3LAN, and sends to PCH. As shown in
figure 18-47.
Figure 18-47: The production circuit of MEPWRG
The model of U80 is BD4140, this is a voltage detection delay chip, the
detection threshold value is 500mV (is 0.5V). As shown in figure 18-48.
Figure 18-48: The screenshot of the description of electrical specification of the

voltage detection threshold value in the data manual of BD4140
18.4: Trigger
Press the switch, producing the low level of -PWRSWITCH, through D76 and
D1 pulls respectively -PWRSW_ASIC, -PWRSW low, is shown in figure 18-49.
Figure 18-49: The trigger circuit

-PWRSW_ASIC is sent to U42 (THINKER1), is shown in figure 18-50, is used
to synchronize the timing sequence, and control to open M1_ON in the battery
mode.
Figure 18-50: THINKER1 chip received the trigger signal
-PWRSW is sent to 23 pin of U23 (H8S2112), is shown in figure 18-51.

After H8S receiving –PWRSW, then sends –PWRSW_EC to PWRBTN# of
PCH, is shown in figure 18-52.
Figure 18-51: H8S received the trigger signal
Figure 18-52: The Bridge received PWRBTN#
After PCH receiving PWRBTN#, sends -PCH_SLP_S5, -PCH_SLP_S4,

-PCH_SLP_S3 in turn, is shown in figure 18-53, sends to H8S and THINKER1.
If AMT function is closed, - PCH_SLP_S3 and –PCH_SLP_M are sent at the
same time.
Figure 18-53: The Bridge sends the power-on instruction
18.5: S3 and S0 State

After U42 (THINKER1) receiving -PCH_SLP_S5#, controls to send USB_ON1,
USBON2, is shown in figure 18-54.
Figure 18-54: Lenovo chip sends USB power supply open signal
USB_ON2 and USB_ON1 is sent respectively to U30, U52 and U53 to control
production of USB_PWR_S1, USB_PWR_D1, USB_PWR_D2, USB_PWR_S2,
Figure 18-55: The production circuit of USB power supply
U42 (THINKER1) sends A1_ON after receiving –PCH_SLP_S4#, is shown in

figure 18-56.
Figure 18-56: U42 sends A1_ON
A1_ON through R901 converted to be VCC1R5A_ON, VCC1R5A_ON

is sent to U32 (VT356), controls to produce VCC1R5A memory main power
supply, as shown in figure 18-57.
Figure 18-57: The production circuit of the memory power supply
U42 sends B1_ON and B2_ON after receiving -PCH_SLP_S3#, B1_ON is

converted to be B_ON, 1R8B_ON, 0R75B_ON, as shown in figure 18-58.
Figure 18-58: The circuit of B1_ON renamed
1R8B_ON is sent to U90, controls production of VCC1R8B, as shown in figure

18-59.
0R7B_ON is sent to U70 (MAX1510) controls production of VCC0R75B
(DDR3_VREF is produced after 4 pin being power on, belongs to S3 voltage),
is shown in figure 18- 60. After VCC0R75B being normal, U70 open drain
outputs DRAMPWRG.
One path of B_ON is sent to U61, U61 outputs VCC3B_DRV, VCC5B_DRV,

B_DRV, is shown in figure 18-61.
Figure 18-59: The production circuit of VCC1R8B
Figure 18-60: The production circuit of VCC0R75B
Figure 18-61: B_ON control circuit
Figure 18-62: The production circuit of VCC3B, VCC5B and

VCC3VIDEO_DP
B_DRV controls production VCC1R5B, VCC1R5_VDDQ, VCC1R05B, as
Figure 18-63: The screenshot of the voltage controlled by B_DRV
Another path of B_ON is sent to U18, controls production of VCC1R05B_VTT,

Figure 18-64: The production circuit of VCC1R05B_VTT

After VCC1R05B being normal, U18 sends VTT_PWRG, this signal through
D59 and D45 to phase with B2_ON sent by U42 (THINKER1) to produce
VCORE_ON, is shown in figure 18-65.
Figure 18-65: The production circuit of VCORE_ON

VCORE_ON is sent to U16 (ADP3212), to produce CPU power supply
VCCCPUCORE, as shown in figure 18-66. After CPU power supply being
normal, ADP3213 sends CPUCORE_PWRGD and -CK_PWRGD.
Figure 18-66: The CPU power supply circuit

In addition, U42 (THINKER1) will also send a number of graphics related open
signal, here we don’t explain it again.
18.6: The Clock, PG and Reset

After CPU power supply being normal, -CKPWRGD sent by ADP3212 through
Q2 inverted, is sent to U2 clock chip, to open each channel of clock, is shown in
figure 18- 67.
Figure 18-67: The working circuit of the clock chip
U61 detected that the voltage of VCC3B and VCC5B is normal, then it sends
BPWRG to H8S,U42 (THINKER1) and other chips, as shown in figure 18-68.If
the standby power supply chip works abnormally, it will pull BPWRG low by
5M_PWRG or 3M_PWRG.
Figure 18-68: U61 sends BPWRG
The detection threshold value of VCC3B and VCC5B is 2.943V and 4.461 V. If
the voltage is normal, delays send B_PGS. The timing sequence and the
detection threshold value of B_PGS as shown in figure 18-69.
Figure 18-69: The description of B voltage threshold value of TB62501 and

B_PGS timing sequence diagram
Figure 18-70 is the logic circuit diagram produced by B_PGS.
Figure 18-70: B_PGS internal block diagram of TB62501
U61 chip has a strong protection function: if and voltage of 3B, 5B, 3A, 3P, 3M,
5M, RD3, RD4 and other is abnormal, it will pull –SHDN (this machine is -
PWRSHUTDOWN) low, and close the common point, as shown in figure 18-71.
Figure 18-71: The screenshot of the internal and logic circuit of TB62501
BPWRG also connects with CPUCORE_PWRGD sent by CPU power supply

chip, and sends to SYS_PWROK and PWROK of PCH, as shown in figure 18-
72.
Figure 18-72: PCH received SYS_PWROK and PWROK

After PCH satisfying the power supply, the clock, SYS_PWROK and PWROK,
then sends the last DRAMPWROK, PROCPWRGD and PLTRST#. As shown
in figure 18- 73, the name of PROCPWRGD is CPUPWRGD after sending, and
its sent directly to VCCPWRGOOD_0 and VCCPWRGOOD_1 of CPU (shown
in figure 18-74).
Figure 18-73: PCH sends CPUPWRGD

DRAMPWROK open drain output by PCH is divided into pressure by
VCC1R5_VDDQ to be 1.05V to send to CPU, is shown in figure 18-74.
Figure 18-74: DRAMPWRG is sent to CPU
After PLTRST# sending, through the same direction device U73, differentiates
into - PLTRST_NEAR and -PLTRST_FAR to send to each onboard chip, as
shown in figure 18-75, we don't explain here again.
Figure 18-75: PCH sends PLTRST#
At last, -PLTRST_FAR through R79 and R990 divided into pressure to be

1.05V to CPU, is shown in figure 18-76.
Figure 18-76: CPU reset circuit
18.7: The Battery Charge Circuit

The figure 18-77 is the battery interface, the pin definition is below.
 1 pin and 2 pin are the positive of the battery.
 6 pin and 7 pin are the negative of the battery.
 3 pin and 4 pin are I2C bus: is used to read the battery parameter for H8S,
such as the number of battery cores, the battery cell brand, a single core
capacity, the battery power and other information, it’s used as a battery
insertion test.
 5 pin is the battery temperature detecting pin.
Figure 18-77: The battery interface circuit

After H8S detecting the battery, starts to monitor the battery voltage, is shown
in figure 18-78, H8S sends the high level of BATMON_EN to make Q29
conducted. As the main battery an example, Q29 conduction makes D48 to be
grounded. D48 also pulls 2 pin of Q19 low. Q19 is PNP model triode, E-C is
conducted, M-BAT-PWR reaches to D53 through Q19. After reverse
breakdown, then divided into pressure by the resistance R444 and R447, and
sends the main voltage sampled signal M_BATVOLT to H8S.
Figure 18-78: The battery voltage monitoring circuit
H8S detects the electrical quantity by I2C bus, if the battery is too low to be
charged, H8S tells U42 (THINKER1) through SPI bus, including charge current,
the quantity of the battery series and other information's shown in figure 18-79.
Figure 18-79: The communication bus of H8S and THINKER1
According to the instruction transmitted by SPI bus, U42 sends proper

CHARGE_3CELL signal to control CELLS of U7 as shown in figure 18-80.
The high level of CHARGE_3CELL is set to be 3 CELL.
The original of CELLS pin definition of U7: 2, 3 or 4 cells selection logic input.
Logic Lo programs 3-cell. Logic HI programs 4-cell. Floating programs 2-celL
[Explanation] Low level is 3CELL, high level is 4CELL, and vacant is 2CELL.
Figure 18-80: The selection of the quantity of cell series
U42 also sends BAT_CRG signal. As shown in figure 18-81, this signal is
divided into two paths. One path is added to 1 pin CE of U7 (BQ24741) by
D34, R244 and R904 dividing into pressure.
The original of CE pin definition of U7: Charge-enable active-HIGH logic input.

HI enables charge. LO disables charge. It has an internal 1 MΩ pull-down
resistor. A 10 kΩ external resistor is required to connect the CE pin to the
external pull-up rail other than VREF.
[Explanation] charge enable pin is effective in high level. Forbids charging is

in low level. There is a pull-down resistance with 10MΩ in it. It can connect to
VREF through external pull-up resistance with 10 KΩ to use to open charge.
Figure 18-81: U7 received CE signal

U7 (BQ24741) got the charging enable, the quantity of cell series, but it also
needs for charging current settings and charging voltage regulation.
The original of charging current settings pin ISET pin definition: Charge current
set input. The voltage ratio of ISET voltage versus VDAC voltage programs the
charge current regulation set-point. Program by connecting a resistor divider
from VDAC to ISET, to AGND; or, by connecting the output of an external
DAC to ISET pin and connect the DAC supply to VDAC pin.
[Explanation] charge current setting input. The voltage ratio of ISET and
VDAC decides the charge current. It can input by the resistance dividing into
the voltage from VDAC, and also can input from the external.
The original of specific charging current settings in the manual is below:

(Battery Current Regulation)
Referred to a formula in the original manual in T410, VDAC is provided by

BQ_VREF who is from VCC3M through the resistance R110 with 0Ω (shown
in figure 18-82), the current detection resistance R728 connected by CSP and
CSN is 0.02Ω (shown in figure 18-83).
Figure 18-82: The screenshot of VDAC origin
Figure 18-83: The charging current detection resistor
According to the calculation formula, changes the voltage value of ISET, then it
can work out the charging current: assume that the voltage of ISET is 1.5V,
according to the formula; we can calculate that the charging current is about
2.28A.
The original of the charging voltage regulation pin VADJ pin definition: Charge
voltage set input. The voltage ratio of VADJ voltage versus VDAC voltage
programs the battery voltage regulation set-point. Program by connecting a
resistor divider from VDAC to VADJ, to AGND; or, by connecting the output
of an external DAC to VADJ pin and connect the DAC supply to VDAC pin.
[Explanation] charge voltage setting input. The voltage ratio of VAD] and
VDAC decides the charge voltage. It can input by the resistance dividing into
the voltage from VDAC, and also can input from the external.
The original of the specific charging voltage settings in the manual is below:
According to the original of the charging voltage settings, CELLS is the main
parameter to determine the charging voltage. VADJ is just to be fine turned,
4.15V~ 4.5V.We doesn’t calculate in detail.
After setting up all the charging open, charging current and charging voltage of
U7 (BQ24741), controls Q4 and Q119 to be conducted in turn, to produce
CHARGE_OUT12, as shown in figure 18-84.
Figure 18-84: The charging voltage output circuit
Another path of BAT_CRG controls Q35 conducted, and converts

CHARGE_OUT12 to be BAT_PWR12, is shown in figure 18-85.
U42 sends BAT_CRG and the main battery selection signal M1GATEON and
M2GATEON, as shown in figure 18-86. M1GATEON and M2GATEON are
sent to U61 (RINKAN_2, U61 sends M1_DRV and M2_DRV after receiving
these two signals. S1GATEON and S2GATEON are the secondary battery
selection signal.
M1_DRV is the high level about 24V, makes Q8 conducted, M2_DRV is the
low level, makes Q34 conducted, BAT_PWR12 charges to the main battery M-
BAT-PWR, is shown in figure 18-87.
When charging is completed to a certain power, the charging mode converts to

be the trickle charging, U42 (THINKER1) stops outputting BAT_CRG, and
outputs the high level of M_TRCL (the main battery trickle charging control
signal), one path of M_TRCL through D9 to take over the working of
BAT_CRQ and continues to send to CE, opens the charging chip, at the same
time, is added to TRICKLE pin of BQ24741 through D16, BQ24741 changes
the charging current to be 150mA, as shown in figure 18-88.
Figure 18-85: The production circuit of BAT-PWR12
Figure 18-86: The battery selection signal
Figure 18-87: The main battery charging circuit
The original of TRICKLE pin definition: Trickle current enable logic input.
When CE is HIGH, a HIGH level on this pin enables accurate 150mA trickle
charge with 20mΩ sense resistor. A LOW level on this pin enables the ISET pin
to program the charge current. It has an internal 1 MΩ pull down resistor.
[Explanation] The open pin of the trickle charge: When the CE pin is high, and
this pin is also high. It starts the current with 150mA to trickle charge. When
this pin is in low level, set the charge current by ISET pin, there is a pull-down
resistor with 1MΩ in it.
Figure 18-88: The charging chip received the trickle charging instruction
The small current CHARGE_OUT12 is sent to Q54, at the same time, the high
level of M_TRCL makes Q62 conducted, so Q54 is also conducted, to produce
the small current M-BAT-TRCL. As shown in figure 18-89.
Figure 18-89: The production circuit of M-BAT-TRCL
The small current M-BAT-TRCL through the fuse F9 charges to the main
battery M- BAT-PWR as shown in figure 18-90.
Figure 18-90: The main battery trickle charging
Chapter 19
Analysis of AMD Platform
Timing Sequence
AMD platform mainly has nVIDIA and AMD two chipsets, at present, only
AMD is selling on the market although nVIDIA has quit, but there is still a part
of the amount of nVIDIA maintenance. In this chapter, use as the "the standard
timing sequence diagram and analysis of the circuit of using this chipset models”
to analyze the timing sequence features of two chipsets.
19.1: The Standard Timing Sequence of

nVIDIA
This section describes nVIDIA chipset motherboard matched AMD CPU. The
standard timing sequence of nVIDIA chipset is shown in figure 19-1, the
Figure 19-1: The standard timing sequence of nVIDIA chipset
+3.3V_VBAT: the RTC circuit power supply of the South bridge, is same as
VCCRTC of Intel.
RTC_RST#: the reset of RTC circuit, 3V.
32.768 kHz: the clock of RTC circuit.
+3.3V_DUAL/+1.5V_DUAL:the standby voltage of 3.3V and 1.5V, some of
the latter is 1.2V_DUAL, and some is 1.1V_DUAL.
SUSCLK: The South Bridge sends 32 kHz clock after the standby voltage
being normal.
25MHz xtal: 25MHz crystal of the South Bridge of nVIDIA, it will affect
power-on.
PWRGD_SB: the standby voltage good, is equal to RSMRST#, 3.3V.
PWRBTN#: the trigger signal sent to the South Bridge.
SLP_S5#: the South bridge sends the signal of exiting the power off state,3.3V,
is usually used to open the memory power supply.
+1.8V_SUS/+0.9V_SUS: the memory power supply and the memory load

power supply.
MEM-VLD: the memory power supply good, sends 3.3V to the South Bridge
it means that the voltage opened by SLP 35# has normal.
SLP_S3#: 3.3V sent by the South Bridge, the signal of exiting the sleep state, is
usually used to open the power supply of the bridge and VDDA power supply.
VDDA2.5V/CORE Power: VDDA2.5V is a PLL power supply needed by CPU,

CORE Power refers to the core power supply of the bridge.
PWRGD: after the power supply of the bridge being normal, sends 3.3V to the
South Bridge, it means that the voltage opened by SLP_S3# has normal.
*_CLK: after the power supply of the bridge being normal, the bridge internal
integrated of the clock chip starts to work, and sends the each clock.
CPUVDD_EN: the South bridge sends the high level 3.3V,is used to open CPU
power supply.
+V_CPU: the core power supply of CPU.
CPU VLD: CPU power management chip sends 3.3V to the South Bridge, it
means that CPU power supply has normal.
HTVDD_EN: The South Bridge sends the high level 3.3Vis used to open bus
power supply 1.2V.
+ 1.2V_HT: the bus power supply 1.2V.
HT_VLD: after the bus power supply being normal. Returned 3.3V high level
to the South Bridge, it means that the bus power supply has normal.
PCIRST#: after the South Bridge receiving HT_VLD, sends 5 of 3.3V reset (4
of PCIRST#, 1 of LPCRST#).
CPUPWROK: single bridge is that the bridge sends directly

HT_MCP_PWRGD to CPU. The double bridge is that the South Bridge sends
HT_MCP_PWRGD to the North Bridge, and the North Bridge sends

HT_CPU_PWRGD again to CPU.
CPURST#: single bridge is that the bridge sends directly HT_MCP_RST# to

CPU. The double bridge is that the South Bridge sends HT_MCP_RST# to the
North Bridge, and the North Bridge sends HT_MCP_RST# again to CPU.
19.2: The Explanation of nVIDIA Chipset

Timing Sequence (MSI MS-16352)
As MSI MS-163 52 an example to analyze nVIDIA chipset timing sequence,
skip the RTC circuit.
First, the adapter interface CN1 inputs 19V, through the inductance PFL1 to
produce +DC_IN to send to the S pole of PQ1, through PR 146 and PR 148
divided into pressure to get 3.1V to control PQ1 to be conducted, produces
DC_IN, is shown in figure 19- 2. (AC_CTL is sent by EC, uses the adapter
alone, EC does not work, only when the battery is inserted, if EC does not
detect the adapter, and then it will send the high level of AC_CTL to make PQ3
conducted. PQ2 is also conducted, +DC_TN is added directly to the G pole of
PQ1, PQ is cut off.)
Figure 19-2: The adapter insert circuit
The first path of DC_IN through PR158 to produce SDC_IN, the second path
through PD5 sends to DCIN of MAX1772, the third path through PR160 and
PQ161 divides into pressure MAX1772_ACIN of 2.24V to send to 11 pin
ACIN, is shown in figure 19-3.
Figure 19-3: The adapter detection part circuit of the charging chip
Figure 19-4 is the screenshot of part of pin definition of MAX 1772. When
ACIN pin is less than 2.048V (REF/2), ACOK will open drain output, and when
ACIN is higher than 2.048V, ACOK will output low level. The relationship
between ACIN and REF/2, ACOK is shown in figure 19-5.
Figure 19-4: The screenshot of part of pin detection of MAX1772
Figure 19-5: ACOK internal block diagram of MAX1772

The low level of AC_OK#, one path is sent to EC, and another path is sent to
PQ5, is shown in figure 19-6. PQ5 is a dual N-channel composite tube. When
AC_OK# is low level, D2 and S3 are cut off, D2 is pulled up to be high level
AC_OK by +3VALW, is sent again to GL so Dl and SI will be conducted, Dl
becomes to be low level.
SDC_IN+ through PQ4A body diode produces the small current PWR_SRC,
trough PR153 and PR152 divides into pressure to be the relative low level
1.73V, controls PQ4A to be conducted completely and produces the large
current common point PWR_SRC.

Next, analyze the production of +3VALW and +5VALW: PWR_SRC through
PR184 insurance resistance sends to 22 pin VIN of PU2 as the main power
supply, is shown in figure 19-7.
Figure 19-7: TPS51120 circuit

In the figure 19-7, EN3 and ENS are vacant, default open 3V/5V linear voltage.
The screenshot of the pin definition of EN3 and EN5 is shown in figure 19-8.
Figure 19-8: The screenshot of the pin definition of EN3 & EN5 of TPS51120
The screenshot of part of TPS51120 internal principle is shown in figure 19-
9.After VIN entering, through P-channel tube produces VREG3 and VREG5. P-
channel tube is controlled by the comparator, the reverse input end of the
comparator is 1.25V internal reference source, and the non-inverting input end
is from the output voltage through dividing into pressure.
TPS51120 outputs +3VALW to send to EC as the standby power supply, is

EC supplies power to the crystal, the crystal oscillates to send 32 kHz frequency
to EC, is shown in figure 19-11. +3VALW through R424 and C864 delays send
high level of ECRST# as the reset of EC, is shown in figure 19-12.
Figure 19-9: The screenshot of the part of TPS51120 internal principle
Figure 19-10: EC gets the power supply
Figure 19-11: EC gets the standby clock
Figure 19-12: EC gets the standby reset

EC starts to read the program in the U8 (BIOS), is shown in figure 19-13.
Figure 19-13: EC reads BIOS

After EC receiving the adapter signal AC__OK#, outputs SUS_ON from 155
Figure 19-14: EC sends SUS_ON

SUS_ON is sent to TPS51120, controls the production of+3VSUS and +5VSUS,
is shown in figure 19-15. After two path of PWM being normal, open drain
outputs +3.3VSUS_PG, then renames to be SUSPWROK later.
Figure 19-15: The standby voltage control circuit (Control outputs +3VSUS &
+5VSUS)
One path of +3VSUS is sent to the South bridge as the main standby voltage
3.3V, another path through PU3 voltage regulator produces +1.5VSUS as the
second standby voltage of the South bridge, is shown in figure 19-16.
Figure 19-16: The production circuit of the second standby voltage of the South
Bridge
Next, as shown in figure 19-17, 25MHz crystal of the South Bridge oscillates,
this crystal is the necessary condition for nVIDIA to power-on.
Figure 19-17: 25MHz crystal of the South Bridge

After 3SVSUSand 5VSUS producing normally from TPS51120, sends
SUSPWROK to the South Bridge PWRGD_SB, it means that the standby
voltage is normal, is shown in figure 19-18.
Figure 19-18: The South Bridge receives that the standby voltage is normal
The trigger switch produces PWRSW- to send to EC, is shown in figure 19-19.
Figure 19-19: The switch trigger circuit

EC sends the low level of PWRBT- through D15 to pull PM_PWRBTN# low, is
shown in figure 19-20. PM_PWRBTN# is sent to the South Bridge, that is to
say, the South Bridge received the trigger signal.
Figure 19-20: EC sends the trigger signal

After the South Bridge receiving PWRBTN#, sends SLP_S5# to rename to be
PM_SLP_S5#, one path is sent to EC, another path is sent to PU4 (OZ813) to
control production of The memory main power supply CPU_VDDIO_SUS, and
sends VTT_VDDIO_PG, is shown in figure 19-21.

The memory main power supply is sent to PU7, produces CPU_VTT_SUS.is
shown in figure 19-22. The specific working process: +5VSUS supplies power
to 5,6,7,8 pin of PU7, CPU_VDDIO_SUS supplies power to 1 pin of PU7,
CPU_VDDIO_SUS through PR231 and PR232 divided into pressure gets 0.9V
to send to 3 pin of PU7 as the reference voltage input, at last,PU7 outputs
CPU_VTT_SUS with 0.9V from 4 pin.
Figure 19-22: The production circuit of the memory VTT
VTT_VDDIO_PG is sent to the South bridge MEM_VLD, it means that the

memory power supply has normal, is shown in figure 19-23.
Figure 19-23: The South Bridge receives that the memory power is normal
The South bridge sends SLP_S3#, renames to be PM_SLP_S3#, one path is sent
to EC, and another path through R434 generates directly RUN_ON (R436 is not
installed), is shown in figure 19-24.
Figure 19-24: The production circuit of RUN_ON
One path of RUN_ON through twice opposition of PQ16 and PQ19 produces
RUND, from PWR_SRC through PR200 and PR204 dividing into pressure to
be 15.6V, is shown in figure 19-25.
Figure 19-25: The production circuit of RUND
RUND controls PQ14 conducted, converts +5VSUS to be +5VRUN, control

PQ15 to be conducted, and converts +3VSUS to be +3VRUN, is shown in
figure 19-26.
Figure 19-26: The production circuit of +5VRUN and +3VRUN
+3VRUN is sent to PU6 to produces +2.5VRUN, is shown in figure 19-27.
Figure 19-27: The production circuit of +2.5VRUN
Another path of high level of RUN_ON makes PD10 to be cut off, +2.5VRUN
through PR226 and PR293 divides into pressure to be 2.4V to send to PU4,
controls production of +1.2VRUN as the core power supply of the bridge, and
sends +l_2VRUN_PG, is shown in figure 19-28.

+1_2VRUN_PG is sent to PU9, opens the core power supply G73M_CORE of
the independent graphics, sends +1V_VGA_PG after being normal, is shown in
figure 19-29.
Figure 19-29: The production circuit of G73M_CORE
+1 V_VGA_PG is sent back to 6 pin of PU9, is used to open +1.8VRUN to

supply power to the graphics and video memory, sends +1_8VRUN_PG after
being normal, is shown in figure 19-30.
+1_8VRUN_PG is sent PU10 and PU12 to control production of +1.5VRUN to

supply power to the South bridge and +1_2VRUN_G73M to supply power to
the graphics, is shown in figure 19-31 and 19-32.
In the figure 19-31 and figure 19-32, after PU10 and PU12 working normally,
sends respectively +1_5VRUN_PG and +l_2VG73M_PG, phase with
RUN_ON to form RUN_PWRGD, is shown in figure 19-33.
Figure 19-32: The production circuit of +1_2VRUN_G73M
Figure 19-33: The production circuit of RUN_PWRGD
RUN_PWRGD is sent to PWRGD pin of the South Bridge, is shown in figure

19-34.
Figure 19-34: South Bridge receives RUN_PWRGD
RUN_PWRGD is sent to Q33, makes D2 and S2 conducted, D2 connects SI, as

long as DVI_A_HPD of G1 has high level (DVI interface hot drawing insert
detection signal), D1 will be pulled down, Q34 will be conducted, and produces
IFPCD IOVDD, as the power supply of DVI display module of G73 graphics, is
shown in figure 19-35. In addition, RUN_PWRGD is also used to control
CPU_HT_RESET#, we don't explain in detail here again.
Figure 19-35: The production circuit of IFPCD IOVDD
After the South Bridge receiving PWRGD, sends the clock signal and
CPUVDD_EN, renames to be VDD_EN, is shown in figure 19-36.
Figure 19-36: The South Bridge sends CPUVDD_EN
VDD_EN is sent to MAX8774 (PU11) to open CPU core power supply

CPU_VDD_RUN, after CPU core power supply being normal, sends VDD_ PG,
Figure 19-37: CPU core power supply circuit

VDD_PG is sent back to CPU_VLD pin of the South Bridge, the South Bridge sends
HTVDD_EN, renames to be VLDT_EN, as shown in figure 19-38.
The high level of VLDT_EN makes D1 pin of PU1 to be pulled down, D1 connects
G2, D2 and S2 will be cut off, D2 is pulled up to be 15.6V high level by RUND,
controls PQ24 to be conducted completely and produce +VLDT, the voltage is
1.2V, as shown in figure 19-39.
Figure 19-38: The South Bridge sends the bus power supply open signal
Figure 19-39: The production circuit of the bus power supply

+VLDT through PR230 added to the B pole of PQ26, PQ26 conducted and
pulled PQ25 grid low, PQ25 is cut off, +3VRUN through PR228 pulled up
VLDT_PG as shown in figure 19-40.
Figure 19-40: The production circuit of VLDT_PG

VLDT_PG is sent to HT_VLD pin of the South Bridge, is shown in figure 19-
41.
Figure 19-41: The South Bridge received VLDT_PG
At last, the South Bridge sends PCI_RESET#, LPC_REEST to EC and other

load chip, the South Bridge does not send MCP_PWRGD and MCP_RST#, is
Figure 19-42: The South Bridge sends PG and Reset
MCP_PWRGD and MCP_RST# through OR gate converts to be

HT_MCP_PWRGD and HT_MCP_RST# to send to the North bridge is shown
in figure 19-43.

After the North Bridge reading BIOS correctly, sends HTCPU_STOP#,
HTCPU_RST#, HTCPU_ PWRGD, is shown in figure 19-44.
Three of high level signal are sent to U019, RUN_PWRGD is also sent to U019,
is shown in figure 19-45.Three signals are high, when RUN_PWRGD is also
high, U019 open drain outputs. CPU_ALL_PWROK, CPU_LDTSTOP#,
CPU_HT_RESET# are pulled up to be 1.8V by CPU_VDDIO_SUS, sends to
CPU. Then, the timing sequence is completed.
Figure 19-44: The North Bridge sends PG and reset
Figure 19-45: The production circuit of PG and reset of CPU
19.3: The Standard Timing Sequence of AMD

Chipset
AMD chipset mainly refers to A50M, A70M and other new chipset matched
with APU, the standard timing sequence of this chipset is shown in figure 19-46.
In the figure 19-46, the explanation of signal is below.
Figure 19-46: The standard timing sequence of AMD chipset

VDDBT_RTC_G: the power supply of RTC circuit, 3V. If RTC circuit of
AMD chipset is wrong, it will lead to no reset, do not run the code, sometime is
light and sometime is not light and other failures.
RTC clock In: the crystal oscillates to supply 32.768kHz frequency to the
bridge. If RTC circuit is wrong, it will lead to no reset.
VDDIO_33_S: the main standby voltage of the bridge, 3.3V.
VDDCR_1l_S: the second standby voltage of the bridge, 1.1V.
RSMRST#: the standby voltage good of the bridge, 3.3V.
PWR_BTN#: after the power switch triggering, it’s sent the trigger signal to the
bridge at last, is high-low-high pulse.
WAKE#: awaken signal, is usually from the network card chip, the function is
similar to PWR_BTN#.
SLP_S5#: the bridge sends the signal of exiting the shutdown state, 3.3V, is
used to control the production of the memory power supply.
SLP_S3#: the bridge sends the signal of exiting the sleep state, 3.3V, is used to
control all of S0 voltage.
All Power Rails: all power are opened, including the memory power supply,
the bridge power supply, and more power supply required by CPU, the single
bridge chipset has no power supply.
PWR_GOOD: inform the bridge that the voltage of S0 state is normal at this
time.
CLK: the clock integrated within the bridge starts to work.
APU_PG: the bridge sends the power good to CPU. A50 platform is also called
LDT_PG.
A_RST#: the bridge sends the platform reset, is equivalent to PLTRST# of Intel,
3.3V.
PCIE_RST#: the bridge sends PCI-E reset, 3.3V.
PCIRST#: the bridge sends PCI reset, 3.3V.
APU_RST#: the bridge sends the reset to CPU directly. A50 platform is also
called LDT_RST#.
19.4: The Timing Sequence of AMD Chipset

(ACER 4235, Quanta ZQE)
ACER 4235 is produced by Quanta, the board number is ZQE, uses AMD
chipset, and the timing sequence of the chipset is shown in figure 19-47.
Figure 19-47: The timing sequence of Quanta ZQE

0: RTC circuit supplies the voltage and 32 kHz frequency to FCH Bridge.
+3VPCU supplies power to EC, and supplies the reset to VCC_POR# pin of EC.
1: the trigger switch produces NBSWON# to EC.
2: EC sends S5_ON.
2-1: S5_ON is sent to PQ10 to open +3V_S5, S5_ON is sent to PU8 to control
the production of +1.1V_S5.
2-2: after PIS outputting +1.1 V_S5 normally, then sends HWPG_1.1 V.
3: EC delays send ICH_RSMRST# to the bridge.
4: EC delays send DNBSWON# to PWRJBTN# of the bridge.
5/6: the bridge sends SLP_S5# and SLP_S3# to EC.
5-1: after EC receiving SUSC#, then sends SUSON to the circuit of PQ36 and
PQ40 and PU10.
5-2: PQ40 converts & output +5VSUS; PU10 controls to produce the memory
main power supply +1.5V_SUS, the reference voltage +SMDDR_VREF and
the memory load power supply +0.75V_DDR_VTT.
5-3: after PU10 working normally, then sends HWPG_1.5V.
6-l: after EC receiving SUSB#, then sends MAINON to PU7, PU4, and
produces MAIND signal to PQ18, at the same time, EC sends VR_ON to send
to PU6.
6-2: PU7 controls the production of+1V,PU4 controls the production of +1.8V,
MAIND controls the production of +5V, +3V, +1.1V, +1.5V, PU6 controls the
production of CPU core power supply +VCORE and +NBCORE.
6-3: after PU7 and PU4 working normally, is sent to HWPG_1V and
HWPG_1.8V; after PU6 working normally, sends CPU_COREPG.
7: all of HWPG_* joints together to form HWPG and send to EC, is shown in
figure 19-48.
Figure 19-48: The production circuit of HWPG

8: after EC receiving HWPG then sends PWROK_EC.
9: PWROK_EC and phase with CPU_COREPG sent by PU6, forms

SB_PWRGD_IN to send to the Bridge, as the condition of the Bridge sending
reset.
10: the bridge sends APU_PWRGD to APU, it means that all power supply are
normal.
11: the bridge sends A_RST#, PCIE_RST#, LDT_RST#. A_RST# and
PCIE_RST# is sent to the onboard chip slot and others, LDT_ RST# is sent to
APU, CPU starts to work.
19.5: The Explanation of AMD A70M (Lenovo

G485, Compal LA-8681P)
AMD A70M is the chipset developed by the super micro company for the
second generation APU platform, about the standard timing sequence of it, we
can refer to AMD standard timing sequence in 19.3 section. Next, analyze the
machine used this chipset, its Lenovo G485, is OEM produced by Compal, the
board number is LA-8681P.
19.5.1 RTC circuit

RTC circuit of AMD platform will cause all kinds of strange problem, such as
no reset, sometime is light (starts-up) and sometime is no light (can’t starts-up)
and others. About machines (AMD platform laptop) with wrong (strange
problem), please note if RTC circuit is normal (check their RTC circuit first).
As shown in figure 19-49, when the adapter and the large battery are not
plugged, CMOS battery of JRTC2 through PR131, PR132 produces CHGRTC,
then through PD109 produces +RTCBATT. After plugging the power,
RTCVREF will replace the power supply of the battery, and can charge CMOS
battery.
Figure 19-49: RTC power supply circuit

+RTCBATT through R105 supplies power to VDDBT_RTC_G of the bridge is
Figure 19-50: FCH gets RTC power supply

After the bridge getting +RTCBATT, the crystal Y1 connected by 32K_X1 and
32K_X2 gets the power supply, the crystal oscillates to produce 32.768kHz
clock to the bridge, is shown in figure 19-51.
Figure 19-51: RTC crystal circuit
19.5.2 Protective Isolation circuit
Plug the adapter, producing VIN, is shown in figure 19-52.
Figure 19-52: The production circuit of VIN
As shown in figure 19-53,VIN through PQ301 body diode produces P2 first,

PQ301 and PQ302 must be conducted completely, then it will produce the
common point B+, the condition of conducting is that the voltage of P2-1 point
is less than 14V.Any of the field effect tube PQ308 and PQ307B is conducted,
then it can form partial pressure, and produce P2-1 been less than 14V.The
signal of controlling PQ308 is that BATT_OUT is high; and controlling
PQ307B to be conducted is that PACIN and ACON are high, and ACOFF must
be low.
Look at BATT_OUT first, if it wants to be high level, PQ202 and PQ203 must
be cut off, and is pulled up by +3VALW. During analyzing, the battery voltage
VMB2 must be less than 8.95V, and EC sends BATT_LEN#, then BATT_OUT
will be high, at the same time, +3VALW must be power on, is shown in figure
19-54. That is to say, before the common point not produced, this circuit didn't
control the production of the common point.
Figure 19-54: The circuit of BATT_OUT

Next, look at PACIN, ACON, ACOFF. ACON is connected to other places, it
means that this machines has no power supply in advance(ignition loop) owned
by Compal. ACOFF connects EC, at this time, the common point is not
produced, EC is no power, and ACOFF is low.
VIN through PQ301 MOSFET produces P2 to send to VCC, VIN through

PR314 and PR317 divides into pressure to ACDET is shown in figure 19-55.
ACOK# output internal block diagram of BQ24727 is shown in figure 19-56.

Analyze the internal block diagram of BQ24727, when the voltage of ACDET
is higher than 0.6V, VCC voltage is higher than 3.75V, the chip outputs the
linear voltage REGN,6V, renamed to be BQ24727VDD; when ACDET voltage
is higher than 2.4V, the chip outputs the low level of ACOK#, renamed to be
ACPRN.
The low level of ACPRN makes PQ316 to be cut off, BQ24727VDD divides
into pressure to produce PACIN about 3.3V, then converts out ACIN to send to
EC at the same time, is shown in figure 19-57. Only when the system program
corrects the electric quantity of the battery, then EC will send the high level of
ACOFF, under other cases, ACOFF is low.
Figure 19-55: The circuit screenshot location of the charging circuit
Figure 19-56: The screenshot of BQ24727 internal block diagram
Figure 19-57: The production circuit of PACIN and ACIN
19.5.3 The standby power supply

One path of the common point B+ is renamed to be RT8205_B+ to send to VIN
of RT8205, another path through PR411 and PR412 divided into pressure to
send to EN is shown in figure 19-58.
Figure 19-58: +B is renamed to be RT8205_B+ and sent to the standby chip
According to RT8205 (PU401) data manual, after RT8205 getting VIN and EN,
then it can output linear VREG3, VREG5, and REF.
VREG3 output by the chip renames to be +3 VLP, is shown in figure 19-59.
Figure 19-59: RT8205 outputs the linear voltage
In RT8205 data manual, EN threshold value is the lowest, 1V, so the lowest
voltage of B+ is 6V, is shown in figure 19-60.
Figure 19-60: The screenshot of the description of electrical specification of EN

threshold value in RT8205 data manual
+3VLP supplies power to U3l (EC), is shown in figure 19-61.

After EC identifying ACIN, EC sends EC_ON (if EC does not identify ACIN, it
needs to receive ON/OFF, then sends EC_ON), is shown in figure 19-62.
Figure 19-62: EC sends EC_ON
EC_ON through PR418 added to the B pole of PQ406, PQ406 is conducted,

PQ405A and PQ405B are cut off (MAINPWON connects to the temperature
control circuit, when there is no over-temperature, it won't be low), "@" means
no part, is shown in figure 19-63.
Figure 19-63: EC_ON control circuit
ENTRIP1 and ENTRIP2 of RT8205 are not pulled down directly, and through
each resistance PR406 and PR405 to be grounded, as the over-current threshold
value setting, and opens two path of PWM (pull up internal), is shown in figure
19-64.
Figure 19-64: RT8205 gets the open by PWM

RT8205 outputs +3VALWP and +5VALWP, through the isolation point PJ402
and PJ403 renamed to be +3VALW and +5VALW, is shown in figure 19-65.
Figure 19-65: The isolation of +3VALW and +5VALW
After RT8205 producing +3VALW and +5VALW normally, open drain outputs
SPOK, is shown in figure 19-66.
Figure 19-66: RT8205 outputs SPOK

Pulled up to be high level by VL to control PQ204 conducted, makes PR218
and PRR220 to divide into pressure, controls PQ205 conducted, produces
+VSBP, through the isolation point PJ201 to rename to be +VSB, is shown in
figure 19-67.
+3VALW supplies power to EC directly, and through L45 converts to be
+EC_AVCC to supply power to EC, is shown in figure 19-68.
Figure 19-67: The production circuit of +VSB

EC of this machine is not need the standby clock, +3VALW through delaying to
reset EC, is shown in figure 19-69.
Figure 19-69: EC gets the reset

EC reads the pin vacancy of ROM; it means that EC has its own program in it,
Figure 19-70: SPI pin of EC is vacant
+3VALW supplies power to the bridge at the same time, as shown in figure 19-
71.
Figure 19-71: FCH gets the standby power supply

+5VALW supplies power to PU601, SPOK is sent to EN of PU601, PU601
outputs +1.1VALWP, through the isolation point to convert to be +1.1VALW,
Figure 19-72: The production circuit of +1.1VALW

+1.1VALW is sent to the bridge as the second standby voltage, is shown in
figure 19-73.
Figure 19-73: The bridge gets the standby voltage with 1.1V
19.5.4 The trigger switch

Press the switch, producing ON/OFFBTN#, is shown in figure 19-74.
Figure 19-74: The switch interface
ON/OFFBTN# through R720 produces ON/OFF, is shown in figure 19-75.

Component with "@" in the figure is not installed, such as D24, R535 and
others.
Figure 19-75: The production circuit of ON/OFF
ON/OFF is sent to EC, is shown in figure 19-76.
Figure 19-76: EC receives the trigger signal
After EC receiving ON/OFF, sends EC_RSMRST# first, when detects that

LID_SW# of 115 pin is high, then sends PBT OUT#, is shown in figure 19-77.
Figure 19-77: The screenshot of the trigger circuit of EC
EC_RSMRST# and PBTN_OUT# are sent respectively to RSMRST# and

PWR_BTN# of the bridge, after the bridge receiving PWR_BTN#, sends
PM_SLP_S5#, PM_SLP_S3#, is shown in figure 19-78.
Figure 19-78: The screenshot of the trigger circuit of FCH
PM_SLP_S5# and PM_SLP_S3# are sent to EC, is shown in figure 19-79.
Figure 19-79: EC receives the power-on signal
19.5.5 Produce Power Supply
After EC receiving SLP_S5#, sends the high level of SYSON, is shown in

figure 19-80.
Figure 19-80: EC sends SYSON

SYSON is sent to EN pin of PU501 (TPS51212), is shown in figure 19-81.
Figure 19-81: The memory power supply chip
After PUT501 receiving EN and the power supply sent by +5VALW, produces
+1.5VP, through the isolation point to rename to be +1.5V, is shown in figure
19-82.
Figure 19-82: The production of the memory power supply
After EC receiving SLP_S3#, sends the high level of SUSP#, is shown in figure
19-83.
Figure 19-83: EC sends SUSP#
One path of SUSP# controls Q61 conducted, pulls 1.5VS_GATE low, makes
the G pole of Q55 to be low level. Q55 is P-channel, the G pole low level can be
conducted, +1.5V through Q55 produces +1.5VS, is shown in figure 19-84.
Figure 19-84: The production circuit of +1.5VS
SUSP# is sent to PU502, is used to control the production of +1.8VSP, through

the isolation point to rename to be +1.8VS, as shown in figure 19-85.
SUSP# is sent to PU602, controls the production of +1.05VSP, through the

isolation point to rename to be +1.05VS, as shown in figure 19-86.
SUSP# through Q63 inverts to be the low level of SUSP is shown in figure 19-
87.
Figure 19-87: The production circuit of SUSP
SUSP is used to open +5VS, +3.3VS, +1.1VS, is shown in figure 19-88, figure
19-89, figure 19-90. As +5VS an example to analyze: the low level of SUSP
controls Q59 to be cut off, +VSB through R584 and R587 pulls up the G pole of
Q34. U34 is N-channel, +VSB with 19V is enough to make it conducted
completely, +5VALW through U34 produces +5VS.
SUSP controls PQ701 to be cut off. +3VALW and +1.5V supplies power to
PU701, +1.5V is divided into pressure to be 0.75V to VREF, PU701 produces
+0.75VSP, through the isolation point renamed to be+0.75VS, as shown in
figure 19-91.
19.5.6 APU power supply

After EC receiving PM_SLP_S3#, delays send VR_ON, is shown in figure 19-
92. VR_ON is sent to ISL6265, is shown in figure 19-93.
Figure 19-92: EC sends VR_ON
Figure 19-93: VR_ON is sent to APU core power supply
ISL6265 gets the power supply and receives SVD/SVC, the chip produces APU
core +APU_CORE and +ACPU_CORE_NB (note, at this time, SVC/SVD is
pulled up by 1.8V, is only used as PVID to use, APU power supply is about
1.4V, only when APU power supply chip gets PWROK, then it will start to
decode SVID). After power supply being normal, ISL6265 sends VGATE, is
VGATE is sent to EC, is shown in figure 19-95.
After EC receiving VGATE, sends FCH_PWRGD, is shown in figure 19-96.
FCH_PQRGD is sent to PWR_GOOD of the bridge, is shown in figure 19-97.
19.5.7 Clock, PG & Reset

After the power supply of the bridge being normal, 25MHz crystal Y4 oscillates
is shown in figure 19-98. After the bridge receiving FCH_PWRGD, the clock
integrated internal starts to work, and sends each clock.
Figure 19-94: APU power supply chip
Figure 19-95: EC receives VGATE
Figure 19-96: EC sends FCH_PWRGD
Figure 19-97: FCH receives PWR_GOOD
Figure 19-98: 25 MHz crystal
The bridge sends APU_PWRGD, is shown in figure 19-99.
Figure 19-99: FCH sends APU_PWRGD
One path is sent to ISL6265, is used to activate the SVI interface of ISL6265,
runs I2C protocol, decodes SVID, and is shown in figure 19-100.
Figure 19-100: ISL6265 receives APU_PWRGD
The original of the explanation of PWROK pin of ISL6265:

System power good input. When this pin is high, the SVI interface is active and
I2C protocol is running. While this pin is low, the SVC, SVD, and VFIXEN
input states determine the pre-PWROK metal VID or VFIX mode voltage. This
pin must be low prior to the ISL6265 PGOOD output going high per the AMD
SVI Controller Guidelines. Another path of APU_PWRGD is sent to APU, is
Figure 19-101: Another part of APU_PWRGD is sent to APU

The bridge sends A_RST#, PCIRST#, PCIE_RST# again. Only A_RST# is
used, and renames to be PLT_RST#, is shown in figure 19-102.
Figure 19-102: The Bridge sends the reset
PLT_RST# is sent to the network card and EC, is shown in figure 19-103 and
figure 19- 104.
Figure 19-103: The network card receives the reset
Figure 19-104: EC receives the reset

PLTRST# convert to be APU_PCIE_RST#, is shown in figure 19-105.
Figure 19-105: PLTRST# renames to be APU_PCIE_RST#

APU_PCIERST# is sent to JWLN1 (MINI PCI-E), is shown in figure 19-106.
Figure 19-106: MINI PCI-E slot receives the reset
APU_PCIE_RST# is also sent to U7, phase with PXS_RST# to produce

GPU_RST#, and is shown in figure 19-107.
Figure 19-107: The production circuit of GPU_RST#
At last, the Bridge sends APU_RST# and sent to APU, as shown in figure 19-
108.
Figure 19-108: The Bridge sends APU_RST# to APU
19.5.8 The independent graphics working timing sequence

EC sends the low level of VGA_GATE# to control Q112 to be cut off, the
bridge sends the high level of PXS_PWREN, is shown in figure 19-109.
Figure 19-109: The circuit screenshot location of PXS_PWREN
PXS_PWREN controls the production of +3VGS and is shown in figure 19-110.
Figure 19-110: The production circuit of +3VGS
PXS+PWREN through Q26 converts to be PXS_PWREN#, is shown in figure

19-111.
Figure 19-111: The production circuit of PXS_PWREN#
PXS_PWREN# is used to open +1.0VGS and +1.8VGS, is shown in figure 19-

112 and figure 19-113.
Figure 19-112: The production circuit of +1.0VGS

PXS_PWREN is also sent to the OR gate U10, phase with +3VGS, produces
PX_MODE (PX_EN is from the graphics card chip), as shown in figure 19-114.
Figure 19-114: The production circuit of PX_MODE
One path of PX_MODE is used to control the production of +1.5VGS, is shown

in figure 19-115.

Another path of PX_MODE is sent to PU801, is shown in figure 19-116.
Figure 19-116: PU801 receives PX_MODE
PU801 controls the production of the graphics card core power supply
+VGA_COREP, through the isolation point renames to be +VGA_CORE. After
the power supply being normal, sends VGA_ PWRGD, is shown in figure 19-
117.
VGA_PWRGD is sent to U9,phase with PX_MODE, outputs the high level to
control Q68 conducted, pulls 1.0V_ON# low, and makes Q68 to be cut off at
the same time, makes VDDC_ON# to be high level of invalid state, is shown in
figure 19-118.
Figure 19-117: The production circuit of +VGA_CORE

The low level of 1.0V_ON# controls Q18 and Q19 to be cut off, the high level
of VDDC_ON# controls Q22 and Q23 to be conducted, converts +VGA_CORE
to be +BIF_VDDC, is shown in figure 19-119.
Figure 19-119: The production circuit of +BIF_VDDC

VGA_PWRGD is sent to the Bridge, is shown in figure 19-120.
Figure 19-120: FCH receives VGA_PWRGD
After the bridge receiving VGA_PWRGD, because PEG_CLKREQ#_R is

forced to be pulled down to be the low level by the resistance R183, the bridge
sends automatically 100MHz difference clock CLK_PCE_VGA and
CLK_PCIE_VGA# to VGA, is shown in figure 19-121.
The bridge sends the high level of reset signal PXS_RST# of the graphics card
again, is shown in figure 19-122.
PXS_RST# phases with APU_PCIE_RST# to produce GPU_RST# to send to
the graphics card, is shown in figure 19-123.
Figure 19-121: FCH sends the graphic card clock
Figure 19-122: The Bridge sends the graphics card reset
Figure 19-123: The graphics card receives the reset
Chapter 20
Analysis of the Laptop
Battery Charging Circuit
There are all kinds of laptop charging chip, but it can be divided into two
categories usually, first, is the old charging chip used under the Intel 1965
platform, the representative mode 1 is MAX1772;second.is the new charging
chip used above Intel GM45 platform, uses SMBUS to transfer the charging
instruction, the representative model are ISL88731 and others. Next, analyze
respectively the working principle of two kinds of charging chip.
20.1: Analysis of Charging Chip MAX1772

Used Usually Under Intel 965GM Platform
MAX 1772 is the charger with high integration density, low cost and more
chemical battery brought out by Maxim Company of USA, it can form the
battery charger with high precision and high efficiency by taking advantage of
it.MAX1772 also possesses the function of the adapter detection. MAX1772 has
the following features:
• Input current limit;

• The precision of output voltage is about 0.7%;
• Can provide the charging current more than 4A;
• The efficiency has a maximum of 95%;
• The duty cycle has a maximum of 99.99%;
• The application range is wide, is suitable for Li+, NiCd, NiMH battery
charging;
• The maximum battery voltage can reach to 18.2V;
• Low cost;
• The charging current and the charging voltage can be controlled by the
analog input.
20.1.1The name and the definition of the pin

MAX 1772 uses double row 28 pin packaging, the top view of the pin
permutation is shown in figure 20-1. The pin definition of MAX 1772 is shown
in table 20-1.
(Pins) --------- (Description)

1. the power input pin.
2. the linear voltage. It makes the voltage input by DCIN pin to output 5.4V
after being adjusted by the linear, during using, it should connect a shunt
capacity with 1uF between this pin and the ground.
3. the adapter current limit input.
4. 4.096V reference voltage output.
5. charge compensation capacitor connection.
6. the output current regulation loop compensation end.
7. voltage regulation loop compensation end.
8. analog ground.
9. analog ground .
10. the battery charging signal amplification output, when the working mode
converts from the voltage model to the current mode, this end can be used to
monitor and display the size of the charge current.
11. the adapter voltage detection.
12. AC detection outputs the open drain output form. When ACIN voltage is
less than REF/2, this pin open drain outputs.
13. the reference input.
14. the charging current control. The range of voltage is REFIN/32-REFIN.If
its less than REFIN/55. the chip stops charging.
15. the maximum output voltage setting input. The range of voltage is 0-
REFIN.
16. the battery serial number setting end, when this pin connects the ground,
sets to be two series, when it connects LDO, sets to be four series, when it
connects LDO/2,sets to be three series.
17. the battery voltage output pin.
18. the output current detection input negative terminal.
19. the output current detection input positive terminal. During using, it
should connect a current detection resistance between CSIN pin.
20. the power ground.
21. down tube driving output end. This end connects with the G pole of the
down tube.
22. the down tube drive power connecting terminal.
23. the power loop end of the top tube. This end connects with the S pole of
the top tube and the inductance.
24. the top tube drive output end. This end connects with the G pole of the
top tube.
25. the top tube drive connection end. During using, it should connect a
capacitance with 1uF between this pin and LX pin.
26. the adapter current detection negative terminal
27. the adapter current detection positive terminal.

28. the adapter input current monitor output.
20.1.2 Application Circuit

In this section, we mainly introduces the application of MAX 1772 in Quanta
CT6, is shown in figure 20-2.
The battery interface signal of CT6 is shown in figure 20-3, the explanation of
signal is below:
MBDATA, MBCLK: the system management bus data and clock.
TEMP_MBAT: battery over temperature indicator.
MBAT+: the main voltage of the battery interface
MBATV: the battery voltage sampling point, the sampling voltage is sent to EC,
EC judges the fault.
Figure 20-2: The application of MAX1772 in CT6
Figure 20-3: The battery interface signal of CT6
The working process:
MAX 1772 through CELLS and VCTL sets the charging voltage.EC through
the system management bus reads the battery parameter, then sends the
charging current setting signal CC-SET to ICTL pin of the charging chip, after
MAX 1772 receiving ICTL, starts to charge the battery according to the set
voltage and current, through charging current detection resistance to detect the
charging current. The setting of CELL pin is shown in figure 20-4, when the
voltage of CELLS pin is less than 0.2V, sets to be 2 core; when the voltage of
CELLS pin is higher than 0.4V and is less than the voltage reduce 0.5V of LDO
pin, sets to be 3 core; when the voltage of CELLS is higher than the voltage
reduce 0.25V of LDO pin, sets to be 4 core.
The calculation of the charging voltage: according to the figure 20-2, we can
know that CELLS is from the partial pressure of 1772_5.4V, is set to be 3 cores,
REFIN is connected to 3VPCU (3.3V), VCTL gets 0.848V by the partial
pressure of REF4.09. According to the formula (20.1), we can calculate that the
charging voltage is 12.6V. As the following:
The calculation of the charging current: in the figure 20-2, the charging current
detection resistance PR112 (is RS2 in the formula (20.2)) is 0.05Ω. According
to the formula (20.2), it only needs to change VICTL, and then the charging
current can be changed.
For example, if EC sends VICTL is 1V voltage, then we can calculate that the
charging current is 1.24A.
20.2: Analysis of The Charging Chip ISL88731

Used Usually by The Intel GM45
ISL88731 is the lithium ion battery charger controller with highly integrated
produced by Intersil Company, it can program through the system management
bus. It is different from the traditional charging chip, ISL88731 though SMBUS
communicates with EC to control charging, SMBUS connects the battery
interface.EC and the charging chip at the same time. The charging voltage,
charging current, charging enable and other control signals are transmitted
through SMBUS, no VCTL, VICTL and other pins.ISL88731 has two functions
of the adapter detection and charging control. The main features of ISL88731:
• 0.5% Battery Voltage Accuracy

• 3% Adapter Current Limit Accuracy
• 3% Charge Current Accuracy
• SMBUS 2-Wire Serial Interface
• Battery Short Circuit Protection
• Fast Response for Pulse-Charging
• Fast System-Load Transient Response
• Monitor Outputs
• Adapter Current (3% Accuracy)
• AC-Adapter Detection
• 11-Bit Battery Voltage Setting
• 6 Bit Charge Current/Adapter Current Setting
• 8A Maximum Battery Charger Current
• 11A Maximum Adapter Current
• +8V to +28V Adapter Voltage Range
20.2.1 The name and the pin definition of ISL88731

The ISL88731 is available in a small 5mm x 5mm 28 Ld Thin (0.8mm) QFN
package, is shown in figure 20-5.
Figure 20-5: Pin definition of ISL88731 (top view)
Functional Pin Description

BOOT = High-Side Power MOSFET Driver Power-Supply Connection.
Connect a 0.1µF capacitor from BOOT-to -PHASE.
UGATE = High-Side Power MOSFET Driver Output. Connect to the high-side
N-channel MOSFET gate.
LGATE = Low-Side Power MOSFET Driver Output. Connect to low-side N
channel MOSFET. LGATE drives between VDDP and PGND.
PHASE = High-Side Power MOSFET Driver Source Connection. Connect to
the source of the high-side N-Channel MOSFET.
CSOP = Charge Current-Sense Positive Input.
CSON = Charge Current-Sense Negative Input.
CSSP = Input Current-Sense Positive Input.
CSSN = Input Current-Sense Negative Input.
DCIN = Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to
GND.
ACIN = AC Adapter Detection Input. Connect to a resistor divider from the AC
adapter output.
ACOK = AC Detect Output. This open drain output is high impedance when
ACIN is greater than 3.2V. The ACOK output remains low when the ISL88731
is powered down. Connect a 10k pull-up resistor from ACOK to VDDSMB.
ICM = Input Current Monitor Output. ICM voltage equals 20 x (VCSSP -
VCSSN).
VREF = VREF is a reference output pin. It is internally compensated. Do not
connect a decoupling capacitor.
PGND = Power Ground. Connect PGND to the source of the low side
MOSFET.
VCC = Power input for internal analog circuits. Connect a 4.7 resistor from
VCC to VDDP and a 1µF ceramic capacitor from VCC to ground.
VDDP = Linear Regulator Output. VDDP is the output of the 5.2V linear
regulator supplied from DCIN. VDDP also directly supplies the LGATE driver
and the BOOT strap diode. Bypass with a 1µF ceramic capacitor from VDDP to
PGND.
ICOMP = Compensation Point for the charging current and adapter current
regulation Loop. Connect 0.01µF to GND. See “Charge Current Control Loop”
on page 18. for details of selecting the ICOMP capacitor.
VCOMP = Compensation Point for the voltage regulation loop. Connect 4.7k
in series with 0.01µF to GND. See “Voltage Control Loop” on page 19 for
details on selecting VCOMP components.
VFB = Feedback for the Battery Voltage.
VDDSMB = SMBus interface Supply Voltage Input. Bypass with a 0.1µF
capacitor to GND.
SDA = SMBus Data I/O. Open-drain Output. Connect an external pull-up
resistor according to SMBus specifications.
SCL = SMBus Clock Input. Connect an external pull-up resistor according to
SMBus specifications.
GND = Analog Ground. Connect directly to the backside paddle. Connect to
PGND close to the output capacitor.
Back Side Paddle = Connect the backside paddle to GND.

NC = No Connect. Pins 1, 5, 7 and 14 are not connected.
(Pins) ----------------- (Description)

1. the vacant pin
2. AC adapter detection input end. From the power adapter voltage dividing into
voltage through two resistances.
3. the reference voltage output, the standard value is 3.2V.
4. the charging current compensation point and the adapter current regulation
loop
5. the vacant pin
6. the compensation point voltage regulation loop
7. the vacant pin
8. inputs the current detection output, the voltage of ICM is equal to 20 times of
(VCSSPJVCSSN)
9. the system management bus
10. the system management bus
11. the system management bus module power supply
12. ground connection
13. the adapter detection output. When ACIN is higher than 3.2V.ACOK signal
open drain outputs the high level, needs for external pulling up.
14. the vacant pin
15. the battery voltage feedback
16. the vacant pin
17. the charging current detection negative input terminal
18. the charging current detection positive input terminal
19. ground connection
20. the G pole driver signal of the charging down tube
21. the linear voltage of 5.2V output
22. the main power supply input.
23. the phase pin, the top tube driving loop.
24. the G pole driver signal of the charging top tube.

25. boot-strap sends supplies power to the driver of the top tube.
26. internal artificial circuit power supply, through 4.7Ω resistance connects
VCC with VDDP.
27. the adapter current detection negative input.
28. the adapter current detection positive input.
20.2.2 The typical application diagram

The typical application of ISL88731 is shown in figure 20-6.
Figure 20-6: The typical application of ISL88731

In the figure 20-6, is the explanation of the working process of ISL88731:
(1) After the adapter switching in, and through the body diode sends to DCIN
pin, supplies main power to the chip; at the same time, through the resistance
dividing into voltage sends to ACIN pin.
(2) The chip internal linear regulator block outputs 5.2V linear voltage from the
chip VDDP and through the resistance supplies the main power supply to VCC.
(3) The chip internal produces the reference voltage with 3.2V.
(4) After ACIN being higher than 3.2V, the chip open drained outputs ACOK,
is pulled up to be high level by VCC.
(5) HOST (EC) through SCL, SDA communicate with the battery interface,
when the battery is low, EC through SDA, SCL transmits the charging voltage,
the charging current, the charging enable and other control instruction to
ISL88731.
(6) The chip starts to drive the charging top tube and down tube conducted in
turn, outputs the voltage to charge the battery.
(7) ISL88731 through VFB monitors the charging voltage, through CSOP and
CSON monitors the charging current.
(8) The chip through CSSP and CSSN monitors the current RSI flow that is the
adapter current. Enlarge the value of "CSSP-CSSN" 20 times through the chip
internal, and outputs from ICM to send to EC, informs EC the size of the
complete machine input current at present.
(9) According to the power dissipation of the total power of the adapter and the
system operation currently, EC adjusts the size of the charging current properly,
to prevent that the charging power is too high and exceeds the adapter output
limiting, then it will cause the adapter burning because of overload.
Chapter 21
Maintenance of Common
Failures
The failure of the laptop can be divided into the following categories:
(1) Short trouble, usually lead to the chip burning hot, burning, etc., it will
seriously damage the adapter.
(2) Not boot failure, also known as "no trigger" fault. It means that the laptop
cannot power up, that is, press the start button, the laptop has not any boot
phenomenon. For example, power light and hard drive indicator lamp does not
light, CPU pan does not turn, as did not press the start button.
(3) Power down faults, is generally divided into power down in the moment of
starting up, power down after starting up for a few seconds to tens of seconds,
power down irregularly during using .etc.
(4) No lights (no display) when starting up, also called "the black screen" fault.
It means that the display does not display after starting up. It can be subdivided
into does not run code fault, common code fault, screen display fault, etc.
(5) Interface fault: it refers to the fault of the sound card, the network card, USB,
the hard disk CD-ROM, the fan and other interfaces.
(6) Crash fault: it means that its usually crashing, blue screen and restarting
during using.
21.1: Short trouble (Short Circuit Problem)

The short trouble of the laptop usually can be divided into the short circuit of
the adapter input voltage, the short circuit of VTN main voltage, the short
circuit of the South Bridge and the North Bridge and the short circuit of other
voltage.
The short circuit of the motherboard voltage will cause a sharp increase in the
current, after the motherboard powering up, we generally use the DC regulated
power supply to observe the changes of the current and determine whether there
is a short circuit or not. In general, the standby current of the laptop
motherboard is 0.01A~ 0.06A, some motherboards are 0.09A, its not the fixed
standard. If connects the DC regulated power supply, the current is about 5A,it
use the power adapter, the LED indicator on the power adapter will flash, this
kind of phenomenon is generally the short circuit of the input voltage of the DC
regulated power supply. If connects the DC regulated power supply, the standby
current is increased, at this time, you need to measure some voltage points of
the motherboard, to determine whether the motherboard been triggered causes
the current increasing or not, it not, then is outage, use the universal meter to
measure the diode value of each voltage.
In actual maintenance, if we haven't the corresponding the laptop motherboard
drawing, it’s difficult to measure the short circuit of some voltages. We know
that the main voltage of the laptop is produced by the adapter being input, then
through the conversion of the PWM circuit. So, since it’s the PWM circuit to
supply power, it must have the inductance to store energy, so we can measure
the inductance on the laptop motherboard, to confirm that these important
voltage is short circuit or not.
Generally speaking, the diode value of these inductance to the ground should
not be less than 100,most of them should be more than 130.1.05V of the front
side bus power supply of the mother board is special, the value of resistance of
this voltage is relatively low in some motherboard, is only more than 20.And
the power supply of the independent graphics card, because of the special of
CPU chip, the value of resistance of this power supply is also low, is less than
10 for the below of G8* series, is even a few to 5 for the above of G9 series. It’s
worth nothing that the diode value of some voltage points to the ground on the
motherboard is very low, for example, on the Intel PM965, the impedance
between both ends of three capacitors is zero, which is normal. Some voltages
are even semi-short circuit, for example, the diode value of 500 to the ground is
short circuit to 200, in the actual repairing, like the voltage short circuit to the
half, it’s difficult to determine whether its short circuit or not, sometimes we
need to rely on actual maintenance experience and compare with the good board
to judge.
Detect that one voltage is short circuit, should disconnect the production circuit
and the load circuit of the voltage first, and then determine which part caused
the short circuit.
But how to disconnect it? In general, if the power supply method is PWM, there
have the design of the isolation point on the laptop motherboard. The isolation
point, which is in the process of production of the motherboard, design an
artificial open circuit on the circuit of the some voltage, and this open circuit is
connected by tin in normal circumstances. This open circuit is usually back of
the power supply inductance, if we found that some voltage is short circuit, we
can use the solder wick to remove the tin on the corresponding isolation point,
thus, renewing the open circuit state, and then artificially disconnect the load
circuit and power supply circuit.
If there is not the design of isolation point on the repaired motherboard, then we
should disconnect the inductance of PWM circuit, use the soldering iron to lever
the side of the inductance. Also can realize the open circuit, but we should note
that when we disconnect it, don’t lever the inductance too high, if make it too
high, it will damage the inductance.
Some voltages convert to be each voltage required by the motherboard through

the conversion of MOS tube. If there is not the corresponding circuit diagram,
it’s difficult to determine that some voltages (as the voltage converted through
MOS tube) are short circuit or not, only by the method of running the line to
judge usually.
Next, we take the short circuit of 3V voltage of DV1000 motherboard an
example, to state the maintenance method of short circuit of the laptop
motherboard.
(1) For the short circuit of the laptop motherboard, we need to determine that
it’s the production end of the internal circuit being short circuit or the external
load end being short circuit. The production of 3V voltage of DV1000 is got
from the standby voltage 3VCPU converting through PQ143, the G pole of
PQ143 is controlled by MAIND signal, is shown in figure 21-1.
(2) In the actual measurement, the diode value of 3V voltage point is 3, is
obviously short circuit.
(3) Cock the first pin of PQ143, determine +3Vvoltage that it’s the internal
production voltage end being short circuit or the load end being short circuits
Figure 21-1: The production circuit of DV1000 3V voltage
Figure 21-2: Disconnect the connection of internal voltage production end and
external load end
(4) By the actual measurement, the external load end of this board 3V voltage is
short circuit, the impedance of the internal production voltage end is normal.
(5) Check the circuit diagram, skim the place where +3V load end used first.
(6) The method of excluding the short circuit is below:
(a) Method 1:
Exclude the short circuit one by one (elapsed time, safety). Like the desktop
motherboard, there are a lot of places to use +3 V in the laptop, and we start to
remove from the most possible places. This method is relatively elapsed time,
but it’s the most secure. Of course, +3V is short circuit; we usually remove the
South bridge first. The South bridge uses +3V at most.
(b) Method 2:
Power up (relatively adventure and be used with CAUTION). Connects two
wires from the DC power adapter, and adjust the appropriate voltage, one end is
grounded, and one end is connected with the voltage point of the short circuit.
In principle, the selection range of the voltage and current is the smaller the
better, mainly to avoid burning plate, sometimes, the short circuit is repaired,
but the motherboard does not start up. The DC regulated power supply adjusts
the appropriate voltage and current, is shown in figure 21-3.
Figure 21-3: The DC Regulated Power Supply adjust the appropriate voltage
and current
After the motherboard powering up, because the current of the short circuit is
large, the next action should be fast. Felt the motherboard rapidly to check if
there is the special hot component, in general, the component with short circuit
will be burning hot after powering up, after removing the hot components, Use
the universal meter to measure the diode value of the short circuit point again. It
may burn out the motherboard in this method, so please use with caution.
(c) Method 3: electric shock
This method is similar to the method 2. But about this method, adjust the
voltage and the current of the DC regulated power supply at the same time, one
of the wire connected to the ground, and one end connected to the short circuit,
with a strong voltage and strong current to breakdown the short circuit point.
Because the voltage and the current are high, it has a great influence to
components on the motherboard, so it’s usually not used.
3V of this board is short circuit, after powering up by the second method, touch
the South Bridge and the South Bridge is very hot. After removing the South
Bridge, measure that the impedance of 3V measurement point has been normal.
After changing the South Bridge, this board is repaired.
21.2: Do Not Trigger Fault

In this section, takes DV1000 as an example to introduce the basic maintenance
thought and the maintenance process of the not trigger fault.
(1) Get the motherboard, we should do a simple appearance inspection first,

then check the value of a few large inductance of the motherboard, judge that if
it’s obvious short circuit.
(2) Plug in the regulated power supply to observe the standby current, in general,
the normal standby current is 0.01~ 0.03 A, no standby current is usually VIN
voltage 19V without output or the standby circuit fault. If the standby current is
too large, then the part of load is short circuit fault. If there is a short circuit,
refer to arrange distinguish method of the short circuit fault in the 21.1 section
to service. The voltage of DV1000 are VIN input voltage, +3VPCU, +5VPCU,
3V_S5, 5V_S5, 1.5V_S5, 3VSUS, 5VSUS, 2.5VSUS, +3V, +5V, +2.5V, +1.5
V, VCCP (1.05V), SMDDR-VREF, SMDDR-VTERM, VCORE.
(3) As shown in figure 21-4, checks VIN voltage whether there is a 19V voltage
or not, if there is no VIN voltage, checks the isolation protection circuit.
Figure 21-4: DV1000 isolation protection circuit

(4) After VIN power supply 19V being normal, measure that the standby
voltage 3VPCU and 5VPCU are normal or not, if there is no standby voltage,
checks the standby voltage circuit. The real object of the standby circuit is
(5) If the standby voltage 3VPCU and 5VPCU are normal, measures that if
there is 3V high level on the power button NBSWON# signal pin, and if its low
level when press the switch. The measurement point of the power button is
Figure 21-5: The real object of the standby voltage circuit
Figure 21-6: The real object of the power button of DV1000
(6) Measure that if the crystal Y8 of the South bridge crystal Y10 and EC
PC97551 starts oscillation(shown in figure 21-7), and if the waveform of the
oscillation starting is normal, if the frequency is 32.768kHz.
(7) Measure that if the chip selection waveform of the chip selection CS# end of
the 30 pin of BIOS is normal, and if the waveform of the data address wire is
normal. If EC can't read the data in the BIOS, or reads data error, it will also
cause that EC is not working properly. Lead to not trigger. If the measurement
is not normal, checks the working condition of the BIOS and X-BUS circuit of
EC communication brushes the BIOS procedure.
(8) Measure if there is low level to high level after the DNBSWON# signal of
EC PC97551 pressing the switch.
(9) Measure that if the RSMRST# signal (shown in figure 21-9) sent by EC PC97551
to the South bridge is normal, If it’s not normal, checks EC PC97551 and the relative
circuit of the South bridge.
Figure 21-7: Measure the crystal waveform of EC PC97551
Figure 21-8: Measure the selection waveform of CS# on BIOS
Figure 21-9: RSMRST# signal of DV1000

We also need to check INTVRMEN and BATLOW# and other signals. We can
refer to the drawing to find out the measurement point of the signal to determine
that if there are normal.
During servicing, we need to combine the specific circuit according to the

power on sequence of DV1000, to analyze flexibility, can not apply
mechanically, or you will fall into the confusion of the maintenance.
21.3: Power Down Fault

In general, the system power off and close down automatically, and other
related bad phenomenon, which are collectively known as the failure of power
down, which is divided into shut down automatically in the adapter state, shut
down automatically in the battery state, shut down automatically during
operating, shut down automatically when puts the hard disk drive, etc.
Power down faults is subdivided into the following categories:
(1) Power down at any time
The voltage value of RTCRST# is low, which will cause power down at any
time.
The temperature control circuit detects the power down at any time caused by
the over- temperature protection (CPU or graphics card cooling fin is not
installed good or the air outlet is blocking) and the self-trouble of the
temperature control circuit, the fault point is usually on the temperature control
circuit of CPU core voltage power supply MOS tube of CPU temperature, the
motherboard temperature control, the graphics card temperature control and
certain plate cut.
For example, the line fault between MBATV of Quanta motherboard battery to
EC, prevents EC from sampling the battery voltage, will also power down at
any time during the battery discharging.
(2) The instant power down
Because some important voltages on the motherboard can't produce, it causes

the under- voltage protection, which causes the instant power down. The fault
usually shows as power off once power-on, can't use the universal meter to
measure the relative voltage, the working voltage of the South Bridge, the North
Bridge and CPU usually appeared.
For example, the under-voltage protection signal HWPG in the Quanta

motherboard, in the process of the trigger power on, if EC detects that HWPG
signal can't be produced, then will close instantly the sending of all voltage
opening signals, which causes the instant power down.
For example, FORCE_OFF# (the temperature control and the under-voltage) of
ASUS, PWRSHUTDOWN# (the temperature control and the under-voltage)
and THERM_STP# (the temperature control and the under-voltage) have the
same meaning with HWPG, they can be used for under-voltage detection.
For example, EMC4000, EMC4001, EMC2102 of DELL and other temperature
control circuit external of the temperature sensing diode is broken, which can
also cause the motherboard power down when starting up or power down after
starting up and displayed.
There is a short circuit caused by the instant power down, for example, in the
Quanta motherboard,3VPCU voltage converted to be 3VSUS voltage and 3V
voltage after powering on, if the secondary voltage(such as 3V voltage) is short
circuit to the ground, then when power on triggered,3VPCU will cause the short
circuit. Once MAX8734A and other standby power chips detect that there is the
short circuit in the final stages, then entered the output discharging mode, closed
the output of 3VPCU and 5VPCU voltage, causing the motherboard power
down.
(3) The instant power down caused by being not detect CPU
In the IBM laptop, using MAX1989, MAX6689 and other temperature control
chips, which external thermal diode can't be open circuit(for example, when
CPU is not installed),or the temperature control chip will be thought too warm,
directly caused that connects low PWRSHUTDOWN# when power on, and
power down instantly.
(4) 4s power down
Being equipped with the working condition of CPU, but it cannot work
normally, the chipset automatic protection causes power down, and the fault
usually shows as 00 or FF power down.
This kind of fault is usually caused by the bus abnormity between CPU and
GMCH, GMCH and ICH, ICH and BIOS, about the maintenance method,
please refer to the maintenance method of not running code. In addition, after
triggering, the boot pin voltage is pulled low, which also lead to 4s power down,
please note the measurement of the boot pin voltage.
(5) Power down caused by THERMTRIP#: power down when enter the
system.
THERMTRIP# is the over-temperature indicator signal sent by CPU and
GMCH to ICH, after ICH receiving THERMTRIP# effective signal, closes all
voltage on the motherboard within 0.5s.So,when CPU or GMCH is over-

temperature, can inform ICH to power down instantly, and achieve the chipset
protection. Power down when enter the system, which is usually caused by
THERMTRIP# signal open circuit sent by CPU or GMCH to ICH.
(6) Power down at any time caused by the smoothing of CPU power supply
voltage being bad
This kind of fault is mostly caused by CPU filter capacitor being bad, we can
observe the frittering effect of CPU voltage through the oscilloscope. This fault
is usually appeared on the Toshiba M200.
(7) The carrying load ability of 3V and 5V standby voltage is not enough (such
as bad smoothing and poor chip performance), which causes power down.
The typical fault is that electric power down caused by poor performance of
common VCC3M and VCC5M standby chip of IBM laptop and bad filter
capacitor. The elimination method is to replace the chip, and change the filter
capacitor.
(8) Power down when using the battery discharging
Figure 21-10: SLP_S3# and temperature signal ALERT#
The battery powers off automatically after starting up, we should focus on the
measurement of BATT_SENSE, BATT_IN# and other signals, this kind of
signal tells to EC that the battery has been plugged at this time, if the system
can't identify the battery normally, then it will power down automatically.
The power down fault is more complex, if we can combine the oscilloscope to
test, there will be a better effect, In the figure 21-10, the oscilloscope contrasts
SLP_S3# and the temperature signal ALERT#, observe that which signal goes
wrong to cause power down.
21.4: Not Running Fault (No Error Code)

The maintenance procedure of not running fault is as follows.
1) When we get the bad motherboard, please do not eager to power on. We
should observe carefully first, if possible, compares with the normal
motherboard, observe the welding and the puts of components on the board
(especially with multiple parts, wrong parts, missing part and tin solder short to
other part/point).Some motherboards are just parts of counter, tin solder short to
other part/point or done the BGA on board before, because the maintenance
staff is eager to success, powers on once get the bad motherboard, which lead to
the damage of the components, then it will spend many times and energy to
repair. If you have a habit of self-detection, then you can greatly improve the
efficiency of maintenance.
2) If there is no CPURST#, please repair according to the timing sequence.
3) CPU is normal, and receives CPURST#, the diagnosis card also displays
FF(00), then there may be problems with the peripheral circuit of CPU or the
North bridge, such as REF, TEST, COMP, CFG and so on(is the peripheral
precision resistance of CPU and the bridge), is shown in figure 21-11 and figure
21-12.
Figure 21-11: GTLREF and COMP signal of CPU
Figure 21-12: The reference voltage of the North Bridge

4) Whether it’s Intel or AMD, the front side bus (FSB) without open circuit and
short circuit are the necessary conditions for the system going code. Here you
can use a dummy load with light (shown in figure 21-14) to measure, and can
also use the dummy load to hit the value of resistance. If some lights don't light
on the dummy load with light it means that there is open circuit to the North
bridge (Intel control line connects the South bridge), if some lights are brighter
than other lights, it means that the data line is short circuit. If you are not sure,
you can verify it again with a universal meter. (Note: the lamp holder is only
suitable for Intel and nVIDIA chipset, the half of the lamps is quite lights and
another half are dark of nVIDIA chipset. The AMD chipset, there only the half
of lamps are lights. Advice you can use the dummy load hit the diode value, a
group is more than 200 and another group is more than 700).
Note: Be careful circuit-hole is broken. The figure 21-14 is a schematic diagram

of the routing.
Figure 21-13: Use the test bench with the light (LED light) to test FSB
Figure 21-14: The schematic diagram of the circuit-hole routing
(5) In addition to the detection of data address line, but also need to measure
that the clock and PG is normal or not, the measurement point can be on the
dummy load (shown in figure 21-15).
(6) When the diagnosis card runs "00" and CPURST# has been normal, we
consider first whether there is a problem with BIOS. Because it’s a firmware,
between the software and hardware, it’s easy to cause that the running code
displays "00".
(7) After excluding that BIOS data is bad, then confirms whether the working
bus of BIOS is normal or not, there are SPI bus, LPC bus, the high address line
of X-BUS and others. The important pin is shown in the 7.2 section.
(8) After confirming that there is no problem, then further analyzes whether the
working voltage of KBC, LPC bus and PCICLK_KBC (33M) works normally
or not. If there is no exception, then replaces EC.LPC bus pin of EC is shown in
figure 21-16.
Figure 21-15: The real object of the dummy load
Figure 21-16: LPC bus of EC
(9) After confirming that EC is normal, continue to analyze DMI bus, is shown
in figure 21-17.
Figure 21-17: The real object of DMI bus

(10) If there is no abnormality of the line resistance, then need to test whether
the working voltage and the clock of the South and North Bridge are normal or
not, if the conditions are met, then replace the South Bridge first.
(11) Replace the North bridge and CPU base at last (note: when you replaces
BAG, cannot be isolated to analyze some simple conditions to make the
decision to replace the BGA, you should comprehensively analyze the South
bridge, the North bridge, the bus of CPU and all working conditions, then
determine to replace)
The figure 21-18 is the diagram of the process of the trouble shooting (AC
mode):
Figure 21-18: The process of the troubleshooting
If you have an oscilloscope, you can analyze the process of running code by
the oscilloscope. Here are some test points of the Intel double bridge platform.
(1) ADS#: after CPU receiving H_RESET# signal sent by the South bridge and
being reset, the address strobe signal will send H_ADS# signal according the
internal default first, then start from the North bridge to the starting module of
BIOS to read the first instruction executed according to the default address
(0FFFFFFF0H), and then execute the starting module, after the starting module
executing, it will jump to POST code to start to execute POST instruction. So,
when ADS# is triggered, it’s shown that CPU has started to work.
Figure 21-19 is the screenshot of the ADS# signal single trigger
2) DMI bus(DMI_RXN0,DMI_TXN0),DMI bus is the main bus used by the

South bridge and the North bridge for communicating, mainly measure
DMI_RXN0 and DMI)TXN0 signals, can be simply knowing whether DMI bus
is transmitting data or not. So, confirm whether this signal is working or not,
which can be preliminary judgment whether the North bridge is communicating
with the South bridge or not.
The figure 21-20 is the screenshot of the comparison between DMI_TXN,
DMI_RXN waveform and H_CPURST# waveform, its H_CPURST# who
increased in the high level first.
3) PCI_FRAME#: PCI frame period signal. When PCI frame period signal
actions, it means that PCI bus is transmitting data. So, only confirm that
PCI_FRAME# is working, and then you can be preliminary judgment that PCI
bus is well. The figure 21-21 is the screenshot of PCI frame period waveform.
Figure 21-19: The screenshot of ADS# single trigger
Figure 21-20: The screenshot of DMI bus waveform
(4) LPC_FRAME#: LPC bus frame period signal LPC bus is the main bus used
for the communication of the South bridge and EC, just measured that if
LPC_FRAME# works normally or not, then can preliminarily judge that if the
South bridge communicates with EC or not. The figure 21-22 is the screenshot
of the waveform of LPC frame period.
Figure 21-21: The screenshot of PCI frame period waveform
Figure 21-22: The screenshot of LPC frame period waveform
(5) The data address line of BIOS can measure LAD0-LAD3 pin and
LFRAME# pin for the BIOS chip of LPC bus.
For the BIOS chip of X-BUS, it can measure the high address line. Only in the
process of power on self-detecting, then the high address line will transmit data,
so the waveform can be measured here to determine whether there is power on
self-detection data transmission between BIOS and EC.
For the BIOS chip of SPI, only under the South bridge, can be measured
whether 1,2,5,6 pin are running code or not.
21.5: The Maintenance of Common Code

POST (Power on Self-Test) is the routine that the system carries out self-test
after the computer powering on/test almost all devices of the system, each
device has a corresponding detection code.
Figure 21-23: Diagnosis card show POST error code “E0 28”
In order to let the designers and the repairer to know what actions BIOS doing
at present, when BIOS detects a device, writes the corresponding code to the
80H diagnostic port first, when the device is detected, then sent the code of
another device, and detects another device. If a device does not pass the test,
then this code will be retained in the 80H, the detection process will be
suspended, and according to the upset alarm sound to give an alarm. We call
this code as Post Code. We can use the diagnostics card to read the code of 80H
diagnostic port through ISA, PCI, LPC and SPI bus, then displays on the LED
light, which is convenient to test and diagnose the motherboard for us.
BIOS code is divided into three major brands are respectively AMI (beginning
with ‘D’), Award (beginning with ‘C’) and Phoenix. The laptop commonly uses
Phoenix.
0A , 28 , 2C , 2E , 38 , E0
0A, 28, 2C, 2E, 38, E0 code are related to the North Bridge, the memory, the
clock generator, EC and BIOS. First, observe whether the memory is plugged
well or not, plugging a few times(used possible combinations),then observe if
the code changes, if it changes, BIOS procedure may be damaged, try to flash
the BIOS; then observe if the memory interface is bad(a lead measurement) and
the welding of the pin; and observe the pull-up tension between the memory and
the North bridge(measure one by one),replace the wrong resistance; also
observe some groups of voltage supplied to the memory interface, which group
is not exist, then to check the corresponding power circuit; at last, measure the
clock of the memory and SDATA/SCLK on SMBus, observe if there are actions,
if not, then try to change the North bridge and the clock generator. if the above
circumstances are excluded, then try to replace the North bridge or EC.
Sometimes, it may run 38 when BIOS program is lost, refresh again or replace a
new BIOS.
49
49 code is related to the South bridge and each PCI device. First, measure
PCIRST#, if it’s not exist, then according to the previous method to find out that
if the South bridge didn't send PCIRST# or its pulled off by a PCI device; then
observe the voltage, the clock, SMDATA/SMCLK and the welding of each PCI
interface/controller; and observe the corresponding E2PROM of PCI device; if
all of the above are normal, then EC and BIOS are suspected.
85 and 87
85 and 87 code are the common code of IBM type, refers to the power on self
test stops in the detection of security chip. The solution is to replace a pair of
security chips and BIOS, or brush the so-called free security chip BIOS.
55
55 code is usually caused by USB fault. Measure 5V power supply impedance
of USB, to determine whether there is a short circuit or not; then measure 5V
voltage, to confirm that 5V voltage is normal; measure USB to the South bridge
signal and OC# over-current protection signal .Except the South bridge
itself,48MHz clock and USB controller power supply of the South bridge need
to be attention.
22
22 code means that the keyboard controller did not pass the test. It is usually a
problem of EC.
4A , DA
4A and DA code means that the graphics card did not pass the test. For the
power supply, contrast the drawing to test one by one; for the clock, there are
27MHz core clock and 100MHz bus clock; for the reset, is PCI-E bus reset; for
the bus, that is PCI-E bus of the graphics card. Both ends of the coupling
capacitor are required to play a value, and to determine that the coupling
capacitor is not bad.
Phoenix BIOS4.0 code is shown in table 21-1, for your reference. For more
POST code, you can consult BIOS CODE of each manufacturer.
Table 21-1: Phoenix BIOS 4.0 Codes
21.6: The Screen Shows Fault

The screen shows fault is divided into parts of the graphics card fault and partial
fault of the interface. If it’s a partial fault of the graphics card, we cannot catch
the EDID waveform usually (the waveform diagram is shown in figure 8-7).For
such problems, we need to detect the working condition of the graphics card
chip. The graphics card fault is usually available in the majority of missing
solder; in general, we can solve the problem by welding, replanting the chip or
changing the graphics card chip.
If the part of the graphics card is normal, there is a continuous waveform on the
any one of LVDS, the measurement point is on the LVDS socket pin, need to
connect up the screen line to be measured. The real object of LVDS socket is
shown in figure 21- 24, LVDS waveform is shown in figure 21-25.
Figure 21-24: The real object of LVDS socket
Figure 21-25: LVDS waveform
The laptop can support multiple display output, except the common LVDS and
CRT output, many models also support S terminal. DVI.HFMI and other output
methods. But the focus of the maintenance is still on the LVDS output and CRT
output.
The problem of LVDS output are mainly the backlight and display. Some
machines screen interface also includes the display and backlight, and other
machines may have two interfaces, the display and backlight are separated.
In the figure 21-26, VADJ, VIN, BLON been circled are the signal belonged to
the backlight part.
VADJ is the intensity control signal, is sent by EC.VADJ is a linear voltage,
when we press the shortcut key of the intensity control on the keyboard, this
signal changes in a certain range.
VIN is the high board power supply. The 19V adapter voltage is used here;
some of the early machines use 5V power supply.
BLON is the opening signal of the backlight; this signal is controlled by EC. If
it’s a independent graphics model, this signal is usually not managed by EC, but
is managed by the graphics card.
Figure 21-26: LVDS interface signal
+3V of the 28 pin is the power supply of EDID chip, it’s a ROM with storing
the screen parameter. Most of machines will detect EDID. If the screen is not
detected, they will refuse to turn on the backlight and the screen power supply.
DELL and other machines will detect the model of the screen and other
parameters in EDID. If the parameter is incorrect, they also will refuse output
from LVDS. If changes the screen of this type of model, we need to replace the
chip of the original screen to the new screen.
LCDVCC of the 27 and 26 pin is the screen power supply. The production
circuit of the screen power supply is usually shown in figure 21 -27.
Figure 21-27: The production circuit of the screen power supply

In the figure 21-27, is the principle of the production circuit of the screen power
supply: when the graphics card completed self detection, and read the
information of the screen, then sent the high level of DISP_ON to control Q19
conducted and pull the G pole of Q18 low, Q18 is P-channel, when the G pole is
low level, +3V converted to be LCDVCC output.
25 and 24 pin are the data lines of EDID ROM, in fact, it’s a pair of SMBUS, is
used to read the chip of the screen.
RF_LED# of the 21 pin is the indicator light of the WIFI. The status indicator
lamp of many laptops are built-in the inverter board, such as wireless indicator,
power status indicator and others.
LCDID of 18, 17 and 16 pin is the screen line identification signal.
11, 10, 8, 7, 5, 4, 2 and 1 pin are LVDS bus, is ordinary resolution ratio. If it’s
high definition panel/screen, in general, it needs two groups of such signals.
The figure 21-28 is the screenshot of the CRT interface circuit, the key test
point of CRT output is in the line (13 pin), field (14 pin), after line and field
signal being output from the graphics card (the North bridge), they will reach to
the CRT interface by buffering. By measuring the waveform of 2 pin and 4 pin
of the buffer U1 and U2, we can easily identify the area where the problem is.
Figure 21-28: The screenshot of CRT interface circuit

If R (l pin), G (2 pin) and B (3 pin) have the problem, it will only cause that the
color is abnormal, and will not result in no output.
Note that some modes do not support starting up from CRT, only after entering
the system and graphics driver completing load, then switched to CRT output.
Figure 21-29: The real object of LED and LCD screen

If it’s the dark screen fault, we need to service the circuit of the backlight
usually. If the opening and the power supply of the backlight are normal, but it’s
also the dark screen, we need to test if the inverter module or the backlight is
wrong. Now the mainstream is divided into LCD(Liquid Crystal Display) and
LED(Light Emitting Diode),it's easy to distinguish between them, as shown in
figure 21-29,the below piece of screen with a high voltage line is LCD screen,
the above screen without the high voltage line is LED screen, LED screen is not
need the hard board.
Next, we introduce the transformation of the common inverter module of LCD
screen.
The inverter module (LCD screen called inverter board, LED screen called LED
driver board) can be called as the hard board. The hard board we used
commonly is divided into 5V (shown in figure 21-30) and 9-20V (shown in
figure 21-31). 5V is used in the old machine, has not been used much. The 9V-
20V (or latest one is 5V ~ 28V!) is used commonly, we don't consider the
withstand voltage, only need to connect the four lines, if customers'
requirements are not strict, then just need to connect three lines.
Figure 21-30: 5V general inverter module (universal inverter board)
Figure 21-31: 5V~ 28Vgeneral inverter module (universal inverter board)
Modify the original inverter board to universal inverter board. Important pins of
inverter board:
(1) VIN = The power supply of inverter board (hard board)
(2) GND = Ground
(3) ON = The opening signal. The name is different on the different board, we
don't have to tangle in the name, and we just need to find this opening signal in
these wires. But we cannot think that the wire with 3.3V is the opening signal,
because there is 3.3V of some indicator lights on the hard board, if we use these
3.3V,it will be out of sync with the time of the screen lighting, which resulting
in white screen. We need to find the signal who can arrive at the same time with
the screen, in general, there have the synchronous 3.3V in these wires sent by
the motherboard to the hard board, if you cannot find it, you also can fly a piece
of line from the screen power supply 3.3V. Figure 21-32 the real object of the
screen interface. In general, we find 3.3V on the screen, are connected to fuse,
and then connected to an inductive filter. The most important is that it can be
measured after starting up. The real object of the screen interface is shown in
figure 21-32, F101 is a fuse, and L101 is an inductance.
(4) ADJ = the intensity control. In general, there have the intensity control wire
in these wires, you can adjust the brightness in the system, and the voltage will
change with the brightness adjustment.
Figure 21-32: The real object of the screen interface
21.7: The Sound Card Fault

The sound card fault is usually divided into the loudspeaker or the earphone
without sound, and the loudspeaker and the earphone are not sound.
The loudspeaker or the earphone has no sound, there may be a problem of the
transformational component of the earphone jack, or is the problem of the
power amplifier, because the earphone jack of some models is independent of
the power amplifier.
Take the Quanta JM7 as an example; observe that how the earphone and the
loudspeaker convert to the sound.
The 4 pin HP_NB_SENSE of CON4 detects if the earphone is plugged or not,

its connecting the ground when the earphone is not plug, after plugging, the 4
pin and the ground are disconnecting ,is shown in figure 21-33.The real object
of the earphone interface is shown in figure 21-34 and figure 21-35.
Figure 21-33: The earphone interface circuit of JM7
Figure 21-34: The earphone is not plug in
Figure 21-35: The earphone is plugged-in

After plugging the earphone, the high level of HP_NB_SENSE is sent to EC, is
Figure 21-36: EC received the signal of the earphone plugging

HP_NB_SENSE conducts Q39,connects R246 to the ground, makes
AUD_SENSE_A been pulled up by +VDDA to turn into the partial pressure, is
shown in figure 21- 37.After the sound card chip detecting AUD__SENSE_A
voltage changing, changes the original loudspeaker output to the earphone
output.
Figure 21-37: AUD_SENSE_A circuit
HP_NB_SENSE is also sent to the 23 pin of the power amplifier chip, is shown
in figure 21-38.
Figure 21-38: The power amplifier chip
After the power amplifier U20 receiving HP_NB_SENSE, then disconnects the
left and right channels of the loudspeaker of the 6, 7, 19 and 20 pin, and outputs
the earphone signal of AUD_HP_JACK_L and AUD_HP_JACK_R of the 15
and 16 pin.
The loudspeaker and the earphone are completely silent, in general, there is the
problem of the sound card itself, we need to check the power supply of the
sound card chip, ACLINK connected by the sound card and the South bridge
and others, is shown in figure 21-39.
Figure 21-39: The diagram of the sound card circuit

In the figure 21-39, the power supply of the U19 sound card is 3.3VRUN and
VDDA, if there are normal, we can test the DOCK_HP_MVIUTE# mute pin of
the 31 pin, then we can test the over the ground resistance of the 5, 6, 8, 10 and
11 pin of AC97 bus, testing if there are the short circuit, the open circuit and
other faults to the South bridge.
Tip: if the machine does not sound, we should determine if there is the problem of the
loudspeaker or the power amplifier does not sound out. First, try to use the earphone,
if there is sound, maybe it’s the problem of the socket, we can use the oscilloscope to
test according to the drawings. If the sound card and the power amplifier are normal,
and there are waveform, but there is no sound, we can connect a loudspeaker between
the output 6 pin and 7 pin or 19 pin and 20 pin of the power amplifier, if there is a
sound, is the contact problem of the loudspeaker or the socket; if there is no sound, we
should test the power supply, enabling and the mute of the power amplifier, if there
are normative it’s the problem of the sound card itself. Next, we also check from the
power supply, the clock, the reset, enabling, the mute and other aspects.
21.8: USB Fault

If it’s a single USB interface who cannot be used, mainly check the appearance
and the power supply of this interface, and check if there is open circuit
between the interface and the South bridge and others; if all interfaces are not
used, in general, we need to check the over the ground resistance of the data line
between the power supply VCCUSBPLL of the South bridge, the clock CLK48,
the South bridge and the port, and check the power supply sent to USB port the
precision resistance of the South bridge USB module, is shown in figure 21-40.
Figure 21-40: USB circuit of the South Bridge
21.9: The Network Card Fault

The network card is wrong, which will cause that the network card can't be
detected. If it’s the network card of PCI-E bus, rarely cause the network card
can't be detected because of the wrong South bridge; if it’s the soft network card
or PCI bus network card, which is likely to cause that the network can't be
detected because of the wrong South bridge. The soft network card linked to the
South bridge directly, about the soft network card fault, we need to test the
network card control module in the South bridge. The network card of PCI-E
and PCI bus is the hard network card. In this section, take the Compal LA-
5891P as an example, mainly introduces the way of troubleshooting of the hard
network card fault.
(1) First, ensure that the basic working condition of the network card is normal,
including the power supply +3V_LAN, +1.2V_LAN of the network card, the
PCI-E bus clock CLK_PCIE_LAN of the network card, CLK_PCIE_LAN#, the
reset PIT_RST# of the network card, PCI-E bus PCIE_DTX_C_PRX_P1/N1 of
the network card, PCIE_PTX_C_DRX_P1/N1 (there are the coupling capacitor
in the middle of PCI-E bus, during maintenance measurement, should test the
over the ground resistance of both ends, any end is open circuit, which will
cause that the network card can't be detected), is shown in figure 21-41.
Figure 21-41: The screenshot of the basic working condition of the network
card
(2) The crystal 25MHz of the network card, is shown in figure 21-42.
Figure 21-42: 25MHz crystal of the network card
(3) Can identify the network card but cannot be used, display "is assigning IP
address”, but has been not assigned the fault of IP address. In general, check the
working condition of MAC address chip: the power supply, SCK clock and
SDA data.MAC address chip is wrong: one is that MAC address chip is burned
out, another is that the internal data of MAC address chip is damaged, because
the physical address of the network card is stored in the MAC address chip, we
need use the special tool to write MAC address. FF-FF-FF- FF-FF-FF and 11-
22-33-44-55-66 are the invalid address.
As shown in figure 21-43, MAC address is set to be stored in the network card
chip, U12 does not install the component in kind.
Figure 21-43: MAC chip of the network card

Tip: MAC address of the soft network card is stored in BIOS. If there is a
problem of the soft network card, we mainly check the power supply, the clock,
the reset, the signal line, and the bus of the South bridge network card module.
Identify the network card but it has been shown that the cable is not plugged in
the kind of red "X", need to check the over the ground resistance of the 8 pieces
of cable signal, the external precision resistance and others. The network bridge
(also called as data pump and network isolation transformer) is wrong, in
general, we can put the corresponding signal pulling directly to use temporarily.
The network bridge is the coil, some signal in the network bridge is
disconnected, which will directly cause that the network card with Gigabit
changed to be the network card with 100 M bit can't be used. The network
bridge and the interface circuit are shown in figure 21-44.
Figure 21-44: The network bridge and the interface circuit
Test if the network card is wrong or not, we can test directly the value of the
main power supply or the value of the 8 pieces of cable signals. In general, after
the lightning stroke, the network card power supply to the ground will directly
short circuit.8 pieces signals external precision resistance, the value of the diode
of 8 pieces of lines to the ground is normal, and then check the network bridge.
21.10: SATA Interface Fault

In this section, take LA-6631P as an example to explain the maintenance of the
SATA interface fault.
After testing that the hard CD-ROM is bad, then check the power supply of
SATA interface first, is shown in figure 21-45.
Figure 21-45: The power supply of the SATA interface

Then check 1.5V power supply VCCSATAPLL of SATA module in the South
Bridge, is shown in figure 21-46.
Figure 21-46: The power supply of SATA module
We also need to check 100MHz clock SATA_CLKN of the South bridge SATA
module and SATA_CLKP. At last, check the data line of SATA interface, the
precision resistance of SATA module and others. The data transmission of
SATA is divided into two transmissions and two receptions, there are four
signals in total. When measure the diode value, should measure one end of the
South Bridge, because the coupling capacitor is connected in the middle, there
is no use in testing the hard disk or one end of the CD- ROM, is shown in figure
21-47.
Figure 21-47: The data line of the clock, the biasing resistor, the interface of the
SATA module
All of the above are normal, in general, we can consider to replace the South
bridge. Crashing once plugged the hard disk, and displays LOGO graphics, then
the South Bridge is usually bad. About other modules of the South bridge, for
example, the sound card module will cause crashing, and displays LOGO.
21.11: The Fan Interface Fault

CPU fan of the laptop is usually divided into three pins and four pins. The fan
with three pins is shown in figure 21-48, the 1 pin supplies power, the 2 pin is
speed detection, and the 3 pin connects the ground. The specific working
process: after EC detecting the appropriate temperature it will send the
appropriate EN_DFAN1 signal to U5,according to the voltage level of VSET
pin,U5 decides the high-low of +VCC_FAN1,in order to control the rotate
speed of the fan. The rotate speed of the fan is sent to EC through
FAN_SPEED1, detects the rotate speed of the fan at real time.
The control circuit of the fan with four pins is shown in figure 21-49, in the
figure, U31 is the temperature control chip, after the temperature control chip
detecting the temperature through DPI and DN1, according to the high-low of
the temperature, it will control the duty cycle of the waveform of PWM pin.
This square signal is sent to the internal circuit of the fan, is used to control the
rotate speed. FAN_TACH is the speed detection pin.
Figure 21-48: The control circuit of the fan with three pins
Figure 21-49: The control circuit of the fan with four pins
21.12: Crash Fault

(1) Excluding the fault of CPU, the memory, the hard disk, the system and
others (this kind of fault is more).
(2) BIOS sets the initialization (for example, SATA of some machines is set to
be AHCI mode, which will cause the blue screen), CMOS is discharging,
upgrades BIOS.
(3) Measure that if all voltages are normal or not, and if it exists low voltage,
unstable, bad smoothing and other phenomenon’s. If 1.5V voltage supply is just
drop to 1.2V after entering the system, which will cause the laptop/machine
crashing and the blue screen.
(4) The South bridge and the peripheral. The South bridge mainly manages the
peripheral, when the South bridge is broken down, it will cause crashing and the
blue screen. In addition, the peripheral also will affect this fault. In general,
during the maintenance, we can enter into the safe mode, without loading any
driving, observes whether it is the blue screen of death. It’s normal under the
safe mode, in general, the problem is in the South bridge, the sound card, the
network card, the card reader chip, 1394 chip and others, we can remove one by
one to find the faulted peripheral. The North bridge.
(5)The North bridge communicates directly with CPU and the South bridge. If
there is a problem of the signal, then it will cause the blue screen of death, and
cannot enter the system. For example, there is a problem of H-DPSLP# signal,
which cause the crashing fault when enter the system.
(6) CLK. The clock is the necessary condition for the motherboard working
normally. because the frequency is higher when the clock works, so the fault
rate is relatively high In the face of blue screen of death and other
phenomenon¡®s, we need to measure the waveform and the frequency sent by
CLK ,to ensure they are normal.
(7) The graphics card. The laptop with the independent graphics card, the
display chip GPU and the memory temperature are higher it is also easy to
cause the blue screen of death fault.
Chapter 22
Example of Maintenance
(Laptop Repair Cases)
22.1: The Example of Maintenance About Don't

Boot Fault
Example (1): IBM T61 cannot boot
Model: IBM T61
Board Part number: -
Fault phenomenon: Do not boot
Maintenance process:
It is lack of parts when we take it out, after completing it, is plugging, but does
not trigger, and no 3V and 5V standby voltage. Also no VCC3SW, measure the
working condition of VCC3SW production chip U61.VINT20 is 20V,
BAT_VOIT is more 6V, which are normal, is shown in figure 22-1.
Figure 22-1: U61 outputs VCC3SW

Touch the chip, it is very hottest VCC3SW, measure VCC3SW line but it’s not
the short circuit, and then replaces the chip immediately. After replacing, it is
still no VCC3SW, and the chip is also very hot. Think for a while, adopts the
exclusive method to solve: disconnect one by one where VCC3SW goes to,
when disconnect D6, VCC3SW returned to be normal. The figure 22-2 is the
circuit where the D6 is.
Figure 22-2: The screenshot of location of D6

Measure the resistance value of RTCVCC, finds that it’s 0Ω, after removing
C287, the fault is removed. The maintenance tell us that sometimes the
measurement of the resistance value being normal did not represent that there is
no short circuit, because there is a diode, the resistance value is not measured
out.
Example (2): Lenovo G480 inflow water, which cause cannot boot
Model: Lenovo G480
Board Part number: Compal LA-7981P
Fault phenomenon: No standby current
First, deal with the place where clear water is, then plugging it, but there is no
standby current. Test the common point B+, and there is no standby voltage on
B+.
There is no voltage, also no current on the common point, which means that it is
not the short circuit, and there is a problem of the protective isolation circuit. By
the way, measure that the resistance value of B+ is more than 400Ω, means that
it is not the short circuit. Open the drawing and check slowly, find the protective
isolation circuit, is shown in figure 22-3.
Measure the G pole of PQ302, the voltage is more than 18V, it is obviously not
normal. About the isolation principle of Compal, we won't explain more,
measure PACIN directly, and find that it is low level, but it should be high level
here in the normal conditions. Next, find out the production of PACIN.
PACIN voltage is produced by the circuit in the figure 22-4: produced by
BQ24727VDD through the resistance PR336 and P339 dividing into voltage is
controlled by ACPRN. ACPRN should be low level, BQ24727VDD should be
high level. Measure BA24727VDD voltage and find that it is just a zero points a
few volts only, it’s obvious that there is a problem. Then, continues to find the
origin of BQ24727VDD.
Figure 22-3: The protective isolation circuit of Lenovo G480
Figure 22-4: The origin of PACIN

BQ24727VDD voltage is produced by the charging chip PU301, is shown in
figure 22- 5. Measure that the main power supply VCC of the chip is 19V and
measure that ACDET is OV. According to the circuit diagram, calculating that
this voltage should be 2.71V (the computational formula: VIN/(PR314+PR317)
x PR317). Measure that there is no VIN, flies line from VIN in other places
directly, and then measure that BQ24727VDD is more than 5V, of course, the
common point is also normal, this machine is repaired successfully.
figure 22-5: The production circuit of BQ24727
Example (3): Lightning strike cause the Lenovo Z360 does not boot
Model: Lenovo Z360
Board Part number: Quanta DALL7AMB6EO REV: E
Fault phenomenon: Not boot after lightning strike
Figure 22-6
Connect the regulated power supply first, the current is about 0.2A, it is
abnormal. Press the power button, the current changes a little.
Disassembling, find that there are two pins of the data pump igniting, is shown
in figure 22-6, others are normal.
Load the circuit diagram from the china fix forum first, there is no E versions,
find LL7A for reference only.
Find 3V and 5V standby chip PU9, is shown in figure 22-7, the part number is
RT8206. 3V and 5V voltage are normal, measure the resistance value of 3V and
5V, it is more than 900Ω after 5V line, the voltage of 3V line ohm value is
obviously small, and it’s abnormal.
Figure 22-7: The screenshot of the circuit location of the standby chip RT8206
Using the method of burning machine, when the voltage is adjusted to 2.9V, the
current is more than 1A. Checks that if there are burned components or not;
When we touch the graphics card power supply chip RT8152E, our hand is
feeling very hot, then removes it and to replace a new one. The figure 22-8 is
the good chip after replacing. About this chip with QFN packaging, we need to
be careful during welding/soldering; it’s easy to missing solder.
Figure 22-8: The real object of RT8152E
Plugging the power again, the current is stability in 4mA; press the power
button, the current jumps to be less than 100mA, then it will power down
immediately. And we can't detect the graphics card voltage, the independent
graphics voltage and CPU voltage. Measure that the opening voltage of
RT8152E is only zero point a few volts, the resistance value is very small, is
shown in figure 22-9, the 4 pin VRON of PU7 is the opening signal. According
to the drawing (schematic diagram), this pin is only connected the AR25 pin
(shown in figure 22-10) of CPU in the 6th page and a circuit of the 35th page.
Pulling up (remove) CPU first, then we find that there is no short circuit already,
means that CPU is broken (short circuit).
Figure 22-9: The screenshot of PU7 circuit
Figure 22-10: CPU sends GFX_VR_EN
Check the graphics chip is also broken down/the model is N11-GE2-S-

B1.Discuss with the clients, if they are agreed, and then changes CPU and the
graphics chip. Starting up after changing, the current jumps to be more than
600mA, but there is still no CPU voltage.
Find out the production circuit of CPU power supply, is shown in figure 22-1 l,
the 38 pin SHDN of ISL62882 is the opening pin, the measured voltage is OV.
There are three branches to check this signal: VRON, HWPG and SYS_SHDN#,
but PD7, PD9 and PR28 in the figure don't install, which means that SHDN is
produced by VRON through PR21 and PC27 delaying.
Figure 22-11: CPU power supply chip circuit
According to the figure, VRON is connected to the 48 pin of EC. Measure that
PR21 is good, but the voltage of EC48 pin is 3.3V, and then measure the
resistance from PR21 to the 48 pin of EC is infinite, it must be broken. Running
line is failed, in order not to waste time, thought that the factory reserved this
design, we can solve the problem from here. Measure that HWPG is 3.3V, then
find a small resistance to weld on the bonding pad of PR28 (shown in figure 22-
12). Powering on again, the current jumps to be more than 1.5A, the voltage of
CPU is 1.02V, which is normal, connects to the screen and the machine is light.
Then enter into the system, it is normal, so the machine has been repaired.
Figure 22-12: Location of PR28
Example (4): IBM R60 No Standby
Model: IBM R60
Board Part number: RP-1
Get this board, hits (check) the diode range values of each key test point on the
motherboard first and they are in the normal range. Find any one of the D pole
of PWM top tube to hit (check) the diode range value of the common point is
461 (0.461), it is normal. Starting to connect the adjustable power supply, the
ampere meter with 3 bit displays the 0.00, which indicates that there is no
standby voltage.
About IBM machine, in general, if there is no standby, it means that there is no

common point voltage. Check from the common point, is shown in figure 22-13,
measures directly that the D pole of Q34 is OV, and then continues to measure
that -PWRSHUTDOWN is 0V.
Figure 22-13: Screenshot of the circuit Q34 location
-PWRSHUTDOWN signal is from U61.When U61 received the power supply

and detected that there is no over-temperature, then it will open drain output,
and is pulled up to be 3.3V by VCC3SW, conducts Q79,and produces the
common point voltage with small current. (Please refer the specific principle is
in the 18.1 section).
VCC3SW of 59 pin is output by U61. It is 0V here; there may be two

possibilities to cause no output: first, the chip itself is damaged; second, the rear
stage pulls it low to 0V. Then, pry up the 59 pin to measure, the pin is 3.3V,
which is normal, then ruled out the first possibility.
Figure 22-14: The part of the screenshot of U61
Hit the diode value at the bonding pad of 59 pin, the universal meter shows that
it is short circuit to the ground. First, burning machine for a few minutes, touch
the board several times, there is no abnormal. Then starting to remove the
suspected fault chip, when removed Lenovo chip U28, the resistance value
returned to be normal, found a U28 to replace, then measured that -
PWRSHUTDOWN is 3.3V, the common point is also normal.
However, the ampere meter with three bit also displayed 000, then measured
that the voltage on the inductance of VCC3M and VCC5M is OV, so we need
continue to test. The voltage of VCC3M and VCC5M is from U41 (MAX1901).
Measure that the main power supply V+ of the chip is 19V,it is normal; the
linear VL is 5V,it is normal; measure the opening signal VCC3M_ON and
28VCC5M_ON of the 4 pin are OV, it is not normal, as shown in figure 22-16.
Continued to check these two signals are from M1_ON of U28.
Figure 22-15: VCC3SW supplies power to U28
Figure 22-16: The screenshot of the circuit MAX1901 location
Measure that M1_ON is OV. Is there a problem of U28 changed just? Or were
we welding not better? Because we have confidence in our own welding, so it
should be that the working condition of the chip is not enough. The condition of
outputting M1_ON for the Lenovo chip U28 are the power supply VCC3SW,
reset SWPWRG and the adapter detection signal EXTPWR#, is shown in figure
22-17.
Figure 22-17: The screenshot of the working condition of U28
By measuring, we found that -EXTPWR_PMH6 of the 73 pin is 3.3V, it is

abnormal and it should be 0V. This signal is from Q53, is shown in figure 22-18.
Figure 22-18: The screenshot of the circuit Q53 location
The D pole of Q53 is controlled by VLS. At this time, open the bitmap
(BoardView), as shown in figure 22-19, and ready to measure the voltage of
each pin of Q53, but we found that Q53 is missing.
Find a small size of N channel field-effect tube to be installed. Plug the power,
and the standby current is 0.03A, measure that VCC3M and VCC5M have
produced. When this machine is in standby, there is a voltage VCC1R5M, is
measured to be 1.5V, which is normal. After triggering the switch lights
normally, this machine is repaired.
Figure 22-19: The location of Q53 in the bitmap (BoradView)
Example (5): ASUS A42J with multiple faults
Model: ASUS A42J
Board Part number: K42JR
Fault phenomenon: The large current is short circuit and others, 2nd repairer
repair this machine.
Colleagues sent a two repair (2nd repairer) machine of ASUS A42J, the board
No. is K42JR, this large current, we can sure that the fault is on the CPU power
supply field-effect tube (transistor). Just in case, replaced PQ8802, PQ8803,
PQ8801 and the capacitor, is shown in figure 22-20.
Figure 22-20: The screenshot circuit of PQ8802 location

Using the universal meter (Multimeter) to test that the resistance value of the
common point returned to be normal, but when powered on to test, it is so bad.
When CPU is not installed, the current jumps repeatedly from 0V to 0.4V, then
measured the voltage of the common point, it also jumps repeatedly from 8V to
19V. So we can only measure slowly, disconnected the common point, and
measured that the G pole of PQ8901 is short circuit to the grounds it is that
PQ8901 is replaced by 0Ω resistance, is shown in figure 22-21.
Figure 22-21: The screenshot of the circuit PQ8901 location
I thought that this resistance 0Ω should not cause the voltage of the common
point jumping repeatedly, but i was still replacing to 100kΩ resistor. Then
connected the common point, it was still jumping, there is a feature, when
disconnected the standby 3.3V, it would not jump, but tested all relative circuits
with 3.3V, there are all normal. It is not so easy, at the same time with the
common point jumping, I found that the adjustable power supply LED is
protected, so there is the short-circuit protection. As long as disconnected 3.3V,
then it wouldn't jump, but it was jumping repeatedly once powered on.
Generally speaking, if the 3.3V rear stage is short circuit, it would not cause the
common point jumping, so there may be nothing wrong with 3.3V,we also need
to solve it from the common point, but why 19V is normal when disconnects
3.3V. CPU power supply is short circuit first, so we also need to test it from
CPU. By measuring, the diode value of the down tube control level of CPU
power supply is more than 400 (0.400), but the diode value of the top tube
PQ8804 is more than 100. So replaced RT8856 directly, QFN chip of ASUS is
difficult to weld, because the reserved pin is too short. After welding, the
current is also jumping, from 0V to 0.4V, but the common point is not jumping.
Measured CPU power supply, there is no voltage, then tested the conditions of
the CPU power supply chip, is shown in figure 22-22.
Figure 22-22: The screenshot of the circuit CPU Power Supply location
Figure 22-23: Circuit of PCI-E_WAKE# location
Measured that the 1 pin of RT8856 is OV, the 2 pin is 3.3V,the 3 pin frequency
setting resistance is normal,6,8,9,10,11 and 12 are also normal, the 13 pin is
1.05V.there is no voltage on 21 and 31 pin. It is strange, the chip has been
replaced, the control level is normal, is the chip broken? Replaced it again.
After replacing, powered on, the current was not jumping and reached to 1.2A.
For a moment, it was jumping from 0A to 0.7A again, measured the G pole of
the field-effect tube, the G pole of the down tube PQ8806 and PQ8807 are 0Ω.
What's wrong, replaced RT8856 again, I need to check it carefully, can't be
powered on for a long time, used the oscilloscope to measure that the range of G
pole of the top tube PQ8804 is only 5V, so there is wrong with the boosted
circuit, replaced PC8811 directly, then measured that the range of the G pole of
PQ8804 is normal. Powering on again, the current is normal and connected the
screen, the logo of ASUS is displayed.
Installing back the laptop and testing, there is a new problem again, can't shut
down! After powering off, the current is jumping from 1.3A to 2.0A, then the
machine is starting up. Based on the knowledge acquired and some experience,
in general, it is the network wake-up signal that caused the shutdown becoming
to be restart. As shown in figure 22-23, measured PCIE_WAKE# directly,
found that the voltage is only 1.6V, short connected the 7 pin and 8 pin of the
exclusion, the starting up and shutdown are normal, then i can sure that this
resistance is broken. As expected, removed it and measured that the resistance
value is more than 500kΩ. Found a resistance to replace, starting up and
shutdown are normal. After installing, the machine stopped at LOGO! At this
time, I just can remove the peripheral one by one to test. Removed the CD-
ROM first, it also stopped at LOGO; then removed the hard disk, it is normal.
So replaced and installed a good hard disk, then this machine is repaired.
Example (6): ASUS K42JR no standby
Model: ASUS K42JR
Board Part number: K42JR 1.1
Removed the machine, observed that if some components were missing, and if
there have wrong parts, any was corroded on board or repaired before, but all
are okay. Then, used the universal meter (Multimeter) to measure the diode
value of each inductance on the whole board, they were in the normal range.
Since there is no standby current, then plugged in directly and used the
universal meter to measure the standby +3VSUS and +5VSUS, and there is no
voltage. In order to judge the problem quickly, turned off the power first, used
the oscilloscope probe to click on the +5VSUS, then turned on the power, the
waveform is shown in figure 22-24. The peak reaches to 5.8V,it is obviously
wrong, it is the over-voltage protection.
Figure 22-24: The waveform of +5VSUS

This condition is usually caused by the filter capacitor; found the filter capacitor
PCE8110 of +5VSUS is shown in figure 22-25. After replacing, the standby
voltage is appeared. Then the machine has repaired! Must to explain, some
people will ask me, this fault is so easy, why you uses the oscilloscope to repair?
Of course, if i don't use the oscilloscope, I still can repair it, but if i use it, for
this fault, i don't need to test the working condition of the chip or others, so I
can find the problem immediately and save time!
Figure 22-25: The location of PCE8110 circuit
In practical maintenance, if the capacitor is not short circuit, it can be connected

in parallel with a capacitor on the PCE8110, it can also solve the problem. The
figure 22-26 is the screenshot of the description of the electrical features of the
over-voltage protection threshold value of this machine's standby chip RT8205.
When the output voltage reaches to 115% (the maximum value), then it is
protected, that is 5 x 115% = 5.75v.

RT8205 threshold
Example (7): Acer Aspire 4738G powered off
Model: Acer Aspire 4738G
Board Part number: Quanta DAOZQ9MB6C0
Fault phenomenon: Power off
Tested the whole machine, it is powered off, after plugging in, there is no
current. Because it uses the adjustable power supply with three bits, the current
may be too small and can't be displayed. Disassembled the motherboard and
observed it first, the components are not damaged. Follow by measured each
major power supply resistance, which all are normal. Used the universal meter
to measure that the standby voltage is normal and the switch has the voltage.
After pressing the power switch, when the current reached to 0.02A,the machine
is powered off. Observed the current, the voltage is not rising. Opened the
drawing and found that there is the voltage state diagram shown in figure 22-27.
By measuring, found that the voltages marked as ALWAYS is normal and also
the +15V line. According to the timing sequence of Quanta, after triggering the
switch, it should produce +3V_S5 and +5V_S5 (the standby voltage of PCH)
first. These two voltages are produced by PQ57 and PQ15 as shown in figure
22-28. These two MOS tubes are controlled by S5_ON sent by EC.
Figure 22-27: The voltage state diagram
Figure 22-28: The control circuit of S5_ON

When pressing the switch, to measure that the voltage of the 2 pin of PQ16 is
3.3V, it is normal, which indicated that EC has sent S5_ON signal. But
measured +3V_S5 and +5V_S5, there is no voltage. This shows that the
problem should be in the conversion circuit, or in the MOS tube converted +3V
S5 and +5V S5.
Measured that the voltage of the 4 pin of PQ15 is only 0.9V, it should be about
13V usually. Measured that +15V of PR143 is normal after removing PQ19,
S5D is still 0.9V;then removed PQ15,measured that S5D is still 0.9V; at last,
removed PQ57, found that the voltage is normal and is more than 12V.
Removed PQ57 MOS tube and replaced it to this machine, then the machine is
starting up normally, the machine has repaired.
Example (8): ASUS K42JR powered off
Model: ASUS K42JR
Board Part number: K42JR
Fault phenomenon: power off
This machine is sent by the client, it is only the mainboard when we received it
and without the CPU (Processor), but it is not repaired by others repairer. The
fault is that the power LED is bright when pressed the power button, the current
is jumping from 0.01A to 0.03A to 0.01A.There is no drawing of 4.1 version, I
found the 2.0 version and it is almost the same. In the drawing, EC is IT8500,
but this machine is IT8570, it is also almost the same, so i repaired according to
this drawing. Since the power LED is bright when pressed the power button,
which means that there is no problem of the power button. And EC has sent
trigger action.
As shown in figure 22-29, measured directly the 112 pin PM_RSMRST# of EC,
is 3.3V and it is normal. Then measured the 56 pin PM_PWRBTN#, is 3.3V, it
is jumping from high to low to high when pressed the power button. After EC
sending this signal to the bridge, the bridge will send each sleep signal. The
timing sequence of ASUS is shown in figure 22-30. After the bridge receiving
the trigger signal, sent the sleep signal PM_SUSC# and PM_SUSB#.
figure 22-29: The screenshot of some pins of EC
Figure 22-30: The screenshot of the timing sequence of ASUS
Figure 22-31: The real object of HM55 Bridge

PM_SUSC# is sent to the 21 pin of EC, measured it , but there is no reaction.
Then the target is locked on the bridge. There is no bitmap (BoardView), it is
difficult to measure the standby condition of the bridge, so i just can use the
popular method to measure some basic conditions. First, measured the
32.768kHz crystal next to the bridge, one of the pin is 3.0V, and another is no
power. The RTC crystal voltage of the bridge must be wrong. Replaced the
crystal directly, the fault is also same. Need to explain, in fact, the crystal
voltage of the bridge is abnormal, which usually caused by the bridge being
affected with damp or the oscillating circuit aging. But during repairing, we
can't think that there are many problems of the bridge, then to ignore the crystal.
After welding (re-solder) the bridge, the crystal voltage is normal and then
triggered power on, everything is normal.
Example (9): SONY NS90HS cannot boot after lightning strike
Model: SONY NS90HS
Board Part number: MBX-202 (Foxconn M790)
Fault phenomenon: Does not boot after lightning strike
Customers reflect that the power adapter is burning out by the lightning strike, it
still can't boot after replacing a new power adapter. Connected to the adjustable
power supply, found that there is no standby current. Disassembled and found
that the isolation circuit IC has been burned and i can't see their part number.
According to the mainboard No: MBX-202, i found the approximate drawing
(schematic), and found that the IC part number of the isolation circuit is
BQ24751. First, cleaned out BQ24571, found that then bonding pad of the 1, 2,
3, 27 and 28 pin are burned out. Then cleaning, painting the green oil, repairing
the pad and welding the chip. Powering on, found that the standby current is
only 0.001A, it is wrong obviously.
By measuring, found that there is no voltage on the common point; it seems that
there is a problem with the isolation circuit. Opening the drawing (schematic),
measured that there have more than 18V on the D pole, the S pole and the G
pole of PQ24, is shown in figure 22- 32. There have no voltage on the G pole
and the S pole of PQ25, and there have no voltage output on the D pole, it is
strange, PQ24 is broken? Then replaced PQ24, but the fault still exists.
Figure 22-32: The screenshot of the circuit PQ24 location

Then observed the 28 pin of 24751, there have 18.9V on PVCC, it is a little low.
The 4 pin ACDRV# is also 18.5V, it should be normal that PQ25 does not
conduct. Then observed that the 5 pin ACDET is only 0.4V, it is wrong
obviously, it should be about 2.71V. Observed the 8 pin over-voltage detection
pin OVPSET, is 2.70V. Repaired the voltage of the 5 pin first, measured that
resistance value of PR166 and PR15 are normal. There are just BQ24751 and
PD6 connected by AC_OFF_3# will affect the voltage. Took off PD6 first, the
voltage returned to 2.70V, it is normal and it seems that there is short circuit on
AC_OFF_3#, which pulled the voltage low. Find out the circuit connected by
AC_OFF3#, is shown in figure 22-33.
Figure 22-33: The screenshot of AC_OFF_3# circuit
There are not many components in this part, then measured one by one, found
that the resistance value of the S pole and the G pole of PQ6 is more than
100Ω ,the resistance value between these two pins is 0 Ω, the PQ6 is broke
down. After replacing PQ6, the voltage of the 5 pin of BQ24751 is normal, and
each standby voltage is also normal. The standby current returned to 0.022A.
After triggering the machine, it is starting up successfully.
Example (10): Lenovo Xuri 410M power off
Model: Lenovo Xuri M410
Board Part number: Quanta LE4
Fault phenomenon: power off or not power on
Connected the machine and plugged the power, the standby current is 0.01A,
there are 3VPCU and 5VPCU, and +15V is only 4.5V. Pressed the power button,
there is no action, and 3VPCU and 5VPCU are missing. Since found that +15V
voltage is only 4.5V, checked the boosted circuit, is shown in figure 22-34.
Figure 22-34: The screenshot of +15V boosted circuit

Checked PD14 and PD15, there is no problem. Then disconnected PD14, found
that the 2 pin of PD15 outputs 10V, it is normal. So there also is the problem
with +15V boost, replaced the capacitor of PC180, the fault is still existing.
Suspect that +15V is pulled low, so cut off directly at the middle of line of+15V
and found that +15V is normal now. So can be confirm that there is a short
circuit at the back of the+15V line.
Looking up the drawing, +15V provides enough voltage for a series of voltage
conversions, is there the problem with these conversion voltage? Then tested
one by one, found that the resistance value of -3V_S5 is zero as shown in figure
22-35.
Figure 22-35: The production circuit of 3V_S5
Connected to the adjustable power supply and use the machine burning method,
adjusted the voltage to be 3.3V, the current is more than 1.6A, not found the
obvious heating components. Then looked up the drawing again, found that
there are the network card and the South bridge where this voltage flowed to.
Then continued to apply voltage to burn, increase the current to be the
maximum, found that the South bridge is very hot. Put it on the BGA machine
to remove the South bridge, then measured the resistance value of +3V_S5,
found that the resistance value is normal. Replaced the South bridge, installed
the machine and measured, everything is normal.
Example (11): Dell N4030 i3 not trigger
Model: Dell N4030
Board Part number: Wistron DJ1
Fault phenomenon: not trigger/ not boot
Figure 22-36: Standby chip circuit

Customers took a N4030 laptop to repair, the fault is no trigger, and the standby
current is 0.000A. Disassembled the machine and not found that something is
abnormal, there are already 19V on the motherboard, measured the voltage 3.3V
and 5V, found that there is no power. Measured that other working conditions
of the standby chip RT8205 are normal, it is just lack of the opening signal of
PWM. There is no voltage on the 1 pin and the 6 pin, as shown in figure 22-36.
According to the pin definition of RT8205, there is pull-up in the 1 pin and the
6 pin, if through a large resistance connected to the ground, it will be the
overflowing threshold value setting, if connected to the ground directly, it will
close PWM channel. Measured that the voltage of these two pins is 0V, it is
obvious that they are connected to the ground directly. Found out the origin of
51125_ENTIP2 and 51125_ENTIP1, is shown in figure 22-37.
Figure 22-37: The screenshot of the origin of the opening signal
First, analyze the working principle of this circuit when the high level of
3V_5V_EN comes, controls PQ4601 conducted, pulls 51125_ENTRIP1 low,
two field-effects tubes of PQ4602 will be cut off, 51125_ENTIP1 and
51125_ENTIP2 connects to the ground through their own resistance
PR4602 and PR4603, as the overflowing threshold value setting. Measured the
G pole of PQ4601 is just 0V. It seems that the external didn't send 3V_5V_EN,
continued to find out the origin of 3V_5V_EN, is shown in figure 22-38.
Figure 22-38: The origin of 3V_5V_EN
3V_5V_EN is from S5_ENABLE, is controlled by the temperature control

signal (if the temperature is too high, PURE_HW_ SHUTDOWN# is low level,
D4201 will be conducted and pull 3V__5V_EN low, realize the power-off
protection) of D4201. Measured that S5_ENABLE is also OV, indicated that
there is problem with the former level. Continued to find out, and found that
S5_ENABLE is from EC, is shown in figure 22-39.
Since this signal is sent by EC, so need to measure the working condition of EC
first. By measuring, found that EC is lack of the standby voltage, thought for a
while, 3.3V linear voltage produced by the previous standby chip is normal,
why there is no voltage here? Is the line in the middle disconnected, or is there
component in the middle? Continued to find out the origin of the standby
voltage of EC and found it finally, is shown in figure 22-40.
Figure 22-39: EC sends S5_ENABLE
Figure 22-40: The production circuit of the standby voltage of EC

This is a kind of energy saving design of DELL: in the adapter mode, plugged
the adapter and the detection signal AC_IN# is low level, pulled KBC_ON# low
through D3705, controlled Q3704 conducted, produced +KBC_PWR: in the
battery mode, ACJN# is high level, needed by triggering the switch to produce
the low level of KBC_PWRBTN# and pull D3704 low, then pulled KBC_ON#
low, opened the standby voltage of EC.
Found Q3704, measured directly that the G pole is 3.3V. Then measured
AC_IN# , is OV, is it D3705 broken? Then measured KBC ON#, is also low
level, why it will be 3.3V after through R3735? The only possible is that Q3704
is damaged, their GS is broken down. Removed and replace Q3704, the standby
is normal now and triggering the machine is light.
Example (12): Toshiba L500 cannot boot
Model: Toshiba Satellite L500
Board Part number: Inventec 6050a2250201
Fault phenomenon: Cannot boot, the 3.3v is jumping
Counterparts sent a Inventec OEM board, the board No. is 6050a2250201,

surmised that is the Toshiba L500 model. The board was been broken, the
battery interface pin was slanting, and there is nothing unusual in other places.
Measured the resistance value of the motherboard and cannot find something
wrong.
Powered on directly, there is no standby, did not trigger, then measured the
common point voltage directly, it was only 8V. It indicated that there is problem
with the common point, found the protective isolation tube, is shown in figure
22-41.
Figure 22-41: The screenshot of the protective isolation circuit

Measured that the S pole of Q6001 is 19V, the D pole is 8V, the control pole is
19V, it is obviously abnormal, and it seems that there is the problem with the
control circuit. This control pole is controlled by the 2 pin ACDRV# of the
charging chip BQ24721.According to the data manual of BQ24721, the power
supply and ACDET are normal, then the chip will send ACDRV#. ACDRV#
needs send the low level to control Q6001, compared ACDET internal and 1.2V,
ACDET must be greater than 1.2V, then recognized the adapter, is shown in
figure 22-42.
Figure 22-42: The screenshot of the principle in the ACDET
Measured that the 32 pin PVCC of BA24721 is 19V, then measured that
ACDET of the 5 pin is only 0.2V.there is the problem at here. Measured that the
resistance value of two divider resistances of ACDET is normal, checking that
Q6004 and C6015 are normal, removed (removed the charging top tube at the
same time) BQ24721, then measured the voltage of ACDET pin on the bonding
pad, is 1.24V, determined that the chip was damaged. Try to find a chip to
replace unfortunately did not find it and need to order. But you can repair other
functions of the machine first, since there is no chip, then did not install the chip,
took off the pipe of the is common point Q6001, and connected directly the S
pole and the D pole by the insurance, not controlled by this charging chip. After
installing the insurance resistance, the common point has electricity, but no
standby current, measured that the standby 3.3v was jumping from 0V to 3.3V,
the standby 5V was OV. Ignored 5V and repaired 3.3V first. The standby chip
of this board is TPS51125,measured that there is no problem with the power
supply of this chip, when measured ENTRIP2 of the 6 pin, found that the
voltage was also jumping, the 6 pin is controlled by +V5AUXON, is shown in
figure 22-43.
Figure 22-43: The screenshot of TPS51125 circuit
Found out that +V5AUXON signal was connected to the chip U6960, the
voltage of the 1pin of U6960 was also jumping. If U6960 wanted to send
+V5AUXON signal, it must detect that +VBAT voltage is enough and the 5 pin
can't be low level, is shown in figure 22-44.
Figure 22-44: The screenshot of the circuit U6960 location
Measured that the voltage of the 4 pin of U6960 was 3.1V, it was normal,
measured that the voltage of the 5 pin was jumping. Continued to find out the
origin of THRM_ SHUTDWN#, found the chip U14, is shown in figure 22-45.
U14 is also the temperature control chip, through the 2 pin and the 3 pin
detected temperature, the power supply of the chip is the standby 3.3V.Saw the
signal name of the 2 pin and the 3 pin, is thought suddenly that some machines
of Toshiba needed install CPU, then it can boot. The 2 pin and the 3 pin through
the internal of CPU detected temperature, if it could not detect the temperature
of CPU, then it will pull the 4 pin low, and closed the standby 3.3V. After the
standby 3.3V being closed, U14 stopped working again, the 4 pin would not be
pulled low, so the standby, 3.3V can be produced again, continued to supply
power to U14, because U14 could not detect the temperature of CPU, it would
pull the 4 pin low again......, by recycling, so led to the standby 3.3V jumping, it
seems that i took a detour for repairing 3.3V. In order to prevent CPU from
damaging by the subsequent problem, and 5V standby of this machine was also
abnormal, determined not to install CPU, and to remove U14, then measured
that 3.3V was not jump, but there was also no 5V standby, so i needed continue
to repair.
As shown in figure 22-46, measured that the voltage of the 1 pin ENTRIP1 of
TPS51125 is OV, it was not normal. The 1 pin was controlled by EC_PW_ON
signal, the specific principle is: EC sent the high level of EC_PW_ON,
controlled Q6106 conducted, Q6107 was cut off, ENTRIP1 was not connect to
the ground directly, and through R6112 connected to the ground as the first path
of over-current threshold setting of PWM, and opened the first path of PWM.
Figure 22-46: The control circuit of EC_PW_ON
Figure 22-47: EC received ACPRES
Measured that EC_PW_ON was OV, found out that it was from EC. Why EC
did not send EC_PW_ON? I thought the working process of the laptop studied
from internet, EC was broken or EC did not meet the condition for sending
EC_PW_ON. Measured that the power supply and the reset of EC were normal,
then measured that the adapter detection signal of the 95 pin of EC was OV, it
was not normal, is shown in figure 22-47. Found that this signal was from the
charging chip. Because i removed the charging chip before, which lead that EC
could not receive the adapter detection signal, then did not send EC_PW_ON
automatically. Then i just need to replace the chip, this board can be repaired.
But there is no chip, and i want to repair the machine, so i determined to change
the circuit. The original circuit is the VREF5 of 5V output by the 11 pin of the
charging chip, is shown in figure 22-48.
Figure 22-48: The charging output REF partial pressure to ACPRES

Now, there is no VREF5 voltage just can draw a 5V from 5V linear voltage of
TPS51125 to the 1 pin of R6021,then can produce ACPRES. The real object of
the jump wire is shown in figure 22-49.
Figure 22-49: The real object of the jump wire
After jumping the wire, ACPRES was 3.3V, and EC sent the high level of
EC_PW_ON automatically, the standby 5V output normally. Starting up and
triggering, the current stopped at 0.14A, it was normal, measured that there was
no 1.8V, found that the top tube of 1.8V power supply was broken, men
replaced it and there was 1.8V, the current rose to 0.45A.Unplugged the power
installed CPU and the memory, the current stopped at 0.7A again, measured that
there was the waveform for SMBUW. But there was no waveform for the
memory exclusion, replaced a memory, then lightened normally. Remark: about
this machine, we just need to buy a new charging chip, and install U14 and
remove the jump wire, and then it can be repaired completely.
Example (13): Samsung R23 cannot boot
Model: Samsung R23
Board Part number: BA41-00810A
Fault phenomenon: Cannot boot
Colleagues sent a Samsung laptop, plugged the adapter, found that the indicator
light did not light. Disassembled it, measured that there was no high level on the
3 pin and the 4 pin of the standby chip MAX8734,after pressing the switch, it
was still the low level.MAX8734 circuit is shown in figure 22-50.
Figure 22-50: The screenshot of the MAX8734 circuit

Found that KBC3_SUSPWRON was sent by EC. Checked the working
condition of EC, found that the adapter detection signal ADT3_SEL of the 23
pin was OV, is shown in figure 22-51.
Figure 22-51: The adapter detection signal ADT3_SEL of EC
ADT3_SEL was sent by the 6 pin of MAAX 19094s show in figure 22-52.
According to the MAX 1909 manual, this chip need to get DCIN, and ACIN
must be higher than 2.048V, then ACOK will open drain output. Measured that
there was no voltage on the 1 pin of MAX1909, found that D504 was burned,
then hit the value of the 1 pin immediately, it was short circuit. First, took off
C536, then it was normal when hit the value. Found a good diode on the board
to weld, welding the capacitor, the voltage of the 1 pin was normal, installed
CPU and the memory, applied an electric current, the machine was lightened,
this machine was repaired.
Figure 22-52: The screenshot of MAX1909 circuit
22.2: The Example of The Breakdown

Maintenance About Not Bright
Example (14): Lenovo G460 do not run code
Model: Lenovo G460
Fault phenomenon: Do not running error code
After powering on, found that the current was 0.77A. Measured each inductance
voltage on the motherboard, except the charging inductance, others were normal,
CPU power supply was also normal. Since CPU power supply was normal, then
observed two signals after QPU power supply in the timing sequence. The
CLK_EN# and VGATE are shown in figure 2-53.
Figure 22-53: The screenshot of the circuit CLK_EN# and VGATE location
Found that these two signals were normal. Then continued to measure
SYS_PWROK that R397 was 3.3V, is shown in figure 22-54.
Figure 22-54: PCH received SYS_PWROK

According to the timing sequence of HM55, after the bridge receiving
SYS_PWROK, then it will send DRAMPWROK and PROCPWRGD to CPU.
By measuring DRAMPWROK was no voltage, I saw suddenly that there was
the bus power supply good signal under DRAMPWROK in the CPU. Then
measured this signal immediately, measured that both ends of R184 were 0V, is
Figure 22-55: The screenshot of the circuit R184 location

It was this signal who affected the bridge to sent DRAMPWROK? Found that
how this signal was produced first. By measuring, VCCP_POK was from the
bus power supply chip PU7, is shown in figure 22-56. Measured that one end of
PR115 was 5V, and one end of it was only 0.3V, removed PR115, measured
that the resistance value was 1kΩ, it was normal. Was the chip damaged? The
bus power supply 1.1V has produced already. The chip should not be damaged!
Then removed PR114, found that the 2 pin of the chip was 5 V, it was normal. It
indicated that the rear stage short circuit pulled VCCP_POK low.
Figure 22-56: The screenshot of the circuit PR114 location

All connected VCCP_POK lines to disconnect it step by step (or one by one).
As shown in figure 22-57, after removing U8, found that VCCP_POK was not
0.3V, at this time, the current rise from 0.77A to 1.2A, but not to through the
memory. Because U8 was removed at this time, caused that DRAMPWROK
was no power and it needed the high level output by U8 to provide the voltage.
The specific principle is: after YCCP_POK being high level, was sent to U8, U8
output the high level of 3.3V, through R195 and R194 divided into voltage to be
VDDPWRGOOD_R of 1.1 V, phase with PM_DRAM_PWRGD (shown in
figure 22-55) sent by PCH to send CPU.

Replaced U8, this machine was repaired and working properly.
Example (15): Dell V130 no display after powering on
Model: Dell V130
Board Part number: Wistron DR13
Fault phenomenon: No display after powering on
This machine is no display after powering on; the current was 0.38A and it
could not power off. Disassembled this machine, found that the machine was
very-dirty, it was full of dust. Cleaned up first, then powered on to measure, the
current was still 0.38A.
Started to measure the voltage, found that the voltage of +5V_RUN,

+3.3V_RUN and +1.5V_RUN were low. +5V_ALW was only about 2.4V.
Used the universal meter (Multimeter) to measure each voltage, there was no
short circuit, according to the figure 22-58, the control voltage of these three
power supplies were pulled by +15V_ALW. Measured that +15V_ALW was
normal, and the RUN_POWER_ON voltage was low, but was not OV, judged
that one of U4201, U4202 and U4204 was not normal. Disconnected it one by
one to measure and when removed U4201, the RUN_POWER_ON voltage was
normal. Replaced U4201 directly, this machine was repaired.
Figure 22-58: The production circuit of +5V_RUN and other voltages

The principle in the figure 22-58: after triggering and powering on, the high
level of PM_SLP_S3# controlled the conduction of the 3 pin and the 4 pin of
Q4202, the 2 pin was pulled low at the same time. Then the 6 pin and the 1 pin
would cut off, RUN_POWER_ON was pulled up to be 15V by +15V_ALW, to
control the conduction of three N channel field-effect tubes, produced three
RUN voltages.
Example (16): Samsung R428 no display after powering on
Model: Samsung R428
Board Part number: BA41-01217A
Fault phenomenon: No display after powering on
There was no display after powering on. The current was 0.3A, replaced the
South bridge, removed the network card, and removed the capacitor under the
South bridge, but it could not be solved. By measuring, the power supply was
normal, but found that a wire was broken when other people removed the
capacitor, repaired it immediately. Measured again, found that the card reader
chip was very hot then removed it directly. For the sake of insurance, not power
on directly, and measured the diode value of other power supply. Found that the
diode value of P5.0V was only more than 30, it was obviously low. According
to the circuit diagram, found that P5.0V was produced by P5.0V_ALW
converting through-Q531, is shown in figure 22-59.The high level of
KBC_PWRON controlled the conduction of Q537 pulled the G pole of Q531
low. Q531 was P channel, the low level was conducted completely,
P5.0V_ALW produced P5.0V normally, then through the short contact
produced P5.0V_ AUD.
Figure 22-59: The production circuit of P5.0V

P5.0V_AUD through two chip inductance B19 and B528 entered into the sound
card chip, is shown in figure 22-60. After disconnecting B19 and B528, P5.0V
was not short circuit. Then powered on again, the current is rise to 0.5A and no
any jumping of the current. Installed CPU dummy load to measure it and found
that there were no PG and reset of CPU.
Figure 22-60: The screenshot of the part of sound card chip

CPU had no PG and reset, so i must repair PG signal first. PG of the Intel
chipset CPU was provided by the South bridge, is shown in figure 22-61,
Figure 22-61: The South Bridge sends CPUPWRGD

By measuring, found that the power supply of the South bridge was normal,
VRMPWRGD war normal, PWROK was also normal. When measured 33MHz
clock required by the South bridge, found that the voltage was 3.3V, is shown in
figure 22- 62.When measured the clock chip, other clocks were normal, only
33MHz clock was not normal. I judged that 33MHz module in the clock chip
was damaged, replaced the clock chip, then the machine was repaired.
Figure 22-62: The screenshot of the 33MHz clock circuit of the South Bridge
Example (17): Inventec HP511 no display and powered down
Model: HP 511
Board Part number: Inventec 6050A2257101
Fault phenomenon: Power down after triggering
The fault of this machine was that it was powered down to be the standby after
triggering power on to 180mA (0.18A) a few seconds later.
First, measured the ground value of each inductance, there was no short circuit,
then powered on, measured that there was no voltage of CPU power supply
inductance. Measured directly that R9879 was no voltage, as shown in figure
22-63. PWR_GOOD_3 is the opening signal of CPU core power supply.
Figure 22-63: The screenshot of CPU power supply opening signal
Found out the origin of PWR_GOOD_3 directly, is shown in figure 22-64. At

this time, the Inventec "Big OR Gate" taught by the previous chapter from this
ebook, i don't explain this circuit principle at here. Measured directly that the 7
pin of U4 was 0V, and the 5 pin was 0V. Then measured that the voltage of
both ends of R99 were OV, then checked the origin of +V3S voltage.
Figure 22-64: The production circuit of PWR_GOOD_3
+V3S is from Q39, is shown in figure 22-65.Measured that the voltage of the D
pole of Q39 was 3.3V, the voltage of the S pole was OV, the voltage of the G
pole was 0.3V, it was obviously not normal, measured R430 that the voltage of
the 1 pin was 17.64V, but the voltage of the 2 pin was 0.5V. it seems that it was
pulled low. Then measured the resistance of the S pole of Q39 was normal. Q39
was good and C408 was also normal, then check the origin of GATE_3S_R.
GATE_3S_R went to two places: the first place is shown in figjire-22--66, by

measuring, Q16 was normal, so this place is normal.
The other path/place of GATE_3 S_R went to the production circuit of the
graphics card core power supplies shown in figure 22-67. Measured that the
voltage of the 2 pin of the resistance R9862 was 0.3V, i thought that it may be
pulled low by U7015 chip, then disconnected the resistance R9862. Triggered
boot again, +V3S and +V5S were produced. The current rise to 0.6A.Then
found a TPS1511 on the board to replace. The machine is light normally. This
machine was repaired.
Figure 22-67: The product circuit of the graphics card core power supply
As a beginner, has a less experience for repairing laptop/machine, in fact, the
chip is damaged. I don't measure the voltage of L550 inductance at that time
just measured 1.8V and 1.2V, then don't measure the voltage of the CPU
inductance. Because it is the first time to repair this kind of circuit of Inventec.
Although waste some time, but it's still worth it.
Example (18): eMachines D725 inflow water, which cause no light
Model: eMachines D725 (operated by Acer)
Board Part number: HW40-MV
Fault phenomenon: The current stopped at 0.09A after triggering
This machine was inflow the large area of water, after cleaning up, then
powered on, measured that there have 3.3V and 5V, the standby current 0.09A,
it was changed when triggered, the transient current also stopped at 0.09A, It
seems that it was much more likely the short circuit protection, then started to
measure. As shown in figure 22-68, when measured the L17, found that the
diode value was only 5, it was the inductance of 1.8V; measured that the diode
value of the L16 was 4, it was the inductance of 1.05V. These two power
supplies were controlled by the same chip TPS51124, measured the G pole of
the down tube U25 of 1.8V power supply, found that the diode value was only
36, and determined that the chip was damaged. Replaced the chip directly, then
the diode value was normal; the diode value of the G pole of U25 was more
than 300, the diode value of 1.8V inductance was more than 120, the diode
value of 1.05V inductance was 9.
Figure 22-68: The screenshot of the TPS51124 circuit
Plugged in again, the standby was 0.005A. Pressed the switch to trigger,
triggered the current 0.19A. Measured and found that there were no voltage of
1.8V and 1.05V, but their opening signal found that PM_SLP_S4# and
PM_SLP_S3# were produces shown in figure 22-69.
Figure 22-69: The screenshot of the open circuit of TPS51124

Measured the power supply of TPS51123, the 16 pin was 5V, the 15 pin was
only 2.5V, measured and found that the resistance value of R274 increases high,
replaced 1.8V and 1.05V rapidly, then it was normal. Installed the CPU and the
memory, plugged the screen, then started up, but the screen was dark. I though
it should be caused by the screen high pressure without boosting. Removed the
screen and found that there were a lot of water in the screen, and it was
corroded, some pins of the interface were gone. So this is a panel/screen failure
and is shown in figure 22-70. At last, replace a screen, this machine can display
normally.
Figure 22-70: The circuit board of the screen with water and moldy
Example (19): Lenovo G470 no CPU voltage
Model: Lenovo G470
Fault phenomenon: No CPU voltage
The board powered on, the current was about 0.37A, and measured found that
other voltage were normal except the CPU voltage. The CPU power
management chip is ISL95831, is shown in figure 22-71.
Figure 22-71: The screenshot of the ISL95831 circuit

Measured and found that VIN, VDD, VDDP, VRON, BOOT1 and BOOT2
voltage were normal. Replaced a CPU, but the fault was still exist. So just used
the oscilloscope, because the CPU of this machine was the i3 second generation,
the adjusting way of CPU voltage was changed from the previous PVID
combination to the CPU internal SVID module adjustment, measured that the
ground value and the voltage of SVID_SDA and SVID_SCLK were normal, but
there was no any waveform. According to the timing sequence of HM6X, if the
SVID module in the CPU wanted to work, CPU must meet the PROCPWRD
signal. But the position number of the resistance and the capacitor on this board
were not marked, it was not easy to find the measurement point of this signal, is
Measured the PROCPWRD and found the voltage was 0V. Because in the
timing sequence of HM6 series, PROCPWRGD was sent to CPU by the bridge
after the bridge communicating with BIOS normally. BIOS or the bridge was
damaged, which would cause that PROCPWRGD couldn't be sent. Then,
brushed (re-programme) BIOS first, the fault was still existing, continued to
replace HM65, then measured that PROCPWRGD was 1.05V, it was normal, so
CPU should send SVID to the power management chip. SVID waveform is
Then measured the CPU power supply, there was the voltage on the inductance,
but it was missing immediately. By measuring, was the over-voltage protection,
replaced the filter capacitor, the laptop was normal now.
Figure 22-72: The screenshot of PROCPWRGD measurement point
Figure 22-73: SVID waveform
Example (20): Lenovo Y430 no clock no display
Model: Lenovo Y430
Fault phenomenon: No display
After receiving the machine, started up but it was not display. The current
jumped to 0.46A, removed and found that the network card was removed by
others. Measured the voltage of each inductance, there were the standby 3V, 5V,
the bridge power supply, the memory power supply and the CPU power supply
all are normal. So use the oscilloscope to measure the clock. Found that there
was no clock.
Measured the power supply of the clock chip, is shown in figure 22-74: each pin
connected with +3VM_CK505 was 3.3V, each voltage of +1.5VM_CK505 was
1.05V. I though this voltage was not normal and should be 1.5V, but found that
this pin was connected to VCCP, which indicated that 1.05V was normal.
Measured that there was the waveform of the 4 pin and the 5 pin, and then
measured the opening signal of the 1 pin. Found that there was no voltage, and
measured that CK_PWRGD was from the South bridge, is shown in figure 22-
75.
Figure 22-74: The screenshot of the clock circuit
Figure 22-75: The South Bridge sends CK_PWRGD
Measured that the South bridge did not send CK_PWRGD_R, measured that
there was the voltage on the South bridge PWROK and VRMPWRGD,
determined that the South bridge is damaged. Removed the South bridge and
replaced it. Measured that it sent CK PWRGD signal normally, this machine
was repaired.
Example (21): Acer 5750G starting up but no display
Model: Acer 5750G
Fault phenomenon: Starting up but no display
The adjustable power supply switched on, the current stopped at 0.4A.
Disassembled the machine, measured the voltage of each inductance, there were
3.3V, 5V, 1.8V, 1.5V and 0.9V. But when measured the CPU power supply,
there was no voltage, CPU power supply chip is ISL95831, is shown in figure
22-76. There was no drawing in my computer, so loaded the circuit diagram of
Acer 5750G from the internet, then opened the circuit diagram, according to the
drawing, measured the power supply of the CPU power supply chip, is shown in
figure 22-77, the 23 pin was 19V, there was no voltage on the 11 pin.
Figure 22-76: The real object of the CPU power supply chip
Figure 22-77: The circuit diagram of the CPU power supply chip
The power supply of the 22 pin was +5VS, measured and found that it was
produced by U22, is shown in figure 22-78. Measured and found that SUSP was
OV, but there was no voltage on the G pole of U22. By detecting, found that
there was slight corrosion beside of R372, but the voltage was 19V.

Since R372 was connected to the G pole of U22, both ends of R372 were 19V.It
was obviously that the control of U22 to R732 in between was line broke. Then
jumped a wire from U22 to R732 and repaired successfully. Starting up again,
powered down at the first time, and restarted automatically. After installing
CMOS battery, the current was normal. Then, this board was repaired.
22.3: The Fault Maintenance Examples of

Power Down
Example (22): Use the oscilloscope to repair the fault of power down of
Lenovo G450
Model: Lenovo G450
Fault phenomenon: Trigger power down
Figure 22-79: The channel-1 represented +5VALW and Channel-2 represented

+3VALW
The standby current of this machine was 0.01A, it was normal. After triggering,
the current jumped to 0.02A. After powering down, the standby was 0.00A and
could not be triggered.
Disassembled this machine, measured that the resistance value of each power
supply was normal. Depended on the experience, about this kind of situation,
when the standby voltage +3VALW or +5VALW converted the rear stage
voltage, there was the short circuit, which caused the protection. In order to
confirm that it was +3VALW or +5VALW conversion voltage who was the
short circuit, which caused the power down protection, then used the
oscilloscope to find the accurate answer. As shown in figure 22- 79, the channel
1 represented +5VALW, channel 2 represented +3VALW, in the figure,
+5VALW was directly straight down (drop), but +3VALW was falling slowly,
which indicated that there was the problem with +5VALW conversion voltage.
Then searched the origin of +5VALW directly, found the conversion MOS tube
U54, is shown in figure 22-80.When the low level of SUSP came,Q28 was cut
off, B+ pulled up the G pole of U54, made it conducted completely, +5VALW
converted to be +5VS and +5VALW TO +5VS.
Figure 22-80: The circuit location of U54

Measured the resistance value of the 1 pin, 2 pin and the 3 pin of MOS tube
U54 was 0Ω, which indicated that there was the short circuit. Burned machine
directly (use machine burn method), used the DC regulated power supply to
connect 3V voltage to the 1 pin, 2 pin and the 3 pin of U54, and forced to
supply power to it. Touched C460, it was hot, removed C460 directly, then
plugged in again, started up and triggered, the current was normal, connected
the screen and the machine was light, this machine was repaired.
Example (23): Lenovo G550 the standby is abnormal and power down
Model: Lenovo G550
Fault phenomenon: The standby is abnormal, power down after triggering
Colleagues sent the Lenovo G550, the light was bright after starting up, but
there was no display on the screen, and would power down. First, observed the
appearance, it was no problem. Connected the regulated power supply, the
standby was about 0.2A, the current was obviously abnormal, in general, the
current should be about 0.02A. Disassembled machine and powered on, the
current was still about 0.2A. Don't worry to measure first, should touched the
main components on the motherboard, when touched EC, the temperature was
obviously high, just turned over and touched the other side, my hand was
scalded by something, observed carefully, it was the USB power supply chip
U50. Use the universal meter (multimeter) to measure that it was short circuit to
the ground. The location circuit of U50 is shown in figure 22-81.
Figure 22-81: The circuit location of U50
After removing U50, the standby current changed to be 0.017A, it was normal.
Pressed the switch, powered on, 1.7A-2.2A-3.3A, powered down at the large
current, it was slow large current doubted that there was a problem with a
certain power supply, measured the resistance value of each large inductance, it
was normal. Removed CPU, and powered on, the current was about 0.6A, there
was no large current. At this time, measure each voltage: the memory power
supply and the memory load power supply were normal, when measured PL501,
found that there was no output. Looked up PU501 drawing, is shown in figure
22-83. Measured the working conditions of PU501: V5FIIT, V5DRV and EN
were normalized the oscilloscope to measure the G pole of the top tube PQ501
and found that there was no instantaneous waveform, judged that PU501 was
damaged. After replaced it, there was +1.5VP, which indicated that it was
PU501 damaged.
Installed CPU, started up, waited for a moment, the machine is light, entered
into the system, everything was normal, and finally this machine was repaired.
The figure 22-83 is the real object of PU501.
Figure 22-83: The real object of PU501
Example (24): HP 4411S power down when enter into the system
Model: HP 4411S
Fault phenomenon: Power down when enter into the system
Disassembled the machine and solved the problem of the heat dissipation, but it
was still powered down, replaced the memory, still powered down, then
replaced the hard disk and installed the system, still powered down, after
replacing CPU, still powered down. The basic exclusive method has been used,
then welded (re-solder) CPU power supply chip, but it was still power down, so
just used the oscilloscope to exclude one by one. The figure 22- 84 is the
comparison of the waveform of SLP_S3# SR and VR_PWRGD.
I repaired many machine with the fault of power down, but it was rare to find
that these two signals powered down at the same time. Then found a voltage
+VCC_CORE to compare with SLP_S3#_3R, two signals still powered down at
the same time, is shown in figure 22-85.
Figure 22-84: The comparison of the waveform-1
Analysis:
(1) It might that 3V and 5V standby voltage load capacitor decreased;
(2) The common point load capacitor was not enough.
Then compared SLP_S3#_3R with the standby voltage +V5A, the waveform is
shown in figure 22-86, in the figure, after +V5A voltage powering down, about
700ms later, it returned to be normal. It was really that the standby voltage load
capacitor decreased?
First, added a 220uF capacitor on the +V5A terminal, but it was still powered
down. Intended to replace the chip, but i have no TPS51125 at that time. So,
continued to measure the mainboard. Then measured SLP_S3#_3R and
+VBATR common point voltage. The comparison of the waveform is shown in
figure 22-87, as the figure shown, after powering down. The common point
voltage returned to be normal 250ms later.

Then, the problem was found, the problem was most likely on the two isolation
tubes, replaced Q25 and Q26, the problem was solved. After repairing,
summarized and analyzed, in fact, powering down should have nothing to do
with Q26, because there was an body diode in the Q26, during measuring by the
oscilloscope, the voltage on the common point was dropped to 0V, then
returned to be normal, if it caused by Q26, it would not drop to OV, then
returned to be normal. The circuit where the Q25 and Q26 are is shown in figure
22-88.
Figure 22-88: The screenshot of the circuit location of Q25 and Q26
Example (25): Acer Aspire 4310 power down
Model: Acer Aspire 4310
Board Part number: Wistron Volvi 07200-1
Fault phenomenon: Power down protection after triggering
Used the regulated power supply, the standby was 0.03A, started up, it jumped
to 0.24A, but powered down 1second later, changed the standby to 0.04A. And
then pressed the power button, but there was no response.
According to the fault phenomenon, judged that the short circuit on the rear
stage circuit was protected. Disassembled and observed that there was no
obvious fault point, powered on, measured the voltage of each large inductance,
found that there was no 1D8V_S3 and CPU power supply, determined to repair
1D8V_S3 first. Looked up the drawing, 1D8V_S3 was provided by U22
MAX8717, is shown in figure 22-89.
Figure 22-89: The production circuit of 1D8V_S3

Measured the other group of U22 output 1D05V_S0, used the universal meter to
measure the voltage of 1.1V, and judged that the power supply of MAX8717
has been satisfied. Then, test the opening signal ON1 of 1D8V_S3, is shown in
figure 22-90, this pin was controlled by PM_SLP_S4#.
Measured PM_SLP_S4# voltage, was only 1.5V, it was not normal. This pin
was 3.3 high level sent by the South Bridge. Used the small knife/burin to
disconnect the 6 pin, is shown in figure 22-91.
Figure 22-90: PK_SLP_S4# control ON1
Figure 22-91: The real object of MAX8717E cut by the knife/burin

After disconnecting ON1, PM_SLP_S4# was changed to be 3.3V, it indicated
that there was a problem with the rear stage of MAX8717, measured that the
resistance value of LI4 was normal. Replaced the filter capacitor C283 back of
the inductance, the fault still existed. Opened the oscilloscope, measured that
there was the voltage output on 1.8V when started up. Continued to use the
burin to cut G29-G38 (the isolation point of 1D8VJPWM and lD8V_S3), is
shown in figure 22-92. Measure again that 1D8V_PWM output normally,
indicated that there was the short circuit on the rear stage of 1D8V_S3.
Figure 22-92: The real object of the isolation point
Continued to test the whereabouts of 1D8V_S3, is shown in figure 22-93. After

removing U49, the current could jump to 0.55A, measured the 1, 2 &3 pin of
U49, the resistance value was 0 ohm. Found the whereabouts of 1D8V_S0, was
the North bridge or the capacitor. Adjusted the regulated power supply to be
1.5V, the maximum current was limited about 3A, started to burn the machine,
found that there was a problem with C444, is shown in figure 22- 94.Then
removed it, there was no short circuit on 1D8V_S0.
Figure 22-93: The screenshot of the circuit of U49 location
Figure 22-94: The real object of C444
Installed CMOS battery first, then plugged the power, the current jumped to be
more than 1A, CPU power supply was normal. Then connected the screen, the
machine was light, entered into the system, everything was normal, then this
machine was repaired.
Example (26): Lenovo ZhaoYang E43G power down after triggering
Model: Lenovo ZhaoYang E43G
Board Part number: Quanta DA0LE9MB8EO REV: E
Fault phenomenon: No trigger, power down after triggering
Figure 22-95: Interface of the switch board
Received the machine of Zhaoyang E43G, was the integrated graphics card, the
South bridge was 82801IBM, EC was IT8502, the board No. was
DAOLE9MB8EO. Unplugged the battery and connected to the adjustable
power supply, the standby current was 0.05A, i thought it was high, pressed the
switch, there was no reaction to the current. Disassembled the machine directly,
took the switching line out and observed carefully, the switching line was
obviously broken. Found the drawing and measured the interface of the switch
board, is shown in figure 22-95, the 8 pin was the switch pin, connected this pin
to the ground, the current rise from 0.05A to 0.13A, but dropped to 0.05A again,
the whole process lasted about 0.5s.
Measured and found that there was no the South bridge standby voltage, but i
could not find the reason why there was no the South bridge standby voltage.
Then i asked the repair friend and he told me that about the board of Quanta,
after triggering, then there was the South bridge standby voltage. Then,
measured the standby voltage of the South bridge and RSMRST# signal at the
moment of triggering, they were normal. At the moment of starting up, the
memory power supply was normal, but there was no the bus +1.05V. +1.05V
was controlled and produced by PU9, is shown in figure 22-96.
Figure 22-96: The screenshot of PU9 circuit

Observed the working conditions of PU9, the 2 pin, the 9 pin and the 13 pin
should be 5V, the 15 pin should be high level, but measured and found that just
the 9 pin and the 13 pin were 5V, the 2 pin was 1.3V. Measured the resistance
value, it was normal, then removed PC146 (1uF/6.3V), the voltage was normal,
started up normally and the machine was light.
Example (27): HP 510 power down repeatedly and restart after starting up
Model: HP 510
Fault phenomenon: Power down repeatedly and restart after starting up
Connected the adapter, the standby was 0.02A, it was normal, triggered and the
current jumped to 0.12A, then powered down. Repeated this action and
measured the voltage on the large inductance, there was no CPU voltage, the
voltage of others was normal.
Then measured the opening signal of CPU directly, found that there was no
voltage. So there was no problem with CPU voltage, I thought that there was a
problem with a certain small voltage. When measured Q41, found that there was
no voltage on the 4 pin, is shown in figure 22-97.
Figure 22-97: The screenshot of the circuit location of Q41

There was no voltage on Q41,it was abnormal. Measured that there was no voltage on
the 1 pin of R417,according to the drawing, found out Q43,is shown in figure 22-98.
Figure 22-98: The screenshot of the circuit location of Q43

The principle of the production of GATE_3S, the high level of SLP_S3#_3R
controlled Q52 and Q54 conducted, then Q53 was cut off, the 1 pin of Q43 was
pulled low, Q43 was conducted, +VBATR flowed to GATE_3S through Q43.
Measured and found that R781 became to be infinitely large, replaced the
resistance and powered on, then the machine was light.
Example (28): Lenovo V450 power down when starting up
Model: Lenovo V450
Fault phenomenon: Power down after starting up
Maintenance process: The current was 0.33A after staring up, powered down
after a few second, and could repeat to trigger after powering down.
From the fault phenomenon, not only instant power down, and to be the standby
after powering down, could repeat to trigger. I thought that the voltage was not
enough first. Observed the board, there was no water, but EC was replaced.
Measured the resistance value of each large inductance, found that it was
normal, and the voltage of each inductance was normal, there was also CPU
power supply, so the main voltage was normal, then it was impossible that the
power down caused by the lack of the voltage.
Since the voltage was normal, measure the condition of the reset of mainboard.
Measured the PG signal VGATE of the CPU voltage first, is shown in figure
22-99.
Figure 22-99: The CPU power supply chip sends VGATE
VGATE was only 1.36V, from the circuit diagram, after PU2 outputting
VGATE, it was pulled up to be high level (all the power chips were the open
drain output PG) it was obviously that this pin should be 3.3V. Measured that
the diode value of the 1 pin was 530, it was normal, found out PR8, measured
one end of+3VS was 1.36V, it was normal.
Found out the production origin of +3VS was U20, is shown in figure 22-100.
Analyze the circuit principle of U20: the low level of SUSP controlled Q32 to
be cut off, then +VSB through R450 pulled up the G pole of U20, U20 was
conducted completely, +3VALW converted to be +3VS. Measured that the D
pole 3.3V of U20 was normal, the S pole was only 1.36V, measured that the G
pole was only 2.18V, found R450, measured that one end of +VSB was 19V,the
resistance value of R450 was 47k , it was normal, removed C572, the fault was
still existing. Measured that the voltage of the G pole of Q32, it was 1.63V in
standby, after powering on, it was 1.74V, it was obviously abnormal. Measured
the G pole SUSP of Q30, it was 3.3V in standby, after powering on, it was OV,
it was normal. Used the buzzing gears to measure that the G pole of Q32 and
the G pole of Q30, it was normal, determined that the wire was broken. Then
jumped wire immediately, powered on again, the fault phenomenon still existed:
the current jumped to 0.33A, then powered down a few seconds later.
Figure 22-100: The production origin of +3VS
After powering down, measured that the G pole of Q32 was 1.72V, and the G
pole of Q30 was 1.72V, though a while, cocked Q32, measured that the voltage
of the G pole was normal, took off Q32 and measured that the diode value
between the G pole and the S pole was about 950, the reverse diode value
between the D pole and the S pole was more than 900, the performance of Q32
was poor, which caused electric leakage. Replaced Q32, plugged the memory,
the current was normalized the oscilloscope to measure I2C bus of LVDS
interface. There was the action of reading the screen, and then this board was
repaired.
Summarize, there were two faults in this machine, the line of the G pole of Q32
was broken, the performance of Q32 was poor.
Example (29): HP 4411 power down repeatedly after starting up
Model: HP 4411
Fault phenomenon: Power down repeatedly after starting up
Colleagues sent the machine of HP 4411, plugged power and the current was
0.03A- 0.02A-0.023A-0.03A-0.02A-0.023A…, after triggering automatically,
powered down repeatedly. Measured and found that there were other voltages
except the CPU voltage, it seems that it was lack of the CPU voltage.
Opened the drawing directly, is shown in figure 22-101, the main power supply
V5IN was 5V, it was normal. Then measure directly that the opening signal 34
pin was 0V. Measured that the diode value was more than 300, it seems that the
external did not send signal.
Figure 22-101: The screenshot of the circuit CPU power supply chip location
As shown in figure 22-102, PWR_GOOD_3 was sent by the "Big OR Gate"
circuit Measured that the 5 pin was 1.37V, the 6 pin was 1.99V, found the
voltage of both ends of R27 was 1.37V, removed R16 and C17, the voltage was
1.44V, it seems that there was no problem with these two components.
Measured that the voltage of +5S and +3S was normal, and then there must be
the problem with the remaining PG signals. Measured that the voltage of the 1
pin and the 2 pin of D1001 was 3.3V, when removed R15 and plugged power.
The current was stable with 0.98A. It seems that the problem was found out.
Since after disconnecting V1.5S_PG, it was normal, then measured +V1.5S
voltage. The production circuit of +V1.5S is shown in figure 22-103, measured
and found that +V1.5S output normally, then there was a problem with PG
output of the chip APL5930. I though, since the voltage was normal, then
ignored PG and removed R15 directly, plugged the memory, connected the
screen, the current was normal. The machine displayed.
Figure 22-102: “Big OR Gate” circuit
Figure 22-103: The screenshot of the production circuit of +1.5S
22.4: The Maintenance Examples of Other

Faults
Example (30): ASUS A8E large short circuit when install battery
Model: ASUS A8E
Board Part number: A8E/A8S
Fault phenomenon: It was normal when plugged the adapter, but it was large
short circuit when plugged the battery.
This board was inflow water and been repaired by others, it could start up
normally when plugged the adapter, it was also normal when just installed the
battery, but if installed the battery and plugged the adapter at the same time,
there was the large short circuit.
About this fault, in general, considered the battery discharge tube, is shown in
figure 22- 104, Q8800 is the battery discharge tube, removed it first.
Figure 22-104: The battery discharge tube
Tried to power on again, the fault was still existing, the voltage of the regulated
power supply was pulled low, powered off immediately, tested carefully again.
As shown in figure 22-105, when removed the charging top tube Q8802, it was
no short circuit. There was the P channel tube. I thought that other maintenance
man installed the tube incorrectly, then found a P channel tube to replace, tried
again, it was still the large short circuit. I thought that it was the charging chip
that caused it. Then found a charging chip on the board to replace, powered on,
the fault still existed.
Figure 22-105: The screenshot of the charging circuit
At this time, thought for a while, because the large short circuit was caused by
installing the battery, so i thought if this machine could not be installed the
battery, and it also could charge the voltage? Then, took out the battery
immediately, then made CHG_EN# to be artificial grounding, is shown in
figure 22-106. Because EC could not detect the battery, so it would not send the
low level of CHG_EN#. When pulled CHG_EN# low, cheated the charging
chip, made it thought that it was EC who sent the charge enable signal.
Figure 22-106: The screenshot of the circuit CHG_EN# location
It was really effective, the charge chip started PWM, and output the voltage,
used the universal meter to measure, found that the voltage was 19V. No
wonder it would cause the large short circuit, then it was easy, according to the
working principle of the charge chip, MODE set the number of batteries in
series, no matter how to connect MODE, and it would not cause that PWM
output 19V. The only possibility was that there was a problem with the top tube
or the voltage feedback.
The pin definition of MODE pin:
Tri-level Input for Setting Number of Cells and Asserting the Conditioning
Mode:
MODE = GND; asserts conditioning mode.
MODE = float; charge with 3 times the cell voltage programmed at VCTL.
MODE = LDO; charge with 4 times the cell voltage programmed at VCTL.
The top tube has been replaced before-then there was only a problem of the
voltage feedback. Measured the diode value of the BATT pin of the chip and
the battery interface, found that it was more than 300. Then measured the BATT
pin and the ground, they were O. Observed carefully and found, when a
maintenance man handled the water fault, repaired the line of the BATT pin, he
could not repair it, but connected FB to the ground. Then removed the original
line immediately, repaired the line again. Then measured the BATT and the
battery interfaced was normal.
Installed the battery again, plugged the adapter. The current was 1.5 A when not
start up, started to charge, triggered and started up, everything was normal,
repaired it successfully.
Example (31): Lenovo S10-2 dark screen
Model: Lenovo S10-2
Fault phenomenon: Dark screen
Received a Lenovo S10-2, the fault was the dark screen. Replaced the screen,
but it was also dark screen. As shown in figure 22-107, measured that the 20 pin
of the screen interface was 19V, but found that BKOFF# was OV, powered off
and the resistance value was 6Ω, it was obviously the short circuit, removed
C10, it was still the short circuit.
Figure 22-107: The screenshot of the screen interface circuit
Found out the origin of BKOFF#, connected to EC (KB926) is shown in figure

22- 108. Cocked the pin BKOFF# of EC, and then measured BKOFF#, it was
no short circuit judged that EC was damaged. I thought, since other functions
were normal, it was not necessary to replace EC.
Figure 22-108: EC sends BK_OFF#
Solution: Jumped the wire from +LCDVDD to BKOFF# directly. Started up the
machine, measure it and the machine is working properly. Why use the
+LCDVDD? Because after detected the graphic card successfully, then there is
the voltage on the +LCDVDD. So that it would not cause the white screen and
other problems on the screen.
END
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Laptop Chip Level Repair Guide 2

Chapter 2: Original & OEM Laptop Mainboard Part Numbers

Chapter 3: The Architecture of The Laptop Mainboard

Chapter 4: The Explanation of Nouns and Common Concepts of

Laptop Chip Level Repair Guide 3

4.5 Reset Signal................................................................................................. 39

Chapter 5: The Basic Application Circuit of Electronic

Chapter 7: Introduction of EC and BIOS…89

Laptop Chip Level Repair Guide 4

Chapter 8: The Basic Working Process of Laptop Computer

Chapter 9: The Explanation of PWM Circuit

Laptop Chip Level Repair Guide 5

Chapter 10: Analysis of Quanta OEM Laptop Mainboard Circuit

Chapter 11: Analysis of Wistron OEM Laptop Mainboard

Chapter 12: Analysis of Compal OEM Laptop Mainboard Circuit

Chapter 13: Analysis of Inventec OEM Laptop Mainboard

Chapter 14: Analysis of INTEL PCH Power on Sequence (i3/i5/i7)

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Chapter 15: Analysis of ASUS K42JR (HM5x) Timing Sequence

Chapter 16: Analysis of Apple A1286 (HM5x) Timing Sequence

Chapter 17: Analysis of DELL N4110 (HM6x) Timing Sequence

Chapter 18: Analysis of ThinkPad (IBM) T410 Timing Sequence

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Chapter 19: Analysis of AMD Platform Timing Sequence

Chapter 20: Analysis of the Laptop Battery Charging Circuit

Chapter 21: Maintenance of Common Failures

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Chapter 22: Example of Maintenance (Laptop Repair Cases)

22.4 The maintenance examples of other faults

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You CANNOT give this E-book away for free.

Copyright @ All Rights Reserved

Disclaimer And/ Or Legal Notices

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Limit of Liability/ Disclaimer of Warranty:

No this parts of this E-book/Guide/Manual shall be reproduced or

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If you want to learn more about Electronic Repair

Thank You for Contribution

Author of this ebook

Note: Some words meaning in this ebook

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1.1: The Level of Laptop Computer

 Install Operation System (OS)

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2) Board Level Laptop Maintenance

3) Components Level Laptop Maintenance

 Resistor, Capacitor, Transistor/MOSFET

4) Signal Level Laptop Mainboard Maintenance

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1.2: The Basic Knowledge You Must Know

a) The analogue and digital circuits.

I. Signal = When a laptop mainboard working, it will sends and

II. Timing Sequence = The meaning of Timing Sequence is as the

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2) Know how to testing electronic components

3) Know the structure of laptop

4) Know how to operation the testing equipment properly