DIGITAL ELECTRONICS 1, What type of logic circuit is represented by the figure shown below? : L, a) XOR b) XNOR c) AND 4) NAND 2. The output of a logic gate is ‘1° when all its inputs are a logic ‘0°. The gate is either a) NAND or EX-OR gate b) NOR or EX-NOR gate ©) OR or EX-NOR gate 4d) AND or EX-OR gate 3. In the given 4-to-1 multiplexer, =I then the output M is ci= O and co a) XO b) XI c) X2 d) X3 4. Which — statement is true asynchronous counters? a) Low frequency applications are limited because of internal propagation delays b) High frequency applications are limited because of internal propagation delays ©) Asynchronous counters do not have major drawbacks and are suitable for use in high and low frequency counting applications 4) Asynchronous counters do not have propagation delays, which limits their use in high frequency applications 5. Given that 1610 = 100,, find the value of x a) 2 regarding b) 3 4 @ 16 6. A single transistor can be used to build which of the following digital logic gates? a) AND gates b) OR gates ©) NOT gates d) NAND gates 7. The group of bits 11001 is serially shifted (right most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains__ a) O1110 b) 00001 ©) 00101 4) 00110 8, Number of 3 line to 8 line decoders required to select 1 out of 64 inputs is, a) 4 b) 8 09 @ 16 9. The terminal count of a typical modulus-10 binary counter is a) 0000 b) 1010 c) 1001 d) 1111 10. What is the minimum number of two inputs NAND gates required to perform the function of two inputs OR gate? a) 2 b) 3 4 4) 6 11, A 4-bit synchronous counter uses flip flops with a propagation delay of 15ns each, The ‘maximum time required for change of state is a) 15ns b) 30ns ©) 45ns d) 60ns 12. The gate that assumes the | state, if and only if the input does not take a 1 state is called___? a) AND gate b) NOT gate ©) NOR gate4) Both band 13. The term “hex inverter” refers to: a) An inverter that has six inputs b) Six inverters in a single logic device ©) An inverter that has a history of failure 4) A six-input symbolic logic device 14, When reading a Boolean expression, what does the word “NOT” indicate? a) The same as b) INVERSION ©) High d) Low 15. Counters can be used for the measurement of: a) Frequeney and time b) Time only ©) Frequency only 4d) None of these 16. In a SR flip-flop, when both $ & R is 1, then ofp: al b) 0 ©) Oscillates between 1 & 0 4) Is indeterminate or ambiguous 17.In order to separate channels in time division multiplexing receiver , itis necessary to use: a) AND gate b) Band pass filter ©) Differentiator 4) Integrator 18. 11001, 1001 and 111001 correspond to the 2°s, complement representation of which one of the following sets of number? a) 25,9 and 57 respectively b) -6,-6 and -6 respectively ©) -7,-1 and -7 respectively 4) -25, 9 and -57 respectively 19. Which of the following is used as a data selector? a) Encoder b) Decoder ©) Multiplexer 4d) Demultiplexer 20. The complement of AB+BC’+CD" is: a) A’CD+B'C+B'D b) A’C'+BC+AB'D" ©) AC+BC+ABD d) VCHB'C+AB'D 21. The following expression when simplified will become XY(X'YZ + X°Y"Z" + XY"Z) a0 DIGITAL ELECTRONICS 2 b) 1 ce) -l a) x 22.the R-S flip flop made of NOR gates, the forbidden input condition is: a) R-0,S=0 b) » S=0 c) R=0,S=1 d) R=1, $=1 23. One application of a digital multiplexer is to facilitate: a) Code conversion b) Parity checking c) Parallel to serial data conversion 4) Data generation 24. The fast carry or look ahead carry circuits found in most 4- bit parallel-adder ‘a) Increase ripple delay b) Adda I to complemented inputs ©) Reduce propagation delay 4) Determine sign and magnitude 25. The Boolean expression for the truth table shown is: A [8 [c |f o fo Jo To o [o [1 |o o [1 fo [e Ce ee 1 i fo [°° fo 1 [fe [1 [oe Se 7 To a) B(A+C\(4+C) b) BiA+€)(4+C) c) BlA+€)( A+0) d) BAC A+C) 26. To realize the equation AB + AC + BC using NAND gates only, the number of gates required will be: a) 5 b) 6 3 a4 27.In k-map reduction for 4- variable POS expression, the cell with address 0000 indica a) A+B+C+D b) A¥B+C+Dd) ABCD 28. To any flip-flop, which of the following can be given as an asynchronous input? a) Preset b) Clock ©) Enable d) Set 29. stepper motor that rotates in steps can be operated by the parallel output of: a) A twisted ring counter b) A ripple counter ©) Aring counter 4) A Johnson counter 30. There are a number of switches in a room. To keep a particular switch ON without affecting the other switches, the logic used is: a) NOT b) OR ©) EXOR d) AND 31. In the octal number system, after ‘7° the next characteris: a A b) 9 °) 8 @ 10 32, Flip-flop circuit is also known as: a) Bistable multivibrator b) Monostable multivibrator ©) Astable multivibrator @) IC 555 33. Which of the following circuits can be used (0 provide select input when MUX is used? a) Counter b) Decoder ©) Priority encoder 4) Shift register 34, Digital sound recording involves storage of| audio signals in the form of: a) digital image b) analogue image ©) photographic image 4) magnetism of tiny particles on magnetic material 35. For two input EX-OR gates, if one input is always Vee or high and the second input is A, then the output Y=? a) 0 b A a DIGITAL ELECTRONICS 3 a1 36. Full adder can be changed into a full subtractor circuit by adding one. a) OR gate b) AND gate ©) NOR gate 4d) Inverter 37.An AND gate followed by a NOT circuit makes ita a) NOR gate b) NAND gate ©) EX-OR gate d) EX-NOR gate 38._ is an un-weighted binary code in which two successive values differ only by 1 bit. a) Gray code b) ASCH code ©) EBCDIC code 4) Alphanumeric code Adding the two's complement of -I1 + (-2) will yield which two's complement answer? a) 1110 1101 39. b) 1111 1001 c) 1110011 d) 1110 1001 40. The output of an AND gate with three inputs, A.B, and C, is HIGH only when: c=0 41. The binary number 10101 is equal to the decimal number: a) 17 b) 45 ©) 2 ou 42. A logic gate with five inputs can have: a) 8 possible input combinations b) 16 possible input combinations ©) 32 possible input combination 4) 64 possible input combination 43. A half adder is constructed by: a) 2-input OR gate and EX-OR gate b) 2-input AND gate and EX-NOR gate ©) 2-input OR gate and EX-NOR gate ) 2-input AND gate and EX-OR gate 44,4 LK flip flop can be converted to a D flip flop by making: a) JSKb) J=K ©) J=K=I only d) J=K=0 only 45.Of the following logic familie DTL,ETL,CMOS and ECL, the fastest one is: a) DTL b) ETL ©) CMOS @) ECL 46. The following gates are universal: a) NAND, NOR and EXCLUSIVE-OR b) NAND and EXCLUSIVE-OR ©) NOR and EXCLUSIVE-OR d) NAND and NOR 47. In a J-K filp flop, when Jn = 0 and Kn=1, the output Qus1 Will have a value of: a1 b) 0 ©) Q d) Qo 48. In SISO shi given by: a) Nf b) Nf. ©) Nfe d) Nife 49, The 4-bit gray code for decimal number 5 is: a) OIL b) 1010 ©) 1110 @) 1000 50. Digital circuit can be made using only___ gates. a) AND b) NOT ©) OR @) NOR The voltage levels for a negative logic system a) Must necessarily be negative b) Could be negative or positive ©) Must necessarily be positive d) Must necessarily be either zero or -5V 52. The decimal equivalent of the hexadecimal number ES is a) 279 b) 229 ©) 327 d) 227 53. A +B = Y is the Boolean function for a) AND gate register, the time delay At is 51. DIGITAL ELECTRONICS 4 b) NAND gate ©) NOR gate ) OR gate 54, The following expression may be simplified as (AB + C+ DOYAC + BC + D) a) A+B4+C+D b) AB+BC ©) AB+BC+CD @) AC+BC+DC+ABD 55, How many flip-flops circuits are needed for a 4 counter? a) Two b) Three ©) Four @) Six 56, For converting a number in decimal number system to its binary equivalent, remainders are recorded after successive division of the number by a) 2 b) 40 8 @ 16 57. Decimal fraction 0.375 in binary form is a) 0.0011 b) 0.011 ©) 0.0111 ¢@) O11 58. A decade counter requires a) Two flip-flops b) Three flip-flops ¢) Four flip-flops 4) Ten flip-flops 59. According to Boolean algebra (1+A+B4C) be simplified as a) AsB+C b) ABC ©) 1+ABC a1 60. A byte is a group of a) 2bits b) 4 ©) 8bits d) 16 bits 61. Which of the following is termed as Universal gate logic? a) OR b) AND ©) NAND d) EX-OR62.A logic gate circuit that outputs a HIGH whenever one of its inputs is a HIGH a) NOT b) OR ©) AND d) EXOR 63. According to Boolean algebra (1+B)(1+C) can be simplified as a) (A¥B+C) b) ABC ol d) 1+ABC 64. A logic gate circuit that outputs a HIGH only when both of its inputs are low a) OR b) AND ©) NAND d) NOR 65. In a train of binary signals, 1 baud is equal to a) 1, bit/sec b) Tp bivsec ©) 1 bitisec 4d) 2bitsec 66. The number of flip flops req mod 17 counter is a4 b) 5 ©) 6 a7 67. The number of bits used to store a BCD digi a 8 b 4 ol a) 2 68. What is the decimal value for the binary number 101.0010? a) 125 b) 125 ©) 90.125 4) 9.125 69. Which of the following is correct for a D-type flip-flop? a) The Q output is either SET or RESET as soon as the D input goes HIGH or LOW b) The output complement follows the input when enabled ©) Only one of the inputs can be HIGH at a time (+A) DIGITAL ELECTRONICS 5 4) The output toggles if one of the inputs is held HIGH 70.Which of the following can be used for debouncing a switch? a) S-Rlatch b) Inverter ©) Integrator d) Pulse generator 71. What is one disadvantage of an S-R flip flop? a) Ithas no enable input b) Ithas a RACE condition ©) Ithas no clock input 4d) Ithas only a single output 72. The output of a logic gate is 1 when all its inputs are at logic 1. The gate is either a) aNAND ora NOR b) an AND oran OR ©) an OR or an XOR ) an AND ora NOR 73. The most suitable gate to check whether the number of 1's ina digital word is even or odd is a) XOR b) NAND ©) NOR @) AND 74. The given combinatorial circuit’ can be replaced with _— a) OR b) AND ©) NAND @) NOR 75. How many flip-flops are needed to divide the input frequency by 40? a) 4 b) 5 ©) 6 @ 40 76. A circuit which produces a high output when all its inputs are high are a) OR gate b) AND gate ©) NOT gate d) NAND gate 77. A shift register in which the output of the last flip flop is connected to the input of the first flip-flopa) Ripple counter b) Parallel counter c) Ring counter 4) BCD counter 78. Which is the simplified expression for the output corresponding to the given K map? As 2 7 ° apoya 2 a) AB b) BD ©) cD @ AC 79. 2°s complement of -7 is a) OL b) 1000 ©) HI @) 1001 80, 1° 52/4 a4 b) 5 ©) 6 a8 81. Any combinational circuit can be designed using only a) AND gates b) OR gates ©) XOR gates 4d) NOR gates In the figure shown, DO and D1 are digital inputs, S is a control input and Y is the output. When S=0, then Y=D0. When S=1, then Y=DI. The given combinational circuit is bo 22 _sflombinational] ¥ circuit >> Ts a) 2 input decoder b) 2 input multiplexer c) Full adder d) Shift register 83. The functional difference between an S-R flip flop and J-K flip flop is that a) JK flip flop is faster than SR flip flop b) JK flip flop has a feedback path c) JK flip flop accepts both inputs 1 ) JK flip flop does not require external clock 2, the base of the number system is 82. Or DIGITAL ELECTRONICS 6 84. Maximum number of flip flops required for a mod-12 ripple counter is a) 3 b) 4 c) 6 4) 12 85. Which of the following is decade counter? a) 1C 7493 b) IC. 7490 ©) IC 7491 @) 1C-7492 Assume that a 4-bit serial in/serial out shift register is initially clear. Bits are shifted in from left. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (right-most bit first) a) 1100 b) OO1L c) HAL 4) 0000 87. The voltage used to represent binary 1 in digital circuits is a) OV b) 45V o) SV 4) 25V 88.A Boolean function x’y’ + xy + xy is 86. @ xty 89. Let A = 1111 1010 and B = 0000 1010 be two 8-bit 2’s complement numbers. Their product in 2's complement is a) 11000100 b) 11000101 c) 1100 0102 d) 11000103 90. The characteristic equation of J-K flip flop is given as a) Qui =S'Qa + K'Qn 1b) Quei=J?'Qn + KQ’a ©) Qui=JQ'n + K'Q'n d) Quii=JQ'n + K’Qu 91. The number of select lines required in a single input and 256 output DEMUX is a) 8 b) 16 ©) 32d) 64 92. An OR gate has 4 inputs. One input is high and 93. 95, 96. 97. 98. 99, the other three are low. The output a) Is low b) Ishigh ©) Isalternately high and low ) May be high or low depending on relative magnitude of inputs ‘The output of a half adder is a) Sum b) Cary ©) Sum and carry ) None of above In which counter does the maximum frequency depend on the modulus? a) Synchronous b) Ripple ©) Both synchronous and ripple 4) Neither synchronous nor ripple A 4-bit ripple counter starts in 0000 states. When the counter reads 0010 the number of| clock pulses which have occurred is a) 2 b) 18 ©) 2or8 @) 2or34 In BCD addition, 0110 is required to be added to the sum for getting the correct result, if a) The sum of two BCD number is not a valid BCD number b) The sum of two BCD number is not a valid BCD number or a carry is produced ©) A carry is produced 4) None of the above is true Binary equivalent of BCD 0001 0010 0110 is a) 111110 b) 1111011 ¢) 1111000 @) WL How many two input NAND and NOR gate is required for implementation of half subtractor circuit? a) 5,4 b)4.4 5,5 4,4 The binary code of 21.125(decimal) is a) 10101.001 b) 10100.001 ©) 10101.010 100. 101. 102. 103. 104, 105. DIGITAL ELECTRONICS 7 4) 10100.111 The fan out of a 7400 NAND gate is, a) 2TTL b) STTL ©) 8TTL @) 10TTL If the state of a 3 bit counter at the clock time in is “110” then its state after three clock cycles will be a) 000 b) 11 ©) 001 @) 100 A symmetrical square wave of time period 100u1s can be obtained from a square wave of time period 10us by using a a) Divide by 5 circuit b) BCD counter ©) Divide by 5 circuit followed by a divide by 2 circuit 4) 4-bit binary counter ‘The output of the circuit shown will be of Ny ae | 5 iL t iL t a) 125Hz b) 250Hz c) 375 Hz @) 500 Hz ‘The number 149 in octal code is a) 154 b) 178 c) 254 d) 225 In full adder, there are a) Two binary number inputs and two outputs b) Three binary digit inputs and two binary outputs c) Three binary digit inputs and three binary digit outputs 4) NAND & OR gates sequential circuit, the outputs at any instant f time depends a) Only on the inputs present at that instant of time b) On past outputs as well as present inputs ©) Only on the past inputs d) Only on the present outputs107. 108, 109, 110. iu. 112. 113. How many FFs are required to build a binary counter circuit to count from 0 to 1023? a) 1 b) 6 ©) 10 @) 24 For a flip-flop formed from two NAND gates as shown in the given figure, the unusable state corresponds to of cy BL — a) X=0, ¥-0 b) X= ©) X=1L.Y=0 @ x How many flip flops circuits are needed to divide by 16? a) Two b) Four ©) Eight 4d) Sixteen ‘The Boolean expression AB is equivalent to a) AB b) A+B °) AFB d) ASB The basic sequential logic building block in which the output follows the data input as long as the enable input is active is a) IK flip flop b) T- flip flop ©) D-flip flop 4d) D-type latch Binary number (1101)2 when added to another binary number (101)2 yields a) 10011 b) 10010 ©) 11010 4) 11001 SHIFT left instruction causes all bits shifted one position to the left with right most bit set to zero. The effect is to a) Multiply by 2 b) Divide by 2 ©) SET the most significant bit 4) None of the above 14, 115. 116. 47. 118. 119. 120, 121. DIGITAL ELECTRONICS 8 ‘The output of the logic gate in figure is A ELD a) 0 b) 1 oa aa Number of 4:1 multiplexers required to design 16:1 multiplexers a) 5 b) 4 2 a1 The characteristic equation of the T-flip flop is given by (Qo a) TQ,’ +T’Qu b) 7 ©) T’Qn+TQn d) TQ, Which of the following is universal logic circuit? a) AND-OR b) Encoder ©) Multiplexer d) Nand gate Minimize Boolean £(0,1,2,3,8,10) a) A’B’ +AB'D’ b) BA’+B'D" ©) A’B’D+B'D’ @) ABD + ABD? A tristate logic device is a a) Special logic device which has three states “High” “Low” and low Impedance Special logic device which has “High” “Low” and “Always High” ©) Quantization Special logic device which has three “high” “low” and high impedance Precision special logic device which has three states “high” “low” and “always high” ‘A decade counter is also referred to as a) BCD counter b) BCD decade counter ©) Modulo-10 counter d) Ring counter What is the Boolean expression for the given logic diagram? expression ABCD b) three d)122, 123. 124, 125. 2to1 mux A a) ANANDB b) AXNORB ©) AXORB d) ANORB What does the following flip flop configuration does? a) Q=Lalways b) Q=Oalways ©) Acts as I-bit counter 4) Actas I-bit memory Determine the output frequency of the given circuit if the input CLK frequency is 1 MHz a] cux—prt @ Se G}—ourput 7 Qj a) 0.5 MHz b) 250 KHz ©) 4MHz @) 1 KHz Propagation delay of flip flops used for counter design largely affects the speed of operation of a) Asynchronous (ripple) counter b) Synchronous up counter ©) Synchronous down counter 4) Synchronous up down counter A code in which each decimal digit is represented by a group of 4 binary bits is a) BCD (binary coded decimal) b) Gray code ©) Excess 3 code 4) ASCII code 126, 127, 128. 129, 130. 131. 132. 133. DIGITAL ELECTRONICS 9 The maximum number of binary bits required to represent a digit of octal number is a) 3 b) 2 os a4 In which of the following gates, the output is high if and only if all inputs are high a) NOT b) XOR ©) OR d) AND The primary function of the multiplexing is a) To select one radio channel from a wide range of transmitted signals b) To match the frequency range of a signal to a particle channel ©) To reduce the bandwidth of a signal 4d) To allow a number of signals to make use of a single communication channel Hexadecimal equivalent of the decimal number 10101 is a) 15 b) 23565 ©) 1010 a) 2775 Logical expression (A+B) (A+C) is equal to a) AYB+C b) A¥B.C ) ABLAC @) ABC A bulb in a staircase has two switches, one switch being at the ground floor and the other one at the first floor. The bulb can be tumed ON and also can be turned OFF by one of the switches irrespective of the state of the other switch. The logic of switching of the bulb resembles a) AND gate b) OR gate ©) NAND gate 4) XOR gate The Boolean function Y=AB+CD is to be realized using only 2 input NAND gates the minimum number of gates required is a) 2 b) 3 o4 @ 5 The state of flip flop when Q=0 and Q”134, 136. 137, 138, 139, 140, 141. a) Reset b) Set ©) Trigger state d) Tristate ‘The one input RS flip flop is the___ a) T b) D oR d) Latch In a decoder, if the input lines are 4 then number of maximum output lines will be: a) 2 b) 16 0) 8 a4 Find the equivalent of AB+ A’+ B’. a) B b) 1 ©) AB aA In a multiplexer, if there are 4 input lines and 1 output line, then number of selection lines will be: a) 2 b) 3 co) 0 om Ina LK flip flop, when J = 1 and K = 1 then it will be considered as: a) No change b) Reset condition ©) Toggle condition 4) Set condition In ___ the flip flop output transition serves a source for triggering other flip-flops. a) Ripple counter b) Parallel adder register d) Serial adder Which one of the following gate is also known as equivalence gate? a) NOR b) AND ©) Ex-OR d) Ex-NOR Identify the following sequential component. 142. 143. 144, 145, 146. DIGITAL ELECTRONICS 10 a) JK flip flop b) Clocked flip flop ©) Master-slave flip flop d) R-S flip flop ‘The Boolean function AB + AC is equivalent to a) ABC + ABC’ + AB'C b) ABC+A’BC+B’C’ ©) A’BYC’ + ABC’ + A’BC d) AB+AC+BC The number of essential prime implicants for the Function Y = A’BC’D + A’BCD'+ AB’C’D + ABC’D’ is given by a) 2 b) 3 o1 a4 Two voltages given as -5 V and -1 V in positive logic conversion represent: a) ~5 Vis logic 1 in some circuits and 0 in the other b) -5 Vis logic 0 and -1 Vis logic 1 ©) -5 Vis logic | and -1 Vis logic 0 4) -5 Vis logic 0 in some circuits and 1 in the other ‘The expression for the truth table given below in POS form is given by: =]=|=|-|e}e]elel> =|=lelel—|-lelele| C 0 1 0 1 0 1 0 1 |---| lel= hal a) AB’C + ABC’ b) A’B’C +ABC ©) (AtBHC’)(A4B"+C’) d) (A+B+C’)(A’+B"+C’) Race around condition is associated with__. a) Sequential circuits with level triggered clock b) Combinational circuits147. 148, 149, 150, 151, 152, ©) Both sequential and combinational circuits 4) Sequential circuits When two asynchronous active low inputs PRESET and CLEAR are applied to a J-K flip flop, the output will be__. a) 1 b) Previous state ©) Undefined 40 Current hogging problem exists in a) Diode transistor logic b) Integrated injection logic ©). Resistor transistor logic 4) Direct-coupled transistor logic What function is performed by the block labeled X in the given figure? a) Analog-to-digital conversion b) Digital-to-analog conversion ©) Audio ON/OFF control 4) Power supply for the audio amplifier What is the maximum conversion time for an S-bit successive-approximation ADC with a clock frequency of 20 kHz? a) 12.8 ms b) 6.4:ms ©) 0.05 ms. d) 0.4 ms If the range of output voltage of a 6-bit DAC is 0 to 15 volts, what is the step voltage of the output? a) 0.117 volt/step b) 0.234 volt/step ©) 2.13 volts/step 4) 4.26 volts/step What is the purpose of a sample-and-hold circuit? a) To keep temporary memory b) To hold a voltage constant so an ADC has time to produce an output ©) To hold a voltage constant so a DAC has time to produce an output 4) To hold data after a multiplexer has selected an output bud ry Uigtalsond |_[ Processing H 153. 154, 155. 156. 157. 158. 159, 160. DIGITAL ELECTRONICS 11 An eight bit digital data 10101100 is fed to an ADC. The reference voltage is +10V. The analog output voltage will be: a) 1.05V b) 6.74V ©) 10.10V @) 5.15V Which of the following is used extensively where lowest power consumption is necessary? a) CMOS b) NMOS ) PMOS. d) Any of the above What is the voltage resolution of an 8-stage ladder network? a) Veer/128 b) Veer/256 ©) Veer /512 4) Veer /1024 A 4-bit R/2R digital to analog converter has a reference of 5 volts. What is the analog output for the input code 1010: a) 0.3125 V b) 3.125V ©) 0.78125 V @) -3.125V ‘The ASCII code is a a) 6-bit b) 7-bit ©) 8-bit @) 9-bit Letter *K’ in the ASCII code is equivalent to in the HEX code. a) 2FH b) 4BH ©) 50H ) 39H SAXX seri range of: a) =20°C to 170°C b) 0°C 0 70°C ©) -10°C to 70°C d) 55°C to 125°C What is the resolution of a digital to analog converter (DAC)? a) It is the comparison between the actual output of the converter and its expected output, code. TTL IC indicates @ temperature161. 162. 163, 164, 165. 166. 167. b) It is the deviation between the ideal straight-line output and the actual output of the converter. ©) Ibis the smallest analog output change that can occur as a result of an increment in the digital input 4) It is its ability to resolve between forward and reverse steps when sequenced over its entire range ‘The number of comparators needed in a 4-bit flash-type A/D converter is, a) 32 b) 15 °) 8 a4 Which of the following is the fastest? a) TIL b) ECL ) CMOS @ LSI ‘The fastest type of Analog to is a) Counter type b) Tracking type ©) Successive approximation type 4) Parallel comparator type An acceptable voltage range of logic 1 for TTL is a) 2t05V b) 0t08V ©) 0t015V d@) 3505V nd the resolution of a 10-bit AD converter for an input range of 10V? a) 97.7mV b) 9.77 mv ©) 0.977 mV @) 977 mV The conversion time of a 12-bit counter type ADC with 1 MHz clock frequeney to convert a full scale input is, a) 4.095 ys b) 4.095 ms ©) 4.095 s d) None ___ is not a grounding consideration for ADC and DAC in printed circuit boards. a) Analog side to analog ground b) Digital side to digital ground igital converter 168. 169. 170. qm. 172. 173. DIGITAL ELECTRONICS 12 ©) Use of separate power supply and connection of their ground leads to single point reference 4) Reduction of inductive loop area between power and return traces Find the FSV (full scale voltage) in a 6 bit R- 2R ladder D/A converter has a reference voltage of 6.5 V a) 64V b) 01 ©) 70V d) 80V The maximum counting range of a four stage counter using IC 74193 is a) 0t0 1023 b) 010.4093, ©) 010 65535 4) 0t0 131071 Sample and hold circuits in analog -to digital converters (ADCs) are designed to: a) Sample and hold the output of the binary counter during the conversion process Stabilize the comparator’s threshold voltage during the conversion process ©) Stabilize the input analog signal during the conversion process Sample and hold the D/A converter staircase waveform during the conversion process Settling time is normally defined as the time taken by DAC to settle withi a) LSB of its final value, when a change occurs in the input code 1/4 LSB of its final value, when a change occurs in the input code ©) 1/2 LSB of its final value, when a change b) occurs in the input code 4) 1 LSB of its final value, when a change occurs in the input code For a 4 bit DAC, the LSB is % of full scale a) 6.25 b) 0.625 °) 2 d) 25 The input voltage range of a 10 bit ADC is 10V. What is the weight of | LSB? a) 10mV b) (10/1024)V ©) (10/(2°-1))V174, 175. 176. 177. 178, 179. 180. 181. ) None of the above The number of comparators in a parallel conversion type 8-bit A to D converter is a) 8 b) 16 ©) 255 4) 127 An analog voltage is in the range of 0 to 8 V is divided in eight equal intervals for conversion to 3-bit digital output. ‘The maximum quantization error is a) OV b) OSV co) IV 4) 2V Which of the following IC logic families has the highest fan-out? a) TTL b) CMOS c) ECL d) Schotty TTL The resolution of a dual slope ADC can be increased by a) Increasing the reference voltage magnitude b) Improving the reference voltage accuracy ©) Increasing the clock frequency 4) Increasing the clock stabilit What should be the memory size of a digital storage oscilloscope to be able to record a transient of 10 seconds with a time resolution of 200 ps? a) 200K b) 50K ©) 2M 4d) None of the above Which of the following is fastest analog to digital converter? a) Successive approximation type b) Dual slope integration type ©) Flash type 4d) Ramp type In dual slope type of ADCs, An input hold time is a) Almost zero b) Higher than that of flash type ADCs ©) Longest 4) Allof the above Which is known as flash converter? a) Weighted resistor D/A converter b) Successive approximation A/D converter 182. 183. 184, 185. 186. 187, 188. DIGITAL ELECTRONICS 13 ©) Dual slope A/D converter 4) Parallel A/D converter The advantage of using a dual slope ADC in a digital voltmeter is that a) Its accuracy is high ) Its conversion time is small ©) It gives output in BCD format 4) Iedoes not require a comparator ‘As compared to TTL, CMOS logic has igh speed of operat igher power dissipation ©) Smaller physical size ) None of the above Which one of the following logic family has least propagation delay? a) BCL b) CMOS ©) BiCMOS @) CMOS and BiCMOS In TTL family, the Totem-pole circuit on the output is used to provide__. a) active pull up and active pull down b) inactive output state ©) active pull down 4d) active pull down The resolution of 4 bit counting ADC is 0.5 V. For an analog input 5.8 Volt, the output of ADC will be__. a) 1010 b) 1011 ©) 1100 @ mi ‘The given logic circuit represents __)>— —j>— —__1>—: a) 4bit binary to decimal converter b) 4 bit decimal to excess-3 code converter ©) 4 bit binary to Gray code converter d) 4 bit decimal to binary converter The range of numbers represented by an 8-bit ‘two's complement representation is, a) -128t0 +127189. 190, 191, 192, 193. b) 127 to +128 ©) -128 to +128 ) 0t0.255 In an 8 bit two's compliment number system, inversion of all 8 bits occurs during code transition a) from -127 to -128 b) from 0 to +127 ©) from +126 to +127 4d) from -1 100 A4x I Multiplexei ‘The output Z is —: shown in figure below a) ANORC b) BNORC ©) BXORC d) AXNORC ‘The initial content of the 4 bit Serial IN Parallel out right shift register is shown in figure is 1100. After four clock pulses are applied, the content of the shift register will be Gt a) O101 b) 1101 c) HAL d) 1110 The logical output of the combination of 3 gates shown in the figure represents a a ea y 8 e ta a) NAND b) XOR ©) AND 4d) OR If (110)x = (132)s, then x= a) 8 194, 195. 196. 197. 198. 199, 200. DIGITAL ELECTRONICS 14 b) 5 4 a9 Find X a) 0 b) AB ©) AB d) AB ‘The output of the circuit shown below is, a) A pulse train of duration 200 milli sec b) A pulse train of duration 100 milli sec ©) A pulse train of duration 400 milli sec ) A pulse train of duration 5 seconds The Gray code equivalent of binary 1100 is a) 1011 b) 1101 c) 1010 d) 1100 A Multiplexer has a) Multiple inputs and single output b) Single input and multiple outputs ©) Multiple inputs and multiple outputs d) Multiple inputs for storage of data A binary half adder a) Adds two binary digits and produces their sum and carry b) Adds half the sum to the carry ©) Adds two binary digits and carry from previous addition 4d) Adds two binary digits a half the speed Which family of the following Integrated circuits has the highest speed a) DTL b) ECL, ©) TIL @) CMOS ‘The most important feature of CMOS family of ICsis a) High speed201. 202. 203. 204. 205. 206. 207. 208. b) Small size ©) Low power consumption 4) Low input impedance What is the resolution of 8 bit A/D converter if| its full scale voltage is 10V a) 0.02 V b) 0.01V ©) 0.039 V @) 0.078 V What value of resistance is to be used in LSB of 4 bit weighted ladder D/A converter if MSB hhas 10 K ohms resistor a) 160K b) 80K ¢) 240K @) 100K The advantage of Totem pole output stage in TIL ICs is a) Low output impedance b) Can sink more current ©) Oscillations avoided 4) None of these Meaning of decoding is a) Binary addition b) Data transmission ©) Demultiplexing 4) Storage of binary information Flip flop cannot be called as a) Bistable multivibrator b) I bit memory unit ©) Latch 4) Combinational circuit In which of the following gate the output will be high when all the inputs are maintained at high level a) NOR b) AND ©) NAND d) EXOR Which of the following definition is true in the De Morgan’s theorem? a) Multiplication symbols are replaced by addition symbol b) Addition symbols multiptication symbol ©) Each of the terms are expressed in the complementary form 4) Allof the above 8421/BCD code for a decimal number 149 is a) 0001 0100 1001 are replaced by 209. 210. 2u1. 212. 213. 214, 215. 216. DIGITAL ELECTRONICS 15 b) 10010101 ©) 10101001 4d) None of the above Combination ci by a) Output depends upon the previous state & present state Output depends upon the input at that particular instant ©) Output depends upon the present state & the clock state Output does not depends upon the input at all A flip flop is defined as a) A bistable device with two complementary outputs b) Itis memory element ©) It will respond to input and it is a basic memory element 4d) Allof the above Four bit code is called a) Nibble b) Byte ©) Word d) Register The register is a a) Simplified unit of a subtractor b) Cascaded group of the flip-flop ©) Binary ripple counter 4d) Data selector The number of clock pulses arriving at the digital counter input should be in the form of a) Decimal b) Binary ©) Octal d) Hexadecimal In which of the counter the clock input is common to all flip flops a) Asynchronous counter b) Synchronous counter ©) Decade counter 4d) Down counter Full adder for two inputs can be developed with the help of a) Two half adder and an OR gate b) One half adder and two OR gate ©) An EXOR gate and an AND gate 4d) Two AND gates and an OR gate The important use of Gray code is for a a) Ripple counter are mainly characterized b) d217. 218. 219. 220. 221. 222. 223. 224. 225. b) Full adder c) Encoder d) Decoder In which of the code only bit changes at each time a) BCD b) Aiken code c) Excess 3 code d) Gray code In Johnson code for N bits, the maximum an be formed is given by an 4) None of the above Digital counter cannot be used as a) Clock b) Timer ©) Event counter 4) Multiplier Extremely low power dissipation and low cost per gate can be achieved in a) MOS ICs b) CMOS ICs ©) TTL ICs 4) ECLICs ASCII code is a a) Error detecting code b) Self correcting code ©) Analphanumeric code 4) A weighted code SN7410 IC is a a) Quad 2 input NAND gate b) Triple 3 input NAND gate ©) Dual M/S -K flip flop 4) None of these In digital circuits parallel operation is preferred because a) Itrequires less memory b) Circuitry is simple ¢)_ Ibis faster than series operation 4) None of the above reasons ‘The basic RS flip flops is a) A bistable multivibrator b) A monostable multivibrator ©) Anastable mutivibrator 4d) None of the above The equivalent decimal number for Gray code 1011 is 226. 221, 228. 229, 230. 231. 232. DIGITAL ELECTRONICS 16 a) 14 b) 13 ©) 41 @ 31 Which of the following circuits is known as half adder? a) AND circuit b) OR circuit ©) Exclusive OR circuit 4) None of these Large scale integrated (LSD) circuits usually contain a) Less than 10 gates b) 1010 100 gates ©) More than 100 gates d) More than 1000 gates Approximately how many numbers of gates are incorporated in SSI chip? a) 12 b) 100 ¢) Excess of 100 ) Excess of 1000 For realizing a decade counter using flip-flops the minimum number of flip flops required is a) 4 b) 5 6 @ 10 Which logic family is widely used in SSI & MSI application? a) ECL b) DTL, ©) TTL 4) None of these Toggle switches can be debounced using a) Astable multivibrator b)_ Shift register ©) RS flip flop )_ None of these In the circuit shown below. If R = 0 and $ = 1, the outputs Q and Q’ will be R Q Ss: ¢ a) Qand Q high b) Both low ©) Qhigh, Q’ low233. 234. 235. 236. 238. 239, 240. 4) Both high Schmitt trigger buffers are normally used as to digital logic circuit to achieve ©) Higher drive capability 4) Higher noise-immunity The key feature of CMOS inverter from the point of low power dissipation is that a) One of the devices is cut-off in either logic state b) It uses one each of MOS and NMOS devices ©) Silicon area required is low 4) Its high speed capability ‘The digital signal is the one which is a) Continuous in time & discrete in amplitude b) Discrete in time & continuous in amplitude ©) Discrete in both time and amplitude 4) Continuous in both time and amplitude Emitter coupled logic (ECL) is faster than TTL and CMOS logic circuits because a). Bipolar transistors are used b) Low voltage swings ¢) Transistors operate in unsaturated mode 4) Constant current source biasing is used MOS and CMOS logic families use: a) Saturated bipolar transistors b) Non-saturated bipolar transistors ©) MOS devices 4) Mixture of MOS and bipolar devices A clocked JK flip-flop differs from a clocked R'S flip-flop in the respect that: a) Ithas entirely different truth-table b) It avoids the ambiguity arising in the output condition from a 1, 1 input ©) Itis faster @) None A full adder for 1 binary operation, whether serial or parallel, typically consists of a) Two half adders b) Four half adders ©) Two half adders and an OR gate 4) Two half adders an AND gate A Register in a digital system is used: a) Foraddition of digital data b) For subtraction of digital data ©) For storage of digital data 4) For storage of permanent data 241. 242. 244, 245. 246. 247. 248. DIGITAL ELECTRONICS 17 To store an n-bit binary number in a register, we require: a) n flip-flops ©) 2n flip-flops d) [n+l] flip-flops ‘The Boolean expres to a) AC+BC+AC b) AC + BC+ BC + ABC c) BC+AC + BC + ACB d) ABC + ABC + ABC + ABC The logical expression y = equivalent to a) y= AB b)y=AB c) y=A+B dy=A+B ‘The number of distinct Boolean expres 4 variables is a) 16 b) 256 ©) 1024 «) 65536 ‘The number of Boolean function that can be generated by n variables is equal to: a) go"! by ©) 20' a2 An 8 bit successive approximation analog to digital converter has full scale reading of 2.55 V and its conversion time for an analog input of 1V is 20ps. The conversion time for a 2V input will be a) 10 ps b) 20 ys c) 40 ps d) 50 ps A 6 bit ladder D/A converter has input 101001. For 1 = 10 V and 0 = OV, The output is a) 4.23 b) 6.51 c) 5.52 d) 9.23 An n bit ADC using V as reference has a resolution of ay V/2 b) Va) AC + BC is equivalent A+KB is249. 250. 251. 252. 253. 254. 255. 256. 257. V/2-1 @)2Vin) The number of counter states which an 8 bit stair step A/D converter has to pass through before conversion is a1 b)8 ©) 255 4) 256 ‘The accuracy of A/D conversion is generally a) #1/2 LSB b) “LSB o) +5 4) None of the above Which converters uses integrating op-amp a) Parallel A/D converter b) Single slope A/D converter ) Dual slop A/D converter 4) Both (b) and (c) In.a4 bit D/A converter, The offset error is the output voltage when input digital voltage is a) HII b) 0000 ©) Either 1111 or 0000 4) None of the above D/A converters are generally a) Weighted resistor network ) Binary ladder network ©) Either (a) or (b) 4) Neither (a) nor (b) A. Darlington emitter follower circuit is sometimes used in the output stage of a TTL gate in order to a) Increase its to To. b) Reduce its Ton ©) Increase its speed of operation 4) Reduce power dissipation The noise margin of a TTL gate is about a) 0.2V b)04V ©) 06V 4) 08V In standard TTL the ‘totem pole stage refers to a) The multi-emitter input stage. ) The phase splitter ©) The output buffer 4) Open collector output stage Which is the most commonly used logic family a) ECL 258. 259, 260. 261. 262. 263. 264. 265. DIGITAL ELECTRONICS 18 b) TTL ) CMOS ) PMO Which logic family has the highest power dissipation per gate a) ECL b) TTL ) CMOS ) PMOS. ime delay of a TTL standard family is above a) 180 ns b) 50 ns ©) 18ns @) 3ns For wired AND connection use a) TTL gates with active pull up b) TTL gates with open collector c) TTL gates without active pull up and with open collector 4) Any one of the above Advanced low power Schottky is a part of a) ECL family b) CMOS family c) TTL family 4d) None of the above TTL uses a) Multi emitter transistor b) Multi collector transistor ) Multi base transistor 4) Multi emitter or multi collector transistor Logic families which are in use now a days are a) DTL & EMOS b) TTL, ECL, CMOS and RTL. ©) TTL, ECL & CMOS d) TTL, ECL, CMOS & DTL Without any additional circuitry an 8:1 MUX can be used to obtain a) Some but not all Boolean functions of 3 variables b) All function of 3 variables but none of 4 variables ©) All functions of 3 variables and some but not all of 4 variables 4) All functions of 4 variables The minimum number of 2-to-1 multiplexers required to realize a 4-to-1 multiplexer is a) b)2 03 dy4266. 267. 268. 269. 270. 27. 272. 273. 274, What are the minimum number of 2-to-1 multiplexers required to generate a 2- input AND gate and a 2-input Ex-OR gate? a) Land 2 b) Land 3 ©) land 1 ) 2and 2 Indicate which of the following logic gates can be used to realize all possible combinational Logic functions a) OR gates only b) NAND gates only ©) EX OR gates only 4) NOR gates only The range of signed decimal number that can be represented by 6-bit 1’s complement number is a) 3110431 b) -63 to +63 ©) -64 10 +63 ¢) 32031 ‘The 2’s complement representation of — 17 is a) 101110 b) 101111 ©) LLLL0 ¢) 110001 An equivalent 2°s complement representation of the 2°s complement number 1101 is a) 110100. b) 001101 ©) HOU @) 111101 11011 in gray code equal to binary a) (10010)2 b) (LLL) ©) (11100). 4) (10001)2 Decimal number 9 in Gray code is a) 1100 b) 1101 ©) 110 @) iti FFie when converted to 8421 BCD is a) 0000 0101 0101 b) 0010 0101 0101 ©) 1111 0101 0101 4) 10000101 0101 ‘The number of bits in EBCDIC is a) 12 b) 10 215. 276. 271. 278. 279, 280, 281. 282. DIGITAL ELECTRONICS 19 8 6 -8 is equal to signed binary number (8 bit) 1) 10001000 6) 00001000 ©) 1000000 d) 11000000 The resolution of annbit DAC with a maximum input of 5 V is 5 mV. The value of nis a) 8 b) 9 c) 10 di A device which converts BCD to seven segment is called a) Encoder b) Decoder ©) Multiplexer 4) none of these A decade counter skips a) binary states 1000 to 1111 ) binary states 0000 to 0011 c) binary states 1010 to 1111 d) binary states 1111 to higher BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment decoder/driver. ‘The segments which will lit up are a) a,b,d b) a,b,c c) all d) abcd Arring counter with 5 flip flops will have a) S states b) 10 states c) 32 states d) infinite states In the expression A + BC, the total number of minterms will be a) 2 b) 3 oc 4 as ‘The circuit in the given figure is283. 284. 285. 286. 287. 288. 289. ‘ met wo) ry * TP nq a) positive logic OR gate b) negative logic OR gate ©) negative logic AND gate 4) positive logic AND gate Which of the following is non-saturatin, a) TTL b) CMOS ©) ECL 4) Both (a) and (b) ‘The number of digits in octal system is, a) 8 b)7 39 @ 10 ‘The expression Y = [TM (0, 1, 3, 4) is a) POS b) SOP ©) Hybrid 4) None of these An 8 bit DAC has a full scale output of 2 mA and full scale error of * 0.5%. If input is 10000000 the range of outputs is a) 99410 1014 wA b) 990 to 1020 WA ©) 800 to 1200 wA 4) none of the above The greatest negative number which can be stored is 8 bit computer using 2's complement arithmetic is a) —256 b) ~ 128 c) ~255 d) -127 ALJK flip flop has tpg = 12 ns. The largest modulus of a ripple counter using these flip flops and operating at 10 MHZ is, a) 16 b) 64 ©) 128 d) 256 The basic storage element in a digital system is 290. 291. 292. 293. 294, 295. 296. DIGITAL ELECTRONICS 20 a) flip flop b) counter c) multiplexer 4) encoder In aripple counter, a) whenever a flip flop sets to 1, the next higher FF toggles b) whenever a flip flop sets to 0, the next higher FF remains unchanged ©) whenever a flip flop sets to 1, the next higher FF faces race condition d) whenever a flip flop sets to 0, the next higher FF faces race condition Which device has one input and many outputs? a) Multiplexer b) Demultiplexer ©) Counter ) Flip flop A carry look ahead adder is frequently used for addition because a) it costs less b) itis faster ©) itis more accurate d) isuses fewer gates A counter type A/D converter contains a 4 bit binary ladder and a counter driven by a 2 MHz clock. Then conversion time a) 7.5 sec b) 10 usec ©) 2ysec d) Spsec How many two input NAND and NOR gate is required for implementation of full subtractor circuit? a) 9,9 b)8.8 O7,7 8,9 In a 7 segment display, LEDs band c lit up. The decimal number displayed is a) 9 b)7 3 a1 In a BCD to 7 segment decoder the minimum and maximum number of outputs active at any time is a) 2and7 b) 3and7 ©) Land 6297. 298. 299, 300. 301. 302. 303. 304. 305. d) 3and6 A three state switch has three outputs. These are a) low, low and high b) low, high, high ©) low. floating, low 4) low, high, floating Maxterm designation for A +B +C is a) Mo b) Mi ©) Ms d) My 1's complement of 11100110 is a) 00011001 b) 10000001 ©) 00011010 4) 00000000 ‘The number of unused states in a 4 bit Johnson counter is a) 2 b) 4 8 @ 12 For a MOD-12 counter, the FF has a tpg = 60 ns The NAND gate has a tpq of 25 n sec. The maximum clock frequency is a) 3.774 MHz b) > 3.774 MHz ©) <3.774 MHz, @) 4.167 MHz A Karnaugh map with 4 variables has a) 2cells| b) 4 cells ©) 8 cells @) 16 cells, An 8 bit data is to be entered into a parallel in register. The number of clock pulses required is a) 8 b) 4 °) 2 gt Which of the following is error correcting code? a) EBCDIC b) Gray c) Hamming @) ASCII A universal shift register can shift a) from left to right 306. 307. 308. 309. 310. 311. 312. DIGITAL ELECTRONICS 21 b) from right to left ©) both from left to right and right to left )_none of the above AECFlis + ISACDi6 = a) C4TBBis b) C47BEis ©) A234Fis d) All Ile The Boolean expression for the circuit of the given figure a) A(F+(B+C)(D+B)} b) A[F+(B+©)(DE)] c) A+F+(B+C)(D+B)] @) AF +(BC) (DE)] A counter has N flip flops. The total number of states are a) N b) 2N o) @) 4N The dual of A + [B + (AQ)] + Dis a) A+[(B(A+C)]+D b) A[B+AC]D ©) A+[B(A+O)]D d) A[B(A+O)]D A divide by 78 counter can be obtained by a) 6 numbers of mod-13 counters b) 13 numbers of mod-6 counters ©) one mod-13 counter followed by mod-6 counter 4) 13 number of mod-13 counters The initial state of MOD-16 down counter is 0110, What state will it be after 37 clock pulses? a) Indeterminate b) O10 ©) 0101 4) 0001 The number of inputs and outputs of a full adder are a) 3 and 2 respectively b) 2 and 3 respectively ©) 4and 2 respectively d) 2and 4 respectively313. 314. 315. 316. 317. 318. 319. 320. 321. In a3 input NAND gate, the number of states in which output is 0 equals, a) 8 by 1 ©) 6 a5 In a mod-12 counter the input clock frequency is 10 kHz. The output frequency is a) 0.833 kHz b) L.OkHz ©) 0.91 kHz ) 0.77 kHz In digital circuits Schottky transistors are preferred over normal transistors because of their a) lower propagation delay b) lower power dissipation ) higher propagation delay 4d) higher power dissipation A flip flop is a a) combinational circuit b) memory element ©) arithmetic element d) memory or arithmetic element Quantization error occurs in a) D/A converter b) A/D converter ) both D/A and A/D converter d) neither D/A nor A/D converter Out of latch and flip flop, which has clock input? a) Latch only b) Flip flop only ©) Both latch and flip flop d) None A mod 4 counter will count a) from 0104 b) from 0103 ©) from any number n ton +4 ) none of the above Which of the following finds application in pocket calculators? a) TTL b) CMOS ©) ECL, d) Both (a) and (c) Decimal number 46 in excess 3 code = a) 1000 1001 b) O111 1001 c) OMI 322. 323. 324. 325. 326. 327. 328. DIGITAL ELECTRONICS 22 @) 1000 1111 A4 input AND gate is equivalent to a) 4 switches in parallel b) 2 switches in series and 2 in parallel ¢) three switches in parallel and one in series ) 4 switches in series The circuit of the given figure is a a) full adder b) full subtractor ©) shift register ) decade counter Avhalf adder adds a) 2bits b) 3 bits ©) 4 bits 4) 2or 3 bits In a 7 segment LED display, the minimum number of segments is activated when the input decimal number is a) 0 b) 1 ©) 2 @) 3 How many two input NAND and NOR gate is required for implementation of half adder circuit? a) 5.4 b)4.4 05,5 4.4 Parallel adder is a) sequential circuit b) combinational circuit ©) either sequential or combinational circuit ) none of the above An 8 bit binary number is to be entered into an 8 bit serial shift register. The number of clock pulses required is al b) 2 o4329. 330. 331. 332. 333. 334. d 8 ECL has high switching speed because the transistors are a) switching between cutoff and saturation regions b) switching between cutoff and active regions ©) switching between active and saturation regions 4) none of the above A current tracer responds to a). steady current only b) pulsating current only ©). both pulsating and steady current 4) none of the above A presettable counter with 4 flip flops can start counting from a) 0000 b) 1000 ©) any number from 0000 to 1000 4) any number from 0000 to 1111 Using the same flip flops a) a synchronous flip flop can operate at higher frequency than ripple counter b) a ripple counter can operate at higher frequency than synchronous counter ©) both ripple and synchronous counter can operate at the same frequency 4) can not determine DeMorgan's first equivalence of a) OR gate and Exclusive OR gate b) NOR gate and Bubbled AND gate ©) NOR gate and NAND gate d) NAND gate and NOT gate The function Y = AC + BD + EF is a) POS b) SOP ©) Hybrid 4) none of the above A 3 bit up-down counter can count from a) 000t0 111 b) 111 10.000, ©) 000 to 111 and also from 111 to 000 4) none of the above A3 input NAND gate is to be used as inverter. Which of the following will give better results? a) The two unused inputs are left open b) The two unused inputs are connected to 0 ©) The two unused inputs are connected to 1 4) None of the above theorem shows the 337. 338. 339. 340. 341. 342. 343. DIGITAL ELECTRONICS 23 A full subtractor has a total of a) 2 inputs b) 3 inputs ©) 4 inputs 4) 5 inputs ‘The inputs to a 3 bit binary adder are 1112 and 1102. The output will be a) 101 b) 1101 ©) 111 @) 1110 BCD number 1100111 = a) 66 b) 67 ©) 68 @d) 69 In the given figure, the flip flop is 10 2 Q@f-— a) negative edge triggered b) positive edge triggered ©) level triggered 4) either (a) or (©) How many two input NAND and NOR gate is required for implementation of full adder circuit? a) 9,9 b)8,8 7,7 8,9 A4 bit modulo 16 ripple counter uses JK flip- flops. If the propagation delay of each FF is 50 ns, The max. clock frequency that can be used is equal to a) 20 MHz b) 10 MHz ©) 5MHz @) 4MHz ‘As the number of flip flops are increased, the total propagation delay of a) ripple counter increases but that of, synchronous counter remains the same b) both ripple and synchronous counters increase ©) both ripple and remain the same ripple counter remains the same but that of synchronous counter increases synchronous counters d)344. 345. 346. 347. 348. 349. 350. For the ring oscillator shown in the figure, the propagation delay of each inverter is 100 pico sec. What is the fundamental frequency of the oscillator output _. pte te to te Yo a) 10MHz b) 100 MHz ¢) 1GHz @) 2GHz Which of the following is not a characteristic of a flip flop? a) Itis.a bistable device b) Ithas two outputs ©) It has two outputs are complement of each other 4) Ithas one input terminal Tf Ais 1011, A" is a) 1011 b) 0100 ©) 1100 @) 1010 A DAC has full scale output of 5 V. If accuracy is + 0.2% the maximum error for an output of 1 Vis a) SmV b) 10mv ©) 2mV @) 20mv Which one of the following can be used as parallel to series converter? a) Decoder b) Digital counter ©) Multiplexer ) Demultiplexer What will be conversion time of a successive approximation A/D converter which uses 2 MHz clock and 5 bit binary ladder containing 8 Vreference? a) 2.5 psec b) 25 usec ©) 3 usec d) 4 usec Three Mod-16 counters are connected in ade, The maximum counting range is a) 16 b) 256 ©) 4096 4) None of the above 351. 352. 353. 354. 355. 356. 357. DIGITAL ELECTRONICS 24 A 4 bit ripple counter starts in 0000 state, When the counter reads 0010 the number of clock pulses which have occurred is, a) 2 b) 18 ©) 2orl8 ) 2or 18 0r34 The inputs A, B, C of the given figure are applied to a 3 input NOR gate. The output is oes LSS a) HIGH from 4 to0 b) LOW from 0 to 4 c) HIGH from 0 to | and LOW from | to 4 d) LOW from 0 to 2 and HIGH from 2 to 4 The number of logic devices required in a Mod-16 synchronous counter are a) 4 b) 5 c) 6 a7 A 6 bit R-2Rladder D/A converter has a reference voltage of 6.5 V. It meets standard linearity then resolution in percent and volts. a) 3%,7V. b) 2%, 6.4V c) 0.1%, 1.57V d) 1.57%, 0.1V In a 4 bit ripple counter using flip flops with tpg = 40 ns, the maximum frequency can be a) 1.25 MHz b) 3.25 MHz ©) 6.25 MHz ) 12.5 MHz BCD equivalent of - 810 is a) 00110 b) 10110 ©) 11000 ) 01000 The device ‘one shot’ has a) two stable states b) one stable state c) either | or 2 stable states 4d) no stable state358. 359, 360. 361. 362. 363. 364. 365. If number of information bits is 4, the parity bits in Hamming code are located at bit positions from the LSB. a) 1,2,5 b) 1,24 ©) 1,23 d) 1,2 A certain JK FF has tpq = 12 n sec the largest MOD counter that can be constructed from these FF and still operate up to 10 MHz is a) Any b) 8 ©) 256 @) 10 Ina shift left register, shifting a bit by one bit means a) division by 2 b) multiplication by 2 ©) subtraction of 2 4) None of the above The series 54 H/74 H denotes a) Standard TTL b) High speed TTL ©) Low Power TTL 4) High Power TTL Logic analyser is a) a multichannel oscilloscope b) similar to logic pulser ©) similar to current tracer ) none of the above In the given figure shows a negative logic AND gate. If positive logic is used this gate is equivalent to Ang sl a) AND gate b) OR gate ©) NOR gate ) NAND gate A 10 bit D/A converter gives a maximum output of 10.23 V. The resolution is a) 10mV b) 20mV ©) 15mV @) 25mV As applied to a flip flop the word edge triggered’s means flop can change state when clock 366. 367. 368. 369. 370. 371. 372. 373. 374. DIGITAL ELECTRONICS 25 b) flip flop can change state when clock signal goes from LOW to HIGH only ©) flip flop can change state when clock signal goes from HIGH to LOW only 4) none of the above A NOR gate is a combination of a) OR gate and AND gate b) AND gate and NOT gate ©) OR gate and NOT gate 4) two NOT gates ‘The number of digits in hexadecimal system a) 15 b) 16 ©) 10 d) 8 For a Mod 64 parallel counter we need a) 6 flip flops b) 6 flip flops and 2 AND gates ©) 6 flip flops and 4 AND gates 4) none of the above 9s complement of 5610 is a) 4310 b) 840 ©) 6510 d) 5310 A 4 bit DAC gives an output of 4.5 V for input of 1001. If input is 0110, the output is a) 15V b) 20V °) 30V @) 45V 1012 x 1012=___ 10 a) 55 b) 45 ©) 35 a) 25 A combination circuit is one in which the output depends on a) input combination at that time ) input combination and previous output ©) input combination and previous input 4) present output and previous output A 14 pin NOT gate IC has NOT gates a) 8 b) 6 os a4 F's complement of (2BFD)hex is, a) E304 b) D403375. 316. 377. 378. 379. 380, 381. ©) D402 @) C403 Inputs A and B of the given figure are applied toa NAND gate. The output is LOW a) from 0106 b) from 0102 ©) from 0 to Land 2to3 d) from 1 to 2 and 3 to4 ‘The minterm designation for ABCD is a) ms b) mo ©) mu @) mis A mode-10 counter can divide the clock frequency by a factor of a) 10 b) 100 ©) 1000 4) 10000 A 4 bit synchronous counter has flip flops having propagation delay of 50. ns each and AND gates having propagation delay of 20 ns each. The maximum frequency of clock pulses can be a) 20 MHz b) 50 MHz ©) 14.3 MHz @) 5 MHz A counter has 4 flip flops. It divides the input frequency by a) 4 b) 2 8 @ 16 If number of information bits is 11, the number of parity bits in Hamming code is a) 5 b) 4 3 2 The number of digit 1 present in the binary representation of 3 x 512 +7x 64+5x8+3is 382. 383. 384, 385. 386. DIGITAL ELECTRONICS 26 a) 8 b) 9 ©) 10 oR A ripple counter has 4 bits and uses flip flops with propagation delay time of 25 ns. The maximum possible time for change of state will be a) 25ns b) 50 ns ©) 75 ns d) 100ns Ina JK Master slave flip flop a) both master and slave are positively clocked b) both master and slave are negatively clocked ©) master is positively clocked and slave is negatively clocked master is negatively clocked and slave is positively clocked ‘The counter which require maximum number of FF for a given mod counter is a) Ripple counter b) BCD counter ©) Ring counter 4) Programmed counter The circuit in the figure has two CMOS-NOR ircuit functions as a {> — oo) a) Flip-flop b) Schmitt trigger ©) Monostable multivibrator 4d) Astable multivibrator A 6 bit DAC uses binary weighted resistors. If MSB resistor is 20 k ohm, the value of LSB resistor is a) 20kohm b) 80kohm ©) 320k ohm ¢) 640k ohm387. 388. 389. 390. 391. 392. 393. ‘Symmetrical square wave of time period 100 ys can be obtained from square wave of time period 10 ys by using a) divide by 5 circuit b) divide by 2 circuit ©) divide by 5 circuit followed by divide by 2 circuit 4) BCD counter A 14 pin AND gate IC has gates. a) 8 b) 6 4 2 ‘The basic shift register operations are a) serial in - serial out b) serial in - parallel out ©) parallel in - serial out 4) all of the above A 4 Dit ripple counter is in 0000 state. The clock pulses are applied and then removed. The counter reads 0011. The number of clock pulses which have occurred are a) 3 b) 3orl9 ©) 3or 19 or 35 4) none of the above TTL logic is preferred to DRL logic because a) greater fan-out is possible ) greater logic levels are possible ) greater fan-in is possible 4) less power consumption is achieve AND In the circuit of the given figure, Vo = +5; 2ka ska %o a) 5V b) 3.1V o) 25V ad 0 Which of the following is true? a) SOP is a two level logic b) POS is a two level logi c) Both SOP and POS are two level logic 394. 395. 396. 398. 399, 400. 401. DIGITAL ELECTRONICS 27 ) Hybrid function is two level logic What is the normal range of analog input voltage? a) Otw1V b) Oto5V ©) 5to15V d) 15Vt030V ICs are a) Analog b) Digital ©) both analog and digital d) mostly analog In a JK flip flop toggle means a) setQ=1andQ=0 b) set Q=Oand Q=1 ©) change the output to the opposite state no change in output In a 4 bit weighted resistor D/A converter, resistor value corresponding to LSB is 32 k ohm. The resistor value corresponding to MSB is a) 32kohm b) 16kohm ©) 8kohm d) 4k ohm Full adder circuit can be implemented by a) Multiplexers b) Half adders ©) AND or OR gates ) Decoders Medium scale integration refers to ICs with a) more than 12 but less than 30 gates on the same chip b)_ more than 50 gates on the same chip ©) more than 20 but less than 100 gates on the same chip more than 12 but less than 100 gates on the same chip All digital circuits can be realised using only a) EX-OR gates b) Multiplexers ©) Half adders d) OR gates The code used to reduce the error due to ambiguity in reading of a binary optical encoder is a) Octal code b) Excess-3 code ©) gray code @) BCD code @d402. 403. 404. 405. 406. 407. 408. 409. 410. How many JK flip-flops are needed to make a bit shift register? a) 2 b) 4 ©) 6 a8 A 10 MHz square wave clocks 5 bit ripple counter. The frequency of the 3rd FF output is, a) 2MHz b) 1.25 MHz ©) 50MHz d) 615 kHz The radix of a hexadecimal system is a) 2 b) 3 8 d) 16 For checking the parity of a digital word, it is preferable to use a) AND gates b) NAND gates ©) EX-OR gates 4) NOR gates Among the digital IC families - ECL, TTL, and cMos a) ECL has the least propagation delay b) TTL has largest fan out ©) CMOS has the lowest noise margin 4) TTL has the lowest power consumption ‘The power dissipated per gate a) is constant at all frequencies bb) increases with frequency ©) decreases with frequency 4) may increase or decrease with frequency Gray code is used in devices which convert analog quantities to digital signal because it is a) more error free b) much simpler than binary code ©). superior to Excess-3 code d)_ absolutely error free A Schottky diode has a) no minority carriers and very low voltage drop in forward direction b) no minority carriers and very high voltage drop in forward direction ©) large number of minority carriers and very high voltage drop in forward direction 4d) large number of minority carriers and very Jow voltage drop in forward direction Boolean algebra obeys 411. 412. 413. 414. 415. 416. 417. 418. DIGITAL ELECTRONICS 28 a) commutative law b) associative law ©) distributive law @) commutative, associative and distr law The figure of merit for a logic family is a) gain band width product b) (propagation delay dissipation) ©) (an out) (power di 4) (noise margin) (power dissip: While obtaining minimal SOP expression a) all do not care terms are ignored ) all do not care terms are treated as 1 ©) all do not care terms are treated as 0 ) only such do not care terms which aid minimization are treated as 1 In 2's complement addition, the carry generated in the last stage is a) added to LSB b) neglected ©) added to bit next to MSB d) added to the bit next to LSB The abbreviation DTL stands for a) Digital Timing Logic b) Diode Transistor Logic ¢) Dynamic Transient Logic d) Delayed Tracking Logic Which one of the following is a D to A conversion technique? a) Successive approximation b) Weighted re ©) Dual slope d) Single slope When a binary adder is used as BCD adder, the sum is a) correct when it is <9 b) correct when itis > 9 ©) correct when it is < 16 4) none of these Two 16: 1 and one 2: 1 multiplexers can be connected to form a a) 16:1 multiplexer b) 32:1 multiplexer ©) 64:1 multiplexer d) 8:1 multiplexer In a ring counter for N clock pulses the scale for the counter is a) Nel b) N:2 time) (power419. 420. 421. 422. 423. 424. 425. 426. c) N:10 d) N: 100 Out of SR and JK flip flops, which is susceptible to race condition? a) SR b) JK c) Both SR and JK d) None of the above Which of the option is correct? a) A flip flop is used to store one bit of| information A transparent latch is aD type flip flop Both (a) and (b) Master slave flip flop is used to store two. bits of information D flip-flop can be used as a a) Differentiator b) divider circuit ) delay switch d) none Which device changes parallel data to serial data? a) Decoder b) Multiplexer c) Demultiplexer 4) Flip flop Race condition always arises in a) synchronous circuit b) asynchronous circuit c) combinational circuit 4) digital circuit ‘The expression Y (A, B, C) =m (1, 3, 5, 6) is to realized using a multiplexer. Then b) °) ad a) use 8 : | multiplexer and ground input lines 1,3,5,6 b) use 8 : 1 multiplexer and ground input lines 0,2,4,7 ¢) use 8: 1 multiplexer and ground input lines 0,1,2,3 4) use 8 : | multiplexer and ground input lines 4,5,6,7 Which of them has 10 inputs and 4 outputs? a) Decimal to BCD encoder b) BCD to decimal decoder ©) Octal to binary encoder 4) Allencoders When signed numbers are used in binary arithmetic, which of the following has unique representation for zero? a) Sign-magnitude 427. 428. 429. 430. 431. 432. DIGITAL ELECTRONICS 29 b) 1's complement ©) 2's complement 4) 9's complement The boolean expres given figure is for shaded area in the a) AB+AC b) ABC +AB C c) ABC + ABC d) None of these To convert JK flip flop to D flip flop a) connect D to both J and K b) connect D to J directly and D to K through inverter ©) connect D to K directly and D to J through inverter 4) connect D to K and leave J open Iftpis the pulse width, Atis the propagation delay, Tis period of pulse train then the following condition can avoid the race around condition a) t=At=T b) 2t)>At>T ©) = a) half adder b) full adder ©) half subtractor 4) full subtractor DeMorgan's second theorem is a) ALA b) A=A 458. 459. 460. 461. 462. 463. 464. 465. 466. DIGITAL ELECTRONICS 31 co) AFB=A.B d) AB=A +B DeMorgan’s first theorem is a) A.A=0 b) A=A co) A¥B=A.B d) AB=A +B InaD latch a) ahigh D sets the latch and low D resets it b) alow D sets the latch and high D resets it ©) race can occur 4) none of the above Which of the following flip-flop do not have race problem? a) T flip-flop b) D flip-flop ©) JK flip-flop ) Master-slave flip-flop Which device changes serial data to parallel data? a) Counter b) Multiplexer ©) Demultiplexer ) Flip flop C4010 is a a) inverting buffer b) non-inverting hex buffer ¢) NORIC @) NANDIC Which of the following is a self complementing code and weighted code both? a) 8421 code b) 2421 code ¢) Excess 3 code Gray code When two 4 bit parallel adders are scaded we get a) 4 bit parallel adder b) 8 bit parallel adder ©) 16 bit parallel adder 4d) none of the above Flash ADC is a) serial ADC b) parallel ADC ©) series-parallel ADC 4) successive approximation ADC A 12 bit ADC is operating with 1 1s clock period. Total conversion time is 14 jis. AD a) flash type b) counting type467. 468. 469. 470. an. 472. 473. 474. 475. ©) integrating type 4) successive approximation type Bitis a) smallest piece of electronic hardware b) drilling tool ©) an abbreviation for binary digit 4d) the smallest number The difference between combinational circuits is a) Combinational circuits store bits b) Combinational circuits have memory ©) Sequential circuits store bits 4) Sequential circuits have memory InJK flip flop toggle state exists if a) J=0,K=1 sequential and b) J=1,K c) J=0,K d) J=1,K=1 In a4 bit D/A converter, the offset error is the output voltage when input digital voltage is a) U1 b) 0000 ©) either 1111 or 0000 4) none of the above To convert SR latch to D tatch a) connect both $ and R to D b) connect D to S directly and D to R through inverter ©) connect D to R directly and D to S through inverter 4) connect $ to D and leave R open ‘Two numbers in excess-3 code are added and the result is less than 8. To get equivalent binary a) 0011 is subtracted b) 0011 is added ©) 0110 is subtracted 4) 0110 is added Ina sequential circuit the output at any instant depends on a). present inputs only ) past inputs only ©) past outputs only 4) past output and present input One XOR gate can work as a) one bit magnitude comparator b) two bit magnitude comparator ©) either (a) or (b) 4) neither (a) nor (b) Inan R-S latch, race condition occurs when 476. 477. 478. 479. 480. 481. 482. DIGITAL ELECTRONICS 32 a) Ris low and S is high b) Rand § are high ©) Rand $ are low igh and $ is low one of the following types of analog to digital convertors the conversion time is practically independent of the amplitude of the analog signal? a) The dual slope integrating type b). Successive approximation type ©) Counter ramp type d) Tracking type ‘A two-input OR gate is designed for positive logic. However, it is operated with negative logic. The resulting logic operation will then be a) OR b) AND ) NOR @) EX-OR A wwisted ring counter consisting of 4 FF will have a) 4 states b) 8 states ©) 2* states ) None of the above Which of these are correct? a) ECL has least propagation delay b) CMOS has highest noise margin ©) Both are correct, ) None of the above ‘The circuit of the given figure is 2p full adder ‘magnitude comparator parity detector ) none of the above Ina digital circuit, a clock is a a) crystal type b) multivibrator ©) flip-flop 4d) free running multivibrator The parity bit is a) always 1 b) always 0 ©) 10rd 4) none of the above483. 484. 485. 486. 487. 488. 489. 490. In which function is each term known as minterm? a) SOP b) POS ©) Hybrid 4) Both SOP and POS In the NMOS inverter a) the driver and active load are enhancement type b) driver is enhancement type and load depletion type ©) driver is depletion type and toad enhancement type 4) both driver and load are depletion type The logic represented by the abbreviation ECL is a) Emitter Coupled Logic b) Electron Carrier Logic ©) Encoding Clock Logic 4) Electrostatic Channel Logic ‘The output of the 74 series of TTL gates is taken from a BJT in a) totem pole configuration b) either totem configuration ©) common base configuration 4) common collector configuration The two outputs of RS flip-flop are a) always low b) always high ©) either low or high 4) always complementary High speed counter a) ring counter b) ripple counter ©). synchronous counter asynchronous counter ‘s complement representation of a 16 bit number (one sign bit and 15 magnitude bit) is FFFF. Its magnitude in decimal representation is a) 0 b) 1 ©) 32676 4) 65,535 A 4 ine to 16 line decoder has a) 16 inputs and 4 outputs b) 4 inputs and 16 outputs ©) either (a) or (b) and common collector pole or open collector 491. 492. 493. 494. 495. 496. 497. DIGITAL ELECTRONICS 33 ) neither (a) nor (b) Which of the following parameters is not specified for digital ICs? a) Gate dissipation b) Propagation delay ©) Noise margin d) Bandwidth The 54/74164 chip is an 8-bit serial-input- parallel-output shift register. The clock is 1 MHz, The time needed to shift a 8-bit binary number into the chip is a) lus b) 2us ©) 8s d) 16 ps Which of the following input is not possible in case of a SR flip-flop? a) S=0,R=0 b) S=0,R=1 0) S=1,R=0 @) S=1,R=1 In a JK flip flop output Qn = I and it does not change when clock pulse is applied. The possible combination of Jn and Knis (X denotes don't care) a) Xand0 b) Xand 1 ©) Oand X @) Land X The open wired circuit in the given figure works as a A sto Dp zy a a) EX-NOR gate b) AND gate ©) XOR gate 4) NOR gate In an R-S latch, to set the output to high a) Ris low and S is high b) Rand § are high ©) Rand $ are low 4) Rishigh and $ is low Which of the following can provide a digital signal? a) Slow change in the value of a resister b) Sine wave ©) Square wave498. 499. 500. 501. 502. 503. 504. 505. 506. 4) Gradual turning of a potentiometer In DTL the junction transistor serves as a) Inverter b) buffer amplifier ) both (a) and (b) 4) none of the above The converter whose conversion independent of number of bits is a) dual stope b) counter type ©) parallel conversion 4) successive approximation A register is a) a group is memories b) a group of devices that store digital data ©) achip used in computers 4) apure silica piece used in digital systems ‘A. binary ladder network D/A converter requires a) resistors of one value only b) resistors of many different values ©) resistors of two different values 4) none of the above A 0 to 6 counter consist of 3 flip-flop and a combinational circuit of 2 input gates. The combinational circuit consist of a) one AND gate b) one OR gate ©) one AND and One OR 4) two AND gate Which one of the following is D/A conversion technique? a) Successive approximation b) Weighted resistor ©) Dual slope 4d) Single slope In a4 bit parallel in parallel out shift register A =1,B=1,C=0,D= I. The data output after 3 clock pulses is a) 1101 b) 1001 ©) 0101 4) 0001 Data can be changed from spatial code to temporal code and vice-versa by using a) ADC and DAC b) shift Register ©) synchronous counter 4) timers In the CMOS inverter time is 507. 508. 509. 510. 511. 512. 513. DIGITAL ELECTRONICS 34 a) one transistor is N channel and the other P channel one is enhancement depletion type ©) both are N channel with one enhancement and the other depletion type None b) type and other @d) For NOR gate SR flip-flop, the ‘no change’ condition is If one wants to design a binary counter, preferred type of flip-flop is a) D-type b) SRtype ©) Latch @) IKtype In which function is each term known as maxterm? a) SOP b) Pos ©) Hybrid d) SOP and Hybrid A decade counter a) counts for ten days b) counts ten times faster than a binary counters ©) counts to 9 and reset on the next pulse 4d) reverts on the pulse after the tenth Which of the following is a weighted code? a) 8421 code b) Excess 3 code ©) Pure binary code 4d) Gray code Schottky clamping is resorted to in TTL gates a) to reduce propagation delay b) to increase noise margin ©) to increase packing density 4d) to increase fan out For the circuit shown in the figure, what is the frequency of the output Q?514. 516. 517. 518. 519. 520. 521. a) Twice the input clock frequency b) Half the input clock frequency ¢) Same as input clock frequency ) Inverse of the propagation delay of the FF Two voltages are -5 V and -10 V. In positive logic a) -5 Vis Land-10 Vis b) -10Vis 1 and-5 Vis0 ©) -5 Vis 1 in some circuits and 0 in others 4) -10 Vis 1 in some circuits and 0 in others ip-flop is commonly used as a) adelay switch b) adigital counter only ©) adigital counter and frequency divider 4) any of the above The basic circuit configuration for TTL resembles that of a a) AND gate b) NAND gate ©) NOR gate 4) OR gate Is Schottky TTL, Schottky diode is used primary to a) prevent saturation of the transistor b) saturate the transistor ©) act asa switch 4) act as a controlling switch A full adder is to be implemented using half| adders and OR gates. A 4 bit parallel adder without any initial carry requires a) 8 half adders and 4 OR gates b) 8 half adders and 3 OR gates ©) Thalf adders and 3 OR gates d) half adders and 4 OR gates ‘The main advantage of hexadecimal numbers is a) ease of conversion from hexadecimal to binary and vice-versa b) ease of conversion from hexadecimal to decimal and vice-versa ©) ease of conversion from gray code to binary and vice-versa 4) the use of numbers and alphabets A pulse train can be delayed by a finite number of clock periods by using a) serial in-serial out shift register ) parallel in serial out shift register ) serial in-parallel out shift register 4) parallel in parallel out shift register ‘The disadvantage of counter type ADC as compared to comparator ADC is that 522. 523. 524, 525. 526. 527. 528. DIGITAL ELECTRONICS 35 a) resolution is low b) conversion time is more ©) circuit is more complex d) stability is low ‘The dual of the function A(B'C + BC + BC’) is a) A+B%C)B+OB+C) b) A’ (BC’ + BC + B°C) c) C(B’A+CA+CA’) d) AB’C + ABC + ABC” Which of the following is equivalent to AND- OR realization? a) NAND-NOR b) NOR-NOR c) NOR-NAND @) NAND-NAND Which of the following is equivalent to OR- AND realization? a) NAND-NOR b) NOR-NOR c) NOR-NAND @) NAND-NAND An SR flip flop can be built using a) NOR gate only b) NAND gate only c) either NOR or NAND gates 4) neither NOR nor NAND gates In the given figure assume that initially Q = 1 and J = 1 with Clock Pulses being given, the subsequent states of Q will be using a) 2 inputs ANDs only b) 2/P XOR and 2 VP AND gate only ©) two 2 inputs NORs and One XNOR gate )_XOR gates and shift registers Which of the following is best suited for parity checking and parity genera a) AND, OR, NOT gates529, 530. 532. 533. 534, 535. 536. b) XOR, Exclusive NOR gate ©) NAND gates )_ NOR gates ‘The op amp is used in a) A/D converters b) D/A converters ©) both (a) and (b) d) shift registers, A decoder converts a) Non-coded information into coded form b) coded information into non-coded form. ©) HIGHs to LOWs d) LOWs to HIGHs A flip-flop has a) one stable state b) no stable states ©) two stable states d) none of the above The rise time is the time it takes a pulse to go from a) the base line to the maximum HIGH voltage b) 10% of the pulse amplitude to maximum HIGH voltage ©) the base line to 90% of the pulse amplitude 4) 10% of the pulse amplitude to 90% of the pulse amplitude ‘An encoder converts a) noncoded information into coded form b) coded information into noncoded form. ©) HIGHs to LOWs 4) LOWs to HIGHS A device used to display one or more digital signals so that they can be compared to expected timing diagrams for the signals is a: a) DMM b) spectrum analyzer ©) logic analyzer d) frequency counter The output of an exclusive-OR gate is HIGH if| a) all inputs are LOW b) all inputs are HIGH ©) the inputs are unequal 4) none of the above One advantage TTL has over CMOS is that TILis a) less expensive b) not sensitive to electrostatic discharge ©) faster the 537. 538. 540. 541. 542. 543. DIGITAL ELECTRONICS 36 d)_more widely available ‘A 2-input NOR gate is equivalent to a a) negative-OR gate b) negative-AND gate ©) negative-NAND gate d) none of the above The output of an exclusive-NOR gate is HIGH if a) the inputs are equal b) one input is HIGH, and the other input is Low ©) the inputs are unequal ) none of the above The basic types of programmable arrays are made up of __. a) AND gates b) OR gates c) NAND and NOR gates d) AND gates and OR gates ‘When grouping cells within a K-map, the cells must be combined in groups of ___. a) 2s b) 1,2,4,8,ete. ©) 4s d) 3s The NAND or NOR gates are referred to as "universal" gates because either: a) can be found in almost all digital circuits b) can be used to build all the other types of gates ©) are used in all countries of the world 4) were the first gates to be integrated Applying the distributive law to the expression, ‘A(B+C 4D) we get__. a) AB+AC+AD b) ABCD c) A+B+C+D @) AB+AC +AD Which statement Karnaugh map? a) A Kamaugh map can be used to replace Boolean rules. The Karnaugh map eliminates the need for using NAND and NOR gates. ©) Variable complements can be eliminated by using Kamaugh maps. Karnaugh maps provide a approach to__simplifying expressions. below best describes a b) @d cookbook Boolean544. 545. 546. 347. 548. 549. 550. 551. Which of the examples below expresses the commutative law of multiplication? a) A+B=B+A b) AB=B+A ) AB=BA d) AB=AxB Why, in most applications, are transistor switches used in place of relays? a) They consume less power. b) They are faster. ©) They are quieter and smaller. 4) all of the above What is the advantage of using serial data transmission over parallel data transmission? a) Itis slower. b) Only one pair of wires is required. ©) More people use it. 4) Itis faster. A TIL totem-pole circuit is designed so that the output transistors: a) are always on together b) provide phase splitting ©) provide voltage regulation 4d) are never on together The most commonly used system representing signed binary numbers is the: a) 2's-complement system. b) I's-complement system. ©) 10s-complement system. 4d) sign-magnitude system ‘The range of positive numbers when using an eight-bit two's-complement system is: a) 01064 for b) Oto 100 c) Oto 127 d) 0t0 256 ‘What distinguishes the look-ahead-carry adder? a) Itis slower than the ripple-carry adder. b) It is easier to implement logically than a full adder. ©) Itis faster than a ripple-carry adder. 4d) It requires advance knowledge of the final answer. On the fifth clock pulse, a 4-bit Johnson sequence is QO = 0, QI = 1, Q2= 1, and Q3= 1. On the sixth clock pulse, the sequence is 3) Q=1,Q=0,Q=0,Q)=0 b) Q=1,Qi=1,Q=1,Qs=0 ©) Q=0,Q1=0,Q=1,Q5=1 552. 553. 554, 555, 556. 557. 558. 559. DIGITAL ELECTRONICS 37 d) Q=0,Qi=0,@=0,Q=1 To operate correctly, starting a ring shift counter requires: clearing all the flip-flops 1 one flip-flop and clearing all ©) clearing one flip-flop and presetting all others )_presetting all the flip-flops In a 6-bit Johnson counter sequence there are a total of how many states, or bit patterns? a) 2 b) 6 °) 12 @) 24 ‘A modulus-12 ring counter requires a minimum of __. a) 10 flip-flops b) 12 flip-flops ©) 6 flip-flops 4) 2 flip-flops The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contai a) O10 b) 00001 ©) 00101 d) 00110 ‘What are the three output conditions of a three- state buffer? a) HIGH, LOW, float b) 1,0, float ©) both of the above 4) neither of the above What is the difference between a ring shift counter and a Johnson shift counter? a) There is no difference. b) Aring is faster. ©) The feedback is reversed. 4) The Johnson is faster Ring shift and Johnson counters are: a) Synchronous counters b) Aynchronous counters ©) True binary counters ) Synchronous and true binary counters The main advantage of the successive- approximation A/D converter over the counter- ramp A/D converter is its: a) more complex circuitry560. 561. 562. 563. 564. 565. 566. 567. b) less complex circuitry ©) longer conversion time 4d) shorter conversion time Which of the following is a complementing code? a) 8421 code b) Excess 3 codes ©) Pure binary code d) Gray code ‘The practical use of binary-weighted digital-to- analog converters is limited to: a) R/2R ladder D/A converters b) 4-bit D/A converters ©) 8-bit D/A converters 4) op-amp comparators ‘What is the major advantage of the R/2R ladder DAC as compared to a binary-weighted-input DAC? a) It has fewer parts for the same number of inputs. b) Itis much easier to analyze its operation, ©) Ituses only two different resistor values. d) The virtual ground is eliminated and the circuit is therefore easier to understand and troubleshoot. self- A simultaneous A/D converter is also known as a(n) AWD converter. a) Flash b) Synchronous ©) Comparator 4d) Asynchronous An open-drain gate is the CMOS counterpart of | a) Anopen-collector TTL gate b) A tristate TTL gate ©) A bipolar junction transistor 4) Anemitter-coupled logic gate Which logic family combines the advantages of CMOS and TTL? a) BiCMOS b) TTL/CMOS ©) ECL, @) TTL/MOS An open-collector output requires _. a) A pull-down resistor b) A pull-up resistor ©) No output resistor 4) An output resistor Most TTL logic used today is some form of| 568. 569. 570. 571. 572. 573. 574. 575. DIGITAL ELECTRONICS 38 a) Schottky TTL b) tristate TTL ©) low-power TTL ) open-collector TTL One output structure of a TTL gate is often referred to as a__. a) totem-pole arrangement ) diode arrangement ©) IBT arrangement 4) base, emitter, collector arrangement Which is not part of emitter-coupled logic (ECL) a) Differential amplifier b) Bias circuit ©) Emitter-follower circuit 4) Totem-pole circuit A Schmitt trigger: a) has two trip points b) isa zero crossing detector ©) has positive feedback 4) has two trip points and positive feedback Which of the following is the most widely used alphanumeric code for computer input and output? a) Gray b) ASCII ©) Parity @) EBCDIC Which of the following is an invalid BCD code? a) O01 b) 1101 ©) 0101 @) 1001 Which type of gate can be used to add two bits? a) Ex-OR b) Ex-NOR ©) Ex-NAND d) NOR The Ex-NOR is sometimes called the a) parity gate b) equality gate ©) inverted OR 4) parity gate or the equality gate How many 344ine-to-S-line decoders required for a I-of-32 decoder? a) 1 b) 2 o4 d) 8 are576. 377. 578. 579. 580. 581. 582. 583. How many 1-of-16 decoders are required for decoding a 7-bit binary number? a) 5 b) 6 7 d 8 Which gate is best used as a basic comparator? a) NOR b) OR ©) Exclusive-OR @) AND The input and output characteristics of a digital logic device used as a buffer is a) Low input impedance and low output impedance b) High input impedance and low output impedance ©) High input impedance and high output impedance 4) Low input impedance and high output impedance ABCD counter is a_. a) binary counter b) full-modulus counter ©) decade counter 4) divide-by-10 counter One application of a digital multiplexer is to facilitate: a) data generation ) serial-to-parallel conversion ©) parity checking 4) data selector How many inputs are required for a 1-of-16 decoder? a) 2 b) 4 8 @ 16 What is the range of invalid TTL output voltage? a) 0.0-04V b) 0424V ©) 245.0V 4) 0.0-5.0V Ten TTL loads per TTL driver is known as a) noise immunity b) fan-out ©) power dissipation 4) propagation delay 584, 585. 586. 587. 588. 589. 590. DIGITAL ELECTRONICS 39 The time needed for an output to change from the result of an input change is known as: a) noise immunity b) fan-out ©). propagation delay d) rise time Which logic family is characterized by a multi- emitter transistor on the input? a) ECL b) CMOS ©) TTL )_None of the above Which of the following logic families has the highest noise margin? a) TTL b) LS TTL ) CMOS d) HCMOS For a 4-bit DAC, the least significant bit (LSB) is a) 6.25% of full scale b) 0.625% of full scale ©) 12% of full scale ) 1.2% of full scale Which A/D conversion method has a fixed conversion time? a) Single-slope analog-to-digital converter b) Dual-slope analog-to-digital converter ©) Digital-ramp analog-to-digital converter ) Successive-approximation analog-to-digital converter ‘The output of this circuit is always__. +Vec cae sere bIpon ‘The symbols on this flip-flop device indicate D. Q ox Lo a) triggering takes place on the negative-going edge of the CLK pulseDIGITAL ELECTRONICS 40 b) triggering takes place on the positive-going ¥(1,2,6,7) and ¥ = [] (0.2.4) edge of the CLK pulse ¥ (1,4,5,6,7) and ¥ = [] (0.2.3) ©) triggering can take place anytime during the ¥ (1,2,5,6,7) and Y= [] (0.1.3) HIGH level of the CLK waveform ¥(1,2,4,5,6,7) and ¥ =] (0,2,3.4) 4) triggering can take place anytime during the] 595. (A.B) = [IM (0.1,2,3)_ represents (M is LOW level of the CLK waveform maxterm) 591. On a positive edge-triggered S-R flip-flop, the a) NOR gate outputs reflect the input condition when b) NAND gates ©) OR gates a)_the clock pulse is LOW 4) A situation where output is independent of b) the cloc! HIGH input ©) the clock pulse transitions from LOW to] 596. The minimum number of 2 to 1 multiplexers HIGH required to realize a 4 to | multiplexer is, 4) the clock pulse transitions from HIGH to a) 1 LOW b) 2 592. Which statement BEST describes the operation, 03 of a negative-edge-triggered D flip-flop? a4 a) The logic level at the D input is transferred] $97. The number of 4-line-to-16-line decoders to Qon NGT of CLK. required to make an 8-line-to-256-line decoder b) The Qoutput is ALWAYS identical to is the CLK input if the D input is HIGH. a) 16 ©) The Qoutput is ALWAYS identical to b) 17 the D input when CLK = PGT. ©) 32 d) The Qoutput is ALWAYS identical to d) 64 the D input 598. Reduce (A,B,C) = Em(0,2,3,4,5,6) 593. Karnaugh map is used to a) F=AB+AB+C a) Minimise the number of flip-flops in a b) F=AB+AB digital circuit c) F=AB+AB+C b) Minimise the number of gates only in a @ F=AB+AC+C digital circuit 599, Reduce f(A,B,C) = []M(0,2,3,4,5,6) ©) Minimise the number of gates and fan-in of a) F=AB+AB+C a digital circuit b) F=(A+B)(A4B)C G) Design gates ©) F=(A+B)(A4B) 594, The Boolean functions can be expressed in @) FoAB+AC+E canonical SOP (sum of products) POS (product of sums) form, For the functions, Y = A + BC, which are such two forms ANSWERS Ob [2b [03b [04b [05.c [06c [O7e [Oe [0%.c [106 tha [2d [3b [tab [isa [ted fia [Be [19 [20.4 ia [22d [23 [24c [25a [26a [27.b [28a [29.¢ [30.6 31d [32a [33a [34a [35.c [36d [37.6 [38a [3%¢ | 40.c 4c [ac [43d [44b [45d [46d [47.b [48d [49a [50.0 S1.b [52.b [53d [54d [55.c [56a [57.6 [58c [52d | 60.cDIGITAL ELECTRONICS 41 6c [2b [6c [otd [osc [66b [67.b [68d [69.a 7b [2b [73a [4c [75.c |76b [7c [Bc [79d Bid [82.b [83c [84d [85.b [86d [87c [88d [89a Ma [92b [93.c [9b [95.c |[96b [97a [9c [99.0 Tole [102.¢ |103.a [104d [105.6 [106.6 | 107.c | 108.a | 109.b Hid [1126 [i3a [tide [15a [Mea [irc [8b | 119. Rie [122¢ |[123.b [124.a [125.a [126a [127d [128d | 129.4 Bid [132.b [133.a [134.b | 135b [136.6 [137.4 | 138¢ | 139.4 iid [142.0 [143.b [144.b | 145.c [146.a | 147¢ [148d | 149.0 151.b [152.6 |153.b [154.a | 155.b [156.6 [157.b | 158.b | 159.d t61.b [162.6 [163d [164.a | 165.b [166.6 [167d | 168.a | 169.¢ Wie [172 |173.b [174.c [175.b_ [176.6 [177.¢ | 178.b | 179.¢ 181d [182.a [183.c [184.a_ [185.a_ [186.¢ | 187.c | 188.a_| 189.d 191.b [192 |[193.b [194d [195.a_ [196.¢ [197.4 | 198.a_| 199.b 201e [202.b | 203.a | 204.¢ | 205.d [206.6 [207d | 208.a_| 209.b 2a [212.6 [213.b [214.b [215.a_ [216c [217d [218 a [219.0 2ie [222.0 [223.c | 224.a [225.b | 226¢ | 227.c | 228a | 229.a 2Ble [232 d [234.a | 235.c [236.c [237 | 238.b | 239.¢ 24a [242d [243.0 [244d [245.0 [246.b | 247.b | 248. | 249.0 251.¢ [252.b [253.b | 254.c [255.0 | 256.c | 257.b | 258.a_ | 259.¢ 26l.c | 262.a | 263.c | 264.c | 265.c | 266.a | 267. bd | 268.a_| 269.b) 27a _[272.b [273.b [274.¢ [275.a_|276.c | 277.b | 278.¢ |279.¢ 281d _[282.b | 283.c | 284.a | 285.a | 286.a | 287.b | 288.d | 289.0 291-b [292.6 [293.a [294.0 [295d [296.4 [297d | 298.a | 299.0 30l-a [302d [303.d | 304.c [305.c [306.6 | 307.a | 308.¢ | 309.d Bid [312.4 [313.b [3i4.a [315.a | 316b [317.b | 318.b | 319.b 321.b [322d [323.b [324.0 [325.b |326.¢ [327.b | 328d | 329.b 331d [332.a_[333.b [334.b [335.c [336.c | 337.b | 338.b | 339.b 34a [342.c [343.a [344.c [345.d_ [346.a [347.b | 348.c | 349.0 351d [352.c [353.c [354d [355.c |356.c | 357.b | 358.b | 359.¢ 361.b [362.a | 363.b [364.0 [365.a | 366.c | 367.b | 368.c | 369.a 37a _[372.a [373.b [374.c [375.c [376d [377.a | 378.c |379.d 381.b | 382.d [383.c | 384.c [385.c [386d | 387.c | 388.c | 389.0 391.a [392.a [393.c | 394.b [395.c |396.¢ | 397.d | 398.a | 399.0 40l.c [402.6 | 403.b [404d [405.c | 406.a [407.6 [408.a [409.a [410.4 4b [412d [413.b [44d [415.0 [4tea [4i7.b | 4i8a [419.a | 420.¢ aac [422.6 [423.b [424.b [425.a | 426.c [427.c | 428b [429.c | 430.c a31.b [432.0 [433.b [434d [435.a [436.a [437.c | 438.a [439.c | 440.b daic [442.6 [443.c [444d [445.b [4d6c [447.a | 448b [449.c | 450.c 451.a [452.c [453d [454.b [455.c [456.a [457.c [458d [459.0 | 460.0 d6l.c [462.6 [463.b [464.b [465.b [406.0 [467.c [468d [469d | 470.b a7i.b [472.a [473.d [474.0 [475.b |476.b | 477.b | 478.b [479.c | 480.c a8i.d [482.c [483.a [484.b [485.a [4s6.b [487.0 [488.c [489.b | 490.b qoi.d [492.c [493.d [494.0 [495.c [496.a [497.c [498.c [499.c | 500.b SOlc [502d [503.b [504.a [505.b |506.a | 507.a | 508.a |50%.b | 510.cDIGITAL ELECTRONICS 42 Sia [512.4 .b [sida [5i5.c [516.6 [Si7.a_ [518¢ [5190 [520.0 S2i.b [522.4 jd [524.b [525.c [526.0 [527.b [528d [529.c | 530.b S3Le¢ [532.4 wa [534.0 [535.c [536.6 [537.b [538.a [530d | 540.b S41b [542.4 jd [5440 [545.0 [546.6 [547d [548.4 [549.¢ | 550.¢ S5L¢ | 552.b jc [554.b [555.c [556.c | 557.c [558.a [559d | 560.b 561.b | 562.¢ a |564.a | 565.a [566.6 | 567.a | 568.a [569d [570d S71.b | 572.b a |574.b | 575.c [576d [577.¢ |578.b [579.c¢ | 580.d 581.b | 582.b ub [584c [585.c [586d | 587.a [588d [589d [590.0 S9Lc [592.0 ib [594.b [595.0 [596.c [597.b | 598.a | 599.bWoR- pte + CoC, Xo ® Geo, qe roc Vbyo = \OOm Le lo! + 6x10° = l0+6 = Whov roork Ex— NOR ~ pate. CoE Xo # COG Hi EG Ky = tert oxn'soxe? ce initiok Stage (ee eer i:\av anil] — AR aa oe Pube 7 —> Ukr Second clock a Wo => After Ard clock Pulse WY [ofofifols } $c adttoder expansion Da matin —> Nex ™ me > a eth TH Oo oh No: of Dy decoder Se Pa x Nov of xg decoders = BH. a Qerc: Mod 10 Counter Initial Count — ©2000 Aeemingd Count - 10.04 lob meee =Free ecred = WR. oe wa Ja GrB) Bt) Era The texan propption A a . ee (ea) Be the Synicteemous a =a +5 +RE+B) (ay ® give, by. [ea = 4] = (fie +e) Cray : vy x BC+ Bo {4 ompti “9 of 4 Flingie.| Y= Fe>+ BE eon . . me Y&uivte & Change of nate na tae avast) Notes- Mvmt Propagation, Alay foe an No eit OSychvNOW Counter ip a by [ty = Mx] We Ginen arg Complement rramber!t ort MS), \ool and Woo, rsp Ge MSG of ah embeds axe LY Ahnet teams AU at. MEPAVE Yumbey 2S Complement ef \\o0) ——Semirlement_ af 001 TS Complement of \oo} = 00 Vo +i Oo14t fecom) ae (oy wintind, 4! ond \Nooy to Mree 100) Umilarly 1p 0) weytsenty Lat 20.8 Given | yenw xecscd Compernent of apove w OlP iN be She een of pos FaRRe F = G (aie) Ce) 26.0 a ABT AT 4 Ee —_ = AB +AC SEO = S 7s AB. AT Re Se, Tolok Mumbex of Nana gat wqubed _ Se3s.c we gave SSDs 4 | ay +OA =H | boa | 29.¢ | Wate =3), Binary quivalect o€ 3), ©2800 \\o) DS Compemerct | wil pie Henee of er00 \\0, Mat, + 1 eee Uivv00 ee ey, | Qdiory = THF on08y gt Fonte ange \o40 +4404) ore), =e, ah Possible inpuk Combinston = 2 s =P sae 44. 4 (S). = (C101), Gay Code fr (0101), Mse ts@ oO Oo \ rt [TT o-+n Oneal = WwW (101), = patente (0 fy S2-b Hexadecimal to decimak 5). = 14x yg! FOS = 2244s (sy, =@r4) | 54. 4 = (e2q) FQB+C HDL) Cacg ge +2) = ABC tage 4 PBD+ ACH Rey Po FADE Bed4 a0 [F = se Feet pe tac] St b PeCimak Reaction -ho Brany, 0-335 x0 = = O-4500 9 O-F80A2 = ese 1 Ossoxg = 4-0 4 L (o-345), = e-ouy,Rec Sg. c¢ RS Cok Pipe tinpn ace! ~tquised jo Comstuck a, ™od Counter 2 > 10 TNO wy decade Wenee bye 4! Em. of Elie Glogs, bab Refer Beg. — og Day vets s] 68.d Binaxg. te decimal Qoor. ool) = »,, Oye = Vero x ety onal 1x02 F Ox Fon Leith oye = 8toxony FOrOH Oe Ye = Gres) Geo *©0\o) A400 outed = F448 = fa VE WAND gore FS. Reker G ne — Sk M240 ve(me6] The Counter Must be Cout by 40, Komap nies eV Who cole }olAyo Ol}o o \]e Wee jo fi fs vole Le fife Fe CD 44. 4 Ge= ri), DS Complement of 014) wil! ge Ly, \S Compement = 1000 ao Voor > (eel), = LA Yoc (SD_ =) Tay UP) yn Sx + 2 : a. aeaicaa te Uxxtt 2x! to S*+2 =(noryq [x=6] 84. b Flit- Flog. WAUed Fy Moai Rime Counter ie ” my Aw Renee, (» = a So dnat ib bill) divide Kee Ree ges ON Neney baa86.4 Wem Number of Sele ck Nimes + Reker Grow : : Vaesg =i ae RG a ng a my as. 4 = SF + OeDy ee ee Sag Counter. The Counter Couvek | a+y : | wereet tant offer each ‘\4! | (F = Ky] [mre=ni Cleck pulte. | Mire , Counk? “tads oote ater 81.4 DARL 3A chockpubse. A ana of (oo Nos}, “T= WO Vonainder ia 4 >.se SIN pve, i Wag a — Soe ” 8 a = (ecco, = C60}, bet. j : 2 i [axe = Wooo oo | Ss we Lacy = Jo. @).= Gero a "| Serna Binary equivalent of ma, = J On + K On decimad O12 ik, rmaltip lyin by ‘2 UnttA ue Bet 1". and tsLoriting doom ah integer after Bch mubtipli cotton « Olesx2 = 0.25 8:2sy2 = 0.5) O-Sxo. ty lori2s), = (oor), lo. Divide (Vag nceersfully by & Umtth Ae quetiont B So! a FAR werminda i Saige Abo =o wwerminder BO 8 JZ =O Weonntes 2 oye zg (ua, = (22s), Seeona yntthed * ia —tEond_otthod + (44), = Voororoiy, T= tome | f= Idokye. Snare 42 octah ee leo pas VO Kya late ero You): = ars) 2 ES] fe 2010, £ loR.¢ ee ‘i Tet Count fom o to 1023, 103. a bt aa r 9. . x e Ke a ik te No: of FP ~equivey « - T~ Flip-Flop, Ue wait) Het hay on \o24. Bim fey, ob the oudput , Similely When we pags the inpat Syme ete om mbit Etpiop | 4. © Cremer tre output Leeg. Bait F= Bong i = RO +p.o| MR Reco > (0,152, 358,10) Kemap Loy BH ex pression, poe ive: ry | ool | mit | * Ane hp of ae From ane Teut BVO Configurasion, the of the Flip-tlop iw >=»! he Flip ttopa « wae ile be oh be Be repeating a fye WYO tan clay Pula. So iy Ba L-BIE Counter, (22. Given civeuit By output te Conmected ithe Se Cond, Frip- Flop. rie 1h A downy Comber . WR oO oie Counter. 80, Olp Time pewog RA Timer Hat oR ane Up Cle Merefre by 4 times So Frequency, tit be Aivided quency,