CMOS IC

LC877B00A
8-Bit Single Chip Microcontroller

Under-Development

LC877BC8A
8 bit Single Chip Microcontroller incorporating 128KB flash memory and 4096 byte RAM on chip
LC877BB2A
8 bit Single Chip Microcontroller incorporating 112KB flash memory and 4096 byte RAM on chip
LC877B96A
8 bit Single Chip Microcontroller incorporating 96KB flash memory and 4096 byte RAM on chip
LC877B80A
8 bit Single Chip Microcontroller incorporating 80KB flash memory and 4096 byte RAM on chip
LC877B78A
8 bit Single Chip Microcontroller incorporating 80KB flash memory and 2048 byte RAM on chip
LC877B72A
8 bit Single Chip Microcontroller incorporating 72KB flash memory and 2048 byte RAM on chip
LC877B64A
8 bit Single Chip Microcontroller incorporating 64KB flash memory and 2048 byte RAM on chip
LC877B56A
8 bit Single Chip Microcontroller incorporating 56KB flash memory and 2048 byte RAM on chip
LC877B48A
8 bit Single Chip Microcontroller incorporating 48KB flash memory and 1536 byte RAM on chip
LC877B40A
8 bit Single Chip Microcontroller incorporating 40KB flash memory and 1536 byte RAM on chip
LC877B32A
8 bit Single Chip Microcontroller incorporating 32KB flash memory and 1536 byte RAM on chip
LC877B24A
8 bit Single Chip Microcontroller incorporating 24KB flash memory and 1536 byte RAM on chip

Ver:1.30 November 30, 2004 Ogata 1/28

N3004
 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A
Overview
The LC877B00 series are an 8-bit single chip microcontroller with the following on-chip functional blocks :
- CPU: operable at a minimum bus cycle time of 83.3 ns Target speed
- 128K-24K bytes ROM
- On-chip RAM: 4096-1536 bytes
- LCD controller / driver
- two high performance 16 bit timer/counters (can be divided into 8 bit units)
- 16 bit timer / PWM (can be divided into two 8 bit timers)
- Four 8-bit timer with prescalers
- Timer for use as date / time clock
- Synchronous serial I/O port (with automatic block transmit / receive function)
- Asynchronous / synchronous serial I/O port
- 15-channel × 8-bit AD converter
- High-speed clock counter
- System clock divider
- Small signal detector
- 20-source 10-vectored interrupt system

All of the above functions are fabricated on a single chip.

Features
(1) ROM
-131072×8bits (LC877BC8A)
-114688×8bits (LC877BB2A)
-98304×8bits (LC877B96A)
-81920×8bits (LC877B80A/78A)
-73728×8bits (LC877B72A)
-65536×8bits (LC877B64A)
-57344×8bits (LC877B56A)
-49152×8bits (LC877B48A)
-40960×8bits (LC877B40A)
-32768×8bits (LC877B32A)
-24576×8bits (LC877B24A)

(2) Random Access Memory (RAM):

-4096 × 9 bits (LC877BC8A/B2A/96A80A)
-2048 × 9 bits (LC877B78A/72A/64A/56A)
-1536 × 9 bits (LC877B48A/40A/32A/24A)

(3) Minimum Bus Cycle Time: 83.3 ns (12 MHz) Target speed
Note: The bus cycle time indicates ROM read time.

(4) Minimum Instruction Cycle Time (tCYC) : 249.9 ns (12MHz) Target speed

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(5) Ports
- Input/output ports
Data direction programmable for each bit individually : 26 (P1n, P30-P35, P70-P73, P8n)
Data direction programmable in nibble units : 8 (P0n)
(When N-channel open drain output is selected, data can be input in bit units.)
- Input ports : 2 (XT1,XT2)
- LCD ports
Segment output : 48 (S00-S47)
Common output : 4 (COM0-COM3)
Bias terminals for LCD driver 3 (V1-V3)
Other functions
Input/output ports : 48(PAn,PBn,PCn,PDn,PEn,PFn)
Input ports : 7 (PLn)
- Oscillator pins : 2 (CF1,CF2)
- Reset pin : 1 ( RES )
- Power supply : 6 (VSS1-3,VDD1-3)

(6) LCD controller

- Seven display modes are available (static, 1/2, 1/3, 1/4 duty×1/2, 1/3 bias)
- Segment output and common output can be switched to general purpose input/output ports.

(7) Small signal detection (MIC signals etc)

- Counts pulses with the level which is greater than a preset value
- 2 bit counter

(8) Timers
- Timer 0: 16 bit timer / counter with capture register
Mode 0: 2 channel 8-bit timer with programmable 8 bit prescaler and 8 bit capture register
Mode 1: 8 bit timer with 8 bit programmable prescaler and 8 bit capture register + 8 bit
Counter with 8-bit capture register
Mode 2: 16 bit timer with 8 bit programmable prescaler and 16 bit capture register
Mode 3: 16 bit counter with 16 bit capture register
- Timer 1: PWM / 16 bit timer/ counter with toggle output function
Mode 0: 8-bit timer with 8-bit prescaler (and toggle output) + 8-bit timer / counter with 8-bit
prescaler (and toggle output)
Mode 1: 2 channel 8-bit PWM with 8-bit prescaler
Mode 2: 16-bit timer / counter with 8-bit prescaler (and toggle output) (Toggle output also
possible using the lower order 8 bits)
Mode 3: 16-bit timer with 8-bit prescaler (and toggle output) (The lower order 8 bits can be
used as PWM output)
- Timer 4: 8-bit timer with 6-bit prescaler
- Timer 5: 8-bit timer with 6-bit prescaler
- Timer 6: 8-bit timer with 6-bit prescaler (and toggle output)
- Timer 7: 8-bit timer with 6-bit prescaler (and toggle output)
- Base Timer
1) The clock signal can be selected from any of the following :
Sub-clock (32.768kHz crystal oscillator), system clock, and prescaler output from timer 0
2) Interrupts of five different time intervals are possible.

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 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A

(9) High-speed clock counter

- Countable up to 20 MHz clock (when using 10MHz main clock)
- Real time output

(10) Serial-interface
- SIO 0: 8 bit synchronous serial interface
1) LSB first / MSB first is selectable
2) Internal 8 bit baud-rate generator (fastest clock period 4 / 3 Tcyc)
3) Consecutive automatic data communication (1-256 bits)
- SIO 1: 8 bit asynchronous / synchronous serial interface
Mode 0: Synchronous 8 bit serial IO (2-wire or 3-wire, transmit clock 2–512 Tcyc)
Mode 1: Asynchronous serial IO (half duplex, 8 data bits, 1 stop bit, baud rate 8–2048Tcyc)
Mode 2: Bus mode 1 (start bit, 8 data bits, transmit clock 2–512 Tcyc)
Mode 3: Bus mode 2 (start detection, 8 data bits, stop detection)

(11) AD converter
-8 bits × 15 channels

(12) Remote control receiver circuit (connected to P73 / INT3 / T0IN terminal)
-Noise rejection function (noise rejection filter’s time constant can be selected from 1 / 32 / 128 Tcyc)

(13) Watchdog timer

- The watching time period is determined by an external RC.
- Watchdog timer can produce interrupt or system reset

(14) Interrupts: 20 sources, 10 vectors

1) Three priority (low, high and highest) multiple interrupts are supported. During interrupt handling,
an equal or lower priority interrupt request is postponed.
2) If interrupt requests to two or more vector addresses occur at once, the higher priority interrupt
takes precedence. In the case of equal priority levels, the vector with the lowest address takes
precedence.
No. Vector Selectable Level Interrupt signal
1 00003H X or L INT0
2 0000BH X or L INT1
3 00013H H or L INT2/T0L/INT4
4 0001BH H or L INT3/Base timer/INT5
5 00023H H or L T0H
6 0002BH H or L T1L/T1H
7 00033H H or L SIO0
8 0003BH H or L SIO1
9 00043H H or L ADC/MIC/T6/T7
10 0004BH H or L Port 0/T4/T5
• Priority Level: X>H>L
• For equal priority levels, vector with lowest address takes precedence.
(15) Subroutine stack levels: 2048 levels max. (LC877BC8A/B2A/96A/80A)
1024 levels max. (LC877B78A/72A/64A/56A)
768 levels max. (LC877B48A/40A/32A/24A)
Stack is located in RAM.

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 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A

(16) Multiplication and division

- 16 bit × 8 bit (executed in 5 cycles)
- 24 bit × 16 bit (12 cycles)
- 16 bit ÷ 8 bit (8 cycles)
- 24 bit ÷ 16 bit (12 cycles)

(17) Oscillation circuits

- On-chip RC oscillation for system clock use.
- CF oscillation for system clock use. (Rf built in, Rd external)
- Crystal oscillation low speed system clock use. (Rf built in, Rd external)
- On-chip frequency variable RC oscillation circuit for system clock use.

(18) System clock divider

- Low power consumption operation is available
- Minimum instruction cycle time (300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs can
be switched by program (when using 10MHz main clock)

(19) Standby function

- HALT mode
HALT mode is used to reduce power consumption. During the HALT mode, program execution
is stopped but peripheral circuits keep operating (some parts of serial transfer operation stop.)
1) Oscillation circuits are not stopped automatically.
2) Released by the system reset or interrupts.
-HOLD mode
HOLD mode is used to reduce power consumption. Program execution and peripheral circuits
are stopped.
1) CF, RC, X’tal and multi-frequency RC oscillation circuits stop automatically.
2) Released by any of the following conditions.
1. Low level input to the reset pin
2. Specified level input to one of INT0, INT1, INT2,INT4,INT5
3. Port 0 interrupt
-X’tal HOLD made
X’tal HOLD mode is used to reduce power consumption. Program execution is stopped.
All peripheral circuits except the base timer are stopped.
1) CF, RC and multi-frequency RC oscillation circuits stop automatically.
2) Crystal oscillator operation is kept in its state at HOLD mode inception.
3) Released by any of the following conditions
1. Low level input to the reset pin
2. Specified level input to one of INT0, INT1, INT2, INT4, INT5
3. Port 0 interrupt
4. Base-timer interrupt

(20) Package
- QIP100E
- TQFP100

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 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A

(21) Development tools

- Evaluation chip: LC87EV690
- Emulator: EVA62S + ECB876600D + SUB877400 + POD100QFP or POD100SQFP (Type B)
: ICE-B877300 + SUB877400 + POD100QFP or POD100SQFP (Type B)
- Flash ROM version: LC87F7BC8A

6/28
 VSS3

P05
P04
P03
P02
P01
P00
VDD3
COM3/PL3
COM2/PL2
COM1/PL1
COM0/PL0
V1/PL4/AN12
V2/PL5/AN13

P35/INT5/T1IN
P34/INT5/T1IN
P33/INT4/T1IN
P32/INT4/T1IN
P31/INT4/T1IN
P30/INT4/T1IN
Pin Assignment

99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
SANYO: QIP100E

100
P06 1 80 V3/PL6/AN14
P07 2 79 S47/PF7
P10/SO0 3 78 S46/PF6
P11/SI0/SB0 4 77 S45/PF5
P12/SCK0 5 76 S44/PF4
P13/SO1 6 75 S43/PF3
P14/SI1/SB1 7 74 S42/PF2
P15/SCK1 8 73 S41/PF1
P16/T1PWML 9 72 S40/PF0
P17/T1PWMH/BUZ 10 71 S39/PE7
RES 11 70 S38/PE6
XT1/AN10 12 69 S37/PE5
XT2/AN11 13 68 S36/PE4
VSS1 14 67 S35/PE3
CF1 15 66 S34/PE2
CF2 16 65 S33/PE1
VDD1 17 64 S32/PE0
P80/AN0 18 63 S31/PD7
P81/AN1 19 62 S30/PD6
P82/AN2 20 61 S29/PD5
P83/AN3 21 60 S28/PD4
P84/AN4 22 59 S27/PD3
P85/AN5 23 58 S26/PD2
P86/AN6 24 57 S25/PD1
P87/AN7/MICIN 25 56 S24/PD0
P70/INT0/T0LCP/AN8 26 55 VSS2
P71/INT1/T0HCP/AN9 27 54 VDD2
P72/INT2/T0IN 28 53 S23/PC7
P73/INT3/T0IN 29 52 S22/PC6
S0/PA0 30 51 S21/PC5
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A

S1PA1
S2/PA2
S3/PA3
S4/PA4
S5/PA5
S6/PA6
S7/PA7
S8/PB0
S9/PB1
S11/PB3
S10/PB2
S12/PB4
S13/PB5
S14/PB6
S15/PB7
S16/PC0
S17/PC1
S18/PC2
S19/PC3
S20/PC4

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 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A

SANYO: TQFP100

S31/PD7
S30/PD6
S29/PD5
S28/PD4
S27/PD3
S26/PD2
S25/PD1
S24/PD0
S39/PE7
S38/PE6
S37/PE5
S36/PE4
S35/PE3
S34/PE2
S33/PE1
S32/PE0
S46/PF6
S45/PF5
S44/PF4
S43/PF3
S42/PF2
S41/PF1
S40/PF0

VDD2
VSS2
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
S47/PF7 76 50 S23/PC7
V3/PL6/AN14 77 49 S22/PC6
V2/PL5/AN13 78 48 S21/PC5
V1/PL4/AN12 79 47 S20/PC4
COM0/PL0 80 46 S19/PC3
COM1/PL1 81 45 S18/PC2
COM2/PL2 82 44 S17/PC1
COM3/PL3 83 43 S16/PC0
P30/INT4/T1IN 84 42 S15/PB7
P31/INT4/T1IN 85 41 S14/PB6
VSS3 86 40 S13/PB5
VDD3 87 39 S12/PB4
P32/INT4/T1IN 88 38 S11/PB3
P33/INT4/T1IN 89 37 S10/PB2
P34/INT5/T1IN 90 36 S9/PB1
P35/INT5/T1IN 91 35 S8/PB0
P00 92 34 S7/PA7
P01 93 33 S6/PA6
P02 94 32 S5/PA5
P03 95 31 S4/PA4
P04 96 30 S3/PA3
P05 97 29 S2/PA2
P06 98 28 S1PA1
P07 99 27 S0/PA0
P10/SO0 100 26 P73/INT3/T0IN
10

12
13
14
15
16
17
18
19
20
21
22
23
24
25
11
1
2
3
4
5
6
7
8
9
P17/T1PWMH/BUZ
P16/T1PWML
P12/SCK0
P13/SO1

XT1/AN10
XT2/AN11

CF1
CF2
P11/SI0/SB0

P14/SI1/SB1
P15/SCK1

VDD1
P80/AN0
P81/AN1
P82/AN2
P83/AN3
P84/AN4
P85/AN5
P86/AN6

P70/INT0/T0LCP/AN8
P71/INT1/T0HCP/AN9
P72/INT2/T0IN
RES

VSS1

P87/AN7/MICIN

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 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A
System Block Diagram

Interrupt control
IR PLA

Stan-by control ROM

CF

Generator
RC

Clock
MRC
PC
X’tal

SIO0 Bus interface ACC

SIO１ Port 1 B register

Timer 0
Port 1 C register
(High speed clock counter)

Timer 1 Port 3
ALU

Base Timer Port 7

LCD Controller Port 8 PSW

INT0～5 ADC RAR

Noise Rejection Filter

Timer 4 Weak Signal Detector RAM

Timer 5 Timer 6 Stack pointer

ＩＦＬＧ Timer 7 Watch dog timer

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 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A
Pin Assignment

Pin name I/O Function Option

VSS1,VSS2,VSS3 - • Power supply (-) No
VDD1,VDD2 - • Power supply (+) No
VDD3
PORT0 I/O • 8bit input/output port Yes
P00 to P07 • Data direction programmable in nibble units
• Use of pull-up resistor can be specified in nibble units
• Input for HOLD release
• Input for port 0 interrupt
• Other functions
P05: clock output (system clock / can selected from sub clock)
P06: timer 6 toggle output P07: timer 7 toggle output
PORT1 I/O • 8bit input/output port Yes
P10 to P17 • Data direction programmable for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other pin functions
P10 SIO0 data output P11 SIO0 data input or bus input/output
P12 SIO0 clock input/output P13 SIO1 data output
P14 SIO1 data input or bus input/output
P15 SIO1 clock input/output P16: Timer 1 PWML output
P17: Timer 1 PWMH output/Buzzer output
PORT3 I/O • 6bit Input/output port Yes
P30 to P35 • Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
•Other functions
P30~p33:INT4 input/HOLD release input/timer1 event input
Timer0L capture input/Timer0H capture input
P34~P35 :INT5 input/HOLD release input/timer 1 event input
Timer0L capture input/Timer0H capture input
• Interrupt detection selection
Rising Falling Rising and falling H level L level
INT4 Yes Yes Yes No No
INT5 Yes Yes Yes No No
PORT7 I/O • 4bit Input/output port No
P70 to P73 • Data direction can be specified for each bit
• Use of pull-up resistor can be specified for each bit individually
• Other functions
P70: INT0 input/HOLD release input/Timer0L capture input/output for
watchdog timer
P71: INT1 input/HOLD release input/Timer0H capture input
P72: INT2 input/HOLD release input/timer 0 event input/Timer0L capture
input
P73: INT3 input(noise rejection filter attached)/timer 0 event
input/Timer0H capture input
AD input port: AN8(P70), AN9(P71)
• Interrupt detection selection
Rising Falling Rising and falling H level L level
INT0 Yes Yes No Yes Yes
INT1 Yes Yes No Yes Yes
INT2 Yes Yes Yes No No
INT3 Yes Yes Yes No No

Continued

10/28
 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A
Pin name I/O Function description Option
PORT8 I/O • 8bit Input/output port No
• Input/output can be specified for each bit individually
P80 to P87 • Other functions:
AD input port: AN0 to AN7
Small signal detector input port: MICIN(P87)
S0/PA0 to I/O • Segment output for LCD No
S7/PA7 • Can be used as general purpose input/output port (PA)
S8/PB0 to I/O • Segment output for LCD No
S15/PB7 • Can be used as general purpose input/output port (PB)
S16/PC0 to I/O • Segment output for LCD No
S23/PC7 • Can be used as general purpose input/output port (PC)
S24 /PD0 to I/O • Segment output for LCD No
S31/PD7 • Can be used as general purpose input/output port (PD)
S32/PE0 to I/O • Segment output for LCD No
S39/PE7 • Can be used as general purpose input/output port (PE)
S40/PF0 to I/O • Segment output for LCD No
S47/PF7 • Can be used as general purpose input/output port (PF)
COM0/PL0 I/O • Common output for LCD No
to • Can be used as general purpose input port (PL)
COM3/PL3
V1/PL4 to I/O • LCD output bias power supply No
V3/PL6 • Can be used as general purpose input port (PL)
• Other functions:
AD input ports: AN12 to AN14
RES I Reset terminal No
XT1 I • Input for 32.768kHz crystal oscillation No
• Other functions:
General purpose input port
AD input port: AN10
• When not in use, connect to VDD1
XT2 I/O • Output for 32.768kHz crystal oscillation No
• Other functions:
General purpose input port
AD input port: AN11
• When not in use, set to oscillation mode and leave open
CF1 I Input terminal for ceramic oscillator No
CF2 O Output terminal for ceramic oscillator No

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 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A
Port Configuration

Port form and pull-up resistor options are shown in the following table.
Port status can be read even when port is set to output mode.

Option applies
Terminal Options Output Form Pull-up resistor
to:
P00 to P07 each bit 1 CMOS Programmable
(Note 1)
2 Nch-open drain None

P10 to P17 each bit 1 CMOS Programmable

2 Nch-open drain Programmable

P30 to P35 each bit 1 CMOS Programmable

2 Nch-open drain None

P70 – None Nch-open drain Programmable

P71 to P73 – None CMOS Programmable

P80 to P87 – None Nch-open drain None

S0/PA0 to – None CMOS Programmable

S47/PF7
COM0/PL0 to – None Input only None
COM3/PL3
V1/PL4 to – None Input only None
V3/PL6
XT1 – None Input only None

XT2 – None Output for 32.768kHz crystal None

oscillation
Note 1 Attachment of Port0 programmable pull-up resistors is controllable in nibble units (P00-03, P04-07).

* Note 1: Connect as follows to reduce noise on VDD.

VSS1, VSS2 and VSS3 must be connected together and grounded.
*Note 2 : The power supply for the internal memory is VDD1 but it uses the VDD2 as the power supply for
ports. When the VDD2 is not backed up, the port level does not become “H” even if the port latch is
in the “H” level. Therefore, when the VDD2 is not backed up and the port latch is “H” level, the port
level is unstable in the HOLD mode, and the back up time becomes shorter because the through
current runs from VDD to GND in the input buffer.
If VDD2 is not backed up, output “L” by the program or pull the port to “L” by the external circuit
in the HOLD mode so that the port level becomes “L” level and unnecessary current consumption is
prevented.

LSI
VDD1
Power
supply Back-up capacitors *2
VDD2

VDD3

VSS1 VSS2 VSS3

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 LC877BC8A/B2A/96A/80A/78A/72A/64A/56A/48A/40A/32A/24A
1. Absolute maximum ratings / Ta=25°C and VSS1=VSS2=VSS3=0V

Limits
Parameter Symbol Pins Conditions
VDD min. typ. max. unit
Supply voltage VDDMAX VDD1,VDD2,VDD3 VDD1=VDD2=VDD3 -0.3 ～ +6.5 V
Supply voltage VLCD V1/PL4, V2/PL5, VDD1=VDD2=VDD3 -0.3 VDD
for LCD V3/PL6
Input voltage VI Port L -0.3 ～ VDD+0.3
XT1,XT2,CF1, RES
Input/Output VI0(1) • Port0, 1, 3, 7, 8 -0.3 ～ VDD+0.3
voltage • Port A, B, C, D, E, F
High Peak IOPH(1) Port 0,1,3 • CMOS output selected -10 mA
level output • Current at each pin
output current IOPH(2) Port 71,72,73 Current at each pin -3
current IOPH(3) Port A, B, C, D, E, F Current at each pin -5
Average IOMH(1) Port 0,1,32,33,34,35 • CMOS output selected -7.5
output • Current at each pin
current IOMH(2) Port 30,31 • CMOS output selected -5
(note 2) • Current at each pin
IOMH(3) Port 71,72,73 Current at each pin -3
IOMH(4) Port A,B,C,D,E,F Current at each pin -3
Total Σ IOAH(1) Port 0, 1, 32, 33, 34, Total of all pins -40
output 35
current Σ IOAH(2) Port 30, 31 Total of all pins -10
Σ IOAH(3) Port 7 Total of all pins -5
Σ IOAH(4) Port A, B, C Total of all pins -25
Σ IOAH(5) Port D, E, F Total of all pins -25
Low Peak IOPL(1) Port 0, 1, 32-35 Current at each pin 20
level output IOPL(2) Port 30, 31 Current at each pin 30
output current IOPL(3) Port 7,8 Current at each pin 10
current IOPL(4) Port A, B,C, D, E, F Current at each pin 10
Average IOML(1) Port 0,1,32-35 Current at each pin 15
output IOML(2) Port 30,31 Current at each pin 22.5
current IOML(3) Port 7,8 Current at each pin 7.5
(note 2) IOML(4) Port A,B,C,D,E,F Current at each pin 7.5
Total Σ IOAL(1) Port 0, 1, 32, 33, 34, Total of all pins 60
output 35
current Σ IOAL(2) Port 30, 31 Total of all pins 60
Σ IOAL(3) Port 7,8 Total of all pins 20
Σ IOAL(4) Port A,B,C Total of all pins 40
Σ IOAL(5) Port D, E, F Total of all pins 40
Maximum Pdmax QIP100E Ta = -20 to +70°C mW
power
TQFP100
consumption
Operating Topg -30 ～ +70 °C
temperature
range
Storage Tstg -55 ～ +125
temperature
range
(note 2) Average output current indicates average value for 100msec term.

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2. Recommended operating range / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V

Limits
Parameter Symbol Pins Conditions
VDD [V] min. typ. max. unit
Operating VDD(1) VDD1=VDD2=VDD3 0.245µs≤ t CYC≤ 2.8 5.5 V
supply voltage 200µs
range (note3) VDD(2) 0.294µs≤ t CYC≤ 2.5 5.5
200µs
VDD(3) 0.735µs≤ t CYC ≤ 2.2 5.5
200µs
Supply VHD VDD1 Keep RAM and 2.0 5.5
voltage register data in
range HOLD mode.
in Hold
mode
Input high VIH(1) • Port 0, 3, 8 Output disable 2.2～5.5 0.3VDD VDD
voltage • Port +0.7

A,B,C,D,E,F,L
VIH(2) • Port 1 Output disable 2.2～5.5 0.3VDD VDD
• Port 71,72,73 +0.7

• P70 port
input/interrupt
VIH(3) P87 small signal input Output disable 2.2～5.5 0.75VDD VDD
VIH(4) Port 70 Output disable 2.2～5.5 0.9VDD VDD
Watchdog timer
VIH(5) XT1, XT2, CF1, RES 2.2～5.5 0.75VDD VDD

Input low VIL(1) • Port 0, 3, 8 Output disable 4.0～5.5 VSS 0.15VDD+

0.4
voltage • Port A,B,C,D,E,F,L
VIL(2) 2.2～4.0 VSS 0.2VDD
VIL(3) • Port 1 Output disable 4.0～5.5 VSS 0.15VDD+
• Port 71,72,73 0.4
VIL(4) 2.2～4.0 VSS 0.2VDD
• P70 port
input/interrupt
VIL(5) Port 87 small signal Output disable 2.2～5.5 VSS 0.2VDD
input
VIL(6) Port 70 Output disable 2.2～5.5 VSS 0.8VDD
Watchdog timer -1.0

VIL(7) XT1,XT2,CF1, RES 2.8～5.5 VSS 0.25VDD

Operation t CYC 2.8～5.5 0.245 200 µs

cycle time 2.5～5.5 0.367 200
(note 4) 2.2～5.5 1.47 200
External FEXCF(1) CF1 • CF2 open 2.8～5.5 0.1 12 MHz
system clock • system clock
2.5～5.5 0.1 8
frequency divider :1/1
• external clock 2.2～5.5 0.1 2
DUTY = 50 ± 5%
• CF2 open 2.8～5.5 0.2 24
• system clock 2.5～5.5 0.2 16
divider :1/2 2.2～5.5 0.2 4
(Note 3) More than 4.5V power supply, on-board writable
(Note 4) Oscillation frequency and Operation cycle time(Tcyc) rerationship:1/1divide-3/Fmcf, 1/2divide-6/Fmcf

Continued

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Limits
Parameter Symbol Pins Conditions
VDD[V] min. typ. max. unit
Oscillation FmCF(1) CF1, CF2 12MHz ceramic resonator 2.8～5.5 12 MHz
frequency oscillation
range Refer to figure 1
(Note 5) FmCF(2) 8MHz ceramic resonator 2.5～5.5 8
oscillation
Refer to figure 1
FmCF(3) 4MHz ceramic resonator 2.2～5.5 4
oscillation
Refer to figure 1
FmRC RC oscillation 2.2～5.5 0.88 1.0 1.22

FmMRC Frequency variable RC 2.2～5.5 44 18 56

oscillation source oscillation

FsX’tal XT1, XT2 32.768kHz crystal resonator 2.2～5.5 32.768 kHz

oscillation
Refer to figure 2
(Note 5) The parts value of oscillation circuit is shown in table 1 and table 2.

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3. Electrical characteristics / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V

Limits
Parameter Symbol Pins Conditions
VDD[V] min. typ. max. unit
High level IIH(1) • Port 0, 1, 3, 7, 8 • Output disabled 2.2～5.5 1 µA
input • Port A, B, C, D, E, • Pull-up resister OFF.
current F, L • VIN=VDD
(including OFF state leak
current of the output Tr.)
IIH(2) RES VIN=VDD 2.2～5.5 1
IIH(3) XT1,XT2 When configured as an 2.2～5.5 1
input port. VIN=VDD
IIH(4) CF1 VIN=VDD 2.2～5.5 15
IIH(5) P87/AN7/MICIN VIN=V BIS +0.5V 4.5～5.5
small signal input (V BIS : Bias voltage) 3.0～5.5
2.2～5.5
Low level IIL(1) • Port 0, 1, 3, 7, 8 • Output disabled 2.2～5.5 -1
input • Port A, B, C, D, E, • Pull-up resister OFF.
current F, L • VIN=VSS
(including OFF state leak
current of the output Tr.)
IIL(2) RES VIN=VSS 2.2～5.5 -1
IIL(3) XT1,XT2 When configured as an 2.2～5.5 -1
input port. VIN=VSS
IIL(4) CF1 VIN=VSS 2.2～5.5 -15
IIL(5) P87/AN7/MICIN VIN=V BIS -0.5V 4.5～5.5 -15 -8.5 -4.2
small signal input (V BIS : Bias voltage) 3.0～5.5
2.2～5.5
High level VOH(1) Port 0, 1, 3: CMOS IOH=-1.0mA 4.5～5.5 VDD-1 V
output VOH(2) output option IOH=-0.4mA 3.0～5.5 VDD-0.4
voltage VOH(3) IOH=-0.2mA 2.2～5.5 VDD-0.4
VOH(4) Port 7 IOH=-0.4mA 3.0～5.5 VDD-0.4
VOH(5) IOH=-0.2mA 2.2～5.5 VDD-0.4
VOH(6) Port A, B, C, D, E, IOH=-1.0mA 4.5～5.5 VDD-1
VOH(7) F IOH=-0.4mA 3.0～5.5 VDD-0.4
VOH(8) IOH=-0.2mA 2.2～5.5 VDD-0.4
Low level VOL(1) Port 0, 1, 3 IOL=10mA 4.5～5.5 1.5
output VOL(2) IOL=1.6mA 3.0～5.5 0.4
VOL(3) IOL=1.0mA 2.2～5.5
VOL(4) Port 30, 31 IOL=30mA 2.2～5.5 1.5
voltage VOL(5) Port 7, 8 IOL=1.6mA 2.2～5.5 0.4
VOL(6) IOL=1.0mA 2.2～5.5 0.4
VOL(7) Port A, B, C, D, E, IOL=1.6mA 2.2～5.5 1.5
VOL(8) F IOL=1.0mA 2.2～5.5 0.4
LCD output VODLS S0–S47 I0=0mA 2.2～5.5 0 ± 0.2
voltage VLCD, 2/3VLCD, 1/3VLCD
regulation level output Refer to figure 8

VODLC COM0–COM3 I0=0mA 2.2～5.5 0 ± 0.2

VLCD, 2/3VLCD,1/2VLCD
1/3VLCD level output
Refer to figure 8

Continued

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Limits
Parameter Symbol Pins Conditions
VDD[V] min. typ. max. unit
LCD bias RLCD(1) Resistance per one Refer to figure 8 2.2～5.5 60 kΩ
resistor bias resistor
RLCD(2) • Resistance per Refer to figure 8 2.2～5.5 30
one bias resistor
• 1/2R mode
Resistance Rpu • Port 0, 1, 3, 7 VOH=0.9VDD 4.5～5.5 15 35 80 kΩ
of pull-up • Port A, B, C, D,
2.2～5.5 25 35 150
MOS Tr. E, F
Hysterisis VHIS(1) • Port 1, 7 2.2～5.5 0.1VDD V
voltage • RES
VHIS(2) Port 87 small 2.2～5.5 0.1VDD
signal input
Pin CP All pins • All Other Terminals 2.2～5.5 10 pF
capacitance Connected To VSS.
• F=1MHz
• T a =25°C
Input Vsen Port 87 small 2.2～5.5 0.12VDD Vpp
signal input
sensitivity

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4. Serial input/output characteristics / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V

Limits
Parameter Symbol Pins Conditions
VDD[V] min. typ. max. unit
Cycle time tSCK(1) SCK0(P12) Refer to figure 6 2.2–5.5 4/3 t CYC

Low level tSCKL(1) 2/3

pulse
width tSCKLA(1) 2/3

High level tSCKH(1) 2/3

Input clock

pulse
width tSCKHA(1) 3

Cycle time tSCK(2) SCK1(P15) Refer to figure 6 2.2–5.5 2

Low level tSCKL(2) 1

pulse
width
High level tSCKH(2) 1
pulse
Serial clock

width
Cycle time tSCK(3) SCK0(P12) • CMOS output 2.2–5.5 4/3
• Refer to figure 6
Low level tSCKL(3) 1/2 tSCK
pulse
width
tSCKLA(2) 3/4

High level tSCKH(3) 1/2

Output clock

pulse
width tSCKHA(2) 2

Cycle time tSCK(4) SCK1(P15) • CMOS output 2.2–5.5 2 tCYC

• Refer to figure 6
Low level tSCKL(4) 1/2 tSCK
pulse
width
High level tSCKH(4) 1/2
pulse
width
Data set-up t sDI SI0(P11), • Measured with 4.5–5.5 0.03 µs
Serial input

time SI1(P14), respect to SI0CLK

SB0(P11), 2.2–5.5 0.1
leading edge.
Data hold time t hDI SB1(P14) • Refer to figure 6 4.5–5.5 0.03
2.2–5.5 0.1
Output delay tdDO SO0(P10), • When Port is open 4.5–5.5 1/3
time SO1(P13), drain: tCYC
Serial output

SB0(011), Time delay form

SB1(P14) +0.05
SIOCLK trailing
edge to the SO data 2.2–5.5 1/3
change
tCYC
• Refer to figure 6
+0.25

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5. Pulse input conditions / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V

Limits
Parameter Symbol Pins Conditions
VDD[V] min. typ. max. unit
High/low tPIH(1) INT0(P70), • Condition that 2.2–5.5 1 t CYC
level pulse tPIL(1) INT1(P71), interrupt is accepted
width INT2(P72) • Condition that event
INT4(P30~P33) input to timer 0 is
INT5(P34~P35) accepted
tPIH(2) INT3(P73) • Condition that 2.2–5.5 2
tPIL(2) (Noise rejection ratio is interrupt is accepted
1/1.) • Condition that event
input to timer 0 is
accepted
tPIH(3) INT3(P73) • Condition that 2.2–5.5 64
tPIL(3) (Noise rejection ratio is interrupt is accepted
1/32.) • Condition that event
input to timer 0 is
accepted
tPIH(4) INT3(P73) • Condition that 2.2–5.5 256
tPIL(4) (Noise rejection ratio is interrupt is accepted
1/128.) • Condition that event
input to timer 0 is
accepted
tPIL(5) MICIN(P87) • Condition that signal 2.2–5.5 1
tPIL(5) is accepted to small
signal detection
counter.
tPIL(6) RES • Condition that reset is 2.2–5.5 200 µs
accepted

6. AD converter characteristics / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V

Limits
Parameter Symbol Pins Conditions
VDD[V] min. typ. max. unit
Resolution N AN0(P80) 3.0–5.5 8 bit
Absolute ET –AN7(P87) (Note6) 3.0–5.5 ±1.5 LSB
precision AN8(P70)
Conversion time ＴCAD AN9(P71) AD conversion 4.0–5.5 15.62 97.92 µs
AN10(XT1) time = 32 × tCYC (tCYC= (tCYC=
AN11(XT2) (ADCR2=0) 0.488µs) 3.06µs)
AN12(V1) (Note 7) 3.0–5.5 23.52 97.92
AN13(V2) (tCYC= (tCYC=
AN14(V3) 0.735µs) 3.06µs)
AD conversion 4.5–5.5 18.82 97.92
time = 64 × tCYC (tCYC= (tCYC=
(ADCR2=1) 0.294µs) 1.53µs)
(Note 7) 3.0–5.5 47.04 97.92
(tCYC= (tCYC=
0.735µs) 1.53µs)
Analog input VAIN 3.0–5.5 VSS VDD V
voltage range
Analog port input IAINH VAIN=VDD 3.0–5.5 1 µA
current IAINL VAIN=VSS 3.0–5.5 -1
(Note 6) Absolute precision does not include quantizing error (±1/2 LSB).
(Note 7) Conversion time means time from executing AD conversion instruction to loading complete digital
value to register.

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7. Current consumption characteristics / Ta=-30°C to +70°C, VSS1=VSS2=VSS3=0V

Limits
Parameter Symbol Pins Conditions
VDD[V] min. typ. max unit
Current IDDOP(1) VDD1= • FmCF=12MHz Ceramic 4.5–5.5 mA
consumption IDDOP(2) VDD2= resonator oscillation 2.8–4.5
during normal VDD3 • FsX’tal=32.768kHz crystal
operation oscillation
(Note 8) • System clock: CF 12MHz
oscillation
• Frequency variable RC
oscillation stopped
• Internal RC oscillation
stopped.
• Divider : 1/1
IDDOP(3) • FmCF=8MHz Ceramic 4.5–5.5
resonator oscillation
IDDOP(4) 2.5–4.5
• FsX’tal=32.768kHz crystal
oscillation
• System clock: CF 8MHz
oscillation
• Frequency variable RC
oscillation stopped
• Internal RC oscillation
stopped.
• Divider : 1/1
IDDOP(3) • FmCF=4MHz Ceramic 4.5–5.5
resonator oscillation
IDDOP(4) 2.2–4.5
• FsX’tal=32.768kHz crystal
oscillation
• System clock: CF 4MHz
oscillation
• Internal RC oscillation
stopped.
• Frequency variable RC
oscillation stopped
• Divider :1/1
IDDOP(5) • FmCF=0Hz (No oscillation) 4.5–5.5
• FsX’tal=32.768kHz crystal
IDDOP(6) 2.2–4.5
oscillation
• Frequency variable RC
oscillation stopped
• System clock: RC oscillation
• Divider :1/2
IDDOP(7) •FmCF=0Hz (No oscillation) 4.5-5.5
•FsX’tal=32.768kHz crystal
IDDOP(8) 2.2–4.5
oscillation
•Internal RC oscillation
stopped.
•System clock: 1MHz with
frequency variable RC
oscillation
•Divider :1/2
IDDOP(9) • FmCF=0Hz (No oscillation) 4.5–5.5 µA
• FsX’tal=32.768kHz crystal
IDDOP(10) 2.2–4.5
oscillation
• System clock: 32.768kHz
• Internal RC oscillation
stopped.
• Frequency variable RC
oscillation stopped
• Divider :1/2
Continued

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Limits
Parameter Symbol Pins Conditions
VDD[V] min. typ. max. unit
Current IDDHALT(1) VDD1= HALT mode 4.5–5.5 mA
consumption IDDHALT(2) VDD2= • FmCF=12MHz Ceramic 2.8–4.5
during HALT VDD3 resonator oscillation
mode • FsX’tal=32.768kHz crystal
(Note 8) oscillation
• System clock :
CF 12MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped
• Divider: 1/1
IDDHALT(3) HALT mode 4.5–5.5
• FmCF=8MHz Ceramic
IDDHALT(4) 2.5–4.5
resonator oscillation
• FsX’tal=32.768kHz crystal
oscillation
• System clock :
CF 8MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped
• Divider: 1/1
IDDHALT(3) HALT mode 4.5–5.5
• FmCF=4MHz Ceramic
IDDHALT(4) resonator oscillation 2.2–4.5
• FsX’tal=32.768kHz crystal
oscillation
• System clock :
CF 4MHz oscillation
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped
• Divider: 1/1
IDDHALT(5) HALT mode 4.5–5.5 µA
• FmCF=0Hz
IDDHALT(6) (Oscillation stop) 2.2–4.5
• FsX’tal=32.768kHz crystal
oscillation
• System clock :
RC oscillation
• Frequency variable RC
oscillation stopped
• Divider: 1/2
IDDHALT(7) HALT mode 4.5–5.5
•FmCF=0Hz (No oscillation)
IDDHALT(8) •FsX’tal=32.768kHz crystal 2.2–4.5
oscillation
•Internal RC oscillation stopped.
•System clock: 1MHz with
frequency variable RC
oscillation
•Divider :1/2
IDDHALT(9) HALT mode 4.5–5.5
• FmCF=0Hz
IDDHALT(10) (Oscillation stop) 2.2–4.5
• FsX’tal=32.768kHz crystal
oscillation
• System clock : 32.768kHz
• Internal RC oscillation stopped.
• Frequency variable RC
oscillation stopped
• Divider: 1/2
Continued

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Limits
Parameter Symbol Pins Conditions
VDD[V] min. typ. max. unit
Current IDDHOLD(1) VDD1 HOLD mode 4.5–5.5 µA
consumption • CF1=VDD or open
during HOLD mode (when using external
IDDHOLD(2) 2.2–4.5
clock)

Current IDDHOLD(3) VDD1 Date/time clock 4.5–5.5

consumption during HOLD mode
Date/time clock IDDHOLD(4) • CF1=VDD or open 2.2–4.5
HOLD mode (when using external
clock)
• FmX’tal=32.768kHz
crystal oscillation
(Note 8) The currents through the output transistors and the pull-up MOS transistors are ignored.

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Main system clock oscillation circuit characteristics
The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer

Table 1. Main system clock oscillation circuit characteristics using ceramic resonator
Oscillation
Operating
Circuit parameters stabilizing
supply voltage
Frequency Manufacturer Oscillator time Notes
range
C1 C2 Rd1 typ max
[V]
[pF] [pF] [Ω] [mS] [mS]

The oscillation stabilizing time is a period until the oscillation becomes stable after VDD becomes higher than
minimum operating voltage. (Refer to Figure4)

Subsystem clock oscillation circuit characteristics

The characteristics in the table bellow is based on the following conditions:
1. Use the standard evaluation board SANYO has provided.
2. Use the peripheral parts with indicated value externally.
3. The peripheral parts value is a recommended value of oscillator manufacturer

Table 2. Subsystem clock oscillation circuit characteristics using crystal oscillator

Oscillation
Operating
Circuit parameters stabilizing
supply
Frequency Manufacturer Oscillator time Notes
voltage range
C3 C4 Rf Rd2 typ max
[V]
[pF] [pF] [Ω] [Ω] [S] [S]

The oscillation stabilizing time is a period until the oscillation becomes stable after executing the instruction
which starts the sub-clock oscillation or after releasing the HOLD mode. (Refer to Figure4)

(Notes) • Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close
to
the oscillation pins as possible with the shortest possible pattern length.

CF1 CF2 XT1 XT2

Rd1 Rf
Rd2

C1 CF C2 C3 C4
X’tal

Figure 1 Ceramic oscillation circuit Figure 2 Crystal oscillation circuit

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0.5VDD

Figure 3 AC timing measurement point

VDD
Power VDD limit
l
0V

Reset time

RES

Internal RC
Resonator

tmsCF

CF1,CF2

tmsXtal

XT1,XT2

Operation mode Unfixed Reset Instruction execution mode

Reset time and oscillation stable time

Without HOLD
HOLD release HOLD release signal VALID
i l Release

Internal RC
Resonator

tmsCF

CF1,CF2

tmsXtal

XT1,XT2

Operation mode HOLD HALT

HOLD release signal and oscillation stable time

Figure 4 Oscillation stabilizing time

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VDD
(Note)
R RES
Select C RES and R RES value to assure that at
least 200µs reset time is generated after the VDD
becomes higher than the minimum operating
RES
voltage.
C RES

Figure 5 Reset circuit

SIOCLK

DATAIN DI0 DI1 DI2 DI3 DI4 DI5 DI6 DI7 DI8

DATAOUT DO0 DO1 DO2 DO3 DO4 DO5 DO6 DO7 DO8

Data RAM
transmission period
(only SIO0)
tSCK
tSCKL tSCKH

SIOCLK

tsDI thDI

DATAIN

tdDO

DATAOUT

Data RAM
tSCKLA tSCKHA transmission period
(only SIO0)
SIOCLK

tsDI thDI

DATAIN

tdDO

DATAOUT

Figure 6 Serial input / output wave form

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tPIL tPIH

Figure 7 Pulse input timing

VDD

SW : ON/OFF(programmable)

RLCD

RLCD
SW : ON(VLCD=VDD)
RLCD

RLCD

VLCD
RLCD

RLCD
2/3VLCD
RLCD
1/2VLCD
RLCD
1/3VLCD
RLCD

RLCD

GND

Figure 8 LCD bias resistor

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Note:

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This catalog provies information as of Nothing,Nothing. Specifications and information herein are subject to change
without notice

PS 28/28