Chapter 2

2.1. The proof is as follows: (x + y ) (x + z ) = xx + xz + xy + yz = x + xz + xy + yz = x(1 + z + y ) + yz = x 1 + yz = x + yz 2.2. The proof is as follows: (x + y ) (x + y ) = xx + xy + xy + yy = x + xy + xy + 0 = x(1 + y + y) = x1 = x 2.3. Proof using Venn diagrams:

x z x

x z x+y

x z yz

x z x+z

x z

x z

x+yz

( x + y)( x + z)

2-1

2.4. Proof of 15a using Venn diagrams:

xy

xy

xy

A similar proof is constructed for 15b. 2.5. Proof using Venn diagrams:

x1 x3

x2

x1 x3

x2

x1 + x2 + x3 x1 x3 x1 + x2 + x3 x1 x3 ( x1 + x2 + x3 ) ( x1 + x2 + x3 ) x2 x2

x1 + x2

2-2

2.6. A possible approach for determining whether or not the expressions are valid is to try to manipulate the left and right sides of an expression into the same form, using the theorems and properties presented in section 2.5. While this may seem simple, it is an awkward approach, because it is not obvious what target form one should try to reach. A much simpler approach is to construct a truth table for each side of an expression. If the truth tables are identical, then the expression is valid. Using this approach, we can show that the answers are: (a) Yes (b) Yes (c) No

2.7. Timing diagram of the waveforms that can be observed on all wires of the circuit:

x2

C f

x3 x1

B D

x1 x2 x3 A B C D f

2-3

2.8. Timing diagram of the waveforms that can be observed on all wires of the circuit:
x1 x3 A D x2 B C f

x1 x2 x3 A B C D f

2.9. Starting with the canonical sum-of-products for f get f = x 1 x2 x3 + x 1 x2 x3 + x 1 x2 x3 + x 1 x 2 x 3 + x 1 x2 x3 + x 1 x2 x 3 + x 1 x2 x3 = x 1 (x 2 x 3 + x 2 x 3 + x 2 x 3 + x 2 x 3 ) + x 2 (x 1 x 3 + x 1 x 3 + x 1 x 3 + x 1 x 3 ) +x3 (x1 x2 + x1 x2 + x1 x2 + x1 x2 ) = x1 (x2 (x3 + x3 ) + x2 (x3 + x3 )) + x2 (x1 (x3 + x3 ) + x1 (x3 + x3 )) +x3 (x1 (x2 + x2 ) + x1 (x2 + x2 )) = x1 (x2 1 + x2 1) + x2 (x1 1 + x1 1) + x3 (x1 1 + x1 1) = x1 (x2 + x2 ) + x2 (x1 + x1 ) + x3 (x1 + x1 ) = x1 1 + x 2 1 + x 3 1 = x1 + x2 + x3 2.10. Starting with the canonical product-of-sums for f can derive: f = (x1 + x2 + x3 )(x1 + x2 + x3 )(x1 + x2 + x3 )(x1 + x2 + x3 ) (x1 + x2 + x3 )(x1 + x2 + x3 )(x1 + x2 + x3 ) = ((x1 + x2 + x3 )(x1 + x2 + x3 ))((x1 + x2 + x3 )(x1 + x2 + x3 )) ((x1 + x2 + x3 )(x1 + x2 + x3 ))((x1 + x2 + x3 )(x1 + x2 + x3 )) = (x1 + x2 + x3 x3 )(x1 + x2 + x3 x3 ) (x1 + x2 + x3 x3 )(x1 + x2 x2 + x3 ) = (x1 + x2 )(x1 + x2 )(x1 + x2 )(x1 + x3 ) 2-4

= (x1 + x2 x2 )(x1 + x2 x3 ) = x 1 (x 1 + x 2 x 3 ) = x 1 x1 + x 1 x2 x3 = x 1 x2 x3 2.11. Derivation of the minimum sum-of-products expression: f = x 1 x3 + x 1 x 2 + x 1 x2 x3 + x 1 x2 x 3 = x1 (x2 + x2 )x3 + x1 x2 (x3 + x3 ) + x1 x2 x3 + x1 x2 x3 = x 1 x 2 x3 + x 1 x2 x3 + x 1 x 2 x 3 + x 1 x2 x3 + x 1 x2 x 3 = x1 x3 + (x1 + x1 )x2 x3 + (x1 + x1 )x2 x3 = x 1 x3 + x 2 x3 + x 2 x3 2.12. Derivation of the minimum sum-of-products expression: f = x 1 x2 x3 + x 1 x2 x4 + x 1 x 2 x3 x4 = x 1 x 2 x 3 (x 4 + x 4 ) + x 1 x 2 x 4 + x 1 x 2 x 3 x 4 = x 1 x2 x3 x 4 + x 1 x 2 x3 x4 + x 1 x2 x4 + x 1 x 2 x3 x 4 = x1 x2 x3 + x1 x2 (x3 + x3 )x4 + x1 x2 x4 = x 1 x2 x3 + x 1 x2 x 4 + x 1 x2 x4 2.13. The simplest POS expression is derived as f = (x1 + x3 + x4 )(x1 + x2 + x3 )(x1 + x2 + x3 + x4 ) = (x1 + x3 + x4 )(x1 + x2 + x3 )(x1 + x2 + x3 + x4 )(x1 + x2 + x3 + x4 ) = (x1 + x3 + x4 )(x1 + x2 + x3 )((x1 + x2 + x4 )(x3 + x3 )) = (x1 + x3 + x4 )(x1 + x2 + x3 )(x1 + x2 + x4 ) 1 = (x1 + x3 + x4 )(x1 + x2 + x3 )(x1 + x2 + x4 ) 2.14. Derivation of the minimum product-of-sums expression: f = (x1 + x2 + x3 )(x1 + x2 + x3 )(x1 + x2 + x3 )(x1 + x2 + x3 ) = ((x1 + x2 ) + x3 )((x1 + x2 ) + x3 )(x1 + (x2 + x3 ))(x1 + (x2 + x3 )) = (x1 + x2 )(x2 + x3 ) 2.15. (a) Location of all minterms in a 3-variable Venn diagram:
m0 m4 m5 x3

x1 m6 m7

x2 m2 m3

m1

2-5

(b) For f = x1 x2 x3 + x1 x2 + x1 x3 have:

x1 x3

x2

x1 x3 x1 x2

x2

x1 x3 x1 x3

x2

x1 x2 x3

Therefore, f is represented as:

x1 x3

x2

f = x 3 + x 1 x2

2.16. The function in Figure 2.18 in Venn diagram form is:

x1 x3

x2

2.17. In Figure P2.1a it is possible to represent only 14 minterms. It is impossible to represent the minterms x1 x2 x3 x4 and x1 x2 x3 x4 . In Figure P2.1b, it is impossible to represent the minterms x1 x2 x3 x4 and x1 x2 x3 x4 .

2.18. Venn diagram for f = x1 x2 x3 x4 + x1 x2 x3 x4 + x1 x2 is

x4 x1 x2 x1 x2

x3

x3

2-6

2.19. The simplest SOP implementation of the function is f = x 1 x2 x3 + x 1 x2 x 3 + x 1 x2 x3 + x 1 x2 x3 = (x1 + x1 )x2 x3 + x1 (x2 + x2 )x3 = x 2 x3 + x 1 x3

2.20. The simplest SOP implementation of the function is f = x 1 x2 x3 + x 1 x2 x3 + x 1 x2 x3 + x 1 x2 x 3 + x 1 x2 x3 = x1 (x2 + x2 )x3 + x1 (x2 + x2 )x3 + (x1 + x1 )x2 x3 = x 1 x3 + x 1 x3 + x 2 x3 Another possibility is f = x 1 x3 + x 1 x3 + x 1 x2

2.21. The simplest POS implementation of the function is f = (x1 + x2 + x3 )(x1 + x2 + x3 )(x1 + x2 + x3 ) = ((x1 + x3 ) + x2 )((x1 + x3 ) + x2 )(x1 + x2 + x3 ) = (x1 + x3 )(x1 + x2 + x3 ) 2.22. The simplest POS implementation of the function is f = (x1 + x2 + x3 )(x1 + x2 + x3 )(x1 + x2 + x3 )(x1 + x2 + x3 ) = ((x1 + x2 ) + x3 )((x1 + x2 ) + x3 )((x1 + x3 ) + x2 )((x1 + x3 ) + x2 ) = (x1 + x2 )(x1 + x3 )

2.23. The lowest cost circuit is dened by f (x1 , x2 , x3 ) = x1 x2 + x1 x3 + x2 x3

2-7

2.24. The truth table that corresponds to the timing diagram in Figure P2.3 is

x1 0 0 0 0 1 1 1 1

x2 0 0 1 1 0 0 1 1

x3 0 1 0 1 0 1 0 1

f 1 0 0 1 0 1 1 0

The simplest SOP expression is f = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3 . 2.25. The truth table that corresponds to the timing diagram in Figure P2.4 is

x1 0 0 0 0 1 1 1 1

x2 0 0 1 1 0 0 1 1

x3 0 1 0 1 0 1 0 1

f 0 1 1 1 1 0 0 1

The simplest SOP expression is derived as follows: f = x 1 x2 x3 + x 1 x2 x 3 + x 1 x2 x3 + x 1 x2 x 3 + x 1 x2 x3 = x1 (x2 + x2 )x3 + x1 x2 (x3 + x3 ) + (x1 + x1 )x2 x3 + x1 x2 x3 = x 1 1 x 3 + x 1 x2 1 + 1 x 2 x3 + x 1 x2 x3 = x 1 x3 + x 1 x2 + x 2 x3 + x 1 x2 x 3

2-8

2.26. (a) x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 y0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1

(b) The simplest POS expression is f = (x1 + y 1 )(x1 + y1 )(x0 + y 0 )(x0 + y0 )

2.27. (a) x1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 x0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 y1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 y0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 f 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1

2-9

(b) The canonical SOP expression is f = x 1 x 0 y 1 y 0 + x 1 x0 y 1 y 0 + x 1 x0 y 1 y 0 + x 1 x0 y 1 y 0 + x 1 x 0 y 1 y 0 + x 1 x 0 y 1 y 0 +x1 x0 y1 y0 + x1 x0 y 1 y0 + x1 x0 y1 y 0 + x1 x0 y1 y0

(c) The simplest SOP expression is f = x 1 x0 + y 1 y 0 + x 1 y 0 + x 0 y 1

2.28. Using the ciruit in Figure 2.25a as a starting point, the function in Figure 2.24 can be implemented using NAND gates as follows:

x1 x2 x3

2.29. Using the ciruit in Figure 2.25b as a starting point, the function in Figure 2.24 can be implemented using NOR gates as follows:
x3 x2 x1

2-10

2.30. The circuit in Figure 2.33 can be implemented using NAND and NOR gates as follows:
x1 x3 g x2 x4 f

2.31. The minimum-cost SOP expression for the function f (x1 , x2 , x3 ) = f = x 1 x 3 + x 2 x3 The corresponding circuit implemented using NAND gates is
x1 x3

m(3, 4, 6, 7) is

f x2

2.32. A minimum-cost SOP expression for the function f (x1 , x2 , x3 ) = f = x 1 x2 + x 1 x3 + x 1 x3 The corresponding circuit implemented using NAND gates is
x2 x1

m(1, 3, 4, 6, 7) is

f x3

2-11

2.33. The minimum-cost POS expression for the function f (x1 , x2 , x3 ) = f = (x1 + x3 )(x2 + x3 ) The corresponding circuit implemented using NOR gates is
x1 x3 x2

m(3, 4, 6, 7) is

2.34. The minimum-cost POS expression for the function f (x1 , x2 , x3 ) = f = (x1 + x3 )(x1 + x2 + x3 ) The corresponding circuit implemented using NOR gates is

m(1, 3, 4, 6, 7) is

x1 f x2 x3

2.37. The circuit in Figure 2.25a can be implemented using; module prob2 37 (x1, x2, x3, f); input x1, x2, x3; output f; not (notx1, x1); not (notx2, x2); not (notx3, x3); and (a, notx1, notx2, x3); and (b, notx1, x2, notx3); and (c, x1, notx2, notx3); and (d, x1, x2, x3); or (f, a, b, c, d); endmodule

2-12

2.38. The circuit in Figure 2.25b can be implemented using; module prob2 38 (x1, x2, x3, f); input x1, x2, x3; output f; not (notx1, x1); not (notx2, x2); not (notx3, x3); or (a, x1, x2, x3); or (b, notx1, notx2, x3); or (c, notx1, x2, notx3); or (d, x1, notx2, notx3); and (f, a, b, c, d); endmodule

2.39. The simplest circuit is obtained in the POS form as f = (x1 + x2 + x3 )(x1 + x2 + x3 ) Verilog code that implements the circuit is module prob2 39 (x1, x2, x3, f); input x1, x2, x3; output f; or (g, x1, x2, x3); or (h, x1, x2, x3); and (f, g, h); endmodule

2.40. The simplest circuit is obtained in the SOP form as f = x 2 + x 1 x3 + x 1 x 3 Verilog code that implements the circuit is module prob2 40 (x1, x2, x3, f); input x1, x2, x3; output f; assign f = x2 | (x1 & x3) | (x1 & x3); endmodule

2-13

2.41. The Verilog code is module prob2 41 (x1, x2, x3, x4, f1, f2); input x1, x2, x3, x4; output f1, f2; assign f1 = (x1 & x3) | (x2 & x3) | (x3 & x4) | (x1 & x2) | (x1 & x4); assign f2 = (x1 | x3) & (x1 | x2 | x4) & (x2 | x3 | x4); endmodule

2.42. The Verilog code is module prob2 42 (x1, x2, x3, x4, f1, f2); input x1, x2, x3, x4; output f1, f2; assign f1 = (x1 & x3) | (x1 & x3) | (x2 & x4) | (x2 & x4); assign f2 = (x1 & x2 & x3 & x4) | (x1 & x2 & x3 & x4) | (x1 & x2 & x3 & x4) | (x1 & x2 & x3 & x4); endmodule

2-14