ModelSim LE/PE Users Manual

Software Version 6.2g February 2007

1991-2007 Mentor Graphics Corporation All rights reserved.

This document contains information that is proprietary to Mentor Graphics Corporation. The original recipient of this document may duplicate this document in whole or in part for internal business purposes only, provided that this entire notice appears in all copies. In duplicating any part of this document, the recipient agrees to make every reasonable effort to prevent the unauthorized use and distribution of the proprietary information.

This document is for information and instruction purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in written agreements between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. RESTRICTED RIGHTS LEGEND 03/97 U.S. Government Restricted Rights. The SOFTWARE and documentation have been developed entirely at private expense and are commercial computer software provided with restricted rights. Use, duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the restrictions set forth in the license agreement provided with the software pursuant to DFARS 227.72023(a) or as set forth in subparagraph (c)(1) and (2) of the Commercial Computer Software - Restricted Rights clause at FAR 52.227-19, as applicable. Contractor/manufacturer is: Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777. Telephone: 503.685.7000 Toll-Free Telephone: 800.592.2210 Website: www.mentor.com SupportNet: www.mentor.com/supportnet Send Feedback on Documentation: www.mentor.com/supportnet/documentation/reply_form.cfm

TRADEMARKS: The trademarks, logos and service marks ("Marks") used herein are the property of Mentor Graphics Corporation or other third parties. No one is permitted to use these Marks without the prior written consent of Mentor Graphics or the respective third-party owner. The use herein of a thirdparty Mark is not an attempt to indicate Mentor Graphics as a source of a product, but is intended to indicate a product from, or associated with, a particular third party. A current list of Mentor Graphics trademarks may be viewed at: www.mentor.com/terms_conditions/trademarks.cfm.

Table of Contents
Chapter 1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tool Structure and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Steps for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 1 Collecting Files and Mapping Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 2 Compiling the Design (vlog, vcom, sccom) . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 3 Loading the Design for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 4 Simulating the Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 5 Debugging the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Line Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Batch Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Standards Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assumptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sections In This Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . What is an "Object" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Installation Directory Pathnames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Where to Find Our Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Download a Free PDF Reader With Search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technical Support and Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 2 Simulator Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Object Icons and Their Meaning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Fonts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Workspace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transcript . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple Document Interface (MDI) Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Organizing Windows with Tab Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Navigating in the Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Window Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main Window Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Active Processes Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Process Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Call Stack Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Coverage Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Workspace Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Missed Coverage Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 32 33 34 35 36 36 37 37 37 38 39 39 39 41 42 42 42 43 43 45 47 47 48 49 51 52 53 54 55 56 57 60 60 60 62 63 65

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Current Exclusions Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Instance Coverage Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Details Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Objects Pane Toggle Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Code Coverage Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Dataflow Window Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Locals Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Memory Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Associative Arrays in Verilog/SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Viewing Single and Multidimensional Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Viewing Packed Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Viewing Memory Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Saving Memory Formats in a DO File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Direct Address Navigation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Splitting the Memory Contents Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Objects Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Filtering the Objects List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Filtering by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Filtering by Signal Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Profile Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Profile Pane Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Profiler Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Opening Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Displaying Multiple Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Dragging and Dropping Objects into the Wave and List Windows . . . . . . . . . . . . . . . . . . 88 Setting your Context by Navigating Source Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Debugging with Source Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Language Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Setting File-Line Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Checking Object Values and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Marking Lines with Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Customizing the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Watch Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Adding Objects to the Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Expanding Objects to Show Individual Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Grouping and Ungrouping Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Saving and Reloading Format Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Wave Window Toolbar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Wave Edit Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Chapter 3 Projects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 What are Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

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What are the Benefits of Projects? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Project Conversion Between Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Getting Started with Projects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 1 Creating a New Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 2 Adding Items to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 3 Compiling the Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Step 4 Simulating a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Other Basic Project Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Project Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sorting the List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing Compile Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto-Generating Compile Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Grouping Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Simulation Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Organizing Projects with Folders. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding a Folder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying File Properties and Project Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File Compilation Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Project Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing Projects from the Command Line. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 4 Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Library Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Design Unit Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Working Library Versus Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Archives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Working with Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Managing Library Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Assigning a Logical Name to a Design Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Moving a Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up Libraries for Group Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Resource Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Predefined Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alternate IEEE Libraries Supplied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rebuilding Supplied Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Regenerating Your Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintaining 32- and 64-bit Versions in the Same Library . . . . . . . . . . . . . . . . . . . . . . . . . Importing FPGA Libraries. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Protecting Source Code Using -nodebug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

107 108 108 109 110 111 112 114 114 115 115 116 116 117 118 118 120 120 122 123 125 125 125 125 126 126 127 127 128 130 130 131 131 131 131 132 132 133 133 134 134

Chapter 5 VHDL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Basic VHDL Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Compiling VHDL Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

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Creating a Design Library for VHDL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invoking the VHDL Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dependency Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Range and Index Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Subprogram Inlining . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Differences Between Language Versions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulating VHDL Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator Resolution Limit (VHDL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Default Binding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delta Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the TextIO Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Syntax for File Declaration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using STD_INPUT and STD_OUTPUT Within the Tool . . . . . . . . . . . . . . . . . . . . . . . . . TextIO Implementation Issues. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Writing Strings and Aggregates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reading and Writing Hexadecimal Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dangling Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The ENDLINE Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The ENDFILE Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Alternative Input/Output Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flushing the TEXTIO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Providing Stimulus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VITAL Specification and Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VITAL Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VITAL Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VITAL Compliance Checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compiling and Simulating with Accelerated VITAL Packages . . . . . . . . . . . . . . . . . . . . . . Util Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . get_resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . init_signal_driver() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . init_signal_spy() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal_force() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal_release() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to_real(). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to_time() . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modeling Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL87 and VHDL93 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL02 example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Affecting Performance by Cancelling Scheduled Events . . . . . . . . . . . . . . . . . . . . . . . . . . . Converting an Integer Into a bit_vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 6 Verilog and SystemVerilog Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Terminology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Verilog Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compiling Verilog Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Working Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invoking the Verilog Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

137 138 138 138 139 139 142 142 143 144 146 147 147 148 148 149 149 150 150 150 150 151 151 151 152 152 152 153 153 153 154 154 154 154 155 156 158 161 165 165 167 167 167 167 168 168

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Incremental Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemVerilog Multi-File Compilation Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog-XL Compatible Compiler Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog-XL uselib Compiler Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog Generate Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulating Verilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator Resolution Limit (Verilog). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Event Ordering in Verilog Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging Event Order Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Negative Timing Check Limits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog-XL Compatible Simulator Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Escaped Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Cell Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDF Timing Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Delay Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE Std 1364 System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemVerilog System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Tasks and Functions Specific to the Tool . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog-XL Compatible System Tasks and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE Std 1364 Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compiler Directives for vlog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog-XL Compatible Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog PLI/VPI and SystemVerilog DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 7 SystemC Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Platforms and Compiler Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Building gcc with Custom Configuration Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HP Limitations for SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Usage Flow for SystemC-Only Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compiling SystemC Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Design Library for SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Modifying SystemC Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Modification Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invoking the SystemC Compiler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compiling Optimized and/or Debug Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying an Alternate g++ Installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Maintaining Portability Between OSCI and the Simulator. . . . . . . . . . . . . . . . . . . . . . . . . Restrictions on Compiling with HP aCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Switching Platforms and Compilation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using sccom in Addition to the Raw C++ Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Issues with C++ Templates. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linking the Compiled Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulating SystemC Designs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

169 172 173 174 175 177 178 179 179 182 185 187 188 189 190 190 190 191 192 194 195 196 199 200 200 201 202 203 203 204 205 205 206 206 207 208 210 210 211 211 212 212 212 214 215 215

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Loading the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Time Unit and Simulator Resolution. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization and Cleanup of SystemC State-Based Code . . . . . . . . . . . . . . . . . . . . . . . . . Debugging the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewable SystemC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewable SystemC Objects. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveform Compare with SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging Source-Level Code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Object and Type Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support for Globals and Statics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support for Aggregates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing FIFOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing SystemC Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Properly Recognizing Derived Module Class Pointers . . . . . . . . . . . . . . . . . . . . . . . . . . . Custom Debugging of SystemC Channels and Variables. . . . . . . . . . . . . . . . . . . . . . . . . . Differences Between the Simulator and OSCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fixed-Point Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support for cin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OSCI 2.1 Feature Implementation Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support for OSCI TLM Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Callback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Accessing Command-Line Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sc_stop Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Construction Parameters for SystemC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Troubleshooting SystemC Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unexplained Behaviors During Loading or Runtime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Errors During Loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Procedural Interface to SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Definition of Terms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Import Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calling SystemVerilog Export Tasks / Functions from SystemC . . . . . . . . . . . . . . . . . . . SystemC Data Type Support in SystemVerilog DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Function Prototype Header File (sc_dpiheader.h). . . . . . . . . . . . . . . . . . . . . . . . SystemC DPI Usage Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 8 Mixed-Language Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Basic Mixed-Language Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Separate Compilers with Common Design Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Access Limitations in Mixed-Language Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator Resolution Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Runtime Modeling Semantics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hierarchical References In Mixed HDL/SystemC Designs . . . . . . . . . . . . . . . . . . . . . . . . Mapping Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog to VHDL Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL To Verilog Mappings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

215 216 216 217 218 218 219 220 220 222 222 222 223 224 224 226 230 231 231 232 232 232 233 233 233 235 235 236 239 239 239 240 244 244 246 246 249 249 249 250 250 251 251 252 253 255

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Verilog And SystemC Signal Interaction And Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . VHDL and SystemC Signal Interaction And Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Instantiating Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog Instantiation Criteria Within VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Declaration for VHDL Instantiating Verilog . . . . . . . . . . . . . . . . . . . . . . . . . vgencomp Component Declaration when VHDL Instantiates Verilog . . . . . . . . . . . . . . . Modules with Unnamed Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog Instantiating VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Instantiation Criteria Within Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Entity and Architecture Names and Escaped Identifiers . . . . . . . . . . . . . . . . . . . . . . . . . . Named Port Associations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic Associations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDF Annotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Instantiating Verilog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog Instantiation Criteria Within SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Foreign Module (Verilog) Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Support for SystemC Instantiating Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog Instantiating SystemC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Instantiation Criteria for Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exporting SystemC Modules for Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parameter Support for Verilog Instantiating SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Instantiating VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Instantiation Criteria Within SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Foreign Module (VHDL) Declaration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic Support for SystemC Instantiating VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Instantiating SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Instantiation Criteria for VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Component Declaration for VHDL Instantiating SystemC . . . . . . . . . . . . . . . . . . . . . . . . vgencomp Component Declaration when VHDL Instantiates SystemC . . . . . . . . . . . . . . Exporting SystemC Modules for VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Generic Support for VHDL Instantiating SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 9 Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Objects Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recording Transactions with SCV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Steps for Recording in SCV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initializing the Library and Creating the WLF Database . . . . . . . . . . . . . . . . . . . . . . . . . . Preparing Attribute Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Transaction Streams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defining Transaction Kinds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recording Special Attributes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ending Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

256 260 264 264 264 265 266 267 267 268 268 268 269 269 269 269 271 275 276 276 276 279 279 279 280 285 285 285 286 286 287 289 289 290 290 292 292 293 294 294 295 296 297 297 298 298

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Specifying and Recording Phase Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Start and End Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling and Disabling Logging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limitations on SCV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relation Recording . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 10 WLF Files (Datasets) and Virtuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving a Simulation to a WLF File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . WLF File Parameter Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Opening Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Dataset Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Structure Tab Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Managing Multiple Datasets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Restricting the Dataset Prefix Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving at Intervals with Dataset Snapshot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Collapsing Time and Delta Steps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Regions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Virtual Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 11 Waveform Analysis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Objects You Can View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wave Window Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List Window Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Objects to the Wave or List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Objects with Drag and Drop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Objects with a Menu Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Objects with a Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Objects with a Window Format File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Measuring Time with Cursors in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Working with Cursors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Understanding Cursor Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Jumping to a Signal Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Time Markers in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Working with Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zooming the Wave Window Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zooming with the Menu, Toolbar and Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving Zoom Range and Scroll Position with Bookmarks. . . . . . . . . . . . . . . . . . . . . . . . . Searching in the Wave and List Windows. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Finding Signal Names. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Searching for Values or Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Expression Builder for Expression Searches . . . . . . . . . . . . . . . . . . . . . . . . . . .

299 299 299 300 300 301 302 303 304 305 305 306 306 306 307 308 309 309 310 311 312 312 313 313 314 316 317 317 317 317 318 318 319 320 321 321 321 322 322 323 324 324 325 326

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Formatting the Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Wave Window Display Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Formatting Objects in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Dividing the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Splitting Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wave Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deleting or Ungrouping a Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Items to an Existing Wave Group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Removing Items from an Existing Wave Group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Wave Group Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Formatting the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting List Window Display Properties. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Formatting Objects in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving the Window Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printing and Saving Waveforms in the Wave window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving a .eps Waveform File and Printing in UNIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printing from the Wave Window on Windows Platforms . . . . . . . . . . . . . . . . . . . . . . . . . Printer Page Setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving List Window Data to a File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Combining Objects into Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring New Line Triggering in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Gating Expressions to Control Triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sampling Signals at a Clock Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Examining Waveform Values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Displaying Drivers of the Selected Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sorting a Group of Objects in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating and managing breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . File-line breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Waveform Compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mixed-Language Waveform Compare Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Three Options for Setting up a Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up a Comparison with the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting a Waveform Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Signals, Regions, and Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Comparison Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Compare Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Differences in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Differences in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Differences in Textual Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving and Reloading Comparison Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Comparing Hierarchical and Flattened Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

328 328 330 332 333 334 334 336 336 336 336 337 337 337 339 340 340 340 340 340 341 343 345 347 347 347 347 348 348 348 348 349 349 350 351 352 353 355 356 357 360 360 361 361

Chapter 12 Tracing Signals with the Dataflow Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Dataflow Window Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

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Objects You Can View in the Dataflow Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Adding Objects to the Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Links to Other Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exploring the Connectivity of the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tracking Your Path Through the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Embedded Wave Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Zooming and Panning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Panning with the Mouse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tracing Events (Causality) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tracing the Source of an Unknown State (StX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Finding Objects by Name in the Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Printing and Saving the Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving a .eps File and Printing the Dataflow Display from UNIX . . . . . . . . . . . . . . . . . . Printing from the Dataflow Display on Windows Platforms . . . . . . . . . . . . . . . . . . . . . . . Configuring Page Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Symbol Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuring Window Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 13 Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unified Coverage Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Purpose of the UCDB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Important Notes About Coverage Statistics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving Coverage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving Data On Demand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving Data at End of Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Merging Coverage Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Merging with vcover merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coverage View Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Code Coverage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Usage Flow for Code Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Code Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Coverage Data in the Graphic Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Coverage Data in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Toggle Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Finite State Machine Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Managing Exclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Excluding Objects from Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving and Recalling Exclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting Coverage Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the coverage report Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the toggle report Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the Coverage Report Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting a Default Coverage Reporting Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XML Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sample Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Coverage Statistics Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

364 364 365 365 366 366 367 368 368 369 370 371 371 372 373 373 375 377 377 378 378 379 379 379 380 380 382 382 383 383 384 386 388 390 392 392 392 396 397 398 398 400 400 401 401 405

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Condition Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 Expression Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 Chapter 14 Finite State Machines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Types of FSM Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM Recognition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM Extraction Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing FSM Coverage in the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Workspace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Missed Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Instance Coverage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM Viewer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM Coverage Reports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . FSM Coverage Exclusions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using the coverage exclude Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 15 C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Supported Platforms and gdb Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running C Debug on Windows Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Up C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Running C Debug from a DO File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stepping in C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Known Problems With Stepping in C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quitting C Debug. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Finding Function Entry Points with Auto Find bp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identifying All Registered Function Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling Auto Step Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Auto Find bp Versus Auto Step Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging Functions During Elaboration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLI Functions in Initialization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPI Functions in Initialization Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Completing Design Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging Functions when Quitting Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C Debug Command Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 16 Profiling Performance and Memory Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introducing Performance and Memory Profiling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Statistical Sampling Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Allocation Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Getting Started with the Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling the Memory Allocation Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enabling the Statistical Sampling Profiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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409 409 409 413 417 417 417 418 419 419 420 421 429 429 431 432 432 433 433 434 436 436 436 437 437 438 439 439 441 443 443 443 444 447 447 448 448 448 448 450
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Collecting Memory Allocation and Performance Data . . . . . . . . . . . . . . . . . . . . . . . . . . . Running the Profiler on Windows with PLI/VPI Code . . . . . . . . . . . . . . . . . . . . . . . . . . . Interpreting Profiler Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Profiler Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Ranked View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Call Tree View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Structural View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Viewing Profile Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integration with Source Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analyzing C Code Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reporting Profiler Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 17 Signal Spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Designed for Testbenches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . disable_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . enable_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . init_signal_driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . init_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal_force. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . signal_release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $disable_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $enable_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $init_signal_driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $init_signal_spy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $signal_force. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $signal_release . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 18 Generating Stimulus with Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Getting Started with the Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Waveform Editor Prior to Loading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Waveform Editor After Loading a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Waveforms from Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Editing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Selecting Parts of the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Stretching and Moving Edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulating Directly from Waveform Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exporting Waveforms to a Stimulus File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driving Simulation with the Saved Stimulus File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Signal Mapping and Importing EVCD Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Waveform Compare with Created Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving the Waveform Editor Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

450 451 451 451 452 453 454 455 457 458 459 463 463 465 466 467 469 472 474 476 477 478 480 482 484 487 487 487 488 489 490 492 494 494 494 495 496 496 497

Chapter 19 Standard Delay Format (SDF) Timing Annotation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 Specifying SDF Files for Simulation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 Instance Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500
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SDF Specification with the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Errors and Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL VITAL SDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDF to VHDL Generic Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resolving Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog SDF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . $sdf_annotate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDF to Verilog Construct Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optional Edge Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Optional Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Rounded Timing Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SDF for Mixed VHDL and Verilog Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interconnect Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Disabling Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying the Wrong Instance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Mistaking a Component or Module Name for an Instance Label. . . . . . . . . . . . . . . . . . . . Forgetting to Specify the Instance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 20 Value Change Dump (VCD) Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating a VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flow for Four-State VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Flow for Extended VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Case Sensitivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Extended VCD as Stimulus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulating with Input Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Replacing Instances with Output Values from a VCD File . . . . . . . . . . . . . . . . . . . . . . . . VCD Commands and VCD Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compressing Files with VCD Tasks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCD File from Source To Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCD Simulator Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCD Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Capturing Port Driver Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Identifier Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resolving Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Chapter 21 Tcl and Macros (DO Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tcl Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tcl References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tcl Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . If Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

500 501 501 501 502 502 504 505 508 509 510 510 510 511 511 511 512 512 515 515 515 516 516 516 516 518 519 520 520 520 521 521 524 524 525 526 526 531 531 531 531 532 535 535

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Command Separator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiple-Line Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Evaluation Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tcl Relational Expression Evaluation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variable Substitution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . System Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . List Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator Tcl Time Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Conversions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Relations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Arithmetic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tcl Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Macros (DO Files) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating DO Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using Parameters with DO Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Deleting a File from a .do Script. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Making Macro Parameters Optional. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Useful Commands for Handling Breakpoints and Errors . . . . . . . . . . . . . . . . . . . . . . . . . . Error Action in DO Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix A Simulator Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variable Settings Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environment Variable Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Environment Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Environment Variables in Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Referencing Environment Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Removing Temp Files (VSOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator Control Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Library Path Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog Compiler Control Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL Compiler Control Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemC Compiler Control Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulation Control Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Simulator Control Variables With The GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message System Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Commonly Used INI Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Variable Precedence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator State Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Referencing Simulator State Variables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Special Considerations for the now Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

536 536 536 536 537 537 538 538 539 540 540 541 541 545 545 546 546 547 548 549 551 551 551 551 552 555 556 557 557 557 559 562 567 569 583 585 587 590 590 591 591

Appendix B Location Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Referencing Source Files with Location Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Using Location Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593

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Pathname Syntax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 How Location Mapping Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 Mapping with TCL Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 Appendix C Error and Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Message Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Getting More Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Changing Message Severity Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suppressing Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suppressing VCOM Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suppressing VLOG Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Suppressing VSIM Warning Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Exit Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Miscellaneous Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . sccom Error Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Enforcing Strict 1076 Compliance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix D Verilog PLI/VPI/DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Implementation Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . g++ Compiler Support for use with PLI/VPI/DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registering PLI Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registering VPI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Registering DPI Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPI Use Flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . When Your DPI Export Function is Not Getting Called . . . . . . . . . . . . . . . . . . . . . . . . . . Simplified Import of FLI / PLI / C Library Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . Use Model for Read-Only Work Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Making Verilog Function Calls from non-DPI C Models . . . . . . . . . . . . . . . . . . . . . . . . . Compiling and Linking C Applications for PLI/VPI/DPI . . . . . . . . . . . . . . . . . . . . . . . . . . . For all UNIX Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Windows Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit Linux Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit Linux for IA64 Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit Linux for Opteron/Athlon 64 and EM64T Platforms. . . . . . . . . . . . . . . . . . . . . . . . 32-bit Solaris Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit Solaris Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit HP700 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit HP Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit HP for IA64 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit IBM RS/6000 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit IBM RS/6000 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Compiling and Linking C++ Applications for PLI/VPI/DPI. . . . . . . . . . . . . . . . . . . . . . . . . Windows Platforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit Linux Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit Linux for IA64 Platform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 595 595 596 596 596 596 597 597 597 599 602 604 607 607 607 608 609 611 612 613 613 614 615 616 616 617 618 619 619 619 620 620 620 620 621 622 623 623 624 625

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64-bit Linux for Opteron/Athlon 64 and EM64T Platforms. . . . . . . . . . . . . . . . . . . . . . . . 32-bit Solaris Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit Solaris Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit HP700 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit HP Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit HP for IA64 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32-bit IBM RS/6000 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit IBM RS/6000 Platform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Specifying Application Files to Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLI/VPI file loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPI File Loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Loading Shared Objects with Global Symbol Visibility . . . . . . . . . . . . . . . . . . . . . . . . . . PLI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VPI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DPI Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The PLI Callback reason Argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The sizetf Callback Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLI Object Handles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Third Party PLI Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Support for VHDL Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE Std 1364 ACC Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IEEE Std 1364 TF Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SystemVerilog DPI Access Routines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog-XL Compatible Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64-bit Support for PLI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Using 64-bit ModelSim with 32-bit Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PLI/VPI Tracing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The Purpose of Tracing Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Invoking a Trace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Debugging PLI/VPI/DPI Application Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Troubleshooting a Missing DPI Import Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . HP-UX Specific Warnings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix E Command and Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Shortcuts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command History Shortcuts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Main and Source Window Mouse and Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . List Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Wave Window Mouse and Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix F Setting GUI Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Customizing the Simulator GUI Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Layouts and Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Custom Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Automatic Saving of Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resetting Layouts to Their Defaults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

625 625 626 626 626 626 627 628 629 629 629 630 630 631 632 632 634 634 635 635 637 639 639 640 640 640 640 641 641 642 642 643 645 645 645 646 649 650 653 653 653 653 655 655

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Navigating the Graphic User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manipulating Panes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Columnar Information Display . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Quick Access Toolbars . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Simulator GUI Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting Preference Variables from the GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Saving GUI Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . The modelsim.tcl File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix G System Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Files Accessed During Startup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Environment Variables Accessed During Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Initialization Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Appendix H Logic Modeling SmartModels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VHDL SmartModel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Creating Foreign Architectures with sm_entity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SmartModel Vector Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Command Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SmartModel Windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Memory Arrays. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Verilog SmartModel Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linking the LMTV Interface to the Simulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Index Third-Party Information End-User License Agreement

655 655 657 657 657 658 659 659 661 661 662 663 667 667 668 671 672 672 674 674 674

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List of Examples
Example 2-1. Wave Window Panes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Example 6-1. Invocation of the Verilog Compiler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Example 6-2. Incremental Compilation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Example 6-3. Sub-Modules with Common Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Example 6-4. Negative Timing Check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 Example 7-1. Converting sc_main to a Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Example 7-2. Using sc_main and Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Example 7-3. Using an SCV Transaction Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Example 7-4. Using the Custom Interface on Different Objects . . . . . . . . . . . . . . . . . . . . . . 228 Example 7-5. Global Import Function Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Example 7-6. SystemVerilog Global Import Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 Example 7-7. Usage of scSetScopeByName and scGetScopeName . . . . . . . . . . . . . . . . . . . 243 Example 8-1. SystemC Instantiating Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Example 8-2. SystemC Instantiating Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Example 8-3. Sample Foreign Module Declaration, with Constructor Arguments for Parameters 272 Example 8-4. Passing Parameters as Constructor Arguments . . . . . . . . . . . . . . . . . . . . . . . . 272 Example 8-5. SystemC Instantiating Verilog, Passing Integer Parameters as Template Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 Example 8-6. Passing Integer Parameters as Template Arguments and Non-integer Parameters as Constructor Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Example 8-7. Verilog Instantiating SystemC, Parameter Information . . . . . . . . . . . . . . . . . 277 Example 8-8. SystemC Design Instantiating a VHDL Design Unit . . . . . . . . . . . . . . . . . . . 280 Example 8-9. SystemC Instantiating VHDL, Generic Information. . . . . . . . . . . . . . . . . . . . 281 Example 8-10. Passing Parameters as Constructor Arguments . . . . . . . . . . . . . . . . . . . . . . . 281 Example 8-11. SystemC Instantiating VHDL, Passing Integer Generics as Template Arguments 283 Example 8-12. Passing Integer Generics as Template Arguments and Non-integer Generics as Constructor Arguments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 Example 13-1. Order of Files to Merge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Example 13-2. Excluding, Merging and Reporting on Several Runs . . . . . . . . . . . . . . . . . . 396 Example 13-3. Reporting Coverage Data from the Command Line . . . . . . . . . . . . . . . . . . . 398 Example 14-1. Using a Single State Variable in Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Example 14-2. Using a single state variable in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 Example 14-3. Using a Current State Variable and a Single Next State Variable in Verilog 411 Example 14-4. Using Current State Variable and Single Next State Variable in VHDL . . . 412 Example 14-5. Verilog Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 Example 14-6. Using Pragmas in VHDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 Example 20-1. Verilog Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 Example 20-2. VHDL Adder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
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Example 20-3. Mixed-HDL Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example 20-4. Replacing Instances. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example 20-5. VCD Output from vcd dumpports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example D-1. VPI Application Registration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example F-1. Configure Window Layouts Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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List of Figures
Figure 1-1. Tool Structure and Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-1. Graphical User Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-2. Main Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-3. Message Viewer Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-4. Tabs in the MDI Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-5. Organizing Files in Tab Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-6. Main Window Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-7. Active Processes Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-8. Call Stack Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-9. Panes that Show Code Coverage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-10. Code Coverage Data in the Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-11. Missed Coverage Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-12. Branch Tab in the Missed Coverage Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-13. Current Exclusions Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-14. Instance Coverage Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-15. Details Pane Showing Condition Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-16. Details Pane Showing Toggle Details. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-17. Details Pane Showing Information from Source Window . . . . . . . . . . . . . . . . Figure 2-18. Toggle Coverage in the Objects Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-19. Code Coverage Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-20. Dataflow Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-21. List Window Docked in Main Window MDI Frame . . . . . . . . . . . . . . . . . . . . Figure 2-22. List Window Undocked . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-23. Locals Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-24. Memory Panes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-25. Viewing Multiple Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-26. Split Screen View of Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-27. Objects Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-28. Objects Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-29. Filtering the Objects List by Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-30. Profile Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-31. Profile Details Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-32. Source Window Showing Language Templates . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-33. Displaying Multiple Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-34. Setting Context from Source Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-35. Source Annotation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-36. Language Templates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-37. Create New Design Wizard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-38. Inserting Module Statement from Verilog Language Template . . . . . . . . . . . . Figure 2-39. Language Template Context Menus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
22

32 45 49 53 54 55 56 60 61 62 65 65 66 67 67 68 68 69 69 71 72 75 76 77 78 80 81 82 82 83 84 84 87 88 89 90 92 92 93 93

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List of Figures

Figure 2-40. Preferences Dialog for Customizing Source Window . . . . . . . . . . . . . . . . . . . Figure 2-41. .Watch Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-42. Grouping Objects in the Watch Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-43. Wave Window Undock Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 2-44. Wave Window Dock Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-1. Create Project Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-2. Project Tab in Workspace Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-3. Add items to the Project Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-4. Create Project File Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-5. Add file to Project Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-6. Right-click Compile Menu in Project Tab of Workspace. . . . . . . . . . . . . . . . . . Figure 3-7. Click Plus Sign to Show Design Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-8. Start Simulation Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-9. Structure Tab of the Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-10. Project Displayed in Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-11. Setting Compile Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-12. Grouping Files. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-13. Simulation Configuration Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-14. Simulation Configuration in the Project Tab . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-15. Add Folder Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-16. Specifying a Project Folder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-17. Project Compiler Settings Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-18. Specifying File Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 3-19. Project Settings Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-1. Creating a New Library. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-2. Design Unit Information in the Workspace . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-3. Edit Library Mapping Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 4-4. Import Library Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 5-1. VHDL Delta Delay Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 6-1. Selecting Use System Verilog Compile Option . . . . . . . . . . . . . . . . . . . . . . . . Figure 7-1. SystemC Objects in GUI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7-2. Breakpoint in SystemC Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7-3. SystemC Objects and Processes in GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 7-4. Aggregates in Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9-1. Transaction in Wave Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9-2. Overlapping Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 9-3. Phase / Child Transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-1. Displaying Two Datasets in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-2. Open Dataset Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-3. Structure Tabs in Workspace Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-4. The Dataset Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-5. Dataset Snapshot Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 10-6. Virtual Objects Indicated by Orange Diamond. . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-1. Undocking the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-2. Docking the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

95 96 97 98 99 109 109 110 111 111 112 112 113 113 114 115 116 117 118 119 119 120 121 122 127 128 129 134 144 169 215 221 221 223 290 291 292 302 304 305 306 308 310 314 315

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Figure 11-3. Panes in the Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-4. Tabular Format of the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-5. Cursor Names, Values and Time Measurements . . . . . . . . . . . . . . . . . . . . . . . Figure 11-6. Time Markers in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-7. Bookmark Properties Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-8. Find Signals by Name or Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-9. Wave Signal Search Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-10. Expression Builder Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-11. Display Tab of the Wave Window Preferences Dialog . . . . . . . . . . . . . . . . . Figure 11-12. Grid & Timeline Tab of Wave Window Preferences Dialog . . . . . . . . . . . . . Figure 11-13. Clock Cycles in Timeline of Wave Window . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-14. Changing Signal Radix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-15. Separate Signals with Wave Window Dividers . . . . . . . . . . . . . . . . . . . . . . . Figure 11-16. Splitting Wave Window Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-17. Fill in the name of the group in the Group Name field. . . . . . . . . . . . . . . . . . Figure 11-18. Wave groups denoted by red diamond . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-19. Modifying List Window Display Properties . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-20. List Signal Properties Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-21. Changing the Radix in the List Window. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-22. Signals Combined to Create Virtual Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-23. Line Triggering in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-24. Setting Trigger Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-25. Trigger Gating Using Expression Builder. . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-26. Waveform Comparison Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-27. Start Comparison Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-28. Compare Tab in the Workspace Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-29. Structure Browser . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-30. Add Comparison by Region Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-31. Comparison Methods Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-32. Adding a Clock for a Clocked Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-33. Waveform Comparison Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-34. Viewing Waveform Differences in the Wave Window . . . . . . . . . . . . . . . . . Figure 11-35. Waveform Difference Details and Markers . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-36. Waveform Differences in the List Window . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 11-37. Reloading and Redisplaying Compare Differences . . . . . . . . . . . . . . . . . . . . Figure 12-1. The Dataflow Window (undocked). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12-2. Green Highlighting Shows Your Path Through the Design . . . . . . . . . . . . . . . Figure 12-3. Wave Viewer Displays Inputs and Outputs of Selected Process . . . . . . . . . . . Figure 12-4. Unknown States Shown as Red Lines in Wave Window . . . . . . . . . . . . . . . . . Figure 12-5. Find in Dataflow Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12-6. The Print Postscript Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12-7. The Print Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12-8. The Dataflow Page Setup Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 12-9. Configuring Dataflow Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13-1. Coverage Tab of Compiler Options Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . .

316 317 319 321 324 325 326 327 329 330 330 331 332 334 335 335 337 338 339 342 343 344 346 350 352 353 354 354 355 356 357 358 359 360 361 363 366 367 369 371 372 372 373 375 385

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List of Figures

Figure 13-2. Enabling Code Coverage in the Start Simulation Dialog . . . . . . . . . . . . . . . . . Figure 13-3. Coverage Data is Shown in Several Window Panes. . . . . . . . . . . . . . . . . . . . . Figure 13-4. Filter Instance List Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13-5. Coverage Data in the Source Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13-6. Toggle Coverage Data in the Objects Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13-7. Sample Toggle Report. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13-8. Coverage Report Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13-9. Sample Statement Coverage Summary Report by File. . . . . . . . . . . . . . . . . . . Figure 13-10. Sample Instance Report with Line Details . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 13-11. Sample Branch Report . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14-1. FSM Coverage Data in the Workspace. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14-2. FSM Coverage in the Objects Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14-3. FSM Missed Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14-4. FSM Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14-5. The FSM Viewer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 14-6. Coverage Type Section of Coverage Report Dialog. . . . . . . . . . . . . . . . . . . . . Figure 15-1. Specifying Path in C Debug setup Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15-2. Setting Breakpoints in Source Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15-3. Right Click Pop-up Menu on Breakpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15-4. Simulation Stopped at Breakpoint on PLI Task . . . . . . . . . . . . . . . . . . . . . . . . Figure 15-5. Stepping into Next File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15-6. Function Pointer to Foreign Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15-7. Highlighted Line in Associated File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 15-8. Stop on quit Button in Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-1. Status Bar: Profile Samples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-2. Profile Pane: Ranked Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-3. Profile Pane: Call Tree Tab. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-4. Profile Pane: Structural Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-5. Profile Details Pane: Function Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-6. Profile Details: Instance Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-7. Profile Details: Callers and Callees. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-8. Accessing Source from Profile Views . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-9. Profile Report Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 16-10. Profile Report Dialog Box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18-1. Workspace Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18-2. Opening Waveform Editor from Workspace or Objects Windows . . . . . . . . . Figure 18-3. Create Pattern Wizard: Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18-4. Toolbar Popup Menu. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18-5. Wave Edit Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18-6. Manipulating Waveforms with the Wave Edit Toolbar and Cursors . . . . . . . . Figure 18-7. Export Waveform Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 18-8. Evcd Import Dialog. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure 19-1. SDF Tab in Start Simulation Dialog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure A-1. Runtime Options Dialog: Defaults Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure A-2. Runtime Options Dialog Box: Assertions Tab. . . . . . . . . . . . . . . . . . . . . . . . . .

386 387 388 389 392 399 400 402 403 404 417 418 418 419 420 421 433 435 435 438 439 440 441 443 450 452 454 454 456 456 457 458 460 461 488 489 490 491 491 493 495 496 500 583 584

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List of Figures

Figure A-3. Runtime Options Dialog Box, WLF Files Tab . . . . . . . . . . . . . . . . . . . . . . . . . Figure D-1. DPI Use Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-1. Save Current Window Layout Dialog Box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-2. GUI: Window Pane. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-3. GUI: Double Bar. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-4. GUI: Undock Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-5. GUI: Dock Button. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-6. GUI: Zoom Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-7. GUI: Zoom Button . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-8. Toolbar Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-9. Preferences Dialog Box: By Window Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figure F-10. Preferences Dialog Box: By Name Tab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

585 612 654 655 656 656 656 656 657 657 658 659

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List of Tables
Table 1-1. Simulation Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1-2. Use Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1-3. Definition of Object by Language . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1-4. Text Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 1-5. Documentation List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-1. GUI Windows and Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-2. Design Object Icons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-3. Icon Shapes and Design Object Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-4. Message Viewer Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-5. Commands for Tab Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-6. Information Displayed in Status Bar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-7. Main Window Toolbar Buttons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-8. Panes that Show Code Coverage Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-9. Coverage Columns in the Workspace Pane . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-10. Toggle Coverage Columns in the Objects Pane . . . . . . . . . . . . . . . . . . . . . . . . Table 2-11. Code Coverage Toolbar Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-12. Dataflow Window Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-13. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-14. Profiler Toolbar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2-15. Wave Window Toolbar Buttons and Menu Selections . . . . . . . . . . . . . . . . . . . Table 2-16. Waveform Editor Toolbar Buttons and Menu Selections . . . . . . . . . . . . . . . . . Table 4-1. Compile Options for the -nodebug Compiling . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-1. Sample Modules With and Without Timescale Directive . . . . . . . . . . . . . . . . . . Table 6-2. Evaluation 1 of always Statements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-3. Evaluation 2 of always Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-4. IEEE Std 1364 System Tasks and Functions - 1 . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-5. IEEE Std 1364 System Tasks and Functions - 2 . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-6. IEEE Std 1364 System Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-7. IEEE Std 1364 File I/O Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-8. SystemVerilog System Tasks and Functions - 1 . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-9. SystemVerilog System Tasks and Functions - 2 . . . . . . . . . . . . . . . . . . . . . . . . . Table 6-10. SystemVerilog System Tasks and Functions - 4 . . . . . . . . . . . . . . . . . . . . . . . . Table 7-1. Supported Platforms for SystemC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-2. Custom gcc Platform Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-3. Simple Conversion - sc_main to Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-4. Using sc_main and Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-5. Modifications Using SCV Transaction Database . . . . . . . . . . . . . . . . . . . . . . . . Table 7-6. Time Unit and Simulator Resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-7. Viewable SystemC Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 37 41 42 42 46 47 47 53 55 56 57 62 63 70 71 73 78 85 102 105 135 180 183 184 192 192 192 193 194 194 194 203 204 208 209 210 216 219

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List of Tables

Table 7-8. Mixed-language Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 7-9. SystemC Types as Represented in SystemVerilog . . . . . . . . . . . . . . . . . . . . . . . Table 10-1. WLF File Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10-2. Structure Tab Columns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 10-3. vsim Arguments for Collapsing Time and Delta Steps . . . . . . . . . . . . . . . . . . . Table 11-1. Actions for Cursors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 11-2. Actions for Time Markers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 11-3. Actions for Bookmarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 11-4. Actions for Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 11-5. Triggering Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 11-6. Mixed-Language Waveform Compares . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 12-1. Dataflow Window Links to Other Windows and Panes . . . . . . . . . . . . . . . . . . Table 12-2. Icon and Menu Selections for Exploring Design Connectivity . . . . . . . . . . . . . Table 13-1. Coverage Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 13-2. Coverage Panes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 13-3. Condition Truth Table for Line 180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 13-4. Condition Truth Table for Line 38 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 13-5. Expression Truth Table for line 236 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15-1. Supported Platforms and gdb Versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15-2. Simulation Stepping Options in C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 15-3. Command Reference for C Debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 17-1. Signal Spy: Mapping VHDL Procedures to Verilog System Tasks . . . . . . . . . Table 18-1. Signal Attributes in Create Pattern Wizard . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18-2. Waveform Editing Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18-3. Selecting Parts of the Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18-4. Wave Editor Mouse/Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18-5. Formats for Saving Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 18-6. Examples for Loading a Stimulus File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-1. Matching SDF to VHDL Generics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-2. Matching SDF IOPATH to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-3. Matching SDF INTERCONNECT and PORT to Verilog . . . . . . . . . . . . . . . . Table 19-4. Matching SDF PATHPULSE and GLOBALPATHPULSE to Verilog . . . . . . Table 19-5. Matching SDF DEVICE to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-6. Matching SDF SETUP to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-7. Matching SDF HOLD to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-8. Matching SDF SETUPHOLD to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-9. Matching SDF RECOVERY to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-10. Matching SDF REMOVAL to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-11. Matching SDF RECREM to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-12. Matching SDF SKEW to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-13. Matching SDF WIDTH to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-14. Matching SDF PERIOD to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-15. Matching SDF NOCHANGE to Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-16. Matching Verilog Timing Checks to SDF SETUP . . . . . . . . . . . . . . . . . . . . . Table 19-17. SDF Data May Be More Accurate Than Model . . . . . . . . . . . . . . . . . . . . . . .

220 245 303 305 309 319 321 323 333 344 349 365 365 377 387 405 406 407 432 436 444 463 490 491 492 494 495 495 501 505 505 506 506 506 506 507 507 507 507 507 508 508 508 508 509

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List of Tables

Table 19-18. Matching Explicit Verilog Edge Transitions to Verilog . . . . . . . . . . . . . . . . . Table 19-19. SDF Timing Check Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-20. SDF Path Delay Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 19-21. Disabling Timing Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20-1. VCD Commands and SystemTasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20-2. VCD Dumpport Commands and System Tasks . . . . . . . . . . . . . . . . . . . . . . . . Table 20-3. VCD Commands and System Tasks for Multiple VCD Files . . . . . . . . . . . . . . Table 20-4. Driver States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20-5. State When Direction is Unknown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20-6. Driver Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20-7. Values for file_format Argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 20-8. Sample Driver Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21-2. Tcl Backslash Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21-3. Tcl List Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21-4. Simulator-Specific Tcl Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21-5. Tcl Time Conversion Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21-6. Tcl Time Relation Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21-7. Tcl Time Arithmetic Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 21-8. Commands for Handling Breakpoints and Errors in Macros . . . . . . . . . . . . . . Table A-1. Add Library Mappings to modelsim.ini File . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A-2. AssertionFormat Variable: Accepted Values . . . . . . . . . . . . . . . . . . . . . . . . . . . Table A-3. License Variable: License Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table C-1. Severity Level Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table C-2. Exit Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table D-1. vsim Arguments for DPI Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table D-2. Supported VHDL Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table D-3. Supported ACC Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table D-4. Supported TF Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table D-5. Values for <action> Argument . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table E-1. Command History Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table E-2. Mouse Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table E-3. Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table E-4. List Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table E-5. Wave Window Mouse Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table E-6. Wave Window Keyboard Shortcuts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table F-1. Predefined GUI Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table G-1. Files Accessed During Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table G-2. Environment Variables Accessed During Startup . . . . . . . . . . . . . . . . . . . . . . .

509 509 510 511 519 519 520 524 525 525 527 528 532 534 538 538 540 540 541 548 556 569 575 595 597 629 635 637 639 641 645 646 646 649 650 650 653 661 662

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List of Tables

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Chapter 1 Introduction
This documentation was written for UNIX, Linux, and Microsoft Windows users. Not all versions of ModelSim are supported on all platforms. Contact your Mentor Graphics sales representative for details.

Tool Structure and Flow

The diagram below illustrates the structure of the ModelSim tool, and the flow of that tool as it is used to verify a design.

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Introduction Simulation Task Overview

Figure 1-1. Tool Structure and Flow

VHDL Design Libraries

vlib vmap
local work library

Map libraries

Libraries

Vendor

Design les

vlog/ vcom/ sccom

Analyze/ Compile

.ini or .mpf le

HDL/SystemC Analyze/ Compile

compiled database

vsim
Interactive Debugging activities i.e. Simulation Output (e.g., vcd)

Simulate

Debug

Post-processing Debug

Simulation Task Overview

The following table provides a reference for the tasks required for compiling, loading, and simulating a design in ModelSim.

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Introduction Basic Steps for Simulation

Table 1-1. Simulation Tasks Task Step 1: Map libraries Example Command Line Entry GUI Menu Pull-down GUI Icons N/A

vlib <library_name> a. File > New > Project vmap work <library_name> b. Enter library name c. Add design files to project vlog file1.v file2.v ... (Verilog) vcom file1.vhd file2.vhd ... (VHDL) a. Compile > Compile or Compile > Compile All

Step 2: Compile the design

Compile or Compile All icons:

vsim <top> or Step 3: vsim <opt_name> Load the design into the simulator

a. Simulate > Start Simulation b. Click on top design module or optimized design unit name c. Click OK This action loads the design for simulation Simulate > Run

Simulate icon:

Step 4: Run the simulation

run step

Run, or Run continue, or Run -all icons:

Step 5: Debug the design

Common debugging commands: bp describe drivers examine force log show

N/A

N/A

Basic Steps for Simulation

This section provides further detail related to each step in the process of simulating your design using ModelSim.

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Introduction Basic Steps for Simulation

Step 1 Collecting Files and Mapping Libraries

Files needed to run ModelSim on your design: design files (VHDL, Verilog, and/or SystemC), including stimulus for the design libraries, both working and resource modelsim.ini (automatically created by the library mapping command

Providing Stimulus to the Design

You can provide stimulus to your design in several ways: Language based testbench Tcl-based ModelSim interactive command, force VCD files / commands See Creating a VCD File and Using Extended VCD as Stimulus 3rd party testbench generation tools

What is a Library?
A library is a location where data to be used for simulation is stored. Libraries are ModelSims way of managing the creation of data before it is needed for use in simulation. It also serves as a way to streamline simulation invocation. Instead of compiling all design data each and every time you simulate, ModelSim uses binary pre-compiled data from these libraries. So, if you make a changes to a single Verilog module, only that module is recompiled, rather than all modules in the design.

Working and Resource Libraries

Design libraries can be used in two ways: 1) as a local working library that contains the compiled version of your design; 2) as a resource library. The contents of your working library will change as you update your design and recompile. A resource library is typically unchanging, and serves as a parts source for your design. Examples of resource libraries might be: shared information within your group, vendor libraries, packages, or previously compiled elements of your own working design. You can create your own resource libraries, or they may be supplied by another design team or a third party (e.g., a silicon vendor). For more information on resource libraries and working libraries, see Working Library Versus Resource Libraries, Managing Library Contents, Working with Design Libraries, and Specifying the Resource Libraries.

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Introduction Basic Steps for Simulation

Creating the Logical Library (vlib)

Before you can compile your source files, you must create a library in which to store the compilation results. You can create the logical library using the GUI, using File > New > Library (see Creating a Library), or you can use the vlib command. For example, the command:
vlib work

creates a library named work. By default, compilation results are stored in the work library.

Mapping the Logical Work to the Physical Work Directory (vmap)

VHDL uses logical library names that can be mapped to ModelSim library directories. If libraries are not mapped properly, and you invoke your simulation, necessary components will not be loaded and simulation will fail. Similarly, compilation can also depend on proper library mapping. By default, ModelSim can find libraries in your current directory (assuming they have the right name), but for it to find libraries located elsewhere, you need to map a logical library name to the pathname of the library. You can use the GUI (Library Mappings with the GUI, a command (Library Mapping from the Command Line), or a project (Getting Started with Projects to assign a logical name to a design library. The format for command line entry is:
vmap <logical_name> <directory_pathname>

This command sets the mapping between a logical library name and a directory.

Step 2 Compiling the Design (vlog, vcom, sccom)

Designs are compiled with one of the three language compilers.

Compiling Verilog (vlog)

ModelSims compiler for the Verilog modules in your design is vlog. Verilog files may be compiled in any order, as they are not order dependent. See Compiling Verilog Files for details.

Compiling VHDL (vcom)

ModelSims compiler for VHDL design units is vcom. VHDL files must be compiled according to the design requirements of the design. Projects may assist you in determining the compile order: for more information, see Auto-Generating Compile Order. See Compiling VHDL Files for details. on VHDL compilation.

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Introduction Basic Steps for Simulation

Compiling SystemC (sccom)

ModelSims compiler for SystemC design units is sccom, and is used only if you have SystemC components in your design. See Compiling SystemC Files for details.

Step 3 Loading the Design for Simulation

vsim topLevelModule
Your design is ready for simulation after it has been compiled. You may then invoke vsim with the names of the top-level modules (many designs contain only one top-level module). For example, if your top-level modules are "testbench" and "globals", then invoke the simulator as follows:
vsim testbench globals

After the simulator loads the top-level modules, it iteratively loads the instantiated modules and UDPs in the design hierarchy, linking the design together by connecting the ports and resolving hierarchical references.

Using SDF
You can incorporate actual delay values to the simulation by applying SDF back-annotation files to the design. For more information on how SDF is used in the design, see Specifying SDF Files for Simulation.

Step 4 Simulating the Design

Once the design has been successfully loaded, the simulation time is set to zero, and you must enter a run command to begin simulation. For more information, see Verilog and SystemVerilog Simulation, SystemC Simulation, and VHDL Simulation. The basic simulator commands are: add wave force bp run step

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Introduction Modes of Operation

Step 5 Debugging the Design

Numerous tools and windows useful in debugging your design are available from the ModelSim GUI. In addition, several basic simulation commands are available from the command line to assist you in debugging your design: describe drivers examine force log show

Modes of Operation
Many users run ModelSim interactivelypushing buttons and/or pulling down menus in a series of windows in the GUI (graphical user interface). But there are really three modes of ModelSim operation, the characteristics of which are outlined in the following table.: Table 1-2. Use Modes ModelSim use mode GUI Characteristics How ModelSim is invoked

interactive; has graphical via a desktop icon or from the OS command windows, push-buttons, shell prompt. Example: OS> vsim menus, and a command line in the transcript. Default mode interactive command line; no GUI with -c argument at the OS command prompt. Example:
OS> vsim -c

Command-line

Batch

at OS command shell prompt using redirection non-interactive batch of standard input. Example: script; no windows or C:\ vsim vfiles.v <infile >outfile interactive command line

The ModelSim Users Manual focuses primarily on the GUI mode of operation. However, this section provides an introduction to the Command-line and Batch modes.

Command Line Mode

In command line mode ModelSim executes any startup command specified by the Startup variable in the modelsim.ini file. If vsim is invoked with the -do "command_string" option, a

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Introduction Modes of Operation

DO file (macro) is called. A DO file executed in this manner will override any startup command in the modelsim.ini file. During simulation a transcript file is created containing any messages to stdout. A transcript file created in command line mode may be used as a DO file if you invoke the transcript on command after the design loads (see the example below). The transcript on command writes all of the commands you invoke to the transcript file. For example, the following series of commands results in a transcript file that can be used for command input if top is re-simulated (remove the quit -f command from the transcript file if you want to remain in the simulator).
vsim -c top

library and design loading messages then execute:

transcript on force clk 1 50, 0 100 -repeat 100 run 500 run @5000 quit -f

Rename transcript files that you intend to use as DO files. They will be overwritten the next time you run vsim if you dont rename them. Also, simulator messages are already commented out, but any messages generated from your design (and subsequently written to the transcript file) will cause the simulator to pause. A transcript file that contains only valid simulator commands will work fine; comment out anything else with a "#". Stand-alone tools pick up project settings in command line mode if they are invoked in the project's root directory. If invoked outside the project directory, stand-alone tools pick up project settings only if you set the MODELSIM environment variable to the path to the project file (<Project_Root_Dir>/<Project_Name>.mpf).

Batch Mode
Batch mode is an operational mode that provides neither an interactive command line nor interactive windows. In a Windows environment, vsim is run from a Windows command prompt and standard input and output are redirected from and to files. Here is an example of a batch mode simulation using redirection of std input and output:
vsim counter < yourfile > outfile

where "yourfile" is a script containing various ModelSim commands. You can use the CTRL-C keyboard interrupt to break batch simulation in UNIX and Windows environments.

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Introduction Standards Supported

Standards Supported
ModelSim VHDL implements the VHDL language as defined by IEEE Standards 1076-1987, 1076-1993, and 1076-2002. ModelSim also supports the 1164-1993 Standard Multivalue Logic System for VHDL Interoperability, and the 1076.2-1996 Standard VHDL Mathematical Packages standards. Any design developed with ModelSim will be compatible with any other VHDL system that is compliant with the 1076 specs. ModelSim Verilog implements the Verilog language as defined by the IEEE Std 1364-1995 and 1364-2005. ModelSim Verilog also supports a partial implementation of SystemVerilog P18002005 (see /<install_dir>/modeltech/docs/technotes/sysvlog.note for implementation details). Both PLI (Programming Language Interface) and VCD (Value Change Dump) are supported for ModelSim users. In addition, all products support SDF 1.0 through 4.0 (except the NETDELAY statement), VITAL 2.2b, VITAL95 IEEE 1076.4-1995, and VITAL 2000 IEEE 1076.4-2000. ModelSim implements the SystemC language based on the Open SystemC Initiative (OSCI) SystemC 2.1 reference simulator.

Assumptions
We assume that you are familiar with the use of your operating system and its graphical interface. We also assume that you have a working knowledge of the design languages. Although ModelSim is an excellent tool to use while learning HDL concepts and practices, this document is not written to support that goal. Finally, we assume that you have worked the appropriate lessons in the ModelSim Tutorial and are familiar with the basic functionality of ModelSim. The ModelSim Tutorial is available from the ModelSim Help menu. The ModelSim Tutorial is also available from the Support page of our web site:
www.model.com

Sections In This Document

In addition to this introduction, you will find the following major sections in this document: Chapter 3, Projects This chapter discusses ModelSim "projects", a container for design files and their associated simulation properties.

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Introduction Sections In This Document

Chapter 4, Design Libraries To simulate an HDL design using ModelSim, you need to know how to create, compile, maintain, and delete design libraries as described in this chapter. Chapter 5, VHDL Simulation This chapter is an overview of compilation and simulation for VHDL within the ModelSim environment. Chapter 6, Verilog and SystemVerilog Simulation This chapter is an overview of compilation and simulation for Verilog and SystemVerilog within the ModelSim environment. Chapter 7, SystemC Simulation This chapter is an overview of preparation, compilation, and simulation for SystemC within the ModelSim environment. Chapter 8, Mixed-Language Simulation This chapter outlines data mapping and the criteria established to instantiate design units between languages. Chapter 10, WLF Files (Datasets) and Virtuals This chapter describes datasets and virtuals - both methods for viewing and organizing simulation data in ModelSim. Chapter 11, Waveform Analysis This chapter describes how to perform waveform analysis with the ModelSim Wave and List windows. Chapter 12, Tracing Signals with the Dataflow Window This chapter describes how to trace signals and assess causality using the ModelSim Dataflow window. Chapter 13, Coverage This chapter describes the Code Coverage feature. Code Coverage gives you graphical and report file feedback on how the source code is being executed. Chapter 15, C Debug This chapter describes C Debug, a graphic interface to the gdb debugger that can be used to debug FLI/PLI/VPI/SystemC C/C++ source code. Chapter 16, Profiling Performance and Memory Use This chapter describes how the ModelSim Performance Analyzer is used to easily identify areas in your simulation where performance can be improved. Chapter 17, Signal Spy This chapter describes Signal Spy, a set of VHDL procedures and Verilog system tasks that let you monitor, drive, force, or release a design object from anywhere in the hierarchy of a VHDL or mixed design. Chapter 19, Standard Delay Format (SDF) Timing Annotation This chapter discusses ModelSims implementation of SDF (Standard Delay Format) timing annotation. Included are sections on VITAL SDF and Verilog SDF, plus troubleshooting. Chapter 20, Value Change Dump (VCD) Files This chapter explains Model Technologys Verilog VCD implementation for ModelSim. The VCD usage is extended to include VHDL designs. Chapter 21, Tcl and Macros (DO Files) This chapter provides an overview of Tcl (tool command language) as used with ModelSim.

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Introduction What is an "Object"

Appendix A, Simulator Variables This appendix describes environment, system, and preference variables used in ModelSim. Appendix C, Error and Warning Messages This appendix describes ModelSim error and warning messages. Appendix D, Verilog PLI/VPI/DPI This appendix describes the ModelSim implementation of the Verilog PLI and VPI. Appendix E, Command and Keyboard Shortcuts This appendix describes ModelSim keyboard and mouse shortcuts. Appendix G, System Initialization This appendix describes what happens during ModelSim startup. Appendix H, Logic Modeling SmartModels This appendix describes the use of the SmartModel Library and SmartModel Windows with ModelSim.

What is an "Object"
Because ModelSim works with so many languages (SystemC, Verilog, VHDL, SystemVerilog, ), an object refers to any valid design element in those languages. The word "object" is used whenever a specific language reference is not needed. Depending on the context, object can refer to any of the following: Table 1-3. Definition of Object by Language Language VHDL An object can be block statement, component instantiation, constant, generate statement, generic, package, signal, alias, or variable function, module instantiation, named fork, named begin, net, task, register, or variable In addition to those listed above for Verilog: class, package, program, interface, array, directive, property, or sequence module, channel, port, variable, or aggregate property, sequence, directive, or endpoint

Verilog SystemVerilog

SystemC PSL

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Introduction Text Conventions

Text Conventions
Text conventions used in this manual include: Table 1-4. Text Conventions Text Type italic text bold text Description provides emphasis and sets off filenames, pathnames, and design unit names indicates commands, command options, menu choices, package and library logical names, as well as variables, dialog box selections, and language keywords monospace type is used for program and command examples is used to connect menu choices when traversing menus as in: File > Quit denotes file types used by ModelSim (e.g., DO, WLF, INI, MPF, PDF, etc.)

monospace type

The right angle (>) UPPER CASE

Installation Directory Pathnames

When referring to installation paths, this manual uses modeltech as a generic representation of the installation directory for all versions of ModelSim. The actual installation directory on your system may contain version information.

Where to Find Our Documentation

ModelSim documentation is available from our website at
www.model.com/support

or from the tool in the following formats and locations: Table 1-5. Documentation List Document Installation & Licensing Guide Quick Guide (command and feature quick-reference) Format PDF HTML PDF How to get it Help > PDF Bookcase Help > Help & Manuals displays the InfoHub Select the Release Management tab Help > PDF Bookcase

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Introduction Technical Support and Updates

Table 1-5. Documentation List Document Tutorial Format PDF HTML Users Manual PDF HTML Reference Manual PDF HTML Std_DevelopersKit Users Manual PDF How to get it Help > PDF Bookcase Help > Help & Manuals displays the InfoHub Select the Support & Training tab Help > PDF Bookcase Help > Help & Manuals displays the InfoHub Select the Help & Manuals tab Help > PDF Bookcase Help > Help & Manuals displays the InfoHub Select the Help & Manuals tab www.model.com/support/documentation/BOO K/sdk_um.pdf The Standard Developers Kit is for use with Mentor Graphics QuickHDL. type help [command name] at the prompt in the Transcript pane type verror <msgNum> at the Transcript or shell prompt select Help > Tcl Man Pages, or find contents.htm in \modeltech\docs\tcl_help_html available from the support site

Command Help Error message help Tcl Man Pages (Tcl manual) Technotes

ASCII ASCII HTML HTML

Download a Free PDF Reader With Search

ModelSim PDF documentation requires an Adobe Acrobat Reader for viewing. The Reader is available without cost from Adobe at
www.adobe.com.

Technical Support and Updates

Support
Online and email technical support options, maintenance renewal, and links to international support contacts:
www.model.com/support/default.asp

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Introduction Technical Support and Updates

Updates
Access to the most current version of ModelSim:
www.model.com/downloads/default.asp

Latest Version Email

Place your name on our list for email notification of news and updates:
ww.model.com/products/informant.asp

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Chapter 2 Simulator Windows

ModelSims graphical user interface (GUI) consists of various windows that give access to parts of your design and numerous debugging tools. Some of the windows display as panes within the ModelSim Main window and some display as windows in the Multiple Document Interface (MDI) frame. Figure 2-1. Graphical User Interface

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Simulator Windows

The following table summarizes all of the available windows and panes. Table 2-1. GUI Windows and Panes Window/pane name Description Main Active Processes central GUI access point More details Main Window

displays all processes that are scheduled Active Processes Pane to run during the current simulation cycle a collection of panes that display code coverage data displays "physical" connectivity and lets you trace events (causality) shows waveform data in a tabular format Code Coverage Panes Dataflow Window List Window

Code coverage Dataflow List Locals

Locals Pane displays data objects that are immediately visible at the current PC of the selected process a Workspace tab and MDI windows that show memories and their contents Memory Panes

Memory Watch Objects Profile Source Transcript

displays signal or variable values at the Watch Pane current simulation time displays all declared data objects in the current scope Objects Pane

two panes that display performance and Profile Panes memory profiling data a text editor for viewing and editing HDL, SystemC, DO, etc. files Source Window

Transcript keeps a running history of commands and messages and provides a commandline interface displays waveforms provides easy access to projects, libraries, compiled design units, memories, etc. Wave Window Workspace

Wave Workspace

The windows and panes are customizable in that you can position and size them as you see fit, and ModelSim will remember your settings upon subsequent invocations. See Navigating the Graphic User Interface for more details.

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Simulator Windows Design Object Icons and Their Meaning

Design Object Icons and Their Meaning

The color and shape of icons convey information about the language and type of a design object. shows the icon colors and the languages they indicate. Table 2-2. Design Object Icons Icon color light blue dark blue green orange Design Language Verilog or SystemVerilog VHDL SystemC virtual object

Here is a list of icon shapes and the design object types they indicate: Table 2-3. Icon Shapes and Design Object Types icon shape square circle diamond caution sign diamond with red dot star example design object type any scope (VHDL block, Verilog named block, SC module, class, interface, task, function, etc.) process valued object (signals, nets, registers, SystemC channel, etc.) comparison object an editable waveform created with the waveform editor transaction; The color of the star for each transaction depends on the language of the region in which the transaction stream occurs: dark blue for VHDL, light blue for Verilog and SystemVerilog, green for SystemC, magenta for PSL.

Setting Fonts
You may need to adjust font settings to accommodate the aspect ratios of wide screen and double screen displays or to handle launching ModelSim from an X-session.

Font Scaling
To change font scaling, select Tools > Options > Adjust Font Scaling. Youll need a ruler to complete the instructions in the lower right corner of the dialog. When you have entered the

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Simulator Windows Main Window

pixel and inches information, click OK to close the dialog. Then, restart ModelSim to see the change. This is a one time setting; you shouldn't have to set it again unless you change display resolution or the hardware (monitor or video card). The font scaling applies to Windows and UNIX operating systems. On UNIX systems, the font scaling is stored based on the $DISPLAY environment variable.

Controlling Fonts in an X-session

When executed via an X-session (e.g., Exceed, VNC), ModelSim uses font definitions from the .Xdefaults file. To ensure that the fonts look correct, create a .Xdefaults file with the following lines:
vsim*Font: -adobe-courier-medium-r-normal--*-120-*-*-*-*-* vsim*SystemFont: -adobe-courier-medium-r-normal--*-120-*-*-*-*-* vsim*StandardFont: -adobe-courier-medium-r-normal--*-120-*-*-*-*-* vsim*MenuFont: -adobe-courier-medium-r-normal--*-120-*-*-*-*-*

Alternatively, you can choose a different font. Use the program "xlsfonts" to identify which fonts are available on your system. Also, the following command can be used to update the X resources if you make changes to the .Xdefaults and wish to use those changes on a UNIX machine:
xrdb -merge .Xdefaults

Main Window
The primary access point in the ModelSim GUI is called the Main window. It provides convenient access to design libraries and objects, source files, debugging commands, simulation status messages, etc. When you load a design, or bring up debugging tools, ModelSim adds panes or opens windows appropriate for your debugging environment (Figure 2-2).

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Simulator Windows Main Window

Figure 2-2. Main Window

Workspace tabs organize design elements in a hierarchical tree structure

The Transcript pane reports status and provides a commandline interface

The Objects pane displays data objects in the current scope

Multiple document interface (MDI) pane

Notice some of the elements that appear: Workspace tabs organize and display design objects in a hierarchical tree format The Transcript pane tracks command history and messages and provides a commandline interface where you can enter ModelSim commands The Objects pane displays design objects such as signals, nets, generics, etc. in the current design scope

Workspace
The Workspace provides convenient access to projects, libraries, design files, compiled design units, simulation/dataset structures, and Waveform Comparison objects. It can be hidden or displayed by selecting View > Windows > Workspace (Main window). The Workspace can display the types of tabs listed below.

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Simulator Windows Main Window

Project tab Shows all files that are included in the open project. Refer to Projects for details. Library tab Shows design libraries and compiled design units. To update the current view of the library, select a library, and then Right click > Update. See Managing Library Contents for details on library management. Structure tabs Shows a hierarchical view of the active simulation and any open datasets. There is one tab for the current simulation (named "sim") and one tab for each open dataset. See Viewing Dataset Structure for details. An entry is created by each object within the design. When you select a region in a structure tab, it becomes the current region and is highlighted. The Source Window and Objects Pane change dynamically to reflect the information for the current region. This feature provides a useful method for finding the source code for a selected region because the system keeps track of the pathname where the source is located and displays it automatically, without the need for you to provide the pathname. Also, when you select a region in the structure pane, the Active Processes Pane is updated. The Active Processes window will in turn update the Locals Pane. Objects can be dragged from the structure tabs to the Dataflow, List and Wave windows. The structure tabs will display code coverage information (see Viewing Coverage Data in the Graphic Interface). You can toggle the display of processes by clicking in a Structure tab and selecting View > Filter > Processes. You can also control implicit wire processes using a preference variable. By default Structure tabs suppress the display of implicit wire processes. To enable the display of implicit wire processes, set PrefMain(HideImplicitWires) to 0 (select Tools > Edit Preferences, By Name tab, and expand the Main object).

Files tab Shows the source files for the loaded design. You can disable the display of this tab by setting the PrefMain(ShowFilePane) preference variable to 0. See Simulator GUI Preferences for information on setting preference variables. The file tab will display code coverage information (see Viewing Coverage Data in the Graphic Interface).

Memories tab Shows a hierarchical list of all memories in the design. To display this tab, select View > Windows > Memory. When you select a memory on the tab, a memory contents page opens in the MDI frame. See Memory Panes. Compare tab Shows comparison objects that were created by doing a waveform comparison. See Waveform Analysis for details.

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Simulator Windows Main Window

Transcript
The Transcript portion of the Main window maintains a running history of commands that are invoked and messages that occur as you work with ModelSim. When a simulation is running, the Transcript displays a VSIM prompt, allowing you to enter command-line commands from within the graphic interface. You can scroll backward and forward through the current work history by using the vertical scrollbar. You can also use arrow keys to recall previous commands, or copy and paste using the mouse within the window (see Main and Source Window Mouse and Keyboard Shortcuts for details).

Saving the Transcript File

Variable settings determine the filename used for saving the transcript. If either PrefMain(file) in the .modelsim file or TranscriptFile in the modelsim.ini file is set, then the transcript output is logged to the specified file. By default the TranscriptFile variable in modelsim.ini is set to transcript. If either variable is set, the transcript contents are always saved and no explicit saving is necessary. If you would like to save an additional copy of the transcript with a different filename, click in the Transcript pane and then select File > Save As, or File > Save. The initial save must be made with the Save As selection, which stores the filename in the Tcl variable PrefMain(saveFile). Subsequent saves can be made with the Save selection. Since no automatic saves are performed for this file, it is written only when you invoke a Save command. The file is written to the specified directory and records the contents of the transcript at the time of the save.

Using the Saved Transcript as a Macro (DO file)

Saved transcript files can be used as macros (DO files). Refer to the do command for more information.

Changing the Number of Lines Saved in the Transcript Window

By default, the Transcript window retains the last 5000 lines of output from the transcript. You can change this default by altering the saveLines preference variable. Setting this variable to 0 instructs the tool to retain all lines of the transcript. See Simulator GUI Preferences for details on setting preference variables.

Disabling Creation of the Transcript File

You can disable the creation of the transcript file by using the following ModelSim command immediately after ModelSim starts:
transcript file ""

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Simulator Windows Main Window

Automatic Command Help

When you start typing a command at the Transcript prompt, a dropdown box appears which lists the available commands matching what has been typed so far. You may use the Up and Down arrow keys or the mouse to select the desired command. When a unique command has been entered, the command usage is presented in the drop down box. You can disable this feature by selecting Help > Command Completion or by setting the PrefMain(EnableCommandHelp) preference variable to 0. See Simulator GUI Preferences for details on setting preference variables.

Message Viewer
The Message Viewer tab, found in the Transcript pane, allows you to easily access, organize, and analyze any Note, Warning, Error or other elaboration and runtime messages written to the transcript during the simulation run. By default, the tool writes transcripted messages to both the transcript and the WLF file. By writing to the WLF file, the Message Viewer tab is able to organize the messages for your analysis.

Controlling the Message Viewer Data

Command Line The -msgmode argument to vsim controls where the simulator outputs the messages.
vsim -msgmode {both | tran | wlf}

where:
o o

both outputs messages to both the transcript and the WLF file. Default behavior. tran outputs messages only to the transcript, therefore they are not available in the Message Viewer. wlf outputs messages only to the WLF file/Message Viewer, therefore they are not available in the transcript.

modelsim.ini File The msgmode variable in the modelsim.ini file accepts the same values described above for the -msgmode argument.

Message Viewer Interface and Tasks

The Message Viewer tab does not display by default. You can bring it up after a simulation run with the View > Message Viewer menu item. The message viewer is also automatically displayed when you perform the dataset open command. Figure 2-3 and Table 2-4 provide an overview of the Message Viewer and several tasks you can perform.

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Simulator Windows Main Window

Figure 2-3. Message Viewer Tab

Table 2-4. Message Viewer Tasks Icon Task 1 2 3 4 Display a detailed description of the message. Action right click the message text then select View Verbose Message.

Open the source file and add a bookmark to double click the object name(s). the location of the object(s). Change the focus of the Workspace and Objects panes. double click the hierarchical reference.

Open the source file and set a marker at the double click the file name. line number.

Multiple Document Interface (MDI) Frame

The MDI frame is an area in the Main window where source editor, memory content, wave, and list windows display. The frame allows multiple windows to be displayed simultaneously, as shown below. A tab appears for each window.

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Simulator Windows Organizing Windows with Tab Groups

Figure 2-4. Tabs in the MDI Frame

Object name

Window tabs

The object name is displayed in the title bar at the top of the window. You can switch between the windows by clicking on a tab.

Organizing Windows with Tab Groups

The MDI can quickly become unwieldy if many windows are open. You can create "tab groups" to help organize the windows. A tab group is a collection of tabs that are separated from other groups of tabs. Figure 2-5 shows how the collection of files in Figure 2-4 could be organized into two tab groups.

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Simulator Windows Navigating in the Main Window

Figure 2-5. Organizing Files in Tab Groups

The commands for creating and organizing tab groups are accessed by right-clicking on any window tab. The table below describes the commands associated with tab groups: Table 2-5. Commands for Tab Groups Command New Tab Group Move Next Group Move Prev Group View > Vertical / Horizontal Description Creates a new tab group containing the selected tab Moves the selected tab to the next group in the MDI Moves the selected tab to the previous group in the MDI Arranges tab groups top-to-bottom (vertical) or right-to-left (horizontal)

Note that you can also move the tabs within a tab group by dragging them with the middle mouse button.

Navigating in the Main Window

The Main window can contain of a number of "panes" and sub-windows that display various types of information about your design, simulation, or debugging session. Here are a few important points to keep in mind about the Main window interface: Windows/panes can be resized, moved, zoomed, undocked, etc. and the changes are persistent.

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Simulator Windows Navigating in the Main Window

You have a number of options for re-sizing, re-positioning, undocking/redocking, and generally modifying the physical characteristics of windows and panes. Windows and panes can be undocked from the main window by pressing the Undock button in the header or by using the view -undock <window_name> command. For example, view -undock objects will undock the Objects window. The default docked or undocked status of each window or pane can be set with the PrefMain(ViewUnDocked) <window_name> preference variable. When you exit ModelSim, the current layout is saved so that it appears the same the next time you invoke the tool. Menus are context sensitive. The menu items that are available and how certain menu items behave depend on which pane or window is active. For example, if the sim tab in the Workspace is active and you choose Edit from the menu bar, the Clear command is disabled. However, if you click in the Transcript pane and choose Edit, the Clear command is enabled. The active pane is denoted by a blue title bar. For more information, see Navigating the Graphic User Interface.

Main Window Status Bar

Figure 2-6. Main Window Status Bar

Fields at the bottom of the Main window provide the following information about the current simulation: Table 2-6. Information Displayed in Status Bar Field Project Now Delta Profile Samples Memory environment line/column Description name of the current project the current simulation time the current simulation iteration number the number of profile samples collected during the current simulation the total memory used during the current simulation name of the current context (object selected in the active Structure tab of the Workspace) line and column numbers of the cursor in the active Source window

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Main Window Toolbar

Buttons on the Main window toolbar give you quick access to various ModelSim commands and functions. Table 2-7. Main Window Toolbar Buttons Button New File create a new source file Open open the Open File dialog Save save the contents of the active pane Print open the Print dialog Cut cut the selected text to the clipboard Copy copy the selected text to the clipboard Paste paste the clipboard text Undo undo the last edit Redo redo the last undone edit Find find text in the active window Collapse All collapse all instances in the active window Expand All expand all instance in the active window Menu equivalent File > New > Source Command equivalents

File > Open

File > Save

File > Print

Edit > Cut

Edit > Copy

Edit > Paste

Edit > Undo

Edit > Redo

Edit > Find Edit > Expand > Collapse All

Edit > Expand > Expand All

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Simulator Windows Navigating in the Main Window

Table 2-7. Main Window Toolbar Buttons Button Compile open the Compile Source Files dialog to select files for compilation Compile All compile all files in the open project Simulate load the selected design unit or simulation configuration object Break stop the current simulation run Environment up move up one level in the design hierarchy Environment back navigate backward to a previously selected context Environment forward navigate forward to a previously selected context Simulate > Run > Restart Restart reload the design elements and reset the simulation time to zero, with the option of maintaining various settings and objects Run Length specify the run length for the current simulation Run run the current simulation for the specified run length Continue Run continue the current simulation run until the end of the specified run length or until it hits a breakpoint or specified break event Simulate > Runtime Options restart Menu equivalent Compile > Compile Command equivalents vcom vlog vcom vlog vsim

Compile > Compile All

Simulate > Start Simulation

Simulate > Break

run

Simulate > Run > Run default_run_length Simulate > Run > Continue

run

run -continue

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Simulator Windows Navigating in the Main Window

Table 2-7. Main Window Toolbar Buttons Button Run -All run the current simulation forever, or until it hits a breakpoint or specified break event Step step the current simulation to the next statement Menu equivalent Simulate > Run > Run -All Command equivalents run -all

Simulate > Run > Step

step

Simulate > Run > Step Over Step -Over HDL statements are executed but treated as simple statements instead of entered and traced line by line C Interrupt reactivates the C debugger when stopped in HDL code Tools > C Debug > C Interrupt

step -over

cdbg interrupt

Memory Profiling Tools > Profile > Memory enable collection of memory usage data Performance Profiling enable collection of statistical performance data Tools > Profile > Performance

Contains filter items in Objects pane Previous Zero Hits jump to previous line with zero coverage Next Zero Hits jump to next line with zero coverage Show Language Templates display language templates View > Source > Show Language Templates

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Simulator Windows Active Processes Pane

Active Processes Pane

The Active Processes pane displays a list of HDL and SystemC processes. Processes are also displayed in the structure tabs of the Main window Workspace. To filter displayed processes in the structure tabs, select View > Filter > Processes. Figure 2-7. Active Processes Pane

Process Status
Each object in the scrollbox is preceded by one of the following indicators: <Ready> Indicates that the process is scheduled to be executed within the current delta time. If you select a "Ready" process, it will be executed next by the simulator. <Wait> Indicates that the process is waiting for a VHDL signal or Verilog net or variable to change or for a specified time-out period. SystemC objects cannot be in a Wait state. <Done> Indicates that the process has executed a VHDL wait statement without a time-out or a sensitivity list. The process will not restart during the current simulation run. SystemC objects cannot be in a Done state.

Call Stack Pane

The Call Stack pane displays the current call stack when you single step your simulation or when the simulation has encountered a breakpoint. When debugging your design, you can use the call stack data to analyze the depth of function calls, which include Verilog functions and tasks and VHDL functions and procedures, that led up to the current point of the simulation. Accessing the Call Stack Pane View > Call Stack

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Simulator Windows Call Stack Pane

Figure 2-8. Call Stack Pane

Using the Call Stack Pane The Call Stack pane contains five columns of information to assist you in debugging your design: # indicates the depth of the function call, with the most recent at the top. In indicates the function. Line indicates the line number containing the function call. File indicates the location of the file containing the function call. Address indicates the address of the execution in a foreign subprogram, such as C.

The Call Stack pane allows you to perform the following actions within the pane: Double-click on the line of any function call:
o o

Displays the local variables at that level in the Locals Pane. Displays the corresponding source code in the Source Window.

Right-click in the column headings

o

Displays a pop-up window that allows you to show or hide columns.

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Simulator Windows Code Coverage Panes

Code Coverage Panes

When you run simulations with code coverage enabled, a number of panes in the Main window will display code coverage data.

Table 2-8. Panes that Show Code Coverage Data Icon Panes with Coverage Data 1 2 3 4 5 6 Workspace Missed Coverage Instance Coverage Details Current Exclusions Objects

Figure 2-9. Panes that Show Code Coverage Data

Current Coverage

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These panes dissect and organize the data collected during coverage analysis. Each pane contains context menus (right-click in the pane to access the menus) with commands appropriate to that pane. You can hide and show the panes by selecting View > Coverage. For details about using code coverage refer to the Coverage chapter.

Workspace Pane
The Workspace pane displays code coverage information in the Files tab and in the structure tabs (e.g., the sim tab) that display structure for any datasets being simulated. When coverage is invoked, several columns for displaying coverage data are added to the Workspace pane. You can toggle columns on/off by right-clicking on a column name and selecting from the context menu that appears. The following code coverage-related columns appear in the Workspace pane: Table 2-9. Coverage Columns in the Workspace Pane Column name Stmt count Description in the Files tab, the number of executable statements in each file; in the sim tab, the number of executable statements in each level and all levels under that level in the Files tab, the number of executable statements that were executed in each file; in the sim tab, the number of executable statements that were executed in each level and all levels under that level in the Files tab, the number of executable statements that were not executed in each file; in the sim tab, the number of executable statements that were not executed in each level and all levels under that level the current ratio of Stmt hits to Stmt count a bar chart displaying the Stmt %; if the percentage is below 90%, the bar is red; 90% or more, the bar is green; you can change this threshold percentage by editing the PrefCoverage(cutoff) preference variable in the Files tab, the number of executable branches in each file; in the sim tab, the number of executable branches in each level and all levels under that level the number of executable branches that have been executed in the current simulation the number of executable branches that were not executed in the current simulation the current ratio of Branch hits to Branch count a bar chart displaying the Branch %; if the percentage is below 90%, the bar is red; 90% or more, the bar is green; you can change this threshold percentage by editing the PrefCoverage(cutoff) preference variable

Stmt hits

Stmt misses

Stmt % Stmt graph

Branch count

Branch hits Branch misses Branch % Branch graph

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Table 2-9. Coverage Columns in the Workspace Pane Column name Condition rows Condition hits Description in the Files tab, the number of conditions in each file; in the sim tab, the number of conditions in each level and all levels under that level in the Files tab, the number of times the conditions in a file have been executed; in the sim tab, the number of times the conditions in a level, and all levels under that level, have been executed in the Files tab, the number of conditions in a file that were not executed; in the sim tab, the number of conditions in a level, and all levels under that level, that were not executed the current ratio of Condition hits to Condition rows a bar chart displaying the Condition %; if the percentage is below 90%, the bar is red; 90% or more, the bar is green; you can change this threshold percentage by editing the PrefCoverage(cutoff) preference variable in the Files tab, the number of executable expressions in each file; in the sim tab, the number of executable expressions in each level and all levels subsumed under that level in the Files tab, the number of times expressions in a file have been executed; in the sim tab, the number of times expressions in a level, and each level under that level, have been executed in the Files tab, the number of executable expressions in a file that were not executed; in the sim tab, the number of executable expressions in a level, and all levels under that level, that were not executed the current ratio of Expression hits to Expression rows a bar chart displaying the Expression %; if the percentage is below 90%, the bar is red; 90% or more, the bar is green; you can change this threshold percentage by editing the PrefCoverage(cutoff) preference variable the number of points in each instance where the logic will transition from one state to another the number of nodes in each instance that have transitioned at least once the number of nodes in each instance that have not transitioned at least once the current ratio of Toggle hits to Toggle nodes a bar chart displaying the Toggle %; if the percentage is below 90%, the bar is red; 90% or more, the bar is green; you can change this threshold percentage by editing the PrefCoverage(cutoff) preference variable

Condition misses

Condition % Condition graph

Expression rows

Expression hits

Expression misses

Expression % Expression graph

Toggle nodes Toggle hits Toggle misses Toggle % Toggle graph

Figure 2-10 shows a portion of the Workspace window pane with code coverage data displayed.

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Figure 2-10. Code Coverage Data in the Workspace

You can sort code coverage information for any column by clicking the column heading. Clicking the column heading again will reverse the order. Coverage information in the Workspace pane is dynamically linked to the Missed Coverage pane and the Current Exclusions pane. Click the left mouse button on any file in the Workspace pane to display that files un-executed statements, branches, conditions, expressions, and toggles in the Missed Coverage pane. Lines from the selected file that are excluded from coverage statistics are displayed in the Current Exclusions pane.

Missed Coverage Pane

When you select a file in the Workspace pane, the Missed Coverage pane displays that uncovered (missed) statements, branches, conditions, and expressions, as well as signals that havent toggled, and finite state machines (FSM) with uncovered states and transitions. The pane includes a tab for each object, as shown below. Figure 2-11. Missed Coverage Pane

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Each tab includes a column for the line number and a column for statement, branch, condition, expression, or toggle on that line. The "X" indicates the object was not executed. When you select (left-click) any object in the Branch, Condition, Expression or Toggle tabs, the Details Pane populates with related details (coverage statistic details, truth tables, and so on) about that object. The Branch tab also includes a column for branch code (conditional "if/then/else" and "case" statements). "XT" indicates that only the true condition of the branch was not executed. "XF" indicates that only the false condition of the branch was not executed. Fractional numbers indicate how many case statement labels were not executed. For example, if only one of six case labels executed, the Branch tab would indicate "X 1/6." Figure 2-12. Branch Tab in the Missed Coverage Pane

When you right-click any object in the Statement, Branch, Condition, or Expression tabs you can select Exclude Selection or Exclude Selection for Instance <name> to exclude the object from coverage statistics and make it appear in the Current Exclusions pane.

Current Exclusions Pane

The Current Exclusions pane lists all files and lines that are excluded from coverage statistics. See Excluding Objects from Coverage for more details.

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Figure 2-13. Current Exclusions Pane

The pane does not display by default. Select View > Code Coverage > Current Exclusions to display the it.

Instance Coverage Pane

The Instance Coverage pane displays coverage statistics for each instance in a flat, nonhierarchical view. It allows sorting of data columns to be more meaningful, and not confused by hierarchy. The Instance Coverage pane contains the same code coverage statistics columns as in the Workspace pane. A partial view of the Instance Coverage pane is shown below. Figure 2-14. Instance Coverage Pane

Details Pane
After code coverage is invoked and the simulation is loaded and run, you can turn on the Details pane by selecting View > Code Coverage > Details. The Details pane shows the details of missed coverage. When you select (left-click) an object in the Missed Coverage pane, the details of that coverage are displayed in the Details pane. Truth tables will be displayed for condition and expression coverage, as shown here.

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Figure 2-15. Details Pane Showing Condition Truth Table

For a description of these truth tables, see Coverage Statistics Details. Toggle details are displayed as follows: Figure 2-16. Details Pane Showing Toggle Details

By clicking the left mouse button on the statement Hits column in the Source window, all coverage information for that line will be displayed in the Details pane as shown here:

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Figure 2-17. Details Pane Showing Information from Source Window

Objects Pane Toggle Coverage

Toggle coverage data is displayed in the Objects pane in multiple columns, as shown below. There is a column for each of the six transition types. Figure 2-18. Toggle Coverage in the Objects Pane

Right click any column name to toggle a column on or off.

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The following table provides a description of the available columns: Table 2-10. Toggle Coverage Columns in the Objects Pane Column name Name Value Kind Mode 1H -> 0L 0L -> 1H 0L -> Z Z -> 0L 1H -> Z Z -> 1H State Count State Hits State % # Nodes # Toggled % Toggled % 01 % Full %Z Description the name of each object in the current region the current value of each object the object type the object mode (internal, in, out, etc.) the number of times each object has transitioned from a 1 or a High state to a 0 or a Low state the number of times each object has transitioned from a 0 or a Low state to 1 or a High state the number of times each object has transitioned from a 0 or a Low state to a high impedance (Z) state the number of times each object has transitioned from a high impedance state to a 0 or a Low state the number of times each object has transitioned from a 1 or a High state to a high impedance state the number of times each object has transitioned from a high impedance state to 1 or a High state the number of values a state machine variable can have the number of state machine variable values that have been hit the current ration of State Hits to State Count the number of scalar bits in each object the number of nodes that have transitioned at least once the current ratio of the # Toggled to the # Nodes for each object the percentage of 1H -> 0L and 0L -> 1H transitions that have occurred (transitions in the first two columns) the percentage of all transitions that have occurred (all six columns) the percentage of 0L -> Z, Z -> 0L, 1H -> Z, and Z -> 1H transitions that have occurred (last four columns)

Code Coverage Toolbar

When you simulate with code coverage enabled, the following toolbar is added to the Main window.

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Figure 2-19. Code Coverage Toolbar

Table 2-11. Code Coverage Toolbar Description Icon or Field Description Enable Filtering enables display filtering of coverage statistics in the Workspace and Instance Coverage panes of the Main window Threshold above displays all coverage statistics above the Filter Threshold for selected columns Threshold below displays all coverage statistics below the Filter Threshold for selected columns Filter Threshold specifies the display coverage percentage for the selected coverage columns Statement applies the display filter to all Statement coverage columns in the Workspace and Instance Coverage panes of the Main window Branch applies the display filter to all Branch coverage columns in the Workspace and Instance Coverage panes of the Main window Condition applies the display filter to all Condition coverage columns in the Workspace and Instance Coverage panes of the Main window Expression applies the display filter to all Expression coverage columns in the Workspace and Instance Coverage panes of the Main window Toggle applies the display filter to all Toggle coverage columns in the Workspace and Instance Coverage panes of the Main window

Dataflow Window
The Dataflow window allows you to explore the "physical" connectivity of your design. It also allows you to trace events that propagate through the design; and to identify the cause of unexpected outputs.

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Note ModelSim versions operating without a dataow license feature have limited Dataow functionality. Without the license feature, the window will show only one process and its attached signals or one signal and its attached processes. Figure 2-20. Dataflow Window

The Dataflow window displays: processes signals, nets, and registers interconnects

The window has built-in mappings for all Verilog primitive gates (i.e., AND, OR, PMOS, NMOS, etc.). For components other than Verilog primitives, you can define a mapping between processes and built-in symbols. See Symbol Mapping for details. Note You cannot view SystemC objects in the Dataflow window.

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Dataflow Window Toolbar

The buttons on the Dataflow window toolbar are described below. Table 2-12. Dataflow Window Toolbar Button Print print the current view of the Dataflow window Select mode set left mouse button to select mode and middle mouse button to zoom mode Zoom mode set left mouse button to zoom mode and middle mouse button to pan mode Pan mode set left mouse button to pan mode and middle mouse button to zoom mode Cut cut the selected object(s) Menu equivalent File > Print (Windows) File > Print Postscript (UNIX) View > Select

View > Zoom

View > Pan

Edit > Cut

Copy copy the selected object(s)

Edit > Copy

Paste paste the previously cut or copied object(s) Undo undo the last action

Edit > Paste Edit > Undo

Redo redo the last undone action

Edit > Redo

Find search for an instance or signal

Edit > Find

Trace input net to event move the next event cursor to the next input event driving the selected output Trace Set jump to the source of the selected input event

Trace > Trace next event

Trace > Trace event set

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Table 2-12. Dataflow Window Toolbar Button Trace Reset return the next event cursor to the selected output Trace net to driver of X step back to the last driver of an unknown value Expand net to all drivers display driver(s) of the selected signal, net, or register Menu equivalent Trace > Trace event reset

Trace > TraceX

Navigate > Expand net to drivers

Expand net to all drivers and readers display Navigate > Expand net driver(s) and reader(s) of the selected signal, net, or register Expand net to all readers display reader(s) of the selected signal, net, or register Erase highlight clear the green highlighting which identifies the path youve traversed through the design Erase all clear the window Navigate > Expand net to readers

Edit > Erase highlight

Edit > Erase all

Regenerate clear and redraw the display using an optimal layout Zoom In zoom in by a factor of two from current view Zoom Out zoom out by a factor of two from current view

Edit > Regenerate

none

none

Zoom Full zoom out to show all components in none the window Stop Drawing halt any drawing currently happening in the window none

Show Wave display the embedded wave viewer View > Show Wave pane

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List Window
The List window displays the results of your simulation run in tabular format. The window is divided into two adjustable columns, which allow you to scroll horizontally through the listing on the right, while keeping time and delta visible on the left. The List window opens by default in the MDI frame of the Main window as shown in Figure 2-21. Figure 2-21. List Window Docked in Main Window MDI Frame

The window can be undocked from the Main window by clicking the Undock button in the window header or by using the view -undock list command.

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Figure 2-22. List Window Undocked

The following type of objects can be viewed in the List pane: VHDL signals, aliases, process variables, and shared variables Verilog nets, registers, and variables SystemC primitive channels and ports Comparisons comparison objects; see Waveform Compare for more information Virtuals Virtual signals and functions

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Locals Pane
The Locals pane displays data objects that are immediately visible from the statement that will be executed next (that statement is denoted by a blue arrow in the Source editor window). The contents of the window change from one statement to the next. The Locals pane includes two columns. The first column lists the names of the immediately visible data objects. The second column lists the current value(s) associated with each name. Figure 2-23. Locals Pane

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Memory Panes
The Main window lists all memories in your design in the Memories tab of the Main window Workspace and displays the contents of a selected memory in the Main window MDI frame. Figure 2-24. Memory Panes

The memory list is from the top-level of the design. In other words, it is not sensitive to the context selected in the Structure tab. ModelSim identifies certain kinds of arrays in various scopes as memories. Memory identification depends on the array element kind as well as the overall array kind (i.e. associative array, unpacked array, etc.). Table 2-13. Memories VHDL Element kind enum1, std_logic_vector, std_bit_vector, or integer. Verilog/SystemVerilog any integral type. (i.e. integer_type): shortint, int, longint, byte, bit (2 state), logic, reg, integer, time (4 state), packed_struct / packed_union (2 state), packed_struct / packed_union (4 state), packed_array (single-Dim, multi-D, 2 state and 4 state), enum or string. module, interface, package, compilation unit, struct, or static variables within a task / function / named block / class any combination of unpacked, dynamic and associative arrays2

Scope: recognizable in

architecture, process, or record

Array kind

single-dimensional or multi-dimensional

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1. These enumerated type value sets must have values that are longer than one character. The listed width is the number of entries in the enumerated type definition and the depth is the size of the array itself. 2. Any combination of unpacked, dynamic, and associative arrays is considered a memory, provided the leaf level of the data structure is a string or an integral type.

Associative Arrays in Verilog/SystemVerilog

For an associative array to be recognized as a memory, the index must be of an integral type (see above) or wildcard type. For associative arrays, the element kind can be any type allowed for fixed-size arrays.

Viewing Single and Multidimensional Memories

Single dimensional arrays of integers are interpreted as 2D memory arrays. In these cases, the word width listed in the Memory List pane is equal to the integer size, and the depth is the size of the array itself. Memories with three or more dimensions display with a plus sign + next to their names in the Memory List. Click the + to show the array indices under that level. When you finally expand down to the 2D level, you can double-click on the index, and the data for the selected 2D slice of the memory will appear in a memory contents pane in the MDI frame.

Viewing Packed Arrays

By default packed dimensions are treated as single vectors in the memory contents pane. To expand packed dimensions of packed arrays, select View > Memory Contents > Expand Packed Memories. To change the permanent default, edit the PrefMemory(ExpandPackedMem) variable. This variable affects only packed arrays. If the variable is set to 1, the packed arrays are treated as unpacked arrays and are expanded along the packed dimensions such that they appear as a linearized bit vector. See Simulator GUI Preferences for details on setting preference variables.

Viewing Memory Contents

When you double-click an instance on the Memory tab, ModelSim automatically displays a memory contents pane in the MDI frame (see Multiple Document Interface (MDI) Frame). You can also enter the command add mem <instance> at the vsim command prompt.

Viewing Multiple Memory Instances

You can view multiple memory instances simultaneously. A memory tab appears in the MDI frame for each instance you double-click in the Memory list.

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Figure 2-25. Viewing Multiple Memories

See Organizing Windows with Tab Groups for more information on tabs.

Saving Memory Formats in a DO File

You can save all open memory instances and their formats (e.g., address radix, data radix, etc.) by creating a DO file. With the memory tab active, select File > Save As. The Save memory format dialog box opens, where you can specify the name for the saved file. By default it is named mem.do. The file will contain all open memory instances and their formats. To load it at a later time, select File > Load.

Direct Address Navigation

You can navigate to any address location directly by editing the address in the address column. Double-click on any address, type in the desired address, and hit Enter. The address display scrolls to the specified location.

Splitting the Memory Contents Pane

To split a memory contents window into two screens displaying the contents of a single memory instance, so any one of the following: select Memories > Split Screen if the Memory Contents Pane is docked in the Main window, select View > Split Screen if the Memory Contents Pane is undocked, right-click in the pane and select Split Screen from the pop-up menu.

This allows you to view different address locations within the same memory instance simultaneously.

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Figure 2-26. Split Screen View of Memory Contents

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Objects Pane
The Objects pane shows the names and current values of declared data objects in the current region (selected in the structure tabs of the Workspace). Data objects include signals, nets, registers, constants and variables not declared in a process, generics, parameters, and SystemC transactions and member data variables. Clicking an entry in the window highlights that object in the Dataflow and Wave windows. Double-clicking an entry highlights that object in a Source editor window (opening a Source editor window if one is not open already). You can also right click an object name and add it to the List or Wave window, or the current log file. Figure 2-27. Objects Pane

Filtering the Objects List

You can filter the objects list by name or by object type.

Filtering by Name
To filter by name, undock the Objects pane from the Main window and start typing letters in the Contains field in the toolbar. Figure 2-28. Objects Filter

As you type, the objects list filters to show only those signals that contain those letters.

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Figure 2-29. Filtering the Objects List by Name

To display all objects again, click the Eraser icon to clear the entry. Filters are stored relative to the region selected in the Structure window. If you re-select a region that had a filter applied, that filter is restored. This allows you to apply different filters to different regions.

Filtering by Signal Type

The View > Filter menu selection allows you to specify which signal types to display in the Objects window. Multiple options can be selected.

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Profile Panes
The Profile and Profile Details panes display the results of statistical performance and memory allocation profiling. By default, both panes are displayed within the Main window but they can be undocked from the Main window to stand alone. Each pane contains three tabs for displaying profile results: Ranked, Call Tree, and Structural. For details about using the profiler refer to Profiling Performance and Memory Use. Figure 2-30. Profile Pane

Figure 2-31. Profile Details Pane

Profile Pane Columns

The Profile panes include the columns described below. Name lists the filename of an HDL function or instance, and the line number at which it appears. Most useful names consist of a line of VHDL or Verilog source code. If you use a PLI/VPI or FLI routine, then the name of the C function that implements that routine can also appear in the Name column. Under (raw) lists the raw number of Profiler samples collected during the execution of a function, including all support routines under that function; or, the number of
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samples collected for an instance, including all instances beneath it in the structural hierarchy. In (raw) lists the raw number of Profiler samples collected during a function or instance. Under% lists the ratio (as a percentage) of the samples collected during the execution of a function and all support routines under that function to the total number of samples collected; or, the ratio of the samples collected during an instance, including all instances beneath it in the structural hierarchy, to the total number of samples collected. In% lists the ratio (as a percentage) of the total samples collected during a function or instance. %Parent (not in Ranked view) lists the ratio, as a percentage, of the samples collected during the execution of a function or instance to the samples collected in the parent function or instance. Mem under lists the amount of memory allocated to a function, including all support routines under that function; or, the amount of memory allocated to an instance, including all instances beneath it in the structural hierarchy. Mem in lists the amount of memory allocated to a function or instance. Mem under (%) lists the ratio (as a percentage) of the amount of memory allocated to a function and all of its support routines to the total memory available; or, the ratio of the amount of memory allocated to an instance, including all instances beneath it in the structural hierarchy, to the total memory available. Mem in (%) lists the ratio (as a percentage) of the amount of memory allocated to a function or instance to the total memory available. %Parent lists (not in Ranked view) the ratio, as a percentage, of the memory allocated to a function or instance to the memory allocated to the parent function or instance.

Profiler Toolbar
The Ranked, Call Tree and Structural views all share a toolbar in the Main window. The table below describes the icons in this toolbar. Table 2-14. Profiler Toolbar Button Memory Profiling enable collection of memory usage data Menu equivalent Tools > Profile > Memory Command equivalents

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Table 2-14. Profiler Toolbar Button Performance Profiling enable collection of statistical performance data Collapse Sections on/off toggling of reporting for collapsed processes and functions. Profile Cutoff display performance and memory profile data equal to or greater than set percentage Refresh profile data refresh profile performance and memory data after changing profile cutoff Save profile results save profile data to output file (prompts for file name) Profile Find search for the named string in the Profile pane Tools > Profile > Profile Report profile report Menu equivalent Tools > Profile > Performance Command equivalents

Tools > Profile > Collapse Sections

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Source Window
Source files display by default in the MDI frame of the Main window. The window can be undocked from the Main window by pressing the Undock button in the window header or by using the view -undock source command. You can edit source files as well as set breakpoints, step through design files, and view code coverage statistics. By default, the Source window displays your source code with line numbers. You may also see the following graphic elements: Red line numbers denote lines on which you can set a breakpoint Blue arrow denotes the currently active line or a process that you have selected in the Active Processes Pane Red circles denote file-line breakpoints; gray circles denote breakpoints that are currently disabled Blue circles denote line bookmarks Language Templates pane displays Language Templates (Figure 2-32) Figure 2-32. Source Window Showing Language Templates

Opening Source Files

You can open source files using the File > Open command. Alternatively, you can open source files by double-clicking objects in other windows. For example, if you double-click an item in

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the Objects window or in the structure tab of the Workspace, the underlying source file for the object will open, and the cursor will scroll to the line where the object is defined. By default files you open from within the design (e.g., by double-clicking an object in the Objects pane) open in Read Only mode. To make the file editable, right-click in the Source window and select Read Only. To change this default behavior, set the PrefSource(ReadOnly) variable to 0. See Simulator GUI Preferences for details on setting preference variables.

Displaying Multiple Source Files

By default each file you open or create is marked by a window tab, as shown in the graphic below. Figure 2-33. Displaying Multiple Source Files

See Organizing Windows with Tab Groups for more information on these tabs.

Dragging and Dropping Objects into the Wave and List Windows
ModelSim allows you to drag and drop objects from the Source window to the Wave and List windows. Double-click an object to highlight it, then drag the object to the Wave or List window. To place a group of objects into the Wave and List windows, drag and drop any section of highlighted code.

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Setting your Context by Navigating Source Files

When debugging your design from within the GUI, you can change your context while analyzing your source files. Figure 2-34 shows the pop-up menu the tool displays after you select then right-click an instance name in a source file. Figure 2-34. Setting Context from Source Files

This functionality allows you to easily navigate your design for debugging purposes by remembering where you have been, similar to the functionality in most web browsers. The navigation options in the pop-up menu function as follows: Open Instance changes your context to the instance you have selected within the source file. This is not available if you have not placed your cursor in, or highlighted the name of, an instance within your source file. If any ambiguities exists, most likely due to generate statements, this option opens a dialog box allowing you to choose from all available instances. Ascend Env changes your context to the next level up within the design. This is not available if you are at the top-level of your design.

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Forward/Back allows you to change to previously selected contexts. This is not available if you have not changed your context.

The Open Instance option is essentially executing an environment command to change your context, therefore any time you use this command manually at the command prompt, that information is also saved for use with the Forward/Back options.

Debugging with Source Annotation

With source annotation you can interactively debug your design by analyzing your source files in addition to using the Wave and Signal windows. Source annotation displays simulation values, including transitions, for each signal in your source file. Figure 2-35 shows an example of source annotation, where the red values are added below the signals. Figure 2-35. Source Annotation Example

Turn on source annotation by selecting View > Source > Show Source Annotation or by rightclicking a source file and selecting Show Source Annotation. Note that transitions are displayed only for those signals that you have logged. To analyze the values at a given time of the simulation you can either: Show the signal values at the current simulation time. This is the default behavior. The window automatically updates the values as you perform a run or a single-step action. Show the signal values at current cursor position in the Wave window.

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You can switch between these two settings by performing the following actions: 1. Tools > Edit Preferences > By Window tab 2. select Source Windows in the Window List box 3. select Annotation in the Category box 4. select Use Values: at Active Waveform cursor or Current simulation time. You can highlight a specific signal in the Wave window by double-clicking on an annotation value in the source file.

Language Templates
ModelSim language templates help you write code. They are a collection of wizards, menus, and dialogs that produce code for new designs, testbenches, language constructs, logic blocks, etc. Note The language templates are not intended to replace thorough knowledge of coding. They are intended as an interactive "reference" for creating small sections of code. If you are unfamiliar with a particular language, you should attend a training class or consult one of the many available books. To use the templates, either open an existing file, or select File > New > Source to create a new file. Once the file is open, select Source > Show Language Templates if the Source window is docked in the Main window; select View > Show Language Templates of the Source window is undocked. This displays a pane that shows the available templates.

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Figure 2-36. Language Templates

The templates that appear depend on the type of file you create. For example Module and Primitive templates are available for Verilog files, and Entity and Architecture templates are available for VHDL files. Double-click an object in the list to open a wizard or to begin creating code. Some of the objects bring up wizards while others insert code into your source file. The dialog below is part of the wizard for creating a new design. Simply follow the directions in the wizards. Figure 2-37. Create New Design Wizard

Code inserted into your source contains a variety of highlighted fields. The example below shows a module statement inserted from the Verilog template.

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Figure 2-38. Inserting Module Statement from Verilog Language Template

Some of the fields, such as module_name in the example above, are to be replaced with names you type. Other fields can be expanded by double-clicking and still others offer a context menu of options when double-clicked. The example below shows the menu that appears when you double-click module_item then select gate_instantiation. Figure 2-39. Language Template Context Menus

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Setting File-Line Breakpoints

You can easily set File-line breakpoints in a Source window using your mouse. Click on a red line number at the left side of the Source window, and a red circle denoting a breakpoint will appear. The breakpoints are toggles click once to create the breakpoint; click again to disable or enable the breakpoint. To delete the breakpoint completely, right click the red circle, and select Remove Breakpoint. Other options on the context menu include: Disable/Enable Breakpoint Deactivate or activate the selected breakpoint. Edit Breakpoint Open the File Breakpoint dialog to change breakpoint arguments. Edit All Breakpoints Open the Modify Breakpoints dialog

Checking Object Values and Descriptions

There are two quick methods to determine the value and description of an object displayed in the Source window: select an object, then right-click and select Examine or Describe from the context menu pause over an object with your mouse pointer to see an examine pop-up

Select Tools > Options > Examine Now or Tools > Options > Examine Current Cursor to choose at what simulation time the object is examined or described. You can also invoke the examine and/or describe commands on the command line or in a macro.

Marking Lines with Bookmarks

Source window bookmarks are blue circles that mark lines in a source file. These graphical icons may ease navigation through a large source file by "highlighting" certain lines. As noted above in the discussion about finding text in the Source window, you can insert bookmarks on any line containing the text for which you are searching. The other method for inserting bookmarks is to right-click a line number and select Add/Remove Bookmark. To remove a bookmark, right-click the line number and select Add/Remove Bookmark again.

Customizing the Source Window

You can customize a variety of settings for Source windows. For example, you can change fonts, spacing, colors, syntax highlighting, and so forth. To customize Source window settings, select Tools > Edit Preferences. This opens the Preferences dialog. Select Source Windows from the Window List.

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Figure 2-40. Preferences Dialog for Customizing Source Window

Select an item from the Category list and then edit the available properties on the right. Click OK or Apply to accept the changes. The changes will be active for the next Source window you open. The changes are saved automatically when you quit ModelSim.

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Watch Pane
The Watch pane shows values for signals and variables at the current simulation time. Unlike the Objects or Locals pane, the Watch pane allows you to view any signal or variable in the design regardless of the current context. Figure 2-41. .Watch Pane

You can view the following objects in the watch pane. VHDL objects signals, aliases, generics, constants, and variables Verilog objects nets, registers, variables, named events, and module parameters SystemC objects primitive channels and ports Virtual objects virtual signals and virtual functions

Adding Objects to the Pane

To add objects to the Watch pane, drag-and-drop objects from the Structure tab, Objects pane, or Locals pane. Alternatively, use the add watch command.

Expanding Objects to Show Individual Bits

If you add an array or record to the Watch pane, you can view individual bit values by doubleclicking the array or record. As shown in the graphic above, /ram_tb/dpram1/inaddr has been

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expanded to show all the individual bit values. Notice the arrow that "ties" the array to the individual bit display.

Grouping and Ungrouping Objects

You can group objects in the Watch pane so they display and move together. Select the objects, then right click one of the objects and choose Group. In the graphic below, two different sets of objects have been grouped together. Figure 2-42. Grouping Objects in the Watch Pane

To ungroup them, right-click the group and select Ungroup.

Saving and Reloading Format Files

You can save a format file (a DO file, actually) that will redraw the contents of the Watch window. Right-click anywhere in the window and select Save Format. Once you have saved the file, you can reload it by right-clicking and selecting Load Format.

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Wave Window
The Wave window, like the List window, allows you to view the results of your simulation. In the Wave window, however, you can see the results as waveforms and their values. The Wave window opens by default in the MDI frame of the Main window as shown below. The window can be undocked from the main window by clicking the Undock button in the window header or by using the view -undock wave command. The preference variable PrefMain(ViewUnDocked) wave can be used to control this default behavior. Setting this variable will open the Wave Window undocked each time you start ModelSim. Figure 2-43. Wave Window Undock Button

Here is an example of a Wave window that is undocked from the MDI frame. All menus and icons associated with Wave window functions now appear in the menu and toolbar areas of the Wave window.

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Figure 2-44. Wave Window Dock Button

If the Wave window is docked into the Main window MDI frame, all menus and icons that were in the standalone version of the Wave window move into the Main window menu bar and toolbar. The Wave window is divided into a number of window panes. All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes.

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Example 2-1. Wave Window Panes

The following types of objects can be viewed in the Wave window VHDL objects (indicated by a dark blue diamond) signals, aliases, process variables, and shared variables Verilog objects (indicated by a light blue diamond) nets, registers, variables, and named events SystemC objects (indicated by a green diamond) primitive channels and ports (indicated by a green four point star) transaction streams and their element Virtual objects (indicated by an orange diamond) virtual signals, buses, and functions, see; Virtual Objects for more information Comparison objects (indicated by a yellow triangle) comparison region and comparison signals; see Waveform Compare for more information Created waveforms (indicated by a red dot on a diamond) see Generating Stimulus with Waveform Editor

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The data in the object values pane is very similar to the Objects window, except that the values change dynamically whenever a cursor in the waveform pane is moved. At the bottom of the waveform pane you can see a time line, tick marks, and the time value of each cursors position. As you click and drag to move a cursor, the time value at the cursor location is updated at the bottom of the cursor. You can resize the window panes by clicking on the bar between them and dragging the bar to a new location. Waveform and signal-name formatting are easily changed via the Format menu. You can reuse any formatting changes you make by saving a Wave window format file (see Saving the Window Format).

Wave Window Panes

The sections below describe the various Wave window panes.

Pathname Pane
The pathname pane displays signal pathnames. Signals can be displayed with full pathnames, as shown here, or with only the leaf element displayed. You can increase the size of the pane by clicking and dragging on the right border. The selected signal is highlighted. The white bar along the left margin indicates the selected dataset (see Splitting Wave Window Panes).

Value Pane
The value pane displays the values of the displayed signals. The radix for each signal can be symbolic, binary, octal, decimal, unsigned, hexadecimal, ASCII, or default. The default radix can be set by selecting Simulate > Runtime Options. Note When the symbolic radix is chosen for SystemVerilog reg and integer types, the values are treated as binary. When the symbolic radix is chosen for SystemVerilog bit and int types, the values are considered to be decimal. The data in this pane is similar to that shown in the Objects Pane, except that the values change dynamically whenever a cursor in the waveform pane is moved.

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Waveform Pane
The waveform pane displays the waveforms that correspond to the displayed signal pathnames. It also displays up to 20 cursors. Signal values can be displayed in analog step, analog interpolated, analog backstep, literal, logic, and event formats. The radix of each signal can be set individually by selecting the signal and then choosing . The default radix is logic. If you rest your mouse pointer on a signal in the waveform pane, a popup displays with information about the signal. You can toggle this popup on and off in the Wave Window Properties dialog. Dashed signal lines in the waveform pane indicate weak or ambiguous strengths of Verilog states. See Verilog States in the Mixed-Language Simulation chapter.

Cursor Panes
There are three cursor panesthe left pane shows the cursor names; the middle pane shows the current simulation time and the value for each cursor; and the right pane shows the absolute time value for each cursor and relative time between cursors. Up to 20 cursors can be displayed. See Measuring Time with Cursors in the Wave Window for more information.

Wave Window Toolbar

The Wave window toolbar (in the undocked Wave window) gives you quick access to these ModelSim commands and functions. Table 2-15. Wave Window Toolbar Buttons and Menu Selections Button Open Dataset open a previously saved dataset Menu equivalent File > Open Other options File > Open from Main window when Transcript window sim tab is active none

File > Save Save Format save the current Wave window display and signal preferences to a DO (macro) file Print print a user-selected range of the current Wave window display to a printer or a file Export Waveform export a created waveform

File > Print none File > Print Postscript

File > Export > Waveform

none

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Table 2-15. Wave Window Toolbar Buttons and Menu Selections Button Menu equivalent Edit > Cut Cut cut the selected signal from the Wave window Edit > Copy Copy copy the signal selected in the pathname pane Paste paste the copied signal above another selected signal Find find a name or value in the Wave window Insert Cursor add a cursor to the waveform pane Edit > Paste Other options right mouse in pathname pane > Cut right mouse in pathname pane > Copy right mouse in pathname pane > Paste <control-f> Windows <control-s> UNIX

Edit > Find

Add > Wave > Cursor right click in cursor pane and select New Cursor (Main window) Add > Cursor (undocked Wave window) right mouse in cursor pane > Delete Cursor n keyboard: Shift + Tab

Edit > Delete Cursor Delete Cursor delete the selected cursor from the window Find Previous Transition locate the previous signal value change for the selected signal Find Next Transition locate the next signal value change for the selected signal Select Mode set mouse to Select Mode click left mouse button to select, drag middle mouse button to zoom Zoom Mode set mouse to Zoom Mode drag left mouse button to zoom, click middle mouse button to select Zoom In 2x zoom in by a factor of two from the current view Edit > Search (Search Reverse)

Edit > Search (Search Forward)

keyboard: Tab

none View > Zoom > Mouse Mode > Select Mode

none View > Zoom > Mouse Mode > Zoom Mode

View > Zoom > Zoom keyboard: i I or + In right mouse in wave pane > Zoom In

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Table 2-15. Wave Window Toolbar Buttons and Menu Selections Button Zoom Out 2x zoom out by a factor of two from current view Zoom in on Active Cursor center active cursor in the display and zoom in Zoom Full zoom out to view the full range of the simulation from time 0 to the current time Stop Wave Drawing halts any waves currently being drawn in the Wave window Menu equivalent Other options View > Zoom > Zoom keyboard: o O or Out right mouse in wave pane > Zoom Out View > Zoom > Zoom keyboard: c or C Cursor View > Zoom > Zoom keyboard: f or F Full right mouse in wave pane > Zoom Full none

[Dataflow window] Show Drivers Navigate > Expand display driver(s) of the selected signal, net, or register net to drivers in the Dataflow window Restart reloads the design elements and resets the simulation time to zero, with the option of keeping the current formatting, breakpoints, and WLF file Run run the current simulation for the default time length Continue Run continue the current simulation run Run -All run the current simulation forever, or until it hits a breakpoint or specified break event Main menu: Simulate > Run > Restart

[Dataflow window] Expand net to all drivers right mouse in wave pane > Show Drivers restart <arguments>

use the run command at the Main menu: Simulate > Run > Run VSIM prompt <default_length> Main menu: Simulate > Run > Continue use the run -continue command at the VSIM prompt

use the run -all command at Main menu: Simulate > Run > Run the VSIM prompt -All

Break none stop the current simulation run

none

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Table 2-15. Wave Window Toolbar Buttons and Menu Selections Button Find First Difference find the first difference in a waveform comparison Find Previous Annotated Difference find the previous annotated difference in a waveform comparison Menu equivalent none Other options none

none

none

none Find Previous Difference find the previous difference in a waveform comparison Find Next Difference find the next difference in a waveform comparison Find Next Annotated Difference find the next annotated difference in a waveform comparison Find Last Difference find the last difference in a waveform comparison none

none

none

none

none

none

none

Wave Edit Toolbar

ModelSims waveform editor has its own toolbar. The toolbar becomes active once you add an editable wave to the Wave window, or if you right-click a blank area of the toolbar and select Wave_edit from the toolbar popup menu. Refer to Generating Stimulus with Waveform Editor for more details. Table 2-16. Waveform Editor Toolbar Buttons and Menu Selections Button Cut Wave cut the selected section of the waveform to the clipboard Menu equivalent1 Edit > Cut Other options wave edit cut

Edit > Copy Copy Wave copy the selected section of the waveform to the clipboard

wave edit copy

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Table 2-16. Waveform Editor Toolbar Buttons and Menu Selections Button Paste Wave paste the wave from the clipboard Insert Pulse Insert a transition at the selected time Delete Edge Delete the selected transition Invert Invert the selected section of the waveform Mirror Mirror the selected section of the waveform Change Value Change the value of the selected section of the waveform Stretch Edge Move the selected edge by increasing/decreasing waveform duration Menu equivalent1 Edit > Paste Other options wave edit paste

Edit > Wave > Insert Pulse Edit > Wave > Delete Edge Edit > Wave > Invert

wave edit insert_pulse

wave edit delete

wave edit invert

Edit > Wave > Mirror

wave edit mirror

Edit > Wave > Value

wave edit change_value

Edit > Wave > Stretch Edge

wave edit stretch

Edit > Wave > Move Move Edge Edge Move the selected edge without increasing/decreasing waveform duration Extend All Waves Increase the duration of all editable waves Wave Undo Undo a previous waveform edit Wave Redo Redo a previously undone waveform edit Edit > Wave > Extend All Waves Edit > Edit Wave > Undo Edit > Edit Wave > Redo

wave edit move

wave edit extend

wave edit undo

wave edit redo

1. Menu equivalents are menu selections made with the Wave window undocked. When the Wave window is docked in the MDI frame of the Main window. Use the Wave > Wave Editor menu selections.

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Chapter 3 Projects
Projects simplify the process of compiling and simulating a design and are a great tool for getting started with ModelSim.

What are Projects?

Projects are collection entities for designs under specification or test. At a minimum, projects have a root directory, a work library, and "metadata" which are stored in a .mpf file located in a project's root directory. The metadata include compiler switch settings, compile order, and file mappings. Projects may also include: Source files or references to source files other files such as READMEs or other project documentation local libraries references to global libraries Simulation Configurations (see Creating a Simulation Configuration) Folders (see Organizing Projects with Folders) Note Project metadata are updated and stored only for actions taken within the project itself. For example, if you have a file in a project, and you compile that file from the command line rather than using the project menu commands, the project will not update to reflect any new compile settings.

What are the Benefits of Projects?

Projects offer benefits to both new and advanced users. Projects simplify interaction with ModelSim; you dont need to understand the intricacies of compiler switches and library mappings eliminate the need to remember a conceptual model of the design; the compile order is maintained for you in the project. Compile order is maintained for HDL-only designs. remove the necessity to re-establish compiler switches and settings at each session; these are stored in the project metadata as are mappings to source files

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allow users to share libraries without copying files to a local directory; you can establish references to source files that are stored remotely or locally allow you to change individual parameters across multiple files; in previous versions you could only set parameters one file at a time enable "what-if" analysis; you can copy a project, manipulate the settings, and rerun it to observe the new results reload the initial settings from the project .mpf file every time the project is opened

Project Conversion Between Versions

Projects are generally not backwards compatible for either number or letter releases. When you open a project created in an earlier version, you will see a message warning that the project will be converted to the newer version. You have the option of continuing with the conversion or cancelling the operation. As stated in the warning message, a backup of the original project is created before the conversion occurs. The backup file is named <project name>.mpf.bak and is created in the same directory in which the original project is located.

Getting Started with Projects

This section describes the four basic steps to working with a project. Step 1 Creating a New Project This creates a .mpf file and a working library. Step 2 Adding Items to the Project Projects can reference or include source files, folders for organization, simulations, and any other files you want to associate with the project. You can copy files into the project directory or simply create mappings to files in other locations. Step 3 Compiling the Files This checks syntax and semantics and creates the pseudo machine code ModelSim uses for simulation. Step 4 Simulating a Design This specifies the design unit you want to simulate and opens a structure tab in the Workspace pane.

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Step 1 Creating a New Project

Select File > New > Project to create a new project. This opens the Create Project dialog where you can specify a project name, location, and default library name. You can generally leave the Default Library Name set to "work." The name you specify will be used to create a working library subdirectory within the Project Location. This dialog also allows you to reference library settings from a selected .ini file or copy them directly into the project. Figure 3-1. Create Project Dialog

After selecting OK, you will see a blank Project tab in the Workspace pane of the Main window (Figure 3-2) Figure 3-2. Project Tab in Workspace Pane

and the Add Items to the Project dialog (Figure 3-3).

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Figure 3-3. Add items to the Project Dialog

The name of the current project is shown at the bottom left corner of the Main window.

Step 2 Adding Items to the Project

The Add Items to the Project dialog includes these options: Create New File Create a new VHDL, Verilog, SystemC, Tcl, or text file using the Source editor. See below for details. Add Existing File Add an existing file. See below for details. Create Simulation Create a Simulation Configuration that specifies source files and simulator options. See Creating a Simulation Configuration for details. Create New Folder Create an organization folder. See Organizing Projects with Folders for details.

Create New File

The File > New > Source menu selections allow you to create a new VHDL, Verilog, SystemC, Tcl, or text file using the Source editor. You can also create a new project file by selecting Project > Add to Project > New File (the Project tab in the Workspace must be active) or right-clicking in the Project tab and selecting Add to Project > New File. This will open the Create Project File dialog (Figure 3-4).

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Figure 3-4. Create Project File Dialog

Specify a name, file type, and folder location for the new file. When you select OK, the file is listed in the Project tab. Double-click the name of the new file and a Source editor window will open, allowing you to create source code.

Add Existing File

You can add an existing file to the project by selecting Project > Add to Project > Existing File or by right-clicking in the Project tab and selecting Add to Project > Existing File. Figure 3-5. Add file to Project Dialog

When you select OK, the file(s) is added to the Project tab.

Step 3 Compiling the Files

The question marks in the Status column in the Project tab denote either the files havent been compiled into the project or the source has changed since the last compile. To compile the files, select Compile > Compile All or right click in the Project tab and select Compile > Compile All (Figure 3-6).

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Figure 3-6. Right-click Compile Menu in Project Tab of Workspace

Once compilation is finished, click the Library tab, expand library work by clicking the "+", and you will see the compiled design units. Figure 3-7. Click Plus Sign to Show Design Hierarchy

Step 4 Simulating a Design

To simulate a design, do one of the following: double-click the Name of an appropriate design object (such as a testbench module or entity) in the Library tab of the Workspace right-click the Name of an appropriate design object and select Simulate from the popup menu

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select Simulate > Start Simulation from the menus to open the Start Simulation dialog (Figure 3-8). Select a design unit in the Design tab. Set other options in the VHDL, Verilog, Libraries, SDF, and Others tabs. Then click OK to start the simulation. Figure 3-8. Start Simulation Dialog

A new tab named sim appears that shows the structure of the active simulation (Figure 3-9). Figure 3-9. Structure Tab of the Workspace

At this point you are ready to run the simulation and analyze your results. You often do this by adding signals to the Wave window and running the simulation for a given period of time. See the ModelSim Tutorial for examples.

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Other Basic Project Operations

Open an Existing Project
If you previously exited ModelSim with a project open, ModelSim automatically will open that same project upon startup. You can open a different project by selecting File > Open and choosing Project Files from the Files of type drop-down.

Close a Project
Right-click in the Project tab and select Close Project. This closes the Project tab but leaves the Library tab open in the workspace. Note that you cannot close a project while a simulation is in progress.

The Project Tab

The Project tab contains information about the objects in your project. By default the tab is divided into five columns. Figure 3-10. Project Displayed in Workspace

Name The name of a file or object. Status Identifies whether a source file has been successfully compiled. Applies only to VHDL or Verilog files. A question mark means the file hasnt been compiled or the source file has changed since the last successful compile; an X means the compile failed; a check mark means the compile succeeded; a checkmark with a yellow triangle behind it means the file compiled but there were warnings generated. Type The file type as determined by registered file types on Windows or the type you specify when you add the file to the project. Order The order in which the file will be compiled when you execute a Compile All command.

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Modified The date and time of the last modification to the file.

You can hide or show columns by right-clicking on a column title and selecting or deselecting entries.

Sorting the List

You can sort the list by any of the five columns. Click on a column heading to sort by that column; click the heading again to invert the sort order. An arrow in the column heading indicates which field the list is sorted by and whether the sort order is descending (down arrow) or ascending (up arrow).

Changing Compile Order

The Compile Order dialog box is functional for HDL-only designs. When you compile all files in a project, ModelSim by default compiles the files in the order in which they were added to the project. You have two alternatives for changing the default compile order: 1) select and compile each file individually; 2) specify a custom compile order. To specify a custom compile order, follow these steps: 1. Select Compile > Compile Order or select it from the context menu in the Project tab. Figure 3-11. Setting Compile Order

2. Drag the files into the correct order or use the up and down arrow buttons. Note that you can select multiple files and drag them simultaneously.

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Auto-Generating Compile Order

Auto Generate is supported for HDL-only designs. The Auto Generate button in the Compile Order dialog (see above) "determines" the correct compile order by making multiple passes over the files. It starts compiling from the top; if a file fails to compile due to dependencies, it moves that file to the bottom and then recompiles it after compiling the rest of the files. It continues in this manner until all files compile successfully or until a file(s) cant be compiled for reasons other than dependency. Files can be displayed in the Project tab in alphabetical or compile order (by clicking the column headings). Keep in mind that the order you see in the Project tab is not necessarily the order in which the files will be compiled.

Grouping Files
You can group two or more files in the Compile Order dialog so they are sent to the compiler at the same time. For example, you might have one file with a bunch of Verilog define statements and a second file that is a Verilog module. You would want to compile these two files together. To group files, follow these steps: 1. Select the files you want to group. Figure 3-12. Grouping Files

2. Click the Group button.

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To ungroup files, select the group and click the Ungroup button.

Creating a Simulation Configuration

A Simulation Configuration associates a design unit(s) and its simulation options. For example, say you routinely load a particular design and you have to specify the simulator resolution, generics, and SDF timing files. Ordinarily you would have to specify those options each time you load the design. With a Simulation Configuration, you would specify the design and those options and then save the configuration with a name (e.g., top_config). The name is then listed in the Project tab and you can double-click it to load the design along with its options. To create a Simulation Configuration, follow these steps: 1. Select Project > Add to Project > Simulation Configuration from the main menu, or right-click the Project tab and select Add to Project > Simulation Configuration from the popup context menu in the Project tab. Figure 3-13. Simulation Configuration Dialog

2. Specify a name in the Simulation Configuration Name field.

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3. Specify the folder in which you want to place the configuration (see Organizing Projects with Folders). 4. Select one or more design unit(s). Use the Control and/or Shift keys to select more than one design unit. The design unit names appear in the Simulate field when you select them. 5. Use the other tabs in the dialog to specify any required simulation options. Click OK and the simulation configuration is added to the Project tab. Figure 3-14. Simulation Configuration in the Project Tab

Double-click the Simulation Configuration verilog_sim to load the design.

Organizing Projects with Folders

The more files you add to a project, the harder it can be to locate the item you need. You can add "folders" to the project to organize your files. These folders are akin to directories in that you can have multiple levels of folders and sub-folders. However, no actual directories are created via the file systemthe folders are present only within the project file.

Adding a Folder
To add a folder to your project, select Project > Add to Project > Folder or right-click in the Project tab and select Add to Project > Folder (Figure 3-15).

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Figure 3-15. Add Folder Dialog

Specify the Folder Name, the location for the folder, and click OK. The folder will be displayed in the Project tab. You use the folders when you add new objects to the project. For example, when you add a file, you can select which folder to place it in. Figure 3-16. Specifying a Project Folder

If you want to move a file into a folder later on, you can do so using the Properties dialog for the file. Simply right-click on the filename in the Project tab and select Properties from the context menu that appears. This will open the Project Compiler Settings Dialog (Figure 3-17). Use the Place in Folder field to specify a folder.

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Figure 3-17. Project Compiler Settings Dialog

On Windows platforms, you can also just drag-and-drop a file into a folder.

Specifying File Properties and Project Settings

You can set two types of properties in a project: file properties and project settings. File properties affect individual files; project settings affect the entire project.

File Compilation Properties

The VHDL and Verilog compilers (vcom and vlog, respectively) have numerous options that affect how a design is compiled and subsequently simulated. You can customize the settings on individual files or a group of files. Note Any changes you make to the compile properties outside of the project, whether from the command line, the GUI, or the modelsim.ini file, will not affect the properties of files already in the project.

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To customize specific files, select the file(s) in the Project tab, right click on the file names, and select Properties. The resulting Project Compiler Settings dialog (Figure 3-18) varies depending on the number and type of files you have selected. If you select a single VHDL or Verilog file, you will see the General tab, Coverage tab, and the VHDL or Verilog tab, respectively. If you select a SystemC file, you will see only the General tab. On the General tab, you will see file properties such as Type, Location, and Size. If you select multiple files, the file properties on the General tab are not listed. Finally, if you select both a VHDL file and a Verilog file, you will see all tabs but no file information on the General tab. Figure 3-18. Specifying File Properties

When setting options on a group of files, keep in mind the following: If two or more files have different settings for the same option, the checkbox in the dialog will be "grayed out." If you change the option, you cannot change it back to a "multi- state setting" without cancelling out of the dialog. Once you click OK, ModelSim will set the option the same for all selected files. If you select a combination of VHDL and Verilog files, the options you set on the VHDL and Verilog tabs apply only to those file types.

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Project Settings
To modify project settings, right-click anywhere within the Project tab and select Project Settings. Figure 3-19. Project Settings Dialog

Converting Pathnames to Softnames for Location Mapping

If you are using location mapping, you can convert a relative pathname, full pathname, or pathname with an environment variable to a softname. A softname is a term for a pathname that uses the location mapping (MGC_LOCATION_MAP). It looks like a pathname containing an environment variable, however it is resolved using the location map rather than the environment. To convert the pathname to a softname for projects using location mapping, follow these steps: 1. Right-click anywhere within the Project tab and select Project Settings 2. Enable the Convert pathnames to softnames within the Location map area of the dialog (Figure 3-19). Once enabled, all pathnames currently in the project and any that are added later are then converted to softnames. During conversion, if there is no softname in the mgc location map matching the entry, the pathname is converted in to a full (hardened) pathname. A pathname is hardened by removing the environment variable or the relative portion of the path. If this happens, any existing

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pathnames that are either relative or use environment variables are also changed: either to softnames if possible, or to hardened pathnames if not. For more information on location mapping and pathnames, see Location Mapping.

Accessing Projects from the Command Line

Generally, projects are used from within the ModelSim GUI. However, standalone tools will use the project file if they are invoked in the project's root directory. If you want to invoke outside the project directory, set the MODELSIM environment variable with the path to the project file (<Project_Root_Dir>/<Project_Name>.mpf). You can also use the project command from the command line to perform common operations on projects.

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Chapter 4 Design Libraries

VHDL designs are associated with libraries, which are objects that contain compiled design units. SystemC, Verilog and SystemVerilog designs simulated within ModelSim are compiled into libraries as well.

Design Library Overview

A design library is a directory or archive that serves as a repository for compiled design units. The design units contained in a design library consist of VHDL entities, packages, architectures, and configurations; Verilog modules and UDPs (user-defined primitives); and SystemC modules. The design units are classified as follows: Primary design units Consist of entities, package declarations, configuration declarations, modulesUDPs, and SystemC modules. Primary design units within a given library must have unique names. Secondary design units Consist of architecture bodies, package bodies. Secondary design units are associated with a primary design unit. Architectures by the same name can exist if they are associated with different entities or modules.

Design Unit Information

The information stored for each design unit in a design library is: retargetable, executable code debugging information dependency information

Working Library Versus Resource Libraries

Design libraries can be used in two ways: 1. as a local working library that contains the compiled version of your design; 2. as a resource library. The contents of your working library will change as you update your design and recompile. A resource library is typically static and serves as a parts source for your design. You can create

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your own resource libraries or they may be supplied by another design team or a third party (e.g., a silicon vendor). Only one library can be the working library. Any number of libraries can be resource libraries during a compilation. You specify which resource libraries will be used when the design is compiled, and there are rules to specify in which order they are searched (refer to Specifying the Resource Libraries). A common example of using both a working library and a resource library is one in which your gate-level design and testbench are compiled into the working library and the design references gate-level models in a separate resource library.

The Library Named "work"

The library named "work" has special attributes within ModelSim it is predefined in the compiler and need not be declared explicitly (i.e. library work). It is also the library name used by the compiler as the default destination of compiled design units (i.e., it does not need to be mapped). In other words, the work library is the default working library.

Archives
By default, design libraries are stored in a directory structure with a sub-directory for each design unit in the library. Alternatively, you can configure a design library to use archives. In this case, each design unit is stored in its own archive file. To create an archive, use the -archive argument to the vlib command. Generally you would do this only in the rare case that you hit the reference count limit on Inodes due to the ".." entries in the lower-level directories (the maximum number of subdirectories on UNIX and Linux is 65533). An example of an error message that is produced when this limit is hit is:
mkdir: cannot create directory `65534': Too many links

Archives may also have limited value to customers seeking disk space savings. Note GMAKE wont work with these archives on the IBM platform.

Working with Design Libraries

The implementation of a design library is not defined within standard VHDL or Verilog. Within ModelSim, design libraries are implemented as directories and can have any legal name allowed by the operating system, with one exception: extended identifiers are not supported for library names.

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Creating a Library
When you create a project (refer to Getting Started with Projects), ModelSim automatically creates a working design library. If you dont create a project, you need to create a working design library before you run the compiler. This can be done from either the command line or from the ModelSim graphic interface. From the ModelSim prompt or a UNIX/DOS prompt, use this vlib command:
vlib <directory_pathname>

To create a new library with the graphic interface, select File > New > Library. Figure 4-1. Creating a New Library

When you click OK, ModelSim creates the specified library directory and writes a speciallyformatted file named _info into that directory. The _info file must remain in the directory to distinguish it as a ModelSim library. The new map entry is written to the modelsim.ini file in the [Library] section. Refer to Library Path Variables for more information. Note Remember that a design library is a special kind of directory. The only way to create a library is to use the ModelSim GUI or the vlib command. Do not try to create libraries using UNIX, DOS, or Windows commands.

Managing Library Contents

Library contents can be viewed, deleted, recompiled, edited and so on using either the graphic interface or command line.

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The Library tab in the Workspace pane provides access to design units (configurations, modules, packages, entities, architectures, and SystemC modules) in a library. Various information about the design units is displayed in columns to the right of the design unit name. Figure 4-2. Design Unit Information in the Workspace

The Library tab has a context menu with various commands that you access by clicking your right mouse button (Windows2nd button, UNIX3rd button) in the Library tab. The context menu includes the following commands: Simulate Loads the selected design unit and opens structure and Files tabs in the workspace. Related command line command is vsim. Simulate with Coverage Loads the selected design unit and collects code coverage data. Related command line command is vsim -coverage. Edit Opens the selected design unit in the Source window; or, if a library is selected, opens the Edit Library Mapping dialog (refer to Library Mappings with the GUI). Refresh Rebuilds the library image of the selected library without using source code. Related command line command is vcom or vlog with the -refresh argument. Recompile Recompiles the selected design unit. Related command line command is vcom or vlog. Update Updates the display of available libraries and design units.

Assigning a Logical Name to a Design Library

VHDL uses logical library names that can be mapped to ModelSim library directories. By default, ModelSim can find libraries in your current directory (assuming they have the right

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name), but for it to find libraries located elsewhere, you need to map a logical library name to the pathname of the library. You can use the GUI, a command, or a project to assign a logical name to a design library.

Library Mappings with the GUI

To associate a logical name with a library, select the library in the workspace, right-click you mouse, and select Edit from the context menu that appears. This brings up a dialog box that allows you to edit the mapping. Figure 4-3. Edit Library Mapping Dialog

The dialog box includes these options: Library Mapping Name The logical name of the library. Library Pathname The pathname to the library.

Library Mapping from the Command Line

You can set the mapping between a logical library name and a directory with the vmap command using the following syntax:
vmap <logical_name> <directory_pathname>

You may invoke this command from either a UNIX/DOS prompt or from the command line within ModelSim. The vmap command adds the mapping to the library section of the modelsim.ini file. You can also modify modelsim.ini manually by adding a mapping line. To do this, use a text editor and add a line under the [Library] section heading using the syntax:
<logical_name> = <directory_pathname>

More than one logical name can be mapped to a single directory. For example, suppose the modelsim.ini file in the current working directory contains following lines:
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Design Libraries Working with Design Libraries [Library] work = /usr/rick/design my_asic = /usr/rick/design

This would allow you to use either the logical name work or my_asic in a library or use clause to refer to the same design library.

Unix Symbolic Links

You can also create a UNIX symbolic link to the library using the host platform command:
ln -s <directory_pathname> <logical_name>

The vmap command can also be used to display the mapping of a logical library name to a directory. To do this, enter the shortened form of the command:
vmap <logical_name>

Library Search Rules

The system searches for the mapping of a logical name in the following order: First the system looks for a modelsim.ini file. If the system doesnt find a modelsim.ini file, or if the specified logical name does not exist in the modelsim.ini file, the system searches the current working directory for a subdirectory that matches the logical name.

An error is generated by the compiler if you specify a logical name that does not resolve to an existing directory.

Moving a Library
Individual design units in a design library cannot be moved. An entire design library can be moved, however, by using standard operating system commands for moving a directory or an archive.

Setting Up Libraries for Group Use

By adding an others clause to your modelsim.ini file, you can have a hierarchy of library mappings. If the tool does not find a mapping in the modelsim.ini file, then it will search the [library] section of the initialization file specified by the others clause. For example:
[library] asic_lib = /cae/asic_lib work = my_work others = /usr/modeltech/modelsim.ini

You can specify only one "others" clause in the library section of a given modelsim.ini file.

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The others clause only instructs the tool to look in the specified modelsim.ini file for a library, it does not load any other part of the specified file.

Specifying the Resource Libraries

Verilog Resource Libraries
ModelSim supports separate compilation of distinct portions of a Verilog design. The vlog compiler is used to compile one or more source files into a specified library. The library thus contains pre-compiled modules and UDPs that are referenced by the simulator as it loads the design. Note Resource libraries are specified differently for Verilog and VHDL. For Verilog you use either the -L or -Lf argument to vlog. Refer to Library Usage for more information.

VHDL Resource Libraries

Within a VHDL source file, you use the VHDL library clause to specify logical names of one or more resource libraries to be referenced in the subsequent design unit. The scope of a library clause includes the text region that starts immediately after the library clause and extends to the end of the declarative region of the associated design unit. It does not extend to the next design unit in the file. Note that the library clause is not used to specify the working library into which the design unit is placed after compilation. The vcom command adds compiled design units to the current working library. By default, this is the library named work. To change the current working library, you can use vcom -work and specify the name of the desired target library.

Predefined Libraries
Certain resource libraries are predefined in standard VHDL. The library named std contains the packages standard and textio, which should not be modified. The contents of these packages and other aspects of the predefined language environment are documented in the IEEE Standard VHDL Language Reference Manual, Std 1076. Refer also to, Using the TextIO Package. A VHDL use clause can be specified to select particular declarations in a library or package that are to be visible within a design unit during compilation. A use clause references the compiled version of the packagenot the source. By default, every VHDL design unit is assumed to contain the following declarations:
LIBRARY std, work; USE std.standard.all

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To specify that all declarations in a library or package can be referenced, add the suffix .all to the library/package name. For example, the use clause above specifies that all declarations in the package standard, in the design library named std, are to be visible to the VHDL design unit immediately following the use clause. Other libraries or packages are not visible unless they are explicitly specified using a library or use clause. Another predefined library is work, the library where a design unit is stored after it is compiled as described earlier. There is no limit to the number of libraries that can be referenced, but only one library is modified during compilation.

Alternate IEEE Libraries Supplied

The installation directory may contain two or more versions of the IEEE library: ieeepure Contains only IEEE approved packages (accelerated for ModelSim). ieee Contains precompiled Synopsys and IEEE arithmetic packages which have been accelerated by Model Technology including math_complex, math_real, numeric_bit, numeric_std, std_logic_1164, std_logic_misc, std_logic_textio, std_logic_arith, std_logic_signed, std_logic_unsigned, vital_primitives, and vital_timing.

You can select which library to use by changing the mapping in the modelsim.ini file. The modelsim.ini file in the installation directory defaults to the ieee library.

Rebuilding Supplied Libraries

Resource libraries are supplied precompiled in the modeltech installation directory. If you need to rebuild these libraries, the sources are provided in the vhdl_src directory; a macro file is also provided for Windows platforms (rebldlibs.do). To rebuild the libraries, invoke the DO file from within ModelSim with this command:
do rbldlibs.do

Make sure your current directory is the modeltech install directory before you run this file. Note Because accelerated subprograms require attributes that are available only under the 1993 standard, many of the libraries are built using vcom with the -93 option. Shell scripts are provided for UNIX (rebuild_libs.csh and rebuild_libs.sh). To rebuild the libraries, execute one of the rebuild_libs scripts while in the modeltech directory.

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Regenerating Your Design Libraries

Depending on your current ModelSim version, you may need to regenerate your design libraries before running a simulation. Check the installation README file to see if your libraries require an update. You can regenerate your design libraries using the Refresh command from the Library tab context menu (refer to Managing Library Contents), or by using the -refresh argument to vcom and vlog. From the command line, you would use vcom with the -refresh argument to update VHDL design units in a library, and vlog with the -refresh argument to update Verilog design units. By default, the work library is updated. Use either vcom or vlog with the -work <library> argument to update a different library. For example, if you have a library named mylib that contains both VHDL and Verilog design units:
vcom -work mylib -refresh vlog -work mylib -refresh

An important feature of -refresh is that it rebuilds the library image without using source code. This means that models delivered as compiled libraries without source code can be rebuilt for a specific release of ModelSim. In general, this works for moving forwards or backwards on a release. Moving backwards on a release may not work if the models used compiler switches, directives, language constructs, or features that do not exist in the older release. Note You don't need to regenerate the std, ieee, vital22b, and verilog libraries. Also, you cannot use the -refresh option to update libraries that were built before the 4.6 release.

Maintaining 32- and 64-bit Versions in the Same Library

ModelSim allows you to maintain 32-bit and 64-bit versions of a design in the same library. To do this, you must compile the design with the 32-bit version and then "refresh" the design with the 64-bit version. For example: Using the 32-bit version of ModelSim:
vlog file1.v file2.v -forcecode -work asic_lib

Next, using the 64-bit version of ModelSim:

vlog -work asic_lib -refresh

This allows you to use either version without having to do a refresh. Do not compile the design with one version, and then recompile it with the other. If you do this, ModelSim will remove the first module, because it could be "stale."

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Design Libraries Importing FPGA Libraries

Importing FPGA Libraries

ModelSim includes an import wizard for referencing and using vendor FPGA libraries. The wizard scans for and enforces dependencies in the libraries and determines the correct mappings and target directories. Note The FPGA libraries you import must be pre-compiled. Most FPGA vendors supply precompiled libraries configured for use with ModelSim. To import an FPGA library, select File > Import > Library. Figure 4-4. Import Library Wizard

Follow the instructions in the wizard to complete the import.

Protecting Source Code Using -nodebug

The -nodebug argument for both vcom and vlog hides internal model data. This allows a model supplier to provide pre-compiled libraries without providing source code and without revealing internal model variables and structure. Note -nodebug encrypts entire files. The Verilog `protect compiler directive allows you to encrypt regions within a file. Refer to Compiler Directives for details.

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Design Libraries Protecting Source Code Using -nodebug

When you compile with -nodebug, all source text, identifiers, and line number information are stripped from the resulting compiled object, so ModelSim cannot locate or display any information of the model except for the external pins. Specifically, this means that: a Source window will not display the design units source code a structure pane will not display the internal structure the Objects pane will not display internal signals the Active Processes pane will not display internal processes the Locals pane will not display internal variables none of the hidden objects may be accessed through the Dataflow window or with ModelSim commands

You can access the design units comprising your model via the library, and you may invoke vsim directly on any of these design units and see the ports. To restrict even this access in the lower levels of your design, you can use the following -nodebug options when you compile: Table 4-1. Compile Options for the -nodebug Compiling Command and Switch vcom -nodebug=ports vlog -nodebug=ports vlog -nodebug=pli vlog -nodebug=ports+pli Result makes the ports of a VHDL design unit invisible makes the ports of a Verilog design unit invisible prevents the use of PLI functions to interrogate the module for information combines the functions of -nodebug=ports and -nodebug=pli

Dont use the =ports option on a design without hierarchy, or on the top level of a hierarchical design. If you do, no ports will be visible for simulation. Rather, compile all lower portions of the design with -nodebug=ports first, then compile the top level with -nodebug alone. Design units or modules compiled with -nodebug can only instantiate design units or modules that are also compiled -nodebug.

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Chapter 5 VHDL Simulation

This chapter describes how to compile, optimize, and simulate VHDL designs in ModelSim. It also discusses using the TextIO package with ModelSim; ModelSims implementation of the VITAL (VHDL Initiative Towards ASIC Libraries) specification for ASIC modeling; and ModelSims special built-in utilities package. The TextIO package is defined within the VHDL Language Reference Manual, IEEE Std 1076; it allows human-readable text input from a declared source within a VHDL file during simulation. Note VHDL is not supported in ModelSim LE.

Basic VHDL Flow

Simulating VHDL designs with ModelSim includes four general steps: 1. Compile your VHDL code into one or more libraries using the vcom command. See Compiling VHDL Files for details. 2. Load your design with the vsim command. See Simulating VHDL Designs for details. 3. Run and debug your design.

Compiling VHDL Files

Creating a Design Library for VHDL
Before you can compile your source files, you must create a library in which to store the compilation results. Use vlib to create a new library. For example:
vlib work

This creates a library named work. By default, compilation results are stored in the work library. The work library is actually a subdirectory named work. This subdirectory contains a special file named _info. Do not create libraries using UNIX, MS Windows, or DOS commands always use the vlib command.
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See Design Libraries for additional information on working with libraries.

Invoking the VHDL Compiler

ModelSim compiles one or more VHDL design units with a single invocation of vcom, the VHDL compiler. The design units are compiled in the order that they appear on the command line. For VHDL, the order of compilation is important you must compile any entities or configurations before an architecture that references them. You can simulate a design containing units written with 1076 -1987, 1076 -1993, and 1076-2002 versions of VHDL. To do so you will need to compile units from each VHDL version separately. The vcom command compiles using 1076 -2002 rules by default; use the -87 or -93 argument to vcom to compile units written with version 1076-1987 or 1076 -1993, respectively. You can also change the default by modifying the VHDL93 variable in the modelsim.ini file (see Simulator Control Variables for more information).

Dependency Checking
Dependent design units must be reanalyzed when the design units they depend on are changed in the library. vcom determines whether or not the compilation results have changed. For example, if you keep an entity and its architectures in the same source file and you modify only an architecture and recompile the source file, the entity compilation results will remain unchanged and you will not have to recompile design units that depend on the entity.

Range and Index Checking

A range check verifies that a scalar value defined with a range subtype is always assigned a value within its range. An index check verifies that whenever an array subscript expression is evaluated, the subscript will be within the array's range. Range and index checks are performed by default when you compile your design. You can disable range checks (potentially offering a performance advantage) and index checks using arguments to the vcom command. Or, you can use the NoRangeCheck and NoIndexCheck variables in the modelsim.ini file to specify whether or not they are performed. See Simulator Control Variables. Range checks in ModelSim are slightly more restrictive than those specified by the VHDL LRM. ModelSim requires any assignment to a signal to also be in range whereas the LRM requires only that range checks be done whenever a signal is updated. Most assignments to signals update the signal anyway, and the more restrictive requirement allows ModelSim to generate better error messages.

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Subprogram Inlining
ModelSim attempts to inline subprograms at compile time to improve simulation performance. This happens automatically and should be largely transparent. However, you can disable automatic inlining two ways: Invoke vcom with the -O0 or -O1 argument Use the mti_inhibit_inline attribute as described below

Single-stepping through a simulation varies slightly depending on whether inlining occurred. When single-stepping to a subprogram call that has not been inlined, the simulator stops first at the line of the call, and then proceeds to the line of the first executable statement in the called subprogram. If the called subprogram has been inlined, the simulator does not first stop at the subprogram call, but stops immediately at the line of the first executable statement.

mti_inhibit_inline Attribute
You can disable inlining for individual design units (a package, architecture, or entity) or subprograms with the mti_inhibit_inline attribute. Follow these rules to use the attribute: Declare the attribute within the design unit's scope as follows:
attribute mti_inhibit_inline : boolean;

Assign the value true to the attribute for the appropriate scope. For example, to inhibit inlining for a particular function (e.g., "foo"), add the following attribute assignment:
attribute mti_inhibit_inline of foo : procedure is true;

To inhibit inlining for a particular package (e.g., "pack"), add the following attribute assignment:
attribute mti_inhibit_inline of pack : package is true;

Do similarly for entities and architectures.

Differences Between Language Versions

There are three versions of the IEEE VHDL 1076 standard: VHDL-1987, VHDL-1993, and VHDL-2002. The default language version for ModelSim is VHDL-2002. If your code was written according to the 87 or 93 version, you may need to update your code or instruct ModelSim to use the earlier versions rules. To select a specific language version, do one of the following: Select the appropriate version from the compiler options menu in the GUI Invoke vcom using the argument -87, -93, or -2002

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Set the VHDL93 variable in the [vcom] section of the modelsim.ini file. Appropriate values for VHDL93 are: - 0, 87, or 1987 for VHDL-1987 - 1, 93, or 1993 for VHDL-1993 - 2, 02, or 2002 for VHDL-2002

The following is a list of language incompatibilities that may cause problems when compiling a design. VHDL-93 and VHDL-2002 The only major problem between VHDL-93 and VHDL2002 is the addition of the keyword "PROTECTED". VHDL-93 programs which use this as an identifier should choose a different name. All other incompatibilities are between VHDL-87 and VHDL-93. VITAL and SDF It is important to use the correct language version for VITAL. VITAL2000 must be compiled with VHDL-93 or VHDL-2002. VITAL95 must be compiled with VHDL-87. A typical error message that indicates the need to compile under language version VHDL-87 is:
"VITALPathDelay DefaultDelay parameter must be locally static"

Purity of NOW In VHDL-93 the function "now" is impure. Consequently, any function that invokes "now" must also be declared to be impure. Such calls to "now" occur in VITAL. A typical error message:
"Cannot call impure function 'now' from inside pure function '<name>'"

Files File syntax and usage changed between VHDL-87 and VHDL-93. In many cases vcom issues a warning and continues:
"Using 1076-1987 syntax for file declaration."

In addition, when files are passed as parameters, the following warning message is produced:
"Subprogram parameter name is declared using VHDL 1987 syntax."

This message often involves calls to endfile(<name>) where <name> is a file parameter. Files and packages Each package header and body should be compiled with the same language version. Common problems in this area involve files as parameters and the size of type CHARACTER. For example, consider a package header and body with a procedure that has a file parameter:
procedure proc1 ( out_file : out std.textio.text) ...

If you compile the package header with VHDL-87 and the body with VHDL-93 or VHDL-2002, you will get an error message such as:
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VHDL Simulation Compiling VHDL Files "** Error: mixed_package_b.vhd(4): Parameter kinds do not conform between declarations in package header and body: 'out_file'."

Direction of concatenation To solve some technical problems, the rules for direction and bounds of concatenation were changed from VHDL-87 to VHDL-93. You won't see any difference in simple variable/signal assignments such as:
v1 := a & b;

But if you (1) have a function that takes an unconstrained array as a parameter, (2) pass a concatenation expression as a formal argument to this parameter, and (3) the body of the function makes assumptions about the direction or bounds of the parameter, then you will get unexpected results. This may be a problem in environments that assume all arrays have "downto" direction. xnor "xnor" is a reserved word in VHDL-93. If you declare an xnor function in VHDL-87 (without quotes) and compile it under VHDL-2002, you will get an error message like the following:
** Error: xnor.vhd(3): near "xnor": expecting: STRING IDENTIFIER

'FOREIGN attribute In VHDL-93 package STANDARD declares an attribute 'FOREIGN. If you declare your own attribute with that name in another package, then ModelSim issues a warning such as the following:
-- Compiling package foopack ** Warning: foreign.vhd(9): (vcom-1140) VHDL-1993 added a definition of the attribute foreign to package std.standard. The attribute is also defined in package 'standard'. Using the definition from package 'standard'.

Size of CHARACTER type In VHDL-87 type CHARACTER has 128 values; in VHDL-93 it has 256 values. Code which depends on this size will behave incorrectly. This situation occurs most commonly in test suites that check VHDL functionality. It's unlikely to occur in practical designs. A typical instance is the replacement of warning message:
"range nul downto del is null"

by
"range nul downto '' is null" -- range is nul downto y(umlaut)

bit string literals In VHDL-87 bit string literals are of type bit_vector. In VHDL-93 they can also be of type STRING or STD_LOGIC_VECTOR. This implies that some expressions that are unambiguous in VHDL-87 now become ambiguous is VHDL-93. A typical error message is:
** Error: bit_string_literal.vhd(5): Subprogram '=' is ambiguous. Suitable definitions exist in packages 'std_logic_1164' and 'standard'.

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Sub-element association In VHDL-87 when using individual sub-element association in an association list, associating individual sub-elements with NULL is discouraged. In VHDL-93 such association is forbidden. A typical message is:
"Formal '<name>' must not be associated with OPEN when subelements are associated individually."

Simulating VHDL Designs

A VHDL design is ready for simulation after it has been compiled with vcom . The simulator may then be invoked with the name of the configuration or entity/architecture pair. Note This section discusses simulation from the UNIX or Windows/DOS command line. You can also use a project to simulate (see Getting Started with Projects) or the Simulate dialog box. This example invokes vsim on the entity my_asic and the architecture structure:
vsim my_asic structure

vsim is capable of annotating a design using VITAL compliant models with timing data from an SDF file. You can specify the min:typ:max delay by invoking vsim with the -sdfmin, -sdftyp, or -sdfmax option. Using the SDF file f1.sdf in the current work directory, the following invocation of vsim annotates maximum timing values for the design unit my_asic:
vsim -sdfmax /my_asic=f1.sdf my_asic

By default, the timing checks within VITAL models are enabled. They can be disabled with the +notimingchecks option. For example:
vsim +notimingchecks topmod

Simulator Resolution Limit (VHDL)

The simulator internally represents time as a 64-bit integer in units equivalent to the smallest unit of simulation time, also known as the simulator resolution limit. The default resolution limit is set to the value specified by the Resolution variable in the modelsim.ini file. You can view the current resolution by invoking the report command with the simulator state option.

Overriding the Resolution

You can override ModelSims default resolution by specifying the -t option on the command line or by selecting a different Simulator Resolution in the Simulate dialog box. Available resolutions are: 1x, 10x, or 100x of fs, ps, ns, us, ms, or sec. For example this command chooses 10 ps resolution:

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VHDL Simulation Simulating VHDL Designs vsim -t 10ps topmod

Clearly you need to be careful when doing this type of operation. If the resolution set by -t is larger than a delay value in your design, the delay values in that design unit are rounded to the closest multiple of the resolution. In the example above, a delay of 4 ps would be rounded to 0 ps.

Choosing the Resolution for VHDL

You should choose the coarsest resolution limit possible that does not result in undesired rounding of your delays. The time precision should not be unnecessarily small because it will limit the maximum simulation time limit, and it will degrade performance in some cases.

Default Binding
By default ModelSim performs default binding when you load the design with vsim. The advantage of performing default binding at load time is that it provides more flexibility for compile order. Namely, entities don't necessarily have to be compiled before other entities/architectures which instantiate them. However, you can force ModelSim to perform default binding at compile time. This may allow you to catch design errors (e.g., entities with incorrect port lists) earlier in the flow. Use one of these two methods to change when default binding occurs: Specify the -bindAtCompile argument to vcom Set the BindAtCompile variable in the modelsim.ini to 1 (true)

Default Binding Rules

When looking for an entity to bind with, ModelSim searches the currently visible libraries for an entity with the same name as the component. ModelSim does this because IEEE 1076-1987 contained a flaw that made it almost impossible for an entity to be directly visible if it had the same name as the component. In short, if a component was declared in an architecture, any likenamed entity above that declaration would be hidden because component/entity names cannot be overloaded. As a result we implemented the following rules for determining default binding: If performing default binding at load time, search the libraries specified with the -Lf argument to vsim. If a directly visible entity has the same name as the component, use it. If an entity would be directly visible in the absence of the component declaration, use it. If the component is declared in a package, search the library that contained the package for an entity with the same name.

If none of these methods is successful, ModelSim will also do the following:

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Search the work library. Search all other libraries that are currently visible by means of the library clause. If performing default binding at load time, search the libraries specified with the -L argument to vsim.

Note that these last three searches are an extension to the 1076 standard.

Disabling Default Binding

If you want default binding to occur only via configurations, you can disable ModelSims normal default binding methods by setting the RequireConfigForAllDefaultBinding variable in the modelsim.ini to 1 (true).

Delta Delays
Event-based simulators such as ModelSim may process many events at a given simulation time. Multiple signals may need updating, statements that are sensitive to these signals must be executed, and any new events that result from these statements must then be queued and executed as well. The steps taken to evaluate the design without advancing simulation time are referred to as "delta times" or just "deltas." The diagram below represents the process for VHDL designs. This process continues until the end of simulation time. Figure 5-1. VHDL Delta Delay Process
Execute concurrent statements at current time Advance delta time

Advance simulation time

No

Any transactions to process? Yes Any events to process? Yes Execute concurrent statements that are sensitive to events No

This mechanism in event-based simulators may cause unexpected results. Consider the following code snippet:
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VHDL Simulation Simulating VHDL Designs clk2 <= clk; process (rst, clk) begin if(rst = '0')then s0 <= '0'; elsif(clk'event and clk='1') then s0 <= inp; end if; end process; process (rst, clk2) begin if(rst = '0')then s1 <= '0'; elsif(clk2'event and clk2='1') then s1 <= s0; end if; end process;

In this example you have two synchronous processes, one triggered with clk and the other with clk2. To your surprise, the signals change in the clk2 process on the same edge as they are set in the clk process. As a result, the value of inp appears at s1 rather than s0. During simulation an event on clk occurs (from the testbench). From this event ModelSim performs the "clk2 <= clk" assignment and the process which is sensitive to clk. Before advancing the simulation time, ModelSim finds that the process sensitive to clk2 can also be run. Since there are no delays present, the effect is that the value of inp appears at s1 in the same simulation cycle. In order to get the expected results, you must do one of the following: Insert a delay at every output Make certain to use the same clock Insert a delta delay

To insert a delta delay, you would modify the code like this:

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VHDL Simulation Using the TextIO Package process (rst, clk) begin if(rst = '0')then s0 <= '0'; elsif(clk'event and clk='1') then s0 <= inp; s0_delayed <= s0; end if; end process; process (rst, clk2) begin if(rst = '0')then s1 <= '0'; elsif(clk2'event and clk2='1') then s1 <= s0_delayed; end if; end process;

The best way to debug delta delay problems is observe your signals in the List window. There you can see how values change at each delta time.

Detecting Infinite Zero-Delay Loops

If a large number of deltas occur without advancing time, it is usually a symptom of an infinite zero-delay loop in the design. In order to detect the presence of these loops, ModelSim defines a limit, the iteration limit", on the number of successive deltas that can occur. When ModelSim reaches the iteration limit, it issues a warning message. The iteration limit default value is 1000. If you receive an iteration limit warning, first increase the iteration limit and try to continue simulation. You can set the iteration limit from the Simulate > Runtime Options menu or by modifying the IterationLimit variable in the modelsim.ini. See Simulator Control Variables for more information on modifying the modelsim.ini file. If the problem persists, look for zero-delay loops. Run the simulation and look at the source code when the error occurs. Use the step button to step through the code and see which signals or variables are continuously oscillating. Two common causes are a loop that has no exit, or a series of gates with zero delay where the outputs are connected back to the inputs.

Using the TextIO Package

To access the routines in TextIO, include the following statement in your VHDL source code:
USE std.textio.all;

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VHDL Simulation Using the TextIO Package

A simple example using the package TextIO is:

USE std.textio.all; ENTITY simple_textio IS END; ARCHITECTURE simple_behavior OF simple_textio IS BEGIN PROCESS VARIABLE i: INTEGER:= 42; VARIABLE LLL: LINE; BEGIN WRITE (LLL, i); WRITELINE (OUTPUT, LLL); WAIT; END PROCESS; END simple_behavior;

Syntax for File Declaration

The VHDL87 syntax for a file declaration is:
file identifier : subtype_indication is [ mode ] file_logical_name ;

where "file_logical_name" must be a string expression. In newer versions of the 1076 spec, syntax for a file declaration is:
file identifier_list : subtype_indication [ file_open_information ] ;

where "file_open_information" is:

[open file_open_kind_expression] is file_logical_name

You can specify a full or relative path as the file_logical_name; for example (VHDL87):
file filename : TEXT is in "usr\rick\myfile";

Normally if a file is declared within an architecture, process, or package, the file is opened when you start the simulator and is closed when you exit from it. If a file is declared in a subprogram, the file is opened when the subprogram is called and closed when execution RETURNs from the subprogram. Alternatively, the opening of files can be delayed until the first read or write by setting the DelayFileOpen variable in the modelsim.ini file. Also, the number of concurrently open files can be controlled by the ConcurrentFileLimit variable. These variables help you manage a large number of files during simulation. See Simulator Variables for more details.

Using STD_INPUT and STD_OUTPUT Within the Tool

The standard VHDL87 TextIO package contains the following file declarations:

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VHDL Simulation TextIO Implementation Issues file input: TEXT is in "STD_INPUT"; file output: TEXT is out "STD_OUTPUT";

Updated versions of the TextIO package contain these file declarations:

file input: TEXT open read_mode is "STD_INPUT"; file output: TEXT open write_mode is "STD_OUTPUT";

STD_INPUT is a file_logical_name that refers to characters that are entered interactively from the keyboard, and STD_OUTPUT refers to text that is displayed on the screen. In ModelSim, reading from the STD_INPUT file allows you to enter text into the current buffer from a prompt in the Transcript pane. The lines written to the STD_OUTPUT file appear in the Transcript.

TextIO Implementation Issues

Writing Strings and Aggregates
A common error in VHDL source code occurs when a call to a WRITE procedure does not specify whether the argument is of type STRING or BIT_VECTOR. For example, the VHDL procedure:
WRITE (L, "hello");

will cause the following error:

ERROR: Subprogram "WRITE" is ambiguous.

In the TextIO package, the WRITE procedure is overloaded for the types STRING and BIT_VECTOR. These lines are reproduced here:
procedure WRITE(L: inout LINE; VALUE: in BIT_VECTOR; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0); procedure WRITE(L: inout LINE; VALUE: in STRING; JUSTIFIED: in SIDE:= RIGHT; FIELD: in WIDTH := 0);

The error occurs because the argument "hello" could be interpreted as a string or a bit vector, but the compiler is not allowed to determine the argument type until it knows which function is being called. The following procedure call also generates an error:
WRITE (L, "010101");

This call is even more ambiguous, because the compiler could not determine, even if allowed to, whether the argument "010101" should be interpreted as a string or a bit vector.

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VHDL Simulation TextIO Implementation Issues

There are two possible solutions to this problem: Use a qualified expression to specify the type, as in:

WRITE (L, string("hello"));

Call a procedure that is not overloaded, as in:

WRITE_STRING (L, "hello");

The WRITE_STRING procedure simply defines the value to be a STRING and calls the WRITE procedure, but it serves as a shell around the WRITE procedure that solves the overloading problem. For further details, refer to the WRITE_STRING procedure in the io_utils package, which is located in the file <install_dir>/modeltech/examples/misc/io_utils.vhd.

Reading and Writing Hexadecimal Numbers

The reading and writing of hexadecimal numbers is not specified in standard VHDL. The Issues Screening and Analysis Committee of the VHDL Analysis and Standardization Group (ISACVASG) has specified that the TextIO package reads and writes only decimal numbers. To expand this functionality, ModelSim supplies hexadecimal routines in the package io_utils, which is located in the file <install_dir>/modeltech/examples/misc/io_utils.vhd. To use these routines, compile the io_utils package and then include the following use clauses in your VHDL source code:
use std.textio.all; use work.io_utils.all;

Dangling Pointers
Dangling pointers are easily created when using the TextIO package, because WRITELINE deallocates the access type (pointer) that is passed to it. Following are examples of good and bad VHDL coding styles: Bad VHDL (because L1 and L2 both point to the same buffer):
READLINE (infile, L1); L2 := L1; WRITELINE (outfile, L1); -- Read and allocate buffer -- Copy pointers -- Deallocate buffer

Good VHDL (because L1 and L2 point to different buffers):

READLINE (infile, L1); L2 := new string(L1.all); WRITELINE (outfile, L1); -- Read and allocate buffer -- Copy contents -- Deallocate buffer

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The ENDLINE Function

The ENDLINE function described in the IEEE Standard VHDL Language Reference Manual, IEEE Std 1076-1987 contains invalid VHDL syntax and cannot be implemented in VHDL. This is because access values must be passed as variables, but functions do not allow variable parameters. Based on an ISAC-VASG recommendation the ENDLINE function has been removed from the TextIO package. The following test may be substituted for this function:
(L = NULL) OR (LLENGTH = 0)

The ENDFILE Function

In the VHDL Language Reference Manuals, the ENDFILE function is listed as:
-- function ENDFILE (L: in TEXT) return BOOLEAN;

As you can see, this function is commented out of the standard TextIO package. This is because the ENDFILE function is implicitly declared, so it can be used with files of any type, not just files of type TEXT.

Using Alternative Input/Output Files

You can use the TextIO package to read and write to your own files. To do this, just declare an input or output file of type TEXT. For example, for an input file: The VHDL87 declaration is:
file myinput : TEXT is in "pathname.dat";

The VHDL93 declaration is:

file myinput : TEXT open read_mode is "pathname.dat";

Then include the identifier for this file ("myinput" in this example) in the READLINE or WRITELINE procedure call.

Flushing the TEXTIO Buffer

Flushing of the TEXTIO buffer is controlled by the UnbufferedOutput variable in the modelsim.ini file.

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VHDL Simulation VITAL Specification and Source Code

Providing Stimulus
You can stimulate and test a design by reading vectors from a file, using them to drive values onto signals, and testing the results. A VHDL test bench has been included with the ModelSim install files as an example. Check for this file:
<install_dir>/modeltech/examples/misc/stimulus.vhd

VITAL Specification and Source Code

VITAL ASIC Modeling Specification The IEEE 1076.4 VITAL ASIC Modeling Specification is available from the Institute of Electrical and Electronics Engineers, Inc.: IEEE Customer Service 445 Hoes Lane Piscataway, NJ 08854-1331 Tel: (732) 981-0060 Fax: (732) 981-1721 home page: http://www.ieee.org VITAL source code The source code for VITAL packages is provided in the directories:
/<install_dir>/vhdl_src/vital22b /vital95 /vital2000

VITAL Packages
VITAL 1995 accelerated packages are pre-compiled into the ieee library in the installation directory. VITAL 2000 accelerated packages are pre-compiled into the vital2000 library. If you need to use the newer library, you either need to change the ieee library mapping or add a use clause to your VHDL code to access the VITAL 2000 packages. To change the ieee library mapping, issue the following command:
vmap ieee <modeltech>/vital2000

Or, alternatively, add use clauses to your code:

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VHDL Simulation VITAL Compliance LIBRARY vital2000; USE vital2000.vital_primitives.all; USE vital2000.vital_timing.all; USE vital2000.vital_memory.all;

Note that if your design uses two libraries -one that depends on vital95 and one that depends on vital2000 - then you will have to change the references in the source code to vital2000. Changing the library mapping will not work.

VITAL Compliance
A simulator is VITAL compliant if it implements the SDF mapping and if it correctly simulates designs using the VITAL packages, as outlined in the VITAL Model Development Specification. ModelSim is compliant with the IEEE 1076.4 VITAL ASIC Modeling Specification. In addition, ModelSim accelerates the VITAL_Timing, VITAL_Primitives, and VITAL_memory packages. The optimized procedures are functionally equivalent to the IEEE 1076.4 VITAL ASIC Modeling Specification (VITAL 1995 and 2000).

VITAL Compliance Checking

If you are using VITAL 2.2b, you must turn off the compliance checking either by not setting the attributes, or by invoking vcom with the option -novitalcheck.

Compiling and Simulating with Accelerated VITAL Packages

vcom automatically recognizes that a VITAL function is being referenced from the ieee library and generates code to call the optimized built-in routines. Invoke with the -novital option if you do not want to use the built-in VITAL routines (when debugging for instance). To exclude all VITAL functions, use -novital all:
vcom -novital all design.vhd

To exclude selected VITAL functions, use one or more -novital <fname> options:
vcom -novital VitalTimingCheck -novital VitalAND design.vhd

The -novital switch only affects calls to VITAL functions from the design units currently being compiled. Pre-compiled design units referenced from the current design units will still call the built-in functions unless they too are compiled with the -novital option. ModelSim VITAL built-ins will be updated in step with new releases of the VITAL packages.

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VHDL Simulation Util Package

Util Package
The util package serves as a container for various VHDL utilities. The package is part of the modelsim_lib library which is located in the modeltech tree and is mapped in the default modelsim.ini file. To access the utilities in the package, you would add lines like the following to your VHDL code:
library modelsim_lib; use modelsim_lib.util.all;

get_resolution
get_resolution returns the current simulator resolution as a real number. For example, 1 femtosecond corresponds to 1e-15. Syntax
resval := get_resolution;

Returns Name resval Arguments None Related functions to_real() to_time() Type real Description The simulator resolution represented as a real

Example If the simulator resolution is set to 10ps, and you invoke the command:
resval := get_resolution;

the value returned to resval would be 1e-11.

init_signal_driver()
The init_signal_driver() procedure drives the value of a VHDL signal or Verilog net onto an existing VHDL signal or Verilog net. This allows you to drive signals or nets at any level of the design hierarchy from within a VHDL architecture (e.g., a testbench).

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VHDL Simulation Util Package

See init_signal_driver for complete details.

init_signal_spy()
The init_signal_spy() utility mirrors the value of a VHDL signal or Verilog register/net onto an existing VHDL signal or Verilog register. This allows you to reference signals, registers, or nets at any level of hierarchy from within a VHDL architecture (e.g., a testbench). See init_signal_spy for complete details.

signal_force()
The signal_force() procedure forces the value specified onto an existing VHDL signal or Verilog register or net. This allows you to force signals, registers, or nets at any level of the design hierarchy from within a VHDL architecture (e.g., a testbench). A signal_force works the same as the force command with the exception that you cannot issue a repeating force. See signal_force for complete details.

signal_release()
The signal_release() procedure releases any force that was applied to an existing VHDL signal or Verilog register or net. This allows you to release signals, registers, or nets at any level of the design hierarchy from within a VHDL architecture (e.g., a testbench). A signal_release works the same as the noforce command. See signal_release for complete details.

to_real()
to_real() converts the physical type time value into a real value with respect to the current simulator resolution. The precision of the converted value is determined by the simulator resolution. For example, if you were converting 1900 fs to a real and the simulator resolution was ps, then the real value would be 2.0 (i.e., 2 ps). Syntax
realval := to_real(timeval);

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Returns Name realval Arguments Name timeval Related functions get_resolution to_time() Type time Description The value of the physical type time Type real Description The time value represented as a real with respect to the simulator resolution

Example If the simulator resolution is set to ps, and you enter the following function:
realval := to_real(12.99 ns);

then the value returned to realval would be 12990.0. If you wanted the returned value to be in units of nanoseconds (ns) instead, you would use the get_resolution function to recalculate the value:
realval := 1e+9 * (to_real(12.99 ns)) * get_resolution();

If you wanted the returned value to be in units of femtoseconds (fs), you would enter the function this way:
realval := 1e+15 * (to_real(12.99 ns)) * get_resolution();

to_time()
to_time() converts a real value into a time value with respect to the current simulator resolution. The precision of the converted value is determined by the simulator resolution. For example, if you were converting 5.9 to a time and the simulator resolution was ps, then the time value would be 6 ps. Syntax
timeval := to_time(realval);

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Returns Name timeval Type time Description The real value represented as a physical type time with respect to the simulator resolution

Arguments Name realval Related functions get_resolution to_real() Type real Description The value of the type real

Example If the simulator resolution is set to ps, and you enter the following function:
timeval := to_time(72.49);

then the value returned to timeval would be 72 ps.

Modeling Memory
As a VHDL user, you might be tempted to model a memory using signals. Two common simulator problems are the likely result: You may get a "memory allocation error" message, which typically means the simulator ran out of memory and failed to allocate enough storage. Or, you may get very long load, elaboration, or run times.

These problems are usually explained by the fact that signals consume a substantial amount of memory (many dozens of bytes per bit), all of which needs to be loaded or initialized before your simulation starts. Modeling memory with variables or protected types instead provides some excellent performance benefits: storage required to model the memory can be reduced by 1-2 orders of magnitude startup and run times are reduced associated memory allocation errors are eliminated

In the VHDL example below, we illustrate three alternative architectures for entity memory:

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Architecture bad_style_87 uses a vhdl signal to store the ram data. Architecture style_87 uses variables in the memory process Architecture style_93 uses variables in the architecture.

For large memories, architecture bad_style_87 runs many times longer than the other two, and uses much more memory. This style should be avoided. Architectures style_87 and style_93 work with equal efficiently. However, VHDL 1993 offers additional flexibility because the ram storage can be shared between multiple processes. For example, a second process is shown that initializes the memory; you could add other processes to create a multi-ported memory. To implement this model, you will need functions that convert vectors to integers. To use it you will probably need to convert integers to vectors. Example functions are provided below in package "conversions". For completeness sake we also show an example using VHDL 2002 protected types, though in this example, protected types offer no advantage over shared variables.

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VHDL87 and VHDL93 Example

library ieee; use ieee.std_logic_1164.all; use work.conversions.all; entity memory is generic(add_bits : integer := 12; data_bits : integer := 32); port(add_in : in std_ulogic_vector(add_bits-1 downto 0); data_in : in std_ulogic_vector(data_bits-1 downto 0); data_out : out std_ulogic_vector(data_bits-1 downto 0); cs, mwrite : in std_ulogic; do_init : in std_ulogic); subtype word is std_ulogic_vector(data_bits-1 downto 0); constant nwords : integer := 2 ** add_bits; type ram_type is array(0 to nwords-1) of word; end; architecture style_93 of memory is -----------------------------shared variable ram : ram_type; -----------------------------begin memory: process (cs) variable address : natural; begin if rising_edge(cs) then address := sulv_to_natural(add_in); if (mwrite = '1') then ram(address) := data_in; end if; data_out <= ram(address); end if; end process memory; -- illustrates a second process using the shared variable initialize: process (do_init) variable address : natural; begin if rising_edge(do_init) then for address in 0 to nwords-1 loop ram(address) := data_in; end loop; end if; end process initialize; end architecture style_93; architecture style_87 of memory is begin memory: process (cs) ----------------------variable ram : ram_type; ----------------------variable address : natural;

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VHDL Simulation Modeling Memory begin if rising_edge(cs) then address := sulv_to_natural(add_in); if (mwrite = '1') then ram(address) := data_in; end if; data_out <= ram(address); end if; end process; end style_87; architecture bad_style_87 of memory is ---------------------signal ram : ram_type; ---------------------begin memory: process (cs) variable address : natural := 0; begin if rising_edge(cs) then address := sulv_to_natural(add_in); if (mwrite = '1') then ram(address) <= data_in; data_out <= data_in; else data_out <= ram(address); end if; end if; end process; end bad_style_87; ----------------------------------------------------------------------------------------------------------------------library ieee; use ieee.std_logic_1164.all; package conversions is function sulv_to_natural(x : std_ulogic_vector) return natural; function natural_to_sulv(n, bits : natural) return std_ulogic_vector; end conversions; package body conversions is function sulv_to_natural(x : std_ulogic_vector) return natural is variable n : natural := 0; variable failure : boolean := false; begin assert (x'high - x'low + 1) <= 31 report "Range of sulv_to_natural argument exceeds natural range" severity error; for i in x'range loop n := n * 2; case x(i) is

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VHDL Simulation Modeling Memory when '1' | 'H' => n := n + 1; when '0' | 'L' => null; when others => failure := true; end case; end loop; assert not failure report "sulv_to_natural cannot convert indefinite std_ulogic_vector" severity error; if failure then return 0; else return n; end if; end sulv_to_natural; function natural_to_sulv(n, bits : natural) return std_ulogic_vector is variable x : std_ulogic_vector(bits-1 downto 0) := (others => '0'); variable tempn : natural := n; begin for i in x'reverse_range loop if (tempn mod 2) = 1 then x(i) := '1'; end if; tempn := tempn / 2; end loop; return x; end natural_to_sulv; end conversions;

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VHDL Simulation Modeling Memory

VHDL02 example
-------------------------------------------------------------------------- Source: sp_syn_ram_protected.vhd -- Component: VHDL synchronous, single-port RAM -- Remarks: Various VHDL examples: random access memory (RAM) ------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY sp_syn_ram_protected IS GENERIC ( data_width : positive := 8; addr_width : positive := 3 ); PORT ( inclk : IN std_logic; outclk : IN std_logic; we : IN std_logic; addr : IN unsigned(addr_width-1 DOWNTO 0); data_in : IN std_logic_vector(data_width-1 DOWNTO 0); data_out : OUT std_logic_vector(data_width-1 DOWNTO 0) ); END sp_syn_ram_protected;

ARCHITECTURE intarch OF sp_syn_ram_protected IS TYPE mem_type IS PROTECTED PROCEDURE write ( data : IN std_logic_vector(data_width-1 downto 0); addr : IN unsigned(addr_width-1 DOWNTO 0)); IMPURE FUNCTION read ( addr : IN unsigned(addr_width-1 DOWNTO 0)) RETURN std_logic_vector; END PROTECTED mem_type; TYPE mem_type IS PROTECTED BODY TYPE mem_array IS ARRAY (0 TO 2**addr_width-1) OF std_logic_vector(data_width-1 DOWNTO 0); VARIABLE mem : mem_array; PROCEDURE write ( data : IN std_logic_vector(data_width-1 downto 0); addr : IN unsigned(addr_width-1 DOWNTO 0)) IS BEGIN mem(to_integer(addr)) := data; END; IMPURE FUNCTION read ( addr : IN unsigned(addr_width-1 DOWNTO 0)) RETURN std_logic_vector IS BEGIN return mem(to_integer(addr)); END; END PROTECTED BODY mem_type;

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SHARED VARIABLE memory : mem_type; BEGIN ASSERT data_width <= 32 REPORT "### Illegal data width detected" SEVERITY failure; control_proc : PROCESS (inclk, outclk) BEGIN IF (inclk'event AND inclk = '1') THEN IF (we = '1') THEN memory.write(data_in, addr); END IF; END IF; IF (outclk'event AND outclk = '1') THEN data_out <= memory.read(addr); END IF; END PROCESS; END intarch; -------------------------------------------------------------------------- Source: ram_tb.vhd -- Component: VHDL testbench for RAM memory example -- Remarks: Simple VHDL example: random access memory (RAM) ------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY ram_tb IS END ram_tb; ARCHITECTURE testbench OF ram_tb IS -------------------------------------------- Component declaration single-port RAM ------------------------------------------COMPONENT sp_syn_ram_protected GENERIC ( data_width : positive := 8; addr_width : positive := 3 ); PORT ( inclk : IN std_logic; outclk : IN std_logic; we : IN std_logic; addr : IN unsigned(addr_width-1 DOWNTO 0); data_in : IN std_logic_vector(data_width-1 DOWNTO 0); data_out : OUT std_logic_vector(data_width-1 DOWNTO 0) ); END COMPONENT; -------------------------------------------

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VHDL Simulation Modeling Memory -- Intermediate signals and constants ------------------------------------------SIGNAL addr : unsigned(19 DOWNTO 0); SIGNAL inaddr : unsigned(3 DOWNTO 0); SIGNAL outaddr : unsigned(3 DOWNTO 0); SIGNAL data_in : unsigned(31 DOWNTO 0); SIGNAL data_in1 : std_logic_vector(7 DOWNTO 0); SIGNAL data_sp1 : std_logic_vector(7 DOWNTO 0); SIGNAL we : std_logic; SIGNAL clk : std_logic; CONSTANT clk_pd : time := 100 ns;

BEGIN ---------------------------------------------------- instantiations of single-port RAM architectures. -- All architectures behave equivalently, but they -- have different implementations. The signal-based -- architecture (rtl) is not a recommended style. --------------------------------------------------spram1 : entity work.sp_syn_ram_protected GENERIC MAP ( data_width => 8, addr_width => 12) PORT MAP ( inclk => clk, outclk => clk, we => we, addr => addr(11 downto 0), data_in => data_in1, data_out => data_sp1); -------------------------------------------- clock generator ------------------------------------------clock_driver : PROCESS BEGIN clk <= '0'; WAIT FOR clk_pd / 2; LOOP clk <= '1', '0' AFTER clk_pd / 2; WAIT FOR clk_pd; END LOOP; END PROCESS; -------------------------------------------- data-in process ------------------------------------------datain_drivers : PROCESS(data_in) BEGIN data_in1 <= std_logic_vector(data_in(7 downto 0)); END PROCESS; -------------------------------------------- simulation control process ------------------------------------------ctrl_sim : PROCESS

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VHDL Simulation Modeling Memory BEGIN FOR i IN 0 TO 1023 LOOP we <= '1'; data_in <= to_unsigned(9000 + i, data_in'length); addr <= to_unsigned(i, addr'length); inaddr <= to_unsigned(i, inaddr'length); outaddr <= to_unsigned(i, outaddr'length); WAIT UNTIL clk'EVENT AND clk = '0'; WAIT UNTIL clk'EVENT AND clk = '0'; data_in <= to_unsigned(7 + i, addr <= to_unsigned(1 + i, inaddr <= to_unsigned(1 + i, WAIT UNTIL clk'EVENT AND clk = WAIT UNTIL clk'EVENT AND clk = data_in'length); addr'length); inaddr'length); '0'; '0';

data_in <= to_unsigned(3, data_in'length); addr <= to_unsigned(2 + i, addr'length); inaddr <= to_unsigned(2 + i, inaddr'length); WAIT UNTIL clk'EVENT AND clk = '0'; WAIT UNTIL clk'EVENT AND clk = '0'; data_in <= to_unsigned(30330, addr <= to_unsigned(3 + i, inaddr <= to_unsigned(3 + i, WAIT UNTIL clk'EVENT AND clk = WAIT UNTIL clk'EVENT AND clk = data_in'length); addr'length); inaddr'length); '0'; '0';

we <= '0'; addr <= to_unsigned(i, addr'length); outaddr <= to_unsigned(i, outaddr'length); WAIT UNTIL clk'EVENT AND clk = '0'; WAIT UNTIL clk'EVENT AND clk = '0'; addr <= to_unsigned(1 + i, outaddr <= to_unsigned(1 + i, WAIT UNTIL clk'EVENT AND clk = WAIT UNTIL clk'EVENT AND clk = addr <= to_unsigned(2 + i, outaddr <= to_unsigned(2 + i, WAIT UNTIL clk'EVENT AND clk = WAIT UNTIL clk'EVENT AND clk = addr <= to_unsigned(3 + i, outaddr <= to_unsigned(3 + i, WAIT UNTIL clk'EVENT AND clk = WAIT UNTIL clk'EVENT AND clk = END LOOP; ASSERT false REPORT "### End of Simulation!" SEVERITY failure; END PROCESS; END testbench; addr'length); outaddr'length); '0'; '0'; addr'length); outaddr'length); '0'; '0'; addr'length); outaddr'length); '0'; '0';

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VHDL Simulation Affecting Performance by Cancelling Scheduled Events

Affecting Performance by Cancelling Scheduled Events

Performance will suffer if events are scheduled far into the future but then cancelled before they take effect. This situation will act like a memory leak and slow down simulation. In VHDL this situation can occur several ways. The most common are waits with time-out clauses and projected waveforms in signal assignments. The following code shows a wait with a time-out:
signals synch : bit := '0'; ... p: process begin wait for 10 ms until synch = 1; end process; synch <= not synch after 10 ns;

At time 0, process p makes an event for time 10ms. When synch goes to 1 at 10 ns, the event at 10 ms is marked as cancelled but not deleted, and a new event is scheduled at 10ms + 10ns. The cancelled events are not reclaimed until time 10ms is reached and the cancelled event is processed. As a result there will be 500000 (10ms/20ns) cancelled but un-deleted events. Once 10ms is reached, memory will no longer increase because the simulator will be reclaiming events as fast as they are added. For projected waveforms the following would behave the same way:
signals synch : bit := '0'; ... p: process(synch) begin output <= '0', '1' after 10ms; end process; synch <= not synch after 10 ns;

Converting an Integer Into a bit_vector

The following code demonstrates how to convert an integer into a bit_vector.

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VHDL Simulation Converting an Integer Into a bit_vector library ieee; use ieee.numeric_bit.ALL; entity test is end test; architecture only of test is signal s1 : bit_vector(7 downto 0); signal int : integer := 45; begin p:process begin wait for 10 ns; s1 <= bit_vector(to_signed(int,8)); end process p; end only;

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Chapter 6 Verilog and SystemVerilog Simulation

This chapter describes how to compile and simulate Verilog and SystemVerilog designs with ModelSim. ModelSim implements the Verilog language as defined by the IEEE Standards 1364-1995 and 1364-2005. We recommend that you obtain these specifications for reference. The following functionality is partially implemented in ModelSim: Verilog Procedural Interface (VPI) (see /<install_dir>/modeltech/docs/technotes/Verilog_VPI.note for details) IEEE Std P1800-2005 SystemVerilog (see /<install_dir>/modeltech/docs/technotes/sysvlog.note for implementation details)

Terminology
This chapter uses the term Verilog to represent both Verilog and SystemVerilog, unless otherwise noted.

Basic Verilog Flow

Simulating Verilog designs with ModelSim includes four general steps: 1. Compile your Verilog code into one or more libraries using the vlog command. See Compiling Verilog Files for details. 2. Load your design with the vsim command. See Simulating Verilog Designs for details. 3. Run and debug your design.

Compiling Verilog Files

The first time you compile a design there is a two-step process: 1. Create a working library with vlib or select File > New > Library. 2. Compile the design using vlog or select Compile > Compile.

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Creating a Working Library

Before you can compile your design, you must create a library in which to store the compilation results. Use the vlib command or select File > New > Library to create a new library. For example:
vlib work

This creates a library named work. By default compilation results are stored in the work library. The work library is actually a subdirectory named work. This subdirectory contains a special file named _info. Do not create libraries using UNIX commands always use the vlib. See Design Libraries for additional information on working with libraries.

Invoking the Verilog Compiler

The Verilog compiler, vlog, compiles Verilog source code into retargetable, executable code. The library format is compatible across all supported platforms, and you can simulate your design on any platform without having to recompile your design. As the design compiles, the resulting object code for modules and UDPs is generated into a library. As noted above, the compiler places results into the work library by default. You can specify an alternate library with the -work argument. Example 6-1. Invocation of the Verilog Compiler Here is a sample invocation of vlog:
vlog top.v +libext+.v+.u -y vlog_lib

After compiling top.v, vlog will scan the vlog_lib library for files with modules with the same name as primitives referenced, but undefined in top.v. The use of +libext+.v+.u implies filenames with a .v or .u suffix (any combination of suffixes may be used). Only referenced definitions will be compiled.

Parsing SystemVerilog Keywords

With standard Verilog files (<filename>.v), vlog will not automatically parse SystemVerilog keywords. SystemVerilog keywords are parsed when any of the following situations exists: any file within the design contains the .sv file extension, the -sv argument is used with the vlog command,

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the Use System Verilog option is selected in the Verilog tab of the Compiler Options dialog. Access this dialog by selecting Compile > Compile Options from the Main window menu bar. Figure 6-1. Selecting Use System Verilog Compile Option

Here are two examples of the vlog command that will enable SystemVerilog features and keywords in ModelSim:
vlog testbench.sv top.v memory.v cache.v vlog -sv testbench.v proc.v

In the first example, the .sv extension for testbench automatically instructs ModelSim to parse SystemVerilog keywords. The -sv option used in the second example enables SystemVerilog features and keywords. Though a primary goal of the SystemVerilog standardization efforts has been to ensure full backward compatibility with the Verilog standard, there is an issue with keywords. SystemVerilog adds several new keywords to the Verilog language (see Table B-1 in Appendix B of the P1800 SystemVerilog standard). If your design uses one of these keywords as a regular identifier for a variable, module, task, function, etc., your design will not compile in ModelSim.

Incremental Compilation
ModelSim Verilog supports incremental compilation of designs. Unlike other Verilog simulators, there is no requirement that you compile the entire design in one invocation of the compiler. You are not required to compile your design in any particular order (unless you are using SystemVerilog packages; see note below) because all module and UDP instantiations and external hierarchical references are resolved when the design is loaded by the simulator.

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Note Compilation order may matter when using SystemVerilog packages. As stated in the IEEE std p1800-2005 LRM, section entitled Referencing data in packages, which states: "Packages must exist in order for the items they define to be recognized by the scopes in which they are imported. Incremental compilation is made possible by deferring these bindings, and as a result some errors cannot be detected during compilation. Commonly, these errors include: modules that were referenced but not compiled, incorrect port connections, and incorrect hierarchical references. Example 6-2. Incremental Compilation Example Contents of testbench.sv
module testbench; timeunit 1ns; timeprecision 10ps; bit d=1, clk = 0; wire q; initial for (int cycles=0; cycles < 100; cycles++) #100 clk = !clk; design dut(q, d, clk); endmodule

Contents of design.v:
module design(output bit q, input bit d, clk); timeunit 1ns; timeprecision 10ps; always @(posedge clk) q = d; endmodule

Compile the design incrementally as follows:

ModelSim> vlog testbench.sv . # Top level modules: # testbench ModelSim> vlog -sv test1.v . # Top level modules: # dut

Note that the compiler lists each module as a top-level module, although, ultimately, only testbench is a top-level module. If a module is not referenced by another module compiled in the same invocation of the compiler, then it is listed as a top-level module. This is just an informative message and can be ignored during incremental compilation.

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The message is more useful when you compile an entire design in one invocation of the compiler and need to know the top-level module names for the simulator. For example,
% vlog top.v and2.v -- Compiling module -- Compiling module -- Compiling module Top level modules: top or2.v top and2 or2

Automatic Incremental Compilation with -incr

The most efficient method of incremental compilation is to manually compile only the modules that have changed. However, this is not always convenient, especially if your source files have compiler directive interdependencies (such as macros). In this case, you may prefer to compile your entire design along with the -incr argument. This causes the compiler to automatically determine which modules have changed and generate code only for those modules. The following is an example of how to compile a design with automatic incremental compilation:
% vlog -incr top.v and2.v or2.v -- Compiling module top -- Compiling module and2 -- Compiling module or2 Top level modules: top

Now, suppose that you modify the functionality of the or2 module:
% vlog -incr top.v and2.v or2.v -- Skipping module top -- Skipping module and2 -- Compiling module or2 Top level modules: top

The compiler informs you that it skipped the modules top and and2, and compiled or2. Automatic incremental compilation is intelligent about when to compile a module. For example, changing a comment in your source code does not result in a recompile; however, changing the compiler command line arguments results in a recompile of all modules. Note Changes to your source code that do not change functionality but that do affect source code line numbers (such as adding a comment line) will cause all affected modules to be recompiled. This happens because debug information must be kept current so that ModelSim can trace back to the correct areas of the source code.

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Library Usage
All modules and UDPs in a Verilog design must be compiled into one or more libraries. One library is usually sufficient for a simple design, but you may want to organize your modules into various libraries for a complex design. If your design uses different modules having the same name, then you are required to put those modules in different libraries because design unit names must be unique within a library. The following is an example of how you may organize your ASIC cells into one library and the rest of your design into another:
% vlib work % vlib asiclib % vlog -work asiclib and2.v or2.v -- Compiling module and2 -- Compiling module or2 Top level modules: and2 or2 % vlog top.v -- Compiling module top Top level modules: top

Note that the first compilation uses the -work asiclib argument to instruct the compiler to place the results in the asiclib library rather than the default work library.

Library Search Rules for vlog

Since instantiation bindings are not determined at compile time, you must instruct the simulator to search your libraries when loading the design. The top-level modules are loaded from the library named work unless you prefix the modules with the <library>. option. All other Verilog instantiations are resolved in the following order: Search libraries specified with -Lf arguments in the order they appear on the command line. Search the library specified in the Verilog-XL uselib Compiler Directive section. Search libraries specified with -L arguments in the order they appear on the command line. Search the work library. Search the library explicitly named in the special escaped identifier instance name.

Handling Sub-Modules with Common Names

Sometimes in one design you need to reference two different modules that have the same name. This situation can occur if you have hierarchical modules organized into separate libraries, and
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you have commonly-named sub-modules in the libraries that have different definitions. This may happen if you are using vendor-supplied libraries. For example, say you have the following design configuration: Example 6-3. Sub-Modules with Common Names
top modA modB

lib1: modA cellX

lib2: modB cellX

The normal library search rules will fail in this situation. For example, if you load the design as follows:
vsim -L lib1 -L lib2 top

both instantiations of cellX resolve to the lib1 version of cellX. On the other hand, if you specify -L lib2 -L lib1, both instantiations of cellX resolve to the lib2 version of cellX. To handle this situation, ModelSim implements a special interpretation of the expression -L work. When you specify -L work first in the search library arguments you are directing vsim to search for the instantiated module or UDP in the library that contains the module that does the instantiation. In the example above you would invoke vsim as follows:
vsim -L work -L lib1 -L lib2 top

SystemVerilog Multi-File Compilation Issues

Declarations in Compilation Unit Scope
SystemVerilog allows the declaration of types, variables, functions, tasks, and other constructs in compilation unit scope ($unit). The visibility of declarations in $unit scope does not extend outside the current compilation unit. Thus, it is important to understand how compilation units are defined by the tool during compilation. By default, vlog operates in Single File Compilation Unit mode (SFCU). This means the visibility of declarations in $unit scope terminates at the end of each source file. Visibility does not carry forward from one file to another, except when a module, interface, or package

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declaration begins in one file and ends in another file. In that case, the compilation unit spans from the file containing the beginning of the declaration to the file containing the end of the declaration. vlog also supports a non-default behavior called Multi File Compilation Unit mode (MFCU). In MFCU mode, vlog compiles all files given on the command line into one compilation unit. You can invoke vlog in MFCU mode as follows: For a specific compilation -- with the -mfcu argument to vlog. For all compilations -- by setting the variable MultiFileCompilationUnit = 1 in the modelsim.ini file.

By using either of these methods, you allow declarations in $unit scope to remain in effect throughout the compilation of all files. In case you have made MFCU the default behavior by setting MultiFileCompilationUnit = 1 in your modelsim.ini file, it is possible to override the default behavior on specific compilations by using the -sfcu argument to vlog.

Macro Definitions and Compiler Directives in Compilation Unit Scope

According to the SystemVerilog IEEE Std p1800-2005 LRM, the visibility of macro definitions and compiler directives span the lifetime of a single compilation unit. By default, this means the definitions of macros and settings of compiler directives terminate at the end of each source file. They do not carry forward from one file to another, except when a module, interface, or package declaration begins in one file and ends in another file. In that case, the compilation unit spans from the file containing the beginning of the definition to the file containing the end of the definition. See Declarations in Compilation Unit Scope for instructions on how to control vlog's handling of compilation units. Note Compiler directives revert to their default values at the end of a compilation unit.

If a compiler directive is specified as an option to the compiler, this setting is used for all compilation units present in the current compilation.

Verilog-XL Compatible Compiler Arguments

The compiler arguments listed below are equivalent to Verilog-XL arguments and may ease the porting of a design to ModelSim. See the vlog command for a description of each argument.

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Verilog and SystemVerilog Simulation Compiling Verilog Files +define+<macro_name>[=<macro_text>] +delay_mode_distributed +delay_mode_path +delay_mode_unit +delay_mode_zero -f <filename> +incdir+<directory> +mindelays +maxdelays +nowarn<mnemonic> +typdelays -u

Arguments Supporting Source Libraries

The compiler arguments listed below support source libraries in the same manner as VerilogXL. See the vlog command for a description of each argument. Note that these source libraries are very different from the libraries that the ModelSim compiler uses to store compilation results. You may find it convenient to use these arguments if you are porting a design to ModelSim or if you are familiar with these arguments and prefer to use them. Source libraries are searched after the source files on the command line are compiled. If there are any unresolved references to modules or UDPs, then the compiler searches the source libraries to satisfy them. The modules compiled from source libraries may in turn have additional unresolved references that cause the source libraries to be searched again. This process is repeated until all references are resolved or until no new unresolved references are found. Source libraries are searched in the order they appear on the command line.
-v <filename> -y <directory> +libext+<suffix> +librescan +nolibcell -R [<simargs>]

Verilog-XL uselib Compiler Directive

The `uselib compiler directive is an alternative source library management scheme to the -v, -y, and +libext compiler arguments. It has the advantage that a design may reference different modules having the same name. You compile designs that contain `uselib directive statements using the -compile_uselibs argument (described below) to vlog. The syntax for the `uselib directive is:
`uselib <library_reference>...

where <library_reference> can be one or more of the following:

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dir=<library_directory>, which is equivalent to the command line argument:

-y <library_directory>

file=<library_file>, which is equivalent to the command line argument:

-v <library_file>

libext=<file_extension>, which is equivalent to the command line argument:

+libext+<file_extension>

lib=<library_name>, which references a library for instantiated objects. This behaves similarly to a LIBRARY/USE clause in VHDL. You must ensure the correct mappings are set up if the library does not exist in the current working directory. The -compile_uselibs argument does not affect this usage of `uselib.

For example, the following directive

`uselib dir=/h/vendorA libext=.v

is equivalent to the following command line arguments:

-y /h/vendorA +libext+.v

Since the `uselib directives are embedded in the Verilog source code, there is more flexibility in defining the source libraries for the instantiations in the design. The appearance of a `uselib directive in the source code explicitly defines how instantiations that follow it are resolved, completely overriding any previous `uselib directives.

-compile_uselibs Argument
Use the -compile_uselibs argument to vlog to reference `uselib directives. The argument finds the source files referenced in the directive, compiles them into automatically created object libraries, and updates the modelsim.ini file with the logical mappings to the libraries. When using -compile_uselibs, ModelSim determines into which directory to compile the object libraries by choosing, in order, from the following three values: The directory name specified by the -compile_uselibs argument. For example,
-compile_uselibs=./mydir

The directory specified by the MTI_USELIB_DIR environment variable (see Environment Variables) A directory named mti_uselibs that is created in the current working directory

The following code fragment and compiler invocation show how two different modules that have the same name can be instantiated within the same design:

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Verilog and SystemVerilog Simulation Compiling Verilog Files module top; `uselib dir=/h/vendorA libext=.v NAND2 u1(n1, n2, n3); `uselib dir=/h/vendorB libext=.v NAND2 u2(n4, n5, n6); endmodule vlog -compile_uselibs top

This allows the NAND2 module to have different definitions in the vendorA and vendorB libraries.

uselib is Persistent
As mentioned above, the appearance of a `uselib directive in the source code explicitly defines how instantiations that follow it are resolved. This may result in unexpected consequences. For example, consider the following compile command:
vlog -compile_uselibs dut.v srtr.v

Assume that dut.v contains a `uselib directive. Since srtr.v is compiled after dut.v, the `uselib directive is still in effect. When srtr is loaded it is using the `uselib directive from dut.v to decide where to locate modules. If this is not what you intend, then you need to put an empty `uselib at the end of dut.v to "close" the previous `uselib statement.

Verilog Configurations
The Verilog 2001 specification added configurations. Configurations specify how a design is "assembled" during the elaboration phase of simulation. Configurations actually consist of two pieces: the library mapping and the configuration itself. The library mapping is used at compile time to determine into which libraries the source files are to be compiled. Here is an example of a simple library map file:
library library library library work rtlLib gateLib aLib ../top.v; lrm_ex_top.v; lrm_ex_adder.vg; lrm_ex_adder.v;

Here is an example of a library map file that uses -incdir:

library lib1 src_dir/*.v -incdir ../include_dir2, ../, my_incdir;

The name of the library map file is arbitrary. You specify the library map file using the -libmap argument to the vlog command. Alternatively, you can specify the file name as the first item on the vlog command line, and the compiler will read it as a library map file. The library map file must be compiled along with the Verilog source files. Multiple map files are allowed but each must be preceded by the -libmap argument.

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The library map file and the configuration can exist in the same or different files. If they are separate, only the map file needs the -libmap argument. The configuration is treated as any other Verilog source file.

Configurations and the Library Named work

The library named work is treated specially by ModelSim (see The Library Named "work" for details) for Verilog configurations. Consider the following code example:
config cfg; design top; instance top.u1 use work.u1; endconfig

In this case, work.u1 indicates to load u1 from the current library.

Verilog Generate Statements

The Verilog 2001 rules for generate statements had numerous inconsistencies and ambiguities. As a result, ModelSim implements the rules that have been adopted for Verilog 2005. Most of the rules are backwards compatible, but there is one key difference related to name visibility.

Name Visibility in Generate Statements

Consider the following code example:
module m; parameter p = 1; generate if (p) integer x = 1; else real x = 2.0; endgenerate initial $display(x); endmodule

This code sample is legal under 2001 rules. However, it is illegal under the 2005 rules and will cause an error in ModelSim. Under the new rules, you cannot hierarchically reference a name in an anonymous scope from outside that scope. In the example above, x does not propagate its visibility upwards, and each condition alternative is considered to be an anonymous scope. To fix the code such that it will simulate properly in ModelSim, write it like this instead:

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Verilog and SystemVerilog Simulation Simulating Verilog Designs module m; parameter p = 1; if (p) begin:s integer x = 1; end else begin:s real x = 2.0; end initial $display(s.x); endmodule

Since the scope is named in this example, normal hierarchical resolution rules apply and the code is fine. Note too that the keywords generate - endgenerate are optional under the 2005 rules and are excluded in the second example.

Simulating Verilog Designs

A Verilog design is ready for simulation after it has been compiled with vlog. The simulator may then be invoked with the names of the top-level modules (many designs contain only one top-level module). For example, if your top-level modules are "testbench" and "globals", then invoke the simulator as follows:
vsim testbench globals

After the simulator loads the top-level modules, it iteratively loads the instantiated modules and UDPs in the design hierarchy, linking the design together by connecting the ports and resolving hierarchical references. By default all modules and UDPs are loaded from the library named work. Modules and UDPs from other libraries can be specified using the -L or -Lf arguments to vsim (see Library Usage for details). On successful loading of the design, the simulation time is set to zero, and you must enter a run command to begin simulation. Commonly, you enter run -all to run until there are no more simulation events or until $finish is executed in the Verilog code. You can also run for specific time periods (e.g., run 100 ns). Enter the quit command to exit the simulator.

Simulator Resolution Limit (Verilog)

The simulator internally represents time as a 64-bit integer in units equivalent to the smallest unit of simulation time, also known as the simulator resolution limit. The resolution limit defaults to the smallest time precision found among all of the `timescale compiler directives in the design. Here is an example of a `timescale directive:
`timescale 1 ns / 100 ps

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The first number is the time units and the second number is the time precision. The directive above causes time values to be read as ns and to be rounded to the nearest 100 ps. Time units and precision can also be specified with SystemVerilog keywords as follows:
timeunit 1 ns timeprecision 100 ps

Modules Without Timescale Directives

You may encounter unexpected behavior if your design contains some modules with timescale directives and others without. The time units for modules without a timescale directive default to the simulator resolution. For example, say you have the two modules shown in the table below:

Table 6-1. Sample Modules With and Without Timescale Directive Module 1 `timescale 1 ns / 10 ps module mod1 (set); output set; reg set; parameter d = 1.55; initial begin set = 1'bz; #d set = 1'b0; #d set = 1'b1; end endmodule If you invoke vsim as vsim mod2 mod1 then Module 1 sets the simulator resolution to 10 ps. Module 2 has no timescale directive, so the time units default to the simulator resolution, in this case 10 ps. If you watched /mod1/set and /mod2/set in the Wave window, youd see that in Module 1 it transitions every 1.55 ns as expected (because of the 1 ns time unit in the timescale directive). However, in Module 2, set transitions every 20 ps. Thats because the delay of 1.55 in Module 2 is read as 15.5 ps and is rounded up to 20 ps. In such cases ModelSim will issue the following warning message during elaboration: Module 2 module mod2 (set); output set; reg set; parameter d = 1.55; initial begin set = 1'bz; #d set = 1'b0; #d set = 1'b1; end endmodule

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Verilog and SystemVerilog Simulation Simulating Verilog Designs ** Warning: (vsim-3010) [TSCALE] - Module 'mod1' has a `timescale directive in effect, but previous modules do not.

If you invoke vsim as vsim mod1 mod2, the simulation results would be the same but ModelSim would produce a different warning message:
** Warning: (vsim-3009) [TSCALE] - Module 'mod2' does not have a `timescale directive in effect, but previous modules do.

These warnings should ALWAYS be investigated. If the design contains no `timescale directives, then the resolution limit and time units default to the value specified by the Resolution variable in the modelsim.ini file. (The variable is set to 1 ns by default.)

-timescale Option
The -timescale option can be used with the vlog and vopt to specifies the default timescale for modules not having an explicit `timescale directive in effect during compilation. The format of the -timescale argument is the same as that of the `timescale directive
-timescale <time_units>/<time_precision>

The format for <time_units> and <time_precision> is <n><units>. The value of <n> must be 1, 10, or 100. The value of <units> must be fs, ps, ns, us, ms, or s. In addition, the <time_units> must be greater than or equal to the <time_precision>. For example:
-timescale "1ns / 1ps"

The argument above needs quotes because it contains white space.

Multiple Timescale Directives

As alluded to above, your design can have multiple timescale directives. The timescale directive takes effect where it appears in a source file and applies to all source files which follow in the same vlog command. Separately compiled modules can also have different timescales. The simulator determines the smallest timescale of all the modules in a design and uses that as the simulator resolution.

timescale, -t, and Rounding

The optional vsim argument -t sets the simulator resolution limit for the overall simulation. If the resolution set by -t is larger than the precision set in a module, the time values in that module are rounded up. If the resolution set by -t is smaller than the precision of the module, the precision of that module remains whatever is specified by the `timescale directive. Consider the following code:

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Verilog and SystemVerilog Simulation Simulating Verilog Designs `timescale 1 ns / 100 ps module foo; initial #12.536 $display

The list below shows three possibilities for -t and how the delays in the module would be handled in each case: -t not set The delay will be rounded to 12.5 as directed by the modules timescale directive. -t is set to 1 fs The delay will be rounded to 12.5. Again, the modules precision is determined by the timescale directive. ModelSim does not override the modules precision. -t is set to 1 ns The delay will be rounded to 12. The modules precision is determined by the -t setting. ModelSim has no choice but to round the modules time values because the entire simulation is operating at 1 ns.

Choosing the Resolution for Verilog

You should choose the coarsest resolution limit possible that does not result in undesired rounding of your delays. The time precision should not be unnecessarily small because it will limit the maximum simulation time limit, and it will degrade performance in some cases.

Event Ordering in Verilog Designs

Event-based simulators such as ModelSim may process multiple events at a given simulation time. The Verilog language is defined such that you cannot explicitly control the order in which simultaneous events are processed. Unfortunately, some designs rely on a particular event order, and these designs may behave differently than you expect.

Event Queues
Section 5 of the IEEE Std 1364-1995 LRM defines several event queues that determine the order in which events are evaluated. At the current simulation time, the simulator has the following pending events: active events inactive events non-blocking assignment update events

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monitor events future events

o o

inactive events non-blocking assignment update events

The LRM dictates that events are processed as follows 1) all active events are processed; 2) the inactive events are moved to the active event queue and then processed; 3) the non-blocking events are moved to the active event queue and then processed; 4) the monitor events are moved to the active queue and then processed; 5) simulation advances to the next time where there is an inactive event or a non-blocking assignment update event. Within the active event queue, the events can be processed in any order, and new active events can be added to the queue in any order. In other words, you cannot control event order within the active queue. The example below illustrates potential ramifications of this situation. Say you have these four statements: 1. always@(q) p = q; 2. always @(q) p2 = not q; 3. always @(p or p2) clk = p and p2; 4. always @(posedge clk) and current values as follows: q = 0, p = 0, p2=1 The tables below show two of the many valid evaluations of these statements. Evaluation events are denoted by a number where the number is the statement to be evaluated. Update events are denoted <name>(old->new) where <name> indicates the reg being updated and new is the updated value.\ Table 6-2. Evaluation 1 of always Statements Event being processed q(0 -> 1) 1 p(0 -> 1) 3 clk(0 -> 1) 4 2 Active event queue q(0 -> 1) 1, 2 p(0 -> 1), 2 3, 2 clk(0 -> 1), 2 4, 2 2 p2(1 -> 0)

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Table 6-2. Evaluation 1 of always Statements (cont.) Event being processed p2(1 -> 0) 3 clk(1 -> 0) Active event queue 3 clk(1 -> 0) <empty>

Table 6-3. Evaluation 2 of always Statement Event being processed q(0 -> 1) 1 2 p(0 -> 1) p2(1 > 0) 3 Active event queue q(0 -> 1) 1, 2 p(0 -> 1), 2 p2(1 -> 0), p(0 -> 1) 3, p2(1 -> 0) 3 <empty> (clk doesnt change)

Again, both evaluations are valid. However, in Evaluation 1, clk has a glitch on it; in Evaluation 2, clk doesnt. This indicates that the design has a zero-delay race condition on clk.

Controlling Event Queues with Blocking or Non-Blocking Assignments

The only control you have over event order is to assign an event to a particular queue. You do this via blocking or non-blocking assignments.

Blocking Assignments
Blocking assignments place an event in the active, inactive, or future queues depending on what type of delay they have: a blocking assignment without a delay goes in the active queue a blocking assignment with an explicit delay of 0 goes in the inactive queue a blocking assignment with a non-zero delay goes in the future queue

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Non-Blocking Assignments
A non-blocking assignment goes into either the non-blocking assignment update event queue or the future non-blocking assignment update event queue. (Non-blocking assignments with no delays and those with explicit zero delays are treated the same.) Non-blocking assignments should be used only for outputs of flip-flops. This insures that all outputs of flip-flops do not change until after all flip-flops have been evaluated. Attempting to use non-blocking assignments in combinational logic paths to remove race conditions may only cause more problems. (In the preceding example, changing all statements to non-blocking assignments would not remove the race condition.) This includes using non-blocking assignments in the generation of gated clocks. The following is an example of how to properly use non-blocking assignments.
gen1: always @(master) clk1 = master; gen2: always @(clk1) clk2 = clk1; f1 : always @(posedge clk1) begin q1 <= d1; end f2: always @(posedge clk2) begin q2 <= q1; end

If written this way, a value on d1 always takes two clock cycles to get from d1 to q2. If you change clk1 = master and clk2 = clk1 to non-blocking assignments or q2 <= q1 and q1 <= d1 to blocking assignments, then d1 may get to q2 is less than two clock cycles.

Debugging Event Order Issues

Since many models have been developed on Verilog-XL, ModelSim tries to duplicate VerilogXL event ordering to ease the porting of those models to ModelSim. However, ModelSim does not match Verilog-XL event ordering in all cases, and if a model ported to ModelSim does not behave as expected, then you should suspect that there are event order dependencies. ModelSim helps you track down event order dependencies with the following compiler arguments: -compat, -hazards, and -keep_delta. See the vlog command for descriptions of -compat and -hazards.

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Hazard Detection
The -hazard argument to vsim detects event order hazards involving simultaneous reading and writing of the same register in concurrently executing processes. vsim detects the following kinds of hazards: WRITE/WRITE Two processes writing to the same variable at the same time. READ/WRITE One process reading a variable at the same time it is being written to by another process. ModelSim calls this a READ/WRITE hazard if it executed the read first. WRITE/READ Same as a READ/WRITE hazard except that ModelSim executed the write first.

vsim issues an error message when it detects a hazard. The message pinpoints the variable and the two processes involved. You can have the simulator break on the statement where the hazard is detected by setting the break on assertion level to Error. To enable hazard detection you must invoke vlog with the -hazards argument when you compile your source code and you must also invoke vsim with the -hazards argument when you simulate. Note Enabling -hazards implicitly enables the -compat argument. As a result, using this argument may affect your simulation results.

Hazard Detection and Optimization Levels

In certain cases hazard detection results are affected by the optimization level used in the simulation. Some optimizations change the read/write operations performed on a variable if the transformation is determined to yield equivalent results. Since the hazard detection algorithm doesnt know whether or not the read/write operations can affect the simulation results, the optimizations can result in different hazard detection results. Generally, the optimizations reduce the number of false hazards by eliminating unnecessary reads and writes, but there are also optimizations that can produce additional false hazards.

Limitations of Hazard Detection

Reads and writes involving bit and part selects of vectors are not considered for hazard detection. The overhead of tracking the overlap between the bit and part selects is too high. A WRITE/WRITE hazard is flagged even if the same value is written by both processes. A WRITE/READ or READ/WRITE hazard is flagged even if the write does not modify the variable's value.

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Glitches on nets caused by non-guaranteed event ordering are not detected. A non-blocking assignment is not treated as a WRITE for hazard detection purposes. This is because non-blocking assignments are not normally involved in hazards. (In fact, they should be used to avoid hazards.) Hazards caused by simultaneous forces are not detected.

Negative Timing Check Limits

Verilog supports negative limit values in the $setuphold and $recrem system tasks. These tasks have optional delayed versions of input signals to insure proper evaluation of models with negative timing check limits. Delay values for these delayed nets are determined by the simulator so that valid data is available for evaluation before a clocking signal. Example 6-4. Negative Timing Check
$setuphold(posedge clk, negedge d, 5, -3, Notifier,,, clk_dly, d_dly);

d violation region clk

3 0

ModelSim calculates the delay for signal d_dly as 4 time units instead of 3. It does this to prevent d_dly and clk_dly from occurring simultaneously when a violation isnt reported. ModelSim accepts negative limit checks by default, unlike current versions of Verilog-XL. To match Verilog-XL default behavior (i.e., zeroing all negative timing check limits), use the +no_neg_tcheck argument to vsim.

Negative Timing Constraint Algorithm

The algorithm ModelSim uses to calculate delays for delayed nets isnt described in IEEE Std 1364. Rather, ModelSim matches Verilog-XL behavior. The algorithm attempts to find a set of delays so the data net is valid when the clock net transitions and the timing checks are satisfied. The algorithm is iterative because a set of delays can be selected that satisfies all timing checks for a pair of inputs but then causes mis-ordering of another pair (where both pairs of inputs share a common input). When a set of delays that satisfies all timing checks is found, the delays are said to converge.

Using Delayed Inputs for Timing Checks

By default ModelSim performs timing checks on inputs specified in the timing check. If you want timing checks performed on the delayed inputs, use the +delayed_timing_checks argument with the vsim command.

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Consider an example. This timing check:

$setuphold(posedge clk, posedge t, 20, -12, NOTIFIER,,, clk_dly, t_dly);

reports a timing violation when posedge t occurs in the violation region:

20 t 0 clk -12

With the +delayed_timing_checks argument, the violation region between the delayed inputs is:
7 t_dly 0 clk_dly 1

Although the check is performed on the delayed inputs, the timing check violation message is adjusted to reference the undelayed inputs. Only the report time of the violation message is noticeably different between the delayed and undelayed timing checks. By far the greatest difference between these modes is evident when there are conditions on a delayed check event because the condition is not implicitly delayed. Also, timing checks specified without explicit delayed signals are delayed, if necessary, when they reference an input that is delayed for a negative timing check limit. Other simulators perform timing checks on the delayed inputs. To be compatible, ModelSim supports both methods.

Verilog-XL Compatible Simulator Arguments

The simulator arguments listed below are equivalent to Verilog-XL arguments and may ease the porting of a design to ModelSim. See the vsim command for a description of each argument.
+alt_path_delays -l <filename> +maxdelays +mindelays +multisource_int_delays +no_cancelled_e_msg +no_neg_tchk +no_notifier +no_path_edge +no_pulse_msg -no_risefall_delaynets +no_show_cancelled_e +nosdfwarn +nowarn<mnemonic>

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Verilog and SystemVerilog Simulation Simulating Verilog Designs +ntc_warn +pulse_e/<percent> +pulse_e_style_ondetect +pulse_e_style_onevent +pulse_int_e/<percent> +pulse_int_r/<percent> +pulse_r/<percent> +sdf_nocheck_celltype +sdf_verbose +show_cancelled_e +transport_int_delays +transport_path_delays +typdelays

Using Escaped Identifiers

ModelSim always converts Verilog escaped identifiers to VHDL syntax. In Verilog, escaped identifiers start with the backslash character and end with a white space. Neither the backslash at the beginning or the white space at the end are considered to be a part of the identifier. When a ModelSim displays Verilog escaped identifiers, however, a backslash is added at the end in order to match the VHDL syntax for escaped identifiers. This is because all Verilog escaped identifiers can be easily converted to VHDL but the converse is not true. So, for example, a Verilog escaped identifier like the following:
\/top/dut/03

will be displayed as follows:

\/top/dut/03\

When entering Verilog identifiers with the ModelSim command line interface, you should use the VHDL syntax, with a backslash at the beginning and end of the identifier. In Tcl, the backslash is one of a number of characters that have a special meaning. For example,
\n

creates a new line. When a Tcl command is used in the command line interface, the TCL backslash should be escaped by adding another backslash. For example:
force -freeze /top/ix/iy/\\yw\[1\]\\ 10 0, 01 {50 ns} -r 100

The Verilog identifier, in this example, is \yw[1]. Here, double backslashes are used because it is necessary to escape the square brackets ([]), which have a special meaning in Tcl. For a more detailed description of special characters in Tcl and how backslashes should be used with those characters, click Help > Tcl Syntax in the menu bar of the graphic interface, or simply open the docs/tcl_help_html/TclCmd directory in your ModelSim installation.
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Cell Libraries
Model Technology passed the ASIC Councils Verilog test suite and achieved the "Library Tested and Approved" designation from Si2 Labs. This test suite is designed to ensure Verilog timing accuracy and functionality and is the first significant hurdle to complete on the way to achieving full ASIC vendor support. As a consequence, many ASIC and FPGA vendors Verilog cell libraries are compatible with ModelSim Verilog. The cell models generally contain Verilog "specify blocks" that describe the path delays and timing constraints for the cells. See section 13 in the IEEE Std 1364-1995 for details on specify blocks, and section 14.5 for details on timing constraints. ModelSim Verilog fully implements specify blocks and timing constraints as defined in IEEE Std 1364 along with some Verilog-XL compatible extensions.

SDF Timing Annotation

ModelSim Verilog supports timing annotation from Standard Delay Format (SDF) files. See Standard Delay Format (SDF) Timing Annotation for details.

Delay Modes
Verilog models may contain both distributed delays and path delays. The delays on primitives, UDPs, and continuous assignments are the distributed delays, whereas the port-to-port delays specified in specify blocks are the path delays. These delays interact to determine the actual delay observed. Most Verilog cells use path delays exclusively, with the distributed delays set to zero. For example,
module and2(y, a, b); input a, b; output y; and(y, a, b); specify (a => y) = 5; (b => y) = 5; endspecify endmodule

In the above two-input "and" gate cell, the distributed delay for the "and" primitive is zero, and the actual delays observed on the module ports are taken from the path delays. This is typical for most cells, but a complex cell may require non-zero distributed delays to work properly. Even so, these delays are usually small enough that the path delays take priority over the distributed delays. The rule is that if a module contains both path delays and distributed delays, then the larger of the two delays for each path shall be used (as defined by the IEEE Std 1364). This is the default behavior, but you can specify alternate delay modes with compiler directives and

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arguments. These arguments and directives are compatible with Verilog-XL. Compiler delay mode arguments take precedence over delay mode directives in the source code.

Distributed Delay Mode

In distributed delay mode the specify path delays are ignored in favor of the distributed delays. Select this delay mode with the +delay_mode_distributed compiler argument or the `delay_mode_distributed compiler directive.

Path Delay Mode

In path delay mode the distributed delays are set to zero in any module that contains a path delay. Select this delay mode with the +delay_mode_path compiler argument or the `delay_mode_path compiler directive.

Unit Delay Mode

In unit delay mode the non-zero distributed delays are set to one unit of simulation resolution (determined by the minimum time_precision argument in all timescale directives in your design or the value specified with the -t argument to vsim), and the specify path delays and timing constraints are ignored. Select this delay mode with the +delay_mode_unit compiler argument or the `delay_mode_unit compiler directive.

Zero Delay Mode

In zero delay mode the distributed delays are set to zero, and the specify path delays and timing constraints are ignored. Select this delay mode with the +delay_mode_zero compiler argument or the `delay_mode_zero compiler directive.

System Tasks and Functions

ModelSim supports system tasks and functions as follows: All system tasks and functions defined in IEEE Std 1364 Some system tasks and functions defined in SystemVerilog IEEE std p1800-2005 LRM Several system tasks and functions that are specific to ModelSim Several non-standard, Verilog-XL system tasks

The system tasks and functions listed in this section are built into the simulator, although some designs depend on user-defined system tasks implemented with the Programming Language Interface (PLI), Verilog Procedural Interface (VPI), or the SystemVerilog DPI (Direct Programming Interface). If the simulator issues warnings regarding undefined system tasks or functions, then it is likely that these tasks or functions are defined by a PLI/VPI application that must be loaded by the simulator.
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IEEE Std 1364 System Tasks and Functions

The following system tasks and functions are described in detail in the IEEE Std 1364. Table 6-4. IEEE Std 1364 System Tasks and Functions - 1 Timescale tasks $printtimescale $timeformat Simulator control tasks $finish $stop Simulation time functions $realtime $stime $time Command line input $test$plusargs $value$plusargs

Table 6-5. IEEE Std 1364 System Tasks and Functions - 2 Probabilistic distribution functions $dist_chi_square $dist_erlang $dist_exponential $dist_normal $dist_poisson $dist_t $dist_uniform $random Conversion functions $bitstoreal $itor $realtobits $rtoi $signed $unsigned Stochastic analysis tasks $q_add $q_exam $q_full $q_initialize $q_remove Timing check tasks

$hold $nochange $period $recovery $setup $setuphold $skew $width1 $removal $recrem

1. Verilog-XL ignores the threshold argument even though it is part of the Verilog spec. ModelSim does not ignore this argument. Be careful that you dont set the threshold argument greater-than-or-equal to the limit argument as that essentially disables the $width check. Note too that you cannot override the threshold argument via SDF annotation.

Table 6-6. IEEE Std 1364 System Tasks Display tasks $display PLA modeling tasks $async$and$array Value change dump (VCD) file tasks $dumpall

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Table 6-6. IEEE Std 1364 System Tasks (cont.) Display tasks $displayb $displayh $displayo $monitor $monitorb $monitorh $monitoro $monitoroff $monitoron $strobe $strobeb $strobeh $strobeo $write $writeb $writeh $writeo PLA modeling tasks $async$nand$array $async$or$array $async$nor$array $async$and$plane $async$nand$plane $async$or$plane $async$nor$plane $sync$and$array $sync$nand$array $sync$or$array $sync$nor$array $sync$and$plane $sync$nand$plane $sync$or$plane $sync$nor$plane Value change dump (VCD) file tasks $dumpfile $dumpflush $dumplimit $dumpoff $dumpon $dumpvars

Table 6-7. IEEE Std 1364 File I/O Tasks File I/O tasks $fclose $fdisplay $fdisplayb $fdisplayh $fdisplayo $feof $ferror $fflush $fgetc
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$fmonitoro $fopen $fread $fscanf $fseek $fstrobe $fstrobeb $fstrobeh $fstrobeo

$fwriteh $fwriteo $readmemb $readmemh $rewind $sdf_annotate $sformat $sscanf $swrite

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Table 6-7. IEEE Std 1364 File I/O Tasks (cont.) File I/O tasks $fgets $fmonitor $fmonitorb $fmonitorh $ftell $fwrite $fwriteb $swriteb $swriteh $swriteo $ungetc

SystemVerilog System Tasks and Functions

The following ModelSim-supported system tasks and functions are described in detail in the SystemVerilog IEEE Std p1800-2005 LRM. Table 6-8. SystemVerilog System Tasks and Functions - 1 Expression size function $bits Range function $isunbounded

Table 6-9. SystemVerilog System Tasks and Functions - 2 Shortreal conversions $shortrealbits $bitstoshortreal Array querying functions $dimensions $left $right $low $high $increment $size

Table 6-10. SystemVerilog System Tasks and Functions - 4 Reading packed data functions $readmemb $readmemh Writing packed data functions $writememb $writememh Other functions $root $unit

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System Tasks and Functions Specific to the Tool

The following system tasks and functions are specific to ModelSim. They are not included in the IEEE Std 1364, nor are they likely supported in other simulators. Their use may limit the portability of your code.
$coverage_save(<filename>, [<instancepath>], [<xml_output>])

The $coverage_save() system function saves only Code Coverage information to a file during a batch run that typically would terminate via the $finish call. It also returns a 1 to indicate that the coverage information was saved successfully or a 0 to indicate an error (unable to open file, instance name not found, etc.) If you dont specify <instancepath>, ModelSim saves all coverage data in the current design to the specified file. If you do specify <instancepath>, ModelSim saves data on that instance, and all instances below it (recursively), to the specified file. If set to 1, the [<xml_output>] argument specifies that the output be saved in XML format. See Coverage for more information on Code Coverage.
$init_signal_driver

The $init_signal_driver() system task drives the value of a VHDL signal or Verilog net onto an existing VHDL signal or Verilog net. This allows you to drive signals or nets at any level of the design hierarchy from within a Verilog module (e.g., a testbench). See $init_signal_driver for complete details.
$init_signal_spy

The $init_signal_spy() system task mirrors the value of a VHDL signal or Verilog register/net onto an existing Verilog register or VHDL signal. This system task allows you to reference signals, registers, or nets at any level of hierarchy from within a Verilog module (e.g., a testbench). See $init_signal_spy for complete details.
$psprintf()

The $psprintf() system function behaves like the $sformat() file I/O task except that the string result is passed back to the user as the function return value for $psprintf(), not placed in the first argument as for $sformat(). Thus $psprintf() can be used where a string is valid. Note that at this time, unlike other system tasks and functions, $psprintf() cannot be overridden by a user-defined system function in the PLI.
$signal_force

The $signal_force() system task forces the value specified onto an existing VHDL signal or Verilog register or net. This allows you to force signals, registers, or nets at any level of the design hierarchy from within a Verilog module (e.g., a testbench). A $signal_force works the same as the force command with the exception that you cannot issue a repeating force. See $signal_force for complete details.

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Verilog and SystemVerilog Simulation System Tasks and Functions $signal_release

The $signal_release() system task releases a value that had previously been forced onto an existing VHDL signal or Verilog register or net. A $signal_release works the same as the noforce command. See $signal_release for complete details.
$sdf_done

This task is a "cleanup" function that removes internal buffers, called MIPDs, that have a delay value of zero. These MIPDs are inserted in response to the -v2k_int_delay argument to the vsim command. In general the simulator will automatically remove all zero delay MIPDs. However, if you have $sdf_annotate() calls in your design that are not getting executed, the zero-delay MIPDs are not removed. Adding the $sdf_done task after your last $sdf_annotate() will remove any zero-delay MIPDs that have been created.

Verilog-XL Compatible System Tasks and Functions

ModelSim supports a number of Verilog-XL specific system tasks and functions.

Supported Tasks and Functions Mentioned in IEEE Std 1364

The following supported system tasks and functions, though not part of the IEEE standard, are described in an annex of the IEEE Std 1364.
$countdrivers $getpattern $sreadmemb $sreadmemh

Supported Tasks not Described in the IEEE Std 1364

The following system tasks are also provided for compatibility with Verilog-XL, though they are not described in the IEEE Std 1364.
$deposit(variable, value);

This system task sets a Verilog register or net to the specified value. variable is the register or net to be changed; value is the new value for the register or net. The value remains until there is a subsequent driver transaction or another $deposit task for the same register or net. This system task operates identically to the ModelSim force -deposit command.
$disable_warnings("<keyword>"[,<module_instance>...]);

This system task instructs ModelSim to disable warnings about timing check violations or triregs that acquire a value of X due to charge decay. <keyword> may be decay or timing. You can specify one or more module instance names. If you dont specify a module instance, ModelSim disables warnings for the entire simulation.

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Verilog and SystemVerilog Simulation System Tasks and Functions $enable_warnings("<keyword>"[,<module_instance>...]);

This system task enables warnings about timing check violations or triregs that acquire a value of X due to charge decay. <keyword> may be decay or timing. You can specify one or more module instance names. If you dont specify a module_instance, ModelSim enables warnings for the entire simulation.
$system("command");

This system function takes a literal string argument, executes the specified operating system command, and displays the status of the underlying OS process. Double quotes are required for the OS command. For example, to list the contents of the working directory on Unix:
$system("ls -l");

Return value of the $system function is a 32-bit integer that is set to the exit status code of the underlying OS process. Note There is a known issue in the return value of this system function on the win32 platform. If the OS command is built with a cygwin compiler, the exit status code may not be reported correctly when an exception is thrown, and thus the return code may be wrong. The workaround is to avoid building the application using cygwin or to use the switch -mno-cygwin in cygwin the gcc command line.
$systemf(list_of_args)

This system function can take any number of arguments. The list_of_args is treated exactly the same as with the $display() function. The OS command that will be run is the final output from $display() given the same list_of_args. Return value of the $systemf function is a 32-bit integer that is set to the exit status code of the underlying OS process. Note There is a known issue in the return value of this system function on the win32 platform. If the OS command is built with a cygwin compiler, the exit status code may not be reported correctly when an exception is thrown, and thus the return code may be wrong. The workaround is to avoid building the application using cygwin or to use the switch -mno-cygwin in cygwin the gcc command line.

Supported Tasks that Have Been Extended

The following system tasks are extended to provide additional functionality for negative timing constraints and an alternate method of conditioning, as in Verilog-XL.
$recovery(reference event, data_event, removal_limit, recovery_limit, [notifier], [tstamp_cond], [tcheck_cond], [delayed_reference], [delayed_data])

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The $recovery system task normally takes a recovery_limit as the third argument and an optional notifier as the fourth argument. By specifying a limit for both the third and fourth arguments, the $recovery timing check is transformed into a combination removal and recovery timing check similar to the $recrem timing check. The only difference is that the removal_limit and recovery_limit are swapped.
$setuphold(clk_event, data_event, setup_limit, hold_limit, [notifier], [tstamp_cond], [tcheck_cond], [delayed_clk], [delayed_data])

The tstamp_cond argument conditions the data_event for the setup check and the clk_event for the hold check. This alternate method of conditioning precludes specifying conditions in the clk_event and data_event arguments. The tcheck_cond argument conditions the data_event for the hold check and the clk_event for the setup check. This alternate method of conditioning precludes specifying conditions in the clk_event and data_event arguments. The delayed_clk argument is a net that is continuously assigned the value of the net specified in the clk_event. The delay is non-zero if the setup_limit is negative, zero otherwise. The delayed_data argument is a net that is continuously assigned the value of the net specified in the data_event. The delay is non-zero if the hold_limit is negative, zero otherwise. The delayed_clk and delayed_data arguments are provided to ease the modeling of devices that may have negative timing constraints. The model's logic should reference the delayed_clk and delayed_data nets in place of the normal clk and data nets. This ensures that the correct data is latched in the presence of negative constraints. The simulator automatically calculates the delays for delayed_clk and delayed_data such that the correct data is latched as long as a timing constraint has not been violated. See Negative Timing Check Limits for more details.

Unsupported Verilog-XL System Tasks

The following system tasks are Verilog-XL system tasks that are not implemented in ModelSim Verilog, but have equivalent simulator commands.
$input("filename")

This system task reads commands from the specified filename. The equivalent simulator command is do <filename>.
$list[(hierarchical_name)]

This system task lists the source code for the specified scope. The equivalent functionality is provided by selecting a module in the structure pane of the Workspace. The corresponding source code is displayed in a Source window.
$reset

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This system task resets the simulation back to its time 0 state. The equivalent simulator command is restart.
$restart("filename")

This system task sets the simulation to the state specified by filename, saved in a previous call to $save. The equivalent simulator command is restore <filename>.
$save("filename")

This system task saves the current simulation state to the file specified by filename. The equivalent simulator command is checkpoint <filename>.
$scope(hierarchical_name)

This system task sets the interactive scope to the scope specified by hierarchical_name. The equivalent simulator command is environment <pathname>.
$showscopes

This system task displays a list of scopes defined in the current interactive scope. The equivalent simulator command is show.
$showvars

This system task displays a list of registers and nets defined in the current interactive scope. The equivalent simulator command is show.

Compiler Directives
ModelSim Verilog supports all of the compiler directives defined in the IEEE Std 1364, some Verilog-XL compiler directives, and some that are proprietary. The SystemVerilog IEEE Std P1800-2005 version of the define and include compiler directives are not currently supported. Many of the compiler directives (such as `timescale) take effect at the point they are defined in the source code and stay in effect until the directive is redefined or until it is reset to its default by a `resetall directive. The effect of compiler directives spans source files, so the order of source files on the compilation command line could be significant. For example, if you have a file that defines some common macros for the entire design, then you might need to place it first in the list of files to be compiled. The `resetall directive affects only the following directives by resetting them back to their default settings (this information is not provided in the IEEE Std 1364):

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Verilog and SystemVerilog Simulation Compiler Directives `celldefine default_decay_time `default_nettype `delay_mode_distributed `delay_mode_path `delay_mode_unit `delay_mode_zero `protected `timescale `unconnected_drive `uselib

ModelSim Verilog implicitly defines the following macro:

`define MODEL_TECH

IEEE Std 1364 Compiler Directives

The following compiler directives are described in detail in the IEEE Std 1364.
`celldefine `default_nettype `define `else `elsif `endcelldefine `endif `ifdef ifndef `include line `nounconnected_drive `resetall `timescale `unconnected_drive `undef

Compiler Directives for vlog

The following directives are specific to ModelSim and are not compatible with other simulators (see note below).
protect ... endprotect

This directive pair allows you to encrypt selected regions of your source code. The code in `protect regions has all debug information stripped out. This behaves exactly as if using the -nodebug argument except that it applies to selected regions of code rather than the whole file. This enables usage scenarios such as making module ports, parameters, and specify blocks publicly visible while keeping the implementation private. The `protect directive is ignored by default unless you use the +protect argument to vlog. Once compiled, the original source file is copied to a new file in the current work
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directory. The name of the new file is the same as the original file with a "p" appended to the suffix. For example, "top.v" is copied to "top.vp". This new file can be delivered and used as a replacement for the original source file. A usage scenario might be that a vendor will use the `protect / `endprotect directives on a module or a portion of a module in a file named filename.v. They will compile it with vlog +protect filename.v to produce a new file named filename.vp. You can compile filename.vp just like any other verilog file. The protection is not compatible between tools, so the vendor mush ship you a different filename.vp than they ship to some who uses a different simulator. The +protect argument is not required when compiling .vp files because the `protect directives are converted to `protected directives which are processed even if +protect is omitted. `protect and `protected directives cannot be nested. If any `include directives occur within a protected region, the compiler generates a copy of the include file with a ".vp" suffix and protects the entire contents of the include file. If errors are detected in a protected region, the error message always reports the first line of the protected block. Though other simulators have a `protect directive, the algorithm ModelSim uses to encrypt source files is different. Hence, even though an uncompiled source file with `protect is compatible with another simulator, once the source is compiled in ModelSim, you could not simulate it elsewhere.

Verilog-XL Compatible Compiler Directives

The following compiler directives are provided for compatibility with Verilog-XL.
default_decay_time <time>

This directive specifies the default decay time to be used in trireg net declarations that do not explicitly declare a decay time. The decay time can be expressed as a real or integer number, or as "infinite" to specify that the charge never decays.
`delay_mode_distributed

This directive disables path delays in favor of distributed delays. See Delay Modes for details.
`delay_mode_path

This directive sets distributed delays to zero in favor of path delays. See Delay Modes for details.
`delay_mode_unit

This directive sets path delays to zero and non-zero distributed delays to one time unit. See Delay Modes for details.
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Verilog and SystemVerilog Simulation Verilog PLI/VPI and SystemVerilog DPI `delay_mode_zero

This directive sets path delays and distributed delays to zero. See Delay Modes for details.
`uselib

This directive is an alternative to the -v, -y, and +libext source library compiler arguments. See Verilog-XL uselib Compiler Directive for details. The following Verilog-XL compiler directives are silently ignored by ModelSim Verilog. Many of these directives are irrelevant to ModelSim Verilog, but may appear in code being ported from Verilog-XL.
`accelerate `autoexpand_vectornets `disable_portfaults `enable_portfaults `expand_vectornets `noaccelerate `noexpand_vectornets `noremove_gatenames `noremove_netnames `nosuppress_faults `remove_gatenames `remove_netnames `suppress_faults

The following Verilog-XL compiler directives produce warning messages in ModelSim Verilog. These are not implemented in ModelSim Verilog, and any code containing these directives may behave differently in ModelSim Verilog than in Verilog-XL.
`default_trireg_strength `signed `unsigned

Verilog PLI/VPI and SystemVerilog DPI

ModelSim supports the use of the Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) and the SystemVerilog DPI (Direct Programming Interface). These three interfaces provide a mechanism for defining tasks and functions that communicate with the simulator through a C procedural interface. For more information on the ModelSim implementation, see Verilog PLI/VPI/DPI.

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Chapter 7 SystemC Simulation

This chapter describes how to compile and simulate SystemC designs with ModelSim. ModelSim implements the SystemC language based on the Open SystemC Initiative (OSCI) SystemC 2.1 reference simulator. It is recommended that you obtain the OSCI functional specification, or the latest version of the SystemC Language Reference Manual as a reference manual. Visit http://www.systemc.org for details. Note The functionality described in this chapter requires a systemc license feature in your ModelSim license file. Please contact your Mentor Graphics sales representative if you currently do not have such a feature. In addition to the functionality described in the OSCI specification, ModelSim for SystemC includes the following features: Single common Graphic Interface for SystemC and HDL languages. Extensive support for mixing SystemC, VHDL, and Verilog in the same design (SDF annotation for HDL only). For detailed information on mixing SystemC with HDL see Mixed-Language Simulation.

Supported Platforms and Compiler Versions

SystemC runs on a subset of ModelSim supported platforms. The table below shows the currently supported platforms and compiler versions: Table 7-1. Supported Platforms for SystemC Platform HP-UX 11.0 or later RedHat Linux 7.2 and 7.3, RedHat Linux Enterprise version 2.1 AMD64 / SUSE Linux Enterprise Server 9.0, 9.1 or Red Hat Enterprise Linux 3, 4 Solaris 8, 9, and 10 Supported compiler versions aCC 3.45 with associated patches gcc 3.2.3, gcc 4.0.2 gcc 4.0.2 VCO is linux (32-bit binary) VCO is linux_x86_64 (64-bit binary) gcc 3.3 32-bit 64-bit support support yes yes yes no no yes

yes

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Table 7-1. Supported Platforms for SystemC Platform Windows 2000 and XP Supported compiler versions Minimalist GNU for Windows (MinGW) gcc 3.3.1 32-bit 64-bit support support yes no

Note ModelSim SystemC has been tested with the gcc versions available from the install tree. Customized versions of gcc may cause problems. We strongly encourage you to use the supplied gcc versions.

Building gcc with Custom Configuration Options

We only test with our default options. If you use advanced gcc configuration options, we cannot guarantee that ModelSim will work with those options. To use a custom gcc build, set the CppPath variable in the modelsim.ini file. This variable specifies the pathname to the compiler binary you intend to use. When using a custom gcc, ModelSim requires that the custom gcc be built with several specific configuration options. These vary on a per-platform basis as shown in the following table: Table 7-2. Custom gcc Platform Requirements Platform Linux Solaris HP-UX Win32 (MinGW) Mandatory configuration options none --with-gnu-ld --with-ld=/path/to/binutils-2.14/bin/ld --with-gnu-as --with-as=/path/to/binutils-2.14/bin/as N/A --with-gnu-ld --with-gnu-as Do NOT build with: --enable-sjlj-exceptions option as it can cause problems with catching exceptions thrown from SC_THREAD and SC_CTHREAD ld.exe and as.exe should be installed into the <install_dir>/bin before building gcc. ld and as are available in the binutils package. ModelSim uses binutils 2.13.90-20021006-2.

If you don't have a GNU binutils2.14 assembler and linker handy, you can use the as and ld programs distributed with ModelSim. They are located inside the built-in gcc in directory <install_dir>/modeltech/gcc-3.2-<mtiplatform>/lib/gcc-lib/<gnuplatform>/3.2. By default ModelSim also uses the following options when configuring built-in gcc:

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--disable-nls --enable-languages=c,c++

These are not mandatory, but they do reduce the size of the gcc installation.

HP Limitations for SystemC

HP is supported for SystemC with the following limitations: variables are not supported aggregates are not supported objects must be explicitly named, using the same name as their object, in order to debug

SystemC simulation objects such as modules, primitive channels, and ports can be explicitly named by passing a name to the constructors of said objects. If an object is not constructed with an explicit name, then the OSCI reference simulator generates an internal name for it, using names such as "signal_0", "signal_1", and so forth.

Required Patch for HP-UX 11.11

If you are running on HP-UX 11.11, you must have the following patch installed: B.11.11.0306 Gold Base Patches for HP-UX 11i, June 2003.

Usage Flow for SystemC-Only Designs

ModelSim allows users to simulate SystemC, either alone or in combination with other VHDL/Verilog modules. The following is an overview of the usage flow for strictly SystemC designs. More detailed instructions are presented in the sections that follow. 1. Create and map the working design library with the vlib and vmap statements, as appropriate to your needs. 2. Modify the SystemC source code, including the following highlights: a. Replace sc_main() with an SC_MODULE, and potentially add a process to contain any testbench code b. Replace sc_start() by using the run command in the GUI c. Remove calls to sc_initialize() d. Export the top level SystemC design unit(s) using the SC_MODULE_EXPORT macro See Modifying SystemC Source Code for a complete list of all modifications.

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3. Analyze the SystemC source using sccom. sccom invokes the native C++ compiler to create the C++ object files in the design library. See Using sccom in Addition to the Raw C++ Compiler for information on when you are required to use sccom vs. another C++ compiler. 4. Perform a final link of the C++ source using sccom -link. This process creates a shared object file in the current work library which will be loaded by vsim at runtime. sccom -link must be re-run before simulation if any new sccom compiles were performed. 5. Simulate the design using the standard vsim command. 6. Simulate the design using the run command, entered at the vsim command prompt. 7. Debug the design using ModelSim GUI features, including the Source and Wave windows.

Compiling SystemC Files

To compile SystemC designs, you must: create a design library modify the SystemC source code run the sccom SystemC compiler run the sccom SystemC linker (sccom -link)

Creating a Design Library for SystemC

Before you can compile your design, you must create a library in which to store the compilation results. Use vlib to create a new library. For example:
vlib work

This creates a library named work. By default, compilation results are stored in the work library. The work library is actually a subdirectory named work. This subdirectory contains a special file named _info. Do not create libraries using UNIX commands always use the vlib command. See Design Libraries for additional information on working with libraries.

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Modifying SystemC Source Code

Several modifications must be applied to your original SystemC source code. To see example code containing the modifications listed below, see Code Modification Examples.

Converting sc_main() to a Module

In order for ModelSim to run the SystemC/C++ source code, the control function of sc_main() must be replaced by a constructor, SC_CTOR(), placed within a module at the top level of the design (see mytop in Example 7-1). In addition: any testbench code inside sc_main() should be moved to a process, normally an SC_THREAD process. all C++ variables in sc_main(), including SystemC primitive channels, ports, and modules, must be defined as members of sc_module. Therefore, initialization must take place in the SC_CTOR. For example, all sc_clock() and sc_signal() initializations must be moved into the constructor.

Replacing sc_start() Function with Run Command and Options

ModelSim uses the run command and its options in place of the sc_start() function. If sc_main() has multiple sc_start() calls mixed in with the testbench code, then use an SC_THREAD() with wait statements to emulate the same behavior. An example of this is shown in Code Modification Examples on page 208.

Removing Calls to sc_initialize()

vsim calls sc_initialize() by default at the end of elaboration, so calls to sc_initialize() are unnecessary.

Exporting All Top Level SystemC Modules

For SystemC designs, you must export all top level modules in your design to ModelSim. You do this with the SC_MODULE_EXPORT(<sc_module_name>) macro. SystemC templates are not supported as top level or boundary modules. See Templatized SystemC Modules. The sc_module_name is the name of the top level module to be simulated in ModelSim. You must specify this macro in a C++ source (.cpp) file. If the macro is contained in a header file instead of a C++ source file, an error may result.

Explicitly Naming Signals, Ports, And Modules for HP-UX

Important: Verify that SystemC signals, ports, and modules are explicitly named to avoid port binding and debugging errors.

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Code Modification Examples

Example 7-1. Converting sc_main to a Module The following is a simple example of how to convert sc_main to a module and elaborate it with vsim. Table 7-3. Simple Conversion - sc_main to Module Original OSCI code #1 (partial)
int sc_main(int argc, char* argv[]) { sc_signal<bool> mysig; mymod mod("mod"); mod.outp(mysig); sc_start(100, SC_NS); } }; SC_MODULE_EXPORT(mytop);

Modified code #1 (partial)

SC_MODULE(mytop) { sc_signal<bool> mysig; mymod mod; SC_CTOR(mytop) : mysig("mysig"), mod("mod") { mod.outp(mysig); }

The run command equivalent to the sc_start(100, SC_NS) statement is:

run 100 ns

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Example 7-2. Using sc_main and Signal Assignments This next example is slightly more complex, illustrating the use of sc_main() and signal assignments, and how you would get the same behavior using ModelSim. Table 7-4. Using sc_main and Signal Assignments OSCI code #2 (partial)
int sc_main(int, char**) { sc_signal<bool> reset; counter_top top("top"); sc_clock CLK("CLK", 10, SC_NS, 0.5, 0.0, SC_NS, false); top.reset(reset); reset.write(1); sc_start(5, SC_NS); reset.write(0); sc_start(100, SC_NS); reset.write(1); sc_start(5, SC_NS); reset.write(0); sc_start(100, SC_NS); }

Modified code #2 (partial)

SC_MODULE(new_top) { sc_signal<bool> reset; counter_top top; sc_clock CLK; void sc_main_body(); SC_CTOR(new_top) : reset("reset"), top("top") CLK("CLK", 10, SC_NS, 0.5, 0.0, SC_NS, false) { top.reset(reset); SC_THREAD(sc_main_body); } }; void new_top::sc_main_body() { reset.write(1); wait(5, SC_NS); reset.write(0); wait(100, SC_NS); reset.write(1); wait(5, SC_NS); reset.write(0); wait(100, SC_NS); sc_stop(); } SC_MODULE_EXPORT(new_top);

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Example 7-3. Using an SCV Transaction Database One last example illustrates the correct way to modify a design using an SCV transaction database. ModelSim requires that the transaction database be created before calling the constructors on the design subelements. The example is as follows: Table 7-5. Modifications Using SCV Transaction Database Original OSCI code # 3 (partial)
int sc_main(int argc, char* argv[]) { scv_startup(); scv_tr_text_init(); scv_tr_db db("my_db"); scv_tr_db db::set_default_db(&db); sc_clock clk ("clk",20,0.5,0,true); sc_signal<bool> rw; test t("t"); t.clk(clk);; t.rw(rw); sc_start(100); } }; SC_MODULE_EXPORT(new_top); }

Modified ModelSim code #3 (partial)

SC_MODULE(top) { sc_signal<bool>* rw; test* t; SC_CTOR(top) { scv_startup(); scv_tr_text_init() scv_tr_db* db = new scv_tr_db("my_db"); scv_tr_db::set_default_db(db):; clk = new sc_clock("clk",20,0.5,0,true); rw = new sc_signal<bool> ("rw"); t = new test("t");

Take care to preserve the order of functions called in sc_main() of the original code. Sub-elements cannot be placed in the initializer list, since the constructor body must be executed prior to their construction. Therefore, the sub-elements must be made pointer types, created with "new" in the SC_CTOR() module.

Invoking the SystemC Compiler

ModelSim compiles one or more SystemC design units with a single invocation of sccom, the SystemC compiler. The design units are compiled in the order that they appear on the command line. For SystemC designs, all design units must be compiled just as they would be for any C++ compilation. An example of an sccom command might be:
sccom -I ../myincludes mytop.cpp mydut.cpp

Compiling Optimized and/or Debug Code

By default, sccom invokes the C++ compiler (g++ or aCC) without any optimizations. If desired, you can enter any g++/aCC optimization arguments at the sccom command line.

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Also, source level debug of SystemC code is not available by default in ModelSim. To compile your SystemC code for source level debugging in ModelSim, use the g++/aCC -g argument on the sccom command line.

Reducing Compilation Time for Non-Debug Simulations

If the SystemC objects in the design need not be visible in the ModelSim simulation database, you can save compilation time by running sccom with the -nodebug argument. This bypasses the parser which creates the ModelSim debug database. However, all files containing an SC_MODULE_EXPORT() macro call must NOT be compiled with the sccom -nodebug argument, otherwise the design fails to load. This approach is useful if you are running a design in regression mode, or creating a library (.a) from the object files (.o) created by sccom, to be linked later with the SystemC shared object.

Specifying an Alternate g++ Installation

We recommend using the version of g++ that is shipped with ModelSim on its various supported platforms. However, if you want to use your own installation, you can do so by setting the CppPath variable in the modelsim.ini file to the g++ executable location. For example, if your g++ executable is installed in /u/abc/gcc-3.2/bin, then you would set the variable as follows:
CppPath /u/abc/gcc-3.2/bin/g++

Maintaining Portability Between OSCI and the Simulator

If you intend to simulate on both ModelSim and the OSCI reference simulator, you can use the MTI_SYSTEMC macro to execute the ModelSim specific code in your design only when running ModelSim. Sccom defines this macro by default during compile time. Using the original and modified code shown in the example shown in Example 7-1, you might write the code as follows:
#ifdef MTI_SYSTEMC //If using the ModelSim simulator, sccom compiles this SC_MODULE(mytop) { sc_signal<bool> mysig; mymod mod; SC_CTOR(mytop) : mysig("mysig"), mod("mod") { mod.outp(mysig); } };

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SystemC Simulation Compiling SystemC Files SC_MODULE_EXPORT(top); #else //Otherwise, it compiles this int sc_main(int argc, char* argv[]) { sc_signal<bool> mysig; mymod mod("mod"); mod.outp(mysig); sc_start(100, SC_NS); } #endif

Restrictions on Compiling with HP aCC

ModelSim uses the aCC -AA option by default when compiling C++ files on HP-UX. It does this so cout will function correctly in the systemc.so file. The -AA option tells aCC to use ANSI-compliant <iostream> rather than cfront-style <iostream.h>. Thus, all C++-based objects in a program must be compiled with -AA. This means you must use <iostream> and "using" clauses in your code. Also, you cannot use the -AP option, which is incompatible with -AA.

Switching Platforms and Compilation

Compiled SystemC libraries are platform dependent. If you move between platforms, you must remove all SystemC files from the working library and then recompile your SystemC source files. To remove SystemC files from the working directory, use the vdel command with the -allsystemc argument. If you attempt to load a design that was compiled on a different platform, an error such as the following occurs:
# vsim work.test_ringbuf # Loading work/systemc.so # ** Error: (vsim-3197) Load of "work/systemc.so" failed: work/systemc.so: ELF file data encoding not little-endian. # ** Error: (vsim-3676) Could not load shared library work/systemc.so for SystemC module 'test_ringbuf'. # Error loading design

You can type verror 3197 at the vsim command prompt and get details about what caused the error and how to fix it.

Using sccom in Addition to the Raw C++ Compiler

When compiling complex C/C++ testbench environments, it is common to compile code with many separate runs of the compiler. Often users compile code into archives (.a files), and then link the archives at the last minute using the -L and -l link options.

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When using ModelSim's SystemC, you may wish to compile a portion of your C design using raw g++ or aCC instead of sccom. Perhaps you have some legacy code or some non-SystemC utility code that you want to avoid compiling with sccom. You can do this, however, some caveats and rules apply.

Rules for sccom Use

The rules governing when and how you must use sccom are as follows: 1. You must compile all code that references SystemC types or objects using sccom. 2. When using sccom, you should not use the -I compiler option to point the compiler at any search directories containing OSCI or any other vendor supplied SystemC header files. sccom does this for you accurately and automatically. 3. If you do use the raw C++ compiler to compile C/C++ functionality into archives or shared objects, you must then link your design using the -L and -l options with the sccom -link command. These options effectively pull the non-SystemC C/C++ code into a simulation image that is used at runtime. Failure to follow the above rules can result in link-time or elaboration-time errors due to mismatches between the OSCI or any other vendor supplied SystemC header files and the ModelSim SystemC header files.

Rules for Using Raw g++ to Compile Non-SystemC C/C++ Code

If you use raw g++ to compile your non-systemC C/C++ code, the following rules apply: 1. The -fPIC option to g++ should be used during compilation with sccom. 2. For C++ code, you must use the built-in g++ delivered with ModelSim, or (if using a custom g++) use the one you built and specified with the CppPath variable in the modelsim.ini file. Otherwise binary incompatibilities may arise between code compiled by sccom and code compiled by raw g++.

Rules for Using Raw HP aCC to Compile Non-SystemC C/C++ Code

If you use HPs aCC compiler to compile your non-systemC C/C++ code, the following rules apply: 1. For C++ code, you should use the +Z and -AA options during compilation 2. You must use HP aCC version 3.45 or higher.

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Issues with C++ Templates

Templatized SystemC Modules
Templatized SystemC modules are not supported for use at: the top level of the design the boundary between SystemC and higher level HDL modules (i.e. the top level of the SystemC branch)

To convert a top level templatized SystemC module, you can either specialize the module to remove the template, or you can create a wrapper module that you can use as the top module. For example, lets say you have a templatized SystemC module as shown below:
template <class T> class top : public sc_module { sc_signal<T> sig1; ... };

You can specialize the module by setting T = int, thereby removing the template, as follows:
class top : public sc_module { sc_signal<int> sig 1; ... };

Or, alternatively, you could write a wrapper to be used over the template module:
class modelsim_top : public sc_module { top<int> actual_top; ... }; SC_MODULE_EXPORT(modelsim_top);

Organizing Templatized Code

Suppose you have a class template, and it contains a certain number of member functions. All those member functions must be visible to the compiler when it compiles any instance of the class. For class templates, the C++ compiler generates code for each unique instance of the class template. Unless it can see the full implementation of the class template, it cannot generate code for it thus leaving the invisible parts as undefined. Since it is legal to have undefined symbols in a .so, sccom -link will not produce any errors or warnings. To make functions visible to the compiler, you must move them to the .h file.

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Linking the Compiled Source

Once the design has been compiled, it must be linked using the sccom command with the -link argument. The sccom -link command collects the object files created in the different design libraries, and uses them to build a shared library (.so) in the current work library or the library specified by the -work option. If you have changed your SystemC source code and recompiled it using sccom, then you must relink the design by running sccom -link before invoking vsim. Otherwise, your changes to the code are not recognized by the simulator. Remember that any dependent .a or .o files should be listed on the sccom -link command line before the .a or .o on which it depends. For more details on dependencies and other syntax issues, see sccom.

Simulating SystemC Designs

After compiling the SystemC source code, you can simulate your design with vsim.

Loading the Design

For SystemC, invoke vsim with the top-level module of the design. This example invokes vsim on a design named top:
vsim top

When the GUI comes up, you can expand the hierarchy of the design to view the SystemC modules. SystemC objects are denoted by green icons (see Design Object Icons and Their Meaning for more information). Figure 7-1. SystemC Objects in GUI

To simulate from a command shell, without the GUI, invoke vsim with the -c option:
vsim -c <top_level_module>

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Running Simulation
Run the simulation using the run command or select one of the Simulate > Run options from the menu bar.

SystemC Time Unit and Simulator Resolution

This section applies to SystemC only simulations. For simulations of mixed-language designs, the rules for how ModelSim interprets the resolution vary. See Simulator Resolution Limit for details on mixed-language simulations. Two related yet distinct concepts are involved with determining the simulation resolution: the SystemC time unit and the simulator resolution. The following table describes the concepts, lists the default values, and defines the methods for setting/overriding the values. Table 7-6. Time Unit and Simulator Resolution Description Set by default as .ini file Default Override default by value ScTimeUnit .ini file variable or sc_set_default_time_unit() function before an sc_clock or sc_time statement.

SystemC time unit

ScTimeUnit 1ns The unit of time used in your SystemC source code. You need to set this in cases where your SystemC default time unit is at odds with any other, non-SystemC segments of your design. 1ns

Resolution Simulator The smallest unit of resolution time measured by the simulator. If your delays get truncated, set the resolution smaller; this value must be less than or equal to the UserTimeUnit

-t argument to vsim (This overrides all other resolution settings.) or sc_set_time_resolution() function or GUI: Simulate > Start Simulation > Resolution

Available settings for both time unit and resolution are: 1x, 10x, or 100x of fs, ps, ns, us, ms, or sec. You can view the current simulator resolution by invoking the report command with the simulator state option.

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Choosing Your Simulator Resolution

You should choose the coarsest simulator resolution limit possible that does not result in undesired rounding of your delays. However, the time precision should also not be set unnecessarily small, because in some cases performance will be degraded. When deciding what to set the simulators resolution to, you must keep in mind the relationship between the simulators resolution and the SystemC time units specified in the source code. For example, with a time unit usage of:
sc_wait(10, SC_PS);

a simulator resolution of 10ps would be fine. No rounding off of the ones digits in the time units would occur. However, a specification of:
sc_wait(9, SC_PS);

would require you to set the resolution limit to 1ps in order to avoid inaccuracies caused by rounding.

Initialization and Cleanup of SystemC State-Based Code

State-based code should not be used in Constructors and Destructors. Constructors and Destructors should be reserved for creating and destroying SystemC design objects, such as sc_modules or sc_signals. State-based code should also not be used in the elaboration phase callbacks before_end_of_elaboration() and end_of_elaboration(). The following virtual functions should be used to initialize and clean up state-based code, such as logfiles or the VCD trace functionality of SystemC. They are virtual methods of the following classes: sc_port_base, sc_module, sc_channel, and sc_prim_channel. You can think of them as phase callback routines in the SystemC language: before_end_of_elaboration () Called after all constructors are called, but before port binding. end_of_elaboration () Called at the end of elaboration after port binding. This function is available in the SystemC 2.1 reference simulator. start_of_simulation () Called before simulation starts. Simulation-specific initialization code can be placed in this function. end_of_simulation () Called before ending the current simulation session.

The call sequence for these functions with respect to the SystemC object construction and destruction is as follows: 1. Constructors 2. before_end_of_elaboration ()

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3. end_of_elaboration () 4. start_of_simulation () 5. end_of_simulation () 6. Destructors

Usage of Callbacks
The start_of_simulation() callback is used to initialize any state-based code. The corresponding cleanup code should be placed in the end_of_simulation() callback. These callbacks are only called during simulation by vsim and thus, are safe.

Debugging the Design

You can debug SystemC designs using all of ModelSims debugging features, with the exception of the Dataflow window. You must have compiled the design using the sccom -g argument in order to debug the SystemC objects in your design.

Viewable SystemC Types

Types (<type>) of the objects which may be viewed for debugging are the following: Types bool, sc_bit sc_logic sc_bv<width> sc_lv<width> sc_int<width> sc_uint<width> sc_fix sc_fix_fast sc_fixed<W,I,Q,O,N> sc_fixed_fast<W,I,Q,O,N> sc_ufix sc_ufix_fast sc_ufixed sc_ufixed_fast sc_signed sc_unsigned char, unsigned char int, unsigned int short, unsigned short long, unsigned long sc_bigint<width> sc_biguint<width> sc_ufixed<W,I,Q,O,N> short, unsigned short long long, unsigned long long float double enum pointer array class struct union

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Types Used as Elements of C/C++ Composite Type

SystemC types used as elements in C/C++ composite types - such as array, struct, class, and union - are not debuggable.

Viewable SystemC Objects

Objects which may be viewed in SystemC for debugging purposes are as shown in the following table. Table 7-7. Viewable SystemC Objects Channels sc_clock (a hierarchical channel) sc_event sc_export sc_mutex sc_fifo<type> sc_signal<type> sc_signal_rv<width> sc_signal_resolved tlm_fifo<type> Ports Variables Module member variables of all C++ and SystemC built-in types (listed in the Types list below) are supported. Aggregates Aggregates of SystemC signals or ports. Only three types of aggregates are supported for debug: struct class array sc_in<type> sc_out<type> sc_inout<type> sc_in_rv<width> sc_out_rv<width> sc_inout_rv<width> sc_in_resolved sc_out_resolved sc_inout_resolved sc_in_clk sc_out_clk User defined channels sc_inout_clk sc_fifo_in derived from sc_fifo_out sc_prim_channel User defined ports derived from sc_port<> which is : connected to a built-in channel connected to a user-defined channel derived from an sc_prim_channel1
1. You must use a special macro to make these ports viewable for debugging. For details See MTI_SC_PORT_ENABLE_DEBUG.

MTI_SC_PORT_ENABLE_DEBUG
A user-defined port which is not connected to a built-in primitive channel is not viewable for debugging by default. You can make the port viewable if the actual channel connected to the port is a channel derived from an sc_prim_channel. If it is, you can add the macro

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MTI_SC_PORT_ENABLE_DEBUG to the channel class public declaration area, as shown in this example:
class my_channel: public sc_prim_channel { ... public: MTI_SC_PORT_ENABLE_DEBUG };

Waveform Compare with SystemC

Waveform compare supports the viewing of SystemC signals and variables. You can compare SystemC objects to SystemC, Verilog or VHDL objects. For pure SystemC compares, you can compare any two signals that match type and size exactly; for C/C++ types and some SystemC types, sign is ignored for compares. Thus, you can compare char to unsigned char or sc_signed to sc_unsigned. All SystemC fixed-point types may be mixed as long as the total number of bits and the number of integer bits match. Mixed-language compares are supported as listed in the following table: Table 7-8. Mixed-language Compares C/C++ types bool, char, unsigned char short, unsigned short int, unsigned int long, unsigned long sc_bit, sc_bv, sc_logic, sc_lv sc_int, sc_uint sc_bigint, sc_biguint sc_signed, sc_unsigned net, reg bit, bit_vector, boolean, std_logic, std_logic_vector

SystemC types

Verilog types VHDL types

The number of elements must match for vectors; specific indexes are ignored.

Debugging Source-Level Code

In order to debug your SystemC source code, you must compile the design for debug using the -g C++ compiler option. You can add this option directly to the sccom command line on a per run basis, with a command such as:
sccom mytop -g

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Or, if you plan to use it every time you run the compiler, you can specify it in the modelsim.ini file with the CppOptions variable. See SystemC Compiler Control Variables for more information. The source code debugger, C Debug, is automatically invoked when the design is compiled for debug in this way. You can set breakpoints in a Source window, and single-step through your SystemC/C++ source code. Figure 7-2. Breakpoint in SystemC Source

The gdb debugger has a known bug that makes it impossible to set breakpoints reliably in constructors or destructors. Try to avoid setting breakpoints in constructors of SystemC objects; it may crash the debugger. You can view and expand SystemC objects in the Objects pane and processes in the Active Processes pane. Figure 7-3. SystemC Objects and Processes in GUI

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SystemC Object and Type Display

This section contains information on how ModelSim displays certain objects and types, as they may differ from other simulators.

Support for Globals and Statics

Globals and statics are supported for ModelSim debugging purposes, however some additional naming conventions must be followed to make them viewable.

Naming Requirement
In order to make a global viewable for debugging purposes, the name given must match the declared signal name. An example:
sc_signal<bool> clock("clock");

For statics to be viewable, the name given must be fully qualified, with the module name and declared name, as follows:
<module_name>::<declared_name>

For example, the static data member "count" is viewable in the following code excerpt:
SC_MODULE(top) { static sc_signal<floag> count; //static data member .... } sc_signal<float> top::count("top::count"); //static named in quotes

Viewing Global and Static Signals

ModelSim translates C++ scopes into a hierarchical arrangement. Since globals and statics exist at a level above ModelSims scope, ModelSim must add a top level, sc_root, to all global and static signals. Thus, to view these static or global signals in ModelSim, you need to add sc_root to the hierarchical name for the signal. In the case of the above examples, the debugging statements for examining "top/count" (a static) and "clock" (a global) would be:
VSIM> examine /sc_root/top/count VSIM> examine /sc_root/clock

Support for Aggregates

ModelSim supports aggregates of SystemC signals or ports. Three types of aggregates are supported: structures, classes, and arrays. Unions are not supported for debug. An aggregate of signals or ports will be shown as a signal of aggregate type. For example, an aggregate such as:

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SystemC Simulation SystemC Object and Type Display sc_signal <sc_logic> a[3];

is equivalent to:
sc_signal <sc_lv<3>> a;

for debug purposes. ModelSim shows one signal - object "a" - in both cases. The following aggregate
sc_signal <float> fbus [6];

when viewed in the Wave window, would appear shown in Figure 7-4. Figure 7-4. Aggregates in Wave Window

Viewing FIFOs
In ModelSim, the values contained in an sc_fifo appear in a definite order. The top-most or leftmost value is always the next to be read from the FIFO. Elements of the FIFO that are not in use are not displayed. Example of a signal where the FIFO has five elements:
# examine f_char # {} VSIM 4> # run 10 VSIM 6> # examine f_char # A VSIM 8> # run 10 VSIM 10> # examine f_char # {A B} VSIM 12> # run 10

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SystemC Simulation SystemC Object and Type Display VSIM # {A VSIM VSIM # {A VSIM VSIM # {A VSIM VSIM # {B VSIM VSIM # {C VSIM VSIM # {D 14> # examine B C} 16> # run 10 18> # examine B C D} 20> # run 10 22> # examine B C D E} 24> # run 10 26> # examine C D E} 28> # run 10 30> # examine D E} 32> # run 10 34> # examine E} f_char

f_char

f_char

f_char

f_char

f_char

Viewing SystemC Memories

The ModelSim tool detects and displays SystemC memories. A memory is defined as any member variable of a SystemC module which is defined as an array of the following type: unsigned char unsigned short unsigned int unsigned long unsigned long long char short int float double enum

Properly Recognizing Derived Module Class Pointers

If you declare a pointer as a base class pointer, but actually assign a derived class object to it, then ModelSim still treats it as a base class pointer, instead of the derived class pointer, as you intended. As such, it would be unavailable for debug. To make it available for debug, you must use the mti_set_typename member function to instruct that it should be treated as a derived class pointer.

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For instance, consider the following example:

class base_mod : public sc_module { sc_signal<int> base_sig; int base_var; ... }; class d1_mod : public base_mod { sc_signal<int> d1_sig; int d1_var; ... }; class d2_mod : public base_mod { sc_signal<int> d2_sig; int d2_var; ... }; SC_MODULE(top) { base_mod* inst; SC_CTOR(top) { if (some_condition) inst = new d1_mod("d1_inst"); else inst = new d2_mod("d2_inst"); } };

The sccom compiler can only see the declarative region of a module. Hence, in the above example, it thinks "inst" is a pointer to the "base_mod" module. After elaboration, the vsim GUI only shows "base_sig" and "base_var" in the objects window for the instance "inst". Depending on which derived module is actually created, you really would like to see all the variables and signals of that derived class. Because we did not associate the proper derived class type with the instance "inst", the signals and variables of the derived class do exist in the kernel, however, they are not debuggable. To correctly associate the derived class type with the instance inst, you can use a member function called mti_set_typename and apply it to the modules. You pass the actual derived class name to the function when an instance is constructed. For example,

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SystemC Simulation SystemC Object and Type Display SC_MODULE(top) { base_mod* inst; SC_CTOR(top) { if (some_condition) { inst = new d1_mod("d1_inst"); inst->mti_set_typename("d1_mod"); } else { inst = new d2_mod("d2_inst"); inst->mti_set_typename("d2_mod"); } } };

In the above case, the class names happen to be simple names, which may not be true if the type is a class template with lots of template parameters. You can look up the name in <work>/moduleinfo.sc file, if you are unsure of the exact names.

Custom Debugging of SystemC Channels and Variables

ModelSim provides a custom interface to give users an easier way to debug SystemC variables of a user-defined type, built-in channels of a user defined type, built-in ports of a user defined type, and user defined channels and ports. This custom interface provides a string based debug solution for simulation objects that are considered to be undebuggable by the SystemC compiler sccom. It can be also used for objects that may be supported for debug natively by the simulator, but whose native debug view is too cumbersome.

Supported SystemC Objects

The custom debug interface provides debug support for the following SystemC objects (T is a user defined type, or a user-defined channel or port):
T sc_signal<T> sc_fifo<T> tlm_fifo<T> sc_in<T> sc_out<T> sc_inout<T>

Registration and Callback Functions

To provide custom debug for any object, you need to register a callback function one for each instance of that object with the simulator. The simulator then calls the callback

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function, with the appropriate arguments, when it needs the latest value of the object. The registration function can be called from the phase callback function before_end_of_elaboration(), or anytime before this function during the elaboration phase of the simulator. During registration, you must specify the maximum length of the string buffer to be reserved for an object instance. The callback function is then passed a pre-allocated string of a length specified during registration. The callback function must write the value of the object in the that string, and it must be null terminated (\0). The ModelSim tool takes the string returned by the callback function, as-is, and displays it in the objects window, wave window, and CLI commands (such as examine). The describe command on custom debug objects simply reports that the object is a custom debug object of the specified length. The macro used to register an object for debugging is SC_MTI_REGISTER_CUSTOM_DEBUG. Occasionally, the ModelSim tool fails to register the object because it considers the object to be undebuggable. In such cases, an error message is issued to that effect. If this occurs, use the SC_MTI_REGISTER_NAMED_CUSTOM_DEBUG to both name and register the object for debugging.

Syntax
typedef void (*mtiCustomDebugCB)(void* obj, char* value, char format_char); void SC_MTI_REGISTER_CUSTOM_DEBUG (void* obj, size_t value_len, mtiCustomDebugCB cb_func); void SC_MTI_REGISTER_NAMED_CUSTOM_DEBUG (void* obj, size_t value_len, mtiCustomDebugCB cb_func, const char* name);

The registration macro SC_MTI_REGISTER_CUSTOM_DEBUG requires three arguments: the handle to the object being debugged value_len the maximum length of the debug string to be reserved for this object cb_func the callback function that will be called by the simulator to get the latest value of the object being debugged

The SC_MTI_REGISTER_NAMED_CUSTOM_DEBUG requires an additional argument: the name of the object

The callback function also must have three arguments: 1. A handle to the object being debugged 2. A pointer to the string value buffer in which the callback must write the string value of the object begin debugged

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3. format_char the expected format of the value: ascii (a), binary (b), decimal (d), hex (h), or octal (o) The callback function does not return anything.

Example 7-4. Using the Custom Interface on Different Objects For the purposes of illustration, let us consider an arbitrary user-defined type T as follows:
class myclass { private: int x; int y; public: void get_string_value(char format_str, char* mti_value); size_t get_value_length(); ... };

Variable of type T would be:

void mti_myclass_debug_cb(void* var, char* mti_value, char format_str) { myclass* real_var = RCAST<myclass*>var; real_var.get_string_value(format_str, mti_value); } SC_MODULE(test) { myclass var1; myclass* var2; SC_CTOR(test) { SC_MTI_REGISTER_CUSTOM_DEBUG( &var1, var1.get_value_length(), mti_myclass_debug_cb); SC_MTI_REGISTER_CUSTOM_DEBUG( var2, var2->get_value_length(), mti_myclass_debug_cb); } };

sc_signal, sc_fifo and tlm_fifo of type T and Associated Ports would be:
void mti_myclass_debug_cb(void* var, char* mti_value, char format_str)

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SystemC Simulation SystemC Object and Type Display { myclass* real_var = RCAST<myclass*>var; real_var.get_string_value(format_str, mti_value); } SC_MODULE(test) { sc_signal<myclass> sig1; sc_signal<myclass> *sig2; sc_fifo<myclass> fifo; SC_CTOR(test) { myclass temp; SC_MTI_REGISTER_CUSTOM_DEBUG( &sig1, temp.get_value_length(), mti_myclass_debug_cb); SC_MTI_REGISTER_CUSTOM_DEBUG( sig2, temp.get_value_length(), mti_myclass_debug_cb); SC_MTI_REGISTER_CUSTOM_DEBUG( &fifo, temp.get_value_length(), mti_myclass_debug_cb); } };

As shown in Example 7-4, although the callback function is registered on a sc_signal<T> or a sc_fifo<T> object, the callback is called on the T object, instead of the channel itself. We call the callback on T because sc_signal<T> has two sets of values, current and new value and sc_fifo can have more than one element in the fifo. The callback is called on each element of the fifo that is valid at any given time. For an sc_signal<T> the callback is called only on the current value, not the new value. By registering the primitive channel sc_signal<T> for custom debug, any standard port connected to it (sc_in<T>, sc_out<T>, sc_inout<T>, sc_fifo_in<T>, etc.) automatically is available for custom debug. It is illegal to register any built-in ports for custom debug separately.

User Defined Primitive Channels and Ports

The callback and registration mechanism for a user defined channel derived from sc_prim_channel are no different than a variable of an user-defined type. Please see the section on variables of type T in Example 7-4 for more details on the registration and callback mechanism for such objects. You have two choices available to you for making user defined ports debuggable:

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Automatic debug of any port connected to a primitive channel Any port that is connected to a channel derived from sc_prim_channel is automatically debuggable only if the connected channel is debuggable either natively or using custom debug. To enable this automatic debugging capability, use the following macro in the channel class:
MTI_SC_PORT_ENABLE_DEBUG

In this case, you may not separately register the port for custom debug. Specific port registration Register the port separately for custom debug. To do this, simply register the specific port, without using the macro. The callback and registration mechanism is the same as a variable of type T.

Hierarchical Channels/Ports Connected to Hierarchical Channels

Hierarchical channels are basically modules, and appear in the structure pane in ModelSim. Since they are part of the design hierarchy, custom debug cannot be supported for hierarchical channels. Ports connected to hierarchical channels, however, though not supported for debug natively in ModelSim, are supported for debug with the custom interface. Any port object registered for custom debug is treated as a variable of a user defined type. Please see Example 7-4, variables of type T, for more details on the registration and callback mechanism for such objects.

Any Other Channels and Ports Connected to Such Channels

It is legal in SystemC to create a channel that implements an interface and is not derived either from sc_channel or sc_prim_channel. Take the following, for example:
class mychannel : public myinterface {} class myport : public sc_port<myinterface> {}

Channels and ports of this category are supported for debug natively in ModelSim. ModelSim treats them as variables of type T. These channels and ports can be registered for custom debug. The registration and callback mechanism is the same as for a variable of type T, as shown in Example 7-4 above.

Differences Between the Simulator and OSCI

ModelSim is based upon the 2.1 reference simulator provided by OSCI. However, there are some minor but key differences to understand:

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vsim calls sc_initialize() by default at the end of elaboration. The user has to explicitly call sc_initialize() in the reference simulator. You should remove calls to sc_initialize() from your code. The default time resolution of the reference simulator is 1ps. For vsim it is 1ns. The user can set the time resolution by using the vsim command with the -t option or by modifying the value of the Resolution variable in the modelsim.ini file. The run command in ModelSim is equivalent to sc_start(). In the reference simulator, sc_start() runs the simulation for the duration of time specified by its argument. In ModelSim the run command runs the simulation for the amount of time specified by its argument. The sc_cycle(), sc_start(), and sc_main() functions are not supported in ModelSim. The default name for sc_object() is bound to the actual C object name. However, this name binding only occurs after all sc_object constructors are executed. As a result, any name() function call placed inside a constructor will not pick up the actual C object name. This feature is not available on HP platforms.

Fixed-Point Types
Contrary to OSCI, ModelSim compiles the SystemC kernel with support for fixed-point types. If you want to compile your own SystemC code to enable that support, youll need to define the compile time macro SC_INCLUDE_FX. You can do this in one of two ways: enter the g++/aCC argument -DSC_INCLUDE_FX on the sccom command line, such as:
sccom -DSC_INCLUDE_FX top.cpp

add a define statement to the C++ source code before the inclusion of the systemc.h, as shown below:
#define SC_INCLUDE_FX #include "systemc.h"

Support for cin

The ModelSim simulator has a limited support for the C++ standard input cin. To enable support for cin, the design source files must be compiled with -DUSE_MTI_CIN sccom option. For example:
sccom -DUSE_MTI_CIN top.cpp

Limitations ModelSim does not support cin when it is passed as a function parameter of type istream. This is true for both C++ functions and member functions of a user-defined class/struct.

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For example, the following cin usage is not supported:

void getInput(istream& is) { int input_data; ... is >> input_data; .... } getinput(cin);

A workaround for this case, the source code needs to be modified as shown below:
void getinput() { int input_data; ... cin >> input_data; .... } getinput();

OSCI 2.1 Feature Implementation Details

Support for OSCI TLM Library
ModelSim includes the header files and examples from the OSCI SystemC TLM (Transaction Level Modeling) Library Standard version 1.0. The TLM library can be used with simulation, and requires no extra switches or files. TLM objects are not debuggable, with the exception of tlm_fifo. Examples and documentation are located in install_dir/examples/systemc/tlm. The TLM header files (tlm_*.h) are located in include/systemc.

Phase Callback
The following functions are supported for phase callbacks: before_end_of_elaboration() start_of_simulation() end_of_simulation()

For more information regarding the use of these functions, see Initialization and Cleanup of SystemC State-Based Code.

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Accessing Command-Line Arguments

The following global functions allow you to gain access to command-line arguments: sc_argc() Returns the number of arguments specified on the vsim command line with the -sc_arg argument. This function can be invoked from anywhere within SystemC code. sc_argv() Returns the arguments specified on the vsim command line with the -sc_arg argument. This function can be invoked from anywhere within SystemC code.

Example: When vsim is invoked with the following command line:

vsim -sc_arg "-a" -c -sc_arg "-b -c" -t ns -sc_arg -d

sc_argc() and sc_argv() will behave as follows:

int argc; const char * const * argv; argc = sc_argc(); argv = sc_argv();

The number of arguments (argc) is now 4.

argv[0] argv[1] argv[2] argv[3] is is is is "vsim" "-a" "-b -c" "-d"

sc_stop Behavior
When encountered during the simulation run in batch mode, sc_stop() stops the current simulation and exits the tool. In GUI mode, a dialog box appears asking you for confirmation before exiting the tool. This is the default operation of sc_stop(). If you want to change the default behavior of sc_stop, you can change the setting of the OnFinish variable in the modelsim.ini file. To change the behavior interactively, use the -onfinish argument to thevsim command.

Construction Parameters for SystemC Types

The material contained in this section applies only to SystemC signals, ports, variables or fifos using one of the following fixed-point types: sc_signed, sc_unsigned, sc_fix, sc_fix_fast, sc_ufix, sc_ufix_fast. These are the only SystemC types that have construction time parameters. If you require values other than the default parameters, you need to read this section. The default size for these types is 32.

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If you are using one of these types in a SystemC signal, port, fifo or an aggregate of one of these (e.g. array of sc_signal), you can not pass the size parameters to the type. This is a limitation imposed by the C++ language. Instead, SystemC provides a global default size (32) that you can control. For sc_signed and sc_unsigned, you need to use the two objects, sc_length_param and sc_length_context, and you need to use them in an unusual way. If you just want the default vector length, simply do this:
SC_MODULE(dut) { sc_signal<sc_signed> s1; sc_signal<sc_signed> s2; SC_CTOR(dut) : s1("s1"), s2("s2") { } }

For a single setting like using five-bit vectors, your module and its constructor would be something like:
SC_MODULE(dut) { sc_length_param l; sc_length_context c; sc_signal<sc_signed> s1; sc_signal<sc_signed> s2; SC_CTOR(dut) : l(5), c(l), s1("s1"), s2("s2") { } }

Notice that the constructor initialization list sets up the length parameter first, assigns the length parameter to the context object, and then constructs the two signals. You DO pass the name to the signal constructor, but the name is passed to the signal object, not to the underlying type. There is no way to reach the underlying type directly. Instead, the default constructors for sc_signed and sc_unsigned reach out to the global area and get the currently defined length parameter, the one you just set. If you need to have signals or ports with different vector sizes, you need to include a pair of parameter and context objects for each different size:
SC_MODULE(dut) { sc_length_param l1; sc_length_context c1; sc_signal<sc_signed> s1; sc_signal<sc_signed> s2; sc_length_param l2; sc_length_context c2; sc_signal<sc_signed> u1; sc_signal<sc_signed> u2;

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SystemC Simulation Troubleshooting SystemC Errors SC_CTOR(dut) : l1(5), c1(l1), s1("s1"), s2("s2"), l2(8), c2(l2), u1("u1"), u2("u2") { } }

With simple variables of this type, you reuse the context object. However, you must have the extra parameter and context objects when you are using them in a constructor-initialization list because the compiler does not allow repeated an item in that list. The four fixed-point types that use construction parameters work exactly the same way, except that they use the objects sc_fxnum_context and sc_fxnum_params to do the work. Also, their are more parameters you can set for fixed-point numbers. Assuming we just want to set the length of the number and the number of fractional bits, heres the example above modified for fixed point numbers:
SC_MODULE(dut) { sc_fxnum_params p1; sc_fxnum_contxt c1; sc_signal<sc_fix> s1; sc_signal<sc_fix> s2; sc_fxnum_params p2; sc_fxnum_contxt c2; sc_signal<sc_ufix> u1; sc_signal<sc_ufix> u2; SC_CTOR(dut) : p1(5,0), c1(p1), s1("s1"), s2("s2"), p2(8,5), c2(p2), u1("u1"), u2("u2") { } }

Troubleshooting SystemC Errors

In the process of modifying your SystemC design to run on ModelSim, you may encounter several common errors. This section highlights some actions you can take to correct such errors.

Unexplained Behaviors During Loading or Runtime

If your SystemC simulation behaves in otherwise unexplainable ways, you should determine whether you need to adjust the stack space ModelSim allocates for threads in your design. The required size for a stack depends on the depth of functions on that stack and the number of bytes they require for automatic (local) variables. By default the SystemC stack size is 10,000 bytes per thread. You may have one or more threads needing a larger stack size. If so, call the SystemC function set_stack_size() and adjust the stack to accommodate your needs. Note that you can ask for too much stack space and have unexplained behavior as well.
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Errors During Loading

When simulating your SystemC design, you might get a "failed to load sc lib" message because of an undefined symbol, looking something like this:
# Loading /home/cmg/newport2_systemc/chip/vhdl/work/systemc.so # ** Error: (vsim-3197) Load of "/home/cmg/newport2_systemc/chip/vhdl/work/systemc.so" failed: ld.so.1: /home/icds_nut/modelsim/5.8a/sunos5/vsimk: fatal: relocation error: file /home/cmg/newport2_systemc/chip/vhdl/work/systemc.so: symbol _Z28host_respond_to_vhdl_requestPm: referenced symbol not found. # ** Error: (vsim-3676) Could not load shared library /home/cmg/newport2_systemc/chip/vhdl/work/systemc.so for SystemC module 'host_xtor'.

Source of Undefined Symbol Message

The causes for such an error could be: missing definition missing type using SystemC 2.1 header files from other vendors bad link order specified in sccom -link multiply-defined symbols

Missing Definition
If the undefined symbol is a C function in your code or a library you are linking with, be sure that you declared it as an extern "C" function:
extern "C" void myFunc();

This should appear in any header files include in your C++ sources compiled by sccom. It tells the compiler to expect a regular C function; otherwise the compiler decorates the name for C++ and then the symbol can't be found. Also, be sure that you actually linked with an object file that fully defines the symbol. You can use the "nm" utility on Unix platforms to test your SystemC object files and any libraries you link with your SystemC sources. For example, assume you ran the following commands:
sccom test.cpp sccom -link libSupport.a

If there is an unresolved symbol and it is not defined in your sources, it should be correctly defined in any linked libraries:
nm libSupport.a | grep "mySymbol"

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Missing Type
When you get errors during design elaboration, be sure that all the items in your SystemC design hierarchy, including parent elements, are declared in the declarative region of a module. If not, sccom ignores them. For example, we have a design containing SystemC over VHDL. The following declaration of a child module "test" inside the constructor module of the code is not allowed and will produce an error:
SC_MODULE(Export) { SC_CTOR(Export) { test *testInst; testInst = new test("test"); } };

The error results from the fact that the SystemC parse operation will not see any of the children of "test". Nor will any debug information be attached to it. Thus, the signal has no type information and can not be bound to the VHDL port. The solution is to move the element declaration into the declarative region of the module.

Using SystemC 2.1 Header Files Supplied by Other Vendors

SystemC 2.1 includes version control for SystemC header files. If you compile your SystemC design using a SystemC 2.1 header file that was distributed by other vendors, and then you run sccom -link to link the design, an error similar to the following may result upon loading the design:
** Error: (vsim-3197) Load of "work/systemc.so" failed: work/systemc.so: undefined symbol: _ZN20sc_api_version_2_1_0C1Ev.

To resolve the error, recompile the design using sccom. Make sure any include paths read by sccom do not point to a SystemC 2.1 installation. By default, sccom automatically picks up the ModelSim SystemC header files.

Misplaced -link Option

The order in which you place the -link option within the sccom -link command is critical. There is a big difference between the following two commands:
sccom -link liblocal.a

and
sccom liblocal.a -link

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The first command ensures that your SystemC object files are seen by the linker before the library "liblocal.a" and the second command ensures that "liblocal.a" is seen first. Some linkers can look for undefined symbols in libraries that follow the undefined reference while others can look both ways. For more information on command syntax and dependencies, see sccom.

Multiple Symbol Definitions

The most common type of error found during sccom -link operation is the multiple symbol definition error. The error message looks something like this:
work/sc/gensrc/test_ringbuf.o: In function `test_ringbuf::clock_generator(void)': work/sc/gensrc/test_ringbuf.o(.text+0x4): multiple definition of `test_ringbuf::clock_generator(void)' work/sc/test_ringbuf.o(.text+0x4): first defined here

This error arises when the same global symbol is present in more than one .o file. There are two common causes of this problem: A stale .o file in the working directory with conflicting symbol names. In this first case, just remove the stale files with the following command:
vdel -lib <lib_path> -allsystemc

Incorrect definition of symbols in header files.

In the second case, if you have an out-of-line function (one that isnt preceded by the "inline" keyword) or a variable defined (i.e. not just referenced or prototyped, but truly defined) in a .h file, you can't include that .h file in more than one .cpp file. Text in .h files is included into .cpp files by the C++ preprocessor. By the time the compiler sees the text, it's just as if you had typed the entire text from the .h file into the .cpp file. So a .h file included into two .cpp files results in lots of duplicate text being processed by the C++ compiler when it starts up. Include guards are a common technique to avoid duplicate text problems. If an .h file has an out-of-line function defined, and that .h file is included into two .c files, then the out-of-line function symbol will be defined in the two corresponding. o files. This leads to a multiple symbol definition error during sccom -link. To solve this problem, add the "inline" keyword to give the function "internal linkage". This makes the function internal to the .o file, and prevents the function's symbol from colliding with a symbol in another .o file. For free functions or variables, you could modify the function definition by adding the "static" keyword instead of "inline", although "inline" is better for efficiency. Sometimes compilers do not honor the "inline" keyword. In such cases, you should move your function(s) from a header file into an out-of-line implementation in a .cpp file.

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SystemC Procedural Interface to SystemVerilog

SystemC designs can communicate with SystemVerilog through a procedural interface, the SystemVerilog Direct Programming Interface (DPI). In contrast to a hierarchical interface, where communication is advanced through signals and ports, DPI communications consists of task and function calls passing data as arguments. This type of interface can be useful in transaction level modeling, in which bus functional models are widely used. This section describes the use flow for using the SystemVerilog DPI to call SystemVerilog export functions from SystemC, and to call SystemC import functions from SystemVerilog. The SystemVerilog LRM describes the details of a DPI C import and export interface. This document describes how to extend the same interface to include SystemC and C++ in general. The import and export keywords used in this document are in accordance with SystemVerilog as described in the SV LRM. An export function or task is defined in SystemVerilog, and is called by C or SystemC. An import task or function is defined in SystemC or C, and is called from SystemVerilog.

Definition of Terms
This section defines the terms used in this section: C++ import function A C++ import function is defined as a free floating C++ function, either in the global or some private namespace. A C++ import function must not have any SystemC types as formal arguments. This function must be made available in the SystemC shared library. SystemC Import Function A SystemC import function must be available in the SystemC shared library, and can be either of the following: A free floating C++ function, either in the global or private namespace, with formal arguments of SystemC types. A SystemC module member function, with or without formal arguments of SystemC types.

Export Function A SystemVerilog export function, as defined in the SystemVerilog LRM.

Use Flow
The use flow of SystemC DPI depends on the function modes, whether they are import or export. The import and export calls described in the following sections can be mixed with each other in any order.
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SystemC Import Functions

In order to make a SystemC import function callable from SystemVerilog, it needs to be registered from the SystemC code before it can be called from SystemVerilog. This can be thought of as exporting the function outside SystemC, thus making it callable from other languages. The registration must be done by passing a pointer to the function using an API. The registration can be done anywhere in the design but it must be done before the call happens in SystemVerilog, otherwise the call fails with undefined behavior.

Global Functions
A global function can be registered using the API below:
int sc_dpi_register_cpp_function(const char* function_name, PTFN func_ptr);

This function takes two arguments: the name of the function, which can be different than the actual function name. This name must match the SystemVerilog import declaration. No two function registered using this API can have the same name: it creates an error if they do. a function pointer to the registered function. On successful registration, this function will return a 0. A non-zero return status means an error. Example 7-5. Global Import Function Registration
int scGlobalImport(sc_logic a, sc_lv<9>* b); sc_dpi_register_cpp_function(scGlobalImport, scGlobalImport);

A macro like the one shown below is provided to make the registration even more simple. In this case the ASCII name of the function will be identical to the name of the function in the source code.
SC_DPI_REGISTER_CPP_FUNCTION(scGlobalImport);

In the SystemVerilog code, the import function needs to be defined with a special marker ("DPI-SC") that tells the SV compiler that this is an import function defined in the SystemC shared library. The syntax for calling the import function remains the same as described in the SystemVerilog LRM. Example 7-6. SystemVerilog Global Import Declaration For the SystemC import function shown in Example 7-5, the SystemVerilog import declaration is as follows:
import mti_scdpi::*; import "DPI-SC" context function int scGlobalImport( input sc_logic a, output sc_lv[8:0] b);

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Please refer to Module Member Functions and Calling SystemVerilog Export Tasks / Functions from SystemC for more details on the SystemC import and export task or function declaration syntax.

Module Member Functions

Registering Functions
Module member functions can be registered anytime before they are called from the SystemVerilog code. The following macro can be used to register a non-static member function if the registration is done from a module constructor or a module member function. For a static member function, the registration is accomplished using the interface SC_DPI_REGISTER_CPP_FUNCTION, as described in SystemC Import Functions.
SC_DPI_REGISTER_CPP_MEMBER_FUNCTION(<function_name>, <func_ptr>); Example: SC_MODULE(top) { void sc_func() { } SC_CTOR(top) { SC_DPI_REGISTER_CPP_MEMBER_FUNCTION(sc_func, &top::sc_func); } };

Note that in the above case, since the registration is done from the module constructor, the module pointer argument might be redundant. However, the module pointer argument will be required if the macro is used outside a constructor. To register a member function from a function that is not a member of the module, the following registration function must be used:
int sc_dpi_register_cpp_member_function(<function_name>, <module_ptr>, <func_ptr>);

This function takes three arguments. The first argument is the name of the function, which can be different than the actual function name. This is the name that must be used in the SystemVerilog import declaration. The second argument is a reference to the module instance where the function is defined. It is illegal to pass a reference to a class other than a class derived from sc_module and will lead to undefined behavior. The third and final argument is a function pointer to the member function being registered. On successful registration, this function will return a 0. A non-zero return status means an error. For example, the member function run() of the module "top" in the example above can be registered as follows:
sc_module* pTop = new top("top"); sc_dpi_register_cpp_member_function("run", pTop, &top::run);

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Setting Stack Size for Import Tasks

The tool implicitly creates a SystemC thread to execute the C++ functions declared as SystemVerilog import tasks. The default stack size is 64KBytes and may not be big enough for any C++ functions. To change the default stack size, you can use the interface sc_dpi_set_stack_size. You must use this interface right after the registration routine, for example:
SC_MODULE(top) { void sc_task() { } SC_CTOR(top) { SC_DPI_REGISTER_CPP_MEMBER_FUNCTION("sc_task", &top::sc_task); sc_dpi_set_stack_size(1000000); // set stack size to be 1Mbyte. } }

For the C++ functions declared as SystemVerilog import functions, you do not need to set the stack size.

Declaring and Calling Member Import Functions in SystemVerilog

The declaration for a member import function in SystemVerilog is similar to the following:
import "DPI-SC" context function int scMemberImport( input sc_logic a, output sc_lv[8:0] b);

Registration of static member functions is identical to the registration of global functions using the API sc_dpi_register_cpp_function(). Only one copy of the overloaded member functions is supported as a DPI import, as DPI can only identify the import function by its name. not by the function parameters. To enable the registration of member functions, the SystemC source file must be compiled with the -DMTI_BIND_SC_MEMBER_FUNCTION macro.

Calling Member Import Functions in a Specific SystemC Scope

A member import function can be registered for multiple module instances, as in the case when registration routine SC_DPI_REGISTER_CPP_MEMBER_FUNCTION() is called from inside a SystemC module constructor. At runtime, you must specify the proper scope when the member import function call is initiated from SystemVerilog side. You can use the following two routines to manipulate the SystemC scope before making the member import function call:
function string scSetScopeByName(input string sc_scope_name);

and
function string scGetScopeName();

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scSetScopeByName() expects the full hierarchical name of a valid SystemC scope as the input. The hierarchical name must use the Verilog-style path separator. The previous scope hierarchical name before setting the new scope will be returned. scGetScopeName() returns the current SystemC scope for next member import function call. Since both routines are predefined in ModelSim built-in package mti_scdpi, you need to import this package into the proper scope where the two routines are used, using the following statement:
import mti_scdpi::*;

Example 7-7. Usage of scSetScopeByName and scGetScopeName

//test.cpp: SC_MODULE(scmod) { void cppImportFn(); SC_CTOR(scmod) { ........ SC_DPI_REGISTER_CPP_MEMBER_FUNCTION("cppImportFn", &scmod::cppImportFn); ...... } }; //test.sv: module top(); import mti_scdpi::*; are defined. string prev_sc_scope; string curr_sc_scope; scmod inst1(); scmod inst2(); //scope name "top.inst1" //scope name "top.inst2" // where scSetScopeByName() and scGetScopeName()

import "DPI-SC" function void cppImportFn(); // call DPI-SC import function under scope "top.inst1" prev_sc_scope = scSetScopeByName("top.inst1"); curr_sc_scope = scGetScopeName(); cppImportFn(); // call DPI-SC import function under scope "top.inst2" prev_sc_scope = scSetScopeByName("top.inst2"); curr_sc_scope = scGetScopeName();

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SystemC Simulation SystemC Procedural Interface to SystemVerilog cppImportFn(); endmodule

Calling SystemVerilog Export Tasks / Functions from SystemC

Unless an export call is made from an import function, you must set the scope of the export function explicitly to provide the SystemVerilog context information to the simulator. You do this by calling svSetScope() before each export function or task call. An export function to be called with SystemC arguments must have an export declaration, similar to the following:
export "DPI-SC" context function Export;

The function declaration must use the SystemC type package, similar to the following:
import mti_scdpi::*; function int Export(input sc_logic a, output sc_bit b);

The syntax for calling an export function from SystemC is the same as any other C++ function call.

SystemC Data Type Support in SystemVerilog DPI

The SystemVerilog package scdpi must be imported if a SystemC data type is used in the arguments of import and export functions.
import mti_scdpi::*

The SystemC data type names have been treated as special keywords. Avoid using these keywords for other purposes in your SystemVerilog source files. The table below shows how each of the SystemC type will be represented in SystemVerilog. This table must be followed strictly for passing arguments of SystemC type. The SystemVerilog

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typedef statements, listed in the middle column of Table 7-9, are automatically imported whenever the mti_scdpi package is imported. Table 7-9. SystemC Types as Represented in SystemVerilog SystemC Type sc_logic sc_bit sc_bv<N> sc_lv<N> sc_int<N> sc_uint<N> sc_bigint<N> sc_biguint<N> sc_fixed<W,I,Q,O,N> sc_ufixed<W,I,Q,O,N> sc_fixed_fast<W...> sc_ufixed_fast<W...> sc_signed sc_unsigned sc_fix sc_ufix sc_fix_fast sc_ufix_fast SV Typedef typedef logic sc_logic typedef bit sc_bit typedef bit sc_bv typedef logic sc_lv typedef bit sc_int typedef bit sc_uint typedef bit sc_bigint typedef bit sc_biguint typedef bit sc_fixed typedef bit sc_ufixed typedef bit sc_fixed_fast typedef bit sc_ufixed_fast typedef bit sc_signed typedef bit sc_unsigned typedef bit sc_fix typedef bit sc_ufix typedef bit sc_fix_fast typedef bit sc_ufix_fast Import/Export Declaration sc_logic sc_bit sc_bit[N-1:0] sc_lv[N-1:0] sc_int[N-1:0] sc_uint[N-1:0] sc_bigint[N-1:0] sc_biguint[N-1:0] sc_fixed[I-1:I-W] sc_ufixed[I-1:I-W] sc_fixed[I-1:I-W] sc_fixed[I-1:I-W] sc_signed[N-1:0] sc_unsigned[N-1:0] sc_fix[I-1:1-W] sc_ufix[I-1:1-W] sc_fix_fast[I-1:1-W] sc_ufix_fast[I-1:1-W]

According to the table above, a SystemC argument of type sc_uint<32> will be declared as sc_uint[31:0] in SystemVerilog DPI-SC declaration. Similarly, sc_lv<9> would be sc_lv[8:0]. to enable the fixed point datatypes, the SystemC source file must be compiled with -DSC_INCLUDE_FX. For fixed-point types the left and right indexes of the SV vector can lead to a negative number. For example, sc_fixed<3,0> will translate to sc_fixed[0-1:0-3] which is sc_fixed[-1:-3]. This representation is used for fixed-point numbers in the ModelSim tool, and must be strictly followed. For the SystemC types whose size is determined during elaboration, such as sc_signed and sc_unsigned, a parameterized array must be used on the SV side. The array size parameter value, on the SystemVerilog side, must match correctly with the constructor arguments passed to types such as sc_signed and sc_unsigned at SystemC elaboration time. Some examples: An export declaration with arguments of SystemC type:
export "DPI-SC" context function Export; import mti_scdpi::*;

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SystemC Simulation SystemC Procedural Interface to SystemVerilog function int Export(input sc_logic a, input sc_int[8:0] b);

An import function with arguments of SystemC type:

import mti_scdpi::*; import "DPI-SC" context function int scGlobalImport( input sc_logic a, output sc_lv[8:0] b);

An export function with arguments of regular C types:

export "DPI-SC" context function Export; function int Export(input int a, output int b);

SystemC Function Prototype Header File (sc_dpiheader.h)

The sc_dpiheader.h file contains the C function prototype statements consistent with the DPI-SC import/export function/task declaration. It is generated by vlog automatically, when compiling Verilog source files. You can use this file as a sanity check for the SystemC function arguments and return type declaration in your source files.

SystemC DPI Usage Example

---------------------------------------hello.v:

module top; hello c_hello(); import "DPI-SC" context function void sc_func(); export "DPI-SC" task verilog_task; task verilog_task(); $display("hello from verilog_task."); endtask initial begin sc_func(); #2000 $finish; end endmodule

---------------------------------------hello.cpp:

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SystemC Simulation SystemC Procedural Interface to SystemVerilog #include "systemc.h" #include "sc_dpiheader.h" SC_MODULE(hello) { void call_verilog_task(); void sc_func(); SC_CTOR(hello) { SC_THREAD(call_verilog_task); SC_DPI_REGISTER_CPP_MEMBER_FUNCTION("sc_func", &hello::sc_func); } ~hello() {}; }; void hello::sc_func() { printf("hello from sc_func(). } void hello::call_verilog_task() { svSetScope(svGetScopeFromName("top")); for(int i = 0; i < 3; ++i) { verilog_task(); } } SC_MODULE_EXPORT(hello);

---------------------------------------Compilation:

vlog -sv hello.v sccom -DMTI_BIND_SC_MEMBER_FUNCTION hello.cpp sccom -link vsim -c -do "run -all; quit -f" top

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Chapter 8 Mixed-Language Simulation

ModelSim single-kernel simulation allows you to simulate designs that are written in VHDL, Verilog, SystemVerilog, and SystemC. The boundaries between languages are enforced at the level of a design unit. This means that although a design unit itself must be entirely of one language type, it may instantiate design units from another language. Any instance in the design hierarchy may be a design unit from another language without restriction.

Basic Mixed-Language Flow

Simulating mixed-language designs with ModelSim includes these general steps: 1. Compile HDL source code using vcom or vlog. Compile SystemC C++ source code using sccom. Compile all modules in the design following order-of-compile rules. For SystemC designs with HDL instances Create a SystemC foreign module declaration for all Verilog and VHDL instances (see SystemC Foreign Module (Verilog) Declaration or SystemC Foreign Module (VHDL) Declaration). For Verilog/VHDL designs with SystemC instances Export any SystemC instances that will be directly instantiated by Verilog/VHDL using the SC_MODULE_EXPORT macro. Exported SystemC modules can be instantiated just as you would instantiate any Verilog/VHDL module or design unit.

2. For designs containing SystemC Link all objects in the design using sccom -link. 3. Simulate the design with the vsim command. 4. Run and debug your design.

Separate Compilers with Common Design Libraries

VHDL source code is compiled by vcom and the resulting compiled design units (entities, architectures, configurations, and packages) are stored in the working library. Likewise, Verilog source code is compiled by vlog and the resulting design units (modules and UDPs) are stored in the working library. SystemC/C++ source code is compiled with the sccom command. The resulting object code is compiled into the working library.

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Design libraries can store any combination of design units from any of the supported languages, provided the design unit names do not overlap (VHDL design unit names are changed to lower case). See Design Libraries for more information about library management.

Access Limitations in Mixed-Language Designs

The Verilog language allows hierarchical access to objects throughout the design. This is not the case with VHDL or SystemC. You cannot directly read or change a VHDL or SystemC object (signal, variable, generic, etc.) with a hierarchical reference within a mixed-language design. Furthermore, you cannot directly access a Verilog object up or down the hierarchy if there is an interceding VHDL or SystemC block. You have two options for accessing VHDL objects or Verilog objects "obstructed" by an interceding block: 1) propagate the value through the ports of all design units in the hierarchy; 2) use the Signal Spy procedures or system tasks (see Signal Spy for details). To access obstructed SystemC objects, propagate the value through the ports of all design units in the hierarchy or use the control/observe functions. The following two member functions of sc_signal may be used to control and observe hierarchical signals in a design: control_foreign_signal() observe_foreign_signal()

For more information on the use of control and observe, see Hierarchical References In Mixed HDL/SystemC Designs.

Simulator Resolution Limit

In a mixed-language design with only one top, the resolution of the top design unit is applied to the whole design. If the root of the mixed design is VHDL, then VHDL simulator resolution rules are used (see Simulator Resolution Limit (VHDL) for VHDL details). If the root of the mixed design is Verilog, Verilog rules are used (see Simulator Resolution Limit (Verilog) for Verilog details). If the root is SystemC, then SystemC rules are used (see SystemC Time Unit and Simulator Resolution for SystemC details). In the case of a mixed-language design with multiple tops, the following algorithm is used: If VHDL or SystemC modules are present, then the Verilog resolution is ignored. An error is issued if the Verilog resolution is finer than the chosen one. If both VHDL and SystemC are present, then the resolution is chosen based on which design unit is elaborated first. For example: vsim sc_top vhdl_top -do vsim.do In this case, the SystemC resolution (default 1 ns) is chosen.

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vsim vhdl_top sc_top -do vsim.do In this case, the VHDL resolution is chosen. All resolutions specified in the source files are ignored if vsim is invoked with the -t option. When set, this overrides all other resolutions.

Runtime Modeling Semantics

The ModelSim simulator is compliant with all pertinent Language Reference Manuals. To achieve this compliance, the sequence of operations in one simulation iteration (i.e. delta cycle) is as follows: SystemC processes are run Signal updates are made HDL processes are run

The above scheduling semantics are required to satisfy both the SystemC and the HDL LRM. Namely, all processes triggered by an event in a SystemC primitive channel shall wake up at the beginning of the following delta. All processes triggered by an event on an HDL signal shall wake up at the end of the current delta. For a signal chain that crosses the language boundary, this means that processes on the SystemC side get woken up one delta later than processes on the HDL side. Consequently, one delta of skew will be introduced between such processes. However, if the processes are communicating with each other, correct system behavior will still result.

Hierarchical References In Mixed HDL/SystemC Designs

A SystemC signal (including sc_signal, sc_buffer, sc_signal_resolved, and sc_signal_rv) can control or observe an HDL signal using two member functions of sc_signal:
bool control_foreign_signal(const char* name); bool observe_foreign_signal(const char* name);

The argument (const char* name) is a full hierarchical path to an HDL signal or port. The return value is "true" if the HDL signal is found and its type is compatible with the SystemC signal type. See tables for Verilog Data Type Mapping to Verilog and VHDL Data Type Mapping to VHDL to view a list of types supported at the mixed language boundary. If it is a supported boundary type, it is supported for hierarchical references. If the function is called during elaboration time, when the HDL signal has not yet elaborated, the function always returns "true"; however, an error is issued before simulation starts.

Control
When a SystemC signal calls control_foreign_signal() on an HDL signal, the HDL signal is considered a fanout of the SystemC signal. This means that every value change of the SystemC
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signal is propagated to the HDL signal. If there is a pre-existing driver on the HDL signal which has been controlled, the value is changed to reflect the SystemC signals value. This value remains in effect until a subsequent driver transaction occurs on the HDL signal, following the semantics of the force -deposit command.

Observe
When a SystemC signal calls observe_foreign_signal() on an HDL signal, the SystemC signal is considered a fanout of the HDL signal. This means that every value change of the HDL signal is propagated to the SystemC signal. If there is a pre-existing driver on the SystemC signal which has been observed, the value is changed to reflect the HDL signals value. This value remains in effect until a subsequent driver transaction occurs on the SystemC signal, following the semantics of the force -deposit command. Once a SystemC signal executes a control or observe on an HDL signal, the effect stays throughout the whole simulation. Any subsequent control/observe on that signal will be an error. Example:
SC_MODULE(test_ringbuf) { sc_signal<bool> observe_sig; sc_signal<sc_lv<4> > control_sig; // HDL module instance ringbuf* ring_INST; SC_CTOR(test_ringbuf) { ring_INST = new ringbuf("ring_INST", "ringbuf"); ..... observe_sig.observe_foreign_signal("/test_ringbuf/ring_INST/block1_INST/b uffers(0)"); control_sig.control_foreign_signal("/test_ringbuf/ring_INST/block1_INST/s ig"); } };

Mapping Data Types

Cross-language (HDL) instantiation does not require any extra effort on your part. As ModelSim loads a design it detects cross-language instantiations made possible because a design unit's language type can be determined as it is loaded from a library and the necessary adaptations and data type conversions are performed automatically. SystemC and HDL crosslanguage instantiation requires minor modification of SystemC source code (addition of SC_MODULE_EXPORT, sc_foreign_module, etc.).

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A VHDL instantiation of Verilog may associate VHDL signals and values with Verilog ports and parameters. Likewise, a Verilog instantiation of VHDL may associate Verilog nets and values with VHDL ports and generics. The same holds true for SystemC and VHDL/Verilog ports. ModelSim automatically maps between the language data types as shown in the sections below.

Verilog to VHDL Mappings

Verilog Parameters
The type of a Verilog parameter is determined by its initial value. Verilog type integer real string VHDL type integer real string

Verilog Ports
The allowed VHDL types for ports connected to Verilog nets and for signals connected to Verilog ports are: Allowed VHDL types bit bit_vector std_logic std_logic_vector vl_logic vl_logic_vector The vl_logic type is an enumeration that defines the full state set for Verilog nets, including ambiguous strengths. The bit and std_logic types are convenient for most applications, but the vl_logic type is provided in case you need access to the full Verilog state set. For example, you may wish to convert between vl_logic and your own user-defined type. The vl_logic type is defined in the vl_types package in the pre-compiled verilog library. This library is provided in the installation directory along with the other pre-compiled libraries (std and ieee). The source code for the vl_types package can be found in the files installed with ModelSim. (See <install_dir>/modeltech/vhdl_src/verilog/vltypes.vhd.)

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Verilog States
Verilog states are mapped to std_logic and bit as follows: Verilog HiZ Sm0 Sm1 SmX Me0 Me1 MeX We0 We1 WeX La0 La1 LaX std_logic 'Z' 'L' 'H' 'W' 'L' 'H' 'W' 'L' 'H' 'W' 'L' 'H' 'W' bit '0' '0' '1' '0' '0' '1' '0' '0' '1' '0' '0' '1' '0' Verilog Pu0 Pu1 PuX St0 St1 StX Su0 Su1 SuX std_logic 'L' 'H' 'W' '0' '1' 'X' '0' '1' 'X' bit '0' '1' '0' '0' '1' '0' '0' '1' '0'

For Verilog states with ambiguous strength: bit receives '0' std_logic receives 'X' if either the 0 or 1 strength component is greater than or equal to strong strength std_logic receives 'W' if both the 0 and 1 strength components are less than strong strength

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VHDL To Verilog Mappings

VHDL Generics
VHDL type integer real time physical enumeration string Verilog type integer or real integer or real integer or real integer or real integer or real string literal

When a scalar type receives a real value, the real is converted to an integer by truncating the decimal portion. Type time is treated specially: the Verilog number is converted to a time value according to the timescale directive of the module. Physical and enumeration types receive a value that corresponds to the position number indicated by the Verilog number. In VHDL this is equivalent to T'VAL(P), where T is the type, VAL is the predefined function attribute that returns a value given a position number, and P is the position number. VHDL type bit is mapped to Verilog states as follows: bit '0' '1' Verilog St0 St1

VHDL type std_logic is mapped to Verilog states as follows: std_logic 'U' 'X' '0' '1' 'Z' 'W' 'L' Verilog StX StX St0 St1 HiZ PuX Pu0
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std_logic 'H' ''

Verilog Pu1 StX

Verilog And SystemC Signal Interaction And Mappings

SystemC has a more complex signal-level interconnect scheme than Verilog. Design units are interconnected via hierarchical and primitive channels. An sc_signal<> is one type of primitive channel. The following section discusses how various SystemC channel types map to Verilog wires when connected to each other across the language boundary.

Channel and Port Type Mapping

The following port type mapping table lists all channels. Three types of primitive channels and one hierarchical channel are supported on the language boundary (SystemC modules connected to Verilog modules). Channels sc_signal<T> sc_signal_rv<W> Ports sc_in<T> sc_out<T>sc_inout<T> sc_in_rv<W> sc_out_rv<W> sc_inout_rv<W> sc_in_resolved sc_out_resolved sc_inout_resolved sc_in_clk sc_out_clk sc_inout_clk N/A sc_fifo_in sc_fifo_out N/A N/A user-defined Verilog mapping Depends on type T. See table entitled Data Type Mapping to Verilog. wire [W-1:0]

sc_signal_resolved

wire [W-1:0]

sc_clock

wire

sc_mutex sc_fifo sc_semaphore sc_buffer user-defined

Not supported on language boundary Not supported on language boundary Not supported on language boundary Not supported on language boundary Not supported on language boundary1

1. User defined SystemC channels and ports derived from built-in SystemC primitive channels and ports can be connected to HDL signals. The built-in SystemC primitive channel or port must be already supported at the mixed-language boundary for the derived class connection to work.

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A SystemC sc_out port connected to an HDL signal higher up in the design hierarchy is treated as a pure output port. A read() operation on such an sc_out port might give incorrect values. Use an sc_inout port to do both read() and write() operations.

Data Type Mapping to Verilog

SystemCs sc_signal<> types are mapped to Verilog types as follows: SystemC bool, sc_bit sc_logic sc_bv<W> sc_lv<W> sc_int<W>, sc_uint<W> sc_bigint<W>, sc_biguint<W> sc_fixed<W,I,Q,O,N>, sc_ufixed<W,I,Q,O,N> sc_fixed_fast<W,I,Q,O,N>, sc_ufixed_fast<W,I,Q,O,N>
1sc_fix, 1sc_ufix 1sc_fix_fast, 1sc_ufix_fast 2sc_signed, 2sc_unsigned

Verilog wire wire wire [W-1:0] wire [W-1:0] wire [W-1:0] wire [W-1:0] wire [W-1:0] wire [W-1:0] wire [WL-1:0] wire [WL-1:0] wire[WL-1:0] wire [7:0] wire [15:0] wire [31:0] wire [31:0] wire [63:0] wire [31:0] wire [63:0] Not supported on language boundary Not supported on language boundary

char, unsigned char short, unsigned short int, unsigned int long, unsigned long long long, unsigned long long float double enum pointers

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SystemC class struct union bit_fields

Verilog Not supported on language boundary Not supported on language boundary Not supported on language boundary Not supported on language boundary

1. WL (word length) is the total number of bits used in the type. It is specified during runtime. To make a port of type sc_fix, sc_ufix, sc_fix_fast, or sc_ufix_fast of word length other than the default(32), you must use sc_fxtype_params and sc_fxtype_context to set the word length. For more information, see Construction Parameters for SystemC Types. 2. To make a port of type sc_signed or sc_unsigned of word length other than the default (32), you must use sc_length_param and sc_length_context to set the word length. For more information, see Construction Parameters for SystemC Types.

Port Direction
Verilog port directions are mapped to SystemC as follows: Verilog input output inout SystemC sc_in<T>, sc_in_resolved, sc_in_rv<W> sc_out<T>, sc_out_resolved, sc_out_rv<W> sc_inout<T>, sc_inout_resolved, sc_inout_rv<W>

Verilog to SystemC State Mappings

Verilog states are mapped to sc_logic, sc_bit, and bool as follows: Verilog HiZ Sm0 Sm1 SmX Me0 Me1 MeX We0 We1 WeX
258

sc_logic 'Z' '0' '1' 'X' '0' '1' 'X' '0' '1' 'X'

sc_bit '0' '0' '1' '0' '0' '1' '0' '0' '1' '0'

bool false false true false false true false false true false
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Verilog La0 La1 LaX Pu0 Pu1 PuX St0 St1 StX Su0 Su1 SuX

sc_logic '0' '1' 'X' '0' '1' 'X' '0' '1' 'X' '0' '1' 'X'

sc_bit '0' '1' '0' '0' '1' '0' '0' '1' '0' '0' '1' '0'

bool false true false false true false false true false false true false

For Verilog states with ambiguous strength: sc_bit receives '1' if the value component is 1, else it receives 0 bool receives true if the value component is 1, else it receives false sc_logic receives 'X' if the value component is X, H, or L sc_logic receives '0' if the value component is 0 sc_logic receives 1 if the value component is 1

SystemC to Verilog State Mappings

SystemC type bool is mapped to Verilog states as follows: bool false true Verilog St0 St1

SystemC type sc_bit is mapped to Verilog states as follows: sc_bit '0' '1' Verilog St0 St1

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SystemC type sc_logic is mapped to Verilog states as follows: sc_logic '0' '1' 'Z' 'X' Verilog St0 St1 HiZ StX

VHDL and SystemC Signal Interaction And Mappings

SystemC has a more complex signal-level interconnect scheme than VHDL. Design units are interconnected via hierarchical and primitive channels. An sc_signal<> is one type of primitive channel. The following section discusses how various SystemC channel types map to VHDL types when connected to each other across the language boundary.

Port Type Mapping

The following port type mapping table lists all channels. Three types of primitive channels and one hierarchical channel are supported on the language boundary (SystemC modules connected to VHDL modules). Channels sc_signal<T> Ports sc_in<T> sc_out<T> sc_inout<T> sc_in_rv<W> sc_out_rv<W> sc_inout_rv<W> sc_in_resolved sc_out_resolved sc_inout_resolved sc_in_clk sc_out_clk sc_inout_clk N/A sc_fifo_in sc_fifo_out N/A VHDL mapping Depends on type T. See table entitled Data Type Mapping to VHDL. std_logic_vector(W-1 downto 0) std_logic

sc_signal_rv<W>

sc_signal_resolved

sc_clock

bit/std_logic/boolean

sc_mutex sc_fifo sc_semaphore

Not supported on language boundary Not supported on language boundary Not supported on language boundary

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Channels sc_buffer user-defined

Ports N/A user-defined

VHDL mapping Not supported on language boundary Not supported on language boundary1

1. User defined SystemC channels and ports derived from built-in SystemC primitive channels and ports can be connected to HDL signals. The built-in SystemC primitive channel or port must be already supported at the mixed-language boundary for the derived class connection to work.

A SystemC sc_out port connected to an HDL signal higher up in the design hierarchy is treated as a pure output port. A read() operation on such an sc_out port might give incorrect values. Use an sc_inout port to do both read() and write() operations.

Data Type Mapping to VHDL

SystemCs sc_signal types are mapped to VHDL types as follows SystemC bool, sc_bit sc_logic sc_bv<W> sc_lv<W> sc_bv<32>, sc_lv<32> sc_bv<64>, sc_lv<64> sc_int<W>, sc_uint<W> sc_bigint<W>, sc_biguint<W> sc_fixed<W,I,Q,O,N>, sc_ufixed<W,I,Q,O,N> sc_fixed_fast<W,I,Q,O,N>, sc_ufixed_fast<W,I,Q,O,N >
1 sc_fix, 1

VHDL bit/std_logic/boolean std_logic bit_vector(W-1 downto 0) std_logic_vector(W-1 downto 0) integer real bit_vector(W-1 downto 0) std_logic_vector(W -1 downto 0) bit_vector(W-1 downto 0) std_logic_vector(W-1 downto 0) bit_vector(W-1 downto 0) std_logic_vector(W-1 downto 0) bit_vector(W-1 downto 0) std_logic_vector(W-1 downto 0) bit_vector(WL-1 downto 0) std_logic_vector(WL- 1 downto 0) bit_vector(WL-1 downto 0) std_logic_vector(WL- 1 downto 0)

sc_ufix sc_ufix_fast

1 sc_fix_fast, 1

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SystemC
2 sc_signed, 2

VHDL bit_vector(WL-1 downto 0) std_logic_vector(WL- 1 downto 0) bit_vector(7 downto 0) std_logic_vector(7 downto 0) bit_vector(15 downto 0) std_logic_vector(15 downto 0) bit_vector(31 downto 0) std_logic_vector(7 downto 0) bit_vector(31 downto 0) std_logic_vector(31 downto 0) bit_vector(63 downto 0) std_logic_vector(63 downto 0) bit_vector(31 downto 0) std_logic_vector(31 downto 0) bit_vector(63 downto 0) std_logic_vector(63 downto 0) real Not supported on language boundary Not supported on language boundary Not supported on language boundary Not supported on language boundary Not supported on language boundary Not supported on language boundary

sc_unsigned

char, unsigned char short, unsigned short int, unsigned int long, unsigned long long long, unsigned long long float double

enum pointers class structure union bit_fields

1. WL (word length) is the total number of bits used in the type. It is specified during runtime. To make a port of type sc_fix, sc_ufix, sc_fix_fast, or sc_ufix_fast of word length other than the default(32), you must use sc_fxtype_params and sc_fxtype_context to set the word length. For more information, see Construction Parameters for SystemC Types. 2. To make a port of type sc_signed or sc_unsigned of word length other than the default (32), you must use sc_length_param and sc_length_context to set the word length. For more information, see Construction Parameters for SystemC Types.

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Port Direction Mapping

VHDL port directions are mapped to SystemC as follows: VHDL in out inout buffer SystemC sc_in<T>, sc_in_resolved, sc_in_rv<W> sc_out<T>, sc_out_resolved, sc_out_rv<W> sc_inout<T>, sc_inout_resolved, sc_inout_rv<W> sc_out<T>, sc_out_resolved, sc_out_rv<W>

VHDL to SystemC State Mapping

VHDL states are mapped to sc_logic, sc_bit, and bool as follows: std_logic 'U' 'X' '0' '1' 'Z' 'W' 'L' 'H' '-' sc_logic 'X' 'X' '0' '1' 'Z' 'X' '0' '1' 'X' sc_bit '0' '0' '0' '1' '0' '0' '0' '1' '0' bool false false false true false false false true false

SystemC to VHDL State Mapping

SystemC type bool is mapped to VHDL boolean as follows: bool false true VHDL false true

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SystemC type sc_bit is mapped to VHDL bit as follows: sc_bit '0' '1' VHDL '0' '1'

SystemC type sc_logic is mapped to VHDL std_logic states as follows: sc_logic '0' '1' 'Z' 'X' std_logic '0' '1' 'Z' 'X'

VHDL Instantiating Verilog

Once you have generated a component declaration for a Verilog module, you can instantiate the component just like any other VHDL component. You can reference a Verilog module in the entity aspect of a component configuration all you need to do is specify a module name instead of an entity name. You can also specify an optional secondary name for an optimized sub-module. Further, you can reference a Verilog configuration in the configuration aspect of a VHDL component configuration - just specify a Verilog configuration name instead of a VHDL configuration name.

Verilog Instantiation Criteria Within VHDL

A Verilog design unit may be instantiated within VHDL if it meets the following criteria: The design unit is a module or configuration. UDPs are not allowed. The ports are named ports (see Modules with Unnamed Ports). The ports are not connected to bidirectional pass switches (it is not possible to handle pass switches in VHDL).

Component Declaration for VHDL Instantiating Verilog

A Verilog module that is compiled into a library can be referenced from a VHDL design as though the module is a VHDL entity. Likewise, a Verilog configuration can be referenced as though it were a VHDL configuration.

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The interface to the module can be extracted from the library in the form of a component declaration by running vgencomp. Given a library and module name, vgencomp writes a component declaration to standard output. The default component port types are: std_logic std_logic_vector

Optionally, you can choose: bit and bit_vector vl_logic and vl_logic_vector

VHDL and Verilog Identifiers

The VHDL identifiers for the component name, port names, and generic names are the same as the Verilog identifiers for the module name, port names, and parameter names. Except for the cases noted below, ModelSim leaves the Verilog identifier alone when it generates the entity. ModelSim converts Verilog identifiers to VHDL 1076-1993 extended identifiers in three cases: The Verilog identifier is not a valid VHDL 1076-1987 identifier. You compile the Verilog module with the -93 argument. One exception is a valid, lowercase identifier (e.g., topmod). Valid, lowercase identifiers will not be converted even if you compile with -93. The Verilog identifier is not unique when case is ignored. For example, if you have TopMod and topmod in the same module, ModelSim will convert the former to \TopMod\).

vgencomp Component Declaration when VHDL Instantiates Verilog

vgencomp generates a component declaration according to these rules: Generic Clause A generic clause is generated if the module has parameters. A corresponding generic is defined for each parameter that has an initial value that does not depend on any other parameters.

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The generic type is determined by the parameter's initial value as follows: Parameter value integer real string literal Generic type integer real string

The default value of the generic is the same as the parameter's initial value. For example: Verilog parameter parameter p1 = 1 - 3; parameter p2 = 3.0; parameter p3 = "Hello"; Port Clause A port clause is generated if the module has ports. A corresponding VHDL port is defined for each named Verilog port. You can set the VHDL port type to bit, std_logic, or vl_logic. If the Verilog port has a range, then the VHDL port type is bit_vector, std_logic_vector, or vl_logic_vector. If the range does not depend on parameters, then the vector type will be constrained accordingly, otherwise it will be unconstrained. For example: Verilog port input p1; output [7:0] p2; output [4:7] p3; inout [W-1:0] p4; VHDL port p1 : in std_logic; p2 : out std_logic_vector(7 downto 0); p3 : out std_logic_vector(4 to 7); p4 : inout std_logic_vector; VHDL generic p1 : integer := -2; p2 : real := 3.000000; p3 : string := "Hello";

Configuration declarations are allowed to reference Verilog modules in the entity aspects of component configurations. However, the configuration declaration cannot extend into a Verilog instance to configure the instantiations within the Verilog module.

Modules with Unnamed Ports

Verilog allows modules to have unnamed ports, whereas VHDL requires that all ports have names. If any of the Verilog ports are unnamed, then all are considered to be unnamed, and it is not possible to create a matching VHDL component. In such cases, the module may not be instantiated from VHDL. Unnamed ports occur when the module port list contains bit-selects, part-selects, or concatenations, as in the following example:

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Mixed-Language Simulation Verilog Instantiating VHDL module m(a[3:0], b[1], b[0], {c,d}); input [3:0] a; input [1:0] b; input c, d; endmodule

Note that a[3:0] is considered to be unnamed even though it is a full part-select. A common mistake is to include the vector bounds in the port list, which has the undesired side effect of making the ports unnamed (which prevents the user from connecting by name even in an allVerilog design). Most modules having unnamed ports can be easily rewritten to explicitly name the ports, thus allowing the module to be instantiated from VHDL. Consider the following example:
module m(y[1], y[0], a[1], a[0]); output [1:0] y; input [1:0] a; endmodule

Here is the same module rewritten with explicit port names added:
module m(.y1(y[1]), .y0(y[0]), .a1(a[1]), .a0(a[0])); output [1:0] y; input [1:0] a; endmodule

"Empty" Ports
Verilog modules may have "empty" ports, which are also unnamed, but they are treated differently from other unnamed ports. If the only unnamed ports are "empty", then the other ports may still be connected to by name, as in the following example:
module m(a, , b); input a, b; endmodule

Although this module has an empty port between ports "a" and "b", the named ports in the module can still be connected to from VHDL.

Verilog Instantiating VHDL

You can reference a VHDL entity or configuration from Verilog as though the design unit is a module or a configuration of the same name.

VHDL Instantiation Criteria Within Verilog

A VHDL design unit may be instantiated within Verilog if it meets the following criteria: The design unit is an entity/architecture pair or a configuration.
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The entity ports are of type bit, bit_vector, std_ulogic, std_ulogic_vector, vl_ulogic, vl_ulogic_vector, or their subtypes. The port clause may have any mix of these types. The generics are of type integer, real, time, physical, enumeration, or string. String is the only composite type allowed.

Entity and Architecture Names and Escaped Identifiers

An entity name is not case sensitive in Verilog instantiations. The entity default architecture is selected from the work library unless specified otherwise. Since instantiation bindings are not determined at compile time in Verilog, you must instruct the simulator to search your libraries when loading the design. See Library Usage for more information. Alternatively, you can employ the escaped identifier to provide an extended form of instantiation:
\mylib.entity(arch) u1 (a, b, c); \mylib.entity u1 (a, b, c); \entity(arch) u1 (a, b, c);

If the escaped identifier takes the form of one of the above and is not the name of a design unit in the work library, then the instantiation is broken down as follows: library = mylib design unit = entity architecture = arch

Named Port Associations

Port associations may be named or positional. Use the same port names and port positions that appear in the entity. Named port associations are not case sensitive unless a VHDL port name is an extended identifier (1076-1993). If the VHDL port name is an extended identifier, the association is case sensitive and the VHDL identifiers leading and trailing backslashes are removed before comparison.

Generic Associations
Generic associations are provided via the module instance parameter value list. List the values in the same order that the generics appear in the entity. Parameter assignment to generics is not case sensitive. The defparam statement is not allowed for setting generic values.

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SDF Annotation
A mixed VHDL/Verilog design can also be annotated with SDF. See SDF for Mixed VHDL and Verilog Designs for more information.

SystemC Instantiating Verilog

To instantiate Verilog modules into a SystemC design, you must first create a SystemC Foreign Module (Verilog) Declaration for each Verilog module. Once you have created the foreign module declaration, you can instantiate the foreign module just like any other SystemC module.

Verilog Instantiation Criteria Within SystemC

A Verilog design unit may be instantiated within SystemC if it meets the following criteria: The design unit is a module (UDPs and Verilog primitives are not allowed). The ports are named ports (Verilog allows unnamed ports). The Verilog module name must be a valid C++ identifier. The ports are not connected to bidirectional pass switches (it is not possible to handle pass switches in SystemC).

A Verilog module that is compiled into a library can be instantiated in a SystemC design as though the module were a SystemC module by passing the Verilog module name to the foreign module constructor. For an illustration of this, see Example 8-1.

SystemC and Verilog Identifiers

The SystemC identifiers for the module name and port names are the same as the Verilog identifiers for the module name and port names. Verilog identifiers must be valid C++ identifiers. SystemC and Verilog are both case sensitive.

SystemC Foreign Module (Verilog) Declaration

In cases where you want to run a mixed simulation with SystemC and Verilog, you must generate and declare a foreign module that stands in for each Verilog module instantiated under SystemC. The foreign modules can be created in one of two ways: running scgenmod, a utility that automatically generates your foreign module declaration (much like vgencomp generates a component declaration) modifying your SystemC source code manually

After you have analyzed the design, you can generate a foreign module declaration with an scgenmod similar to the following:

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Mixed-Language Simulation SystemC Instantiating Verilog scgenmod mod1

where mod1 is a Verilog module. A foreign module declaration for the specified module is written to stdout.

Guidelines for Manual Creation in Verilog

Apply the following guidelines to the creation of foreign modules. A foreign module: contains ports corresponding to Verilog ports. These ports must be explicitly named in the foreign modules constructor initializer list. must not contain any internal design elements such as child instances, primitive channels, or processes. must pass a secondary constructor argument denoting the modules HDL name to the sc_foreign_module base class constructor. For Verilog, the HDL name is simply the Verilog module name corresponding to the foreign module, or [<lib>].<module>. parameterized modules are allowed, see Parameter Support for SystemC Instantiating Verilog for details. Example 8-1. SystemC Instantiating Verilog A sample Verilog module to be instantiated in a SystemC design is:
module vcounter (clock, topcount, count); input clock; input topcount; output count; reg count; ... endmodule

The SystemC foreign module declaration for the above Verilog module is:
class counter : public sc_foreign_module { public: sc_in<bool> clock; sc_in<sc_logic> topcount; sc_out<sc_logic> count; counter(sc_module_name nm) : sc_foreign_module(nm, "lib.vcounter"), clock("clock"), topcount("topcount"), count("count") {} };

The Verilog module is then instantiated in the SystemC source as follows:

counter dut("dut");

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where the constructor argument (dut) is the instance name of the Verilog module. Example 8-2. SystemC Instantiating Verilog Another variation of the SystemC foreign module declaration for the same Verilog module might be:
class counter : public sc_foreign_module { public: ... counter(sc_module_name nm, char* hdl_name) : sc_foreign_module(nm, hdl_name), clock("clock"), ... {} };

The instantiation of this module would be:

counter dut("dut", "lib.counter");

Parameter Support for SystemC Instantiating Verilog

Since the SystemC language has no concept of parameters, parameterized values must be passed from a SystemC parent to a Verilog child through the SystemC foreign module (sc_foreign_module). See SystemC Foreign Module (Verilog) Declaration for information regarding the creation of sc_foreign_module.

Passing Parameters to sc_foreign_module (Verilog)

To instantiate a Verilog module containing parameterized values into the SystemC design, you can use one of two methods, depending on whether the parameter is an integer. If the parameter is an integer, you have two choices: passing as a template argument to the foreign module or as a constructor argument to the foreign module. Non-integer parameters must be passed to the foreign module using constructor arguments.

Passing Integer and Non-Integer Parameters as Constructor Arguments

Both integer and non-integer parameters can be passed by specifying two parameters to the sc_foreign_module constructor: the number of parameters (int num_generics), and the parameter list (const char* generic_list). The generic_list is listed as an array of const char*. If you create your foreign module manually (see Guidelines for Manual Creation in Verilog), you must also pass the parameter information to the sc_foreign_module constructor. If you use scgenmod to create the foreign module declaration, the parameter information is detected in the HDL child and is incorporated automatically.

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Example 8-3. Sample Foreign Module Declaration, with Constructor Arguments for Parameters Following Example 8-1, lets see the parameter information that would be passed to the SystemC foreign module declaration:
class counter : public sc_foreign_module { public: sc_in<bool> clk; ... counter(sc_module_name nm, char* hdl_name int num_generics, const char** generic_list) : sc_foreign_module(nm, hdl_name, num_generics, generic_list), {elaborate_foreign_module(hdl_name, num_generics, generic_list);} };

Example 8-4. Passing Parameters as Constructor Arguments Verilog module:

module counter (clk, count) parameter integer_param = 4; parameter real_param = 2.9; parameter str_param = "ERROR"; output [7:0] count; input clk; ... endmodule

Foreign module (created by the command: scgenmod counter):

class counter : public sc_foreign_module { public: sc_in<sc_logic> clk; sc_out<sc_lv<8> > count;

counter(sc_module_name nm, const char* hdl_name int num_generics, const char** generic_list) : sc_foreign_module(nm), clk("clk"), count("count") { elaborate_foreign_module(hdl_name, num_generics, generic_list); } ~counter() {}

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Mixed-Language Simulation SystemC Instantiating Verilog };

Instantiation of the foreign module in SystemC:

SC_MODULE(top) { counter* counter_inst_1; // Instantiate counter with counter_size = 20

SC_CTOR(top) { const char* generic_list[3]; generic_list[0] = strdup("integer_param=16"); generic_list[1] = strdup("real_param=2.6"); generic_list[2] = strdup("str_param=\"Hello\""); //Pass all parameter overrides using foreign module constructor args counter_inst_1 = new counter("c_inst", "work.counter", 3, \ generic_list); // Cleanup the memory allocated for the generic list for (int i = 0; i < 3; i++;) free((char*)generic_list[i]); } };

Passing Integer Parameters as Template Arguments

Integer parameters can be passed as template arguments to a foreign module. Doing so enables port sizes of Verilog modules to be configured using the integer template arguments. Use the -createtemplate option to scgenmod to generate a class template foreign module. Example 8-5. SystemC Instantiating Verilog, Passing Integer Parameters as Template Arguments Verilog module:
module counter (clk, count) parameter counter_size = 4; output [counter_size - 1 : 0] count; input clk; ... endmodule

Foreign module (created by the command: scgenmod -createtemplate counter):

template <int counter_size = 4> class counter : public sc_foreign_module {

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Mixed-Language Simulation SystemC Instantiating Verilog public: sc_in<sc_logic> clk; sc_out<sc_lv<counter_size-1 + 1> > count;

counter(sc_module_name nm, const char* hdl_name) : sc_foreign_module(nm), clk("clk"), count("count") { this->add_parameter("counter_size", counter_size); elaborate_foreign_module(hdl_name); } ~counter() {} };

Instantiation of the foreign module in SystemC:

SC_MODULE(top) { counter<20> counter_inst_1; // Instantiates counter with counter_size = 20 counter counter_inst_2; // Instantiates counter with default counter_size = 4 SC_CTOR(top) : counter_inst_1(cinst_1, "work.counter"), counter_inst_2(cinst_2, "work.counter") {} };

Example 8-6. Passing Integer Parameters as Template Arguments and Noninteger Parameters as Constructor Arguments Verilog module:
module counter (clk, count) parameter counter_size = 4; parameter real_param = 2.9; parameter str_param = "ERROR"; output [counter_size - 1 : 0] count; input clk; ... endmodule

Foreign module (created by command: scgenmod -createtemplate counter):

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Mixed-Language Simulation Verilog Instantiating SystemC template <int counter_size = 4> class counter : public sc_foreign_module { public: sc_in<sc_logic> clk; sc_out<sc_lv<counter_size-1 + 1> > count;

counter(sc_module_name nm, const char* hdl_name int num_generics, const char** generic_list) : sc_foreign_module(nm), clk("clk"), count("count") { this->add_parameter("counter_size", counter_size); elaborate_foreign_module(hdl_name, num_generics, generic_list); } ~counter() {} };

Instantiation of the foreign module in SystemC:

SC_MODULE(top) { // Instantiate counter with counter_size = 20 counter<20>* counter_inst_1; SC_CTOR(top) { const char* generic_list[2]; generic_list[0] = strdup("real_param=2.6"); generic_list[1] = strdup("str_param=\"Hello\""); // // The integer parameter override is already passed as template // argument. Pass the overrides for the non-integer parameters // using the foreign module constructor arguments. // counter_inst_1 = new counter<20>("c_inst", "work.counter", 2, \ generic_list); // Cleanup the memory allocated for the generic list for (int i = 0; i < 2; i++;) free((char*)generic_list[i]); } };

Verilog Instantiating SystemC

You can reference a SystemC module from Verilog as though the design unit is a module of the same name.

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SystemC Instantiation Criteria for Verilog

A SystemC module can be instantiated in Verilog if it meets the following criteria: SystemC module names are case sensitive. The module name at the SystemC instantiation site must match exactly with the actual SystemC module name. SystemC modules are exported using the SC_MODULE_EXPORT macro. See Exporting SystemC Modules for Verilog. The module ports are as listed in the table shown in Channel and Port Type Mapping. Port data type mapping must match exactly. See the table in Data Type Mapping to Verilog.

Port associations may be named or positional. Use the same port names and port positions that appear in the SystemC module declaration. Named port associations are case sensitive.

Exporting SystemC Modules for Verilog

To be able to instantiate a SystemC module from Verilog (or use a SystemC module as a top level module), the module must be exported. Assume a SystemC module named transceiver exists, and that it is declared in header file transceiver.h. Then the module is exported by placing the following code in a .cpp file:
#include "transceiver.h" SC_MODULE_EXPORT(transceiver);

Parameter Support for Verilog Instantiating SystemC

Passing Parameters from Verilog to SystemC
To pass actual parameter values, simply use the native Verilog parameter override syntax. Parameters are passed to SystemC via the module instance parameter value list. In addition to int, real, and string, ModelSim supports parameters with a bit range. Named parameter association must be used for all Verilog modules that instantiate SystemC.

Retrieving Parameter Values

To retrieve parameter override information from Verilog, you can use the following functions:

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Mixed-Language Simulation Verilog Instantiating SystemC int sc_get_param(const char* param_name, int& param_value); int sc_get_param(const char* param_name, double& param_value); int sc_get_param(const char* param_name, sc_string& param_value, char format_char = 'a');

The first argument to sc_get_param defines the parameter name, the second defines the parameter value. For retrieving string values, ModelSim also provides a third optional argument, format_char. It is used to specify the format for displaying the retrieved string. The format can be ASCII ("a" or "A"), binary ("b" or "b"), decimal ("d" or "d"), octal ("o" or "O"), or hexadecimal ("h" or "H"). ASCII is the default. These functions return a 1 if successful, otherwise they return a 0. Alternatively, you can use the following forms of the above functions in the constructor initializer list:
int sc_get_int_param(const char* param_name, int* is_successful); double sc_get_real_param(const char* param_name, int* issuccessful); sc_string sc_get_string_param(const char* param_name, char format_char = 'a', int* is_successful);

Example 8-7. Verilog Instantiating SystemC, Parameter Information Here is a complete example, ring buffer, including all files necessary for simulation.
// test_ringbuf.v `timescale 1ns / 1ps module test_ringbuf(); reg clock; ... parameter int_param = 4; parameter real_param = 2.6; parameter str_param = "Hello World"; parameter [7:0] reg_param = 'b001100xz; // Instantiate SystemC module ringbuf #(.int_param(int_param), .real_param(real_param), .str_param(str_param), .reg_param(reg_param)) chip(.clock(clock), ... ... }; endmodule ------------------------------------------------------------------------// ringbuf.h #ifndef INCLUDED_RINGBUF #define INCLUDED_RINGBUF #include <systemc.h> #include "control.h"

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Mixed-Language Simulation Verilog Instantiating SystemC ... SC_MODULE(ringbuf) { public: // Module ports sc_in clock; ... ... SC_CTOR(ringbuf) : clock("clock"), ... ... { int int_param = 0 if (sc_get_param(int_param, &int_param)) cout << int_param << int_param << end1; double real_param = 0.0; int is_successful = 0; real_param = sc_get_real_param(real_param, &is_successful); if (is_successful) cout << real_param << real_param << end1; std::string str_param; str_param = sc_get_string_param(str_param, a, &is_successful); if (is_successful) cout << str_param= << str_param.c_str() << end1; str::string reg_param; if (sc_get_param(reg_param, b)) cout << reg_param= << reg_param.c_str() << end1; } ~ringbuf() {} }; #endif -----------------------------------------------------------------------// ringbuf.cpp #include "ringbuf.h" SC_MODULE_EXPORT(ringbuf);

To run the simulation, you would enter the following commands:

vsim1> vlib work vsim1> sccom ringbuf.cpp vsim1> vlog test_ringbuf.v vsim1> sccom -link vsim1> vsim test_ringbuf

The simulation would return the following:

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Mixed-Language Simulation SystemC Instantiating VHDL # # # # int_param=4 real_param=2.6 str_param=Hello World reg_param=001100xz

SystemC Instantiating VHDL

To instantiate VHDL design units into a SystemC design, you must first generate a SystemC Foreign Module (Verilog) Declaration for each VHDL design unit you want to instantiate. Once you have generated the foreign module declaration, you can instantiate the foreign module just like any other SystemC module.

VHDL Instantiation Criteria Within SystemC

A VHDL design unit may be instantiated from SystemC if it meets the following criteria: The design unit is an entity/architecture pair or a configuration. The entity ports are of type bit, bit_vector, std_logic, std_logic_vector, std_ulogic, std_ulogic_vector, or their subtypes. The port clause may have any mix of these types. Only locally static subtypes are allowed.

Port associations may be named or positional. Use the same port names and port positions that appear in the entity.

SystemC Foreign Module (VHDL) Declaration

In cases where you want to run a mixed simulation with SystemC and VHDL, you must create and declare a foreign module that stands in for each VHDL design unit instantiated under SystemC. The foreign modules can be created in one of two ways: running scgenmod, a utility that automatically generates your foreign module declaration (much like vgencomp generates a component declaration) modifying your SystemC source code manually

After you have analyzed the design, you can generate a foreign module declaration with an scgenmod command similar to the following:
scgenmod mod1

Where mod1 is a VHDL entity. A foreign module declaration for the specified entity is written to stdout.

Guidelines for Manual Creation in VHDL

Apply the following guidelines to the creation of foreign modules. A foreign module:

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contains ports corresponding to VHDL ports. These ports must be explicitly named in the foreign modules constructor initializer list. must not contain any internal design elements such as child instances, primitive channels, or processes. must pass a secondary constructor argument denoting the modules HDL name to the sc_foreign_module base class constructor. For VHDL, the HDL name can be in the format [<lib>.]<primary>[(<secondary>)] or [<lib>.]<conf>. generics are supported for VHDL instantiations in SystemC designs. See Generic Support for SystemC Instantiating VHDL for more information. Example 8-8. SystemC Design Instantiating a VHDL Design Unit

A sample VHDL design unit to be instantiated in a SystemC design is:

entity counter is port (count : buffer bit_vector(8 downto 1); clk : in bit; reset : in bit); end; architecture only of counter is ... ... end only;

The SystemC foreign module declaration for the above VHDL module is:
class counter : public sc_foreign_module { public: sc_in<bool> clk; sc_in<bool> reset; sc_out<sc_logic> count; counter(sc_module_name nm) : sc_foreign_module(nm, "work.counter(only)"), clk("clk"), reset("reset"), count("count") {} };

The VHDL module is then instantiated in the SystemC source as follows:

counter dut("dut");

where the constructor argument (dut) is the VHDL instance name.

Generic Support for SystemC Instantiating VHDL

Since the SystemC language has no concept of generics, generic values must be passed from a SystemC parent to an HDL child through the SystemC foreign module (sc_foreign_module).
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See SystemC Foreign Module (Verilog) Declaration for information regarding the creation of sc_foreign_module.

Passing Generics to sc_foreign_module Constructor (VHDL)

To instantiate a VHDL entity containing generics into the SystemC design, you can use one of two methods, depending on whether the generic is an integer. If the generic is an integer, you have two choices: passing as a template argument to the foreign module or as a constructor argument to the foreign module. Non-integer generics must be passed to the foreign module using constructor arguments.

Passing Integer and Non-Integer Generics as Constructor Arguments

Both integer and non-integer parameters can be passed by specifying two generic parameters to the sc_foreign_module constructor: the number of generics (int num_generics), and the generic list (const char* generics_list). The generic_list is listed as an array of const char*. If you create your foreign module manually (see Guidelines for Manual Creation in VHDL), you must also pass the generic information to the sc_foreign_module constructor. If you use scgenmod to create the foreign module declaration, the generic information is detected in the HDL child and is incorporated automatically. Example 8-9. SystemC Instantiating VHDL, Generic Information Following Example 8-8, lets see the generic information that would be passed to the SystemC foreign module declaration. The generic parameters passed to the constructor are shown in magenta color:
class counter : public sc_foreign_module { public: sc_in<bool> clk; ... counter(sc_module_name nm, char* hdl_name int num_generics, const char** generic_list) : sc_foreign_module(nm, hdl_name, num_generics, generic_list), {elaborate_foreign_module(hdl_name, num_generics, generic_list);} };

The instantiation is:

dut = new counter ("dut", "work.counter", 9, generic_list);

Example 8-10. Passing Parameters as Constructor Arguments VHDL module:

entity counter is generic(

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Mixed-Language Simulation SystemC Instantiating VHDL integer_gen : integer := 4, real_gen : real := 0.0, str_gen : string); port( clk : in std_logic; count : out std_logic_vector(7 downto 0)); end counter;

Foreign module (created by the command: scgenmod counter)):

class counter : public sc_foreign_module { public: sc_in<sc_logic> clk; sc_out<sc_lv<8> > count;

counter(sc_module_name nm, const char* hdl_name int num_generics, const char** generic_list) : sc_foreign_module(nm), clk("clk"), count("count") { elaborate_foreign_module(hdl_name, num_generics, generic_list); } ~counter() {} };

Instantiation of the foreign module in SystemC:

SC_MODULE(top) { counter* counter_inst_1; // Instantiate counter with counter_size = 20

SC_CTOR(top) { const char* generic_list[3]; generic_list[0] = strdup("integer_param=16"); generic_list[1] = strdup("real_param=2.6"); generic_list[2] = strdup("str_param=\"Hello\""); //Pass all parameter overrides using foreign module constructor args counter_inst_1 = new counter("c_inst", "work.counter", 3, \ generic_list); // Cleanup the memory allocated for the generic list for (int i = 0; i < 3; i++;) free((char*)generic_list[i]); } };

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Passing Integer Generics as Template Arguments

Integer generics can be passed as template arguments to a foreign module. Doing so enables port sizes of VHDL modules to be configured using the integer template arguments. Use the -createtemplate option to scgenmod to generate a class template foreign module. Example 8-11. SystemC Instantiating VHDL, Passing Integer Generics as Template Arguments Verilog module:
entity counter is generic(counter_size : integer := 4); port( clk : in std_logic; count : out std_logic_vector(counter_size - 1 downto 0)); end counter;

Foreign module (created by the command: scgenmod -createtemplate counter):

template <int counter_size = 4> class counter : public sc_foreign_module { public: sc_in<sc_logic> clk; sc_out<sc_lv<counter_size-1 + 1> > count;

counter(sc_module_name nm, const char* hdl_name) : sc_foreign_module(nm), clk("clk"), count("count") { this->add_parameter("counter_size", counter_size); elaborate_foreign_module(hdl_name); } ~counter() {} }

Instantiation of the foreign module in SystemC:

SC_MODULE(top) { counter<20> counter_inst_1; // Instantiates counter with counter_size = 20 counter counter_inst_2; // Instantiates counter with default counter_size = 4 SC_CTOR(top) : counter_inst_1(cinst_1, "work.counter"), counter_inst_2(cinst_2, "work.counter") {}

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};

Example 8-12. Passing Integer Generics as Template Arguments and Noninteger Generics as Constructor Arguments Verilog module:
module counter (clk, count) parameter counter_size = 4; parameter real_param = 2.9; parameter str_param = "ERROR"; output [counter_size - 1 : 0] count; input clk; ... endmodule

Foreign module (created by the command: scgenmod -createtemplate counter):

template <int counter_size = 4> class counter : public sc_foreign_module { public: sc_in<sc_logic> clk; sc_out<sc_lv<counter_size-1 + 1> > count;

counter(sc_module_name nm, const char* hdl_name int num_generics, const char** generic_list) : sc_foreign_module(nm), clk("clk"), count("count") { this->add_parameter("counter_size", counter_size); elaborate_foreign_module(hdl_name, num_generics, generic_list); } ~counter() {} };

Instantiation of the foreign module in SystemC:

SC_MODULE(top) { // Instantiate counter with counter_size = 20 counter<20>* counter_inst_1; SC_CTOR(top) { const char* generic_list[2]; generic_list[0] = strdup("real_param=2.6");

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Mixed-Language Simulation VHDL Instantiating SystemC generic_list[1] = strdup("str_param=\"Hello\""); // // The integer parameter override is already passed as template // argument. Pass the overrides for the non-integer parameters // using the foreign module constructor arguments. // counter_inst_1 = new counter<20>("c_inst", "work.counter", 2, \ generic_list); // Cleanup the memory allocated for the generic list for (int i = 0; i < 2; i++;) free((char*)generic_list[i]); } };

VHDL Instantiating SystemC

To instantiate SystemC in a VHDL design, you must create a component declaration for the SystemC module. Once you have generated the component declaration, you can instantiate the SystemC component just like any other VHDL component.

SystemC Instantiation Criteria for VHDL

A SystemC design unit may be instantiated within VHDL if it meets the following criteria: SystemC module names are case sensitive. The module name at the SystemC instantiation site must match exactly with the actual SystemC module name. The SystemC design unit is exported using the SC_MODULE_EXPORT macro. The module ports are as listed in the table in Data Type Mapping to VHDL Port data type mapping must match exactly. See the table in Port Type Mapping.

Port associations may be named or positional. Use the same port names and port positions that appear in the SystemC module. Named port associations are case sensitive.

Component Declaration for VHDL Instantiating SystemC

A SystemC design unit can be referenced from a VHDL design as though it is a VHDL entity. The interface to the design unit can be extracted from the library in the form of a component declaration by running vgencomp. Given a library and a SystemC module name, vgencomp writes a component declaration to standard output. The default component port types are: std_logic

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std_logic_vector

Optionally, you can choose: bit and bit_vector

VHDL and SystemC Identifiers

The VHDL identifiers for the component name and port names are the same as the SystemC identifiers for the module name and port names. If a SystemC identifier is not a valid VHDL 1076-1987 identifier, it is converted to a VHDL 1076-1993 extended identifier (in which case you must compile the VHDL with the -93 or later switch).

vgencomp Component Declaration when VHDL Instantiates SystemC

vgencomp generates a component declaration according to these rules: Port Clause A port clause is generated if the module has ports. A corresponding VHDL port is defined for each named SystemC port. You can set the VHDL port type to bit or std_logic. If the SystemC port has a range, then the VHDL port type is bit_vector or std_logic_vector. For example: SystemC port sc_in<sc_logic>p1; sc_out<sc_lv<8>>p2; VHDL port p1 : in std_logic; p2 : out std_logic_vector(7 downto 0);

sc_inout<sc_lv<8>>p3; p3 : inout std_logic_vector(7 downto 0) Configuration declarations are allowed to reference SystemC modules in the entity aspects of component configurations. However, the configuration declaration cannot extend into a SystemC instance to configure the instantiations within the SystemC module.

Exporting SystemC Modules for VHDL

To be able to instantiate a SystemC module within VHDL (or use a SystemC module as a top level module), the module must be exported. Assume a SystemC module named transceiver exists, and that it is declared in header file transceiver.h. Then the module is exported by placing the following code in a .cpp file:
#include "transceiver.h"

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The sccom -link command collects the object files created in the work library, and uses them to build a shared library (.so) in the current work library. If you have changed your SystemC source code and recompiled it using sccom, then you must run sccom -link before invoking vsim. Otherwise your changes to the code are not recognized by the simulator.

Generic Support for VHDL Instantiating SystemC

Support for generics is available in a workaround flow for the current release. For workaround flow details, please refer to systemc_generics.note located in the <install_dir>/modeltech/docs/technotes directory.

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Chapter 9 Transactions
Introduction
A transaction is a statement of what the design is doing between one time and another during a simulation run. It is just that simple.

Transactions vs. Transaction Level Modeling (TLM)

While the definition of a transaction may be simple, the word "transaction" itself can be confusing because of its association with Transaction Level Modeling. In TLM, design units pass messages across interfaces and these messages are typically called transactions. We use the term "transaction" in a broader sense: it is an abstract statement, logged in the WLF file, of what the design was doing at a specific time. The transaction is included in the designers source code and logged into the WLF file. Often, transactions represent packets of data moving around between design objects. Transactions allow users to debug and monitor the design at any level of abstraction. You can use the SystemC Verification (SCV) library to record transactions for viewing with the ModelSim tool. You create and record transactions through published API calls in your design source code. As simulation progresses, individual transactions are recorded into the WLF file and are available for design debug and performance analysis in both interactive debug and postsimulation debug.

Transaction Definitions
Minimally, a transaction consists of a name, a start time, and an end time. With that alone, you could record the transitions of a state machine, summarize the activity on a bus, and so forth. Transactions can also be assigned user-defined attributes, such as address, data, status, and so on. Much as values are recorded on wires and signals, transactions are recorded on streams. Streams are debuggable objects: they appear in or may be added to GUI windows such as the Objects pane or Wave windows. The tool creates substreams as needed so that overlapping transactions on the stream remain distinct. Overlapping transactions can be drawn either as parallel, where no specific relationship exists between the two transactions; or phase, where the overlapping transaction is actually a child of the initial transaction.

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Viewing Transactions
Viewing transactions in the GUI is intended to be as intuitive as possible. Thus, most of the usual mouse-based operations, such as drag-and-drop, function similarly for transaction streams, substreams, attributes and elements of attributes.

Wave Window
Transaction stream objects are denoted by a four pointed star (green for SystemC). Streams which have objects below them appear with a plus icon to indicate that they can be expanded to reveal substreams and any attributes.

A Simple Transaction
Transactions are best viewed in the wave window. Figure 9-1 shows a transaction stream from a bus monitor. The transactions include simple, user-defined address and data attributes: Figure 9-1. Transaction in Wave Window

A transaction in the wave window appears as a box surrounding the transaction elements. The left edge of the box indicates the start time for the transaction, the right edge indicates the end time. A transaction that occurs in zero time appears as a simple vertical line. The top row of a transaction is the "Tag" or the kind of transaction. When the transaction stream is expanded, as in Figure 9-1, additional rows are revealed that represent attributes of the transaction.

Overlapping Transactions
When more than one transaction is recorded on a stream at one time, the transactions are overlapping. The tool creates a separate substream for each transaction so that they are distinct from each other in the view. The stream expands to reveal the different substreams in this case. Expanding the substream reveals attributes on those transactions. They appear in the wave window as follows:

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Figure 9-2. Overlapping Transactions

Substream Creation
Substreams are created so as to make debug possible. Without them, overlapping transactions would obscure each other. That said, you have no direct control over the creation of substreams; the tool creates them as needed. It uses a very simple rule: a transaction is placed on the first substream that has no active transaction and does not have any transaction in the future of the one being logged.

Retroactive Recording
Retroactive recording refers to the recording of a transaction that occurred in the past. When drawing transactions, this can lead to more substreams being added than you might expect. For example, you might have a substream with a blank period between 10 ns and 20 ns, during which no transactions are recorded, and you want to record a transaction retroactively between 11 and 16 ns. Even though there might be a space between the two transactions long enough for your retroactive transaction, the tool creates an additional substream to draw that transaction. It does this because the cost of tracking all available "spaces" in the past is too high; the simpler solution is to track the end of the last transaction on each substream only. You can control the number of retroactive recording channels that are allowed in the WLF file by setting the RetroChannelLimit in the modelsim.ini file. Setting the variable to 0 turns off retroactive recording. Setting the limit too high can risk your performance, and the WLF file may not operate.

Drawing Phase / Child Transactions

The tool has an alternative way of drawing transactions that are considered to be phases of a parent transaction. Thus, you can consider them as children of the initial transaction. For example, consider that a busRead transaction may have several steps or phases. Each of these could be represented as a smaller, overlapping transaction and would appear on a second substream. However, you can indicate that these are phase, and by doing so, you instruct the tool to draw them specially, as shown in Figure 9-3.

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Figure 9-3. Phase / Child Transactions

See Specifying and Recording Phase Transactions for information on how to specify the recording of a transaction as a phase of a parent transaction.

Structure Pane
Transactions are events occurring on transaction objects, otherwise known as streams. Stream objects look like signals in the design hierarchy. When you navigate to a region containing a stream, the stream is visible in the Objects pane or in the Transcript area in response to a show command.

Objects Pane
Streams appear as simple or composite signals, depending on the complexity of transactions that have been defined for the stream. The icon for a stream is a four-point star in the color of the source language for the region in which the stream is found. Thus, a stream in a SystemC instance has a green star as its icon. If the stream is composite (has attributes or phase/child transactions), there is an expand button to the left of the icon as with any composite object. A substream has an expand button if it in turn has a substream or if transactions on that substream have user-specified attributes. An attribute has an expand button if its value is a composite value, such as an array or structure. If there have been no transactions defined on the stream, or none of the transactions have attributes, then the stream is a simple signal with the tag of the current transaction as its value. When no transaction is active, the value is "<Inactive>". Otherwise, the value is the tag of the active transaction, such as "busRetry".

List Window
Transaction streams, substreams, attributes and attribute elements may be added to the list window alongside HDL items. For HDL items, the List window normally prints a row containing the values of all selected design elements at each time or delta advance. This makes sense, as one expects that they have only one value per time step and the deltas help to show the underlying simulation behavior,

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Transactions Recording Transactions with SCV

interaction of processes, etc. Transactions, however, may have significant events in the same delta: one transaction may end and another may begin without any time or delta advance. For transactions, the List window prints a row any time a transactions state changes. Specifically, rows are printed when a transaction starts or ends, and when any attribute changes state. The following is an example of a list output for a stream, showing a begin attribute, a special attribute and an end attribute in the style of SCV:
ns /top/abc/busMon delta 0 +0 <Inactive> 1 +0 <Inactive> 1 +0 <Inactive> 1 +0 {busRead 1 <Inactive> <Inactive>} 3 +0 {busRead 1 100 <Inactive>} 3 +0 {busRead 1 100 10} 3 +0 <Inactive> 4 +0 <Inactive> 4 +0 <Inactive> 4 +0 <Inactive> ...

In the list above, the same time/delta repeats itself as changes are made to the transaction. For example, at 1(0) a busRead begins with the begin attribute set to the value 1. At time 3(0), the end attribute value 100 arrives, and so on.

Recording Transactions with SCV

SystemC users use the SCV librarys transaction recording API routines to define transactions, to start them, to end them, to create relationships between them and to attach additional information (attributes) to them. These routines are described in the SystemC Verification Standard Specification, Version 1.0e. Please refer to this documentation for SCV specific details. This section highlights specific steps you must take to record transactions in a WLF file. SCV recording in ModelSim requires only one addition to your source code: the design must call scv_tr_wlf_init() to log transactions in the WLF file (see Initializing the Library and Creating the WLF Database). Note You must include the SCV libraries as part of the build process using the -scv argument to the tools SystemC compilation command sccom, during both the compilation and the linking phases.

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Steps for Recording in SCV

The steps can be summarized as follows: Initialize SCV and the MTI extensions for transaction recording and debug. Create a database tied to WLF. Provide SCV extensions for user-defined types used with attributes. Define transaction streams. Define transaction kinds. Start transactions. Record special attributes. End transactions.

Recording of attributes and relationships can occur at different points between (and including) the start and end of the transaction(s) as specified in the SCV API. Additional actions can include: Specify relationships between transactions. Specify the begin and/or end time for a transaction. Control database logging.

The sections which follow document any areas where the ModelSim tools implementation deviates from the SCV specification.

Initializing the Library and Creating the WLF Database

The design must initialize the SCV library once as part of its own initialization. In your code, you issue a call to scv_startup(), followed by scv_tr_wlf_init(). After this, transactions are written to specific database objects in the code. You can create many objects, or create one and specify it as the default object. The following is an example of a one-time initialization routine that sets up SCV, ties all databases to WLF and then creates one database as the default:
static scv_tr_db * init_recording() { scv_tr_db *txdb; /* Initialize SCV: */ scv_startup(); /* Tie databases to WLF: */ scv_tr_wlf_init();

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/* Create the new DB and make it the default: */ txdb = new scv_tr_db("txdb"); if (txdb != NULL) scv_tr_db::set_default_db(txdb); return txdb;

The ModelSim tool ignores the name argument to scv_tr_db() since all databases are tied to the WLF file once the user calls scv_tr_wlf_init(). The ModelSim tool also ignores the sc_time_unit argument to scv_tr_db() when the database is a WLF database. The time unit of the database is specified by the overall simulation time unit.

Preparing Attribute Types

If your design uses standard C and SC types for attributes, no preparation work is needed with SCV, since SCV Extensions are defined for those types. For classes, structures or other userdefined types, you must provide SCV extensions so that SCV and the ModelSim tool can extract the necessary type and composition information to record the type. An example is as follows:
struct busAddrAttr { unsigned _addr; }; template<> class scv_extensions<busAddrAttr> : public scv_extensions_base<busAddrAttr> { public: scv_extensions<unsigned> _addr; SCV_EXTENSIONS_CTOR(busAddrAttr) { SCV_FIELD(_addr); } };

All C/C++ and SystemC types are supported, with the exception of those listed in the section Unsupported Types.

Naming Attributes
Legal C-language identifiers are recommended for naming attributes, as these are guaranteed to be supported for debug. Note The ModelSim tool issues a warning for a non-standard name.

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Defining Transaction Streams

Transactions are written on streams just the way ones and zeros are driven onto wires in a design. Therefore, the design must create one or more stream objects. Streams are tied to a specific database so that all transactions on them are written into that database only. Usually, the code declares the stream as a member of the module that will use it. Then, it must call the constructor, passing the stream's name (see Naming Streams) and database as parameters:
SC_MODULE(busModel) { public: scv_tr_db *txdb; scv_tr_stream busStream; SC_CTOR(busModel) : txdb(init_recording()), busStream( "busModel", "**TRANSACTOR**") { } }

This example code declares the database and stream objects. In the module constructor, it initializes the database by calling the setup routine. It initializes the stream object with its display name and a string indicating the stream kind. The database is presumed to be the default, though we could have been explicit and passed "txdb" as a third parameter.

Naming Transactions
The name of a transaction is the same as the name of the generator used to start the transaction. Anonymous transactions are not allowed. There are no restrictions on the names, though we recommend using standard C-language identifiers.

Naming Streams
You must provide a name for streams so that they can be referenced for debug. Anonymous streams are not allowed. Any name can be used, however, only legal C-language identifiers are recommended since these are guaranteed to be supported for debug. Note The ModelSim tool issues a warning for a non-standard name.

Substream Names
The tool names substreams automatically. The name of any substream is the first character of the parents name followed by a simple index number. The first substream has the index zero. If the parent stream has a non-standard name, such as one that starts with a numeral or a space, you may have difficulty with debug.
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Defining Transaction Kinds

In SCV, each transaction is defined by a generator object, a kind of template for a transaction. The generator specifies the tag of the transaction and optional begin and end attributes. That is, begin and end attributes are part of the generator for that kind and are treated as part of each instance of that transaction. First, the code must declare each generator, usually in the module in which it is to be used. Any begin and end attribute types must be provided as template parameters. Then, the generator must be constructed, usually in the constructor initialization list of the parent module:
SC_MODULE(busModel) { public: scv_tr_db *txdb; scv_tr_stream busStream; scv_tr_generator<busAddrAttr, busDataAttr> busRead; SC_CTOR(busModel) : txdb(init_recording()), busStream( "busModel", "**TRANSACTOR**"), busRead("busRead", busStream) { } }

The third and fourth arguments to scv_tr_generator::scv_tr_generator() are the names for the begin and end attributes. SCV allows these to be NULL by default. The above example adds the declaration of the generator "busRead" and shows how the constructor is provided with a name (also "busRead") and the stream on which it will be used. The begin and end attributes are left anonymous. For any given stream, an attribute's type is fixed the first time you use the attribute. Therefore, you can not change the type of that attribute on that stream. If you try, the ModelSim tool issues a fatal error.

Starting Transactions
To issue a transaction, the design sets the value for the begin attribute and calls scv_tr_generator::begin_transaction(...) with the appropriate parameters as defined in the SCV API:
scv_tr_handle txh; busAddrAttr busAddr; busAddr._addr = 0x00FC01; txh = busRead.begin_transaction(busAddr);

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In this example, only the begin attribute "busAddr" is passed to ::begin_transaction(). Other parameters may be used to specify relationships or specify a begin time other than the current simulation time (see Specifying Start and End Times). Your design is not required to specify the values of begin attributes, even if they are part of the generator. For example, if your design had done this:
txh = busRead.begin_transaction();

... the value of the begin attribute would be considered undefined. The ModelSim tool allows this and indicates that such values are undefined for a specific transaction instance.

Recording Special Attributes

Special attributes are not part of the original transaction generator: they are afterthoughts. The type is defined as discussed in the section entitled Preparing Attribute Types, but they are recorded on the specific transaction instance through the transaction handle:
if (status != BUS_OK) { errorAttr err; err.code = status; txh.record_attribute(err); }

Multiple Uses of Same Special Attribute

There is nothing to prevent your design from setting the same special attribute many times during the transaction. However, the ModelSim tool records only the last value of the attribute prior to the end of the transaction. Once any attribute is used, special or otherwise, it is considered an attribute of the parent stream from that time onward. Thus, it shows up as a parameter on all subsequent transactions, even if it is unused.

Ending Transactions
You can end transactions in your code by placing a call to scv_tr_generator::end_transaction(), specifying any end attributes or other parameters:
busDataAttr busData; busData._data = 10; busRead.end_transaction(txh, busData);

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In this example, only the transaction handle "txh" and the end attribute "busData" is passed to ::end_transaction(). Other parameters may be used to specify relationships or specify an end time other than the current simulation time. See Specifying Start and End Times for details. The design is not required to specify the values of end attributes, even if they are part of the generator. For example, if the design had done this:
busRead.end_transaction(txh);

... the value of the end attribute would be considered undefined. The ModelSim tool allows this and indicates that such values are undefined for a specific transaction instance.

Specifying and Recording Phase Transactions

Phase (child) transactions are unique to ModelSim. If recorded, they appear as transactions attached to their parent. The SCV specification does not describe this kind of transaction, but ModelSim can record it. To record phase transactions, you must specify mti_phase as the relation name and provide an appropriate parent transaction handle in a call to ::begin_transaction(). Any transaction may have phases, including another phase transaction. You can specify your own relation name for phases by modifying the value of the variable ScvPhaseRelationName in the modelsim.ini from mti_phase to something else, such as child. This variable applies to recording only; once a phase is recorded in a WLF file, it is drawn as a phase, regardless of the setting of this variable.

Specifying Start and End Times

The SCV API allows you to specify a start and/or end time for any transaction. These are passed as parameters to ::begin_transaction() and ::end_transaction(). The time must be the current simulation time or earlier.

Start and End Times for Phase Transactions

The start and end times for phase (child) transactions must be entirely within the range of the parent transaction. In other words, the start time for the phase transaction must match or be later than the parent transactions start time, and the end time must match or be earlier than the parents end time.

Enabling and Disabling Logging

For transactions, all logging control is through SCV API routines. By default, when your design creates a stream, logging is enabled for that stream. You can enable and disable logging for the entire TR database through calls to scv_tr_db::set_recording(). There is no way to disable

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recording on a single stream. Further, there is no way in the ModelSim tool to distinguish a stream that is disabled from one that is merely inactive.

Limitations on SCV
The following limitations apply to SCV transactions in the ModelSim tool.

Unsupported Types
C/C++ native and user-defined types (array, class, struct, union) and all SystemC types are supported with the following exceptions:

Unsupported C++ Atomic Types

bit-field T* (pointer)

Unsupported C/C++ Aggregate Types

C/C++ user-defined types of all kinds are supported only if the design includes the SCV Introspection code for them.

Unsupported SC Fixed-Point Types

Most C/C++ and SystemC types are supported, however the following are limited or are not supported at this time: sc_fix, sc_fix_fast sc_fixed, sc_fixed_fast sc_ufix, sc_ufix_fast sc_ufixed, sc_ufixed_fast

Recording in one WLF

You can record transactions in one WLF file at a time. The SCV API routines allow you to create and use multiple databases. However, if the chosen database is WLF, all databases are aliased to the same WLF file. Once created, you may load multiple WLF files that contain transactions into ModelSim for viewing and debugging.

Relation Recording
Relations are not recorded in the WLF database in the current release.

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Chapter 10 WLF Files (Datasets) and Virtuals

This chapter describes the Wave Log Format (WLF) file and how you should and can use it in your simulation flow. A ModelSim simulation can be saved to a wave log format (WLF) file for future viewing or comparison to a current simulation. We use the term "dataset" to refer to a WLF file that has been reopened for viewing. You can open more than one WLF file for simultaneous viewing. You can also create virtual signals that are simple logical combinations of, or logical functions of, signals from different datasets. WLF files are recordings of simulation runs. The WLF file is written as an archive file in binary format and is used to drive the debug windows at a later time. The files contain data from logged objects (e.g., signals and variables) and the design hierarchy in which the logged objects are found. You can record the entire design or choose specific objects. The WLF file provides you with precise in-simulation and post-simulation debugging capability. Any number of WLF files can be reloaded for viewing or comparing to the active simulation. A dataset is a previously recorded simulation that has been loaded into ModelSim. Each dataset has a logical name to let you indicate the dataset to which any command applies. This logical name is displayed as a prefix. The current, active simulation is prefixed by "sim:", while any other datasets are prefixed by the name of the WLF file by default. Two datasets are displayed in the Wave window in Figure 10-1. The current simulation is shown in the top pane and is indicated by the "sim" prefix. A dataset from a previous simulation is shown in the bottom pane and is indicated by the "gold" prefix.

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Figure 10-1. Displaying Two Datasets in the Wave Window

The simulator resolution (see Simulator Resolution Limit (Verilog) or Simulator Resolution Limit (VHDL)) must be the same for all datasets you are comparing, including the current simulation. If you have a WLF file that is in a different resolution, you can use the wlfman command to change it.

Saving a Simulation to a WLF File

If you add objects to the Dataflow, List, or Wave windows, or log objects with the log command, the results of each simulation run are automatically saved to a WLF file called vsim.wlf in the current directory. If you then run a new simulation in the same directory, the vsim.wlf file is overwritten with the new results. If you want to save the WLF file and not have it be overwritten, select the dataset tab in the Workspace and then select File > Save. Or, you can use the -wlf <filename> argument to the vsim command or the dataset save command.

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Note If you do not use dataset save or dataset snapshot, you must end a simulation session with a quit or quit -sim command in order to produce a valid WLF file. If you dont end the simulation in this manner, the WLF file will not close properly, and ModelSim may issue the error message "bad magic number" when you try to open an incomplete dataset in subsequent sessions. If you end up with a "damaged" WLF file, you can try to "repair" it using the wlfrecover command.

WLF File Parameter Overview

There are a number of WLF file parameters that you can control via the modelsim.ini file or a simulator argument. This section summarizes the various parameters. Table 10-1. WLF File Parameters Feature WLF Filename WLF Size Limit WLF Time Limit WLF Compression WLF Optimization1 WLF Delete on Quita WLF Cache Sizea WLF Collapse Mode vsim argument -wlf <filename> -wlfslim <n> -wlftlim <t> -wlfcompress -wlfnocompress -wlfopt -wlfnoopt -wlfdeleteonquit -wlfnodeleteonquit -wlfcachesize <n> -wlfnocollapse -wlfcollapsedelta -wlfcollapsetime modelsim.ini WLFSizeLimit = <n> WLFTimeLimit = <t> WLFCompress = 0|1 WLFOptimize = 0|1 WLFDeleteOnQuit = 0|1 WLFCacheSize = <n> Default no limit no limit 1 (-wlfcompress) 1 (-wlfopt) 0 256 WLFFilename=<filename> vsim.wlf

WLFCollapseModel = 0|1|2 1

1. These parameters can also be set using the dataset config command.

WLF Filename Specify the name of the WLF file. WLF Size Limit Limit the size of a WLF file to <n> megabytes by truncating from the front of the file as necessary. WLF Time Limit Limit the size of a WLF file to <t> time by truncating from the front of the file as necessary. WLF Compression Compress the data in the WLF file. WLF Optimization Write additional data to the WLF file to improve draw performance at large zoom ranges. Optimization results in approximately 15% larger

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WLF files. Disabling WLF optimization also prevents ModelSim from reading a previously generated WLF file that contains optimized data. WLF Delete on Quit Delete the WLF file automatically when the simulation exits. Valid for current simulation dataset (vsim.wlf) only. WLF Cache Size Specify the size in megabytes of the WLF reader cache. WLF reader cache is enabled by default. The default value is 256. This feature caches blocks of the WLF file to reduce redundant file I/O. If the cache is made smaller or disabled, least recently used data will be freed to reduce the cache to the specified size. WLF Collapse Mode WLF event collapsing has three settings: disabled, delta, time:
o o

When disabled, all events and event order are preserved. Delta mode records an object's value at the end of a simulation delta (iteration) only. Default. Time mode records an object's value at the end of a simulation time step only.

Opening Datasets
To open a dataset, do one of the following: Select File > Open and choose Log Files or use the dataset open command. Figure 10-2. Open Dataset Dialog Box

The Open Dataset dialog includes the following options: Dataset Pathname Identifies the path and filename of the WLF file you want to open. Logical Name for Dataset This is the name by which the dataset will be referred. By default this is the name of the WLF file.

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Viewing Dataset Structure

Each dataset you open creates a structure tab in the Main window workspace. The tab is labeled with the name of the dataset and displays a hierarchy of the design units in that dataset. The graphic below shows three structure tabs: one for the active simulation (sim) and one each for two datasets (test and gold). Figure 10-3. Structure Tabs in Workspace Pane

Click here to scroll tabs

If you have too many tabs to display in the available space, you can scroll the tabs left or right by clicking the arrow icons at the bottom right-hand corner of the window.

Structure Tab Columns

Each structure tab displays three columns by default: Table 10-2. Structure Tab Columns Column name Instance Design unit Description the name of the instance the name of the design unit

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Table 10-2. Structure Tab Columns (cont.) Column name Design unit type Description the type (e.g., Module, Entity, etc.) of the design unit

Aside from the three columns listed above, there are numerous columns related to code coverage that can be displayed in structure tabs. You can hide or show columns by rightclicking a column name and selecting the name on the list.

Managing Multiple Datasets

GUI
When you have one or more datasets open, you can manage them using the Dataset Browser. To open the browser, select File > Datasets. Figure 10-4. The Dataset Browser

Command Line
You can open multiple datasets when the simulator is invoked by specifying more than one vsim -view <filename> option. By default the dataset prefix will be the filename of the WLF file. You can specify a different dataset name as an optional qualifier to the vsim -view switch on the command line using the following syntax:
-view <dataset>=<filename>

For example:

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WLF Files (Datasets) and Virtuals Managing Multiple Datasets vsim -view foo=vsim.wlf

ModelSim designates one of the datasets to be the "active" dataset, and refers all names without dataset prefixes to that dataset. The active dataset is displayed in the context path at the bottom of the Main window. When you select a design unit in a datasets structure tab, that dataset becomes active automatically. Alternatively, you can use the Dataset Browser or the environment command to change the active dataset. Design regions and signal names can be fully specified over multiple WLF files by using the dataset name as a prefix in the path. For example:
sim:/top/alu/out view:/top/alu/out golden:.top.alu.out

Dataset prefixes are not required unless more than one dataset is open, and you want to refer to something outside the active dataset. When more than one dataset is open, ModelSim will automatically prefix names in the Wave and List windows with the dataset name. You can change this default by selecting Tools > Window Preferences (Wave and List windows). ModelSim also remembers a "current context" within each open dataset. You can toggle between the current context of each dataset using the environment command, specifying the dataset without a path. For example:
env foo:

sets the active dataset to foo and the current context to the context last specified for foo. The context is then applied to any unlocked windows. The current context of the current dataset (usually referred to as just "current context") is used for finding objects specified without a path. The Objects pane can be locked to a specific context of a dataset. Being locked to a dataset means that the pane will update only when the content of that dataset changes. If locked to both a dataset and a context (e.g., test: /top/foo), the pane will update only when that specific context changes. You specify the dataset to which the pane is locked by selecting File > Environment.

Restricting the Dataset Prefix Display

The default for dataset prefix viewing is set with a variable in pref.tcl, PrefMain(DisplayDatasetPrefix). Setting the variable to 1 will display the prefix, setting it to 0 will not. It is set to 1 by default. Either edit the pref.tcl file directly or use the Tools > Edit Preferences command to change the variable value. Additionally, you can restrict display of the dataset prefix if you use the environment -nodataset command to view a dataset. To display the prefix use the environment command

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with the -dataset option (you wont need to specify this option if the variable noted above is set to 1). The environment command line switches override the pref.tcl variable.

Saving at Intervals with Dataset Snapshot

Dataset Snapshot lets you periodically copy data from the current simulation WLF file to another file. This is useful for taking periodic "snapshots" of your simulation or for clearing the current simulation WLF file based on size or elapsed time. Once you have logged the appropriate objects, select Tools > Dataset Snapshot (Wave window). Figure 10-5. Dataset Snapshot Dialog

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WLF Files (Datasets) and Virtuals Collapsing Time and Delta Steps

Collapsing Time and Delta Steps

By default ModelSim collapses delta steps. This means each logged signal that has events during a simulation delta has its final value recorded to the WLF file when the delta has expired. The event order in the WLF file matches the order of the first events of each signal. You can configure how ModelSim collapses time and delta steps using arguments to the vsim command or by setting the WLFCollapseMode variable in the modelsim.ini file. The table below summarizes the arguments and how they affect event recording. Table 10-3. vsim Arguments for Collapsing Time and Delta Steps vsim argument -wlfnocollapse effect All events for each logged signal are recorded to the WLF file in the exact order they occur in the simulation. modelsim.ini setting WLFCollapseMode = 0

-wlfdeltacollapse

Each logged signal which has events during a WLFCollapseMode = 1 simulation delta has its final value recorded to the WLF file when the delta has expired. Default. Same as delta collapsing but at the timestep granularity. WLFCollapseMode = 2

-wlftimecollapse

When a run completes that includes single stepping or hitting a breakpoint, all events are flushed to the WLF file regardless of the time collapse mode. Its possible that single stepping through part of a simulation may yield a slightly different WLF file than just running over that piece of code. If particular detail is required in debugging, you should disable time collapsing.

Virtual Objects
Virtual objects are signal-like or region-like objects created in the GUI that do not exist in the ModelSim simulation kernel. ModelSim supports the following kinds of virtual objects: Virtual Signals Virtual Functions Virtual Regions Virtual Types

Virtual objects are indicated by an orange diamond as illustrated by bus in Figure 10-6:

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Figure 10-6. Virtual Objects Indicated by Orange Diamond

Virtual Signals
Virtual signals are aliases for combinations or subelements of signals written to the WLF file by the simulation kernel. They can be displayed in the Objects, List, and Wave windows, accessed by the examine command, and set using the force command. You can create virtual signals using the Tools > Combine Signals (Wave and List windows) menu selections or by using the virtual signal command. Once created, virtual signals can be dragged and dropped from the Objects pane to the Wave and List windows. Virtual signals are automatically attached to the design region in the hierarchy that corresponds to the nearest common ancestor of all the elements of the virtual signal. The virtual signal command has an -install <region> option to specify where the virtual signal should be installed. This can be used to install the virtual signal in a user-defined region in order to reconstruct the original RTL hierarchy when simulating and driving a post-synthesis, gate-level implementation. A virtual signal can be used to reconstruct RTL-level design buses that were broken down during synthesis. The virtual hide command can be used to hide the display of the broken-down bits if you don't want them cluttering up the Objects pane. If the virtual signal has elements from more than one WLF file, it will be automatically installed in the virtual region virtuals:/Signals.

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Virtual signals are not hierarchical if two virtual signals are concatenated to become a third virtual signal, the resulting virtual signal will be a concatenation of all the scalar elements of the first two virtual signals. The definitions of virtuals can be saved to a macro file using the virtual save command. By default, when quitting, ModelSim will append any newly-created virtuals (that have not been saved) to the virtuals.do file in the local directory. If you have virtual signals displayed in the Wave or List window when you save the Wave or List format, you will need to execute the virtuals.do file (or some other equivalent) to restore the virtual signal definitions before you re-load the Wave or List format during a later run. There is one exception: "implicit virtuals" are automatically saved with the Wave or List format.

Implicit and Explicit Virtuals

An implicit virtual is a virtual signal that was automatically created by ModelSim without your knowledge and without you providing a name for it. An example would be if you expand a bus in the Wave window, then drag one bit out of the bus to display it separately. That action creates a one-bit virtual signal whose definition is stored in a special location, and is not visible in the Objects pane or to the normal virtual commands. All other virtual signals are considered "explicit virtuals".

Virtual Functions
Virtual functions behave in the GUI like signals but are not aliases of combinations or elements of signals logged by the kernel. They consist of logical operations on logged signals and can be dependent on simulation time. They can be displayed in the Objects, Wave, and List windows and accessed by the examine command, but cannot be set by the force command. Examples of virtual functions include the following: a function defined as the inverse of a given signal a function defined as the exclusive-OR of two signals a function defined as a repetitive clock a function defined as "the rising edge of CLK delayed by 1.34 ns"

Virtual functions can also be used to convert signal types and map signal values. The result type of a virtual function can be any of the types supported in the GUI expression syntax: integer, real, boolean, std_logic, std_logic_vector, and arrays and records of these types. Verilog types are converted to VHDL 9-state std_logic equivalents and Verilog net strengths are ignored.

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Virtual functions can be created using the virtual function command. Virtual functions are also implicitly created by ModelSim when referencing bit-selects or partselects of Verilog registers in the GUI, or when expanding Verilog registers in the Objects, Wave, or List window. This is necessary because referencing Verilog register elements requires an intermediate step of shifting and masking of the Verilog "vreg" data structure.

Virtual Regions
User-defined design hierarchy regions can be defined and attached to any existing design region or to the virtuals context tree. They can be used to reconstruct the RTL hierarchy in a gate-level design and to locate virtual signals. Thus, virtual signals and virtual regions can be used in a gate-level design to allow you to use the RTL test bench. Virtual regions are created and attached using the virtual region command.

Virtual Types
User-defined enumerated types can be defined in order to display signal bit sequences as meaningful alphanumeric names. The virtual type is then used in a type conversion expression to convert a signal to values of the new type. When the converted signal is displayed in any of the windows, the value will be displayed as the enumeration string corresponding to the value of the original signal. Virtual types are created using the virtual type command.

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Chapter 11 Waveform Analysis

When your simulation finishes, you will often want to analyze waveforms to assess and debug your design. Designers typically use the Wave window for waveform analysis. However, you can also look at waveform data in a textual format in the List window. To analyze waveforms in ModelSim, follow these steps: 1. Compile your files. 2. Load your design. 3. Add objects to the Wave or List window.
add wave <object_name> add list <object_name>

4. Run the design.

Objects You Can View

The list below identifies the types of objects can be viewed in the Wave or List window. VHDL objects (indicated by dark blue diamond in the Wave window) signals, aliases, process variables, and shared variables Verilog objects (indicated by light blue diamond in the Wave window) nets, registers, variables, and named events SystemC objects (indicated by a green diamond in the Wave window) primitive channels and ports Virtual objects (indicated by an orange diamond in the Wave window) virtual signals, buses, and functions, see; Virtual Objects for more information Comparisons (indicated by a yellow triangle) comparison regions and comparison signals; see Waveform Compare for more information

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Wave Window Overview

The Wave window opens by default in the MDI frame of the Main window as shown below. The window can be undocked from the main window by pressing the Undock button in the window header or by using the view -undock wave command. The preference variable PrefMain(ViewUnDocked) wave can be used to control this default behavior. Setting this variable will open the Wave Window undocked each time you start ModelSim. Figure 11-1. Undocking the Wave Window

Here is an example of a Wave window that is undocked from the MDI frame. All menus and icons associated with Wave window functions now appear in the menu and toolbar areas of the Wave window.

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Waveform Analysis Wave Window Overview

Figure 11-2. Docking the Wave Window

If the Wave window is docked into the Main window MDI frame, all menus and icons that were in the standalone version of the Wave window move into the Main window menu bar and toolbar. The Wave window is divided into a number of window panes. All window panes in the Wave window can be resized by clicking and dragging the bar between any two panes.

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Waveform Analysis List Window Overview

Figure 11-3. Panes in the Wave Window

List Window Overview

The List window displays simulation results in tabular format. Common tasks that people use the window for include: Using gating expressions and trigger settings to focus in on particular signals or events. See Configuring New Line Triggering in the List Window. Debugging delta delay issues. See Delta Delays for more information.

The window is divided into two adjustable panes, which allows you to scroll horizontally through the listing on the right, while keeping time and delta visible on the left.

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Figure 11-4. Tabular Format of the List Window

Adding Objects to the Wave or List Window

You can add objects to the Wave or List window in several ways.

Adding Objects with Drag and Drop

You can drag and drop objects into the Wave or List window from the Workspace, Active Processes, Memory, Objects, Source, or Locals panes. You can also drag objects from the Wave window to the List window and vice versa. Select the objects in the first window, then drop them into the Wave window. Depending on what you select, all objects or any portion of the design can be added.

Adding Objects with a Menu Command

The Add menu in the Main windows let you add objects to the Wave window, List window, or Log file.

Adding Objects with a Command

Use the add list or add wave commands to add objects from the command line. For example:
VSIM> add wave /proc/a

Adds signal /proc/a to the Wave window.

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Waveform Analysis Measuring Time with Cursors in the Wave Window VSIM> add list *

Adds all the objects in the current region to the List window.
VSIM> add wave -r /*

Adds all objects in the design to the Wave window.

Adding Objects with a Window Format File

Select File > Open > Format and specify a previously saved format file. See Saving the Window Format for details on how to create a format file.

Measuring Time with Cursors in the Wave Window

ModelSim uses cursors to measure time in the Wave window. Cursors extend a vertical line over the waveform display and identify a specific simulation time. Multiple cursors can be used to measure time intervals, as shown in the graphic below. When the Wave window is first drawn, there is one cursor located at time zero. Clicking anywhere in the waveform display brings that cursor to the mouse location. The selected cursor is drawn as a bold solid line; all other cursors are drawn with thin lines. As shown in the graphic below, three window panes relate to cursors: the cursor name pane on the bottom left, the cursor value pane in the bottom middle, and the cursor pane with horizontal "tracks" on the bottom right.

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Waveform Analysis Measuring Time with Cursors in the Wave Window

Figure 11-5. Cursor Names, Values and Time Measurements

Working with Cursors

The table below summarizes common cursor actions. Table 11-1. Actions for Cursors Action Add cursor Menu command Menu command (Wave window docked) (Wave window undocked) Add > Wave > Cursor Add > Cursor Toolbar button

Delete cursor

Wave > Delete Cursor

Edit > Delete Cursor

Zoom In on Active Cursor

Wave > Zoom > Zoom Cursor

View > Zoom > Zoom Cursor

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Waveform Analysis Measuring Time with Cursors in the Wave Window

Table 11-1. Actions for Cursors (cont.) Action Lock cursor Name cursor Select cursor Menu command Menu command (Wave window docked) (Wave window undocked) Wave > Edit Cursor Wave > Edit Cursor Wave > Cursors Edit > Edit Cursor Edit > Edit Cursor View > Cursors Toolbar button NA NA NA

Shortcuts for Working with Cursors

There are a number of useful keyboard and mouse shortcuts related to the actions listed above: Select a cursor by clicking the cursor name. Jump to a "hidden" cursor (one that is out of view) by double-clicking the cursor name. Name a cursor by right-clicking the cursor name and entering a new value. Press <Enter> on your keyboard after you have typed the new name. Move a locked cursor by holding down the <shift> key and then clicking-and-dragging the cursor. Move a cursor to a particular time by right-clicking the cursor value and typing the value to which you want to scroll. Press <Enter> on your keyboard after you have typed the new value.

Understanding Cursor Behavior

The following list describes how cursors "behave" when you click in various panes of the Wave window: If you click in the waveform pane, the cursor closest to the mouse position is selected and then moved to the mouse position. Clicking in a horizontal "track" in the cursor pane selects that cursor and moves it to the mouse position. Cursors "snap" to a waveform edge if you click or drag a cursor along the selected waveform to within ten pixels of a waveform edge. You can set the snap distance in the Window Preferences dialog. Select Tools > Options > Wave Preferences when the Wave window is docked in the Main window MDI frame. Select Tools > Window Preferences when the Wave window is a stand-alone, undocked window. You can position a cursor without snapping by dragging in the cursor pane below the waveforms.

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Waveform Analysis Setting Time Markers in the List Window

Jumping to a Signal Transition

You can move the active cursor to the next or previous transition on the selected signal using these two buttons on the toolbar: Find Previous Transition locate the previous signal value change for the selected signal Find Next Transition locate the next signal value change for the selected signal

Setting Time Markers in the List Window

Time markers in the List window are similar to cursors in the Wave window. Time markers tag lines in the data table so you can quickly jump back to that time. Markers are indicated by a thin box surrounding the marked line. Figure 11-6. Time Markers in the List Window

Working with Markers

The table below summarizes actions you can take with markers. Table 11-2. Actions for Time Markers Action Add marker Method Select a line and then select Edit > Add Marker
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Waveform Analysis Zooming the Wave Window Display

Table 11-2. Actions for Time Markers (cont.) Action Delete marker Goto marker Method Select a tagged line and then select Edit > Delete Marker Select View > Goto > <time>

Zooming the Wave Window Display

Zooming lets you change the simulation range in the waveform pane. You can zoom using the context menu, toolbar buttons, mouse, keyboard, or commands.

Zooming with the Menu, Toolbar and Mouse

You can access Zoom commands from the View menu in the Wave window when it is undocked, from the Wave > Zoom menu selections in the Main window when the Wave window is docked, or by clicking the right mouse button in the waveform pane of the Wave window. These zoom buttons are available on the toolbar: Zoom In 2x zoom in by a factor of two from the current view Zoom In on Active Cursor centers the active cursor in the waveform display and zooms in Zoom Mode change mouse pointer to zoom mode; see below To zoom with the mouse, first enter zoom mode by selecting View > Zoom > Mouse Mode > Zoom Mode. The left mouse button then offers 3 zoom options by clicking and dragging in different directions: Down-Right or Down-Left: Zoom Area (In) Up-Right: Zoom Out Up-Left: Zoom Fit Zoom Out 2x zoom out by a factor of two from current view Zoom Full zoom out to view the full range of the simulation from time 0 to the current time

Also note the following about zooming with the mouse:

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Waveform Analysis Zooming the Wave Window Display

The zoom amount is displayed at the mouse cursor. A zoom operation must be more than 10 pixels to activate. You can enter zoom mode temporarily by holding the <Ctrl> key down while in select mode. With the mouse in the Select Mode, the middle mouse button will perform the above zoom operations.

Saving Zoom Range and Scroll Position with Bookmarks

Bookmarks save a particular zoom range and scroll position. This lets you return easily to a specific view later. You save the bookmark with a name and then access the named bookmark from the Bookmark menu. Bookmarks are saved in the Wave format file (see Adding Objects with a Window Format File) and are restored when the format file is read.

Managing Bookmarks
The table below summarizes actions you can take with bookmarks. Table 11-3. Actions for Bookmarks Action Menu commands (Wave window docked) Add > Wave > Bookmark Wave > Bookmarks > <bookmark_name> Menu commands (Wave window undocked) Add > Bookmark View > Bookmarks > <bookmark_name> Command

Add bookmark View bookmark

bookmark add wave bookmark goto wave bookmark delete wave

Delete bookmark Wave > Bookmarks > View > Bookmarks > Bookmarks > <select Bookmarks > <select bookmark then Delete> bookmark then Delete>

Adding Bookmarks
To add a bookmark, follow these steps: 1. Zoom the wave window as you see fit using one of the techniques discussed in Zooming the Wave Window Display. 2. If the Wave window is docked, select Add > Wave > Bookmark. If the Wave window is undocked, select Add > Bookmark.

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Waveform Analysis Searching in the Wave and List Windows

Figure 11-7. Bookmark Properties Dialog

3. Give the bookmark a name and click OK.

Editing Bookmarks
Once a bookmark exists, you can change its properties by selecting Wave > Bookmarks > Bookmarks if the Wave window is docked; or by selecting Tools > Bookmarks if the Wave window is undocked.

Searching in the Wave and List Windows

The Wave and List windows provide two methods for locating objects: Finding signal names Select Edit > Find or use the find command to search for the name of a signal. Search for values or transitions Select Edit > Signal Search to locate transitions or signal values. The search feature is not available in all versions of ModelSim.

Finding Signal Names

The Find command is used to locate a signal name or value in the Wave or List window. When you select Edit > Find, the Find dialog appears.

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Waveform Analysis Searching in the Wave and List Windows

Figure 11-8. Find Signals by Name or Value

One option of note is the "Exact" checkbox. Check Exact if you only want to find objects that match your search exactly. For example, searching for "clk" without Exact will find /top/clk and clk1. There are two differences between the Wave and List windows as it relates to the Find feature: In the Wave window you can specify a value to search for in the values pane. The find operation works only within the active pane in the Wave window.

Searching for Values or Transitions

Available in some versions of ModelSim, the Search command lets you search for transitions or values on selected signals. When you select Edit > Search Signals, the Signal Search dialog appears.

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Waveform Analysis Searching in the Wave and List Windows

Figure 11-9. Wave Signal Search Dialog

One option of note is Search for Expression. The expression can involve more than one signal but is limited to signals currently in the window. Expressions can include constants, variables, and DO files. See Expression Syntax for more information.

Using the Expression Builder for Expression Searches

The Expression Builder is a feature of the Wave and List Signal Search dialog boxes, and the List trigger properties dialog box. It aids in building a search expression that follows the GUI_expression_format. To locate the Builder: select Edit > Search Signals (List or Wave window) select the Search for Expression option in the resulting dialog box select the Builder button

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Waveform Analysis Searching in the Wave and List Windows

Figure 11-10. Expression Builder Dialog

The Expression Builder dialog box provides an array of buttons that help you build a GUI expression. For instance, rather than typing in a signal name, you can select the signal in the associated Wave or List window and press Insert Selected Signal. All Expression Builder buttons correspond to the Expression Syntax.

Saving an Expression to a Tcl Variable

Clicking the Save button will save the expression to a Tcl variable. Once saved this variable can be used in place of the expression. For example, say you save an expression to the variable "foo". Here are some operations you could do with the saved variable: Read the value of foo with the set command:
set foo

Put $foo in the Expression: entry box for the Search for Expression selection. Issue a searchlog command using foo:
searchlog -expr $foo 0

Searching for when a Signal Reaches a Particular Value

Select the signal in the Wave window and click Insert Selected Signal and ==. Then, click the value buttons or type a value.

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Evaluating Only on Clock Edges

Click the && button to AND this condition with the rest of the expression. Then select the clock in the Wave window and click Insert Selected Signal and rising. You can also select the falling edge or both edges.

Operators
Other buttons will add operators of various kinds (see Expression Syntax), or you can type them in.

Formatting the Wave Window

Setting Wave Window Display Preferences
You can set Wave Window display preferences by selecting Tools > Options > Wave Preferences (when the window is docked in the MDI frame) or Tools > Window Preferences (when the window is undocked). These commands open the Wave Window Preferences dialog (Figure 11-11).

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Waveform Analysis Formatting the Wave Window

Figure 11-11. Display Tab of the Wave Window Preferences Dialog

Hiding/Showing Path Hierarchy

You can set how many elements of the object path display by changing the Display Signal Path value in the Wave Window Preferences dialog (Figure 11-11). Zero indicates the full path while a non-zero number indicates the number of path elements to be displayed.

Setting the Timeline to Count Clock Cycles

You can set the timeline of the Wave window to count clock cycles rather than elapsed time. If the Wave window is docked in the MDI frame, open the Wave Window Preferences dialog by selecting Tools > Options > Wave Preferences from the Main window menus. If the Wave window is undocked, select Tools > Window Preferences from the Wave window menus. This opens the Wave Window Preferences dialog. In the dialog, select the Grid & Timeline tab (Figure 11-12).

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Waveform Analysis Formatting the Wave Window

Figure 11-12. Grid & Timeline Tab of Wave Window Preferences Dialog

Enter the period of your clock in the Grid Period field and select Display grid period count (cycle count). The timeline will now show the number of clock cycles, as shown in Figure 11-13. Figure 11-13. Clock Cycles in Timeline of Wave Window

Formatting Objects in the Wave Window

You can adjust various object properties to create the view you find most useful. Select one or more objects and then select View > Properties or use the selections in the Format menu.

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Waveform Analysis Formatting the Wave Window

Changing Radix (base) for the Wave Window

One common adjustment is changing the radix (base) of an object. When you select View > Properties, the Wave Signal Properties dialog appears. Figure 11-14. Changing Signal Radix

The default radix is symbolic, which means that for an enumerated type, the value pane lists the actual values of the enumerated type of that object. For the other radixes - binary, octal, decimal, unsigned, hexadecimal, or ASCII - the object value is converted to an appropriate representation in that radix. Note When the symbolic radix is chosen for SystemVerilog reg and integer types, the values are treated as binary. When the symbolic radix is chosen for SystemVerilog bit and int types, the values are considered to be decimal. Aside from the Wave Signal Properties dialog, there are three other ways to change the radix: Change the default radix for the current simulation using Simulate > Runtime Options (Main window) Change the default radix for the current simulation using the radix command. Change the default radix permanently by editing the DefaultRadix variable in the modelsim.ini file.

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Waveform Analysis Formatting the Wave Window

Dividing the Wave Window

Dividers serve as a visual aid for debugging, allowing you to separate signals and waveforms for easier viewing. In the graphic below, a bus is separated from the two signals above it with a divider called "Bus." Figure 11-15. Separate Signals with Wave Window Dividers

To insert a divider, follow these steps: 1. Select the signal above which you want to place the divider. 2. If the Wave pane is docked in MDI frame of the Main window, select Add > Wave > Divider from the Main window menu bar. If the Wave window stands alone, undocked from the Main window, select Add > Divider from the Wave window menu bar. 3. Specify the divider name in the Wave Divider Properties dialog. The default name is New Divider. Unnamed dividers are permitted. Simply delete "New Divider" in the Divider Name field to create an unnamed divider. 4. Specify the divider height (default height is 17 pixels) and then click OK. You can also insert dividers with the -divider argument to the add wave command.

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Waveform Analysis Formatting the Wave Window

Working with Dividers

The table below summarizes several actions you can take with dividers: Table 11-4. Actions for Dividers Action Move a divider Method Click-and-drag the divider to the desired location

Change a dividers Right-click the divider and select Divider Properties name or size Delete a divider Right-click the divider and select Delete

Splitting Wave Window Panes

The pathnames, values, and waveforms panes of the Wave window display can be split to accommodate signals from one or more datasets. For more information on viewing multiple simulations, see WLF Files (Datasets) and Virtuals. To split the window, select Add > Window Pane. In the illustration below, the top split shows the current active simulation with the prefix "sim," and the bottom split shows a second dataset with the prefix "gold".

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Waveform Analysis Wave Groups

Figure 11-16. Splitting Wave Window Panes

The Active Split

The active split is denoted with a solid white bar to the left of the signal names. The active split becomes the target for objects added to the Wave window.

Wave Groups
Wave groups are a wave window specific container object for creating arbitrary groups of items. A wave group may contain 0, 1 or many items. The command line as well as drag and drop may be used to add or remove items from a group. Groups themselves may be dragged around the wave window or to another wave window. Currently, groups may not be nested.

Creating a Wave Group

There are two ways to create a wave group. 1. Use the Tools > Group menu selection.
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Waveform Analysis Wave Groups

a. Select a set of signals in the wave window. b. Select the Tools > Group menu item. The Wave Group Create dialog will appear. Figure 11-17. Fill in the name of the group in the Group Name field.

c. Click Ok. The new wave group will be denoted by a red diamond in the Wave window pathnames. Figure 11-18. Wave groups denoted by red diamond

2. Use the -group argument to the add wave command. Example 1 The following command will create a group named mygroup containing three items:
add wave -group mygroup sig1 sig2 sig3

Example 2 The following command will create an empty group named mygroup:
add wave -group mygroup

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Waveform Analysis Wave Groups

Deleting or Ungrouping a Wave Group

If a wave group is selected and cut or deleted the entire group and all its contents will be removed from the wave window. Likewise, the delete wave command will remove the entire group if the group name is specified. If a wave group is selected and the Tools > Ungroup menu item is selected the group will be removed and all of its contents will remain in the Wave window in existing order.

Adding Items to an Existing Wave Group

There are three ways to add items to an existing wave group. 1. Using the drag and drop capability to move items outside of the group or from other windows within ModelSim into the group. The insertion indicator will show the position the item will be dropped into the group. If the cursor is moved over the lower portion of the group item name a box will be drawn around the group name indicating the item will be dropped into the last position in the group. 2. The cut/copy/paste functions may be used to paste items into a group. 3. Use the add wave -group command. The following example adds two more signals to an existing group called mygroup.
add wave -group mygroup sig4 sig5

Removing Items from an Existing Wave Group

You can use any of the following methods to remove an item from a wave group. 1. Use the drag and drop capability to move an item outside of the group. 2. Use menu or icon selections to cut or delete an item or items from the group. 3. Use the delete wave command to specify a signal to be removed from the group. Note The delete wave command removes all occurrences of a specified name from the wave window, not just an occurrence within a group.

Miscellaneous Wave Group Features

Dragging a wave group from the Wave window to the List window will result in all of the items within the group being added to the List window.

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Waveform Analysis Formatting the List Window

Dragging a group from the Wave window to the Transcript window will result in a list of all of the items within the group being added to the existing command line, if any.

Formatting the List Window

Setting List Window Display Properties
Before you add objects to the List window, you can set the windows display properties. To change when and how a signal is displayed in the List window, select Tools > List Preferences from the List window menu bar (when the window is undocked). Figure 11-19. Modifying List Window Display Properties

Formatting Objects in the List Window

You can adjust various properties of objects to create the view you find most useful. Select one or more objects and then select View > Signal Properties from the List window menu bar (when the window is undocked).

Changing Radix (base) for the List Window

One common adjustment is changing the radix (base) of an object. When you select View > Signal Properties, the List Signal Properties dialog appears (Figure 11-20).

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Waveform Analysis Formatting the List Window

Figure 11-20. List Signal Properties Dialog

The default radix is symbolic, which means that for an enumerated type, the window lists the actual values of the enumerated type of that object. For the other radixes - binary, octal, decimal, unsigned, hexadecimal, or ASCII - the object value is converted to an appropriate representation in that radix. Changing the radix can make it easier to view information in the List window. Compare the image below (with decimal values) with the image in the section List Window Overview (with symbolic values).

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Waveform Analysis Saving the Window Format

Figure 11-21. Changing the Radix in the List Window

Aside from the List Signal Properties dialog, there are three other ways to change the radix: Change the default radix for the current simulation using Simulate > Runtime Options (Main window) Change the default radix for the current simulation using the radix command. Change the default radix permanently by editing the DefaultRadix variable in the modelsim.ini file.

Saving the Window Format

By default all Wave and List window information is forgotten once you close the windows. If you want to restore the windows to a previously configured layout, you must save a window format file. Follow these steps: 1. Add the objects you want to the Wave or List window. 2. Edit and format the objects to create the view you want. 3. Save the format to a file by selecting File > Save > Format. To use the format file, start with a blank Wave or List window and run the DO file in one of two ways: Invoke the do command from the command line:
VSIM> do <my_format_file>

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Waveform Analysis Printing and Saving Waveforms in the Wave window

Select File > Load. Note Window format files are design-specific. Use them only with the design you were simulating when they were created.

Printing and Saving Waveforms in the Wave window

You can print the waveform display or save it as an encapsulated postscript (EPS) file.

Saving a .eps Waveform File and Printing in UNIX

Select File > Print Postscript (Wave window) to print all or part of the waveform in the current Wave window in UNIX, or save the waveform as a .eps file on any platform (see also the write wave command).

Printing from the Wave Window on Windows Platforms

Select File > Print (Wave window) to print all or part of the waveform in the current Wave window, or save the waveform as a printer file (a Postscript file for Postscript printers).

Printer Page Setup

Select File > Page setup or click the Setup button in the Write Postscript or Print dialog box to define how the printed page will appear.

Saving List Window Data to a File

Select File > Write List in the List window to save the data in one of these formats: Tabular writes a text file that looks like the window listing
ns 0 0 2 delta +0 +1 +0 /a X 0 0 /b X 1 1 /cin U 0 0 /sum X X X /cout U U U

Events writes a text file containing transitions during simulation

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Waveform Analysis Combining Objects into Buses @0 +0 /a X /b X /cin U /sum X /cout U @0 +1 /a 0 /b 1 /cin 0

TSSI writes a file in standard TSSI format; see also, the write tssi command.
0 00000000000000010????????? 2 00000000000000010???????1? 3 00000000000000010??????010 4 00000000000000010000000010 100 00000001000000010000000010

You can also save List window output using the write list command.

Combining Objects into Buses

You can combine signals in the Wave or List window into buses. A bus is a collection of signals concatenated in a specific order to create a new virtual signal with a specific value. A virtual compare signal (the result of a comparison simulation) is not supported for combination with any other signal. To combine signals into a bus, use one of the following methods: Select two or more signals in the Wave or List window and then choose Tools > Combine Signals from the menu bar. A virtual signal that is the result of a comparison simulation is not supported for combining with any other signal. Use the virtual signal command at the Main window command prompt.

In the illustration below, three signals have been combined to form a new bus called "Bus1". Note that the component signals are listed in the order in which they were selected in the Wave window. Also note that the value of the bus is made up of the values of its component signals, arranged in a specific order.

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Waveform Analysis Combining Objects into Buses

Figure 11-22. Signals Combined to Create Virtual Bus

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Waveform Analysis Configuring New Line Triggering in the List Window

Configuring New Line Triggering in the List Window

New line triggering refers to what events cause a new line of data to be added to the List window. By default ModelSim adds a new line for any signal change including deltas within a single unit of time resolution. You can set new line triggering on a signal-by-signal basis or for the whole simulation. To set for a single signal, select View > Signal Properties from the List window menu bar (when the window is undocked) and select the Triggers line setting. Individual signal settings override global settings. Figure 11-23. Line Triggering in the List Window

To modify new line triggering for the whole simulation, select Tools > List Preferences from the List window menu bar (when the window is undocked), or use the configure command. When you select Tools > List Preferences, the Modify Display Properties dialog appears:

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Waveform Analysis Configuring New Line Triggering in the List Window

Figure 11-24. Setting Trigger Properties

The following table summaries the triggering options: Table 11-5. Triggering Options Option Deltas Description Choose between displaying all deltas (Expand Deltas), displaying the value at the final delta (Collapse Delta). You can also hide the delta column all together (No Delta), however this will display the value at the final delta. Specify an interval at which you want to trigger data display Use a gating expression to control triggering; see Using Gating Expressions to Control Triggering for more details

Strobe trigger Trigger gating

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Waveform Analysis Configuring New Line Triggering in the List Window

Using Gating Expressions to Control Triggering

Trigger gating controls the display of data based on an expression. Triggering is enabled once the gating expression evaluates to true. This setup behaves much like a hardware signal analyzer that starts recording data on a specified setup of address bits and clock edges. Here are some points about gating expressions: Gating expressions affect the display of data but not acquisition of the data. The expression is evaluated when the List window would normally have displayed a row of data (given the other trigger settings). The duration determines for how long triggering stays enabled after the gating expression returns to false (0). The default of 0 duration will enable triggering only while the expression is true (1). The duration is expressed in x number of default timescale units. Gating is level-sensitive rather than edge-triggered.

Trigger Gating Example Using the Expression Builder

This example shows how to create a gating expression with the ModelSim Expression Builder. Here is the procedure: 1. Select Tools > Window Preferences from the List window menu bar (when the window is undocked) and select the Triggers tab. 2. Click the Use Expression Builder button.

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Figure 11-25. Trigger Gating Using Expression Builder

3. Select the signal in the List window that you want to be the enable signal by clicking on its name in the header area of the List window. 4. Click Insert Selected Signal and then 'rising in the Expression Builder. 5. Click OK to close the Expression Builder. You should see the name of the signal plus "'rising" added to the Expression entry box of the Modify Display Properties dialog box. 6. Click OK to close the dialog. If you already have simulation data in the List window, the display should immediately switch to showing only those cycles for which the gating signal is rising. If that isn't quite what you want, you can go back to the expression builder and play with it until you get it the way you want it. If you want the enable signal to work like a "One-Shot" that would display all values for the next, say 10 ns, after the rising edge of enable, then set the On Duration value to 10 ns.

Trigger Gating Example Using Commands

The following commands show the gating portion of a trigger configuration statement:
configure list -usegating 1 configure list -gateduration 100 configure list -gateexpr {/test_delta/iom_dd'rising}

See the configure command for more details.

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Waveform Analysis Miscellaneous Tasks

Sampling Signals at a Clock Change

You easily can sample signals at a clock change using the add list command with the -notrigger argument. The -notrigger argument disables triggering the display on the specified signals. For example:
add list clk -notrigger a b c

When you run the simulation, List window entries for clk, a, b, and c appear only when clk changes. If you want to display on rising edges only, you have two options: 1. Turn off the List window triggering on the clock signal, and then define a repeating strobe for the List window. 2. Define a "gating expression" for the List window that requires the clock to be in a specified state. See above.

Miscellaneous Tasks
Examining Waveform Values
You can use your mouse to display a dialog that shows the value of a waveform at a particular time. You can do this two ways: Rest your mouse pointer on a waveform. After a short delay, a dialog will pop-up that displays the value for the time at which your mouse pointer is positioned. If youd prefer that this popup not display, it can be toggled off in the display properties. See Setting Wave Window Display Preferences. Right-click a waveform and select Examine. A dialog displays the value for the time at which you clicked your mouse. This method works in the List window as well.

Displaying Drivers of the Selected Waveform

You can automatically display in the Dataflow window the drivers of a signal selected in the Wave window. You can do this three ways: Select a waveform and click the Show Drivers button on the toolbar. Select a waveform and select Show Drivers from the shortcut menu Double-click a waveform edge (you can enable/disable this option in the display properties dialog; see Setting Wave Window Display Preferences)

This operation opens the Dataflow window and displays the drivers of the signal selected in the Wave window. The Wave pane in the Dataflow window also opens to show the selected signal
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with a cursor at the selected time. The Dataflow window shows the signal(s) values at the current cursor position.

Sorting a Group of Objects in the Wave Window

Select View > Sort to sort the objects in the pathname and values panes.

Creating and managing breakpoints

ModelSim supports both signal (i.e., when conditions) and file-line breakpoints. Breakpoints can be set from multiple locations in the GUI or from the command line. Breakpoints within SystemC portions of the design can only be set using File-line breakpoints.

Signal breakpoints
Signal breakpoints (when conditions) instruct ModelSim to perform actions when the specified conditions are met. For example, you can break on a signal value or at a specific simulator time (see the when command for additional details). When a breakpoint is hit, a message in the Main window transcript identifies the signal that caused the breakpoint.

Setting signal breakpoints from the command line

You use the when command to set a signal breakpoint from the VSIM> prompt.

Setting signal breakpoints from the GUI

Signal breakpoints are most easily set in the Objects Pane and the Wave Window Overview. Right-click a signal and select Insert Breakpoint from the context menu. A breakpoint is set on that signal and will be listed in the Breakpoints dialog.

File-line breakpoints
File-line breakpoints are set on executable lines in your source files. When the line is hit, the simulator stops and the Source window opens to show the line with the breakpoint. You can change this behavior by editing the PrefSource(OpenOnBreak) variable. See Simulator GUI Preferences for details on setting preference variables. Since C Debug is invoked when you set a breakpoint within a SystemC module, your C Debug settings must be in place prior to setting a breakpoint. See Setting Up C Debug for more information. Once invoked, C Debug can be exited using the C Debug menu.

Setting file-line breakpoints from the command line

You use the bp command to set a file-line breakpoint from the VSIM> prompt.
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Setting file-line breakpoints from the GUI

File-line breakpoints are most easily set using your mouse in the Source Window. Click on a blue line number at the left side of the Source window, and a red diamond denoting a breakpoint will appear. The breakpoints are toggles click once to create the colored diamond; click again to disable or enable the breakpoint. To delete the breakpoint completely, click the red diamond with your right mouse button, and select Remove Breakpoint.

Waveform Compare
The ModelSim Waveform Compare feature allows you to compare simulation runs. Differences encountered in the comparison are summarized and listed in the Main window transcript and are shown in the Wave and List windows. In addition, you can write a list of the differences to a file using the compare info command. Note The Waveform Compare feature is available as an add-on to the PE or LE versions. Contact Mentor Graphics sales for more information. The basic steps for running a comparison are as follows: 1. Run one simulation and save the dataset. For more information on saving datasets, see Saving a Simulation to a WLF File. 2. Run a second simulation. 3. Setup and run a comparison. 4. Analyze the differences in the Wave or List window.

Mixed-Language Waveform Compare Support

Mixed-language compares are supported as listed in the following table: Table 11-6. Mixed-Language Waveform Compares Language C/C++ types Compares bool, char, unsigned char short, unsigned short int, unsigned int long, unsigned long sc_bit, sc_bv, sc_logic, sc_lv sc_int, sc_uint sc_bigint, sc_biguint sc_signed, sc_unsigned

SystemC types

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Table 11-6. Mixed-Language Waveform Compares (cont.) Language Verilog types Compares net, reg

The number of elements must match for vectors; specific indexes are ignored.

Three Options for Setting up a Comparison

There are three options for setting up a comparison: Comparison Wizard A series of dialogs that "walk" you through the process Comparison commands Use a series of compare commands GUI Use various dialogs to "manually" configure the comparison

Comparison Wizard
The simplest method for setting up a comparison is using the Wizard. The wizard is a series of dialogs that walks you through the process. To start the Wizard, select Tools > Waveform Compare > Comparison Wizard from either the Wave or Main window. The graphic below shows the first dialog in the Wizard. As you can see from this example, the dialogs include instructions on the left-hand side. Figure 11-26. Waveform Comparison Wizard

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Comparison Graphic Interface

You can also set up a comparison via the GUI without using the Wizard. The steps of this process are described further in Setting Up a Comparison with the GUI.

Comparison Commands
There are numerous commands that give you complete control over a comparison. These commands can be entered in the Main window transcript or run via a DO file. The commands are detailed in the Reference Manual, but the following example shows the basic sequence:
compare start gold vsim compare add /* compare run

This example command sequence assumes that the gold.wlf reference dataset is loaded with the current simulation, the vsim.wlf dataset. The compare start command instructs ModelSim to compare the reference gold.wlf dataset against the current simulation. The compare add /* command instructs ModelSim to compare all signals in the gold.wlf reference dataset against all signals in the vsim.wlf dataset. The compare run command runs the comparison.

Comparing Signals with Different Names

You can use the compare add command to specify a comparison between two signals with different names.

Setting Up a Comparison with the GUI

To setup a comparison with the GUI, follow these steps: 1. Initiate the comparison by specifying the reference and test datasets. See Starting a Waveform Comparison for details. 2. Add objects to the comparison. See Adding Signals, Regions, and Clocks for details. 3. Specify the comparison method. See Specifying the Comparison Method for details. 4. Configure comparison options. See Setting Compare Options for details. 5. Run the comparison by selecting Tools > Waveform Compare > Run Comparison. 6. View the results. See Viewing Differences in the Wave Window, Viewing Differences in the List Window, and Viewing Differences in Textual Formatfor details. Waveform Compare is initiated from either the Main or Wave window by selecting Tools >Waveform Compare > Start Comparison.

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Starting a Waveform Comparison

Select Tools >Waveform Compare > Start Comparison to initiate the comparison. The Start Comparison dialog box allows you define the Reference and Test datasets. Figure 11-27. Start Comparison Dialog

Reference Dataset
The Reference Dataset is the .wlf file to which the test dataset will be compared. It can be a saved dataset, the current simulation dataset, or any part of the current simulation dataset.

Test Dataset
The Test Dataset is the .wlf file that will be compared against the Reference Dataset. Like the Reference Dataset, it can be a saved dataset, the current simulation dataset, or any part of the current simulation dataset. Once you click OK in the Start Comparison dialog box, ModelSim adds a Compare tab to the Main window.

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Figure 11-28. Compare Tab in the Workspace Pane

After adding the signals, regions, and/or clocks you want to use in the comparison (see Adding Signals, Regions, and Clocks), you will be able to drag compare objects from this tab into the Wave and List windows.

Adding Signals, Regions, and Clocks

To designate the signals, regions, or clocks to be used in the comparison, click Tools > Waveform Compare > Add.

Adding Signals
Clicking Tools > Waveform Compare > Add > Compare by Signal in the Wave window opens the structure_browser window, where you can specify signals to be used in the comparison.

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Figure 11-29. Structure Browser

Adding Regions
Rather than comparing individual signals, you can also compare entire regions of your design. Select Tools > Waveform Compare > Add > Compare by Region to open the Add Comparison by Region dialog. Figure 11-30. Add Comparison by Region Dialog

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Adding Clocks
You add clocks when you want to perform a clocked comparison. See Specifying the Comparison Method for details.

Specifying the Comparison Method

The Waveform Compare feature provides two comparison methods: Continuous comparison Test signals are compared to reference signals at each transition of the reference. Timing differences between the test and reference signals are shown with rectangular red markers in the Wave window and yellow markers in the List window. Clocked comparisons Signals are compared only at or just after an edge on some signal. In this mode, you define one or more clocks. The test signal is compared to a reference signal and both are sampled relative to the defined clock. The clock can be defined as the rising or falling edge (or either edge) of a particular signal plus a userspecified delay. The design need not have any events occurring at the specified clock time. Differences between test signals and the clock are highlighted with red diamonds in the Wave window.

To specify the comparison method, select Tools > Waveform Compare > Options and select the Comparison Method tab. Figure 11-31. Comparison Methods Tab

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Continuous Comparison
Continuous comparisons are the default. You have the option of specifying leading and trailing tolerances and a when expression that must evaluate to "true" or 1 at the signal edge for the comparison to become effective.

Clocked Comparison
To specify a clocked comparison you must define a clock in the Add Clock dialog. You can access this dialog via the Clocks button in the Comparison Method tab or by selecting Tools > Waveform Compare > Add > Clocks. Figure 11-32. Adding a Clock for a Clocked Comparison

Setting Compare Options

There are a few "global" options that you can set for a comparison. Select Tools > Waveform Compare > Options.

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Figure 11-33. Waveform Comparison Options

Options in this dialog include setting the maximum number of differences allowed before the comparison terminates, specifying signal value matching rules, and saving or resetting the defaults.

Viewing Differences in the Wave Window

The Wave window provides a graphic display of comparison results. Pathnames of all test signals included in the comparison are denoted by yellow triangles. Test signals that contain timing differences when compared with the reference signals are denoted by a red X over the yellow triangle.

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Figure 11-34. Viewing Waveform Differences in the Wave Window

The names of the comparison objects take the form:

<path>/\refSignalName<>testSignalName\

If you compare two signals from different regions, the signal names include the uncommon part of the path. In comparisons of signals with multiple bits, you can display them in "buswise" or "bitwise" format. Buswise format lists the busses under the compare object whereas bitwise format lists each individual bit under the compare object. To select one format or the other, click your right mouse button on the plus sign (+) next to a compare object. Timing differences are also indicated by red bars in the vertical and horizontal scroll bars of the waveform display, and by red difference markers on the waveforms themselves. Rectangular difference markers denote continuous differences. Diamond difference markers denote clocked differences. Placing your mouse cursor over any difference marker will initiate a popup display that provides timing details for that difference.

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Figure 11-35. Waveform Difference Details and Markers

The values column of the Wave window displays the words "match" or "diff" for every test signal, depending on the location of the selected cursor. "Match" indicates that the value of the test signal matches the value of the reference signal at the time of the selected cursor. "Diff" indicates a difference between the test and reference signal values at the selected cursor.

Annotating Differences
You can tag differences with textual notes that are included in the difference details popup and comparison reports. Click a difference with the right mouse button, and select Annotate Diff. Or, use the compare annotate command.

Compare Icons
The Wave window includes six comparison icons that let you quickly jump between differences. From left to right, the icons do the following: find first difference, find previous annotated difference, find previous difference, find next difference, find next annotated difference, find last difference. Use these icons to move the selected cursor. These buttons cycle through differences on all signals. To view differences for just the selected signal, press <tab> and <shift - tab> on your keyboard. Note If you have differences on individual bits of a bus, the compare icons will stop on those differences but <tab> and <shift - tab> will not.

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The compare icons cycle through comparison objects in all open Wave windows. If you have two Wave windows displayed, each containing different comparison objects, the compare icons will cycle through the differences displayed in both windows.

Viewing Differences in the List Window

Compare objects can be displayed in the List window too. Differences are highlighted with a yellow background. Tabbing on selected columns moves the selection to the next difference (actually difference edge). Shift-tabbing moves the selection backwards. Figure 11-36. Waveform Differences in the List Window

Right-clicking on a yellow-highlighted difference gives you three options: Diff Info, Annotate Diff, and Ignore/Noignore diff. With these options you can elect to display difference information, you can ignore selected differences or turn off ignore, and you can annotate individual differences.

Viewing Differences in Textual Format

You can also view text output of the differences either in the Transcript pane of the Main window or in a saved file. To view them in the transcript, select Tools > Waveform Compare > Differences > Show. To save them to a text file, select Tools > Waveform Compare > Differences > Write Report.

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Saving and Reloading Comparison Results

To save comparison results for future use, you must save both the comparison setup rules and the comparison differences. To save the rules, select Tools > Waveform Compare > Rules > Save. This file will contain all rules for reproducing the comparison. The default file name is "compare.rul." To save the differences, select Tools > Waveform Compare > Differences > Save. The default file name is "compare.dif". To reload the comparison results at a later time, select Tools > Waveform Compare > Reload and specify the rules and difference files. Figure 11-37. Reloading and Redisplaying Compare Differences

Comparing Hierarchical and Flattened Designs

If you are comparing a hierarchical RTL design simulation against a flattened synthesized design simulation, you may have different hierarchies, different signal names, and the buses may be broken down into one-bit signals in the gate-level design. All of these differences can be handled by ModelSims Waveform Compare feature. If the test design is hierarchical but the hierarchy is different from the hierarchy of the reference design, you can use the compare add command to specify which region path in the test design corresponds to that in the reference design. If the test design is flattened and test signal names are different from reference signal names, the compare add command allows you to specify which signal in the test design will be compared to which signal in the reference design. If, in addition, buses have been dismantled, or "bit-blasted", you can use the -rebuild option of the compare add command to automatically rebuild the bus in the test design. This will allow you to look at the differences as one bus versus another.

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If signals in the RTL test design are different in type from the synthesized signals in the reference design registers versus nets, for example the Waveform Compare feature will automatically do the type conversion for you. If the type differences are too extreme (say integer versus real), Waveform Compare will let you know.

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Chapter 12 Tracing Signals with the Dataflow Window

This chapter discusses how to use the Dataflow window for tracing signal values and browsing the physical connectivity of your design.

Dataflow Window Overview

The Dataflow window allows you to explore the "physical" connectivity of your design; to trace events that propagate through the design; and to identify the cause of unexpected outputs. Note ModelSim versions operating without a dataflow license feature have limited Dataflow functionality. Without the license feature, the window displays the message Extended mode disabled and will show only one process and its attached signals or one signal and its attached processes. Contact your Mentor Graphics sales representative if you currently dont have a dataflow feature. Figure 12-1. The Dataflow Window (undocked)

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Tracing Signals with the Dataflow Window Adding Objects to the Window

Objects You Can View in the Dataflow Window

The Dataflow window displays: processes signals, nets, and registers and interconnect

The window has built-in mappings for all Verilog primitive gates (i.e., AND, OR, etc.). For components other than Verilog primitives, you can define a mapping between processes and built-in symbols. See Symbol Mapping for details. You cannot view SystemC objects in the Dataflow window; however, you can view HDL regions from mixed designs that include SystemC.

Adding Objects to the Window

You can use any of the following methods to add objects to the Dataflow window: drag and drop objects from other windows use the Navigate menu options in the Dataflow window use the add dataflow command double-click any waveform in the Wave window display

The Navigate menu offers four commands that will add objects to the window. The commands include: View region clear the window and display all signals from the current region Add region display all signals from the current region without first clearing window View all nets clear the window and display all signals from the entire design Add ports add port symbols to the port signals in the current region

When you view regions or entire nets, the window initially displays only the drivers of the added objects in order to reduce clutter. You can easily view readers by selecting an object and invoking Navigate > Expand net to readers. A small circle above an input signal on a block denotes a trigger signal that is on the process sensitivity list.

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Links to Other Windows

The Dataflow window has links to other windows as described below: Table 12-1. Dataflow Window Links to Other Windows and Panes Window Main Window Link select a signal or process in the Dataflow window, and the structure tab updates if that object is in a different design unit select a process in either window, and that process is highlighted in the other select a design object in either window, and that object is highlighted in the other trace through the design in the Dataflow window, and the associated signals are added to the Wave window move a cursor in the Wave window, and the values update in the Dataflow window select an object in the Dataflow window, and the Source window updates if that object is in a different source file

Active Processes Pane Objects Pane Wave Window

Source Window

Exploring the Connectivity of the Design

A primary use of the Dataflow window is exploring the "physical" connectivity of your design. One way of doing this is by expanding the view from process to process. This allows you to see the drivers/receivers of a particular signal, net, or register. You can expand the view of your design using menu commands or your mouse. To expand with the mouse, simply double click a signal, register, or process. Depending on the specific object you click, the view will expand to show the driving process and interconnect, the reading process and interconnect, or both. Alternatively, you can select a signal, register, or net, and use one of the toolbar buttons or menu commands described in Table 12-2: Table 12-2. Icon and Menu Selections for Exploring Design Connectivity Navigate > Expand net to drivers Expand net to all drivers display driver(s) of the selected signal, net, or register

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Table 12-2. Icon and Menu Selections for Exploring Design Connectivity Expand net to all drivers and readers display driver(s) and reader(s) of the selected signal, net, or register Expand net to all readers display reader(s) of the selected signal, net, or register Navigate > Expand net

Navigate > Expand net to readers

As you expand the view, note that the "layout" of the design may adjust to best show the connectivity. For example, the location of an input signal may shift from the bottom to the top of a process.

Tracking Your Path Through the Design

You can quickly traverse through many components in your design. To help mark your path, the objects that you have expanded are highlighted in green. Figure 12-2. Green Highlighting Shows Your Path Through the Design

You can clear this highlighting using the Edit > Erase highlight command or by clicking the Erase highlight icon in the toolbar.

The Embedded Wave Viewer

Another way of exploring your design is to use the Dataflow windows embedded wave viewer. This viewer closely resembles, in appearance and operation, the stand-alone Wave window (see Waveform Analysis for more information). The wave viewer is opened using the View > Show Wave command or by clicking the Show Wave icon. One common scenario is to place signals in the wave viewer and the Dataflow panes, run the design for some amount of time, and then use time cursors to investigate value changes. In other words, as you place and move cursors in the wave viewer pane (see Measuring Time with Cursors in the Wave Window for details), the signal values update in the Dataflow pane.

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Tracing Signals with the Dataflow Window Zooming and Panning

Figure 12-3. Wave Viewer Displays Inputs and Outputs of Selected Process

Another scenario is to select a process in the Dataflow pane, which automatically adds to the wave viewer pane all signals attached to the process. See Tracing Events (Causality) for another example of using the embedded wave viewer.

Zooming and Panning

The Dataflow window offers several tools for zooming and panning the display.
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These zoom buttons are available on the toolbar: Zoom In zoom in by a factor of two from the current view Zoom Out zoom out by a factor of two from current view Zoom Full zoom out to view the entire schematic

To zoom with the mouse, you can either use the middle mouse button or enter Zoom Mode by selecting View > Zoom and then use the left mouse button. Four zoom options are possible by clicking and dragging in different directions: Down-Right: Zoom Area (In) Up-Right: Zoom Out (zoom amount is displayed at the mouse cursor) Down-Left: Zoom Selected Up-Left: Zoom Full

The zoom amount is displayed at the mouse cursor. A zoom operation must be more than 10 pixels to activate.

Panning with the Mouse

You can pan with the mouse in two ways: 1) enter Pan Mode by selecting View > Pan and then drag with the left mouse button to move the design; 2) hold down the <Ctrl> key and drag with the middle mouse button to move the design.

Tracing Events (Causality)

One of the most useful features of the Dataflow window is tracing an event to see the cause of an unexpected output. This feature uses the Dataflow windows embedded wave viewer (see The Embedded Wave Viewer for more details). In short you identify an output of interest in the Dataflow pane and then use time cursors in the wave viewer pane to identify events that contribute to the output. The process for tracing events is as follows: 1. Log all signals before starting the simulation (add log -r /*). 2. After running a simulation for some period of time, open the Dataflow window and the wave viewer pane. 3. Add a process or signal of interest into the Dataflow window (if adding a signal, find its driving process). Select the process and all signals attached to the selected process will appear in the wave viewer pane.
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Tracing Signals with the Dataflow Window Tracing the Source of an Unknown State (StX)

4. Place a time cursor on an edge of interest; the edge should be on a signal that is an output of the process. 5. Select Trace > Trace input net to event. A second cursor is added at the most recent input event. 6. Keep selecting Trace > Trace next event until you've reached an input event of interest. Note that the signals with the events are selected in the wave pane. 7. Now select Trace > Trace Set. The Dataflow display "jumps" to the source of the selected input event(s). The operation follows all signals selected in the wave viewer pane. You can change which signals are followed by changing the selection. 8. To continue tracing, go back to step 5 and repeat. If you want to start over at the originally selected output, select Trace > Trace event reset.

Tracing the Source of an Unknown State (StX)

Another useful Dataflow window debugging tool is the ability to trace an unknown state (StX) back to its source. Unknown values are indicated by red lines in the Wave window (Figure 12-4) and in the wave viewer of the Dataflow window. Figure 12-4. Unknown States Shown as Red Lines in Wave Window

The procedure for tracing to the source of an unknown state in the Dataflow window is as follows: 1. Load your design.
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Tracing Signals with the Dataflow Window Finding Objects by Name in the Dataflow Window

2. Log all signals in the design or any signals that may possibly contribute to the unknown value (log -r /* will log all signals in the design). 3. Add signals to the Wave window or wave viewer pane, and run your design the desired length of time. 4. Put a Wave window cursor on the time at which the signal value is unknown (StX). In Figure 12-4, Cursor 1 at time 2305 shows an unknown state on signal t_out. 5. Add the signal of interest to the Dataflow window by doing one of the following:
o o

double-clicking on the signals waveform in the Wave window, right-clicking the signal in the Objects window and selecting Add to Dataflow > Selected Signals from the popup menu, selecting the signal in the Objects window and selecting Add > Dataflow > Selected Signals from the menu bar.

6. In the Dataflow window, make sure the signal of interest is selected. 7. Trace to the source of the unknown by doing one of the following:
o

If the Dataflow window is docked, select Tools > Trace > TraceX, Tools > Trace > TraceX Delay, Tools > Trace > ChaseX, or Tools > Trace > ChaseX Delay. If the Dataflow window is undocked, select Trace > TraceX, Trace > TraceX Delay, Trace > ChaseX, or Trace > ChaseX Delay. These commands behave as follows: TraceX / TraceX Delay Steps back to the last driver of an X value. TraceX Delay works similarly but it steps back in time to the last driver of an X value. TraceX should be used for RTL designs; TraceX Delay should be used for gatelevel netlists with back annotated delays. ChaseX / ChaseX Delay "Jumps" through a design from output to input, following X values. ChaseX Delay acts the same as ChaseX but also moves backwards in time to the point where the output value transitions to X. ChaseX should be used for RTL designs; ChaseX Delay should be used for gate-level netlists with back annotated delays.

Finding Objects by Name in the Dataflow Window

Select Edit > Find from the menu bar, or click the Find icon in the toolbar, to search for signal, net, or register names or an instance of a component. This opens the Find in Dataflow dialog (Figure 12-5).

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Figure 12-5. Find in Dataflow Dialog

With the Find in Dataflow dialog you can limit the search by type to instances or signals. You select Exact to find an item that exactly matches the entry youve typed in the Find field. The Match case selection will enforce case-sensitive matching of your entry. And the Zoom to selection will zoom in to the item in Find field. The Find All button allows you to find and highlight all occurrences of the item in the Find field. If Zoom to is checked, the view will change such that all selected items are viewable. If Zoom to is not selected, then no change is made to zoom or scroll state.

Printing and Saving the Display

Saving a .eps File and Printing the Dataflow Display from UNIX
Select File > Print Postscript to setup and print the Dataflow display in UNIX, or save the waveform as a .eps file on any platform.

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Figure 12-6. The Print Postscript Dialog

Printing from the Dataflow Display on Windows Platforms

Select File > Print to print the Dataflow display or to save the display to a file. Figure 12-7. The Print Dialog

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Tracing Signals with the Dataflow Window Configuring Page Setup

Configuring Page Setup

Clicking the Setup button in the Print Postscript or Print dialog box allows you to configure page view, highlight, color mode, orientation, and paper options (this is the same dialog that opens via File > Page setup). Figure 12-8. The Dataflow Page Setup Dialog

Symbol Mapping
The Dataflow window has built-in mappings for all Verilog primitive gates (i.e., AND, OR, etc.). For components other than Verilog primitives, you can define a mapping between processes and built-in symbols. This is done through a file containing name pairs, one per line, where the first name is the concatenation of the design unit and process names, (DUname.Processname), and the second name is the name of a built-in symbol. For example:
xorg(only).p1 XOR org(only).p1 OR andg(only).p1 AND

Entities and modules are mapped the same way:

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Tracing Signals with the Dataflow Window Symbol Mapping AND1 AND AND2 AND # A 2-input and gate AND3 AND AND4 AND AND5 AND AND6 AND xnor(test) XNOR

Note that for primitive gate symbols, pin mapping is automatic. The Dataflow window looks in the current working directory and inside each library referenced by the design for the file dataflow.bsm (.bsm stands for "Built-in Symbol Map"). It will read all files found.

User-defined symbols
You can also define your own symbols using an ASCII symbol library file format for defining symbol shapes. This capability is delivered via Concept Engineerings NlviewTM widget Symlib format. For more specific details on this widget, see
www.model.com/support/documentation/BOOK/nlviewSymlib.pdf.

The Dataflow window will search the current working directory, and inside each library referenced by the design, for the file dataflow.sym. Any and all files found will be given to the Nlview widget to use for symbol lookups. Again, as with the built-in symbols, the DU name and optional process name is used for the symbol lookup. Here's an example of a symbol for a full adder:
symbol adder(structural) * DEF \ port a in -loc -12 -15 0 -15 \ pinattrdsp @name -cl 2 -15 8 \ port b in -loc -12 15 0 15 \ pinattrdsp @name -cl 2 15 8 \ port cin in -loc 20 -40 20 -28 \ pinattrdsp @name -uc 19 -26 8 \ port cout out -loc 20 40 20 28 \ pinattrdsp @name -lc 19 26 8 \ port sum out -loc 63 0 51 0 \ pinattrdsp @name -cr 49 0 8 \ path 10 0 0 7 \ path 0 7 0 35 \ path 0 35 51 17 \ path 51 17 51 -17 \ path 51 -17 0 -35 \ path 0 -35 0 -7 \ path 0 -7 10 0

Port mapping is done by name for these symbols, so the port names in the symbol definition must match the port names of the Entity|Module|Process (in the case of the process, its the signal names that the process reads/writes).

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Tracing Signals with the Dataflow Window Configuring Window Options

Note When you create or modify a symlib file, you must generate a file index. This index is how the Nlview widget finds and extracts symbols from the file. To generate the index, select Tools > Create symlib index (Dataflow window) and specify the symlib file. The file will be rewritten with a correct, up-to-date index.

Configuring Window Options

You can configure several options that determine how the Dataflow window behaves. The settings affect only the current session. Select Tools > Options to open the Dataflow Options dialog box. Figure 12-9. Configuring Dataflow Options

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Chapter 13 Coverage
Note The functionality described in this chapter requires a coverage license feature in your ModelSim license file. Please contact your Mentor Graphics sales representative if you currently do not have such a feature. Most commands related to coverage are used in one of three modes that correspond to the type of coverage analysis required. Table 13-1. Coverage Modes Mode Type of Coverage Analysis Interactive simulation Post-process Commands

Simulation Mode

coverage, toggle, and vcover commands (such as clear, merge, report, save...) vsim -viewcov <file>.ucdb brings up separate GUI All coverage commands are available vcover utility with commands given as arguments to the invocation

Coverage View Mode

Batch Mode

Batch simulation

Each of these modes of analysis act upon a single, universal database that stores your coverage data, the Unified Coverage Database.

Unified Coverage Database

The Unified Coverage DataBase (UCDB) is a custom database for representing coverage data. Coverage data collected in the database includes: Code coverage: branch, condition, expression, statement, and toggle Finite State Machine (FSM) coverage SystemVerilog covergroup coverage SVA and PSL directive coverage Assertion data (pass, fail, attempt counts)
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User-defined data Test item data

0-In data is written into the database with a standalone converter. The UCDB is used natively by ModelSim for all coverage data, deprecating previous separate file formats for code coverage and functional coverage.

Purpose of the UCDB

The Unified Coverage Database is a single persistent form for various kinds of verification data, notably: coverage data of all kinds, and some other information useful for analyzing verification results. When created from ModelSim, it is a single "snapshot" of data in the kernel. Thus, it represents all coverage and assertion objects in the design and testbench, along with enough hierarchical environment to indicate where these objects reside. This data is sufficient to generate complete coverage reports and can also be combined with data acquired outside ModelSim e.g., 0-In coverage and user-defined data.

Important Notes About Coverage Statistics

You should be aware of the following special circumstances related to collecting coverage statistics: Package bodies are not instance-specific: ModelSim sums the counts for all invocations no matter who the caller is. Also, all standard and accelerated packages are ignored for coverage statistics calculation. Design units compiled with -nodebug are ignored, as if they were excluded. When condition coverage is enabled, expression short circuiting in VHDL is disabled. This can result in simulation errors. For example:
if ( (i /= 0) AND (10/i > 1) ) then

will never produce a divide-by-0 error in normal VHDL because the test (i/=0) will be FALSE if i is 0 and 10/i will never be done. With condition coverage enabled both expressions (i /= 0) and (10/i > 1) will always be evaluated and if i is 0, there will be a divide-by-zero error reported. Code coverage is normally turned off for code at the top level of generate blocks (even though code coverage for instances within those blocks may be on). This is done in order to keep ungenerated blocks from preventing 100% code coverage. You can enable code coverage inside the top level of generate blocks by using the -coverGenerate option for vcom or vlog (refer to Enabling Code Coverage).

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Coverage Saving Coverage Data

You may find that design units or instances excluded from code coverage will appear in toggle coverage statistics reports. This happens when ports of the design unit or instance are connected to nets that have toggle coverage turned on elsewhere in the design.

Saving Coverage Data

You can save your coverage data on demand, or at the end of simulation.

Saving Data On Demand

Options for saving coverage data dynamically (during simulation) or in coverage view mode, are: coverage save CLI command During simulation, the following command saves data from the current simulation into a UCDB file called myfile1.ucdb:
coverage save myfile1.ucdb

While viewing results in coverage view mode, you can make changes to the data (using the coverage testattr command, for example). You can then save the changed data to a new file using the following command:
coverage save myfile2.ucdb

$coverage_save system task (not recommended) This is a non-standard SystemVerilog system task that saves code coverage data only, thus it is not recommended. For more information, see System Tasks and Functions Specific to the Tool.

Saving Data at End of Simulation

By default, coverage data is not automatically saved at the end of simulation. To enable the auto-save of coverage data, set a proper filename for the data using any of the following methods: UCDBFilename=<filename>, set in modelsim.ini By default, <filename> is an empty string (""). coverage save -onexit command, specified at Vsim> prompt The coverage save command preserves instance-specific information. For example:
coverage save -onexit myoutput.ucdb

$set_coverage_db_name(<filename>), executed in SystemVerilog code

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If more than one method is used for a given simulation, the last command encountered wins. For example, if you issue the command coverage save -onexit vsim.ucdb, but your SystemVerilog code also contains a $set_coverage_db_name() task, with no name specified, coverage data is not saved for the simulation.

Merging Coverage Data

When you have multiple sets of coverage data, from multiple tests of the same design, you can combine the results into a single UCDB. This is accomplished by merging the UCDB files. Be aware, however, that certain information is lost during a merge, such as which specific test may have incremented a specific count. If this information is important to you, you may instead want to preserve the individual UCDB files, each one representing a unique test run. The vcover code coverage utility supports instance-specific toggles and summing the instances of each design unit. It also supports source code annotation and printing of condition and expression truth tables.

Merging with vcover merge

The merge utility, vcover merge, allows you to merge multiple coverage data files offline, without first loading a design. The merge utility is a standard ModelSim utility that can be invoked from the command line. For example,
vcover merge output inputA.ucdb inputB.ucdb

merges coverage statistics in UCDB files inputA.ucdb and inputB.ucdb and writes them to a new UCDB file called output.

Order of UCDB Files Being Merged

The order of input files specified to vcover merge is important. Example 13-1. Order of Files to Merge
vcover merge output inputA.ucdb inputB.ucdb

When this command is issued, the tool issues the message "Establishing file inputA as the merge base". This means that source information from subsequent files on a module instance or design unit basis must map into the source information available in inputA. Lets say that inputA contains statement coverage from this version of module "m":
1 2 3 4 5 6 module m; initial begin $display("hello"); $display("there"); end endmodule

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and inputB contains statement coverage from a previous version of module "m":
1 2 3 4 5 module m; initial begin $display("hello"); end endmodule

When inputA is specified first, the merge succeeds, because line number 3 in inputB is found in the set of line numbers { 3, 4 } found in file inputA. However, if the merge is reversed ("vcover merge output inputB inputA") the merge fails. The inputB file will be the basis for the merge, and so the set of line numbers expected for module m is only { 3 }. When line 4 is found in inputA, the merge will fail with this error:
** Error: (vcover-6820) Source code change detected, ignoring code coverage merge for instance m.

If an instance in a code coverage database actually has been changed, a warning is generated.

Merge Usage Scenarios

How to go about merging the UCDBs depends upon where and how the data being merged is stored in the databases. As a way of understanding your options, consider three basic merge scenarios, as follows: Scenario 1: You have data from two or more UCDB files, at the same level of hierarchy (scope) in the design. Example commands:
vcover merge output.ucdb file1.ucdb file2.ucdb

Scenario 2: You have data from two or more UCDB files, at different levels of hierarchy. For example: /top/des instance in file1.ucdb, and top/i/des instance in file2.ucdb. Option 1: Strip top levels of hierarchy from both and then merge the stripped files. Example commands:
vcover merge -strip 1 file1_stripped.ucdb file1.ucdb vcover merge -strip 2 file2_stripped.ucdb file2.ucdb vcover merge output.ucdb file1_stripped.ucdb file2_stripped.ucdb

Option 2: Strip levels off instance in one UCDB file, and install to match the hierarchy in the other. In this example, strip /top/ off the /top/des and then add the /top/i hierarchy to it. Example commands:
vcover merge file1_stripped.ucdb -strip 1 file1.ucdb vcover merge file1_installed.ucdb -install /top/i file1_stripped.ucdb vcover merge output.ucdb file1_installed.ucdb file2.ucdb

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Scenario 3: You have two sets of data from a single UCDB file, at different levels of hierarchy. Because they are instantiated at different levels within the same file, the tool cannot merge both of them into the same database. In this scenario, it is best to merge by design unit type using the vcover merge -du command. For example, /top/designinst1 and /top/other/designinst2 are two separate instantiations of the same design within a single UCDB file. Example command for merging all instances in file3.ucdb would be:
vcover merge -du designinst1 output.ucdb file3.ucdb

Coverage View Mode

Raw UCDB coverage data can be saved, merged with coverage statistics from the current simulation or from previously saved coverage data, and viewed at a later date using the Coverage View Mode. The Coverage View Mode allows all ModelSim coverage data saved in the UCDB format code coverage, covergroup coverage, directive coverage, and assertion data to be called up and displayed in the same coverage GUIs used for simulation. The coverage view invocation of the tool is separate from that of the simulation.

Invoking the Coverage View Mode

Use the vsim command with the -viewcov <ucdb_filename> argument to invoke the Coverage View Mode. This allows you to view saved and/or merged coverage results from earlier simulations. Multiple -viewcov arguments are allowed. For example, the Coverage View Mode is invoked with:
vsim -viewcov myresult.ucdb

where myresult.ucdb is the coverage data saved in ucdb format. The design hierarchy and coverage data is imported from a UCDB.

Code Coverage Data

ModelSim code coverage gives you graphical and report file feedback on which statements, branches, conditions, and expressions in your source code have been executed. It also measures bits of logic that have been toggled during execution. With coverage enabled, ModelSim counts how many times each executable statement, branch, condition, expression, and logic node in each instance is executed during simulation. Statement coverage counts the execution of each statement on a line individually, even if there are multiple statements in a line.

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Coverage Code Coverage Data

Branch coverage counts the execution of each conditional "if/then/else" and "case" statement and indicates when a true or false condition has not executed. Condition coverage analyzes the decision made in "if" and ternary statements and is an extension to branch coverage. Expression coverage analyzes the expressions on the right hand side of assignment statements, and is similar to condition coverage. Toggle coverage counts each time a logic node transitions from one state to another.

Coverage statistics are displayed in the Main, Objects, and Source windows and also can be output in different text reports (see Reporting Coverage Data). Raw coverage data can be saved and recalled, or merged with coverage data from the current simulation (see Coverage Statistics Details). ModelSim code coverage offers these benefits: It is totally non-intrusive because its integrated into the ModelSim engine it doesnt require instrumented HDL code as do third-party coverage products. It has very little impact on simulation performance (typically 10 to 20 percent). It allows you to merge sets of coverage data without requiring elaboration of the design or a simulation license.

Usage Flow for Code Coverage

The following is an overview of the usage flow for simulating with code coverage. More detailed instructions are presented in the sections that follow. 1. Compile the design using the -cover bcestxf or -coverAll arguments to vcom or vlog. (See Enabling Code Coverage.) 2. Simulate the design using the -coverage argument to vsim. 3. Run the design. 4. Analyze coverage statistics in the Main, Objects, and Source windows. 5. Edit the source code to improve coverage. 6. Re-compile, re-simulate, and re-analyze the statistics and design.

Supported Types
ModelSim code coverage supports VHDL and Verilog/SystemVerilog data types. Code coverage does not work on SystemC design units.

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VHDL Coverage Support

Supported types for toggle coverage are: boolean, bit, enum, integer, std_logic/std_ulogic, and arrays of these types. Counts are recorded for each enumeration value and a signal is considered toggled if all the enumerations have non-zero counts. For VHDL integers, a record is kept of each value the integer assumes and an associated count. The maximum number of values recorded is determined by a limit variable that can be changed on a per-signal basis. The default is 100 values. The limit variable can be turned off completely with the -toggleNoIntegers option for the vsim command. The limit variable can be increased by setting the vsim command line option -toggleMaxIntValues, setting ToggleMaxIntValues in the modelsim.ini file, or setting the Tcl variable ToggleMaxIntValues. Condition and expression coverage supports bit and boolean types. Arbitrary types are supported when they involve a relational operator with a boolean result. These types of subexpressions are treated as an external expression that is first evaluated and then used as a boolean input to the full condition. The subexpression can look like:
(var <relop> const)

or:
(var1 <relop> var2)

where var, var1 and var2 may be of any type; <relop> is a relational operator (e.g.,==,<,>,>=); and const is a constant of the appropriate type. Expressions containing only one input variable are ignored, as are expressions containing vectors. Logical operators (e.g.,and,or,xor) are supported for std_logic/std_ulogic, bit, and boolean variable types.

Verilog/SystemVerilog Coverage Support

Supported types for toggle coverage are net, register, bit, enum and integer (which includes shortint, int, longint, byte, integer and time). SystemVerilog integer types are treated as 32-bit registers and counts are kept for each bit. For condition and expression coverage, as in VHDL, arbitrary types are supported when they involve a relational operator with a boolean result. Expressions containing only one input variable are ignored, as are expressions containing vectors. Logical operator (e.g.,&&,||,^) are supported for one-bit net, logic, and reg types.

Enabling Code Coverage

Enabling code coverage is a two-step process:

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1. Use the -cover argument to vcom or vlog when you compile your design. This argument tells ModelSim which coverage statistics to collect. For example:
vlog top.v proc.v cache.v -cover bcesxf

Each character after the -cover argument identifies a type of coverage statistic: "b" indicates branch, "c" indicates condition, "e" indicates expression, "s" indicates statement, "t" indicates 2-transition toggle coverage, "x" indicates extended 6-transition toggle coverage (t and x are mutually exclusive), and f indicates Finite State Machine coverage. See Enabling Toggle Coverage for details on two other methods for enabling toggle coverage. You can use graphic interface to perform the same task. Select Compile > Compile Options and select the Coverage tab. Alternatively, if you are using a project, right-click on a selected design object (or objects) and select Properties. Figure 13-1. Coverage Tab of Compiler Options Dialog

If you check Ignore VHDL Subprograms, code coverage collection is disabled for VHDL subprograms.

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2. Use the -coverage argument to vsim when you simulate your design. For example:
vsim -coverage work.top

Or, use the graphic interface. Select Simulate > Start Simulation and select the design unit to be simulated in the Design tab. Then select the Others tab and check Enable code coverage box as shown in Figure 13-2. Figure 13-2. Enabling Code Coverage in the Start Simulation Dialog

Viewing Coverage Data in the Graphic Interface

When you simulate a design with code coverage enabled, coverage data is displayed in several window panes (Figure 13-3): Workspace, Missed Coverage, Current Exclusions, Instance Coverage, Details, Objects, Source, and Finite State Machine.

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Figure 13-3. Coverage Data is Shown in Several Window Panes

The table below summarizes the coverage panes. For further details, see Code Coverage Panes. Table 13-2. Coverage Panes Icon 1 2 Coverage pane Workspace Missed Coverage Description displays coverage data and graphs for each design object or file displays missed coverage for the selected design object or file. Left-click on each line to display details of object in Details window displays coverage statistics for each instance in a flat format displays details of missed statement, branch, condition, expression, and toggle coverage

3 4

Instance coverage Details

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Table 13-2. Coverage Panes Icon 5 6 Coverage pane Current exclusions1 Objects Description lists all files and lines that are excluded from the current analysis displays details of toggle coverage

1. The Current Exclusions pane does not display by default. Select View > Code Coverage > Current Exclusions to display the pane.

Setting a Coverage Threshold

You can specify a percentage above or below which you dont want to see coverage statistics. For example, you might set a threshold of 85% such that only objects with coverage below that percentage are displayed. Anything above that percentage is filtered. You can set a filter using either a dialog or toolbar icons (see below). To access the dialog, right-click any object in the Instance Coverage pane and select Set filter. Figure 13-4. Filter Instance List Dialog

Viewing Coverage Data in the Source Window

The Source Window includes two columns for code coverage statistics the Hits column and the BC (Branch Coverage) column. These columns provide an immediate visual indication about how your source code is executing. The default code coverage indicators are check marks and Xs. A green check mark indicates that the statements, branches or expressions in a particular line have been covered.

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A red X indicates that a statement or branch was not covered. An XT indicates the true branch of an conditional statement was not covered. An XF indicates the false branch was not covered. A green "E" indicates a line of code that has been excluded from code coverage statistics. Figure 13-5. Coverage Data in the Source Window

Expressions have associated truth tables that can be seen in the Details pane when an expression is selected in the Missed Coverage pane. Each line in the truth table is one of the possible combinations for the expression. The expression is considered to be covered (gets a green check mark) only if the entire truth table is covered. When you hover the cursor over a line of code (see line 58 in the illustration above), the number of statement and branch executions, or "hits," will be displayed in place of the check marks and Xs. If you prefer, you can display only numbers by selecting Tools > Code Coverage > Show Coverage Numbers. Also, when you click in either the Hits or BC column, the Details pane in the Main window updates to display information on that line.

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You can skip to "missed lines" three ways: select Edit > Previous Coverage Miss and Edit > Next Coverage Miss from the menu bar; click the Previous zero hits and Next zero hits icons on the toolbar; or press Shift-Tab (previous miss) or Tab (next miss).

Controlling Data Display in a Source Window

The Tools > Code Coverage menu contains several commands for controlling coverage data display in a Source window. Hide/Show coverage data toggles the Hits column off and on. Hide/Show branch coverage toggles the BC column off and on. Hide/Show coverage numbers displays the number of executions in the Hits and BC columns rather than checkmarks and Xs. When multiple statements occur on a single line an ellipsis ("...") replaces the Hits number. In such cases, hover the cursor over each statement to highlight it and display the number of executions for that statement. Show coverage By Instance displays only the number of executions for the currently selected instance in the Main window workspace.

Toggle Coverage
Toggle coverage is the ability to count and collect changes of state on specified nodes, including Verilog nets and registers and the following VHDL signal types: boolean, bit, bit_vector, enum, integer, std_logic/std_ulogic, and std_logic_vector/std_ulogic_vector. Toggle coverage is integrated as a metric into the coverage tool so that the use model and reporting are the same as the other coverage metrics. There are two modes of toggle coverage operation - standard and extended. Standard toggle coverage only counts Low or 0 <--> High or 1 transitions. Extended toggle coverage counts these transitions plus the following:
Z <--> 1 or H Z <--> 0 or L

Extended coverage allows a more detailed view of testbench effectiveness and is especially useful for examining coverage of tri-state signals. It helps to ensure, for example, that a bus has toggled from high 'Z' to a '1' or '0', and a '1' or '0' back to a high 'Z'. Toggle coverage ignores zero-delay glitches.

Enabling Toggle Coverage

In the section Enabling Code Coverage we explained that toggle coverage could be enabled during compile by using the t or x arguments with vcom -cover or vlog -cover. This section describes two other methods for enabling toggle coverage:

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1. using the toggle add command 2. using the Tools > Toggle Coverage > Add or Tools > Toggle Coverage > Extended selections in the Main window menu.

Using the Toggle Add Command

The toggle add command allows you to initiate toggle coverage at any time from the command line. Upon the next running of the simulation, toggle coverage data will be collected according to the arguments employed (i.e., the -full argument enables collection of extended toggle coverage statistics for the transitions mentioned above). If you use a toggle add command on a group of signals to get standard toggle coverage, then try to convert to extended toggle coverage with the toggle add -full command on the same signals, nothing will change. The only way to change the internal toggle triggers from standard to extended toggle coverage is to restart vsim and use the correct command.

Using the Main Window Menu Selections

You can enable toggle coverage by selecting Tools > Toggle Coverage > Add or Tools > Toggle Coverage > Extended from the Main window menu. These selections allow you to enable toggle coverage for Selected Signals, Signals in Region, or Signals in Design. After making a selection, toggle coverage statistics will be captured the next time you run the simulation.

Viewing Toggle Coverage Data in the Objects Pane

To view toggle coverage data in the Objects pane right-click in the pane to open a context popup menu the Toggle Coverage selection. When highlighted, this selection allows you to display toggle coverage data for the Selected Signals, the Signals in Region, or the Signals in Design. Toggle coverage data is displayed in the Objects pane in multiple columns, as shown below. There is a column for each of the six transition types. Right click any column name to toggle that column on or off. See Objects Pane Toggle Coverage for more details on each column.

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Figure 13-6. Toggle Coverage Data in the Objects Pane

Finite State Machine Coverage

Information about Finite State Machine coverage can be found in the Finite State Machines chapter.

Managing Exclusions
ModelSim includes the following mechanisms for creating coverage exclusions: You can use fcover configure -exclude/-include to exclude functional coverage SVA and PSL directives. Use source code pragmas to exclude individual code coverage metrics. Use the coverage exclude command for code coverage exclusions. Use the GUI to create exclusions. Right-click any object in the Missed Coverage pane (except Toggle and FSM objects) and select Exclude Selection

Exclusions are stored in the current exclusions file and in the UCDB. This allows report generation based on the most recent snapshot of functional coverage state. In its internal operation, ModelSim guarantees that the exclusions file and the UCDB are consistent with each other in the exclusions specified. Exclusions are implemented using the "flags" field associated with a cover item. The primary functions ucdb_IncludeCover and ucdb_ExcludeCover dynamically include or exclude cover items. The flag UCDB_EXCLUDE_PRAGMA is used as a flag with cover items (specifically statement coverage) that are excluded by pragma.

Excluding Objects from Coverage

You can exclude any number of lines or files, or condition and expression UDP truth table rows, from coverage statistics collection. The line exclusions can be instance-specific or they can

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apply to all instances in the enclosing design unit. Truth table row exclusions can be instance specific. You can also exclude nodes from toggle statistics collection using the toggle disable command. The following methods can be used for excluding objects: Exclude Lines and Files Using the GUI Exclude Individual Metrics with Pragmas Exclude Lines and Rows from UDP Truth Tables Exclude Lines and Rows with the Coverage Exclude Command Exclude Nodes from Toggle Coverage Exclude Bus Bits from Toggle Coverage Exclude enum Signals from Toggle Coverage Exclude Any/All Coverage Data in a Single File

Exclude Lines and Files Using the GUI

There are several locations in the GUI where you can access commands to exclude lines or files: Right-click a file in Files tab of the Workspace pane and select Code Coverage > Exclude Selected File from the popup menu. Right-click an entry in the Main window Missed Coverage pane and select Exclude Selection or Exclude Selection For Instance <inst_name> from the popup menu. Right-click a line in the Hits column of the Source window and select Exclude Coverage Line xxx, Exclude Coverage Line xxx For Instance <inst_name>, or Exclude Entire File.

Exclude Individual Metrics with Pragmas

ModelSim also supports the use of source code pragmas to selectively turn coverage off and on for individual code coverage metrics. In Verilog, the pragmas are:
// coverage off // coverage on

In VHDL, the pragmas are:

-- coverage off -- coverage on

Bracket the line or lines you want to exclude with these pragmas.

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Pragmas allow you to turn statement, branch, condition, expression and FSM coverage on and off independently. To create an exclusion, add an additional argument to the coverage on or coverage off pragma using characters to indicate the coverage metric. For example
// coverage off sce

turns off statement, condition and expression coverage in Verilog, and leaves the other metrics alone.
-- coverage on bf

turns on branch and FSM coverage in VHDL, leaving the other metrics alone. Here are some points to keep in mind about using these pragmas: Pragmas are enforced at the design unit level only. For example, if you put "-- coverage off" before an architecture declaration, all statements in that architecture will be excluded from coverage; however, statements in all following design units will be included in statement coverage (until the next "-- coverage off"). Pragmas cannot be used to exclude specific subconditions or subexpressions within lines, although they can be used for individual case statement alternatives.

Exclude Lines and Rows from UDP Truth Tables

You can exclude lines and rows from condition and expression UDP truth tables using the coverage exclude command. Exclusions may be instance-specific. For more details, see the coverage exclude command.

Exclude Lines and Rows with the Coverage Exclude Command

You can use the coverage exclude command for direct exclusion of specific lines in a source file or rows within a condition or expression truth table.

Exclude Nodes from Toggle Coverage

You can disable toggle coverage with the toggle disable command. This command turns off the collection of toggle statistics for the specified nodes and provides a method of implementing coverage exclusions for toggle coverage. It is intended to be used as follows: 1. Enable toggle statistics collection for all signals using the -cover t/x argument to vcom or vlog. 2. Exclude certain signals by disabling them with the toggle disable command. The toggle enable command re-enables toggle statistics collection on nodes whose toggle coverage has previously been disabled via the toggle disable command. (See the Reference Manual for correct syntax.)

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Exclude Bus Bits from Toggle Coverage

You can exclude bus bits from toggle coverage using special source code pragmas. Verilog syntax
// coverage toggle_ignore <simple_signal_name> "{<list> | all}"

VHDL syntax
-- coverage toggle_ignore <simple_signal_name> "{<list> | all}"

The following rules apply to using these pragmas: <list> is a space-separated list of bit indices or ranges, where a range is two integers separated by ':' or '-'. If using a range, the range must be in the same ascending or descending order as the signal declaration. The all keyword indicates that you are excluding the entire signal and can be specified instead of <list>. Quotes are required around the <list> or all keyword. The pragma must be placed within the declarative region of the module or architecture in which <simple_signal_name> is declared.

Exclude enum Signals from Toggle Coverage

You can exclude individual VHDL enums or ranges of enums from toggle coverage and reporting by specifying enum exclusions in source code pragmas or by using the -exclude argument to the toggle add command.

Exclude Any/All Coverage Data in a Single File

In cases where you would like to exclude all types of coverage data from an exclusions file, use the coverage exclude command. It can be used to exclude any / all of the following types of coverage: Datasets (.wlf files) Coverage types within datasets; source file(s) Lines within a source file Rows within a condition or expression truth table Instances or design units; Transitions or states within a Finite State Machine

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A .do file is created when the user does a File > Save with the Current Exclusions window active. The default name of the .do file is exclude.do For example, the contents of the exclusions.do file might look like the following:
coverage exclude -srcfile xyz.vhd -linerange 12 55 67-90 coverage exclude -srcfile abc.vhd -linerange 3-6 9-14 77 coverage exclude -srcfile pqr.vhd -linerange all -inout

This will exclude lines 12, 55, and 67 to 90 (inclusive) of file xyz.vhd; lines 3 to 6, 9 to 14, and 77 of abc.vhd; all lines from pqr.vhd, and all INOUT toggle nodes. This exclude.do file can then be used as follows: 1. Compile your design with vcom -cover (vlog -cover if you have a Verilog design) 2. Load and run your design with:
vsim -coverage <design_name> -do exclude.do run -all

Saving and Recalling Exclusions

You may specify files and line numbers or condition and expression UDP truth table rows (see below for details) that you wish to exclude from coverage statistics. These exclusions will appear in the Current Exclusions pane. You can then create a .do file that contains these exclusions by making the Current Exclusions pane active and then choosing File > Save from the menus. To load this .do file during a future analysis, select the Current Exclusions pane and select File > Open. Example 13-2. Excluding, Merging and Reporting on Several Runs Suppose you are doing a number of simulations, i, numbered from 1 to n. 1. Use vlib to create a working library. 2. Use vcom and/or vlog to compile. 3. Use vsim to load and run the design:
vsim -c <design_i> -do "log -r /*; run -all; do <exclude_file_i.do>; coverage save <results_i>; quit -f"

Note, you can have different exclude files <exclude_file_i> for each run i, numbered from 1 to n. 4. Use vcover merge to merge the coverage data:
vcover merge <merged_results_file> <results_1> <results_2> ... <results_n>

5. Use vcover report to generate your report:

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Coverage Reporting Coverage Data vcover report [switches_you_want] -output <report_file> <merged_results_file>

Exclusions are invoked at the vsim step 3. All the various results files <results_i> contain the exclusion information inserted at step 3. The exclusion information for the merged results file is derived by ORing the exclusion flags from each vsim run. So, for example, if runs 1 and 2 exclude xyz.vhd line 12, but the other runs don't exclude that line, the exclusion flag for xyz.vhd line 12 is set in the merged results since at least one of the runs excluded that line. Then the final vcover report will not show coverage results for file xyz.vhd line 12. Let's suppose your <exclude_file_i> are all the same, and called exclude.do. The contents of exclude.do file could be:
coverage exclude -srcfile xyz.vhd -linerange 12 55 67-90 coverage exclude -srcfile abc.vhd -linerange 3-6 9-14 77 coverage exclude -srcfile pqr.vhd -linerange all

This will exclude lines 12, 55, and 67 to 90 (inclusive) of file xyz.vhd; lines 3 to 6, 9 to 14, and 77 of abc.vhd; and all lines from pqr.vhd.

Default Filter File

The Tcl preference variable PrefCoverage(pref_InitFilterFrom) specifies a default filter file to read when a design is loaded with the -coverage switch. By default this variable is not set. See Simulator GUI Preferences for details on changing this variable.

Reporting Coverage Data

You may create coverage reports from the command line or with the GUI. When the simulation is loaded, you can create coverage reports using: the coverage report command, the toggle report command, or the Coverage Report dialog.

To create reports when a simulation isnt loaded, use the vcover report command. This command produces textual output of coverage data from a previously save code or functional coverage run.

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Using the coverage report Command

The coverage report command produces textual output of coverage statistics or exclusions of the current simulation. Example 13-3. Reporting Coverage Data from the Command Line Here is a sample command sequence that outputs a code coverage report and saves the coverage data:
vlog vlog vlog vlog -cover -cover -cover -cover bcefsx bcefsx bcefsx bcefsx ../rtl/host/top.v ../rtl/host/a.v ../rtl/host/b.v ../rtl/host/c.v

vsim -c -coverage top run 1 ms coverage report -file d:\\sample\\coverage_rep coverage save d:\\sample\\coverage

The vlog command compiles Verilog and SystemVerilog design units. The -cover bcesx option specifies the types of coverage statistics to collect: b = branch coverage c = condition coverage e = expression coverage f = finite state machine coverage s = statement coverage x = extended toggle coverage The -coverage option for the vsim command turns off optimizations that interfere with code coverage and enables code coverage statistics collection during simulation. The -file option for the coverage report command specifies a filename for the coverage report: coverage_rep. And the coverage save command saves the file to d:\\sample\\coverage.

Using the toggle report Command

The toggle report command displays a list of all nodes that have not transitioned to both 0 and 1 at least once, and the counts for how many times each node toggled for each state transition type. Also displayed is a summary of the number of nodes checked, the number that toggled, the number that didn't toggle, and a percentage that toggled. The toggle report command is intended to be used as follows: 1. Enable statistics collection with the toggle add command.

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2. Run the simulation with the run command. 3. Produce the report with the toggle report command. Figure 13-7. Sample Toggle Report

You can produce this same information using the coverage report command.

Port Collapsing and Toggle Coverage

The simulator collapses certain ports that are connected to the same signal in order to improve performance. Collapsed signals will not appear in the toggle coverage report. If you want to ensure that you are reporting all signals in the design, use the -nocollapse argument to vsim when you load your design. The -nocollapse argument degrades simulator performance, so it should be used only when it is absolutely necessary to see all signals in a toggle report.

Ordering of Toggle Nodes

The ordering of nodes in the report may vary depending on how you specify the signal list. If you use a wildcard in the signal argument (e.g., toggle report -all -r /*), the nodes are listed in the order signals are found when searching down the context tree using the wildcard. Multiple elements of the same net will be listed multiple times. If you do not use a wildcard (e.g., toggle report -all -r /*), the nodes are listed in the order in which they were originally added to toggle coverage, and elements are not duplicated.

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Using the Coverage Report Dialog

To create a coverage report using the ModelSim GUI, access the Coverage Report dialog by right-clicking any object in the Files tab of the Workspace pane and selecting Code Coverage > Code Coverage Reports; or, select Tools > Code Coverage > Reports. Figure 13-8. Coverage Report Dialog

Setting a Default Coverage Reporting Mode

You can specify a default coverage mode that persists from one ModelSim session to the next through the preference variable PrefCoverage(DefaultCoverageMode). The modes available allow you to specify that lists and data given in each report are listed by: file, design unit, or instance. By default, the report is listed by file. See Simulator GUI Preferences for details on changing this variable.

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You may also specify a default coverage mode for the current invocation of ModelSim by using the -setdefault [byfile | byinstance | bydu] argument for either the coverage report or the vcover report command.

XML Output
You can output coverage reports in XML format by checking Write XML Format in the Coverage Report dialog or by using the -xml argument to the coverage report command. The following example is an abbreviated "By Instance" report that includes line details:
<?xml version="1.0"?> <report lines="1" byInstance="1"> <instance path="/test_delta/chip/control_126k_inst" du="mode_two_control"> <source_table files="1"> <file fn="0" path="C:/modelsim_examples/coverage/Modetwo.v"></file> </source_table> <statements active="30" hits="17" percent="56.7"> </statements> <statement_data> <stmt fn="0" ln="39" st="1" hits="82"> </stmt> <stmt fn="0" ln="42" st="1" hits="82"> </stmt> <stmt fn="0" ln="44" st="1" hits="82"> </stmt>

"fn" stands for filename, "ln" stands for line number, and "st" stands for statement. There is also an XSL stylesheet named covreport.xsl located in <install_dir>/examples/tutorials/vhdl/coverage, or <install_dir>/examples/tutorials/verilog/coverage. Use it as a foundation for building your own customized report translators.

Sample Reports
Below are abbreviated coverage reports with descriptions of select fields.

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Statement Coverage Summary Report by File

Figure 13-9. Sample Statement Coverage Summary Report by File

This report shows statement coverage by file with Active, Hits and % Covered columns. % Coverage shows statement hits divided by the number of active statements.

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Instance Report with Line Details

Figure 13-10. Sample Instance Report with Line Details

Each line may contain more than one statement, and each statement is given a number. The "Stmt" field identifies the statement number a specific line. The Count field shows the number of hits for the identified statement. So on line 22 of the report above, statement 2 received 28119 hits.

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Note The Count column will indicate INF when the count has overflowed the unsigned long variable used by ModelSim to keep the count.

Branch Report
Figure 13-11. Sample Branch Report

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If an IF Branch ends in an "else" clause, the "else" count will be shown. Otherwise, an "All False" count will be given, which indicates how many times none of the conditions evaluated "true." If "INF" appears in the Count column, it indicates that the coverage count has exceeded ~4 billion (232 -1). ***0*** indicates a zero count for that branch.

Coverage Statistics Details

This section describes how condition and expression coverage statistics are calculated.

Condition Coverage
Condition coverage analyzes the decision made in "if" and ternary statements and is an extension to branch coverage. A truth table is constructed for the condition expression and counts are kept for each row of the truth table that occurs. For example, the following IF statement:
Line 180: IF (a or b) THEN x := 0; else x := 1; endif;

reflects this truth table. Table 13-3. Condition Truth Table for Line 180 Truth table for line 180 counts a Row 1 Row 2 Row 3 unknown 5 0 8 0 1 0 b 1 0 (a or b) 1 1 0

Row 1 indicates that (a or b) is true if a is true, no matter what b is. The "counts" column indicates that this combination has executed 5 times. The '-' character means "don't care." Likewise, row 2 indicates that the result is true if b is true no matter what a is, and this combination has executed zero times. Finally, row 3 indicates that the result is always zero when a is zero and b is zero, and that this combination has executed 8 times. The unknown row indicates how many times the line was executed when one of the variables had an unknown state. If more than one row matches the input, each matching row is counted. If you would prefer no counts to be incremented on multiple matches, set CoverCountAll to 0 in your modelsim.ini file to reverse the default behavior. Alternatively, you can use the -covercountnone argument to vsim to disable the count for a specific invocation.

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Values that are vectors are treated as subexpressions external to the table until they resolve to a boolean result. For example, take the IF statement:
Line 38:IF ((e = '1') AND (bus = "0111")) ...

A truth table will be generated in which bus = "0111" is evaluated as a subexpression and the result, which is boolean, becomes an input to the truth table. The truth table looks as follows: Table 13-4. Condition Truth Table for Line 38 Truth table for line 38 counts e Row 1 Row 2 Row 3 unknown 0 10 1 0 0 1 (bus="0111") 0 1 (e=1) AND ( bus = "0111") 0 0 1

Index expressions also serve as inputs to the table. Conditions containing function calls cannot be handled and will be ignored for condition coverage. If a line contains a condition that is uncovered - some part of its truth table was not encountered - that line will appear in the Missed Coverage pane under the Conditions tab. When that line is selected, the condition truth table will appear in the Details pane and the line will be highlighted in the Source window. Condition coverage truth tables are printed in coverage reports when the Condition Coverage type is selected in the Coverage Reports dialog (see Reporting Coverage Data), or when the lines argument is specified in the coverage report command and one or more of the rows has a zero hit count. To force the table to be printed even when it is 100% covered, use the -dump argument to the coverage report command. Tip: Condition coverage does not do short circuit evaluation of IF conditions. So if you turn on condition coverage and you get a crash, that is the first thing you should check.

Expression Coverage
Expression coverage analyzes the expressions on the right hand side of assignment statements and counts when these expressions are executed. For expressions that involve logical operators, a truth table is constructed and counts are tabulated for conditions matching rows in the truth table. For example, take the statement:

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Coverage Coverage Statistics Details Line 236: x <= a xor (not b(0));

This statement results in the following truth table, with associated counts. Table 13-5. Expression Truth Table for line 236 Truth table for line 236 counts a Row 1 Row 2 Row 3 Row 4 unknown 1 0 2 0 0 0 0 1 1 b(0) 0 1 0 1 (a xor (not b(0))) 1 0 0 1

If a line contains an expression that is uncovered (some part of its truth table was not encountered) that line will appear in the Missed Coverage pane under the Expressions tab. When that line is selected, the expression truth table will appear in the Details pane and the line will be highlighted in the Source window. As with condition coverage, expression coverage truth tables are printed in coverage reports when the Expression Coverage type is selected in the Coverage Reports dialog (see Reporting Coverage Data) or when the -lines argument is specified in the coverage report command and one or more of the rows has a zero hit count. To force the table to be printed even when it is 100% covered, use the -dump argument for the coverage report command.

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Chapter 14 Finite State Machines

Because of the complexity of state machines, Finite State Machine (FSM) design is prone to the introduction of errors. It is important, therefore, to analyze the coverage of FSMs in RTL before going to the next stages of synthesis in the design cycle.

Types of FSM Coverage

In ModelSim, two kinds of coverage are defined for FSMs. 1. State Coverage Metric: This metric determines how many FSM states have been reached during simulation. 2. Transition or FSM Arc Coverage Matrix: This metric determines how many transitions have been exercised in the simulation of the state machine. ModelSim also performs state reachability analysis on extracted FSMs and flags unreachable states. All existing coverage command line options such as coverage clear, coverage exclude, coverage report, etc. can be used for FSM coverage. Note The functionality described in this chapter requires a coverage license feature in your ModelSim license file. Please contact your Mentor Graphics sales representative if you currently do not have such a feature.

FSM Recognition
FSM recognition happens as part of code generation. If code is generated in vcom or vlog, then FSMs are recognized in vcom or vlog. But if FSM depends on any parameter/generics, then it is recognized only in vopt. FSM recognition and coverage is enabled at compile time by using the -cover f or -coverAll arguments for vcom or vlog. Various design styles are used in Verilog and VHDL to specify FSMs. Their main features are as follows: There should be a finite number of states which the state variable can hold. The next state assignments to the state variable must be made under a clock. The next state value must depend on the current state value of the state variable.

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State assignments that do not depend on the current state value are considered reset assignments.

There are two types of supported FSMs: 1. using a single state variable 2. using a current state variable and a next state variable. The following examples illustrate the two supported types. Example 14-1. Using a Single State Variable in Verilog
RTL module fsm_test (out, inp, clk, enb, cnd, rst); output out; reg out; input [7:0] inp; input clk, enb, cnd, rst; parameter [2:0] s0 = 3'h0, s1 = 3'h1, s2 = 3'h2, s3 = 3'h3, s4 = 3'h4, s5 = 3'h5, s6 = 3'h6, s7 = 3'h7; reg [2:0] cst, nst; always @(posedge clk or posedge rst) if (rst) cst <= s0; else casex (cst) s0: begin out = inp[0]; if (enb) s1: begin out = inp[1]; if (enb) s2: begin out = inp[2]; if (enb) s3: begin out = inp[3]; if (enb) s4: begin out = inp[4]; if (enb) s5: begin out = inp[4]; if (enb) s6: begin out = inp[6]; if (enb) s7: begin out = inp[7]; if (enb) default: begin out = inp[5]; cst endcase endmodule

cst = cst = cst = cst = cst = cst = cst = cst = = s1;

s1; s2; s3; s4; s5; s6; s7; s0; end

end end end end end end end end

Example 14-2. Using a single state variable in VHDL

RTL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; entity fsm is port( in1 : in signed(1 downto 0); in2 : in signed(1 downto 0); en : in std_logic_vector(1 downto 0); clk: in std_logic; reset : in std_logic_vector( 3 downto 0); out1 : out signed(1 downto 0)); end fsm; architecture arch of fsm is

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type my_enum is (s0 , s1, s2, s3,s4,s5); type mytype is array (3 downto 0) of std_logic; signal test : mytype; signal cst : my_enum; begin process(clk,reset) begin if(reset(1 downto 0) = "11") then cst <= s0; elsif(clk'event and clk = '1') then case cst is when s0 => cst <= s1; when s1 => cst <= s2; when s2 => cst <= s3; when others => cst <= s0; end case; end if; end process; end arch;

Example 14-3. Using a Current State Variable and a Single Next State Variable in Verilog
RTL module fsm_test (out, inp, clk, enb, cnd, rst); output out; reg out; input [7:0] inp; input clk, enb, cnd, rst; parameter [2:0] s0 = 3'h0, s1 = 3'h1, s2 = 3'h2, s3 = 3'h3, s4 = 3'h4, s5 = 3'h5, s6 = 3'h6, s7 = 3'h7; reg [2:0] cst, nst; always @(posedge clk or posedge rst) if (rst) cst <= s0; else cst <= nst; always @(cst or inp or enb) begin casex (cst) s0: begin out = inp[0]; if (enb) s1: begin out = inp[1]; if (enb) s2: begin out = inp[2]; if (enb) s3: begin out = inp[3]; if (enb) s4: begin out = inp[4]; if (enb) s5: begin out = inp[4]; if (enb) s6: begin out = inp[6]; if (enb) s7: begin out = inp[7]; if (enb) default: begin out = inp[5]; nst endcase end endmodule

nst = nst = nst = nst = nst = nst = nst = nst = = s1;

s1; s2; s3; s4; s5; s6; s7; s0; end

end end end end end end end end

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Example 14-4. Using Current State Variable and Single Next State Variable in VHDL
RTL library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use work.pack.all; entity fsm is port( in1 : in signed(1 downto 0); in2 : in signed(1 downto 0); en : in std_logic_vector(1 downto 0); clk: in std_logic; reset : in std_logic_vector( 3 downto 0); out1 : out signed(1 downto 0)); end fsm; architecture arch of fsm is type my_enum is (s0 , s1, s2, s3,s4,s5); type mytype is array (3 downto 0) of std_logic; signal test : mytype; signal cst, nst : my_enum; begin process(clk,reset) begin if(reset(1 downto 0) = "11") then cst <= s0; elsif(clk'event and clk = '1') then cst <= nst; end if; end process; process(cst) begin case cst is when s0 => nst when s1 => nst when s2 => nst when others => end case; end process; end arch;

<= s1; <= s2; <= s3; nst <= s0;

Note Multi-level next state assignments are not supported.

Supported Design Styles for FSM Extraction

The following styles of writing FSMs in VHDL, Verilog, and SystemVerilog are supported: Using enum or constant literals or constant expressions and case statements Using constants In Verilog, constants can be specified using localparams or parameters. Parameters are considered constant only in the Vopt flow. Hence, if FSMs
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are written with parameters as state values, they will be recognized only in the Vopt flow. Using current state variable Using current state and next state variable Using current state variables as record/structure fields. Nested records and SV structures are not supported. Using with-select statement (VHDL only) Using when-else logic (VHDL only) One-Hot/One-Cold style FSMs(Verilog only) Using Verilog Generate statement. These FSMs are recognized only in Vopt flow. Using any integral SystemVerilog types like logic, int, bit_vector, enum, packed struct etc. Typedefs of these types are also supported.

Unsupported Design Styles

The following design styles of writing FSMs in VHDL, Verilog, and SystemVerilog are not supported: Using bit-selects or part-selects (Verilog) and index expressions or slice expressions (VHDL) FSMs in Generate statements are not recognized. Multiple case statements or nested case statements used to define FSM transitions Multiple if statements used to define FSM transitions Mixed case and if-else statements used to specify FSM transitions

FSM Extraction Reporting

Output messages are generated to report the FSMs extracted from the design. These reports contain the following information. The current state variable The next state variable (if any) The clock under which the state variable is assigned The state set of the FSM The reset states of the FSM

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The set of state transitions along with the line numbers from which they have been identified

State reachability analysis is carried out on the extracted FSMs and the unreachable states, if any, are also reported. A state is marked as unreachable if it cannot be reached from the reset states. These messages can be suppressed using the "-suppress 1947" arguments for vcom or vlog. The following Verilog example will illustrate the above points. Example 14-5. Verilog Reporting
RTL module fsm_test (out, inp, clk, enb, cnd, rst); output out; reg out; input [7:0] inp; input clk, enb, cnd, rst; parameter [2:0] s0 = 3'h0, s1 = 3'h1, s2 = 3'h2, s3 = 3'h3, s4 = 3'h4, s5 = 3'h5, s6 = 3'h6, s7 = 3'h7; reg [2:0] cst, nst; always @(posedge clk or posedge rst) if (rst) cst <= s0; else cst <= nst; always @(cst or inp or enb) begin casex (cst) s0: begin out = inp[0]; if (enb) s1: begin out = inp[1]; if (enb) s2: begin out = inp[2]; if (enb) s3: begin out = inp[3]; if (enb) s4: begin out = inp[4]; if (enb) s5: begin out = inp[4]; if (enb) unreachable state s6: begin out = inp[6]; if (enb) s7: begin out = inp[7]; if (enb) default: begin out = inp[5]; nst endcase end endmodule COMPILE REPORT ** Note: (vlog-1947) FSM RECOGNITION INFO Fsm detected in : fsm-unreach.v Current State Variable : cst : fsm-unreach.v(8) Next State Variable : nst : fsm-unreach.v(8) Clock : clk Reset States are: { s0 } State Set is : { s0 , s1 , s2 , s4 , s3 , s6 , s5 , s7 } Transition table is ------------------------------------------s0 => s1 Line : (18 => 18) s0 => s0 Line : (12 => 12) s1 => s2 Line : (19 => 19) s1 => s0 Line : (12 => 12)

nst nst nst nst nst nst

= = = = = =

s1; s2; s4; s6; s3; s6;

end end end end end end // state s5 is an

nst = s7; end nst = s0; end = s1; end

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s2 => s4 Line : (20 => 20) s2 => s0 Line : (12 => 12) s4 => s3 Line : (22 => 22) s4 => s0 Line : (12 => 12) s3 => s6 Line : (21 => 21) s3 => s0 Line : (12 => 12) s6 => s7 Line : (24 => 24) s6 => s0 Line : (12 => 12) s5 => s6 Line : (23 => 23) s5 => s0 Line : (12 => 12) s7 => s0 Line : (25 => 25) (12 => 12) ------------------------------------------INFO : State s5 is unreachable from the reset states

Disabling FSM Extraction Using Pragmas

The user can also disable FSM extraction using pragmas. The "coverage fsm_off <cst_var_name>" pragma turns off FSM recognition at compile time for the FSM whose current state variable name has been specified in the pragma. This pragma must be written after the declaration of the current state variable. Example 14-6. Using Pragmas in VHDL
RTL entity fsm1 is port(clk : bit; reset : bit); end fsm1; architecture arch of fsm1 is type state_codes is (s0, s1, s2, s3); begin process variable curr_state : integer range 0 to 3; variable next_state : integer range 0 to 3; -- coverage fsm_off curr_state begin wait until clk'event and clk = '1'; curr_state := next_state; if(reset = '1') then curr_state := 0; else case curr_state is when 0 => next_state := 1; when 1 => next_state := 2; when 2 => next_state := 3; when 3 => next_state := 0; when others => next_state := 0; end case; end if; end process; end arch;

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COMPILE REPORT ** Warning: [13] fsm-pragma.vhdl(14): Detected coverage fsm_off pragma: Turning off FSM coverage for "curr_state".

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Viewing FSM Coverage in the GUI

Once the FSMs have been detected, you can simulate the design and view coverage results in the graphic user interface. 1. Compile the design with the -cover f argument for the vcom or vlog command. 2. Load the design with the -coverage argument for the vsim command. 3. Run the simulation. FSM coverage data will appear in the Workspace, Objects, Missed Coverage, Instance Coverage, Details, and Current Exclusions window panes. In addition, you can generate a graphical state machine diagram in the FSM Viewer by double-clicking any FSM item in the Missed Coverage pane.

Workspace
Both the sim and the Files tab of the Workspace will display FSM coverage data in the following columns: States, State hits, State misses, State graph, Transitions, Transition hits, Transition misses, Transition %, and Transition graphs. Figure 14-1. FSM Coverage Data in the Workspace

The State % is the State hits divided by the States. Likewise, Transition % is the Transition hits divided by the Transitions. The State graph and the Transition graph will display a green bar with State % or Transition %, respectively, is 90% or greater. The bar graphs will be red for percentages under 90.

Objects
The Objects pane will display FSM coverage data in the State Count, State Hits and State % columns (Figure 14-2). The icon that appears next to the state variable name is also a button . Clicking this button will open a state machine view in the MDI area (see FSM Viewer).

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Figure 14-2. FSM Coverage in the Objects Pane

Missed Coverage
The Missed Coverage pane contains an FSM tab that lists states and transitions that have been fully covered during simulation. Transitions are listed under states, and the source line numbers for each transition is listed under its respective transition. A design unit for file that contains a state machine must be selected in the workspace before anything will appear here. In the Missed Coverage pane, the icon that appears next to the state variable name is also a button . Pressing this button will open a state machine view in the MDI area (see FSM Viewer). When you select a state, the state name will be highlighted in the FSM Viewer. When you select a transition, that transition line will be highlighted in the FSM Viewer. When you select the source line number for the transition, a Source view will open in the MDI frame and display the line number you have selected. Figure 14-3. FSM Missed Coverage

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Details
Select any FSM item in the Missed Coverage pane to show the details of state and transition coverage in the Details pane. Figure 14-4. FSM Details

Instance Coverage
The Instance Coverage pane will display FSM coverage data in the following columns: States, State hits, State misses, State graph, Transitions, Transition hits, Transition misses, Transition %, and Transition graphs.

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FSM Viewer
The icon that appears next to the state variable name in the Objects, Locals or Missed Coverage panes is also a button . Pressing this button will open a state machine view in the MDI area. This is the FSM Viewer. The numbers in boxes are the state and transition hit counts. Figure 14-5. The FSM Viewer

The FSM Viewer is dynamically linked to the Details pane. If you select a bubble or a line in this diagram, the Details pane will display all FSM details, as shown in Figure 14-4. If you select a bubble, its name will be bold-faced. If you select a line, the names of both bubbles connected to the line will be bold-faced.

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Using the Mouse in the FSM Viewer

These mouse operations are defined for the FSM Viewer: The mouse wheel performs zoom & center operations on the diagram. Mouse up will zoom out. Mouse down will zoom in. Whether zooming in or out, the view will recenter towards the mouse location. LMB (button-1) click will select the item under the mouse. Shift-LMB (button-1) click will extend the current selection. LMB (button-1) drag will select items inside the bounding box. MMB (button-3) drag has similar definitions as found in the Dataflow and Wave windows:
o o

Drag up and to the left will Zoom Full. Drag up and to the right will Zoom Out. The amount is determined by the distance dragged. Drag down and to the left will Zoom Selected. Drag down and to the right will Zoom In on the area of the bounding box.

o o

The Zoom toolbar has 3 additional mode buttons. The Show State Counts button The Show Transition Counts button hit count. will turn on/off the display of the state hit count. will turn on/off the display of the transition

The Info Mode button turns on the hover display mode for either or both hit counts, whichever are currently not displayed.

FSM Coverage Reports

You can initiate FSM coverage reports using the GUI or by entering coverage report commands at the command line. Using the GUI, select Tools > Code Coverage > Reports to open the Coverage Report dialog. In the Coverage Type section of the dialog, select Finite State Machine Coverage. Figure 14-6. Coverage Type Section of Coverage Report Dialog

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The various coverage reporting commands available to view FSM coverage reports are detailed below.

Coverage Summary by Instance

Data is collected for all FSMs in each instance, merged together and reported when the following command is used:
coverage report -select f -byInst

The format of the FSM coverage summary by instance report is as follows:

Coverage Report Summary Data by instance Instance: /top/mach Design Unit: work.statemach(fast) Enabled Coverage Active --------------------States 4 Transitions 12 Instance: /top/machinv Design Unit: work.statemach(fast) Enabled Coverage Active --------------------States 4 Transitions 12

Hits % Covered ---- --------3 75.0 8 66.7

Hits % Covered ---- --------3 75.0 8 66.7

Instance: /top/toggle Design Unit: work.vhdl_toggle(arch_toggle) Enabled Coverage Active Hits % Covered ------------------------ --------States 3 3 100.0 Transitions 3 3 100.0

Coverage Summary by Design Unit

Data is collected for all FSMs in all instances of each design unit. This data is then merged and reported when the following command is used:
coverage report -select f -byDu

The format of the FSM coverage summary by design unit report is as follows:
Coverage Report Summary Data by DU Design Unit: work.statemach(fast) Enabled Coverage Active --------------------States 4 Transitions 12

Hits % Covered ---- --------3 75.0 9 75.0

Design Unit: work.vhdl_toggle(arch_toggle) Enabled Coverage Active Hits % Covered

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Finite State Machines FSM Coverage Reports ---------------States Transitions -----3 3 ---- --------3 100.0 3 100.0

Coverage Summary by File

Data is collected for FSMs for all design units defined in each file and given in the report when the following command is used:
coverage report -select f -byFile

The format of the coverage summary by file is as follows:

Coverage Report Summary Data by file File: test.v Enabled Coverage ---------------States Transitions File: test.vhd Enabled Coverage ---------------States Transitions

Active -----4 12

Hits % Covered ---- --------3 75.0 9 75.0

Active -----3 3

Hits % Covered ---- --------3 100.0 3 100.0

Coverage Details by Instance

Coverage details for each FSM can also be reported by file, instance or design unit by appending the "-details" option to the above commands. These reports specify the states, and transitions of the FSMs along with the number of times they have been hit in the simulation. Those states and transitions which have not been hit are listed separately. The command used is:
coverage report -select f -byInst -details

The format of a coverage details report by instance is as follows:

# # # # # # # # # # # # # # # # Coverage Report by instance FSM Coverage: Inst ---------------------------/fsm_test_vhdl_10_config_rtl Num_Fsm ------1 States -----6 Hits ---6 % ----100.0 DU ----------------------------fsm_test_vhdl_10_config_rtl Transitions ----------17 Hits ---6 % ----35.3

=============================FSM Details============================= FSM Coverage for instance /fsm_test_vhdl_10_config_rtl --

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Finite State Machines FSM Coverage Reports # FSM_ID [0] # Current State Object : state # ---------------------# State Value MapInfo : # --------------------# State Name Value # -------------# st0 0000 # st1 0001 # st2 0010 # st3 0011 # st4 0100 # st5 1111 # Covered States : # ---------------# State Hit_count # ------------# st0 1 # st1 1 # st2 1 # st3 2 # st4 1 # st5 2 # Covered Transitions : # --------------------# Trans_ID Transition Hit_count # ------------------------# 4 st1 -> st2 1 # 7 st2 -> st3 1 # 9 st3 -> st3 1 # 10 st3 -> st4 1 # 13 st4 -> st0 1 # 15 st5 -> st5 1 # Uncovered Transitions : # ----------------------# Trans_ID Transition # ----------------# 0 st0 -> st0 # 1 st0 -> st1 # 2 st0 -> st5 # 3 st1 -> st1 # 5 st1 -> st5 # 6 st2 -> st2 # 8 st2 -> st5 # 11 st3 -> st5 # 12 st4 -> st4 # 14 st4 -> st5 # 16 st5 -> st0 # # Fsm_id States Hits % Transitions Hits % # ------- --------- ------------------ ----# 0 6 6 100.0 17 6 35.3

Coverage Details by Design Unit

The command used for reporting FSM coverage details by design unit is as follows:
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Finite State Machines FSM Coverage Reports coverage report -select f -byDu -details

The format of a coverage details report by design unit will look like the following:
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # Coverage Report by DU FSM Coverage: Inst ----DU ----------------------------fsm_test_vhdl_10_config_rtl States -----6 Hits ---6 % ----100.0 Transitions ----------17 Hits ---6 % ----35.3

Num_Fsm ------1

=============================FSM Details============================= FSM Coverage for Design Unit fsm_test_vhdl_10_config_rtl -FSM_ID [0] Current State Object : state ---------------------State Value MapInfo : --------------------State Name Value -------------st0 0000 st1 0001 st2 0010 st3 0011 st4 0100 st5 1111 Covered States : ---------------State Hit_count ------------st0 1 st1 1 st2 1 st3 2 st4 1 st5 2 Covered Transitions : --------------------Trans_ID Transition Hit_count ----------------- --------4 st1 -> st2 1 7 st2 -> st3 1 9 st3 -> st3 1 10 st3 -> st4 1 13 st4 -> st0 1 15 st5 -> st5 1 Uncovered Transitions : ----------------------Trans_ID Transition

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Finite State Machines FSM Coverage Reports # # # # # # # # # # # # # # # # # # # ----------------0 st0 -> st0 1 st0 -> st1 2 st0 -> st5 3 st1 -> st1 5 st1 -> st5 6 st2 -> st2 8 st2 -> st5 11 st3 -> st5 12 st4 -> st4 14 st4 -> st5 16 st5 -> st0 Inst DU ---- -----------------------------fsm_test_vhdl_10_config_rtl Fsm_id ------0 States -----6 Hits ---6 % ----100.0 Transitions ----------17 Hits ---6 % ----35.3

Coverage Details by File

The command used for reporting FSM coverage details by file is:
coverage report -select f -byFile -details

The format used to report FSM coverage details by file will look like the following:
# # # # # # # # # # # # # # # # # # # # # # # # # # # # Coverage Report by file FSM Coverage: File -------------------------------config_rtl_fsm_test_vhdl_10.vhdl Num_Fsm ------1 States -----6 Hits ---6 % ----100.0 Transitions ----------17 Hits ---6 % ----35.3

=============================FSM Details============================= FSM Coverage for file src/vhdl/fsm7/config_rtl_fsm_test_vhdl_10.vhdl --

FSM_ID [0] Current State Object : state ---------------------State Value MapInfo : --------------------State Name ---------st0 st1 st2 st3

Value ----0000 0001 0010 0011

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Finite State Machines FSM Coverage Reports # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # st4 0100 st5 1111 Covered States : ---------------State Hit_count ------------st0 1 st1 1 st2 1 st3 2 st4 1 st5 2 Covered Transitions : --------------------Trans_ID Transition Hit_count ------------------------4 st1 -> st2 1 7 st2 -> st3 1 9 st3 -> st3 1 10 st3 -> st4 1 13 st4 -> st0 1 15 st5 -> st5 1 Uncovered Transitions : ----------------------Trans_ID Transition ----------------0 st0 -> st0 1 st0 -> st1 2 st0 -> st5 3 st1 -> st1 5 st1 -> st5 6 st2 -> st2 8 st2 -> st5 11 st3 -> st5 12 st4 -> st4 14 st4 -> st5 16 st5 -> st0 File DU ---------------------------------------------------------------config_rtl_fsm_test_vhdl_10.vhdl vhdl fsm_test_vhdl_10_config_rtl Fsm_id ------0 States -----6 Hits ---6 % ----100.0 Transitions ----------17 Hits ---6 % ----35.3

Coverage Using the -zeros Option

When the -zeros option is given with the coverage report command the uncovered states and transitions will be reported. The coverage report will list the number of active states and transitions, the hits, and the percent covered. The format of the FSM coverage report using the -zeros option will appear as follows:
Coverage Report Summary Data by DU Design Unit: work.sm(fast)

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Finite State Machines FSM Coverage Reports Enabled Coverage ---------------States Transitions Active -----11 21 Hits % Covered ---- --------10 90.9 13 61.9

Coverage Using the -above, -below Options

Reports will be generated for those states and transitions whose coverage percentages fall within the given limits defined by the -above and -below options for the coverage report command. The format of the report will be as follows:
# # # # # # # # # # Coverage Report by file, with line data, having coverage > 10.0 percent FSM Coverage: File -------------------------------config_rtl_fsm_test_vhdl_10.vhdl Num_Fsm ------1 States -----6 Hits ---6 % ----100.0 Transitions ----------17 Hits ---6 % ----35.3

Coverage Using the -totals Option

Appending the -totals option to the coverage report command will give a summary of the all the states and transitions along with their hits and percentage coverages. The format of the report will be as follows:
# Coverage Report Totals BY FILES: Number of Files 0, # Active Statements 0, Hits 0, Statement Coverage Percentage 100.0 # Active Branches 0, Hits 0, Branch Coverage Percentage 100.0 # Active Conditions 0, Hits 0, Condition Coverage Percentage 100.0 # Active Expressions 0, Hits 0, Expression Coverage Percentage 100.0 # Active States 6, Hits 6, State Coverage Percentage 100.0 # Active Transitions 17, Hits 6, Transition Coverage Percentage 35.3 # # Coverage Report Totals BY INSTANCES: Number of Instances 1 # Active Statements 0, Hits 0, Statement Coverage Percentage 100.0 # Active Branches 0, Hits 0, Branch Coverage Percentage 100.0 # Active Conditions 0, Hits 0, Condition Coverage Percentage 100.0 # Active Expressions 0, Hits 0, Expression Coverage Percentage 100.0 # Active States 6, Hits 6, State Coverage Percentage 100.0 # Active Transitions 17, Hits 6, Transition Coverage Percentage 35.3

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FSM Coverage Exclusions

In ModelSim, any transition of an FSM can be excluded from the coverage reports using the coverage exclude command at the command line. See the coverage exclude command for details.

Using the coverage exclude Command

The coverage exclude command is used to exclude the specified transitions from coverage reports. Consider the following coverage report:
# FSM Coverage for du fsm_top-# # FSM_ID: state # Current State Object : state # ---------------------# State Value MapInfo : # --------------------# State Name Value # -------------# idle 0 # rd_wd_1 8 # wt_blk_1 3 # wt_wd_1 1 # ctrl 10 # wt_wd_2 2 # wt_blk_2 4 # wt_blk_3 5 # Covered Transitions : # --------------------# Trans_ID Transition # ----------------# 0 idle -> idle # 2 idle -> wt_wd_1 # 3 idle -> wt_blk_1 # 4 idle -> rd_wd_1 # 5 rd_wd_1 -> rd_wd_2 # 7 wt_blk_1 -> wt_blk_2 # 9 wt_wd_1 -> wt_wd_2

Hit_count --------9 4 2 6 6 2 4

The following are some examples of commands used to exclude data from the coverage report:
coverage exclude -du fsm_top -ftrans state all

excludes all transitions from the FSM whose FSM_ID is state in the design unit fsm_top.
coverage exclude -du fsm_top -ftrans state 2 3 4

excludes transitions numbered 2, 3 and 4 from the FSM whose FSM_ID is state, in the design unit fsm_top.
coverage exclude -inst /fsm_top/a1 -ftrans state all

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excludes all the transitions from the /fsm_top/a1 instance, in the FSM whose FSM_ID is state, in instance /fsm_top/a1.
coverage exclude -inst /fsm_top/a1 -ftrans state 2 3 4

excludes all the transitions numbered 2, 3 and 4 from the FSM whose FSM_ID is state, in instance /fsm_top/a1.

Using -clear with coverage exclude

When the -clear option is used with coverage exclude, it re-enables the reporting of those transitions which have been excluded. The transitions are specified in the same manner as that for the coverage exclude command. For example:
coverage exclude -clear -du fsm_test -ftrans <fsm_id> 2 3 4

re-enables the reporting of the specified transitions.

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Chapter 15 C Debug
C Debug allows you to interactively debug PLI/VPI/DPI/SystemC/C/C++ source code with the open-source gdb debugger. Even though C Debug doesnt provide access to all gdb features, you may wish to read gdb documentation for additional information. For debugging memory errors in C source files, please refer to the application note entitled Using the valgrind Tool with ModelSim. Note The functionality described in this chapter requires a cdebug license feature in your ModelSim license file. Please contact your Mentor Graphics sales representative if you currently do not have such a feature.

Tip: Please be aware of the following caveats before using C Debug:

C Debug is an interface to the open-source gdb debugger. We have not customized gdb source code, and C Debug doesnt remove any of the limitations or bugs of gdb. We assume that you are competent with C or C++ coding and C debugging in general. Recommended usage is that you invoke C Debug once for a given simulation and then quit both C Debug and ModelSim. Starting and stopping C Debug more than once during a single simulation session may cause problems for gdb. The gdb debugger has a known bug that makes it impossible to set breakpoints reliably in constructors or destructors. Be careful while stepping through code which may end up calling constructors of SystemC objects; it may crash the debugger. Generally you should not have an existing .gdbinit file. If you do, make certain you havent done any of the following: defined your own commands or renamed existing commands; used 'set annotate...', 'set height...', 'set width...', or 'set print...'; set breakpoints or watchpoints. To use C Debug on Windows platforms, you must compile your source code with gcc/g++. See Running C Debug on Windows Platforms below.

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Supported Platforms and gdb Versions

ModelSim ships with the gdb 6.0 debugger. Testing has shown this version to be the most reliable for SystemC applications. However, for FLI/PLI/DPI applications, you can also use a current installation of gdb if you prefer. For gcc versions 4.0 and above, gdb version 6.1 (or later) is required. C Debug has been tested on these platforms with these versions of gdb: Table 15-1. Supported Platforms and gdb Versions Platform 32-bit Solaris 8, 9
1 2 3

Required gdb version gdb-5.0-sol-2.6 wdb version 3.3 or later wdb version 4.2 /usr/bin/gdb 5.2 or later gdb 6.0 from MinGW-32 gdb 6.0 or later /usr/bin/gdb 5.2 or later gdb 5.3.92 or 6.1.1

32- and 64-bit HP-UX 11.0 , 11.11 32-bit Redhat Linux 7.2 or later 32-bit Windows 2000 and XP
1

64-bit HP-UX B.11.22 on Itanium 2

Opteron / SuSE Linux 9.0 or Redhat EWS 3.0 (32-bit mode only)1 x86 / Redhat Linux 6.0 to 7.11 Opteron & Athlon 64 / Redhat EWS 3.0

1. ModelSim ships gdb 6.3 for Solaris 8, 9 and Linux platforms. 2. You must install kernel patch PHKL_22568 (or a later patch that supersedes PHKL_22568) on HP-UX 11.0. If you do not, you will see the following error message when trying to enable C Debug: # Unable to find dynamic library list. # error from C debugger 3. You must install B.11.11.0306 Gold Base Patches for HP-UX 11i, June 2003.

To invoke C Debug, you must have the following: A cdebug license feature. The correct gdb debugger version for your platform.

Running C Debug on Windows Platforms

To use C Debug on Windows, you must compile your C/C++ source code using the gcc/g++ compiler supplied with ModelSim. Source compiled with Microsoft Visual C++ is not debuggable using C Debug. The g++ compiler is installed in the following location:

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C Debug Setting Up C Debug ../modeltech/gcc-3.2.3-mingw32/

Setting Up C Debug
Before viewing your SystemC/C/C++ source code, you must set up the C Debug path and options. To set up C Debug, follow these steps: 1. Compile and link your C code with the -g switch (to create debug symbols) and without -O (or any other optimization switches you normally use). See SystemC Simulation for information on compiling and linking SystemC code. Refer to the chapter Verilog PLI/VPI/DPI for information on compiling and linking C code. 2. Specify the path to the gdb debugger by selecting Tools > C Debug > C Debug Setup Figure 15-1. Specifying Path in C Debug setup Dialog

Select "default" to point at the supplied version of gdb or "custom" to point at a separate installation. 3. Start the debugger by selecting Tools > C Debug > Start C Debug. ModelSim will start the debugger automatically if you set a breakpoint in a SystemC file. 4. If you are not using gcc, or otherwise havent specified a source directory, specify a source directory for your C code with the following command:
ModelSim> gdb dir <srcdirpath1>[:<srcdirpath2>[...]]

Running C Debug from a DO File

You can run C Debug from a DO file but there is a configuration issue of which you should be aware. It takes C Debug a few moments to start-up. If you try to execute a run command before C Debug is fully loaded, you may see an error like the following:
# # # # # ** Error: Stopped in C debugger, unable to real_run mti_run 10us Error in macro ./do_file line 8 Stopped in C debugger, unable to real_run mti_run 10us while executing "run 10us

In your DO file, add the command cdbg_wait_for_starting to alleviate this problem. For example:

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C Debug Setting Breakpoints cdbg enable_auto_step on cdbg set_debugger /modelsim/5.8c_32/common/linux cdbg debug_on cdbg_wait_for_starting run 10us

Setting Breakpoints
Breakpoints in C Debug work much like normal HDL breakpoints. You can create and edit them with ModelSim commands (bp, bd, enablebp, disablebp) or via a Source window in the GUI (see File-line breakpoints). Some differences do exist: The Breakpoints dialog in the ModelSim GUI doesnt list C breakpoints. C breakpoint id numbers require a "c." prefix when referenced in a command. When using the bp command to set a breakpoint in a C file, you must use the -c argument.

Here are some example commands:

bp -c *0x400188d4

Sets a C breakpoint at the hex address 400188d4. Note the * prefix for the hex address.
bp -c or_checktf

Sets a C breakpoint at the entry to function or_checktf.

bp -c or.c 91

Sets a C breakpoint at line 91 of or.c.

bp -c -cond "x < 5" foo.c 10

Sets a C breakpoint at line 10 of source file foo.c for the condition expression x < 5.
enablebp c.1

Enables C breakpoint number 1. The graphic below shows a C file with one enabled breakpoint (on line 44) and one disabled breakpoint (on line 48).

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Figure 15-2. Setting Breakpoints in Source Code

Clicking the red diamonds with your right (third) mouse button pops up a menu with commands for removing or enabling/disabling the breakpoints. Figure 15-3. Right Click Pop-up Menu on Breakpoint

Note The gdb debugger has a known bug that makes it impossible to set breakpoints reliably in constructors or destructors. Do not set breakpoints in constructors of SystemC objects; it may crash the debugger.

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Stepping in C Debug
Stepping in C Debug works much like you would expect. You use the same buttons and commands that you use when working with an HDL-only design. Table 15-2. Simulation Stepping Options in C Debug Button Menu equivalent Tools > C Debug > Step steps the current simulation Run > Step to the next statement; if the next statement is a call to a C function that was compiled with debug info, ModelSim will step into the function Tools > C Debug > Step Over statements are executed but Run > Step -Over treated as simple statements instead of entered and traced line-by-line; C functions are not stepped into unless you have an enabled breakpoint in the C file Tools > C Debug > Continue Run Run > Continue continue the current simulation run until the end of the specified run length or until it hits a breakpoint or specified break event Other equivalents use the step command at the CDBG> prompt see: step command

use the step -over command at the CDBG> prompt see: step command

use the run -continue command at the CDBG> prompt see: run command

Known Problems With Stepping in C Debug

The following are known limitations which relate to problems with gdb: The gdb debugger has a known bug that makes it impossible to set breakpoints reliably in constructors or destructors. Be careful while stepping through code which may end up calling constructors of SystemC objects; it may crash the debugger. With some platform and compiler versions, step may actually behave like run -continue when in a C file. This is a gdb quirk that results from not having any debugging information when in an internal function to VSIM (i.e., any FLI or VPI function). In these situations, use step -over to move line-by-line.

Quitting C Debug
To end a debugging session, you can do one of the following.

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From the GUI: Select Tools > C Debug > Quit C Debug. From the command line, enter the following in the Transcript window:
cgdb quit

Note Recommended usage is that you invoke C Debug once for a given simulation and then quit both C Debug and ModelSim. Starting and stopping C Debug more than once during a single simulation session may cause problems for gdb.

Finding Function Entry Points with Auto Find bp

ModelSim can automatically locate and set breakpoints at all currently known function entry points (i.e., PLI/VPI/DPI system tasks and functions and callbacks). Select Tools > C Debug > Auto find bp to invoke this feature. The Auto find bp command provides a "snapshot" of your design when you invoke the command. If additional callbacks get registered later in the simulation, ModelSim will not identify these new function entry points unless you re-execute the Auto find bp command. If you want functions to be identified regardless of when they are registered, use Identifying All Registered Function Calls instead. The Auto find bp command sets breakpoints in an enabled state and doesnt toggle that state to account for step -over or run -continue commands. This may result in unexpected behavior. For example, say you have invoked the Auto find bp command and you are currently stopped on a line of code that calls a C function. If you execute a step -over or run -continue command, ModelSim will stop on the breakpoint set in the called C file.

Identifying All Registered Function Calls

Auto step mode automatically identifies and sets breakpoints at registered function calls (i.e., PLI/VPI system tasks and functions and callbacks). Auto step mode is helpful when you are not entirely familiar with a design and its associated C routines. As you step through the design, ModelSim steps into and displays the associated C file when you hit a C function call in your HDL code. If you execute a step -over or run -continue command, ModelSim does not step into the C code. When you first enable Auto step mode, ModelSim scans your design and sets enabled breakpoints at all currently known function entry points. As you step through the simulation, Auto step continues looking for newly registered callbacks and sets enabled breakpoints at any new entry points it identifies. Once you execute a step -over or run -continue command, Auto step disables the breakpoints it set, and the simulation continues running. The next time you

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execute a step command, the automatic breakpoints are re-enabled and Auto step sets breakpoints on any new entry points it identifies. Note that Auto step does not disable user-set breakpoints.

Enabling Auto Step Mode

To enable Auto step mode, follow these steps: 1. Configure C Debug as described in Setting Up C Debug. 2. Select Tools > C Debug > Enable auto step. 3. Load and run your design. Example The graphic below shows a simulation that has stopped at a user-set breakpoint on a PLI system task. Figure 15-4. Simulation Stopped at Breakpoint on PLI Task

Because Auto step mode is enabled, ModelSim automatically sets a breakpoint in the underlying xor_gate.c file. If you click the step button at this point, ModelSim will step into that file.

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C Debug Debugging Functions During Elaboration

Figure 15-5. Stepping into Next File

Auto Find bp Versus Auto Step Mode

As noted in Finding Function Entry Points with Auto Find bp, the Auto find bp command also locates and sets breakpoints at function entry points. Note the following differences between Auto find bp and Auto step mode: Auto find bp provides a "snapshot" of currently known function entry points at the time you invoke the command. Auto step mode continues to locate and set automatic breakpoints in newly registered function calls as the simulation continues. In other words, Auto find bp is static while Auto step mode is dynamic. Auto find bp sets automatic breakpoints in an enabled state and doesnt change that state to account for step-over or run-continue commands. Auto step mode enables and disables automatic breakpoints depending on how you step through the design. In cases where you invoke both features, Auto step mode takes precedence over Auto find bp. In other words, even if Auto find bp has set enabled breakpoints, if you then invoke Auto step mode, it will toggle those breakpoints to account for step-over and run-continue commands.

Debugging Functions During Elaboration

Initialization mode allows you to examine and debug functions that are called during elaboration (i.e., while your design is in the process of loading). When you select this mode, ModelSim sets special breakpoints for foreign architectures and PLI/VPI modules that allow you to set breakpoints in the initialization functions. When the design finishes loading, the

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special breakpoints are automatically deleted, and any breakpoints that you set are disabled (unless you specify Keep user init bps in the C debug setup dialog). To run C Debug in initialization mode, follow these steps: 1. Start C Debug by selecting Tools > C Debug > Start C Debug before loading your design. 2. Select Tools > C Debug > Init mode. 3. Load your design. As the design loads, ModelSim prints to the Transcript the names and/or hex addresses of called functions. For example the Transcript below shows a function pointer to a foreign architecture: Figure 15-6. Function Pointer to Foreign Architecture

To set a breakpoint on that function, you would type:

bp -c *0x4001b571

or
bp -c and_gate_init

ModelSim in turn reports that it has set a breakpoint at line 37 of the and_gate.c file. As you continue through the design load using run -continue, ModelSim hits that breakpoint and displays the file and associated line in a Source window.

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Figure 15-7. Highlighted Line in Associated File

PLI Functions in Initialization Mode

There are two methods for registering callback functions in the PLI: 1) using a veriusertfs array to define all usertf entries; and 2) adding an init_usertfs function to explicitly register each usertfs entry (see Registering PLI Applications for more details). The messages ModelSim produces in initialization mode vary depending on which method you use.

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ModelSim produces a Transcript message like the following when it encounters a veriusertfs array during initialization:
# vsim -pli ./veriuser.sl mux_tb # Loading ./veriuser.sl # Shared object file './veriuser.sl' # veriusertfs array - registering calltf # Function ptr '0x40019518'. $or_c. # C breakpoint c.1 # 0x0814fc96 in mti_cdbg_shared_objects_loaded cont # Shared object file './veriuser.sl' # veriusertfs array - registering checktf # Function ptr '0x40019570'. $or_c. # C breakpoint c.1 # 0x0814fc96 in mti_cdbg_shared_objects_loaded cont # Shared object file './veriuser.sl' # veriusertfs array - registering sizetf # Function ptr '0x0'. $or_c. # C breakpoint c.1 # 0x0814fc96 in mti_cdbg_shared_objects_loaded cont # Shared object file './veriuser.sl' # veriusertfs array - registering misctf # Function ptr '0x0'. $or_c. # C breakpoint c.1 # 0x0814fc96 in mti_cdbg_shared_objects_loaded

()

()

()

()

You can set breakpoints on non-null callbacks using the function pointer (e.g., bp -c *0x40019570). You cannot set breakpoints on null functions. The sizetf and misctf entries in the example above are null (the function pointer is '0x0'). ModelSim reports the entries in multiples of four with at least one entry each for calltf, checktf, sizetf, and misctf. Checktf and sizetf functions are called during initialization but calltf and misctf are not called until runtime. The second registration method uses init_usertfs functions for each usertfs entry. ModelSim produces a Transcript message like the following when it encounters an init_usertfs function during initialization:
# Shared object file './veriuser.sl' # Function name 'init_usertfs' # Function ptr '0x40019bec'. Before first call of init_usertfs. # C breakpoint c.1 # 0x0814fc96 in mti_cdbg_shared_objects_loaded ()

You can set a breakpoint on the function using either the function name (i.e., bp -c init_usertfs) or the function pointer (i.e., bp -c *0x40019bec). ModelSim will hit this breakpoint as you continue through initialization.

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VPI Functions in Initialization Mode

VPI functions are registered via routines placed in a table named vlog_startup_routines (see Registering PLI Applications for more details). ModelSim produces a Transcript message like the following when it encounters a vlog_startup_routines table during initialization:
# Shared object file './vpi_test.sl' # vlog_startup_routines array # Function ptr '0x4001d310'. Before first call using function pointer. # C breakpoint c.1 # 0x0814fc96 in mti_cdbg_shared_objects_loaded ()

You can set a breakpoint on the function using the function pointer (i.e., bp -c *0x4001d310). ModelSim will hit this breakpoint as you continue through initialization.

Completing Design Load

If you are through looking at the initialization code you can select Tools > C Debug > Complete load at any time, and ModelSim will continue loading the design without stopping. The one exception to this is if you have set a breakpoint in a LoadDone callback and also specified Keep user init bps in the C Debug setup dialog.

Debugging Functions when Quitting Simulation

Stop on quit mode allows you to debug functions that are called when the simulator exits. Such functions include those referenced by an misctf function called by a quit or $finish in PLI code, or cbEndofSimulation function called by a quit or $finish in VPI code. To enable Stop on quit mode, follow these steps: 1. Start C Debug by selecting Tools > C Debug > Start C Debug. 2. Select Tools > C Debug > C Debug Setup. 3. Select Stop on quit in the C Debug setup dialog. Figure 15-8. Stop on quit Button in Dialog

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With this mode enabled, if you have set a breakpoint in a quit callback function, C Debug will stop at the breakpoint after you issue the quit command in ModelSim. This allows you to step and examine the code in the quit callback function. Invoke run -continue when you are done looking at the C code. Note that whether or not a C breakpoint was hit, when you return to the VSIM> prompt, youll need to quit C Debug by selecting Tools > C Debug > Quit C Debug before finally quitting the simulation.

C Debug Command Reference

The table below provides a brief description of the commands that can be invoked when C Debug is running. Follow the links to the Reference Manual for complete command syntax. Table 15-3. Command Reference for C Debug Command bd Description deletes a previously set C breakpoint sets a C breakpoint changes the value of a C variable Corresponding menu command right click breakpoint in Source window and select Remove Breakpoint click the desired line number in the Source window none

bp -c change describe

prints the type information of a C select the C variable name in the variable Source window and select Tools > Describe or right click and select Describe. disables a previously set C breakpoint enables a previously disabled C breakpoint prints the value of a C variable right click breakpoint in Source window and select Disable Breakpoint right click breakpoint in Source window and select Enable Breakpoint select the C variable name in the Source window and select Tools > Examine or right click and select Examine none none

disablebp

enablebp

examine

gdb dir pop

sets the source directory search path for the C debugger moves the specified number of call frames up the C callstack

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Table 15-3. Command Reference for C Debug Command push run -continue Description moves the specified number of call frames down the C callstack continues running the simulation after stopping Corresponding menu command none click the run -continue button on the Main or Source window toolbar

run -finish

continues running the simulation Tools > C Debug > Run > Finish until control returns to the calling function Tools > C Debug > Show displays the names and types of the local variables and arguments of the current C function click the step or step -over button single step in the C debugger to on the Main or Source window the next executable line of C toolbar code; step goes into function calls, whereas step -over does not displays a stack trace of the C call stack Tools > C Debug > Traceback

show

step

tb

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Chapter 16 Profiling Performance and Memory Use

The ModelSim profiler combines a statistical sampling profiler with a memory allocation profiler to provide instance specific execution and memory allocation data. It allows you to quickly determine how your memory is being allocated and easily identify areas in your simulation where performance can be improved. The profiler can be used at all levels of design simulation Functional, RTL, and Gate Level and has the potential to save hours of regression test time. In addition, ASIC and FPGA design flows benefit from the use of this tool. Note The functionality described in this chapter requires a profiler license feature in your ModelSim license file. Please contact your Mentor Graphics sales representative if you currently do not have such a feature. Profiling is not supported on Opteron / Athlon 64 platforms.

Introducing Performance and Memory Profiling

The profiler provides an interactive graphical representation of both memory and CPU usage on a per instance basis. It shows you what part of your design is consuming resources (CPU cycles or memory), allowing you to more quickly find problem areas in your code. The profiler enables those familiar with the design and validation environment to find first-level improvements in a matter of minutes. For example, the statistical sampling profiler might show the following: non-accelerated VITAL library cells that are impacting simulation run time objects in the sensitivity list that are not required, resulting in a process that consumes more simulation time than necessary a testbench process that is active even though it is not needed an inefficient C module random number processes that are consuming simulation resources in a testbench running in non-random mode

With this information, you can make changes to the VHDL or Verilog source code that will speed up the simulation.

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The memory allocation profiler provides insight into how much memory different parts of the design are consuming. The two major areas of concern are typically: 1) memory usage during elaboration, and 2) during simulation. If memory is exhausted during elaboration, for example, memory profiling may provide insights into what part(s) of the design are memory intensive. Or, if your HDL or PLI code is allocating memory and not freeing it when appropriate, the memory profiler will indicate excessive memory use in particular portions of the design.

Statistical Sampling Profiler

The profilers statistical sampling profiler samples the current simulation at a user-determined rate (every <n> milliseconds of real or "wall-clock" time, not simulation time) and records what is executing at each sample point. The advantage of statistical sampling is that an entire simulation need not be run to get good information about what parts of your design are using the most simulation time. A few thousand samples, for example, can be accumulated before pausing the simulation to see where simulation time is being spent. The statistical profiler reports only on the samples that it can attribute to user code. For example, if you use the -nodebug argument to vcom or vlog, it cannot report sample results.

Memory Allocation Profiler

The profilers memory allocation profiler records every memory allocation and deallocation that takes place in the context of elaborating and simulating the design. It makes a record of the design element that is active at the time of allocation so memory resources can be attributed to appropriate parts of the design. This provides insights into memory usage that can help you recode designs to, for example, minimize memory use, correct memory leaks, and change optimization parameters used at compile time.

Getting Started with the Profiler

Memory allocation profiling and statistical sampling are enabled separately.

Enabling the Memory Allocation Profiler

To record memory usage during elaboration and simulation, enable memory allocation profiling when the design is loaded with the -memprof argument to the vsim command.
vsim -memprof <design_unit>

Note that profile-data collection for the call tree is off by default. See The Call Tree View for additional information on collecting call-stack data. You can use the graphic user interface as follows to perform the same task.

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1. Select Simulate > Start Simulation or the Simulate icon, to open the Start Simulation dialog box. 2. Select the Others tab. 3. Click the Enable memory profiling checkbox to select it. 4. Click OK to load the design with memory allocation profiling enabled. If memory allocation during elaboration is not a concern, the memory allocation profiler can be enabled at any time after the design is loaded by doing any one of the following: select Tools > Profile > Memory use the -m argument with the profile on command
profile on -m

click the Memory Profiling icon

Handling Large Files

To allow memory allocation profiling of large designs, where the design itself plus the data required to keep track of memory allocation exceeds the memory available on the machine, the memory profiler allows you to route raw memory allocation data to an external file. This allows you to save the memory profile with minimal memory impact on the simulator, regardless of the size of your design. The external data file is created during elaboration by using either the -memprof+file=<filename> or the -memprof+fileonly=<filename> argument with the vsim command. The -memprof+file=<filename> option will collect memory profile data during both elaboration and simulation and save it to the named external file and makes the data available for viewing and reporting during the current simulation. The -memprof+fileonly=<filename> option will collect memory profile data during both elaboration and simulation and save it to only the named external file. No data is saved for viewing and reporting during the current simulation, which reduces the overall amount of memory required by memory allocation profiling. Alternatively, you can save memory profile data from the simulation only by using either the -m -file <filename> or the -m -fileonly <filename> argument with the profile on command. The -m -file <filename> option saves memory profile data from simulation to the designated external file and makes the data available for viewing and reporting during the current simulation.

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The -m -fileonly <filename> option saves memory profile data from simulation to only the designated external file. No data is saved for viewing and reporting during the current simulation, which reduces the overall amount of memory required by memory allocation profiling. After elaboration and/or simulation is complete, a separate session can be invoked and the profile data can be read in with the profile reload command for analysis. It should be noted, however, that this command will clear all performance and memory profiling data collected to that point (implicit profile clear). Any currently loaded design will be unloaded (implicit quit -sim), and run-time profiling will be turned off (implicit profile off -m -p). If a new design is loaded after you have read the raw profile data, then all internal profile data is cleared (implicit profile clear), but run-time profiling is not turned back on.

Enabling the Statistical Sampling Profiler

To enable the profilers statistical sampling profiler prior to a simulation run, do any one of the following: select Tools > Profile > Performance use the profile on command click the Performance Profiling icon

Collecting Memory Allocation and Performance Data

Both memory allocation profiling and statistical sampling occur during the execution of a ModelSim run command. With profiling enabled, all subsequent run commands will collect memory allocation data and performance statistics. Profiling results are cumulative each run command performed with profiling enabled will add new information to the data already gathered. To clear this data, select Tools > Profile > Clear Profile Data or use the prole clear command. With the profiler enabled and a run command initiated, the simulator will provide a "Profiling" message in the transcript to indicate that profiling has started. If the statistical sampling profiler and the memory allocation profiler are on, the status bar will display the number of Profile Samples collected and the amount of memory allocated, as shown below. Each profile sample will become a data point in the simulations performance profile. Figure 16-1. Status Bar: Profile Samples

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Turning Profiling Off

You can turn off the statistical sampling profiler or the memory allocation profiler by doing any one of the following: deselect the Performance and/or Memory options in the Tools > Profile menu deselect the Performance Profiling and Memory Profiling icons in the toolbar use the profile off command with the -p or -m arguments.

Any ModelSim run commands that follow will not be profiled.

Running the Profiler on Windows with PLI/VPI Code

If you need to run the profiler under Windows on a design that contains PLI/VPI code, add these two switches to the compiling/linking command:
/DEBUG /DEBUGTYPE:COFF

These switches add symbols to the .dll file that the profiler can use in its report.

Interpreting Profiler Data

The utility of the data supplied by the profiler depends in large part on how your code is written. In cases where a single model or instance consumes a high percentage of simulation time or requires a high percentage of memory, the statistical sampling profiler or the memory allocation profiler quickly identifies that object, allowing you to implement a change that runs faster or requires less memory. More commonly, simulation time or memory allocation will be spread among a handful of modules or entities for example, 30% of simulation time split between models X, Y, and Z; or 20% of memory allocation going to models A, B, C and D. In such situations, careful examination and improvement of each model may result in overall speed improvement or more efficient memory allocation. There are times, however, when the statistical sampling and memory allocation profilers tell you nothing more than that simulation time or memory allocation is fairly equally distributed throughout your design. In such situations, the profiler provides little helpful information and improvement must come from a higher level examination of how the design can be changed or optimized.

Viewing Profiler Results

The profiler provides three views of the collected data Ranked, Call Tree and Structural. All three views are enabled by selecting View > Windows > Profile or by typing view profilemain

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at the VSIM prompt. This opens the Profile pane. The Profile pane includes selection tabs for the Ranked, Call Tree, and Structural views. Note The Profile pane, by default, only shows performance and memory profile data equal to or greater than 1 percent. You can change this with the Profile Cutoff tool in the Profiler Toolbar.

The Ranked View

The Ranked view displays the results of the statistical performance profiler and the memory allocation profiler for each function or instance. By default, ranked profiler results are sorted by values in the In% column, which shows the percentage of the total samples collected for each function or instance. You can sort ranked results by any other column by simply clicking the column heading. Click the down arrow to the left of the Name column to open a Configure Columns dialog, which allows you to select which columns are to be hidden or displayed. The use of colors in the display provides an immediate visual indication of where your design is spending most of its simulation time. By default, red text indicates functions or instances that are consuming 5% or more of simulation time. Figure 16-2. Profile Pane: Ranked Tab

The Ranked view does not provide hierarchical, function-call information.

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The Call Tree View

Data collection for the call tree is off by default, due to the fact that it will increase the simulation time and resource usage. Collection can be turned on from the VSIM command prompt with profile option collect_calltrees on and off with profile option collect_calltrees off. Call stack data collection can also be turned on with the -memprof+call argument to the vsim command. By default, profiler results in the Call Tree view are sorted according to the Under(%) column, which shows the percentage of the total samples collected for each function or instance and all supporting routines or instances. Sort results by any other column by clicking the column heading. As in the Ranked view, red object names indicate functions or instances that, by default, are consuming 5% or more of simulation time. The Call Tree view differs from the Ranked view in two important respects. Entries in the Name column of the Call Tree view are indented in hierarchical order to indicate which functions or routines call which others. A %Parent column in the Call Tree view allows you to see what percentage of a parent routines simulation time is used in which subroutines.

The Call Tree view presents data in a call-stack format that provides more context than does the ranked view about where simulation time is spent. For example, your models may contain several instances of a utility function that computes the maximum of 3-delay values. A Ranked view might reveal that the simulation spent 60% of its time in this utility function, but would not tell you which routine or routines were making the most use of it. The Call Tree view will reveal which line is calling the function most frequently. Using this information, you might decide that instead of calling the function every time to compute the maximum of the 3-delays, this spot in your VHDL code can be used to compute it just once. You can then store the maximum delay value in a local variable. The two %Parent columns in the Call Tree view show the percent of simulation time or allocated memory a given function or instance is using of its parents total simulation time or available memory. From these columns, you can calculate the percentage of total simulation time or memory taken up by any function. For example, if a particular parent entry used 10% of the total simulation time or allocated memory, and it called a routine that used 80% of its simulation time or memory, then the percentage of total simulation time spent in, or memory allocated to, that routine would be 80% of 10%, or 8%. In addition to these differences, the Ranked view displays any particular function only once, regardless of where it was used. In the Call Tree view, the function can appear multiple times each time in the context of where it was used.

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Figure 16-3. Profile Pane: Call Tree Tab

The Structural View

The Structural view displays instance-specific performance and memory profile information in a hierarchical structure format identical to the structural view in the Workspace. It contains the same information found in the Call Tree view but adds an additional dimension with which to categorize performance samples and memory allocation. It shows how call stacks are associated with different instances in the design. For example, in the illustration that follows, TCL_Flush and TCL_Close appear under both test_sm and sm_0. Figure 16-4. Profile Pane: Structural Tab

In the Call Tree and Structural views, you can expand and collapse the various levels to hide data that is not useful to the current analysis and/or is cluttering the display. Click on the '+' box

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next to an object name to expand the hierarchy and show supporting functions and/or instances beneath it. Click the '-' box to collapse all levels beneath the entry. Note that profile-data collection for the call tree is off by default. See The Call Tree View for additional information on collecting call-stack data. You can also right click any function or instance in the Call Tree and Structural views to obtain popup menu selections for rooting the display to the currently selected item, to ascend the displayed root one level, or to expand and collapse the hierarchy.

Toggling Display of Call Stack Entries

By default call stack entries do not display in the Structural tab. To display call stack entries, right-click in the pane and select Show Calls.

Viewing Profile Details

The Profiler increases visibility into simulation performance and memory usage with dynamic links to the Source window and the Profile Details pane. The Profile Details pane is enabled by selecting View > Windows > Profile Details or by entering the view profiledetails command at the VSIM prompt. You can also right-click any function or instance in the Ranked, Call Tree, or Structural views to open a popup menu that includes options for viewing profile details. The following options are available: View Source opens the Source window to the location of the selected function. View Instantiation opens the Source window to the location of the instantiation. Function Usage opens the Profile Details pane and displays all instances using the selected function. In the Profile Details pane shown below, all the instances using function Tcl_Close are displayed. The statistical performance and memory allocation data shows how much simulation time and memory is used by Tcl_Close in each instance.

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Figure 16-5. Profile Details Pane: Function Usage

Instance Usage opens the Profile Details pane and displays all instances with the same definition as the selected instance. Figure 16-6. Profile Details: Instance Usage

View Instantiation opens the Source window to the point in the source code where the selected instance is instantiated. Callers and Callees opens the Profile Details pane and displays the callers and callees for the selected function. Items above the selected function are callers; items below are callees. The selected function is distinguished with an arrow on the left and in 'hotForeground' color as shown below.

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Figure 16-7. Profile Details: Callers and Callees

Display in Call Tree expands the Call Tree view of the Profile window and displays all occurrences of the selected function and puts the selected function into a search buffer so you can easily cycle across all occurrences of that function. Note that profile-data collection for the call tree is off by default. See The Call Tree View for additional information on collecting call-stack data.

Display in Structural expands the Structural view of the Profile window and displays all occurrences of the selected function and puts the selected function into a search buffer so you can easily cycle across all occurrences of that function.

Integration with Source Windows

The Ranked, Call Tree and Structural profile views are all dynamically linked to Source window. You can double-click any function or instance in the Ranked, Call Tree and Structural views to bring up that object in a Source window with the selected line highlighted.

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Figure 16-8. Accessing Source from Profile Views

You can perform the same task by right-clicking any function or instance in any one of the three Profile views and selecting View Source from the popup menu that opens. When you right-click an instance in the Structural profile view, the View Instantiation selection will become active in the popup menu. Selecting this option opens the instantiation in a Source window and highlights it. The right-click popup menu also allows you to change the root instance of the display, ascend to the next highest root instance, or reset the root instance to the top level instance. The selection of a context in the structure tab of the Workspace pane will cause the root display to be set in the Structural view.

Analyzing C Code Performance

You can include C code in your design via SystemC, the Verilog PLI/VPI. The profiler can be used to determine the impact of these C modules on simulator performance. Factors that can affect simulator performance when a design includes C code are as follows: PLI applications with large sensitivity lists Calling operating system functions from C code

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Calling the simulators command interpreter from C code Inefficient C code

In addition, the Verilog PLI/VPI requires maintenance of the simulators internal data structures as well as the PLI/VPI data structures for portability.

Reporting Profiler Results

You can create performance and memory profile reports using the Profile Report dialog or the profile report command. For example, the command
profile report -calltree -file calltree.rpt -cutoff 2

will produce a Call Tree profile report in a text file called calltree.rpt, as shown here.

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Figure 16-9. Profile Report Example

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Select Tools > Profile > Profile Report to open the Profile Report dialog. The Profile Report dialog allows you to select the following performance profile type for reporting: Call Tree, Ranked, Structural, Callers and Callees, Function to Instance, and Instances using the same definition. When the Structural profile type is selected, you can designate the root instance pathname, include function call hierarchy, and specify the structure level to be reported. You can elect to report performance information only, memory information only, or a both. By default, all data collected will be reported. Both performance and memory data will be displayed with a default cutoff of 0% - meaning, the report will contain any functions or instances that use simulation time or memory - unless you specify a different cutoff percentage. You may elect to write the report directly to the Transcript window or to a file. If the "View file" box is selected, the profile report will be generated and immediately displayed in Notepad when the OK button is clicked. Figure 16-10. Profile Report Dialog Box

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Chapter 17 Signal Spy

The Verilog language allows access to any signal from any other hierarchical block without having to route it via the interface. This means you can use hierarchical notation to either assign or determine the value of a signal in the design hierarchy from a testbench. This capability fails when a Verilog testbench attempts to reference a signal in a VHDL block or reference a signal in a Verilog block through a VHDL level of hierarchy. This limitation exists because VHDL does not allow hierarchical notation. In order to reference internal hierarchical signals, you have to resort to defining signals in a global package and then utilize those signals in the hierarchical blocks in question. But, this requires that you keep making changes depending on the signals that you want to reference. The Signal Spy procedures and system tasks overcome the aforementioned limitations. They allow you to monitor (spy), drive, force, or release hierarchical objects in a VHDL or mixed design. The VHDL procedures are provided via the Util Package within the modelsim_lib library. To access the procedures you would add lines like the following to your VHDL code:
library modelsim_lib; use modelsim_lib.util.all;

The Verilog tasks are available as built-in System Tasks and Functions. The table below shows the VHDL procedures and their corresponding Verilog system tasks. Table 17-1. Signal Spy: Mapping VHDL Procedures to Verilog System Tasks VHDL procedures disable_signal_spy enable_signal_spy init_signal_driver init_signal_spy signal_force signal_release Verilog system tasks $disable_signal_spy $enable_signal_spy $init_signal_driver $init_signal_spy $signal_force $signal_release

Designed for Testbenches

Signal Spy limits the portability of your code. HDL code with Signal Spy procedures or tasks works only in ModelSim, not other simulators. We therefore recommend using Signal Spy only
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in testbenches, where portability is less of a concern, and the need for such a tool is more applicable.

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Signal Spy disable_signal_spy

disable_signal_spy
The disable_signal_spy() procedure disables the associated init_signal_spy. The association between the disable_signal_spy call and the init_signal_spy call is based on specifying the same src_object and dest_object arguments to both functions. The disable_signal_spy call can only affect init_signal_spy calls that had their control_state argument set to "0" or "1". Syntax disable_signal_spy(<src_object>, <dest_object>, <verbose>) Returns Nothing Arguments src_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. This path should match the path that was specified in the init_signal_spy call that you wish to disable. dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. This path should match the path that was specified in the init_signal_spy call that you wish to disable. verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the transcript stating that a disable occurred and the simulation time that it occurred. Default is 0, no message Related procedures init_signal_spy, enable_signal_spy Example See init_signal_spy Example

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enable_signal_spy
The enable_signal_spy() procedure enables the associated init_signal_spy. The association between the enable_signal_spy call and the init_signal_spy call is based on specifying the same src_object and dest_object arguments to both functions. The enable_signal_spy call can only affect init_signal_spy calls that had their control_state argument set to "0" or "1". Syntax enable_signal_spy(<src_object>, <dest_object>, <verbose>) Returns Nothing Arguments src_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. This path should match the path that was specified in the init_signal_spy call that you wish to enable. dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. This path should match the path that was specified in the init_signal_spy call that you wish to enable. verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the transcript stating that an enable occurred and the simulation time that it occurred. Default is 0, no message Related procedures init_signal_spy, disable_signal_spy Example See init_signal_spy Example

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Signal Spy init_signal_driver

init_signal_driver
The init_signal_driver() procedure drives the value of a VHDL signal or Verilog net (called the src_object) onto an existing VHDL signal or Verilog net (called the dest_object). This allows you to drive signals or nets at any level of the design hierarchy from within a VHDL architecture (e.g., a testbench). The init_signal_driver procedure drives the value onto the destination signal just as if the signals were directly connected in the HDL code. Any existing or subsequent drive or force of the destination signal, by some other means, will be considered with the init_signal_driver value in the resolution of the signal. Call only once The init_signal_driver procedure creates a persistent relationship between the source and destination signals. Hence, you need to call init_signal_driver only once for a particular pair of signals. Once init_signal_driver is called, any change on the source signal will be driven on the destination signal until the end of the simulation. Thus, we recommend that you place all init_signal_driver calls in a VHDL process. You need to code the VHDL process correctly so that it is executed only once. The VHDL process should not be sensitive to any signals and should contain only init_signal_driver calls and a simple wait statement. The process will execute once and then wait forever. See the example below. Syntax init_signal_driver(<src_object>, <dest_object>, <delay>, <delay_type>, <verbose>) Returns Nothing Arguments src_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to an existing VHDL signal or Verilog net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. delay Optional time value. Specifies a delay relative to the time at which the src_object changes. The delay can be an inertial or transport delay. If no delay is specified, then a delay of zero is assumed.

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delay_type Optional del_mode. Specifies the type of delay that will be applied. The value must be either mti_inertial or mti_transport. The default is mti_inertial.

verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the src_object is driving the dest_object. Default is 0, no message.

Related procedures init_signal_spy, signal_force, signal_release Limitations When driving a Verilog net, the only delay_type allowed is inertial. If you set the delay type to mti_transport, the setting will be ignored and the delay type will be mti_inertial. Any delays that are set to a value less than the simulator resolution will be rounded to the nearest resolution unit; no special warning will be issued.

init_signal_driver Example This example creates a local clock (clk0) and connects it to two clocks within the design hierarchy. The .../blk1/clk will match local clk0 and a message will be displayed. The open entries allow the default delay and delay_type while setting the verbose parameter to a 1. The .../blk2/clk will match the local clk0 but be delayed by 100 ps.
library IEEE, modelsim_lib; use IEEE.std_logic_1164.all; use modelsim_lib.util.all; entity testbench is end; architecture only of testbench is signal clk0 : std_logic; begin gen_clk0 : process begin clk0 <= '1' after 0 ps, '0' after 20 ps; wait for 40 ps; end process gen_clk0; drive_sig_process : process begin init_signal_driver("clk0", "/testbench/uut/blk1/clk", open, open, 1); init_signal_driver("clk0", "/testbench/uut/blk2/clk", 100 ps, mti_transport); wait; end process drive_sig_process; ... end;

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Signal Spy init_signal_spy

init_signal_spy
The init_signal_spy() procedure mirrors the value of a VHDL signal or Verilog register/net (called the src_object) onto an existing VHDL signal or Verilog register (called the dest_object). This allows you to reference signals, registers, or nets at any level of hierarchy from within a VHDL architecture (e.g., a testbench). The init_signal_spy procedure only sets the value onto the destination signal and does not drive or force the value. Any existing or subsequent drive or force of the destination signal, by some other means, will override the value that was set by init_signal_spy. Call only once The init_signal_spy procedure creates a persistent relationship between the source and destination signals. Hence, you need to call init_signal_spy once for a particular pair of signals. Once init_signal_spy is called, any change on the source signal will mirror on the destination signal until the end of the simulation unless the control_state is set. The control_state determines whether the mirroring of values can be enabled/disabled and what the initial state is. Subsequent control of whether the mirroring of values is enabled/disabled is handled by the enable_signal_spy and disable_signal_spy calls. We recommend that you place all init_signal_spy calls in a VHDL process. You need to code the VHDL process correctly so that it is executed only once. The VHDL process should not be sensitive to any signals and should contain only init_signal_spy calls and a simple wait statement. The process will execute once and then wait forever, which is the desired behavior. See the example below. Syntax init_signal_spy(<src_object>, <dest_object>, <verbose>, <control_state>) Returns Nothing Arguments src_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to an existing VHDL signal or Verilog register. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes.

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verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the src_objects value is mirrored onto the dest_object. Default is 0, no message.

control_state Optional integer. Possible values are -1, 0, or 1. Specifies whether or not you want the ability to enable/disable mirroring of values and, if so, specifies the initial state. The default is -1, no ability to enable/disable and mirroring is enabled. "0" turns on the ability to enable/disable and initially disables mirroring. "1" turns on the ability to enable/disable and initially enables mirroring.

Related procedures init_signal_driver, signal_force, signal_release, enable_signal_spy, disable_signal_spy Limitations When mirroring the value of a Verilog register/net onto a VHDL signal, the VHDL signal must be of type bit, bit_vector, std_logic, or std_logic_vector. Verilog memories (arrays of registers) are not supported.

init_signal_spy Example In this example, the value of /top/uut/inst1/sig1 is mirrored onto /top/top_sig1. A message is issued to the transcript. The ability to control the mirroring of values is turned on and the init_signal_spy is initially enabled. The mirroring of values will be disabled when enable_sig transitions to a 0 and enable when enable_sig transitions to a 1.
library ieee; library modelsim_lib; use ieee.std_logic_1164.all; use modelsim_lib.util.all; entity top is end; architecture only of top is signal top_sig1 : std_logic; begin ... spy_process : process begin init_signal_spy("/top/uut/inst1/sig1","/top/top_sig1",1,1); wait; end process spy_process; ... spy_enable_disable : process(enable_sig) begin if (enable_sig = '1') then enable_signal_spy("/top/uut/inst1/sig1","/top/top_sig1",0); elseif (enable_sig = '0')

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Signal Spy init_signal_spy disable_signal_spy("/top/uut/inst1/sig1","/top/top_sig1",0); end if; end process spy_enable_disable; ... end;

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Signal Spy signal_force

signal_force
The signal_force() procedure forces the value specified onto an existing VHDL signal or Verilog register or net (called the dest_object). This allows you to force signals, registers, or nets at any level of the design hierarchy from within a VHDL architecture (e.g., a testbench). A signal_force works the same as the force command with the exception that you cannot issue a repeating force. The force will remain on the signal until a signal_release, a force or release command, or a subsequent signal_force is issued. Signal_force can be called concurrently or sequentially in a process. This command acquires displays any signals using your radix setting (either the default, or as you specify) unless you specify the radix in the value you set. Syntax signal_force(<dest_object>, <value>, <rel_time>, <force_type>, <cancel_period>, <verbose>) Returns Nothing Arguments dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to an existing VHDL signal or Verilog register/net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. value Required string. Specifies the value to which the dest_object is to be forced. The specified value must be appropriate for the type. rel_time Optional time. Specifies a time relative to the current simulation time for the force to occur. The default is 0. force_type Optional forcetype. Specifies the type of force that will be applied. The value must be one of the following; default, deposit, drive, or freeze. The default is "default" (which is "freeze" for unresolved objects or "drive" for resolved objects). See the force command for further details on force type. cancel_period Optional time. Cancels the signal_force command after the specified period of time units. Cancellation occurs at the last simulation delta cycle of a time unit. A value of zero cancels the force at the end of the current time period. Default is -1 ms. A negative value means that the force will not be cancelled.

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Signal Spy signal_force

verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the value is being forced on the dest_object at the specified time. Default is 0, no message.

Related procedures init_signal_driver, init_signal_spy, signal_release Limitations You cannot force bits or slices of a register; you can force only the entire register. signal_force Example This example forces reset to a "1" from time 0 ns to 40 ns. At 40 ns, reset is forced to a "0", 2 ms after the second signal_force call was executed. If you want to skip parameters so that you can specify subsequent parameters, you need to use the keyword "open" as a placeholder for the skipped parameter(s). The first signal_force procedure illustrates this, where an "open" for the cancel_period parameter means that the default value of -1 ms is used.
library IEEE, modelsim_lib; use IEEE.std_logic_1164.all; use modelsim_lib.util.all; entity testbench is end; architecture only of testbench is begin force_process : process begin signal_force("/testbench/uut/blk1/reset", "1", 0 ns, freeze, open, 1); signal_force("/testbench/uut/blk1/reset", "0", 40 ns, freeze, 2 ms, 1); wait; end process force_process; ... end;

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Signal Spy signal_release

signal_release
The signal_release() procedure releases any force that was applied to an existing VHDL signal or Verilog register/net (called the dest_object). This allows you to release signals, registers or nets at any level of the design hierarchy from within a VHDL architecture (e.g., a testbench). A signal_release works the same as the noforce command. Signal_release can be called concurrently or sequentially in a process. Syntax signal_release(<dest_object>, <verbose>) Returns Nothing Arguments dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to an existing VHDL signal or Verilog register/net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the signal is being released and the time of the release. Default is 0, no message. Related procedures init_signal_driver, init_signal_spy, signal_force Limitations You cannot release a bit or slice of a register; you can release only the entire register.

signal_release Example This example releases any forces on the signals data and clk when the signal release_flag is a "1". Both calls will send a message to the transcript stating which signal was released and when.
library IEEE, modelsim_lib; use IEEE.std_logic_1164.all; use modelsim_lib.util.all; entity testbench is end; architecture only of testbench is signal release_flag : std_logic;

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Signal Spy signal_release begin stim_design : process begin ... wait until release_flag = '1'; signal_release("/testbench/dut/blk1/data", 1); signal_release("/testbench/dut/blk1/clk", 1); ... end process stim_design; ... end;

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Signal Spy $disable_signal_spy

$disable_signal_spy
The $disable_signal_spy() system task disables the associated $init_signal_spy task. The association between the $disable_signal_spy task and the $init_signal_spy task is based on specifying the same src_object and dest_object arguments to both tasks. The $disable_signal_spy task can only affect $init_signal_spy tasks that had their control_state argument set to "0" or "1". Syntax $disable_signal_spy(<src_object>, <dest_object>, <verbose>) Returns Nothing Arguments src_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. This path should match the path that was specified in the init_signal_spy call that you wish to disable. dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. This path should match the path that was specified in the init_signal_spy call that you wish to disable. verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the transcript stating that a disable occurred and the simulation time that it occurred. Default is 0, no message Related tasks $init_signal_spy, $enable_signal_spy Example See $init_signal_spy Example

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Signal Spy $enable_signal_spy

$enable_signal_spy
The $enable_signal_spy() system task enables the associated $init_signal_spy task. The association between the $enable_signal_spy task and the $init_signal_spy task is based on specifying the same src_object and dest_object arguments to both tasks. The $enable_signal_spy task can only affect $init_signal_spys tasks that had their control_state argument set to "0" or "1". Syntax $enable_signal_spy(<src_object>, <dest_object>, <verbose>) Returns Nothing Arguments src_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. This path should match the path that was specified in the init_signal_spy call that you wish to enable. dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. This path should match the path that was specified in the init_signal_spy call that you wish to enable. verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the transcript stating that an enable occurred and the simulation time that it occurred. Default is 0, no message Related tasks $init_signal_spy, $disable_signal_spy Example See $init_signal_spy Example

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Signal Spy $init_signal_driver

$init_signal_driver
The $init_signal_driver() system task drives the value of a VHDL signal or Verilog net (called the src_object) onto an existing VHDL signal or Verilog register/net (called the dest_object). This allows you to drive signals or nets at any level of the design hierarchy from within a Verilog module (e.g., a testbench). The $init_signal_driver system task drives the value onto the destination signal just as if the signals were directly connected in the HDL code. Any existing or subsequent drive or force of the destination signal, by some other means, will be considered with the $init_signal_driver value in the resolution of the signal. Call only once The $init_signal_driver system task creates a persistent relationship between the source and destination signals. Hence, you need to call $init_signal_driver only once for a particular pair of signals. Once $init_signal_driver is called, any change on the source signal will be driven on the destination signal until the end of the simulation. Thus, we recommend that you place all $init_signal_driver calls in a Verilog initial block. See the example below. Syntax $init_signal_driver(<src_object>, <dest_object>, <delay>, <delay_type>, <verbose>) Returns Nothing Arguments src_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to an existing VHDL signal or Verilog net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. delay Optional integer, real, or time. Specifies a delay relative to the time at which the src_object changes. The delay can be an inertial or transport delay. If no delay is specified, then a delay of zero is assumed.

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Signal Spy $init_signal_driver

delay_type Optional integer. Specifies the type of delay that will be applied. The value must be either 0 (inertial) or 1 (transport). The default is 0.

verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the src_object is driving the dest_object. Default is 0, no message.

Related tasks $init_signal_spy, $signal_force, $signal_release Limitations When driving a Verilog net, the only delay_type allowed is inertial. If you set the delay type to 1 (transport), the setting will be ignored, and the delay type will be inertial. Any delays that are set to a value less than the simulator resolution will be rounded to the nearest resolution unit; no special warning will be issued. Verilog memories (arrays of registers) are not supported.

$init_signal_driver Example This example creates a local clock (clk0) and connects it to two clocks within the design hierarchy. The .../blk1/clk will match local clk0 and a message will be displayed. The .../blk2/clk will match the local clk0 but be delayed by 100 ps. For the second call to work, the .../blk2/clk must be a VHDL based signal, because if it were a Verilog net a 100 ps inertial delay would consume the 40 ps clock period. Verilog nets are limited to only inertial delays and thus the setting of 1 (transport delay) would be ignored.
`timescale 1 ps / 1 ps module testbench; reg clk0; initial begin clk0 = 1; forever begin #20 clk0 = ~clk0; end end initial begin $init_signal_driver("clk0", "/testbench/uut/blk1/clk", , , 1); $init_signal_driver("clk0", "/testbench/uut/blk2/clk", 100, 1); end ... endmodule

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Signal Spy $init_signal_spy

$init_signal_spy
The $init_signal_spy() system task mirrors the value of a VHDL signal or Verilog register/net (called the src_object) onto an existing VHDL signal or Verilog register (called the dest_object). This allows you to reference signals, registers, or nets at any level of hierarchy from within a Verilog module (e.g., a testbench). The $init_signal_spy system task only sets the value onto the destination signal and does not drive or force the value. Any existing or subsequent drive or force of the destination signal, by some other means, will override the value set by $init_signal_spy. Call only once The $init_signal_spy system task creates a persistent relationship between the source and the destination signal. Hence, you need to call $init_signal_spy only once for a particular pair of signals. Once $init_signal_spy is called, any change on the source signal will mirror on the destination signal until the end of the simulation unless the control_state is set. The control_state determines whether the mirroring of values can be enabled/disabled and what the initial state is. Subsequent control of whether the mirroring of values is enabled/disabled is handled by the $enable_signal_spy and $disable_signal_spy tasks. We recommend that you place all $init_signal_spy tasks in a Verilog initial block. See the example below. Syntax $init_signal_spy(<src_object>, <dest_object>, <verbose>, <control_state>) Returns Nothing Arguments src_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a VHDL signal or Verilog register/net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to a Verilog register or VHDL signal. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the src_objects value is mirrored onto the dest_object. Default is 0, no message.

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Signal Spy $init_signal_spy

control_state Optional integer. Possible values are -1, 0, or 1. Specifies whether or not you want the ability to enable/disable mirroring of values and, if so, specifies the initial state. The default is -1, no ability to enable/disable and mirroring is enabled. "0" turns on the ability to enable/disable and initially disables mirroring. "1" turns on the ability to enable/disable and initially enables mirroring.

Related tasks $init_signal_driver, $signal_force, $signal_release, $disable_signal_spy Limitations When mirroring the value of a VHDL signal onto a Verilog register, the VHDL signal must be of type bit, bit_vector, std_logic, or std_logic_vector. Verilog memories (arrays of registers) are not supported.

$init_signal_spy Example In this example, the value of .top.uut.inst1.sig1 is mirrored onto .top.top_sig1. A message is issued to the transcript. The ability to control the mirroring of values is turned on and the init_signal_spy is initially enabled. The mirroring of values will be disabled when enable_reg transitions to a 0 and enabled when enable_reg transitions to a 1.
module top; ... reg top_sig1; reg enable_reg; ... initial begin $init_signal_spy(".top.uut.inst1.sig1",".top.top_sig1",1,1); end always @ (posedge enable_reg) begin $enable_signal_spy(".top.uut.inst1.sig1",".top.top_sig1",0); end always @ (negedge enable_reg) begin $disable_signal_spy(".top.uut.inst1.sig1",".top.top_sig1",0); end ... endmodule

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Signal Spy $signal_force

$signal_force
The $signal_force() system task forces the value specified onto an existing VHDL signal or Verilog register/net (called the dest_object). This allows you to force signals, registers, or nets at any level of the design hierarchy from within a Verilog module (e.g., a testbench). A $signal_force works the same as the force command with the exception that you cannot issue a repeating force. The force will remain on the signal until a $signal_release, a force or release command, or a subsequent $signal_force is issued. $signal_force can be called concurrently or sequentially in a process. Syntax $signal_force(<dest_object>, <value>, <rel_time>, <force_type>, <cancel_period>, <verbose>) Returns Nothing Arguments dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to an existing VHDL signal or Verilog register/net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. value Required string. Specifies the value to which the dest_object is to be forced. The specified value must be appropriate for the type. rel_time Optional integer, real, or time. Specifies a time relative to the current simulation time for the force to occur. The default is 0. force_type Optional integer. Specifies the type of force that will be applied. The value must be one of the following; 0 (default), 1 (deposit), 2 (drive), or 3 (freeze). The default is "default" (which is "freeze" for unresolved objects or "drive" for resolved objects). See the force command for further details on force type. cancel_period Optional integer, real, time. Cancels the $signal_force command after the specified period of time units. Cancellation occurs at the last simulation delta cycle of a time unit. A value of zero cancels the force at the end of the current time period. Default is -1. A negative value means that the force will not be cancelled.

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Signal Spy $signal_force

verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the value is being forced on the dest_object at the specified time. Default is 0, no message.

Related tasks $init_signal_driver, $init_signal_spy, $signal_release Limitations You cannot force bits or slices of a register; you can force only the entire register. Verilog memories (arrays of registers) are not supported.

$signal_force Example This example forces reset to a "1" from time 0 ns to 40 ns. At 40 ns, reset is forced to a "0", 200000 ns after the second $signal_force call was executed.
`timescale 1 ns / 1 ns module testbench; initial begin $signal_force("/testbench/uut/blk1/reset", "1", 0, 3, , 1); $signal_force("/testbench/uut/blk1/reset", "0", 40, 3, 200000, 1); end ... endmodule

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$signal_release
The $signal_release() system task releases any force that was applied to an existing VHDL signal or Verilog register/net (called the dest_object). This allows you to release signals, registers, or nets at any level of the design hierarchy from within a Verilog module (e.g., a testbench). A $signal_release works the same as the noforce command. $signal_release can be called concurrently or sequentially in a process. Syntax $signal_release(<dest_object>, <verbose>) Returns Nothing Arguments dest_object Required string. A full hierarchical path (or relative downward path with reference to the calling block) to an existing VHDL signal or Verilog register/net. Use the path separator to which your simulation is set (i.e., "/" or "."). A full hierarchical path must begin with a "/" or ".". The path must be contained within double quotes. verbose Optional integer. Possible values are 0 or 1. Specifies whether you want a message reported in the Transcript stating that the signal is being released and the time of the release. Default is 0, no message. Related tasks $init_signal_driver, $init_signal_spy, $signal_force Limitations You cannot release a bit or slice of a register; you can release only the entire register.

$signal_release Example This example releases any forces on the signals data and clk when the register release_flag transitions to a "1". Both calls will send a message to the transcript stating which signal was released and when.

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Signal Spy $signal_release module testbench; reg release_flag; always @(posedge release_flag) begin $signal_release("/testbench/dut/blk1/data", 1); $signal_release("/testbench/dut/blk1/clk", 1); end ... endmodule

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Chapter 18 Generating Stimulus with Waveform Editor

The ModelSim Waveform Editor offers a simple method for creating design stimulus. You can generate and edit waveforms in a graphical manner and then drive the simulation with those waveforms. With Waveform Editor you can do the following: Create waveforms using four predefined patterns: clock, random, repeater, and counter. See Creating Waveforms from Patterns. Edit waveforms with numerous functions including inserting, deleting, and stretching edges; mirroring, inverting, and copying waveform sections; and changing waveform values on-the-fly. See Editing Waveforms. Drive the simulation directly from the created waveforms Save created waveforms to four stimulus file formats: Tcl force format, extended VCD format, Verilog module, or VHDL architecture. The HDL formats include code that matches the created waveforms and can be used in testbenches to drive a simulation. See Exporting Waveforms to a Stimulus File

Limitations The current version does not support the following: Enumerated signals, records, multi-dimensional arrays, and memories User-defined types SystemC or SystemVerilog

Getting Started with the Waveform Editor

You can use Waveform Editor before or after loading a design. Regardless of which method you choose, you will select design objects and use them as the basis for created waveforms.

Using Waveform Editor Prior to Loading a Design

Here are the basic steps for using waveform editor prior to loading a design: 1. Right-click a design unit on the Library tab of the Workspace pane and select Create Wave.

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Generating Stimulus with Waveform Editor Getting Started with the Waveform Editor

Figure 18-1. Workspace Pane

2. Edit the waveforms in the Wave window. See Editing Waveforms for more details. 3. Run the simulation (see Simulating Directly from Waveform Editor) or save the created waveforms to a stimulus file (see Exporting Waveforms to a Stimulus File).

Using Waveform Editor After Loading a Design

Here are the basic steps for using waveform editor after loading a design: 1. Right-click a block in the structure tab of the Workspace pane or an object in the Object pane and select Create Wave.

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Generating Stimulus with Waveform Editor Creating Waveforms from Patterns

Figure 18-2. Opening Waveform Editor from Workspace or Objects Windows

2. Use the Create Pattern wizard to create the waveforms (see Creating Waveforms from Patterns). 3. Edit the waveforms as required (see Editing Waveforms). 4. Run the simulation (see Simulating Directly from Waveform Editor) or save the created waveforms to a stimulus file (see Exporting Waveforms to a Stimulus File).

Creating Waveforms from Patterns

Waveform Editor includes a Create Pattern wizard that walks you through the process of creating waveforms. To access the wizard: Right-click an object in the Objects pane or structure pane and select Create Wave. Right-click a signal already in the Wave window and select Create/Modify Waveform. (Only possible before simulation is run.)

The graphic below shows the initial dialog in the wizard. Note that the Drive Type field is not present for input and output signals.

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Figure 18-3. Create Pattern Wizard: Waveform

In this dialog you specify the signal that the waveform will be based upon, the Drive Type (if applicable), the start and end time for the waveform, and the pattern for the waveform. The second dialog in the wizard lets you specify the appropriate attributes based on the pattern you select. The table below shows the five available patterns and their attributes: Table 18-1. Signal Attributes in Create Pattern Wizard Pattern Clock Constant Random Description Specify an initial value, duty cycle, and clock period for the waveform. Specify a value. Generates different patterns depending upon the seed value. Specify the type (normal or uniform), an initial value, and a seed value. If you dont specify a seed value, ModelSim uses a default value of 5. Specify an initial value and pattern that repeats. You can also specify how many times the pattern repeats. Specify start and end values, time period, type (Range, Binary, Gray, One Hot, Zero Hot, Johnson), counter direction, step count, and repeat number.

Repeater Counter

Editing Waveforms
You can edit waveforms interactively with menu commands, mouse actions, or by using the wave edit command.

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To edit waveforms in the Wave window, follow these steps: 1. Create an editable pattern as described under Creating Waveforms from Patterns. 2. Enter editing mode by right-clicking a blank area of the toolbar and selecting Wave_edit from the toolbar popup menu. Figure 18-4. Toolbar Popup Menu

This will open the Wave Edit toolbar. For details about the Wave Edit toolbar, please refer to Wave Edit Toolbar. Figure 18-5. Wave Edit Toolbar

3. Select an edge or a section of the waveform with your mouse. See Selecting Parts of the Waveform for more details. 4. Select a command from the Wave > Wave Editor menu when the Wave window is docked, from the Edit > Wave menu when the Wave window is undocked, or rightclick on the waveform and select a command from the Wave context menu. The table below summarizes the editing commands that are available. Table 18-2. Waveform Editing Commands Operation Cut Copy Paste Insert Pulse Description Cut the selected portion of the waveform to the clipboard Copy the selected portion of the waveform to the clipboard Paste the contents of the clipboard over the selected section or at the active cursor location Insert a pulse at the location of the active cursor

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Table 18-2. Waveform Editing Commands (cont.) Operation Delete Edge Invert Mirror Value Stretch Edge Description Delete the edge at the active cursor Invert the selected waveform section Mirror the selected waveform section Change the value of the selected portion of the waveform Move an edge forward/backward by "stretching" the waveform; see Stretching and Moving Edges for more information Move an edge forward/backward without changing other edges; see Stretching and Moving Edges for more information Extend all created waveforms by the specified amount or to the specified simulation time; ModelSim cannot undo this edit or any edits done prior to an extend command Change the drive type of the selected portion of the waveform Undo waveform edits (except changing drive type and extending all waves) Redo previously undone waveform edits

Move Edge

Extend All Waves Change Drive Type Undo Redo

These commands can also be accessed via toolbar buttons. See Wave Edit Toolbar for more information.

Selecting Parts of the Waveform

There are several methods for selecting edges or sections of a waveform. The table and graphic below describe the various options. Table 18-3. Selecting Parts of the Waveform Action Select a waveform edge Select a section of the waveform Select a section of multiple waveforms Method Click on or just to the right of the waveform edge Click-and-drag the mouse pointer in the waveform pane Click-and-drag the mouse pointer while holding the <Shift> key

Extend/contract the selection size Drag a cursor in the cursor pane

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Table 18-3. Selecting Parts of the Waveform (cont.) Action Extend/contract selection from edge-to-edge Method Click Next Transition/Previous Transition icons after selecting section

Figure 18-6. Manipulating Waveforms with the Wave Edit Toolbar and Cursors

Selection and Zoom Percentage

You may find that you cannot select the exact range you want because the mouse moves more than one unit of simulation time (e.g., 228 ns to 230 ns). If this happens, zoom in on the Wave display (see Zooming the Wave Window Display), and you should be able to select the range you want.

Auto Snapping of the Cursor

When you click just to the right of a waveform edge in the waveform pane, the cursor automatically "snaps" to the nearest edge. This behavior is controlled by the Snap Distance setting in the Wave window preferences dialog.

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Stretching and Moving Edges

There are mouse and keyboard shortcuts for moving and stretching edges: Table 18-4. Wave Editor Mouse/Keyboard Shortcuts Action Stretch an edge Move an edge Mouse/keyboard shortcut Hold the <Ctrl> key and drag the edge Hold the <Ctrl> key and drag the edge with the 2nd (middle) mouse button

Here are some points to keep in mind about stretching and moving edges: If you stretch an edge forward, more waveform is inserted at the beginning of simulation time. If you stretch an edge backward, waveform is deleted at the beginning of simulation time. If you move an edge past another edge, either forward or backward, the edge you moved past is deleted.

Simulating Directly from Waveform Editor

You need not save the waveforms in order to use them as stimulus for a simulation. Once you have configured all the waveforms, you can run the simulation as normal by selecting Simulate > Start Simulation in the Main window or using the vsim command. ModelSim automatically uses the created waveforms as stimulus for the simulation. Furthermore, while running the simulation you can continue editing the waveforms to modify the stimulus for the part of the simulation yet to be completed.

Exporting Waveforms to a Stimulus File

Once you have created and edited the waveforms, you can save the data to a stimulus file that can be used to drive a simulation now or at a later time. To save the waveform data, select File > Export > Waveform or use the wave export command.

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Generating Stimulus with Waveform Editor Driving Simulation with the Saved Stimulus File

Figure 18-7. Export Waveform Dialog

You can save the waveforms in four different formats: Table 18-5. Formats for Saving Waveforms Format Force format Description Creates a Tcl script that contains force commands necessary to recreate the waveforms; source the file when loading the simulation as described under Driving Simulation with the Saved Stimulus File Creates an extended VCD file which can be reloaded using the Import > EVCD File command or can be used with the -vcdstim argument to vsim to simulate the design Creates a VHDL architecture that you load as the toplevel design unit Creates a Verilog module that you load as the toplevel design unit

EVCD format

VHDL Testbench Verilog Testbench

Driving Simulation with the Saved Stimulus File

The method for loading the stimulus file depends upon what type of format you saved. In each of the following examples, assume that the top-level of your block is named "top" and you saved the waveforms to a stimulus file named "mywaves" with the default extension. Table 18-6. Examples for Loading a Stimulus File Format Force format Extended VCD format1 Loading example vsim top -do mywaves.do vsim top -vcdstim mywaves.vcd

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Table 18-6. Examples for Loading a Stimulus File (cont.) Format VHDL Testbench Verilog Testbench Loading example vcom mywaves.vhd vsim mywaves vlog mywaves.v vsim mywaves

1. You can also use the Import > EVCD command from the Wave window. See below for more details on working with EVCD files.

Signal Mapping and Importing EVCD Files

When you import a previously saved EVCD file, ModelSim attempts to map the signals in the EVCD file to the signals in the loaded design. It matches signals based on name and width. If ModelSim cant map the signals automatically, you can do the mapping yourself by selecting one or more signals, right-clicking a selected signal, and then selecting Map to Design Signal. Figure 18-8. Evcd Import Dialog

Select a signal from the drop-down arrow and click OK. You will repeat this process for each signal you selected. Note This command works only with extended VCD files created with ModelSim.

Using Waveform Compare with Created Waveforms

The Waveform Compare feature compares two or more waveforms and displays the differences in the Wave window (see Waveform Compare for details). This feature can be used in tandem with Waveform Editor. The combination is most useful in situations where you know the expected output of a signal and want to compare visually the differences between expected output and simulated output. The basic procedure for using the two features together is as follows:

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Create a waveform based on the signal of interest with a drive type of expected output Add the design signal of interest to the Wave window and then run the design Start a comparison and use the created waveform as the reference dataset for the comparison. Use the text "Edit" to designate a create waveform as the reference dataset. For example:
compare start Edit sim compare add -wave /test_counter/count compare run

Saving the Waveform Editor Commands

When you create and edit waveforms in the Wave window, ModelSim tracks the underlying Tcl commands and reports them to the transcript. You can save those commands to a DO file that can be run at a later time to recreate the waveforms. To save your waveform editor commands, select File > Save.

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Chapter 19 Standard Delay Format (SDF) Timing Annotation

This chapter discusses ModelSims implementation of SDF (Standard Delay Format) timing annotation. Included are sections on VITAL SDF and Verilog SDF, plus troubleshooting. Verilog and VHDL VITAL timing data can be annotated from SDF files by using the simulators built-in SDF annotator. ASIC and FPGA vendors usually provide tools that create SDF files for use with their cell libraries. Refer to your vendors documentation for details on creating SDF files for your library. Many vendors also provide instructions on using their SDF files and libraries with ModelSim. The SDF specification was originally created for Verilog designs, but it has also been adopted for VHDL VITAL designs. In general, the designer does not need to be familiar with the details of the SDF specification because the cell library provider has already supplied tools that create SDF files that match their libraries. Note ModelSim will read SDF files that were compressed using gzip. Other compression formats (e.g., Unix zip) are not supported.

Specifying SDF Files for Simulation

ModelSim supports SDF versions 1.0 through 4.0 (except the NETDELAY statement). The simulators built-in SDF annotator automatically adjusts to the version of the file. Use the following vsim command-line options to specify the SDF files, the desired timing values, and their associated design instances:
-sdfmin [<instance>=]<filename> -sdftyp [<instance>=]<filename> -sdfmax [<instance>=]<filename>

Any number of SDF files can be applied to any instance in the design by specifying one of the above options for each file. Use -sdfmin to select minimum, -sdftyp to select typical, and -sdfmax to select maximum timing values from the SDF file.

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Instance Specification
The instance paths in the SDF file are relative to the instance to which the SDF is applied. Usually, this instance is an ASIC or FPGA model instantiated under a testbench. For example, to annotate maximum timing values from the SDF file myasic.sdf to an instance u1 under a toplevel named testbench, invoke the simulator as follows:
vsim -sdfmax /testbench/u1=myasic.sdf testbench

If the instance name is omitted then the SDF file is applied to the top-level. This is usually incorrect because in most cases the model is instantiated under a testbench or within a larger system level simulation. In fact, the design can have several models, each having its own SDF file. In this case, specify an SDF file for each instance. For example,
vsim -sdfmax /system/u1=asic1.sdf -sdfmax /system/u2=asic2.sdf system

SDF Specification with the GUI

As an alternative to the command-line options, you can specify SDF files in the Start Simulation dialog box under the SDF tab. Figure 19-1. SDF Tab in Start Simulation Dialog

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You can access this dialog by invoking the simulator without any arguments or by selecting Simulate > Start Simulation. See the GUI chapter for a description of this dialog. For Verilog designs, you can also specify SDF files by using the $sdf_annotate system task. See $sdf_annotate for more details.

Errors and Warnings

Errors issued by the SDF annotator while loading the design prevent the simulation from continuing, whereas warnings do not. Use the -sdfnoerror option with vsim to change SDF errors to warnings so that the simulation can continue. Warning messages can be suppressed by using vsim with either the -sdfnowarn or +nosdfwarn options. Another option is to use the SDF tab from the Start Simulation dialog box (shown above). Select Disable SDF warnings (-sdfnowarn +nosdfwarn) to disable warnings, or select Reduce SDF errors to warnings (-sdfnoerror) to change errors to warnings. See Troubleshooting for more information on errors and warnings and how to avoid them.

VHDL VITAL SDF

VHDL SDF annotation works on VITAL cells only. The IEEE 1076.4 VITAL ASIC Modeling Specification describes how cells must be written to support SDF annotation. Once again, the designer does not need to know the details of this specification because the library provider has already written the VITAL cells and tools that create compatible SDF files. However, the following summary may help you understand simulator error messages. For additional VITAL specification information, see VITAL Specification and Source Code.

SDF to VHDL Generic Matching

An SDF file contains delay and timing constraint data for cell instances in the design. The annotator must locate the cell instances and the placeholders (VHDL generics) for the timing data. Each type of SDF timing construct is mapped to the name of a generic as specified by the VITAL modeling specification. The annotator locates the generic and updates it with the timing value from the SDF file. It is an error if the annotator fails to find the cell instance or the named generic. The following are examples of SDF constructs and their associated generic names: Table 19-1. Matching SDF to VHDL Generics SDF construct (IOPATH a y (3)) (IOPATH (posedge clk) q (1) (2)) (INTERCONNECT u1/y u2/a (5)) (SETUP d (posedge clk) (5))
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Matching VHDL generic name tpd_a_y tpd_clk_q_posedge tipd_a tsetup_d_clk_noedge_posedge

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Table 19-1. Matching SDF to VHDL Generics (cont.) SDF construct (HOLD (negedge d) (posedge clk) (5)) (SETUPHOLD d clk (5) (5)) Matching VHDL generic name thold_d_clk_negedge_posedge tsetup_d_clk & thold_d_clk

(WIDTH (COND (reset==1b0) clk) (5)) tpw_clk_reset_eq_0 The SDF statement CONDELSE, when targeted for Vital cells, is annotated to a tpd generic of the form tpd_<inputPort>_<outputPort>.

Resolving Errors
If the simulator finds the cell instance but not the generic then an error message is issued. For example,
** Error (vsim-SDF-3240) myasic.sdf(18): Instance /testbench/dut/u1 does not have a generic named tpd_a_y

In this case, make sure that the design is using the appropriate VITAL library cells. If it is, then there is probably a mismatch between the SDF and the VITAL cells. You need to find the cell instance and compare its generic names to those expected by the annotator. Look in the VHDL source files provided by the cell library vendor. If none of the generic names look like VITAL timing generic names, then perhaps the VITAL library cells are not being used. If the generic names do look like VITAL timing generic names but dont match the names expected by the annotator, then there are several possibilities: The vendors tools are not conforming to the VITAL specification. The SDF file was accidentally applied to the wrong instance. In this case, the simulator also issues other error messages indicating that cell instances in the SDF could not be located in the design. The vendors library and SDF were developed for the older VITAL 2.2b specification. This version uses different name mapping rules. In this case, invoke vsim with the -vital2.2b option:
vsim -vital2.2b -sdfmax /testbench/u1=myasic.sdf testbench

For more information on resolving errors see Troubleshooting.

Verilog SDF
Verilog designs can be annotated using either the simulator command-line options or the $sdf_annotate system task (also commonly used in other Verilog simulators). The commandline options annotate the design immediately after it is loaded, but before any simulation events

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take place. The $sdf_annotate task annotates the design at the time it is called in the Verilog source code. This provides more flexibility than the command-line options.

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$sdf_annotate
Syntax $sdf_annotate (["<sdffile>"], [<instance>], ["<config_file>"], ["<log_file>"], ["<mtm_spec>"], ["<scale_factor>"], ["<scale_type>"]); Arguments "<sdffile>" String that specifies the SDF file. Required. <instance> Hierarchical name of the instance to be annotated. Optional. Defaults to the instance where the $sdf_annotate call is made. "<config_file>" String that specifies the configuration file. Optional. Currently not supported, this argument is ignored. "<log_file>" String that specifies the logfile. Optional. Currently not supported, this argument is ignored. "<mtm_spec>" String that specifies the delay selection. Optional. The allowed strings are "minimum", "typical", "maximum", and "tool_control". Case is ignored and the default is "tool_control". The "tool_control" argument means to use the delay specified on the command line by +mindelays, +typdelays, or +maxdelays (defaults to +typdelays). "<scale_factor>" String that specifies delay scaling factors. Optional. The format is "<min_mult>:<typ_mult>:<max_mult>". Each multiplier is a real number that is used to scale the corresponding delay in the SDF file. "<scale_type>" String that overrides the <mtm_spec> delay selection. Optional. The <mtm_spec> delay selection is always used to select the delay scaling factor, but if a <scale_type> is specified, then it will determine the min/typ/max selection from the SDF file. The allowed strings are "from_min", "from_minimum", "from_typ", "from_typical", "from_max", "from_maximum", and "from_mtm". Case is ignored, and the default is "from_mtm", which means to use the <mtm_spec> value. Examples Optional arguments can be omitted by using commas or by leaving them out if they are at the end of the argument list. For example, to specify only the SDF file and the instance to which it applies:

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Standard Delay Format (SDF) Timing Annotation $sdf_annotate $sdf_annotate("myasic.sdf", testbench.u1);

To also specify maximum delay values:

$sdf_annotate("myasic.sdf", testbench.u1, , , "maximum");

SDF to Verilog Construct Matching

The annotator matches SDF constructs to corresponding Verilog constructs in the cells. Usually, the cells contain path delays and timing checks within specify blocks. For each SDF construct, the annotator locates the cell instance and updates each specify path delay or timing check that matches. An SDF construct can have multiple matches, in which case each matching specify statement is updated with the SDF timing value. SDF constructs are matched to Verilog constructs as follows. IOPATH is matched to specify path delays or primitives: Table 19-2. Matching SDF IOPATH to Verilog SDF (IOPATH (posedge clk) q (3) (4)) (IOPATH a y (3) (4)) Verilog (posedge clk => q) = 0; buf u1 (y, a);

The IOPATH construct usually annotates path delays. If ModelSim cant locate a corresponding specify path delay, it returns an error unless you use the +sdf_iopath_to_prim_ok argument to vsim. If you specify that argument and the module contains no path delays, then all primitives that drive the specified output port are annotated. INTERCONNECT and PORT are matched to input ports: Table 19-3. Matching SDF INTERCONNECT and PORT to Verilog SDF (INTERCONNECT u1.y u2.a (5)) (PORT u2.a (5)) Verilog input a; inout a;

Both of these constructs identify a module input or inout port and create an internal net that is a delayed version of the port. This is called a Module Input Port Delay (MIPD). All primitives, specify path delays, and specify timing checks connected to the original port are reconnected to the new MIPD net.

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PATHPULSE and GLOBALPATHPULSE are matched to specify path delays:

Table 19-4. Matching SDF PATHPULSE and GLOBALPATHPULSE to Verilog SDF (PATHPULSE a y (5) (10)) (GLOBALPATHPULSE a y (30) (60)) Verilog (a => y) = 0; (a => y) = 0;

If the input and output ports are omitted in the SDF, then all path delays are matched in the cell. DEVICE is matched to primitives or specify path delays: Table 19-5. Matching SDF DEVICE to Verilog SDF (DEVICE y (5)) (DEVICE y (5)) Verilog and u1(y, a, b); (a => y) = 0; (b => y) = 0;

If the SDF cell instance is a primitive instance, then that primitives delay is annotated. If it is a module instance, then all specify path delays are annotated that drive the output port specified in the DEVICE construct (all path delays are annotated if the output port is omitted). If the module contains no path delays, then all primitives that drive the specified output port are annotated (or all primitives that drive any output port if the output port is omitted). SETUP is matched to $setup and $setuphold: Table 19-6. Matching SDF SETUP to Verilog SDF (SETUP d (posedge clk) (5)) (SETUP d (posedge clk) (5)) Verilog $setup(d, posedge clk, 0); $setuphold(posedge clk, d, 0, 0);

HOLD is matched to $hold and $setuphold: Table 19-7. Matching SDF HOLD to Verilog SDF (HOLD d (posedge clk) (5)) (HOLD d (posedge clk) (5)) Verilog $hold(posedge clk, d, 0); $setuphold(posedge clk, d, 0, 0);

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SETUPHOLD is matched to $setup, $hold, and $setuphold: Table 19-8. Matching SDF SETUPHOLD to Verilog SDF (SETUPHOLD d (posedge clk) (5) (5)) (SETUPHOLD d (posedge clk) (5) (5)) (SETUPHOLD d (posedge clk) (5) (5)) Verilog $setup(d, posedge clk, 0); $hold(posedge clk, d, 0); $setuphold(posedge clk, d, 0, 0);

RECOVERY is matched to $recovery: Table 19-9. Matching SDF RECOVERY to Verilog

SDF

Verilog

(RECOVERY (negedge reset) (posedge clk) $recovery(negedge reset, posedge clk, 0); (5)) REMOVAL is matched to $removal: Table 19-10. Matching SDF REMOVAL to Verilog SDF Verilog (REMOVAL (negedge reset) (posedge clk) $removal(negedge reset, posedge clk, 0); (5)) RECREM is matched to $recovery, $removal, and $recrem: Table 19-11. Matching SDF RECREM to Verilog SDF (RECREM (negedge reset) (posedge clk) (5) (5)) (RECREM (negedge reset) (posedge clk) (5) (5)) (RECREM (negedge reset) (posedge clk) (5) (5)) SKEW is matched to $skew: Table 19-12. Matching SDF SKEW to Verilog SDF (SKEW (posedge clk1) (posedge clk2) (5)) Verilog $skew(posedge clk1, posedge clk2, 0); Verilog $recovery(negedge reset, posedge clk, 0); $removal(negedge reset, posedge clk, 0); $recrem(negedge reset, posedge clk, 0);

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WIDTH is matched to $width: Table 19-13. Matching SDF WIDTH to Verilog SDF (WIDTH (posedge clk) (5)) Verilog $width(posedge clk, 0);

PERIOD is matched to $period: Table 19-14. Matching SDF PERIOD to Verilog SDF (PERIOD (posedge clk) (5)) Verilog $period(posedge clk, 0);

NOCHANGE is matched to $nochange: Table 19-15. Matching SDF NOCHANGE to Verilog

SDF (NOCHANGE (negedge write) addr (5) (5))

Verilog $nochange(negedge write, addr, 0, 0);

Optional Edge Specifications

Timing check ports and path delay input ports can have optional edge specifications. The annotator uses the following rules to match edges: A match occurs if the SDF port does not have an edge. A match occurs if the specify port does not have an edge. A match occurs if the SDF port edge is identical to the specify port edge. A match occurs if explicit edge transitions in the specify port edge overlap with the SDF port edge.

These rules allow SDF annotation to take place even if there is a difference between the number of edge-specific constructs in the SDF file and the Verilog specify block. For example, the Verilog specify block may contain separate setup timing checks for a falling and rising edge on data with respect to clock, while the SDF file may contain only a single setup check for both edges: Table 19-16. Matching Verilog Timing Checks to SDF SETUP SDF (SETUP data (posedge clock) (5)) (SETUP data (posedge clock) (5)) Verilog $setup(posedge data, posedge clk, 0); $setup(negedge data, posedge clk, 0);

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In this case, the cell accommodates more accurate data than can be supplied by the tool that created the SDF file, and both timing checks correctly receive the same value. Likewise, the SDF file may contain more accurate data than the model can accommodate. Table 19-17. SDF Data May Be More Accurate Than Model SDF Verilog (SETUP (posedge data) (posedge clock) (4)) $setup(data, posedge clk, 0); (SETUP (negedge data) (posedge clock) (6)) $setup(data, posedge clk, 0); In this case, both SDF constructs are matched and the timing check receives the value from the last one encountered. Timing check edge specifiers can also use explicit edge transitions instead of posedge and negedge. However, the SDF file is limited to posedge and negedge. For example, Table 19-18. Matching Explicit Verilog Edge Transitions to Verilog SDF (SETUP data (posedge clock) (5)) Verilog $setup(data, edge[01, 0x] clk, 0);

The explicit edge specifiers are 01, 0x, 10, 1x, x0, and x1. The set of [01, 0x, x1] is equivalent to posedge, while the set of [10, 1x, x0] is equivalent to negedge. A match occurs if any of the explicit edges in the specify port match any of the explicit edges implied by the SDF port.

Optional Conditions
Timing check ports and path delays can have optional conditions. The annotator uses the following rules to match conditions: A match occurs if the SDF does not have a condition. A match occurs for a timing check if the SDF port condition is semantically equivalent to the specify port condition. A match occurs for a path delay if the SDF condition is lexically identical to the specify condition.

Timing check conditions are limited to very simple conditions, therefore the annotator can match the expressions based on semantics. For example, Table 19-19. SDF Timing Check Conditions SDF (SETUP data (COND (reset!=1) (posedge clock)) (5)) Verilog $setup(data, posedge clk &&& (reset==0),0);

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The conditions are semantically equivalent and a match occurs. In contrast, path delay conditions may be complicated and semantically equivalent conditions may not match. For example, Table 19-20. SDF Path Delay Conditions SDF (COND (r1 || r2) (IOPATH clk q (5))) (COND (r1 || r2) (IOPATH clk q (5))) Verilog if (r1 || r2) (clk => q) = 5; // matches if (r2 || r1) (clk => q) = 5; // does not match

The annotator does not match the second condition above because the order of r1 and r2 are reversed.

Rounded Timing Values

The SDF TIMESCALE construct specifies time units of values in the SDF file. The annotator rounds timing values from the SDF file to the time precision of the module that is annotated. For example, if the SDF TIMESCALE is 1ns and a value of .016 is annotated to a path delay in a module having a time precision of 10ps (from the timescale directive), then the path delay receives a value of 20ps. The SDF value of 16ps is rounded to 20ps. Interconnect delays are rounded to the time precision of the module that contains the annotated MIPD.

SDF for Mixed VHDL and Verilog Designs

Annotation of a mixed VHDL and Verilog design is very flexible. VHDL VITAL cells and Verilog cells can be annotated from the same SDF file. This flexibility is available only by using the simulators SDF command-line options. The Verilog $sdf_annotate system task can annotate Verilog cells only. See the vsim command for more information on SDF commandline options.

Interconnect Delays
An interconnect delay represents the delay from the output of one device to the input of another. ModelSim can model single interconnect delays or multisource interconnect delays for Verilog, VHDL/VITAL, or mixed designs. See the vsim command for more information on the relevant command-line arguments. Timing checks are performed on the interconnect delayed versions of input ports. This may result in misleading timing constraint violations, because the ports may satisfy the constraint while the delayed versions may not. If the simulator seems to report incorrect violations, be sure to account for the effect of interconnect delays.

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Standard Delay Format (SDF) Timing Annotation Disabling Timing Checks

Disabling Timing Checks

ModelSim offers a number of options for disabling timing checks on a "global" or individual basis. The table below provides a summary of those options. See the command and argument descriptions in the Reference Manual for more details. Table 19-21. Disabling Timing Checks Command and argument vlog +notimingchecks vlog +nospecify vsim +no_neg_tchk vsim +no_notifier Effect disables timing check system tasks for all instances in the specified Verilog design disables specify path delays and timing checks for all instances in the specified Verilog design disables negative timing check limits by setting them to zero for all instances in the specified design disables the toggling of the notifier register argument of the timing check system tasks for all instances in the specified design disables error messages issued by timing check system tasks when timing check violations occur for all instances in the specified design disables Verilog and VITAL timing checks for all instances in the specified design disables specify path delays and timing checks for all instances in the specified design

vsim +no_tchk_msg

vsim +notimingchecks vsim +nospecify

Troubleshooting
Specifying the Wrong Instance
By far, the most common mistake in SDF annotation is to specify the wrong instance to the simulators SDF options. The most common case is to leave off the instance altogether, which is the same as selecting the top-level design unit. This is generally wrong because the instance paths in the SDF are relative to the ASIC or FPGA model, which is usually instantiated under a top-level testbench. See Instance Specification for an example. A common example for both VHDL and Verilog testbenches is provided below. For simplicity, the test benches do nothing more than instantiate a model that has no ports.

VHDL Testbench
entity testbench is end;

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Standard Delay Format (SDF) Timing Annotation Troubleshooting architecture only of testbench is component myasic end component; begin dut : myasic; end;

Verilog Testbench
module testbench; myasic dut(); endmodule

The name of the model is myasic and the instance label is dut. For either testbench, an appropriate simulator invocation might be:
vsim -sdfmax /testbench/dut=myasic.sdf testbench

Optionally, you can leave off the name of the top-level:

vsim -sdfmax /dut=myasic.sdf testbench

The important thing is to select the instance for which the SDF is intended. If the model is deep within the design hierarchy, an easy way to find the instance name is to first invoke the simulator without SDF options, view the structure pane, navigate to the model instance, select it, and enter the environment command. This command displays the instance name that should be used in the SDF command-line option.

Mistaking a Component or Module Name for an Instance Label

Another common error is to specify the component or module name rather than the instance label. For example, the following invocation is wrong for the above testbenches:
vsim -sdfmax /testbench/myasic=myasic.sdf testbench

This results in the following error message:

** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE /testbench/myasic.

Forgetting to Specify the Instance

If you leave off the instance altogether, then the simulator issues a message for each instance path in the SDF that is not found in the design. For example,
vsim -sdfmax myasic.sdf testbench

Results in:

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Standard Delay Format (SDF) Timing Annotation Troubleshooting ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE /testbench/u1 ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE /testbench/u2 ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE /testbench/u3 ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE /testbench/u4 ** Error (vsim-SDF-3250) myasic.sdf(0): Failed to find INSTANCE /testbench/u5 ** Warning (vsim-SDF-3432) myasic.sdf: This file is probably applied to the wrong instance. ** Warning (vsim-SDF-3432) myasic.sdf: Ignoring subsequent missing instances from this file.

After annotation is done, the simulator issues a summary of how many instances were not found and possibly a suggestion for a qualifying instance:
** Warning (vsim-SDF-3440) myasic.sdf: Failed to find any of the 358 instances from this file. ** Warning (vsim-SDF-3442) myasic.sdf: Try instance /testbench/dut. It contains all instance paths from this file.

The simulator recommends an instance only if the file was applied to the top-level and a qualifying instance is found one level down. Also see Resolving Errors for specific VHDL VITAL SDF troubleshooting.

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Chapter 20 Value Change Dump (VCD) Files

This chapter describes how to use VCD files in ModelSim. The VCD file format is specified in the IEEE 1364 standard. It is an ASCII file containing header information, variable definitions, and variable value changes. VCD is in common use for Verilog designs, and is controlled by VCD system task calls in the Verilog source code. ModelSim provides command equivalents for these system tasks and extends VCD support to VHDL designs. The ModelSim commands can be used on VHDL, Verilog, or mixed designs. If you need vendor-specific ASIC design-flow documentation that incorporates VCD, please contact your ASIC vendor.

Creating a VCD File

There are two flows in ModelSim for creating a VCD file. One flow produces a four-state VCD file with variable changes in 0, 1, x, and z with no strength information; the other produces an extended VCD file with variable changes in all states and strength information and port driver data. Both flows will also capture port driver changes unless filtered out with optional command-line arguments.

Flow for Four-State VCD File

First, compile and load the design:
% cd ~/modeltech/examples/misc % vlib work % vlog counter.v tcounter.v % vsim test_counter

Next, with the design loaded, specify the VCD file name with the vcd file command and add objects to the file with the vcd add command:
VSIM 1> vcd file myvcdfile.vcd VSIM 2> vcd add /test_counter/dut/* VSIM 3> run VSIM 4> quit -f

There will now be a VCD file in the working directory.

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Flow for Extended VCD File

First, compile and load the design:
% cd ~/modeltech/examples/misc % vlib work % vlog counter.v tcounter.v % vsim test_counter

Next, with the design loaded, specify the VCD file name and objects to add with the vcd dumpports command:
VSIM 1> vcd dumpports -file myvcdfile.vcd /test_counter/dut/* VSIM 3> run VSIM 4> quit -f

There will now be an extended VCD file called myvcdfile.vcd in the working directory. Note There is an internal limit to the number of port driver changes that can be created with the vcd dumpports command. If that limit is reached, use the vcd add command with the -dumpports option to create additional port driver changes. By default ModelSim uses strength ranges for resolving conflicts as specified by IEEE 1364-2005. You can ignore strength ranges using the -no_strength_range argument to the vcd dumpports command. See Resolving Values for more details.

Case Sensitivity
VHDL is not case sensitive so ModelSim converts all signal names to lower case when it produces a VCD file. Conversely, Verilog designs are case sensitive so ModelSim maintains case when it produces a VCD file.

Using Extended VCD as Stimulus

You can use an extended VCD file as stimulus to re-simulate your design. There are two ways to do this: 1) simulate the top level of a design unit with the input values from an extended VCD file; and 2) specify one or more instances in a design to be replaced with the output values from the associated VCD file.

Simulating with Input Values from a VCD File

When simulating with inputs from an extended VCD file, you can simulate only one design unit at a time. In other words, you can apply the VCD file inputs only to the top level of the design unit for which you captured port data. The general procedure includes two steps:
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1. Create a VCD file for a single design unit using the vcd dumpports command. 2. Resimulate the single design unit using the -vcdstim argument to vsim. Note that -vcdstim works only with VCD files that were created by a ModelSim simulation. Example 20-1. Verilog Counter First, create the VCD file for the single instance using vcd dumpports:
% cd ~/modeltech/examples/misc % vlib work % vlog counter.v tcounter.v % vsim test_counter VSIM 1> vcd dumpports -file counter.vcd /test_counter/dut/* VSIM 2> run VSIM 3> quit -f

Next, rerun the counter without the testbench, using the -vcdstim argument:
% vsim -vcdstim counter.vcd counter VSIM 1> add wave /* VSIM 2> run 200

Example 20-2. VHDL Adder First, create the VCD file using vcd dumpports:
% cd ~/modeltech/examples/misc % vlib work % vcom gates.vhd adder.vhd stimulus.vhd % vsim testbench2 VSIM 1> vcd dumpports -file addern.vcd /testbench2/uut/* VSIM 2> run 1000 VSIM 3> quit -f

Next, rerun the adder without the testbench, using the -vcdstim argument:
% vsim -vcdstim addern.vcd addern -gn=8 -do "add wave /*; run 1000"

Example 20-3. Mixed-HDL Design First, create three VCD files, one for each module:
% cd ~/modeltech/examples/tutorials/mixed/projects % vlib work % vlog cache.v memory.v proc.v % vcom util.vhd set.vhd top.vhd % vsim top VSIM 1> vcd dumpports -file proc.vcd /top/p/* VSIM 2> vcd dumpports -file cache.vcd /top/c/* VSIM 3> vcd dumpports -file memory.vcd /top/m/* VSIM 4> run 1000 VSIM 5> quit -f

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Next, rerun each module separately, using the captured VCD stimulus:
% vsim -vcdstim proc.vcd proc -do "add wave /*; run 1000" VSIM 1> quit -f % vsim -vcdstim cache.vcd cache -do "add wave /*; run 1000" VSIM 1> quit -f % vsim -vcdstim memory.vcd memory -do "add wave /*; run 1000" VSIM 1> quit -f

Replacing Instances with Output Values from a VCD File

Replacing instances with output values from a VCD file lets you simulate without the instances source or even the compiled object. The general procedure includes two steps: 1. Create VCD files for one or more instances in your design using the vcd dumpports command. If necessary, use the -vcdstim switch to handle port order problems (see below). 2. Re-simulate your design using the -vcdstim <instance>=<filename> argument to vsim. Note that this works only with VCD files that were created by a ModelSim simulation. Example 20-4. Replacing Instances In the following example, the three instances /top/p, /top/c, and /top/m are replaced in simulation by the output values found in the corresponding VCD files. First, create VCD files for all instances you want to replace:
vcd dumpports -vcdstim -file proc.vcd /top/p/* vcd dumpports -vcdstim -file cache.vcd /top/c/* vcd dumpports -vcdstim -file memory.vcd /top/m/* run 1000

Next, simulate your design and map the instances to the VCD files you created:
vsim top -vcdstim /top/p=proc.vcd -vcdstim /top/c=cache.vcd -vcdstim /top/m=memory.vcd

Port Order Issues

The -vcdstim argument to the vcd dumpports command ensures the order that port names appear in the VCD file matches the order that they are declared in the instances module or entity declaration. Consider the following module declaration:
module proc(clk, addr, data, rw, strb, rdy); input clk, rdy; output addr, rw, strb; inout data;

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The order of the ports in the module line (clk, addr, data, ...) does not match the order of those ports in the input, output, and inout lines (clk, rdy, addr, ...). In this case the -vcdstim argument to the vcd dumpports command needs to be used. In cases where the order is the same, you do not need to use the -vcdstim argument to vcd dumpports. Also, module declarations of the form:
module proc(input clk, output addr, inout data, ...)

do not require use of the argument.

VCD Commands and VCD Tasks

ModelSim VCD commands map to IEEE Std 1364 VCD system tasks and appear in the VCD file along with the results of those commands. The table below maps the VCD commands to their associated tasks. Table 20-1. VCD Commands and SystemTasks VCD commands vcd add vcd checkpoint vcd file vcd flush vcd limit vcd off vcd on VCD system tasks $dumpvars $dumpall $dumpfile $dumpflush $dumplimit $dumpoff $dumpon

ModelSim also supports extended VCD (dumpports system tasks). The table below maps the VCD dumpports commands to their associated tasks. Table 20-2. VCD Dumpport Commands and System Tasks VCD dumpports commands vcd dumpports vcd dumpportsall vcd dumpportsflush vcd dumpportslimit vcd dumpportsoff vcd dumpportson VCD system tasks $dumpports $dumpportsall $dumpportsflush $dumpportslimit $dumpportsoff $dumpportson

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ModelSim supports multiple VCD files. This functionality is an extension of the IEEE Std 1364 specification. The tasks behave the same as the IEEE equivalent tasks such as $dumpfile, $dumpvar, etc. The difference is that $fdumpfile can be called multiple times to create more than one VCD file, and the remaining tasks require a filename argument to associate their actions with a specific file. Table 20-3. VCD Commands and System Tasks for Multiple VCD Files VCD commands vcd add -file <filename> vcd checkpoint <filename> vcd files <filename> vcd flush <filename> vcd limit <filename> vcd off <filename> vcd on <filename> VCD system tasks $fdumpvars $fdumpall $fdumpfile $fdumpflush $fdumplimit $fdumpoff $fdumpon

Compressing Files with VCD Tasks

ModelSim can produce compressed VCD files using the gzip compression algorithm. Since we cannot change the syntax of the system tasks, we act on the extension of the output file name. If you specify a .gz extension on the filename, ModelSim will compress the output.

VCD File from Source To Output

The following example shows the VHDL source, a set of simulator commands, and the resulting VCD output.

VHDL Source Code

The design is a simple shifter device represented by the following VHDL source code:

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Value Change Dump (VCD) Files VCD File from Source To Output library IEEE; use IEEE.STD_LOGIC_1164.all; entity SHIFTER_MOD is port (CLK, RESET, data_in : IN STD_LOGIC; Q : INOUT STD_LOGIC_VECTOR(8 downto 0)); END SHIFTER_MOD ; architecture RTL of SHIFTER_MOD is begin process (CLK,RESET) begin if (RESET = '1') then Q <= (others => '0') ; elsif (CLK'event and CLK = '1') then Q <= Q(Q'left - 1 downto 0) & data_in ; end if ; end process ; end ;

VCD Simulator Commands

At simulator time zero, the designer executes the following commands:
vcd file output.vcd vcd add -r * force reset 1 0 force data_in 0 0 force clk 0 0 run 100 force clk 1 0, 0 50 -repeat 100 run 100 vcd off force reset 0 0 force data_in 1 0 run 100 vcd on run 850 force reset 1 0 run 50 vcd checkpoint quit -sim

VCD Output
The VCD file created as a result of the preceding scenario would be called output.vcd. The following pages show how it would look.

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Value Change Dump (VCD) Files VCD File from Source To Output $date Thu Sep 18 11:07:43 2003 $end $version ModelSim Version 6.1 $end $timescale 1ns $end $scope module shifter_mod $end $var wire 1 ! clk $end $var wire 1 " reset $end $var wire 1 # data_in $end $var wire 1 $ q [8] $end $var wire 1 % q [7] $end $var wire 1 & q [6] $end $var wire 1 ' q [5] $end $var wire 1 ( q [4] $end $var wire 1 ) q [3] $end $var wire 1 * q [2] $end $var wire 1 + q [1] $end $var wire 1 , q [0] $end $upscope $end $enddefinitions $end #0 $dumpvars 0! 1" 0# 0$ 0% 0& 0' 0( 0) 0* 0+ 0, $end #100 1! #150 0! #200 1! $dumpoff x! x" x# x$ x% x& x' x( x) x* x+ x,

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Value Change Dump (VCD) Files VCD File from Source To Output $end #300 $dumpon 1! 0" 1# 0$ 0% 0& 0' 0( 0) 0* 0+ 1, $end #350 0! #400 1! 1+ #450 0! #500 1! 1* #550 0! #600 1! 1) #650 0! #700 1! 1( #750 0! #800 1! 1' #850 0! #900 1! 1& #950 0! #1000 1! 1% #1050 0! #1100 1! 1$ #1150 0!

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Value Change Dump (VCD) Files Capturing Port Driver Data 1" 0, 0+ 0* 0) 0( 0' 0& 0% 0$ #1200 1! $dumpall 1! 1" 1# 0$ 0% 0& 0' 0( 0) 0* 0+ 0, $end

Capturing Port Driver Data

Some ASIC vendors toolkits read a VCD file format that provides details on port drivers. This information can be used, for example, to drive a tester. See the ASIC vendors documentation for toolkit specific information. In ModelSim use the vcd dumpports command to create a VCD file that captures port driver data. Each time an external or internal port driver changes values, a new value change is recorded in the VCD file with the following format:
p<state> <0 strength> <1 strength> <identifier_code>

Driver States
The driver states are recorded as TSSI states if the direction is known, as detailed in this table: Table 20-4. Driver States Input (testfixture) D low U high N unknown Z tri-state
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Table 20-4. Driver States (cont.) Input (testfixture) Output (dut) d low (two or more l low (two or more drivers active) drivers active) u high (two or more h high (two or drivers active) more drivers active) If the direction is unknown, the state will be recorded as one of the following: Table 20-5. State When Direction is Unknown Unknown direction 0 low (both input and output are driving low) 1 high (both input and output are driving high) ? unknown (both input and output are driving unknown) F three-state (input and output unconnected) A unknown (input driving low and output driving high) a unknown (input driving low and output driving unknown) B unknown (input driving high and output driving low) b unknown (input driving high and output driving unknown) C unknown (input driving unknown and output driving low) c unknown (input driving unknown and output driving high) f unknown (input and output three-stated)

Driver Strength
The recorded 0 and 1 strength values are based on Verilog strengths: Table 20-6. Driver Strength Strength 0 highz 1 small VHDL std_logic mappings Z

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Table 20-6. Driver Strength (cont.) Strength 2 medium 3 weak 4 large 5 pull 6 strong 7 supply W,H,L U,X,0,1,- VHDL std_logic mappings

Identifier Code
The <identifier_code> is an integer preceded by < that starts at zero and is incremented for each port in the order the ports are specified. Also, the variable type recorded in the VCD header is "port".

Resolving Values
The resolved values written to the VCD file depend on which options you specify when creating the file.

Default Behavior
By default ModelSim generates output according to IEEE 1364-2005. The standard states that the values 0 (both input and output are active with value 0) and 1 (both input and output are active with value 1) are conflict states. The standard then defines two strength ranges: Strong: strengths 7, 6, and 5 Weak: strengths 4, 3, 2, 1

The rules for resolving values are as follows: If the input and output are driving the same value with the same range of strength, the resolved value is 0 or 1, and the strength is the stronger of the two. If the input is driving a strong strength and the output is driving a weak strength, the resolved value is D, d, U or u, and the strength is the strength of the input. If the input is driving a weak strength and the output is driving a strong strength, the resolved value is L, l, H or h, and the strength is the strength of the output.

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Ignoring Strength Ranges

You may wish to ignore strength ranges and have ModelSim handle each strength separately. Any of the following options will produce this behavior: Use the -no_strength_range argument to the vcd dumpports command Use an optional argument to $dumpports (see Extended $dumpports Syntax below) Use the +dumpports+no_strength_range argument to vsim command

In this situation, ModelSim reports strengths for both the zero and one components of the value if the strengths are the same. If the strengths are different, ModelSim reports only the winning strength. In other words, the two strength values either match (e.g., pA 5 5 !) or the winning strength is shown and the other is zero (e.g., pH 0 5 !).

Extended $dumpports Syntax

ModelSim extends the $dumpports system task in order to support exclusion of strength ranges. The extended syntax is as follows:
$dumpports (scope_list, file_pathname, ncsim_file_index, file_format)

The nc_sim_index argument is required yet ignored by ModelSim. It is required only to be compatible with NCSims argument list. The file_format argument accepts the following values or an ORed combination thereof (see examples below): Table 20-7. Values for file_format Argument File_format value 0 2 4 8 Meaning Ignore strength range Use strength ranges; produces IEEE 1364-compliant behavior Compress the EVCD output Include port direction information in the EVCD file header; same as using -direction argument to vcd dumpports

Here are some examples:

// ignore strength range $dumpports(top, "filename", 0, 0) // compress and ignore strength range $dumpports(top, "filename", 0, 4) // print direction and ignore strength range $dumpports(top, "filename", 0, 8)

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Value Change Dump (VCD) Files Capturing Port Driver Data // compress, print direction, and ignore strength range $dumpports(top, "filename", 0, 12)

Example 20-5. VCD Output from vcd dumpports This example demonstrates how vcd dumpports resolves values based on certain combinations of driver values and strengths and whether or not you use strength ranges. Table 20-8 is sample driver data. Table 20-8. Sample Driver Data time 0 100 200 300 900 27400 27500 27600 in value 0 0 0 0 1 1 1 1 out value in strength value out strength value (range) (range) 0 0 0 0 0 1 1 1 7 (strong) 6 (strong) 5 (strong) 4 (weak) 6 (strong) 5 (strong) 4 (weak) 3 (weak) 7 (strong) 7 (strong) 7 (strong) 7 (strong) 7 (strong) 4 (weak) 4 (weak) 4 (weak)

Given the driver data above and use of 1364 strength ranges, here is what the VCD file output would look like:
#0 p0 7 0 #100 p0 7 0 #200 p0 7 0 #300 pL 7 0 #900 pB 7 0 #27400 pU 0 5 #27500 p1 0 4 #27600 p1 0 4 <0 <0 <0 <0 <0 <0 <0 <0

Here is what the output would look like if you ignore strength ranges:

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Value Change Dump (VCD) Files Capturing Port Driver Data #0 p0 7 0 #100 pL 7 0 #200 pL 7 0 #300 pL 7 0 #900 pL 7 0 #27400 pU 0 5 #27500 p1 0 4 #27600 pH 0 4

<0 <0 <0 <0 <0 <0 <0 <0

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Chapter 21 Tcl and Macros (DO Files)

Tcl is a scripting language for controlling and extending ModelSim. Within ModelSim you can develop implementations from Tcl scripts without the use of C code. Because Tcl is interpreted, development is rapid; you can generate and execute Tcl scripts on the fly without stopping to recompile or restart ModelSim. In addition, if ModelSim does not provide the command you need, you can use Tcl to create your own commands.

Tcl Features
Using Tcl with ModelSim gives you these features: command history (like that in C shells) full expression evaluation and support for all C-language operators a full range of math and trig functions support of lists and arrays regular expression pattern matching procedures the ability to define your own commands command substitution (that is, commands may be nested) robust scripting language for macros

Tcl References
Two books about Tcl are Tcl and the Tk Toolkit by John K. Ousterhout, published by AddisonWesley Publishing Company, Inc., and Practical Programming in Tcl and Tk by Brent Welch published by Prentice Hall. You can also consult the following online references: Select Help > Tcl Man Pages.

Tcl Commands
For complete information on Tcl commands, select Help > Tcl Man Pages. Also see Simulator GUI Preferences for information on Tcl preference variables.

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ModelSim command names that conflict with Tcl commands have been renamed or have been replaced by Tcl commands. See the list below: Table 21-1. Previous ModelSim Command changed to (or replaced by) command continue format list | wave if list nolist | nowave set source wave run with the -continue option write format with either list or wave specified replaced by the Tcl if command, see If Command Syntax for more information add list delete with either list or wave specified replaced by the Tcl set command vsource add wave

Tcl Command Syntax

The following eleven rules define the syntax and semantics of the Tcl language. Additional details on If Command Syntax. 1. A Tcl script is a string containing one or more commands. Semi-colons and newlines are command separators unless quoted as described below. Close brackets ("]") are command terminators during command substitution (see below) unless quoted. 2. A command is evaluated in two steps. First, the Tcl interpreter breaks the command into words and performs substitutions as described below. These substitutions are performed in the same way for all commands. The first word is used to locate a command procedure to carry out the command, then all of the words of the command are passed to the command procedure. The command procedure is free to interpret each of its words in any way it likes, such as an integer, variable name, list, or Tcl script. Different commands interpret their words differently. 3. Words of a command are separated by white space (except for newlines, which are command separators). 4. If the first character of a word is a double-quote (") then the word is terminated by the next double-quote character. If semi-colons, close brackets, or white space characters (including newlines) appear between the quotes then they are treated as ordinary characters and included in the word. Command substitution, variable substitution, and backslash substitution are performed on the characters between the quotes as described below. The double-quotes are not retained as part of the word.

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5. If the first character of a word is an open brace ({) then the word is terminated by the matching close brace (}). Braces nest within the word: for each additional open brace there must be an additional close brace (however, if an open brace or close brace within the word is quoted with a backslash then it is not counted in locating the matching close brace). No substitutions are performed on the characters between the braces except for backslash-newline substitutions described below, nor do semi-colons, newlines, close brackets, or white space receive any special interpretation. The word will consist of exactly the characters between the outer braces, not including the braces themselves. 6. If a word contains an open bracket ([) then Tcl performs command substitution. To do this it invokes the Tcl interpreter recursively to process the characters following the open bracket as a Tcl script. The script may contain any number of commands and must be terminated by a close bracket (]). The result of the script (i.e. the result of its last command) is substituted into the word in place of the brackets and all of the characters between them. There may be any number of command substitutions in a single word. Command substitution is not performed on words enclosed in braces. 7. If a word contains a dollar-sign ($) then Tcl performs variable substitution: the dollarsign and the following characters are replaced in the word by the value of a variable. Variable substitution may take any of the following forms:
o

$name Name is the name of a scalar variable; the name is terminated by any character that isn't a letter, digit, or underscore.

$name(index) Name gives the name of an array variable and index gives the name of an element within that array. Name must contain only letters, digits, and underscores. Command substitutions, variable substitutions, and backslash substitutions are performed on the characters of index.

${name} Name is the name of a scalar variable. It may contain any characters whatsoever except for close braces. There may be any number of variable substitutions in a single word. Variable substitution is not performed on words enclosed in braces.

8. If a backslash (\) appears within a word then backslash substitution occurs. In all cases but those described below the backslash is dropped and the following character is treated as an ordinary character and included in the word. This allows characters such as double quotes, close brackets, and dollar signs to be included in words without

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triggering special processing. The following table lists the backslash sequences that are handled specially, along with the value that replaces each sequence. Table 21-2. Tcl Backslash Sequences Sequence \a \b \f \n \r \t \v \<newline>whiteSpace Value Audible alert (bell) (0x7) Backspace (0x8) Form feed (0xc). Newline (0xa) Carriage-return (0xd) Tab (0x9) Vertical tab (0xb) A single space character replaces the backslash, newline, and all spaces and tabs after the newline. This backslash sequence is unique in that it is replaced in a separate prepass before the command is actually parsed. This means that it will be replaced even when it occurs between braces, and the resulting space will be treated as a word separator if it isn't in braces or quotes. Backslash ("\") The digits ooo (one, two, or three of them) give the octal value of the character. The hexadecimal digits hh give the hexadecimal value of the character. Any number of digits may be present.

\\ \ooo \xhh

Backslash substitution is not performed on words enclosed in braces, except for backslash-newline as described above. 9. If a hash character (#) appears at a point where Tcl is expecting the first character of the first word of a command, then the hash character and the characters that follow it, up through the next newline, are treated as a comment and ignored. The comment character only has significance when it appears at the beginning of a command. 10. Each character is processed exactly once by the Tcl interpreter as part of creating the words of a command. For example, if variable substitution occurs then no further substitutions are performed on the value of the variable; the value is inserted into the word verbatim. If command substitution occurs then the nested command is processed entirely by the recursive call to the Tcl interpreter; no substitutions are performed before making the recursive call and no additional substitutions are performed on the result of the nested script.

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11. Substitutions do not affect the word boundaries of a command. For example, during variable substitution the entire value of the variable becomes part of a single word, even if the variable's value contains spaces.

If Command Syntax
The Tcl if command executes scripts conditionally. Note that in the syntax below the question mark (?) indicates an optional argument. Syntax
if expr1 ?then? body1 elseif expr2 ?then? body2 elseif ... ?else? ?bodyN?

Description The if command evaluates expr1 as an expression. The value of the expression must be a boolean (a numeric value, where 0 is false and anything else is true, or a string value such as true or yes for true and false or no for false); if it is true then body1 is executed by passing it to the Tcl interpreter. Otherwise expr2 is evaluated as an expression and if it is true then body2 is executed, and so on. If none of the expressions evaluates to true then bodyN is executed. The then and else arguments are optional "noise words" to make the command easier to read. There may be any number of elseif clauses, including zero. BodyN may also be omitted as long as else is omitted too. The return value from the command is the result of the body script that was executed, or an empty string if none of the expressions was non-zero and there was no bodyN.

Command Substitution
Placing a command in square brackets ([ ]) will cause that command to be evaluated first and its results returned in place of the command. An example is:
set a 25 set b 11 set c 3 echo "the result is [expr ($a + $b)/$c]"

will output:
"the result is 12"

This feature allows VHDL variables and signals, and Verilog nets and registers to be accessed using:
[examine -<radix> name]

The %name substitution is no longer supported. Everywhere %name could be used, you now can use [examine -value -<radix> name] which allows the flexibility of specifying command options. The radix specification is optional.

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Command Separator
A semicolon character (;) works as a separator for multiple commands on the same line. It is not required at the end of a line in a command sequence.

Multiple-Line Commands
With Tcl, multiple-line commands can be used within macros and on the command line. The command line prompt will change (as in a C shell) until the multiple-line command is complete. In the example below, note the way the opening brace { is at the end of the if and else lines. This is important because otherwise the Tcl scanner won't know that there is more coming in the command and will try to execute what it has up to that point, which won't be what you intend.
if { [exa sig_a] == "0011ZZ"} { echo "Signal value matches" do macro_1.do } else { echo "Signal value fails" do macro_2.do }

Evaluation Order
An important thing to remember when using Tcl is that anything put in braces ({}) is not evaluated immediately. This is important for if-then-else statements, procedures, loops, and so forth.

Tcl Relational Expression Evaluation

When you are comparing values, the following hints may be useful: Tcl stores all values as strings, and will convert certain strings to numeric values when appropriate. If you want a literal to be treated as a numeric value, don't quote it.
if {[exa var_1] == 345}...

The following will also work:

if {[exa var_1] == "345"}...

However, if a literal cannot be represented as a number, you must quote it, or Tcl will give you an error. For instance:
if {[exa var_2] == 001Z}...

will give an error.

if {[exa var_2] == "001Z"}...

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will work okay. Don't quote single characters in single quotes:

if {[exa var_3] == 'X'}...

will give an error

if {[exa var_3] == "X"}...

will work okay. For the equal operator, you must use the C operator (==). For not-equal, you must use the C operator (!=).

Variable Substitution
When a $<var_name> is encountered, the Tcl parser will look for variables that have been defined either by ModelSim or by you, and substitute the value of the variable. Note Tcl is case sensitive for variable names.

To access environment variables, use the construct:

$env(<var_name>) echo My user name is $env(USER)

Environment variables can also be set using the env array:

set env(SHELL) /bin/csh

See Simulator State Variables for more information about ModelSim-defined variables.

System Commands
To pass commands to the UNIX shell or DOS window, use the Tcl exec command:
echo The date is [exec date]

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List Processing
In Tcl a "list" is a set of strings in curly braces separated by spaces. Several Tcl commands are available for creating lists, indexing into lists, appending to lists, getting the length of lists and shifting lists. These commands are: Table 21-3. Tcl List Commands Command syntax lappend var_name val1 val2 ... lindex list_name index linsert list_name index val1 val2 ... list val1, val2 ... llength list_name lrange list_name first last Description appends val1, val2, etc. to list var_name returns the index-th element of list_name; the first element is 0 inserts val1, val2, etc. just before the index-th element of list_name returns a Tcl list consisting of val1, val2, etc. returns the number of elements in list_name returns a sublist of list_name, from index first to index last; first or last may be "end", which refers to the last element in the list replaces elements first through last with val1, val2, etc.

lreplace list_name first last val1, val2, ...

Two other commands, lsearch and lsort, are also available for list manipulation. See the Tcl man pages (Help > Tcl Man Pages) for more information on these commands.

Simulator Tcl Commands

These additional commands enhance the interface between Tcl and ModelSim. Only brief descriptions are provided here; for more information and command syntax see the Reference Manual. Table 21-4. Simulator-Specific Tcl Commands Command alias find lshift lsublist Description creates a new Tcl procedure that evaluates the specified commands; used to create a user-defined alias locates incrTcl classes and objects takes a Tcl list as argument and shifts it in-place one place to the left, eliminating the 0th element returns a sublist of the specified Tcl list that matches the specified Tcl glob pattern

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Table 21-4. Simulator-Specific Tcl Commands Command printenv Description echoes to the Transcript pane the current names and values of all environment variables

Simulator Tcl Time Commands

ModelSim Tcl time commands make simulator-time-based values available for use within other Tcl procedures. Time values may optionally contain a units specifier where the intervening space is also optional. If the space is present, the value must be quoted (e.g. 10ns, "10 ns"). Time values without units are taken to be in the UserTimeScale. Return values are always in the current Time Scale Units. All time values are converted to a 64-bit integer value in the current Time Scale. This means that values smaller than the current Time Scale will be truncated to 0.

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Conversions
Table 21-5. Tcl Time Conversion Commands Command intToTime <intHi32> <intLo32>
Description

converts two 32-bit pieces (high and low order) into a 64-bit quantity (Time in ModelSim is a 64-bit integer) converts a <real> number to a 64-bit integer in the current Time Scale returns the value of <time> multiplied by the <scaleFactor> integer

RealToTime <real> scaleTime <time> <scaleFactor>

Relations
Table 21-6. Tcl Time Relation Commands Command eqTime <time> <time> neqTime <time> <time> gtTime <time> <time> gteTime <time> <time> ltTime <time> <time> lteTime <time> <time>
Description

evaluates for equal evaluates for not equal evaluates for greater than evaluates for greater than or equal evaluates for less than evaluates for less than or equal

All relation operations return 1 or 0 for true or false respectively and are suitable return values for TCL conditional expressions. For example,
if {[eqTime $Now 1750ns]} { ... }

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Arithmetic
Table 21-7. Tcl Time Arithmetic Commands Command addTime <time> <time> divTime <time> <time> mulTime <time> <time> subTime <time> <time>
Description

add time 64-bit integer divide 64-bit integer multiply subtract time

Tcl Examples
This is an example of using the Tcl while loop to copy a list from variable a to variable b, reversing the order of the elements along the way:
set b [list] set i [expr {[llength $a] - 1}] while {$i >= 0} { lappend b [lindex $a $i] incr i -1 }

This example uses the Tcl for command to copy a list from variable a to variable b, reversing the order of the elements along the way:
set b [list] for {set i [expr {[llength $a] - 1}]} {$i >= 0} {incr i -1} { lappend b [lindex $a $i] }

This example uses the Tcl foreach command to copy a list from variable a to variable b, reversing the order of the elements along the way (the foreach command iterates over all of the elements of a list):
set b [list] foreach i $a { set b [linsert $b 0 $i] }

This example shows a list reversal as above, this time aborting on a particular element using the Tcl break command:
set b [list] foreach i $a { if {$i = "ZZZ"} break set b [linsert $b 0 $i] }

This example is a list reversal that skips a particular element by using the Tcl continue command:
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Tcl and Macros (DO Files) Tcl Examples set b [list] foreach i $a { if {$i = "ZZZ"} continue set b [linsert $b 0 $i] }

The next example works in UNIX only. In a Windows environment, the Tcl exec command will execute compiled files only, not system commands.) The example shows how you can access system information and transfer it into VHDL variables or signals and Verilog nets or registers. When a particular HDL source breakpoint occurs, a Tcl function is called that gets the date and time and deposits it into a VHDL signal of type STRING. If a particular environment variable (DO_ECHO) is set, the function also echoes the new date and time to the transcript file by examining the VHDL variable. (in VHDL source):
signal datime : string(1 to 28) := " ";# 28 spaces

(on VSIM command line or in macro):

proc set_date {} { global env set do_the_echo [set env(DO_ECHO)] set s [clock format [clock seconds]] force -deposit datime $s if {do_the_echo} { echo "New time is [examine -value datime]" } } bp src/waveadd.vhd 133 {set_date; continue} --sets the breakpoint to call set_date

This next example shows a complete Tcl script that restores multiple Wave windows to their state in a previous simulation, including signals listed, geometry, and screen position. It also adds buttons to the Main window toolbar to ease management of the wave files.
## This file contains procedures to manage multiple wave files. ## Source this file from the command line or as a startup script. ## source <path>/wave_mgr.tcl ## add_wave_buttons ## Add wave management buttons to the main toolbar (new, save and load) ## new_wave ## Dialog box creates a new wave window with the user provided name ## named_wave <name> ## Creates a new wave window with the specified title ## save_wave <file-root> ## Saves name, window location and contents for all open windows ## wave windows ## Creates <file-root><n>.do file for each window where <n> is 1 ## to the number of windows. Default file-root is "wave". Also ## creates windowSet.do file that contains title and geometry info.

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Tcl and Macros (DO Files) Tcl Examples ## load_wave <file-root> ## Opens and loads wave windows for all files matching <fileroot><n>.do ## where <n> are the numbers from 1-9. Default <file-root> is "wave". ## Also runs windowSet.do file if it exists. ## Add wave management buttons to the main toolbar proc add_wave_buttons {} { _add_menu main controls right SystemMenu SystemWindowFrame {Load Waves} \ load_wave _add_menu main controls right SystemMenu SystemWindowFrame {Save Waves} \ save_wave _add_menu main controls right SystemMenu SystemWindowFrame {New Wave} \ new_wave } ## Simple Dialog requests name of new wave window. Defaults to Wave<n> proc new_wave {} { global vsimPriv set defaultName "Wave[llength $vsimPriv(WaveWindows)]" set windowName [GetValue . "Create Named Wave Window:" $defaultName ] if {$windowName == ""} { # Dialog canceled # abort operation return } ## Debug puts "Window name: $windowName\n" if {$windowName == "{}"} { set windowName "" } if {$windowName != ""} { named_wave $windowName } else { named_wave $defaultName } } ## Creates a new wave window with the provided name (defaults to "Wave") proc named_wave {{name "Wave"}} { set newWave [view -new wave] if {[string length $name] > 0} { wm title $newWave $name } } ## Writes out format of all wave windows, stores geometry and title info in ## windowSet.do file. Removes any extra files with the same fileroot. ## Default file name is wave<n> starting from 1.

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Tcl and Macros (DO Files) Tcl Examples proc save_wave {{fileroot "wave"}} { global vsimPriv set n 1 if {[catch {open windowSet_$fileroot.do w 755} fileId]} { error "Open failure for $fileroot ($fileId)" } foreach w $vsimPriv(WaveWindows) { echo "Saving: [wm title $w]" set filename $fileroot$n.do if {[file exists $filename]} { # Use different file set n2 0 while {[file exists ${fileroot}${n}${n2}.do]} { incr n2 } set filename ${fileroot}${n}${n2}.do } write format wave -window $w $filename puts $fileId "wm title $w \"[wm title $w]\"" puts $fileId "wm geometry $w [wm geometry $w]" puts $fileId "mtiGrid_colconfig $w.grid name -width \ [mtiGrid_colcget $w.grid name -width]" puts $fileId "mtiGrid_colconfig $w.grid value -width \ [mtiGrid_colcget $w.grid value -width]" flush $fileId incr n } foreach f [lsort [glob -nocomplain $fileroot\[$n-9\].do]] { echo "Removing: $f" exec rm $f } } } ## Provide file root argument and load_wave restores all saved windows. ## Default file root is "wave". proc load_wave {{fileroot "wave"}} { foreach f [lsort [glob -nocomplain $fileroot\[1-9\].do]] { echo "Loading: $f" view -new wave do $f } if {[file exists windowSet_$fileroot.do]} { do windowSet_$fileroot.do } } ...

This next example specifies the compiler arguments and lets you compile any number of files.

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Tcl and Macros (DO Files) Macros (DO Files) set Files [list] set nbrArgs $argc for {set x 1} {$x <= $nbrArgs} {incr x} { set lappend Files $1 shift } eval vcom -93 -explicit -noaccel $Files

This example is an enhanced version of the last one. The additional code determines whether the files are VHDL or Verilog and uses the appropriate compiler and arguments depending on the file type. Note that the macro assumes your VHDL files have a .vhd file extension.
set set set for vhdFiles [list] vFiles [list] nbrArgs $argc {set x 1} {$x <= $nbrArgs} {incr x} { if {[string match *.vhd $1]} { lappend vhdFiles $1 } else { lappend vFiles $1 } shift $vhdFiles] > 0} { -93 -explicit -noaccel $vhdFiles $vFiles] > 0} { $vFiles

} if {[llength eval vcom } if {[llength eval vlog }

Macros (DO Files)

ModelSim macros (also called DO files) are simply scripts that contain ModelSim and, optionally, Tcl commands. You invoke these scripts with the Tools > TCL > Execute Macro menu selection or the do command.

Creating DO Files
You can create DO files, like any other Tcl script, by typing the required commands in any editor and saving the file. Alternatively, you can save the transcript as a DO file (see Saving the Transcript File). All "event watching" commands (e.g. onbreak, onerror, etc.) must be placed before run commands within the macros in order to take effect. The following is a simple DO file that was saved from the transcript. It is used in the dataset exercise in the ModelSim Tutorial. This DO file adds several signals to the Wave window, provides stimulus to those signals, and then advances the simulation.

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Tcl and Macros (DO Files) Macros (DO Files) add wave ld add wave rst add wave clk add wave d add wave q force -freeze clk 0 0, 1 {50 ns} -r 100 force rst 1 force rst 0 10 force ld 0 force d 1010 onerror {cont} run 1700 force ld 1 run 100 force ld 0 run 400 force rst 1 run 200 force rst 0 10 run 1500

Using Parameters with DO Files

You can increase the flexibility of DO files by using parameters. Parameters specify values that are passed to the corresponding parameters $1 through $9 in the macro file. For example say the macro "testfile" contains the line bp $1 $2. The command below would place a breakpoint in the source file named design.vhd at line 127:
do testfile design.vhd 127

There is no limit on the number of parameters that can be passed to macros, but only nine values are visible at one time. You can use the shift command to see the other parameters.

Deleting a File from a .do Script

To delete a file from a .do script, use the Tcl file command as follows:
file delete myfile.log

This will delete the file "myfile.log." You can also use the transcript file command to perform a deletion:
transcript file () transcript file my file.log

The first line will close the current log file. The second will open a new log file. If it has the same name as an existing file, it will replace the previous one.

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Making Macro Parameters Optional

If you want to make macro parameters optional (i.e., be able to specify fewer parameter values with the do command than the number of parameters referenced in the macro), you must use the argc simulator state variable. The argc simulator state variable returns the number of parameters passed. The examples below show several ways of using argc.

Example 1
This macro specifies the files to compile and handles 0-2 compiler arguments as parameters. If you supply more arguments, ModelSim generates a message.
switch $argc { 0 {vcom file1.vhd file2.vhd file3.vhd } 1 {vcom $1 file1.vhd file2.vhd file3.vhd } 2 {vcom $1 $2 file1.vhd file2.vhd file3.vhd } default {echo Too many arguments. The macro accepts 0-2 args. }

Example 2
This macro specifies the compiler arguments and lets you compile any number of files.
variable Files "" set nbrArgs $argc for {set x 1} {$x <= $nbrArgs} {incr x} { set Files [concat $Files $1] shift } eval vcom -93 -explicit -noaccel $Files

Example 3
This macro is an enhanced version of the one shown in example 2. The additional code determines whether the files are VHDL or Verilog and uses the appropriate compiler and arguments depending on the file type. Note that the macro assumes your VHDL files have a .vhd file extension.

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Tcl and Macros (DO Files) Macros (DO Files) variable vhdFiles "" variable vFiles "" set nbrArgs $argc set vhdFilesExist 0 set vFilesExist 0 for {set x 1} {$x <= $nbrArgs} {incr x} { if {[string match *.vhd $1]} { set vhdFiles [concat $vhdFiles $1] set vhdFilesExist 1 } else { set vFiles [concat $vFiles $1] set vFilesExist 1 } shift } if {$vhdFilesExist == 1} { eval vcom -93 -explicit -noaccel $vhdFiles } if {$vFilesExist == 1} { eval vlog $vFiles }

Useful Commands for Handling Breakpoints and Errors

If you are executing a macro when your simulation hits a breakpoint or causes a run-time error, ModelSim interrupts the macro and returns control to the command line. The following commands may be useful for handling such events. (Any other legal command may be executed as well.) Table 21-8. Commands for Handling Breakpoints and Errors in Macros command run -continue onbreak onElabError onerror status abort pause result continue as if the breakpoint had not been executed, completes the run that was interrupted specify a command to run when you hit a breakpoint within a macro specify a command to run when an error is encountered during elaboration specify a command to run when an error is encountered within a macro get a traceback of nested macro calls when a macro is interrupted terminate a macro once the macro has been interrupted or paused cause the macro to be interrupted; the macro can be resumed by entering a resume command via the command line

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You can also set the OnErrorDefaultAction Tcl variable to determine what action ModelSim takes when an error occurs. To set the variable on a permanent basis, you must define the variable in a modelsim.tcl file (see The modelsim.tcl File for details).

Error Action in DO Files

If a command in a macro returns an error, ModelSim does the following: 1. If an onerror command has been set in the macro script, ModelSim executes that command. The onerror command must be placed prior to the run command in the DO file to take effect. 2. If no onerror command has been specified in the script, ModelSim checks the OnErrorDefaultAction variable. If the variable is defined, its action will be invoked. 3. If neither 1 or 2 is true, the macro aborts.

Using the Tcl Source Command with DO Files

Either the do command or Tcl source command can execute a DO file, but they behave differently. With the source command, the DO file is executed exactly as if the commands in it were typed in by hand at the prompt. Each time a breakpoint is hit, the Source window is updated to show the breakpoint. This behavior could be inconvenient with a large DO file containing many breakpoints. When a do command is interrupted by an error or breakpoint, it does not update any windows, and keeps the DO file "locked". This keeps the Source window from flashing, scrolling, and moving the arrow when a complex DO file is executed. Typically an onbreak resume command is used to keep the macro running as it hits breakpoints. Add an onbreak abort command to the DO file if you want to exit the macro and update the Source window.

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Appendix A Simulator Variables

This appendix documents the following types of variables: Environment Variables Variables referenced and set according to operating system conventions. Environment variables prepare the ModelSim environment prior to simulation. Simulator Control Variables Variables used to control compiler, simulator, and various other functions. Simulator State Variables Variables that provide feedback on the state of the current simulation.

Variable Settings Report

The report command returns a list of current settings for either the simulator state or simulator control variables. Use the following commands at either the ModelSim or VSIM prompt:
report simulator state report simulator control

Environment Variables
Environment Variable Expansion
The shell commands vcom, vlog, vsim, and vmap, no longer expand environment variables in filename arguments and options. Instead, variables should be expanded by the shell beforehand, in the usual manner. The -f option that most of these commands support, now performs environment variable expansion throughout the file. Environment variable expansion is still performed in the following places: Pathname and other values in the modelsim.ini file Strings used as file pathnames in VHDL and Verilog VHDL Foreign attributes The PLIOBJS environment variable may contain a path that has an environment variable. Verilog `uselib file and dir directives
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Anywhere in the contents of a -f file

The recommended method for using flexible pathnames is to make use of the MGC Location Map system (see Using Location Mapping). When this is used, then pathnames stored in libraries and project files (.mpf) will be converted to logical pathnames. If a file or path name contains the dollar sign character ($), and must be used in one of the places listed above that accepts environment variables, then the explicit dollar sign must be escaped by using a double dollar sign ($$).

Setting Environment Variables

Before compiling or simulating, several environment variables may be set to provide the functions described below. The variables are set through the System control panel on Windows 2000 and XP machines. For UNIX, the variables are typically found in the .login script. The LM_LICENSE_FILE variable is required; all others are optional.

DOPATH
The toolset uses the DOPATH environment variable to search for DO files (macros). DOPATH consists of a colon-separated (semi-colon for Windows) list of paths to directories. You can override this environment variable with the DOPATH Tcl preference variable. The DOPATH environment variable isnt accessible when you invoke vsim from a UNIX shell or from a Windows command prompt. It is accessible once ModelSim or vsim is invoked. If you need to invoke from a shell or command line and use the DOPATH environment variable, use the following syntax:
vsim -do "do <dofile_name>" <design_unit>

EDITOR
The EDITOR environment variable specifies the editor to invoke with the edit command

HOME
The toolset uses the HOME environment variable to look for an optional graphical preference file and optional location map file. Refer to Simulator Control Variables for additional information.

HOME_0IN
The HOME_0IN environment variable identifies the location of the 0-In executables directory. Refer to the 0-In documentation for more information.

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LD_LIBRARY_PATH
A UNIX shell environment variable setting the search directories for shared libraries. It instructs the OS where to search for the shared libraries for FLI/PLI/VPI/DPI. This variable is used for both 32-bit and 64-bit shared libraries on Solaris/Linux systems.

LD_LIBRARY_PATH_32
A UNIX shell environment variable setting the search directories for shared libraries. It instructs the OS where to search for the shared libraries for FLI/PLI/VPI/DPI. This variable is used only for 32-bit shared libraries on Solaris/Linux systems.

LD_LIBRARY_PATH_64
A UNIX shell environment variable setting the search directories for shared libraries. It instructs the OS where to search for the shared libraries for FLI/PLI/VPI/DPI. This variable is used only for 64-bit shared libraries on Solaris/Linux systems.

LM_LICENSE_FILE
The toolsets file manager uses the LM_LICENSE_FILE environment variable to find the location of the license file. The argument may be a colon-separated (semi-colon for Windows) set of paths, including paths to other vendor license files. The environment variable is required.

MODEL_TECH
The toolset automatically sets the MODEL_TECH environment variable to the directory in which the binary executable resides; DO NOT SET THIS VARIABLE!

MODEL_TECH_TCL
The toolset uses the MODEL_TECH_TCL environment variable to find Tcl libraries for Tcl/Tk 8.3 and vsim, and may also be used to specify a startup DO file. This variable defaults to /modeltech/../tcl, however you may set it to an alternate path

MGC_LOCATION_MAP
The toolset uses the MGC_LOCATION_MAP environment variable to find source files based on easily reallocated "soft" paths.

MODELSIM
The toolset uses the MODELSIM environment variable to find the modelsim.ini file. The argument consists of a path including the file name. An alternative use of this variable is to set it to the path of a project file (<Project_Root_Dir>/<Project_Name>.mpf). This allows you to use project settings with

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command line tools. However, if you do this, the .mpf file will replace modelsim.ini as the initialization file for all tools.

MODELSIM_PREFERENCES
The MODELSIM_PREFERENCES environment variable specifies the location to store user interface preferences. Setting this variable with the path of a file instructs the toolset to use this file instead of the default location (your HOME directory in UNIX or in the registry in Windows). The file does not need to exist beforehand, the toolset will initialize it. Also, if this file is read-only, the toolset will not update or otherwise modify the file. This variable may contain a relative pathname in which case the file will be relative to the working directory at the time the tool is started.

MODELSIM_TCL
The toolset uses the MODELSIM_TCL environment variable to look for an optional graphical preference file. The argument can be a colon-separated (UNIX) or semi-colon separated (Windows) list of file paths.

MTI_COSIM_TRACE
The MTI_COSIM_TRACE environment variable creates an mti_trace_cosim file containing debugging information about FLI/PLI/VPI function calls. You should set this variable to any value before invoking the simulator.

MTI_TF_LIMIT
The MTI_TF_LIMIT environment variable limits the size of the VSOUT temp file (generated by the toolsets kernel). Set the argument of this variable to the size of k-bytes The environment variable TMPDIR controls the location of this file, while STDOUT controls the name. The default setting is 10, and a value of 0 specifies that there is no limit. This variable does not control the size of the transcript file.

MTI_RELEASE_ON_SUSPEND
The MTI_RELEASE_ON_SUSPEND environment variable allows you to turn off or modify the delay for the functionality of releasing all licenses when the tool is suspended. The default setting is 10 (in seconds), which means that if you do not set this variable your licenses will be released 10 seconds after your run is suspended. If you set this environment variable with an argument of 0 (zero) the tool will not release the licenses after being suspended. You can change the default length of time (number of seconds) by setting this environment variable to an integer greater than 0 (zero).

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MTI_USELIB_DIR
The MTI_USELIB_DIR environment variable specifies the directory into which object libraries are compiled when using the -compile_uselibs argument to the vlog command

NOMMAP
When set to 1, the NOMMAP environment variable disables memory mapping in the toolset. You should only use this variable when running on Linux 7.1 because it will decrease the speed with which the tool reads files.

PLIOBJS
The toolset uses the PLIOBJS environment variable to search for PLI object files for loading. The argument consists of a space-separated list of file or path names

STDOUT
The argument to the STDOUT environment variable specifies a filename to which the simulator saves the VSOUT temp file information. Typically this information is deleted when the simulator exits. The location for this file is set with the TMPDIR variable, which allows you to find and delete the file in the event of a crash, because an unnamed VSOUT file is not deleted after a crash.

TMP
(Windows environments) The TMP environment variable specifies the path to a tempnam() generated file (VSOUT) containing all stdout from the simulation kernel.

TMPDIR
(UNIX environments) The TMPDIR environment variable specifies the path to a tempnam() generated file (VSOUT) containing all stdout from the simulation kernel.

Creating Environment Variables in Windows

In addition to the predefined variables shown above, you can define your own environment variables. This example shows a user-defined library path variable that can be referenced by the vmap command to add library mapping to the modelsim.ini file. 1. From your desktop, right-click your My Computer icon and select Properties 2. In the System Properties dialog box, select the Advanced tab 3. Click Environment Variables 4. In the Environment Variables dialog box and User variables for <user> pane, select New:

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5. In the New User Variable dialog box, add the new variable with this data
Variable ame: MY_PATH Variable value:\temp\work

6. OK (New User Variable, Environment Variable, and System Properties dialog boxes)

Library Mapping with Environment Variables

Once the MY_PATH variable is set, you can use it with the vmap command to add library mappings to the current modelsim.ini file. Table A-1. Add Library Mappings to modelsim.ini File Prompt Type DOS prompt ModelSim or vsim prompt Command vmap MY_VITAL %MY_PATH% vmap MY_VITAL \$MY_PATH1 Result added to modelsim.ini MY_VITAL = c:\temp\work MY_VITAL = $MY_PATH

1. The dollar sign ($) character is Tcl syntax that indicates a variable. The backslash (\) character is an escape character that prevents the variable from being evaluated during the execution of vmap.

You can easily add additional hierarchy to the path. For example,
vmap MORE_VITAL %MY_PATH%\more_path\and_more_path vmap MORE_VITAL \$MY_PATH\more_path\and_more_path

Referencing Environment Variables

There are two ways to reference environment variables within ModelSim. Environment variables are allowed in a FILE variable being opened in VHDL. For example,
use std.textio.all; entity test is end; architecture only of test is begin process FILE in_file : text is in "$ENV_VAR_NAME"; begin wait; end process; end;

Environment variables may also be referenced from the ModelSim command line or in macros using the Tcl env array mechanism:
echo "$env(ENV_VAR_NAME)"

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Note Environment variable expansion does not occur in files that are referenced via the -f argument to vcom, vlog, or vsim.

Removing Temp Files (VSOUT)

The VSOUT temp file is the communication mechanism between the simulator kernel and the Graphical User Interface. In normal circumstances the file is deleted when the simulator exits. If the tool crashes, however, the temp file must be deleted manually. Specifying the location of the temp file with TMPDIR (above) will help you locate and remove the file.

Simulator Control Variables

Initialization (INI) files contain control variables that specify reference library paths and compiler and simulator settings. The default initialization file is modelsim.ini and is located in your install directory. To set these variables, edit the initialization file directly with any text editor. The syntax for variables in the file is:
<variable> = <value>

Comments within the file are preceded with a semicolon ( ; ). The following sections contain information about the variables: Library Path Variables Verilog Compiler Control Variables VHDL Compiler Control Variables SystemC Compiler Control Variables Simulation Control Variables

Library Path Variables

You can find these variables under the heading [Library] in the modelsim.ini file.

ieee
This variable sets the path to the library containing IEEE and Synopsys arithmetic packages. Value Range: any valid path; may include environment variables Default: $MODEL_TECH/../ieee

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modelsim_lib
This variable sets the path to the library containing Model Technology VHDL utilities such as Signal Spy. Value Range: any valid path; may include environment variables Default: $MODEL_TECH/../modelsim_lib

std
This variable sets the path to the VHDL STD library. Value Range: any valid path; may include environment variables Default: $MODEL_TECH/../std

std_developerskit
This variable sets the path to the libraries for MGC standard developers kit. Value Range: any valid path; may include environment variables Default: $MODEL_TECH/../std_developerskit

synopsys
This variable sets the path to the accelerated arithmetic packages. Value Range: any valid path; may include environment variables Default: $MODEL_TECH/../synopsys

sv_std
This variable sets the path to the SystemVerilog STD library. Value Range: any valid path; may include environment variables Default: $MODEL_TECH/../sv_std

verilog
This variable sets the path to the library containing VHDL/Verilog type mappings. Value Range: any valid path; may include environment variables Default: $MODEL_TECH/../verilog

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vital2000
This variable sets the path to the VITAL 2000 library Value Range: any valid path; may include environment variables Default: $MODEL_TECH/../vital2000

others
This variable points to another modelsim.ini file whose library path variables will also be read; the pathname must include "modelsim.ini"; only one others variable can be specified in any modelsim.ini file. Value Range: any valid path; may include environment variables Default: none

Verilog Compiler Control Variables

You can find these variables under the heading [vlog] in the modelsim.ini file.

DisableOpt
This variable, when on, disables all optimizations enacted by the compiler; same as the -O0 argument to vlog. Value Range: 0, 1 Default: off (0)

GenerateLoopIterationMax
This variable specifies the maximum number of iterations permitted for a generate loop; restricting this permits the implementation to recognize infinite generate loops. Value Range: natural integer (>=0) Default: 100000

GenerateRecursionDepthMax
This variable specifies the maximum depth permitted for a recursive generate instantiation; restricting this permits the implementation to recognize infinite recursions. Value Range: natural integer (>=0) Default: 200

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Hazard
This variable turns on Verilog hazard checking (order-dependent accessing of global variables). Value Range: 0, 1 Default: off (0)

Incremental
This variable activates the incremental compilation of modules. Value Range: 0, 1 Default: off (0)

MultiFileCompilationUnit
Controls how Verilog files are compiled into compilation units. Valid arguments: 1 -- (0n) Compiles all files on command line into a single compilation unit. This behavior is called Multi File Compilation Unit (MFCU) mode; same as -mfcu argument to 0 -- (Off) Default value. Compiles each file in the compilation command line into separate compilation units. This behavior is called Single File Compilation Unit (SFCU) mode.

Refer to SystemVerilog Multi-File Compilation Issues for details on the implications of these settings. Note The default behavior in versions prior to 6.1 was opposite of the current default behavior.

NoDebug
This variable, when on, disables the inclusion of debugging info within design units. Value Range: 0, 1 Default: off (0)

Protect
This variable enables `protect directive processing. Refer to Compiler Directives for details. Value Range: 0, 1 Default: off (0)

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Quiet
This variable turns off "loading" messages. Value Range: 0, 1 Default: off (0)

Show_BadOptionWarning
This variable instructs the tool to generate a warning whenever an unknown plus argument is encountered. Value Range: 0, 1 Default: off (0)

Show_Lint
This variable instructs the tool to display lint warning messages. Value Range: 0, 1 Default: off (0)

Show_WarnCantDoCoverage
This variable instructs the tool to display warning messages when the simulator encounters constructs which code coverage cannot handle. Value Range: 0,1 Default: on (1)

Show_WarnMatchCadence
This variable instructs the tool to display warning messages about non-LRM compliance in order to match Cadence behavior. Value Range: 0, 1 Default: on (1)

Show_source
This variable instructs the tool to show any source line containing an error. Value Range: 0, 1 Default: off (0)

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vlog95compat
This variable instructs the tool to disable SystemVerilog and Verilog 2001 support, making the compiler compatible with IEEE Std 1364-1995. Value Range: 0, 1 Default: off (0)

VHDL Compiler Control Variables

You can find these variables under the heading [vcom].

BindAtCompile
This variable instructs the tool to perform VHDL default binding at compile time rather than load time. Refer to Default Binding for more information. Value Range: 0, 1 Default: off (0)

CheckSynthesis
This variable turns on limited synthesis rule compliance checking, which includes checking only signals used (read) by a process and understanding only combinational logic, not clocked logic. Value Range: 0, 1 Default: off (0)

DisableOpt
This variable disables all optimizations enacted by the compiler, similar to using the -O0 argument to vcom. Value Range: 0, 1 Default: off (0)

Explicit
This variable enables the resolving of ambiguous function overloading in favor of the "explicit" function declaration (not the one automatically created by the compiler for each type declaration). Value Range: 0, 1

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Default: on (1)

IgnoreVitalErrors
This variable instructs the tool to ignore VITAL compliance checking errors. Value Range: 0, 1 Default: off (0)

NoCaseStaticError
This variable changes case statement static errors to warnings. Value Range: 0, 1 Default: off (0)

NoDebug
This variable disables turns off inclusion of debugging info within design units. Value Range: 0, 1 Default: off (0)

NoIndexCheck
This variable disables run time index checks. Value Range: 0, 1 Default: off (0)

NoOthersStaticError
This variable disables errors caused by aggregates that are not locally static. Value Range: 0, 1 Default: off (0)

NoRangeCheck
This variable disables run time range checking. Value Range: 0, 1 Default: off (0)

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NoVital
This variable disables acceleration of the VITAL packages. Value Range: 0, 1 Default: off (0)

NoVitalCheck
This variable disables VITAL compliance checking. Value Range: 0, 1 Default: off (0)

Optimize_1164
This variable disables optimization for the IEEE std_logic_1164 package. Value Range: 0, 1 Default: on (1)

PedanticErrors
This variable overrides NoCaseStaticError and NoOthersStaticError Value Range: 0, 1 Default: off(0)

Quiet
This variable disables the loading messages. Value Range: 0, 1 Default: off (0)

RequireConfigForAllDefaultBinding
This variable instructs the compiler not to generate a default binding during compilation. Value Range: 0, 1 Default: off (0)

Show_Lint
This variable enables lint-style checking.
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Value Range: 0, 1 Default: off (0)

Show_source
This variable shows source line containing error. Value Range: 0, 1 Default: off (0)

Show_VitalChecksOpt
This variable enables VITAL optimization warnings. Value Range: 0, 1 Default: on (1)

Show_VitalChecksWarnings
This variable enables VITAL compliance-check warnings. Value Range: 0, 1 Default: on (1)

Show_WarnCantDoCoverage
This variable enables warnings when the simulator encounters constructs which code coverage cannot handle. Value Range: 0, 1 Default: on (1)

Show_Warning1
This variable enables unbound-component warnings. Value Range: 0, 1 Default: on (1)

Show_Warning2
This variable enables process-without-a-wait-statement warnings. Value Range: 0, 1

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Default: on (1)

Show_Warning3
This variable enables null-range warnings. Value Range: 0, 1 Default: on (1)

Show_Warning4
This variable enables no-space-in-time-literal warnings. Value Range: 0, 1 Default: on (1)

Show_Warning5
This variable enables multiple-drivers-on-unresolved-signal warnings. Value Range: 0, 1 Default: on (1)

Show_Warning9
This variable enables warnings about signal value dependency at elaboration. Value Range: 0, 1 Default: on (1)

Show_Warning10
This variable enables warnings about VHDL-1993 constructs in VHDL-1987 code. Value Range: 0, 1 Default: on (1)

Show_WarnLocallyStaticError
This variable enables warnings about locally static errors deferred until run time. Value Range: 0, 1 Default: on (1)

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VHDL93
This variable enables support for VHDL-1987, where 1 enables support for VHDL-1993 and 2 enables support for VHDL-2002. Value Range: 0, 1, 2 Default: 2

SystemC Compiler Control Variables

You can find these variables under the heading [sccom].

CppOptions
This variable adds any specified C++ compiler options to the sccom command line at the time of invocation. Value Range: any valid C+++ compiler options Default: none

CppPath
This variable should point directly to the location of the g++ executable, such as:
% CppPath /usr/bin/g++

This variable is not required when running SystemC designs. By default, you should install and use the built-in g++ compiler that comes with the tool. Value Range: C++ compiler path Default: none

DpiOutOfTheBlue
This variable enables DPI out of the blue calls from C functions (must not be declared as import tasks or functions). For more information, see Making Verilog Function Calls from nonDPI C Models. Value Range: 0, 1 Default: 0 - Support for out of the blue DPI calls is disabled.

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RetroChannelLimit
This variable controls the maximum number of retroactive recording channels allowed in the WLF file. Setting the value to 0 turns off retroactive recording. Setting the value too high can risk your performance, and the WLF file may not operate. Value Range: integer Default: 20

SccomLogfile
This variable creates a log file for sccom. Value Range: 0, 1 Default: off (0)

SccomVerbose
This variable enables verbose messages from sccom, refer to sccom -verbose for more information. Value Range: 0, 1 Default: off (0)

ScvPhaseRelationName
This variable changes the precise name used by SCV to specify phase transactions in the WLF file. See Overlapping Transactions and Specifying and Recording Phase Transactions for details. Value Range: any legal string is accepted, but legal C-language identifiers are recommended. Default: mti_phase

UseScv
This variable enables the use of SCV include files and library, refer to sccom -scv for more information. Value Range: 0, 1 Default: off (0)

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Simulation Control Variables

You can find these variables under the heading [vsim] in the modelsim.ini file.

AssertFile
This variable specifies an alternative file for storing VHDL assertion messages. Value Range: any valid filename Default: transcript

AssertionDebug
This variable specifies that SVA assertion passes are reported. Value Range: 0, 1 Default: off (0)

AssertionFormat
This variable defines the format of VHDL assertion messages. Value Range: Table A-2. AssertionFormat Variable: Accepted Values Variable %S %R %T %D %I %i %O %K %P %F %L %% Description severity level report message time of assertion delta instance or region pathname (if available) instance pathname with process process name kind of object path points to; returns Instance, Signal, Process, or Unknown instance or region path without leaf process file line number of assertion, or if from subprogram, line from which call is made print % character

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Default: "** %S: %R\n Time: %T Iteration: %D%I\n"

AssertionFormatBreak
This variable defines the format of messages for VHDL assertions that trigger a breakpoint. Value Range: Refer to Table A-2 Default: "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"

AssertionFormatError
This variable defines the format of messages for VHDL Error assertions. If undefined, AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used. Value Range: Refer to Table A-2 Default: "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"

AssertionFormatFail
This variable defines the format of messages for VHDL Fail assertions. If undefined, AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used Value Range: Refer to Table A-2 Default: "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"

AssertionFormatFatal
This variable defines the format of messages for VHDL Fatal assertions If undefined, AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used. Value Range: Refer to Table A-2 Default: "** %S: %R\n Time: %T Iteration: %D %K: %i File: %F\n"

AssertionFormatNote
This variable defines the format of messages for VHDL Note assertions If undefined, AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used

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Value Range: Refer to Table A-2 Default: "** %S: %R\n Time: %T Iteration: %D%I\n"

AssertionFormatWarning
This variable defines the format of messages for VHDL Warning assertions If undefined, AssertionFormat is used unless assertion causes a breakpoint in which case AssertionFormatBreak is used Value Range: Refer to Table A-2 Default: "** %S: %R\n Time: %T Iteration: %D%I\n"

BreakOnAssertion
This variable defines the severity of VHDL assertions that cause a simulation break. It also controls any messages in the source code that use assertion_failure_*. For example, since most runtime messages use some form of assertion_failure_*, any runtime error will cause the simulation to break if the user sets BreakOnAssertion to 2. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: 0 (note), 1 (warning), 2 (error), 3 (failure), 4 (fatal) Default: 3 (failure)

CheckPlusargs
This variable defines the simulators behavior when encountering unrecognized plusargs. Value Range: 0 (ignores), 1 (issues warning, simulates while ignoring), 2 (issues error, exits) Default: 0 (ignores)

CheckpointCompressMode
This variable specifies that checkpoint files are written in compressed format Value Range: 0, 1 Default: on (1)

CommandHistory
This variable specifies the name of a file in which to store the Main window command history.

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Value Range: any valid filename Default: commented out (;)

ConcurrentFileLimit
This variable controls the number of VHDL files open concurrently. This number should be less than the current limit setting for max file descriptors. Value Range: any positive integer or 0 (unlimited) Default: 40

CoverExcludeDefault
This variable excludes code coverage data collection from the default branch of case statements. Value Range: 0, 1 Default: 0

CoverGenerate
This variable enables code coverage inside the top level of generate blocks. Value Range: 0, 1 Default: 0

DatasetSeparator
This variable specifies the dataset separator for fully-rooted contexts, for example:
sim:/top

The argument to DatasetSeparator must not be the same character as PathSeparator Value Range: any character except those with special meaning, such as \, {, }, etc. Default: :

DefaultForceKind
This variable defines the kind of force used when not otherwise specified. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI.
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Value Range: freeze, drive, or deposit Default: drive, for resolved signals; freeze, for unresolved signals
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DefaultRadix
This variable specifies a numeric radix may be specified as a name or number. For example, you can specify binary as binary or 2 or octal as octal or 8. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: symbolic, binary, octal, decimal, unsigned, hexadecimal, ascii Default: symbolic

DefaultRestartOptions
This variable sets the default behavior for the restart command Value Range: one or more of: -force, -noassertions, -nobreakpoint, -nofcovers, -nolist, -nolog, -nowave Default: commented out (;)

DelayFileOpen
This variable instructs the tool to open VHDL87 files on first read or write, else open files when elaborated. Value Range: 0, 1 Default: off (0)

DumpportsCollapse
This variable collapses vectors (VCD id entries) in dumpports output. Value Range: 0, 1 Default: off (0)

GenerateFormat
This variable controls the format of a generate statement label. Do not enclose the argument in quotation marks. Value Range: Any non-quoted string containing at a minimum a %s followed by a %d Default: %s__%d

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GlobalSharedObjectsList
This variable instruct the tool to load the specified PLI/FLI shared objects with global symbol visibility. Value Range: comma separated list of filenames Default: commented out (;)

IgnoreError
This variable instructs the tool to ignore VHDL assertion errors. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: 0,1 Default: off (0)

IgnoreFailure
This variable instructs the tool to ignore VHDL assertion failures. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: 0,1 Default: off (0)

IgnoreNote
This variable instructs the tool to ignore VHDL assertion notes. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: 0,1 Default: off (0)

IgnoreWarning
This variable instructs the tool to ignore VHDL assertion warnings. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI.
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Default: off (0)

IterationLimit
This variable specifies a limit on simulation kernel iterations allowed without advancing time. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: positive integer Default: 5000

License
This variable controls the license file search. Value Range: one ore more of the following <license_option>, separated by spaces if using multiple entries. Refer also to the vsim <license_option>. Table A-3. License Variable: License Options license_option lnlonly mixedonly nomgc nolnl nomix nomti noqueue noslvhdl noslvlog noviewer plus vlog vhdl viewsim Description only use msimhdlsim and hdlsim exclude single language licenses exclude MGC licenses exclude language neutral licenses exclude msimhdlmix and hdlmix exclude MTI licenses do not wait in license queue if no licenses are available exclude qhsimvh and vsim exclude qhsimvl and vsimvlog disable viewer license checkout only use PLUS license only use VLOG license only use VHDL license accepts a simulation license rather than being queued for a viewer license

Default: search all licenses

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LockedMemory
For HP-UX 10.2 use only. This variable enables memory locking to speed up large designs (> 500mb memory footprint) Value Range: positive integer in units of MB. Default: disabled

MaxReportRhsCrossProducts
This variable specifies a limit on number of Cross (bin) products which are listed against a Cross when a XML or UCDB report is generated. The warning reports when any instance of unusually high number of Cross (bin) product and truncation of Cross (bin) product list for a Cross. Value Range: positive integer Default: 1000

NumericStdNoWarnings
This variable disables warnings generated within the accelerated numeric_std and numeric_bit packages. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: 0, 1 Default: off (0)

OnFinish
This variable controls the behavior of the tool when it encounters $finish or sc_stop() in the design code. Value Range: ask
o o

In batch mode, the simulation exits. In GUI mode, a dialog box pops up and asks for user confirmation on whether to quit the simulation.

stop Causes the simulation to stay loaded in memory. This can make some postsimulation tasks easier. exit The simulation exits without asking for any confirmation.

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Default: ask Exits in batch mode; prompts user in GUI mode.

PathSeparator
This variable specifies the character used for hierarchical boundaries of HDL modules. This variable does not affect file system paths. The argument to PathSeparator must not be the same character as DatasetSeparator. Value Range: any character except those with special meaning, such as \, {, }, etc. Default: /

PrintSimStats
This variable instructs the simulator to print the output of the simstats command upon exit. You can set this variable interactively with the -printsimstats argument to the vsim command. Value Range: 0, 1 Default: 0

Resolution
This variable specifies the simulator resolution. The argument must be less than or equal to the UserTimeUnit and must not contain a space between value and units, for example:
Resoultion = 10fs

You can override this value with the -t argument to vsim. You should set a smaller resolution if your delays get truncated. Value Range: fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100 Default: ns

RunLength
This variable specifies the default simulation length in units specified by the UserTimeUnit variable You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: positive integer Default: 100

ScTimeUnit
This variable sets the default time unit for SystemC simulations.
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Value Range: fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100 Default: 1 ns

ShowFunctions
This variable sets the format for Breakpoint and Fatal error messages. When set to 1 (the default value), messages will display the name of the function, task, subprogram, module, or architecture where the condition occurred, in addition to the file and line number. Set to 0 to revert messages to previous format. Value Range: 0, 1 Default: 1

SignalSpyPathSeparator
This variable specifies a unique path separator for the Signal Spy functions. The argument to SignalSpyPathSeparator must not be the same character as DatasetSeparator. Value Range: any character except those with special meaning, such as \, {, }, etc. Default: /

ShowUnassociatedScNameWarning
This variable instructs the tool to display unassociated SystemC name warnings. Value Range: 0, 1 Default: off (1)

ShowUndebuggableScTypeWarning
This variable instructs the tool to display undebuggable SystemC type warnings. Value Range: 0, 1 Default: on (1)

Startup
This variable specifies a simulation startup macro. Refer to the do command Value Range: = do <DO filename>; any valid macro (do) file Default: commented out (;)

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StdArithNoWarnings
This variable suppresses warnings generated within the accelerated Synopsys std_arith packages. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: 0, 1 Default: off (0)

ToggleMaxIntValues
This variable sets the maximum number of VHDL integer values to record with toggle coverage. Value Range: positive integer Default: 100

TranscriptFile
This variable specifies a file for saving command transcript. You can specify environment variables in the pathname. Value Range: any valid filename Default: transcript

UCDBFilename
This variable specifies the default unified coverage database file name that is written at the end of the simulation. All coverage statistics are saved to the .ucdb file. Value Range: any valid file name Default: vsim.ucdb

UnbufferedOutput
This variable controls VHDL and Verilog files open for write. Value Range: 0 (buffered), 1 (unbuffered) Default: 0

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UseCsupV2
Applies only to HP-UX 11.00 and when you compiled FLI/PLI/VPI C++ code with the -AA option for aCC. This variable instructs vsim to use /usr/lib/libCsup_v2.sl for shared object loading. Value Range: 0, 1 Default: off (0)

UserTimeUnit
This variable specifies scaling for the Wave window and the default time units to use for commands such as force and run. You should generally set this variable to default, in which case it takes the value of the Resolution variable. Value Range: fs, ps, ns, us, ms, sec, or default Default: default

Veriuser
This variable specifies a list of dynamically loadable objects for Verilog PLI/VPI applications. Value Range: one or more valid shared object names Default: commented out (;)

WarnConstantChange
This variable controls whether a warning is issued when the change command changes the value of a VHDL constant or generic. Value Range: 0, 1 Default: on (1)

WaveSignalNameWidth
This variable controls the number of visible hierarchical regions of a signal name shown in the Wave Window. Value Range: 0 (display full name), positive integer (display corresponding level of hierarchy) Default: 0

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WLFCacheSize
This variable sets the number of megabytes for the WLF reader cache; WLF reader caching caches blocks of the WLF file to reduce redundant file I/O Value Range: positive integer Default: 0

WLFCollapseMode
This variable controls when the WLF file records values. Value Range: 0 (every change of logged object), 1 (end of each delta step), 2 (end of simulator time step) Default: 1

WLFCompress
This variable enables WLF file compression. Value Range: 0, 1 Default: 1 (on)

WLFDeleteOnQuit
This variable specifies whether a WLF file should be deleted when the simulation ends. Value Range: 0, 1 Default: 0 (do not delete)

WLFFilename
This variable specifies the default WLF file name. Value Range: 0, 1 Default: vsim.wlf

WLFOptimize
This variable specifies whether the viewing of waveforms is optimized. Value Range: 0, 1 Default: 1 (on)

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WLFSaveAllRegions
This variable specifies the regions to save in the WLF file. Value Range: 0 (only regions containing logged signals), 1 (all design hierarchy) Default: 0

WLFSizeLimit
This variable limits the WLF file by size (as closely as possible) to the specified number of megabytes; if both size and time limits are specified the most restrictive is used. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: any positive integer in units of MB or 0 (unlimited) Default: 0 (unlimited)

WLFTimeLimit
This variable limits the WLF file by time (as closely as possible) to the specified amount of time. If both time and size limits are specified the most restrictive is used. You can set this variable interactively in the GUI; refer to Setting Simulator Control Variables With The GUI. Value Range: any positive integer or 0 (unlimited) Default: 0 (unlimited)

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Setting Simulator Control Variables With The GUI

Changes made in the Runtime Options dialog are written to the active modelsim.ini file, if it is writable, and affect the current session as well as all future sessions. If the file is read-only, the changes affect only the current session. The Runtime Options dialog is accessible by selecting Simulate > Runtime Options in the Main window. The dialog contains three tabs - Defaults, Assertions, and WLF Files. The Defaults tab includes these options: Figure A-1. Runtime Options Dialog: Defaults Tab

Default Radix Sets the default radix for the current simulation run. You can also use the radix command to set the same temporary default. The chosen radix is used for all commands (force, examine, change are examples) and for displayed values in the Objects, Locals, Dataflow, List, and Wave windows. The corresponding modelsim.ini variable is DefaultRadix. Suppress Warnings
o

Selecting From Synopsys Packages suppresses warnings generated within the accelerated Synopsys std_arith packages. The corresponding modelsim.ini variable is StdArithNoWarnings. Selecting From IEEE Numeric Std Packages suppresses warnings generated within the accelerated numeric_std and numeric_bit packages. The corresponding modelsim.ini variable is NumericStdNoWarnings.

Default Run Sets the default run length for the current simulation. The corresponding modelsim.ini variable is RunLength.

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Iteration Limit Sets a limit on the number of deltas within the same simulation time unit to prevent infinite looping. The corresponding modelsim.ini variable is IterationLimit. Default Force Type Selects the default force type for the current simulation. The corresponding modelsim.ini variable is DefaultForceKind.

The Assertions tab includes these options: Figure A-2. Runtime Options Dialog Box: Assertions Tab

No Message Display For -VHDL Selects the VHDL assertion severity for which messages will not be displayed (even if break on assertion is set for that severity). Multiple selections are possible. The corresponding modelsim.ini variables are IgnoreFailure, IgnoreError, IgnoreWarning, and IgnoreNote.

The WLF Files tab includes these options:

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Figure A-3. Runtime Options Dialog Box, WLF Files Tab

WLF File Size Limit Limits the WLF file by size (as closely as possible) to the specified number of megabytes. If both size and time limits are specified, the most restrictive is used. Setting it to 0 results in no limit. The corresponding modelsim.ini variable is WLFSizeLimit. WLF File Time Limit Limits the WLF file by size (as closely as possible) to the specified amount of time. If both time and size limits are specified, the most restrictive is used. Setting it to 0 results in no limit. The corresponding modelsim.ini variable is WLFTimeLimit. WLF Attributes Specifies whether to compress WLF files and whether to delete the WLF file when the simulation ends. You would typically only disable compression for troubleshooting purposes. The corresponding modelsim.ini variables are WLFCompress for compression and WLFDeleteOnQuit for WLF file deletion. Design Hierarchy Specifies whether to save all design hierarchy in the WLF file or only regions containing logged signals. The corresponding modelsim.ini variable is WLFSaveAllRegions.

Message System Variables

The message system variables (located under the [msg_system] heading) help you identify and troubleshoot problems while using the application. See also Message System.

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error
This variable changes the severity of the listed message numbers to "error". Refer to Changing Message Severity Level for more information. Value Range: list of message numbers Default: none

fatal
This variable changes the severity of the listed message numbers to "fatal". Refer to Changing Message Severity Level for more information. Value Range: list of message numbers Default: none

note
This variable changes the severity of the listed message numbers to "note". Refer to Changing Message Severity Level for more information Value Range: list of message numbers Default: none

suppress
This variable suppresses the listed message numbers. Refer to Changing Message Severity Level for more information Value Range: list of message numbers Default: none

warning
This variable changes the severity of the listed message numbers to "warning". Refer to Changing Message Severity Level for more information Value Range: list of message numbers Default: none

msgmode
This variable controls where the simulator outputs elaboration and runtime messages. Refer to the section Message Viewer for more information.

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Value Range: tran (transcript only), wlf (wlf file only), both Default: both

Commonly Used INI Variables

Several of the more commonly used modelsim.ini variables are further explained below.

Common Environment Variables

You can use environment variables in your initialization files. Use a dollar sign ($) before the environment variable name. For example:
[Library] work = $HOME/work_lib test_lib = ./$TESTNUM/work ... [vsim] IgnoreNote = $IGNORE_ASSERTS IgnoreWarning = $IGNORE_ASSERTS IgnoreError = 0 IgnoreFailure = 0

There is one environment variable, MODEL_TECH, that you cannot and should not set. MODEL_TECH is a special variable set by Model Technology software. Its value is the name of the directory from which the VCOM or VLOG compilers or VSIM simulator was invoked. MODEL_TECH is used by the other Model Technology tools to find the libraries.

Hierarchical Library Mapping

By adding an "others" clause to your modelsim.ini file, you can have a hierarchy of library mappings. If the ModelSim tools dont find a mapping in the modelsim.ini file, then they will search only the library section of the initialization file specified by the "others" clause. For example:
[Library] asic_lib = /cae/asic_lib work = my_work others = /install_dir/modeltech/modelsim.ini

Since the file referred to by the "others" clause may itself contain an "others" clause, you can use this feature to chain a set of hierarchical INI files for library mappings.

Creating a Transcript File

A feature in the system initialization file allows you to keep a record of everything that occurs in the transcript: error messages, assertions, commands, command outputs, etc. To do this, set

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the value for the TranscriptFile line in the modelsim.ini file to the name of the file in which you would like to record the ModelSim history.
; Save the command window contents to this file TranscriptFile = trnscrpt

You can disable the creation of the transcript file by using the following ModelSim command immediately after ModelSim starts:
transcript file ""

Using a Startup File

The system initialization file allows you to specify a command or a do file that is to be executed after the design is loaded. For example:
; VSIM Startup command Startup = do mystartup.do

The line shown above instructs ModelSim to execute the commands in the macro file named mystartup.do.
; VSIM Startup command Startup = run -all

The line shown above instructs VSIM to run until there are no events scheduled. See the do command for additional information on creating do files.

Turning Off Assertion Messages

You can turn off assertion messages from your VHDL code by setting a switch in the modelsim.ini file. This option was added because some utility packages print a huge number of warnings.
[vsim] IgnoreNote = 1 IgnoreWarning = 1 IgnoreError = 1 IgnoreFailure = 1

Turning off Warnings from Arithmetic Packages

You can disable warnings from the Synopsys and numeric standard packages by adding the following lines to the [vsim] section of the modelsim.ini file.
[vsim] NumericStdNoWarnings = 1 StdArithNoWarnings = 1

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Force Command Defaults

The force command has -freeze, -drive, and -deposit options. When none of these is specified, then -freeze is assumed for unresolved signals and -drive is assumed for resolved signals. But if you prefer -freeze as the default for both resolved and unresolved signals, you can change the defaults in the modelsim.ini file.
[vsim] ; Default Force Kind ; The choices are freeze, drive, or deposit DefaultForceKind = freeze

Restart Command Defaults

The restart command has -force, -nobreakpoint, -nofcovers, -nolist, -nolog, and -nowave options. You can set any of these as defaults by entering the following line in the modelsim.ini file:
DefaultRestartOptions = <options>

where <options> can be one or more of -force, -nobreakpoint, -nofcovers, -nolist, -nolog, and nowave. Example:
DefaultRestartOptions = -nolog -force

VHDL Standard
You can specify which version of the 1076 Std ModelSim follows by default using the VHDL93 variable:
[vcom] ; VHDL93 variable selects language version as the default. ; Default is VHDL-2002. ; Value of 0 or 1987 for VHDL-1987. ; Value of 1 or 1993 for VHDL-1993. ; Default or value of 2 or 2002 for VHDL-2002. VHDL93 = 2002

Opening VHDL Files

You can delay the opening of VHDL files with an entry in the INI file if you wish. Normally VHDL files are opened when the file declaration is elaborated. If the DelayFileOpen option is enabled, then the file is not opened until the first read or write to that file.
[vsim] DelayFileOpen = 1

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Simulator Variables Variable Precedence

Variable Precedence
Note that some variables can be set in a .modelsim file (Registry in Windows) or a .ini file. A variable set in the .modelsim file takes precedence over the same variable set in a .ini file. For example, assume you have the following line in your modelsim.ini file:
TranscriptFile = transcript

And assume you have the following line in your .modelsim file:
set PrefMain(file) {}

In this case the setting in the .modelsim file overrides that in the modelsim.ini file, and a transcript file will not be produced.

Simulator State Variables

Unlike other variables that must be explicitly set, simulator state variables return a value relative to the current simulation. Simulator state variables can be useful in commands, especially when used within ModelSim DO files (macros). The variables are referenced in commands by prefixing the name with a dollar sign ($).

argc
This variable returns the total number of parameters passed to the current macro.

architecture
This variable returns the name of the top-level architecture currently being simulated; for a configuration or Verilog module, this variable returns an empty string.

configuration
This variable returns the name of the top-level configuration currently being simulated; returns an empty string if no configuration.

delta
This variable returns the number of the current simulator iteration.

entity
This variable returns the name of the top-level VHDL entity or Verilog module currently being simulated.

library
This variable returns the library name for the current region.

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MacroNestingLevel
This variable returns the current depth of macro call nesting.

n
This variable represents a macro parameter, where n can be an integer in the range 1-9.

Now
This variable always returns the current simulation time with time units (e.g., 110,000 ns) Note: will return a comma between thousands.

now
This variable when time resolution is a unary unit (i.e., 1ns, 1ps, 1fs): returns the current simulation time without time units (e.g., 100000) when time resolution is a multiple of the unary unit (i.e., 10ns, 100ps, 10fs): returns the current simulation time with time units (e.g. 110000 ns) Note: will not return comma between thousands.

resolution
This variable returns the current simulation time resolution.

Referencing Simulator State Variables

Variable values may be referenced in simulator commands by preceding the variable name with a dollar sign ($). For example, to use the now and resolution variables in an echo command type:
echo "The time is $now $resolution."

Depending on the current simulator state, this command could result in:
The time is 12390 ps 10ps.

If you do not want the dollar sign to denote a simulator variable, precede it with a "\". For example, \$now will not be interpreted as the current simulator time.

Special Considerations for the now Variable

For the when command, special processing is performed on comparisons involving the now variable. If you specify "when {$now=100}...", the simulator will stop at time 100 regardless of the multiplier applied to the time resolution. You must use 64-bit time operators if the time value of now will exceed 2147483647 (the limit of 32-bit numbers). For example:

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Simulator Variables Simulator State Variables if { [gtTime $now 2us] } { . . .

See Simulator Tcl Time Commands for details on 64-bit time operators.

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Appendix B Location Mapping

Pathnames to source files are recorded in libraries by storing the working directory from which the compile is invoked and the pathname to the file as specified in the invocation of the compiler. The pathname may be either a complete pathname or a relative pathname.

Referencing Source Files with Location Maps

ModelSim tools that reference source files from the library locate a source file as follows: If the pathname stored in the library is complete, then this is the path used to reference the file. If the pathname is relative, then the tool looks for the file relative to the current working directory. If this file does not exist, then the path relative to the working directory stored in the library is used.

This method of referencing source files generally works fine if the libraries are created and used on a single system. However, when multiple systems access a library across a network, the physical pathnames are not always the same and the source file reference rules do not always work.

Using Location Mapping

Location maps are used to replace prefixes of physical pathnames in the library with environment variables. The location map defines a mapping between physical pathname prefixes and environment variables. ModelSim tools open the location map file on invocation if the MGC_LOCATION_MAP environment variable is set. If MGC_LOCATION_MAP is not set, ModelSim will look for a file named "mgc_location_map" in the following locations, in order: the current directory your home directory the directory containing the ModelSim binaries the ModelSim installation directory

Use these two steps to map your files:

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1. Set the environment variable MGC_LOCATION_MAP to the path to your location map file. 2. Specify the mappings from physical pathnames to logical pathnames:
$SRC /home/vhdl/src /usr/vhdl/src $IEEE /usr/modeltech/ieee

Pathname Syntax
The logical pathnames must begin with $ and the physical pathnames must begin with /. The logical pathname is followed by one or more equivalent physical pathnames. Physical pathnames are equivalent if they refer to the same physical directory (they just have different pathnames on different systems).

How Location Mapping Works

When a pathname is stored, an attempt is made to map the physical pathname to a path relative to a logical pathname. This is done by searching the location map file for the first physical pathname that is a prefix to the pathname in question. The logical pathname is then substituted for the prefix. For example, "/usr/vhdl/src/test.vhd" is mapped to "$SRC/test.vhd". If a mapping can be made to a logical pathname, then this is the pathname that is saved. The path to a source file entry for a design unit in a library is a good example of a typical mapping. For mapping from a logical pathname back to the physical pathname, ModelSim expects an environment variable to be set for each logical pathname (with the same name). ModelSim reads the location map file when a tool is invoked. If the environment variables corresponding to logical pathnames have not been set in your shell, ModelSim sets the variables to the first physical pathname following the logical pathname in the location map. For example, if you don't set the SRC environment variable, ModelSim will automatically set it to "/home/vhdl/src".

Mapping with TCL Variables

Two Tcl variables may also be used to specify alternative source-file paths; SourceDir and SourceMap. You would define these variables in a modelsim.tcl file. See the The modelsim.tcl File for details.

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Appendix C Error and Warning Messages

Message System
The ModelSim message system helps you identify and troubleshoot problems while using the application. The messages display in a standard format in the Transcript pane. Accordingly, you can also access them from a saved transcript file (see Saving the Transcript File for more details).

Message Format
The format for the messages is:
** <SEVERITY LEVEL>: ([<Tool>[-<Group>]]-<MsgNum>) <Message>

SEVERITY LEVEL may be one of the following: Table C-1. Severity Level Types severity level Note Warning Error Fatal INTERNAL ERROR meaning This is an informational message. There may be a problem that will affect the accuracy of your results. The tool cannot complete the operation. The tool cannot complete execution. This is an unexpected error that should be reported to your support representative.

Tool indicates which ModelSim tool was being executed when the message was generated. For example tool could be vcom, vdel, vsim, etc. Group indicates the topic to which the problem is related. For example group could be FLI, PLI, VCD, etc.

Example
# ** Error: (vsim-PLI-3071) ./src/19/testfile(77): $fdumplimit : Too few arguments.

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Error and Warning Messages Suppressing Warning Messages

Getting More Information

Each message is identified by a unique MsgNum id. You can access additional information about a message using the unique id and the verror command. For example:
% verror 3071 Message # 3071: Not enough arguments are being passed to the specified system task or function.

Changing Message Severity Level

You can suppress or change the severity of notes, warnings, and errors that come from vcom, vlog, and vsim. You cannot change the severity of or suppress Fatal or Internal messages. There are two ways to modify the severity of or suppress notes, warnings, and errors: Use the -error, -fatal, -note, -suppress, and -warning arguments to sccom, vcom, vlog, or vsim. See the command descriptions in the Reference Manual for details on those arguments. Set a permanent default in the [msg_system] section of the modelsim.ini file. See Simulator Control Variables for more information.

Suppressing Warning Messages

You can suppress some warning messages. For example, you may receive warning messages about unbound components about which you are not concerned.

Suppressing VCOM Warning Messages

Use the -nowarn <number> argument to vcom to suppress a specific warning message. For example:
vcom -nowarn 1

suppresses unbound component warning messages. Alternatively, warnings may be disabled for all compiles via the modelsim.ini file (see Verilog Compiler Control Variables). The warning message numbers are:

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Error and Warning Messages Exit Codes 1 = unbound component 2 = process without a wait statement 3 = null range 4 = no space in time literal 5 = multiple drivers on unresolved signal 6 = compliance checks 7 = optimization messages 8 = lint checks 9 = signal value dependency at elaboration 10 = VHDL93 constructs in VHDL87 code 14 = locally static error deferred until simulation run

These numbers are category-of-warning message numbers. They are unrelated to vcom arguments that are specified by numbers, such as vcom -87 which disables support for VHDL-1993 and 2002.

Suppressing VLOG Warning Messages

Use the +nowarn<CODE> argument to vlog to suppress a specific warning message. Warnings that can be disabled include the <CODE> name in square brackets in the warning message. For example:
vlog +nowarnDECAY

suppresses decay warning messages.

Suppressing VSIM Warning Messages

Use the +nowarn<CODE> argument to vsim to suppress a specific warning message. Warnings that can be disabled include the <CODE> name in square brackets in the warning message. For example:
vsim +nowarnTFMPC

suppresses warning messages about too few port connections.

Exit Codes
The table below describes exit codes used by ModelSim tools. Table C-2. Exit Codes Exit code 0 1 2 3 Description Normal (non-error) return Incorrect invocation of tool Previous errors prevent continuing Cannot create a system process (execv, fork, spawn, etc.)

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Table C-2. Exit Codes Exit code 4 5 6 7 8 9 10 11 12 13 14 15 16 19 22 23 42 43 44 45 90 99 100 101 102 111 202 204 Description Licensing problem Cannot create/open/find/read/write a design library Cannot create/open/find/read/write a design unit Cannot open/read/write/dup a file (open, lseek, write, mmap, munmap, fopen, fdopen, fread, dup2, etc.) File is corrupted or incorrect type, version, or format of file Memory allocation error General language semantics error General language syntax error Problem during load or elaboration Problem during restore Problem during refresh Communication problem (Cannot create/read/write/close pipe/socket) Version incompatibility License manager not found/unreadable/unexecutable (vlm/mgvlm) SystemC link error SystemC DPI internal error Lost license License read/write failure Modeltech daemon license checkout failure #44 Modeltech daemon license checkout failure #45 Assertion failure (SEVERITY_QUIT) Unexpected error in tool GUI Tcl initialization failure GUI Tk initialization failure GUI IncrTk initialization failure X11 display error Interrupt (SIGINT) Illegal instruction (SIGILL)

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Table C-2. Exit Codes Exit code 205 206 208 210 211 213 214 215 216 217 218 230 231 Description Trace trap (SIGTRAP) Abort (SIGABRT) Floating point exception (SIGFPE) Bus error (SIGBUS) Segmentation violation (SIGSEGV) Write on a pipe with no reader (SIGPIPE) Alarm clock (SIGALRM) Software termination signal from kill (SIGTERM) User-defined signal 1 (SIGUSR1) User-defined signal 2 (SIGUSR2) Child status change (SIGCHLD) Exceeded CPU limit (SIGXCPU) Exceeded file size limit (SIGXFSZ)

Miscellaneous Messages
This section describes miscellaneous messages which may be associated with ModelSim.

Compilation of DPI Export TFs Error

# ** Fatal: (vsim-3740) Can't locate a C compiler for compilation of DPI export tasks/functions.

Description ModelSim was unable to locate a C compiler to compile the DPI exported tasks or functions in your design. Suggested Action Make sure that a C compiler is visible from where you are running the simulation.

Empty port name warning

# ** WARNING: [8] <path/file_name>: empty port name in port list.

Description ModelSim reports these warnings if you use the -lint argument to vlog. It reports the warning for any NULL module ports. Suggested action If you wish to ignore this warning, do not use the -lint argument.

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Lock message
waiting for lock by user@user. Lockfile is <library_path>/_lock

Description The _lock file is created in a library when you begin a compilation into that library, and it is removed when the compilation completes. This prevents simultaneous updates to the library. If a previous compile did not terminate properly, ModelSim may fail to remove the _lock file. Suggested action Manually remove the _lock file after making sure that no one else is actually using that library.

Metavalue detected warning

Warning: NUMERIC_STD.">": metavalue detected, returning FALSE

Description This warning is an assertion being issued by the IEEE numeric_std package. It indicates that there is an 'X' in the comparison. Suggested action The message does not indicate which comparison is reporting the problem since the assertion is coming from a standard package. To track the problem, note the time the warning occurs, restart the simulation, and run to one time unit before the noted time. At this point, start stepping the simulator until the warning appears. The location of the blue arrow in a Source window will be pointing at the line following the line with the comparison. These messages can be turned off by setting the NumericStdNoWarnings variable to 1 from the command line or in the modelsim.ini file.

Sensitivity list warning

signal is read by the process but is not in the sensitivity list

Description ModelSim outputs this message when you use the -check_synthesis argument to vcom. It reports the warning for any signal that is read by the process but is not in the sensitivity list. Suggested action There are cases where you may purposely omit signals from the sensitivity list even though they are read by the process. For example, in a strictly sequential process, you may prefer to include only the clock and reset in the sensitivity list because it would be a design error if any other signal triggered the process. In such cases, your only option is to not use the -check_synthesis argument.

Tcl Initialization error 2

Tcl_Init Error 2 : Can't find a usable Init.tcl in the following directories : ./../tcl/tcl8.3 .

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Error and Warning Messages Miscellaneous Messages

Description This message typically occurs when the base file was not included in a Unix installation. When you install ModelSim, you need to download and install 3 files from the ftp site. These files are:
modeltech-base.tar.gz modeltech-docs.tar.gz modeltech-<platform>.exe.gz

If you install only the <platform> file, you will not get the Tcl files that are located in the base file. This message could also occur if the file or directory was deleted or corrupted. Suggested action Reinstall ModelSim with all three files.

Too few port connections

# ** Warning (vsim-3017): foo.v(1422): [TFMPC] - Too few port connections. Expected 2, found 1. # Region: /foo/tb

Description This warning occurs when an instantiation has fewer port connections than the corresponding module definition. The warning doesnt necessarily mean anything is wrong; it is legal in Verilog to have an instantiation that doesnt connect all of the pins. However, someone that expects all pins to be connected would like to see such a warning. Here are some examples of legal instantiations that will and will not cause the warning message. Module definition:
module foo (a, b, c, d);

Instantiation that does not connect all pins but will not produce the warning:
foo inst1(e, f, g, ); // positional association foo inst1(.a(e), .b(f), .c(g), .d()); // named association

Instantiation that does not connect all pins but will produce the warning:
foo inst1(e, f, g); // positional association foo inst1(.a(e), .b(f), .c(g)); // named association

Any instantiation above will leave pin d unconnected but the first example has a placeholder for the connection. Heres another example:
foo inst1(e, , g, h); foo inst1(.a(e), .b(), .c(g), .d(h));

Suggested actions

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Error and Warning Messages sccom Error Messages o

Check that there is not an extra comma at the end of the port list. (e.g., model(a,b,) ). The extra comma is legal Verilog and implies that there is a third port connection that is unnamed. If you are purposefully leaving pins unconnected, you can disable these messages using the +nowarnTFMPC argument to vsim.

VSIM license lost

Console output: Signal 0 caught... Closing vsim vlm child. vsim is exiting with code 4 FATAL ERROR in license manager transcript/vsim output: # ** Error: VSIM license lost; # Time: 5027 ns Iteration: # ** Fatal: Unable to kill and # Time: 5027 ns Iteration:

attempting to re-establish. 2 restart license process. 2

Description ModelSim queries the license server for a license at regular intervals. Usually these "License Lost" error messages indicate that network traffic is high, and communication with the license server times out. Suggested action Anything you can do to improve network communication with the license server will probably solve or decrease the frequency of this problem.

Failed to find libswift entry

** Error: Failed to find LMC Smartmodel libswift entry in project file. # Fatal: Foreign module requested halt

Description ModelSim could not locate the libswift entry and therefore could not link to the Logic Modeling library. Suggested action Uncomment the appropriate libswift entry in the [lmc] section of the modelsim.ini or project .mpf file. See VHDL SmartModel Interface for more information.

sccom Error Messages

This section describes sccom error messages which may be associated with ModelSim.

Failed to load sc lib error: undefined symbol

# ** Error: (vsim-3197) Load of "/home/cmg/newport2_systemc/chip/vhdl/work/systemc.so" failed:ld.so.1: /home/icds_nut/modelsim/5.8a/sunos5/vsimk: fatal: relocation error: file /home/cmg/newport2_systemc/chip/vhdl/work/systemc.so:

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Error and Warning Messages sccom Error Messages symbol_Z28host_respond_to_vhdl_requestPm: referenced symbol not found. # ** Error: (vsim-3676) Could not load shared library /home/cmg/newport2_systemc/chip/vhdl/work/systemc.so for SystemC module 'host_xtor'.

Description The causes for such an error could be:

o o o

missing symbol definition bad link order specified in sccom -link multiply defined symbols (see Multiple Symbol Definitions)

1. Suggested action
o

If the undefined symbol is a C function in your code or a library you are linking with, be sure that you declared it as an extern "C" function:
extern "C" void myFunc();

The order in which you place the -link option within the sccom -link command is critical. Make sure you have used it appropriately. See sccom for syntax and usage information. See Misplaced -link Option for further explanation of error and correction.

Multiply defined symbols

work/sc/gensrc/test_ringbuf.o: In function `test_ringbuf::clock_generator(void)': work/sc/gensrc/test_ringbuf.o(.text+0x4): multiple definition of `test_ringbuf::clock_generator(void)' work/sc/test_ringbuf.o(.text+0x4): first defined here

Meaning The most common type of error found during sccom -link operation is the multiple symbol definition error. This typically arises when the same global symbol is present in more than one .o file. Several causes are likely:
o

A common cause of multiple symbol definitions involves incorrect definition of symbols in header files. If you have an out-of-line function (one that isnt preceded by the "inline" keyword) or a variable defined (i.e., not just referenced or prototyped, but truly defined) in a .h file, you can't include that .h file in more than one .cpp file. Another cause of errors is due to ModelSims name association feature. The name association feature automatically generates .cpp files in the work library. These files "include" your header files. Thus, while it might appear as though you have included your header file in only one .cpp file, from the linkers point of view, it is included in multiple .cpp files.

Suggested action Make sure you dont have any out-of-line functions. Use the "inline" keyword. See Multiple Symbol Definitions.

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Enforcing Strict 1076 Compliance

The optional -pedanticerrors argument to vcom enforces strict compliance to the IEEE 1076 LRM in the cases listed below. The default behavior for these cases is to issue an insuppressible warning message. If you compile with -pedanticerrors, the warnings change to an error, unless otherwise noted. Descriptions in quotes are actual warning/error messages emitted by vcom. As noted, in some cases you can suppress the warning using -nowarn [level]. Type conversion between array types, where the element subtypes of the arrays do not have identical constraints. "Extended identifier terminates at newline character (0xa)." "Extended identifier contains non-graphic character 0x%x." "Extended identifier \"%s\" contains no graphic characters." "Extended identifier \"%s\" did not terminate with backslash character." "An abstract literal and an identifier must have a separator between them." This is for forming physical literals, which comprise an optional numeric literal, followed by a separator, followed by an identifier (the unit name). Warning is level 4, which means "-nowarn 4" will suppress it. In VHDL 1993 or 2002, a subprogram parameter was declared using VHDL 1987 syntax (which means that it was a class VARIABLE parameter of a file type, which is the only way to do it in VHDL 1987 and is illegal in later VHDLs). Warning is level 10. "Shared variables must be of a protected type." Applies to VHDL 2002 only. Expressions evaluated during elaboration cannot depend on signal values. Warning is level 9. "Non-standard use of output port '%s' in PSL expression." Warning is level 11. "Non-standard use of linkage port '%s' in PSL expression." Warning is level 11. Type mark of type conversion expression must be a named type or subtype, it can't have a constraint on it. When the actual in a PORT MAP association is an expression, it must be a (globally) static expression. The port must also be of mode IN. The expression in the CASE and selected signal assignment statements must follow the rules given in 8.8 of the LRM. In certain cases we can relax these rules, but -pedanticerrors forces strict compliance. A CASE choice expression must be a locally static expression. We allow it to be only globally static, but -pedanticerrors will check that it is locally static. Same rule for selected signal assignment statement choices. Warning level is 8.

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When making a default binding for a component instantiation, ModelSim's non-standard search rules found a matching entity. VHDL 2002 LRM Section 5.2.2 spells out the standard search rules. Warning level is 1. Both FOR GENERATE and IF GENERATE expressions must be globally static. We allow non-static expressions unless -pedanticerrors is present. When the actual part of an association element is in the form of a conversion function call [or a type conversion], and the formal is of an unconstrained array type, the return type of the conversion function [type mark of the type conversion] must be of a constrained array subtype. We relax this (with a warning) unless -pedanticerrors is present when it becomes an error. OTHERS choice in a record aggregate must refer to at least one record element. In an array aggregate of an array type whose element subtype is itself an array, all expressions in the array aggregate must have the same index constraint, which is the element's index constraint. No warning is issued; the presence of -pedanticerrors will produce an error. Non-static choice in an array aggregate must be the only choice in the only element association of the aggregate. The range constraint of a scalar subtype indication must have bounds both of the same type as the type mark of the subtype indication. The index constraint of an array subtype indication must have index ranges each of whose both bounds must be of the same type as the corresponding index subtype. When compiling VHDL 1987, various VHDL 1993 and 2002 syntax is allowed. Use -pedanticerrors to force strict compliance. Warnings are all level 10.

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Appendix D Verilog PLI/VPI/DPI

This appendix describes the ModelSim implementation of the Verilog PLI (Programming Language Interface), VPI (Verilog Procedural Interface) and SystemVerilog DPI (Direct Programming Interface). These three interfaces provide a mechanism for defining tasks and functions that communicate with the simulator through a C procedural interface. There are many third party applications available that interface to Verilog simulators through the PLI (see Third Party PLI Applications). In addition, you may write your own PLI/VPI/DPI applications.

Implementation Information
ModelSim Verilog implements the PLI as defined in the IEEE Std 1364-2001, with the exception of the acc_handle_datapath() routine. We did not implement the acc_handle_datapath() routine because the information it returns is more appropriate for a static timing analysis tool. The VPI is partially implemented as defined in the IEEE Std 1364-2005. The list of currently supported functionality can be found in the following file:
<install_dir>/modeltech/docs/technotes/Verilog_VPI.note

ModelSim SystemVerilog implements DPI as defined in IEEE Std P1800-2005. The IEEE Std 1364 is the reference that defines the usage of the PLI/VPI routines, and the IEEE Std P1800-2005 Language Reference Manual (LRM) defines the usage of DPI routines. This manual describes only the details of using the PLI/VPI/DPI with ModelSim Verilog and SystemVerilog.

g++ Compiler Support for use with PLI/VPI/DPI

We strongly encourage that unless you have a reason to do otherwise, you should use the builtin g++ compiler that is shipped with the ModelSim compiler to compile your C++ code. This is the version that has been tested and is supported for any given release.

Specifying Your Own g++ Compiler

If you must use a different g++ compiler, other than that shipped with ModelSim, you need to set a variable in your modelsim.ini file, as follows:
CppPath = /usr/bin/g++

to point to the desired g++ version.

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Registering PLI Applications

Each PLI application must register its system tasks and functions with the simulator, providing the name of each system task and function and the associated callback routines. Since many PLI applications already interface to Verilog-XL, ModelSim Verilog PLI applications make use of the same mechanism to register information about each system task and function in an array of s_tfcell structures. This structure is declared in the veriuser.h include file as follows:
typedef int (*p_tffn)(); typedef struct t_tfcell { short type;/* USERTASK, USERFUNCTION, or USERREALFUNCTION */ short data;/* passed as data argument of callback function */ p_tffn checktf; /* argument checking callback function */ p_tffn sizetf; /* function return size callback function */ p_tffn calltf; /* task or function call callback function */ p_tffn misctf; /* miscellaneous reason callback function */ char *tfname;/* name of system task or function */ /* The following fields are ignored by ModelSim Verilog */ int forwref; char *tfveritool; char *tferrmessage; int hash; struct t_tfcell *left_p; struct t_tfcell *right_p; char *namecell_p; int warning_printed; } s_tfcell, *p_tfcell;

The various callback functions (checktf, sizetf, calltf, and misctf) are described in detail in the IEEE Std 1364. The simulator calls these functions for various reasons. All callback functions are optional, but most applications contain at least the calltf function, which is called when the system task or function is executed in the Verilog code. The first argument to the callback functions is the value supplied in the data field (many PLI applications don't use this field). The type field defines the entry as either a system task (USERTASK) or a system function that returns either a register (USERFUNCTION) or a real (USERREALFUNCTION). The tfname field is the system task or function name (it must begin with $). The remaining fields are not used by ModelSim Verilog. On loading of a PLI application, the simulator first looks for an init_usertfs function, and then a veriusertfs array. If init_usertfs is found, the simulator calls that function so that it can call mti_RegisterUserTF() for each system task or function defined. The mti_RegisterUserTF() function is declared in veriuser.h as follows:
void mti_RegisterUserTF(p_tfcell usertf);

The storage for each usertf entry passed to the simulator must persist throughout the simulation because the simulator de-references the usertf pointer to call the callback functions. We recommend that you define your entries in an array, with the last entry set to 0. If the array is named veriusertfs (as is the case for linking to Verilog-XL), then you don't have to provide an

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init_usertfs function, and the simulator will automatically register the entries directly from the array (the last entry must be 0). For example,
s_tfcell veriusertfs[] = { {usertask, 0, 0, 0, abc_calltf, 0, "$abc"}, {usertask, 0, 0, 0, xyz_calltf, 0, "$xyz"}, {0} /* last entry must be 0 */ };

Alternatively, you can add an init_usertfs function to explicitly register each entry from the array:
void init_usertfs() { p_tfcell usertf = veriusertfs; while (usertf->type) mti_RegisterUserTF(usertf++); }

It is an error if a PLI shared library does not contain a veriusertfs array or an init_usertfs function. Since PLI applications are dynamically loaded by the simulator, you must specify which applications to load (each application must be a dynamically loadable library, see Compiling and Linking C Applications for PLI/VPI/DPI). The PLI applications are specified as follows (note that on a Windows platform the file extension would be .dll): As a list in the Veriuser entry in the modelsim.ini file:
Veriuser = pliapp1.so pliapp2.so pliappn.so

As a list in the PLIOBJS environment variable:

% setenv PLIOBJS "pliapp1.so pliapp2.so pliappn.so"

As a -pli argument to the simulator (multiple arguments are allowed):

-pli pliapp1.so -pli pliapp2.so -pli pliappn.so

The various methods of specifying PLI applications can be used simultaneously. The libraries are loaded in the order listed above. Environment variable references can be used in the paths to the libraries in all cases.

Registering VPI Applications

Each VPI application must register its system tasks and functions and its callbacks with the simulator. To accomplish this, one or more user-created registration routines must be called at simulation startup. Each registration routine should make one or more calls to vpi_register_systf() to register user-defined system tasks and functions and vpi_register_cb() to register callbacks. The registration routines must be placed in a table named

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vlog_startup_routines so that the simulator can find them. The table must be terminated with a 0 entry. Example D-1. VPI Application Registration
PLI_INT32 MyFuncCalltf( PLI_BYTE8 *user_data ) { ... } PLI_INT32 MyFuncCompiletf( PLI_BYTE8 *user_data ) { ... } PLI_INT32 MyFuncSizetf( PLI_BYTE8 *user_data ) { ... } PLI_INT32 MyEndOfCompCB( p_cb_data cb_data_p ) { ... } PLI_INT32 MyStartOfSimCB( p_cb_data cb_data_p ) { ... } void RegisterMySystfs( void ) { vpiHandle tmpH; s_cb_data callback; s_vpi_systf_data systf_data; systf_data.type = vpiSysFunc; systf_data.sysfunctype = vpiSizedFunc; systf_data.tfname = "$myfunc"; systf_data.calltf = MyFuncCalltf; systf_data.compiletf = MyFuncCompiletf; systf_data.sizetf = MyFuncSizetf; systf_data.user_data = 0; tmpH = vpi_register_systf( &systf_data ); vpi_free_object(tmpH); callback.reason = cbEndOfCompile; callback.cb_rtn = MyEndOfCompCB; callback.user_data = 0; tmpH = vpi_register_cb( &callback ); vpi_free_object(tmpH); callback.reason = cbStartOfSimulation; callback.cb_rtn = MyStartOfSimCB; callback.user_data = 0; tmpH = vpi_register_cb( &callback ); vpi_free_object(tmpH); } void (*vlog_startup_routines[ ] ) () = { RegisterMySystfs, 0 /* last entry must be 0 */ };

Loading VPI applications into the simulator is the same as described in Registering PLI Applications.

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Using PLI and VPI Together

PLI and VPI applications can co-exist in the same application object file. In such cases, the applications are loaded at startup as follows: If an init_usertfs() function exists, then it is executed and only those system tasks and functions registered by calls to mti_RegisterUserTF() will be defined. If an init_usertfs() function does not exist but a veriusertfs table does exist, then only those system tasks and functions listed in the veriusertfs table will be defined. If an init_usertfs() function does not exist and a veriusertfs table does not exist, but a vlog_startup_routines table does exist, then only those system tasks and functions and callbacks registered by functions in the vlog_startup_routines table will be defined.

As a result, when PLI and VPI applications exist in the same application object file, they must be registered in the same manner. VPI registration functions that would normally be listed in a vlog_startup_routines table can be called from an init_usertfs() function instead.

Registering DPI Applications

DPI applications do not need to be registered. However, each DPI imported or exported task or function must be identified using SystemVerilog import DPI-C or export DPI-Csyntax. Examples of the syntax follow:
export "DPI-C" task t1; task t1(input int i, output int o); . . . end task import "DPI-C" function void f1(input int i, output int o);

Your code must provide imported functions or tasks, compiled with an external compiler. An imported task must return an int value, "1" indicating that it is returning due to a disable, or "0" indicating otherwise. These imported functions or objects may then be loaded as a shared library into the simulator with either the command line option -sv_lib <lib> or -sv_liblist <bootstrap_file>. For example,
vlog dut.v gcc -shared -Bsymbolic -o imports.so imports.c vsim -sv_lib imports top -do <do_file>

The -sv_lib option specifies the shared library name, without an extension. A file extension is added by the tool, as appropriate to your platform. For a list of file extensions accepted by platform, see DPI File Loading.

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You can also use the command line options -sv_root and -sv_liblist to control the process for loading imported functions and tasks. These options are defined in the IEEE Std P1800-2005 LRM.

DPI Use Flow

Correct use of ModelSim DPI depends on the flow presented in this section. Figure D-1. DPI Use Flow Diagram
Step 1 Create header
.v
vlog -dpiheader dpiheader.h

vlog

dpiheader.h

Step 2 Include header

#include "dpiheader.h"

vsim

Step 1.5 Required for Windows only

.c

vsim -dpiexportobj <exportobj>

gcc
<exportobj> C compiler

mtipli.lib

.o
compiled user code

ld/link
loader/linker

Step 3 Compile and load/link C code

<test>.so
shared object

vsim

Step 4 Simulate
vsim -sv_lib <test>

1. Run vlog to generate a dpiheader.h file. This file defines the interface between C and ModelSim for exported and imported tasks and functions. Though the dpiheader.h is a user convenience file rather than requirement, including dpiheader.h in your C code can immediately solve problems

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caused by an improperly defined interface. An example command for creating the header file would be:
vlog -dpiheader <dpiheader>.h files.v

2. Required for Windows only; Run a preliminary invocation of vsim with the -dpiexportobj argument. Because of limitations with the linker/loader provided on Windows, this additional step is required. You must create the exported task/function compiled object file (exportobj) by running a preliminary vsim command, such as:
vsim -dpiexportobj exportobj top

3. Include the dpiheader.h file in your C code. ModelSim recommends that any user DPI C code that accesses exported tasks/functions, or defines imported tasks/functions, will include the dpiheader.h file. This allows the C compiler to verify the interface between C and ModelSim. 4. Compile the C code into a shared object. Compile your code, providing any .a or other .o files required. For Windows users In this step, the object file needs to be bound together with the .obj that you created using the -dpiexportobj argument, into a single .dll file. 5. Simulate the design. When simulating, specify the name of the imported DPI C shared object (according to the SystemVerilog LRM). For example:
vsim -sv_lib <test> top

When Your DPI Export Function is Not Getting Called

This issue can arise in your C code due to the way the C linker resolves symbols. It happens if a name you choose for a SystemVerilog export function happens to match a function name in a custom, or even standard C library. In this case, your C compiler will bind calls to the function in that C library, rather than to the export function in the SystemVerilog simulator. The symptoms of such a misbinding can be difficult to detect. Generally, the misbound function silently returns an unexpected or incorrect value. To determine if you have this type of name aliasing problem, consult the C library documentation (either the online help or man pages).

Simplified Import of FLI / PLI / C Library Functions

In addition to the traditional method of importing FLI / PLI / C library functions, a simplified method can be used: you can declare VPI and FLI functions as DPI-C imports. When you
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declare VPI and FLI functions as DPI-C imports, the DPI shared object is loaded at runtime automatically. Neither the C implementation of the import tf, nor the -sv_lib argument is required. Also, on most platforms (see Platform Specific Information), you can declare most standard C library functions as DPI-C imports. The following example is processed directly, without DPI C code:
package cmath; import "DPI-C" function real sin(input real x); import "DPI-C" function real sqrt(input real x); endpackage package fli; import "DPI-C" function mti_Cmd(input string cmd); endpackage module top; import cmath::*; import fli::*; int status, A; initial begin $display("sin(0.98) = %f", sin(0.98)); $display("sqrt(0.98) = %f", sqrt(0.98)); status = mti_Cmd("change A 123"); $display("A = %1d, status = %1d", A, status); end endmodule

To simulate, you would simply enter a command such as: vsim top.

Platform Specific Information

This feature is not supported on AIX. On Windows, only FLI and PLI commands may be imported in this fashion. C library functions are not automatically importable. They must be wrapped in user DPI C functions, which are brought into the simulator using the -sv_lib argument.

Use Model for Read-Only Work Libraries

You may want to create the work library as a read-only entity, which enables multiple users to simultaneously share the design library at runtime. The steps are as follows: Windows and RS6000/RS64 On these platforms, simply change the permissions on the design library to read only by issuing a command such as "chmod -R a-w <libname>". Do this after you have finished compiling with vlog/vcom and vopt.

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All Other Platforms If a design contains no DPI export tasks or functions, the work library can be changed by simply changing the permissions, as shown for win32 and rs6000/rs64 above. For designs that contain DPI export tasks and functions, and are not run on Windows or RS6000/RS64, by default vsim creates a shared object in directory <libname>/_dpi. This shared object is called exportwrapper.so (Linux and Solaris) or exportwrapper.sl (hp700, hppa64, and hpux_ia64). If you are using a read-only library, vsim must not create any objects in the library.

To prevent vsim from creating objects in the library at runtime, the vsim -dpiexportobj flow is available on all platforms. Use this flow after compilation, but before you start simulation using the design library. An example command sequence on Linux would be:
vlib work vlog -dpiheader dpiheader.h test.sv gcc -shared -Bsymbolic -o test.so test.c vsim -c -dpiexportobj work/_dpi/exportwrapper top chmod -R a-w work

The library is now ready for simulation by multiple simultaneous users, as follows:
vsim top -sv_lib test

The work/_dpi/exportwrapper argument provides a basename for the shared object. At runtime, vsim automatically checks to see if the file work/_dpi/exportwrapper.so is up-todate with respect to its C source code. If it is out of date, an error message is issued and elaboration stops.

Making Verilog Function Calls from non-DPI C Models

Working in certain FLI or PLI C applications, you might want to interact with the simulator by directly calling Verilog DPI export functions. Such applications may include complex 3rd party integrations, or multi-threaded C testbenches. Normally calls to export functions from PLI or FLI code are illegal. These calls are referred to as "out-of-the-blue" calls, since they do not originate in the controlled environment of a DPI import tf. You can set the ModelSim tool to allow out-of-the-blue Verilog function calls either for all simulations (DpiOutOfTheBlue = 1 in modelsim.ini file), or for a specific simulation (vsim dpioutoftheblue 1). One restriction applies: only Verilog functions may be called out of the blue. It is illegal to call Verilog tasks in this way. The simulator issues an error if it detects such a call.

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Compiling and Linking C Applications for PLI/VPI/DPI

The following platform-specific instructions show you how to compile and link your PLI/VPI/DPI C applications so that they can be loaded by ModelSim. Various native C/C++ compilers are supported on different platforms. The gcc compiler is supported on all platforms. The following PLI/VPI/DPI routines are declared in the include files located in the ModelSim <install_dir>/modeltech/include directory: acc_user.h declares the ACC routines veriuser.h declares the TF routines vpi_user.h declares the VPI routines svdpi.h declares DPI routines

The following instructions assume that the PLI, VPI, or DPI application is in a single source file. For multiple source files, compile each file as specified in the instructions and link all of the resulting object files together with the specified link instructions. Although compilation and simulation switches are platform-specific, loading shared libraries is the same for all platforms. For information on loading libraries for PLI/VPI see PLI/VPI file loading. For DPI loading instructions, see DPI File Loading.

For all UNIX Platforms

The information in this section applies to all UNIX platforms.

app.so
If app.so is not in your current directory, you must tell the OS where to search for the shared object. You can do this one of two ways: Add a path before app.so in the command line option or control variable (The path may include environment variables.) Put the path in a UNIX shell environment variable: LD_LIBRARY_PATH_32= <library path without filename> (for Solaris/Linux 32-bit) or LD_LIBRARY_PATH_64= <library path without filename> (for Solaris 64-bit) or SHLIB_PATH= <library path without filename> (for HP-UX)

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Correct Linking of Shared Libraries with -Bsymbolic

In the examples shown throughout this appendix, the -Bsymbolic linker option is used with the compilation (gcc or g++) or link (ld) commands to correctly resolve symbols. This option instructs the linker to search for the symbol within the local shared library and bind to that symbol if it exists. If the symbol is not found within the library, the linker searches for the symbol within the vsimk executable and binds to that symbol, if it exists. When using the -Bsymbolic option, the linker may warn about symbol references that are not resolved within the local shared library. It is safe to ignore these warnings, provided the symbols are present in other shared libraries or the vsimk executable. (An example of such a warning would be a reference to a common API call such as vpi_printf()).

Windows Platforms
Microsoft Visual C 4.1 or Later
cl -c -I<install_dir>\modeltech\include app.c link -dll -export:<init_function> app.obj <install_dir>\win32\mtipli.lib -out:app.dll

For the Verilog PLI, the <init_function> should be "init_usertfs". Alternatively, if there is no init_usertfs function, the <init_function> specified on the command line should be "veriusertfs". For the Verilog VPI, the <init_function> should be "vlog_startup_routines". These requirements ensure that the appropriate symbol is exported, and thus ModelSim can find the symbol when it dynamically loads the DLL. When executing cl commands in a DO file, use the /NOLOGO switch to prevent the Microsoft C compiler from writing the logo banner to stderr. Writing the logo causes Tcl to think an error occurred. If you need to run the profiler (see Profiling Performance and Memory Use) on a design that contains PLI/VPI code, add these two switches to the link commands shown above:
/DEBUG /DEBUGTYPE:COFF

These switches add symbols to the .dll that the profiler can use in its report. MinGW gcc 3.2.3
gcc -c -I<install_dir>\include app.c gcc -shared -Bsymbolic -o app.dll app.o -L<install_dir>\win32 -lmtipli

The ModelSim tool requires the use of MinGW gcc compiler rather than the Cygwin gcc compiler. MinGW gcc is available on the ModelSim FTP site. Remember to add the path to your gcc executable in the Windows environment variables.

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DPI Imports on Windows Platforms

When linking the shared objects, be sure to specify one export option for each DPI imported task or function in your linking command line. You can use the -isymfile argument from the vlog command to obtain a complete list of all imported tasks/functions expected by ModelSim. As an alternative to specifying one -export option for each imported task or function, you can make use of the __declspec (dllexport) macro supported by Visual C. You can place this macro before every DPI import task or function declaration in your C source. All the marked functions will be available for use by vsim as DPI import tasks and functions.

DPI Flow for Exported Tasks and Functions on Windows Platforms

Since the Windows platform lacks the necessary runtime linking capabilities, you must perform an additional manual step in order to prepare shared objects containing calls to exported SystemVerilog tasks or functions. You need to invoke a special run of vsim. The command is as follows:
vsim <top du list> -dpiexportobj <objname> <other args>

The -dpiexportobj generates an object file <objname>.obj that contains "glue" code for exported tasks and functions. You must add that object file to the link line for your .dll, listed after the other object files. For example, a link line for MinGW would be:
gcc -shared -Bsymbolic -o app.dll app.obj <objname>.obj -L<install_dir>\modeltech\win32 -lmtipli

and a link line for Visual C would be:

link -dll -export:<init_function> app.obj <objname>.obj\ <install_dir>\modeltech\win32\mtipli.lib -out:app.dll

32-bit Linux Platform

If your PLI/VPI/DPI application uses anything from a system library, you will need to specify that library when you link your PLI/VPI/DPI application. For example, to use the standard C library, specify -lc to the ld command. gcc compiler
gcc -c -I/<install_dir>/modeltech/include app.c ld -shared -Bsymbolic -E -o app.so app.o -lc

If you are using ModelSim with RedHat version 7.1 or below, you also need to add the -noinhibit-exec switch when you specify -Bsymbolic. The compiler switch -freg-struct-return must be used when compiling any FLI application code that contains foreign functions that return real or time values.

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64-bit Linux for IA64 Platform

64-bit Linux is supported on RedHat Linux Advanced Workstation 2.1 for Itanium 2. gcc compiler (gcc 3.2 or later)
gcc -c -fPIC -I/<install_dir>/modeltech/include app.c ld -shared -Bsymbolic -E --allow-shlib-undefined -o app.so app.o

If your PLI/VPI/DPI application requires a user or vendor-supplied C library, or an additional system library, you will need to specify that library when you link your PLI/VPI/DPI application. For example, to use the system math library libm, specify -lm to the ld command:
gcc -c -fPIC -I/<install_dir>/modeltech/include math_app.c ld -shared -Bsymbolic -E --allow-shlib-undefined -o math_app.so math_app.o -lm

64-bit Linux for Opteron/Athlon 64 and EM64T Platforms

64-bit Linux is supported on RedHat Linux EWS 3.0 for Opteron/Athlon 64 and EM64T. gcc compiler (gcc 3.2 or later)
gcc -c -fPIC -I/<install_dir>/modeltech/include app.c ld -shared -Bsymbolic -E --allow-shlib-undefined -o app.so app.o

To compile for 32-bit operation, specify the -m32 argument on the gcc command line. If your PLI/VPI/DPI application requires a user or vendor-supplied C library, or an additional system library, you will need to specify that library when you link your PLI/VPI/DPI application. For example, to use the system math library libm, specify -lm to the ld command:
gcc -c -fPIC -I/<install_dir>/modeltech/include math_app.c ld -shared -Bsymbolic -E --allow-shlib-undefined -o math_app.so math_app.o -lm

32-bit Solaris Platform

If your PLI/VPI/DPI application uses anything from a system library, you will need to specify that library when you link your PLI/VPI/DPI application. For example, to use the standard C library, specify -lc to the ld command. gcc compiler
gcc -c -I/<install_dir>/modeltech/include app.c ld -G -Bsymbolic -o app.so app.o -lc

cc compiler
cc -c -I/<install_dir>/modeltech/include app.c ld -G -Bsymbolic -o app.so app.o -lc

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64-bit Solaris Platform

gcc compiler
gcc -c -I<install_dir>/modeltech/include -m64 -fPIC app.c gcc -shared -Bsymbolic -o app.so -m64 app.o

This was tested with gcc 3.2.2. You may need to add the location of libgcc_s.so.1 to the LD_LIBRARY_PATH_64 environment variable. cc compiler
cc -v -xarch=v9 -O -I<install_dir>/modeltech/include -c app.c ld -G -Bsymbolic app.o -o app.so

32-bit HP700 Platform

A shared library is created by creating object files that contain position-independent code (use the +z or -fPIC compiler argument) and by linking as a shared library (use the -b linker argument). If your PLI/VPI/DPI application uses anything from a system library, youll need to specify that library when you link your PLI/VPI/DPI application. For example, to use the standard C library, specify -lc to the ld command. gcc compiler
gcc -c -fPIC -I/<install_dir>/modeltech/include app.c ld -b -o app.sl app.o -lc

Note that -fPIC may not work with all versions of gcc. cc compiler
cc -c +z +DD32 -I/<install_dir>/modeltech/include app.c ld -b -o app.sl app.o -lc

64-bit HP Platform
cc compiler
cc -v +DD64 -O -I<install_dir>/modeltech/include -c app.c ld -b -o app.sl app.o -lc

64-bit HP for IA64 Platform

cc compiler (/opt/ansic/bin/cc, /usr/ccs/bin/ld)
cc -c +DD64 -I/<install_dir>/modeltech/include app.c ld -b -o app.sl app.o

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If your PLI/VPI/DPI application requires a user or vendor-supplied C library, or an additional system library, you will need to specify that library when you link your PLI/VPI/DPI application. For example, to use the system math library, specify '-lm' to the 'ld' command:
cc -c +DD64 -I/<install_dir>/modeltech/include math_app.c ld -b -o math_app.sl math_app.o -lm

32-bit IBM RS/6000 Platform

ModelSim loads shared libraries on the IBM RS/6000 workstation. The shared library must import ModelSim's PLI/VPI/DPI symbols, and it must export the PLI or VPI applications initialization function or table. The ModelSim tools export file is located in the ModelSim installation directory in rs6000/mti_exports. If your PLI/VPI/DPI application uses anything from a system library, youll need to specify that library when you link your PLI/VPI/DPI application. For example, to use the standard C library, specify -lc to the ld command. The resulting object must be marked as shared reentrant using these gcc or cc compiler commands for AIX 4.x: gcc compiler
gcc -c -I/<install_dir>/modeltech/include app.c ld -o app.sl app.o -bE:app.exp \ -bI:/<install_dir>/modeltech/rs6000/mti_exports -bM:SRE -bnoentry -lc

cc compiler
cc -c -I/<install_dir>/modeltech/include app.c ld -o app.sl app.o -bE:app.exp \ -bI:/<install_dir>/modeltech/rs6000/mti_exports -bM:SRE -bnoentry -lc

The app.exp file must export the PLI/VPI initialization function or table. For the PLI, the exported symbol should be "init_usertfs". Alternatively, if there is no init_usertfs function, then the exported symbol should be "veriusertfs". For the VPI, the exported symbol should be "vlog_startup_routines". These requirements ensure that the appropriate symbol is exported, and thus ModelSim can find the symbol when it dynamically loads the shared object.

DPI Imports on 32-bit IBM RS/6000 Platform

When linking the shared objects, be sure to specify -bE:<isymfile> option on the link command line. <isymfile> is the name of the file generated by the-isymfile argument to the vlog command. Once you have created the <isymfile>, it contains a complete list of all imported tasks and functions expected by ModelSim.

DPI Flow for Exported Tasks and Functions on 32-bit IBM RS/6000 Platform
Since the RS6000 platform lacks the necessary runtime linking capabilities, you must perform an additional manual step in order to prepare shared objects containing calls to exported

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SystemVerilog tasks or functions shared object file. You need to invoke a special run of vsim. The command is as follows:
vsim <top du list> -dpiexportobj <objname> <other args>

The -dpiexportobj generates the object file <objname>.o that contains "glue" code for exported tasks and functions. You must add that object file to the link line, listed after the other object files. For example, a link line would be:
ld -o app.so app.o <objname>.o -bE:<isymfile> -bI:/<install_dir>/modeltech/rs6000/mti_exports -bM:SRE -bnoentry -lc

64-bit IBM RS/6000 Platform

Only versions 5.1 and later of AIX support the 64-bit platform. A gcc 64-bit compiler is not available at this time. VisualAge cc compiler
cc -c -q64 -I/<install_dir>/modeltech/include app.c ld -o app.s1 app.o -b64 -bE:app.exports \ -bI:/<install_dir>/modeltech/rs64/mti_exports -bM:SRE -bnoentry -lc

DPI Imports on 64-bit IBM RS/6000 Platform

When linking the shared objects, be sure to specify -bE:<isymfile> option on the link command line. <isymfile> is the name of the file generated by the-isymfile argument to the vlog command. Once you have created the <isymfile>, it contains a complete list of all imported tasks and functions expected by ModelSim.

DPI Flow for Exported Tasks and Functions on 64-bit IBM RS/6000 Platform
Since the RS6000 platform lacks the necessary runtime linking capabilities, you must perform an additional manual step in order to prepare shared objects containing calls to exported SystemVerilog tasks or functions shared object file. You need to invoke a special run of vsim. The command is as follows:
vsim <top du list> -dpiexportobj <objname> <other args>

The -dpiexportobj generates the object file <objname>.o that contains "glue" code for exported tasks and functions. You must add that object file to the link line, listed after the other object files. For example, a link line would be:
ld -o app.dll app.o <objname>.o -bE:<isymfile> -bI:/<install_dir>/modeltech/rs6000/mti_exports -bM:SRE -bnoentry -lc

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Compiling and Linking C++ Applications for PLI/VPI/DPI

ModelSim does not have direct support for any language other than standard C; however, C++ code can be loaded and executed under certain conditions. Since ModelSim's PLI/VPI/DPI functions have a standard C prototype, you must prevent the C++ compiler from mangling the PLI/VPI/DPI function names. This can be accomplished by using the following type of extern:
extern "C" { <PLI/VPI/DPI application function prototypes> }

The header files veriuser.h, acc_user.h, and vpi_user.h, svdpi.h, and dpiheader.h already include this type of extern. You must also put the PLI/VPI/DPI shared library entry point (veriusertfs, init_usertfs, or vlog_startup_routines) inside of this type of extern. The following platform-specific instructions show you how to compile and link your PLI/VPI/DPI C++ applications so that they can be loaded by ModelSim. Although compilation and simulation switches are platform-specific, loading shared libraries is the same for all platforms. For information on loading libraries, see DPI File Loading.

For PLI/VPI only

If app.so is not in your current directory you must tell Solaris where to search for the shared object. You can do this one of two ways: Add a path before app.so in the foreign attribute specification. (The path may include environment variables.) Put the path in a UNIX shell environment variable: LD_LIBRARY_PATH_32= <library path without filename> (32-bit) or LD_LIBRARY_PATH_64= <library path without filename> (64-bit)

Windows Platforms
Microsoft Visual C++ 4.1 or Later
cl -c [-GX] -I<install_dir>\modeltech\include app.cxx link -dll -export:<init_function> app.obj <install_dir>\modeltech\win32\mtipli.lib /out:app.dll

The -GX argument enables exception handling.

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For the Verilog PLI, the <init_function> should be "init_usertfs". Alternatively, if there is no init_usertfs function, the <init_function> specified on the command line should be "veriusertfs". For the Verilog VPI, the <init_function> should be "vlog_startup_routines". These requirements ensure that the appropriate symbol is exported, and thus ModelSim can find the symbol when it dynamically loads the DLL. When executing cl commands in a DO file, use the /NOLOGO switch to prevent the Microsoft C compiler from writing the logo banner to stderr. Writing the logo causes Tcl to think an error occurred. If you need to run the profiler (see Profiling Performance and Memory Use) on a design that contains PLI/VPI code, add these two switches to the link command shown above:
/DEBUG /DEBUGTYPE:COFF

These switches add symbols to the .dll that the profiler can use in its report. MinGW C++ Version 3.2.3
g++ -c -I<install_dir>\modeltech\include app.cpp g++ -shared -Bsymbolic -o app.dll app.o -L<install_dir>\modeltech\win32 -lmtipli

ModelSim requires the use of MinGW gcc compiler rather than the Cygwin gcc compiler.

DPI Imports on Windows Platforms

When linking the shared objects, be sure to specify one -export option for each DPI imported task or function in your linking command line. You can use Verilogs -isymfile option to obtain a complete list of all imported tasks and functions expected by ModelSim.

DPI Special Flow for Exported Tasks and Functions

Since the Windows platform lacks the necessary runtime linking complexity, you must perform an additional manual step in order to compile the HDL source files into the shared object file. You need to invoke a special run of vsim. The command is as follows:
vsim <top du list> -dpiexportobj <objname> <other args>

The -dpiexportobj generates the object file <objname>.obj that contains "glue" code for exported tasks and functions. You must add that object file to the link line, listed after the other object files. For example, if the object name was dpi1, the link line for MinGW would be:
g++ -shared -Bsymbolic -o app.dll app.obj <objname>.obj -L<install_dir>\modeltech\win32 -lmtipli

32-bit Linux Platform

GNU C++ Version 2.95.3 or Later

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Verilog PLI/VPI/DPI Compiling and Linking C++ Applications for PLI/VPI/DPI g++ -c -fPIC -I<install_dir>/modeltech/include app.cpp g++ -shared -Bsymbolic -fPIC -o app.so app.o

64-bit Linux for IA64 Platform

64-bit Linux is supported on RedHat Linux Advanced Workstation 2.1 for Itanium 2. GNU C++ compiler version gcc 3.2 or later
g++ -c -fPIC -I/<install_dir>/modeltech/include app.cpp ld -shared -Bsymbolic -E --allow-shlib-undefined -o app.so app.o

If your PLI/VPI application requires a user or vendor-supplied C library, or an additional system library, you will need to specify that library when you link your PLI/VPI application. For example, to use the system math library libm, specify '-lm' to the 'ld' command:
g++ -c -fPIC -I/<install_dir>/modeltech/include math_app.cpp ld -shared -Bsymbolic -E --allow-shlib-undefined -o math_app.so math_app.o -lm

64-bit Linux for Opteron/Athlon 64 and EM64T Platforms

64-bit Linux is supported on RedHat Linux EWS 3.0 for Opteron/Athlon 64 and EM64T. GNU C++ compiler version gcc 3.2 or later
g++ -c -fPIC -I/<install_dir>/modeltech/include app.cpp ld -shared -Bsymbolic -E --allow-shlib-undefined -o app.so app.o

To compile for 32-bit operation, specify the -m32 argument on the gcc command line. If your PLI/VPI/DPI application requires a user or vendor-supplied C library, or an additional system library, you will need to specify that library when you link your PLI/VPI/DPI application. For example, to use the system math library libm, specify -lm to the ld command:
g++ -c -fPIC -I/<install_dir>/modeltech/include math_app.cpp ld -shared -Bsymbolic -E --allow-shlib-undefined -o math_app.so math_app.o -lm

32-bit Solaris Platform

If your PLI/VPI application uses anything from a system library, you will need to specify that library when you link your PLI/VPI application. For example, to use the standard C library, specify -lc to the ld command. GNU C++ compiler version gcc 3.2 or later
g++ -c -I/<install_dir>/modeltech/include app.cpp ld -G -Bsymbolic -o app.so app.o -lc

Sun Forte C++ Compiler

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Verilog PLI/VPI/DPI Compiling and Linking C++ Applications for PLI/VPI/DPI cc -c -I/<install_dir>/modeltech/include app.cpp ld -G -Bsymbolic -o app.so app.o -lc

64-bit Solaris Platform

GNU C++ compiler version gcc 3.2 or later
g++ -c -I<install_dir>/modeltech/include -m64 -fPIC app.cpp g++ -shared -Bsymbolic -o app.so -m64 app.o

This was tested with gcc 3.2.2. You may need to add the location of libgcc_s.so.1 to the LD_LIBRARY_PATH_64 environment variable. cc compiler
cc -v -xarch=v9 -O -I<install_dir>/modeltech/include -c app.cpp ld -G -Bsymbolic app.o -o app.so

32-bit HP700 Platform

A shared library is created by creating object files that contain position-independent code (use the +z or -fPIC compiler argument) and by linking as a shared library (use the -b linker argument). If your PLI/VPI application uses anything from a system library, youll need to specify that library when you link your PLI/VPI application. For example, to use the standard C library, specify -lc to the ld command. GNU C++ compiler
g++ -c -fPIC -I/<install_dir>/modeltech/include app.cpp ld -b -o app.sl app.o -lc

cc compiler
cc -c +z +DD32 -I/<install_dir>/modeltech/include app.cpp ld -b -o app.sl app.o -lc

Note that -fPIC may not work with all versions of gcc.

64-bit HP Platform
cc Compiler
cc -v +DD64 -O -I<install_dir>/modeltech/include -c app.cpp ld -b -o app.sl app.o -lc

64-bit HP for IA64 Platform

HP ANSI C++ Compiler (/opt/ansic/bin/cc, /usr/ccs/bin/ld)

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Verilog PLI/VPI/DPI Compiling and Linking C++ Applications for PLI/VPI/DPI cc -c +DD64 -I/<install_dir>/modeltech/include app.cpp ld -b -o app.sl app.o

If your PLI/VPI application requires a user or vendor-supplied C library, or an additional system library, you will need to specify that library when you link your PLI/VPI application. For example, to use the system math library, specify '-lm' to the 'ld' command:
cc -c +DD64 -I/<install_dir>/modeltech/include math_app.c ld -b -o math_app.sl math_app.o -lm

32-bit IBM RS/6000 Platform

ModelSim loads shared libraries on the IBM RS/6000 workstation. The shared library must import ModelSim's PLI/VPI symbols, and it must export the PLI or VPI applications initialization function or table. The ModelSim tool's export file is located in the ModelSim installation directory in rs6000/mti_exports. If your PLI/VPI application uses anything from a system library, youll need to specify that library when you link your PLI/VPI application. For example, to use the standard C library, specify -lc to the ld command. The resulting object must be marked as shared reentrant using these gcc or cc compiler commands for AIX 4.x: GNU C++ compiler version gcc 3.2 or later
g++ -c -I/<install_dir>/modeltech/include app.cpp ld -o app.sl app.o -bE:app.exp \ -bI:/<install_dir>/modeltech/rs6000/mti_exports -bM:SRE -bnoentry -lc

VisualAge C++ Compiler

cc -c -I/<install_dir>/modeltech/include app.cpp ld -o app.sl app.o -bE:app.exp \ -bI:/<install_dir>/modeltech/rs6000/mti_exports -bM:SRE -bnoentry -lc

The app.exp file must export the PLI/VPI initialization function or table. For the PLI, the exported symbol should be "init_usertfs". Alternatively, if there is no init_usertfs function, then the exported symbol should be "veriusertfs". For the VPI, the exported symbol should be "vlog_startup_routines". These requirements ensure that the appropriate symbol is exported, and thus ModelSim can find the symbol when it dynamically loads the shared object.

For DPI Imports

When linking the shared objects, be sure to specify -bE:<isymfile> option on the link command line. <isymfile> is the name of the file generated by the-isymfile argument to the vlog command. Once you have created the <isymfile>, it contains a complete list of all imported tasks and functions expected by ModelSim.

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DPI Special Flow for Exported Tasks and Functions

Since the RS6000 platform lacks the necessary runtime linking capabilities, you must perform an additional manual step in order to prepare shared objects containing calls to exported SystemVerilog tasks or functions shared object file. You need to invoke a special run of vsim. The command is as follows:
vsim <top du list> -dpiexportobj <objname> <other args>

The -dpiexportobj generates the object file <objname>.o that contains "glue" code for exported tasks and functions. You must add that object file to the link line, listed after the other object files. For example, a link line would be:
ld -o app.dll app.o <objname>.o -bE:<isymfile> -bI:/<install_dir>/modeltech/rs6000/mti_exports -bM:SRE -bnoentry -lc

64-bit IBM RS/6000 Platform

Only version 5.1 and later of AIX supports the 64-bit platform. A gcc 64-bit compiler is not available at this time. VisualAge C++ Compiler
cc -c -q64 -I/<install_dir>/modeltech/include app.cpp ld -o app.s1 app.o -b64 -bE:app.exports \ -bI:/<install_dir>/modeltech/rs64/mti_exports -bM:SRE -bnoentry -lc

For DPI Imports

When linking the shared objects, be sure to specify -bE:<isymfile> option on the link command line. <isymfile> is the name of the file generated by the-isymfile argument to the vlog command. Once you have created the <isymfile>, it contains a complete list of all imported tasks and functions expected by ModelSim.

DPI Special Flow for Exported Tasks and Functions

Since the RS6000 platform lacks the necessary runtime linking capabilities, you must perform an additional manual step in order to prepare shared objects containing calls to exported SystemVerilog tasks or functions shared object file. You need to invoke a special run of vsim. The command is as follows:
vsim <top du list> -dpiexportobj <objname> <other args>

The -dpiexportobj generates the object file <objname>.o that contains "glue" code for exported tasks and functions. You must add that object file to the link line, listed after the other object files. For example, a link line would be:

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Verilog PLI/VPI/DPI Specifying Application Files to Load ld -o app.so app.o <objname>.o -bE:<isymfile> -bI:/<install_dir>/modeltech/rs6000/mti_exports -bM:SRE -bnoentry -lc

Specifying Application Files to Load

PLI and VPI file loading is identical. DPI file loading uses switches to the vsim command.

PLI/VPI file loading

The PLI/VPI applications are specified as follows: As a list in the Veriuser entry in the modelsim.ini file:
Veriuser = pliapp1.so pliapp2.so pliappn.so

As a list in the PLIOBJS environment variable:

% setenv PLIOBJS "pliapp1.so pliapp2.so pliappn.so"

As a -pli argument to the simulator (multiple arguments are allowed):

-pli pliapp1.so -pli pliapp2.so -pli pliappn.so

Note On Windows platforms, the file names shown above should end with .dll rather than .so.

The various methods of specifying PLI/VPI applications can be used simultaneously. The libraries are loaded in the order listed above. Environment variable references can be used in the paths to the libraries in all cases. See also Simulator Variables for more information on the modelsim.ini file.

DPI File Loading

DPI applications are specified to vsim using the following SystemVerilog arguments: Table D-1. vsim Arguments for DPI Application Argument -sv_lib <name> Description specifies a library name to be searched and used. No filename extensions must be specified. (The extensions ModelSim expects are: .sl for HP, .dll for Win32, .so for all other platforms.) specifies a new prefix for shared objects as specified by -sv_lib specifies a bootstrap file to use

-sv_root <name> -sv_liblist

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When the simulator finds an imported task or function, it searches for the symbol in the collection of shared objects specified using these arguments. For example, you can specify the DPI application as follows:
vsim -sv_lib dpiapp1 -sv_lib dpiapp2 -sv_lib dpiappn top

It is a mistake to specify DPI import tasks and functions (tf) inside PLI/VPI shared objects. However, a DPI import tf can make calls to PLI/VPI C code, providing that vsim -gblso was used to mark the PLI/VPI shared object with global symbol visibility. See Loading Shared Objects with Global Symbol Visibility.

Loading Shared Objects with Global Symbol Visibility

On Unix platforms you can load shared objects such that all symbols in the object have global visibility. To do this, use the -gblso argument to vsim when you load your PLI/VPI application. For example:
vsim -pli obj1.so -pli obj2.so -gblso obj1.so top

The -gblso argument works in conjunction with the GlobalSharedObjectList variable in the modelsim.ini file. This variable allows user C code in other shared objects to refer to symbols in a shared object that has been marked as global. All shared objects marked as global are loaded by the simulator earlier than any non-global shared objects.

PLI Example
The following example is a trivial, but complete PLI application.
hello.c: #include "veriuser.h" static PLI_INT32 hello() { io_printf("Hi there\n"); return 0; } s_tfcell veriusertfs[] = { {usertask, 0, 0, 0, hello, 0, "$hello"}, {0} /* last entry must be 0 */ }; hello.v: module hello; initial $hello; endmodule Compile the PLI code for the Solaris operating system: % cc -c -I<install_dir>/modeltech/include hello.c % ld -G -Bsymbolic -o hello.sl hello.o Compile the Verilog code: % vlib work % vlog hello.v Simulate the design:

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Verilog PLI/VPI/DPI VPI Example % vsim -c -pli hello.sl hello # Loading work.hello # Loading ./hello.sl VSIM 1> run -all # Hi there VSIM 2> quit

VPI Example
The following example is a trivial, but complete VPI application. A general VPI example can be found in <install_dir>/modeltech/examples/verilog/vpi.
hello.c: #include "vpi_user.h" static PLI_INT32 hello(PLI_BYTE8 * param) { vpi_printf( "Hello world!\n" ); return 0; } void RegisterMyTfs( void ) { s_vpi_systf_data systf_data; vpiHandle systf_handle; systf_data.type = vpiSysTask; systf_data.sysfunctype = vpiSysTask; systf_data.tfname = "$hello"; systf_data.calltf = hello; systf_data.compiletf = 0; systf_data.sizetf = 0; systf_data.user_data = 0; systf_handle = vpi_register_systf( &systf_data ); vpi_free_object( systf_handle ); } void (*vlog_startup_routines[])() = { RegisterMyTfs, 0 }; hello.v: module hello; initial $hello; endmodule Compile the VPI code for the Solaris operating system: % gcc -c -I<install_dir>/include hello.c % ld -G -Bsymbolic -o hello.sl hello.o Compile the Verilog code: % vlib work % vlog hello.v Simulate the design: % vsim -c -pli hello.sl hello # Loading work.hello # Loading ./hello.sl VSIM 1> run -all # Hello world! VSIM 2> quit

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DPI Example
The following example is a trivial but complete DPI application. For win32 and RS6000 platforms, an additional step is required. For additional examples, see the <install_dir>/modeltech/examples/systemverilog/dpi directory.
hello_c.c: #include "svdpi.h" #include "dpiheader.h" int c_task(int i, int *o) { printf("Hello from c_task()\n"); verilog_task(i, o); /* Call back into Verilog */ *o = i; return(0); /* Return success (required by tasks) */

}
hello.v: module hello_top; int ret; export "DPI-C" task verilog_task; task verilog_task(input int i, output int o); #10; $display("Hello from verilog_task()"); endtask import "DPI-C" context task c_task(input int i, output int o); initial begin c_task(1, ret); // Call the c task named 'c_task()' end endmodule Compile the Verilog code: % vlib work % vlog -sv -dpiheader dpiheader.h hello.v Compile the DPI code for the Solaris operating system: % gcc -c -g -I<install_dir>/modeltech/include hello_c.c % ld -G -Bsymbolic -o hello_c.so hello_c.o Simulate the design: % vsim -c -sv_lib hello_c hello_top # Loading work.hello_c # Loading ./hello_c.so VSIM 1> run -all # Hello from c_task() # Hello from verilog_task() VSIM 2> quit

The PLI Callback reason Argument

The second argument to a PLI callback function is the reason argument. The values of the various reason constants are defined in the veriuser.h include file. See IEEE Std 1364 for a description of the reason constants. The following details relate to ModelSim Verilog, and may not be obvious in the IEEE Std 1364. Specifically, the simulator passes the reason values to the misctf callback functions under the following circumstances:

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Verilog PLI/VPI/DPI The PLI Callback reason Argument reason_endofcompile

For the completion of loading the design.

reason_finish

For the execution of the $finish system task or the quit command.
reason_startofsave

For the start of execution of the checkpoint command, but before any of the simulation state has been saved. This allows the PLI application to prepare for the save, but it shouldn't save its data with calls to tf_write_save() until it is called with reason_save.
reason_save

For the execution of the checkpoint command. This is when the PLI application must save its state with calls to tf_write_save().
reason_startofrestart

For the start of execution of the restore command, but before any of the simulation state has been restored. This allows the PLI application to prepare for the restore, but it shouldn't restore its state with calls to tf_read_restart() until it is called with reason_restart. The reason_startofrestart value is passed only for a restore command, and not in the case that the simulator is invoked with -restore.
reason_restart

For the execution of the restore command. This is when the PLI application must restore its state with calls to tf_read_restart().
reason_reset

For the execution of the restart command. This is when the PLI application should free its memory and reset its state. We recommend that all PLI applications reset their internal state during a restart as the shared library containing the PLI code might not be reloaded. (See the -keeploaded and -keeploadedrestart arguments to vsim for related information.)
reason_endofreset

For the completion of the restart command, after the simulation state has been reset but before the design has been reloaded.
reason_interactive

For the execution of the $stop system task or any other time the simulation is interrupted and waiting for user input.
reason_scope

For the execution of the environment command or selecting a scope in the structure window. Also for the call to acc_set_interactive_scope() if the callback_flag argument is non-zero.
reason_paramvc

For the change of value on the system task or function argument.

reason_synch

For the end of time step event scheduled by tf_synchronize().

reason_rosynch

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Verilog PLI/VPI/DPI The sizetf Callback Function

For the end of time step event scheduled by tf_rosynchronize().

reason_reactivate

For the simulation event scheduled by tf_setdelay().

reason_paramdrc

Not supported in ModelSim Verilog.

reason_force

Not supported in ModelSim Verilog.

reason_release

Not supported in ModelSim Verilog.

reason_disable

Not supported in ModelSim Verilog.

The sizetf Callback Function

A user-defined system function specifies the width of its return value with the sizetf callback function, and the simulator calls this function while loading the design. The following details on the sizetf callback function are not found in the IEEE Std 1364: If you omit the sizetf function, then a return width of 32 is assumed. The sizetf function should return 0 if the system function return value is of Verilog type "real". The sizetf function should return -32 if the system function return value is of Verilog type "integer".

PLI Object Handles

Many of the object handles returned by the PLI ACC routines are pointers to objects that naturally exist in the simulation data structures, and the handles to these objects are valid throughout the simulation, even after the acc_close() routine is called. However, some of the objects are created on demand, and the handles to these objects become invalid after acc_close() is called. The following object types are created on demand in ModelSim Verilog:
accOperator (acc_handle_condition) accWirePath (acc_handle_path) accTerminal (acc_handle_terminal, acc_next_cell_load, acc_next_driver, and acc_next_load) accPathTerminal (acc_next_input and acc_next_output) accTchkTerminal (acc_handle_tchkarg1 and acc_handle_tchkarg2) accPartSelect (acc_handle_conn, acc_handle_pathin, and acc_handle_pathout)

If your PLI application uses these types of objects, then it is important to call acc_close() to free the memory allocated for these objects when the application is done using them.

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Verilog PLI/VPI/DPI Third Party PLI Applications

If your PLI application places value change callbacks on accRegBit or accTerminal objects, do not call acc_close() while these callbacks are in effect.

Third Party PLI Applications

Many third party PLI applications come with instructions on using them with ModelSim Verilog. Even without the instructions, it is still likely that you can get it to work with ModelSim Verilog as long as the application uses standard PLI routines. The following guidelines are for preparing a Verilog-XL PLI application to work with ModelSim Verilog. Generally, a Verilog-XL PLI application comes with a collection of object files and a veriuser.c file. The veriuser.c file contains the registration information as described above in Registering PLI Applications. To prepare the application for ModelSim Verilog, you must compile the veriuser.c file and link it to the object files to create a dynamically loadable object (see Compiling and Linking C Applications for PLI/VPI/DPI). For example, if you have a veriuser.c file and a library archive libapp.a file that contains the application's object files, then the following commands should be used to create a dynamically loadable object for the Solaris operating system:
% cc -c -I<install_dir>/modeltech/include veriuser.c % ld -G -o app.sl veriuser.o libapp.a

The PLI application is now ready to be run with ModelSim Verilog. All that's left is to specify the resulting object file to the simulator for loading using the Veriuser entry in the modesim.ini file, the -pli simulator argument, or the PLIOBJS environment variable (see Registering PLI Applications). Note On the HP700 platform, the object files must be compiled as position-independent code by using the +z compiler argument. Since, the object files supplied for Verilog-XL may be compiled for static linking, you may not be able to use the object files to create a dynamically loadable object for ModelSim Verilog. In this case, you must get the third party application vendor to supply the object files compiled as position-independent code.

Support for VHDL Objects

The PLI ACC routines also provide limited support for VHDL objects in either an all VHDL design or a mixed VHDL/Verilog design. The following table lists the VHDL objects for which handles may be obtained and their type and fulltype constants: Table D-2. Supported VHDL Objects Type accArchitecture Fulltype accArchitecture Description instantiation of an architecture

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Table D-2. Supported VHDL Objects Type accArchitecture accArchitecture accArchitecture accArchitecture Fulltype accEntityVitalLevel0 accArchVitalLevel0 accArchVitalLevel1 accForeignArch Description instantiation of an architecture whose entity is marked with the attribute VITAL_Level0 instantiation of an architecture which is marked with the attribute VITAL_Level0 instantiation of an architecture which is marked with the attribute VITAL_Level1 instantiation of an architecture which is marked with the attribute FOREIGN and which does not contain any VHDL statements or objects other than ports and generics

accArchitecture

accForeignArchMixed instantiation of an architecture which is marked with the attribute FOREIGN and which contains some VHDL statements or objects besides ports and generics accBlock accForLoop accShadow accGenerate accPackage accSignal block statement for loop statement foreign scope created by mti_CreateRegion() generate statement package declaration signal declaration

accBlock accForLoop accForeign accGenerate accPackage accSignal

The type and fulltype constants for VHDL objects are defined in the acc_vhdl.h include file. All of these objects (except signals) are scope objects that define levels of hierarchy in the structure window. Currently, the PLI ACC interface has no provision for obtaining handles to generics, types, constants, variables, attributes, subprograms, and processes.

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Verilog PLI/VPI/DPI IEEE Std 1364 ACC Routines

IEEE Std 1364 ACC Routines

ModelSim Verilog supports the following ACC routines: Table D-3. Supported ACC Routines Routines acc_append_delays acc_append_pulsere acc_close acc_collect acc_compare_handles acc_configure acc_count acc_fetch_argc acc_fetch_argv acc_fetch_attribute acc_fetch_attribute_int acc_fetch_attribute_str acc_fetch_defname acc_fetch_delay_mode acc_fetch_delays acc_fetch_direction acc_fetch_edge acc_fetch_fullname acc_fetch_fulltype acc_fetch_index acc_fetch_location acc_fetch_name acc_fetch_paramtype acc_fetch_paramval acc_fetch_polarity acc_fetch_precision acc_fetch_pulsere acc_fetch_range acc_fetch_size acc_fetch_tfarg acc_fetch_itfarg acc_fetch_tfarg_int acc_fetch_itfarg_int acc_fetch_tfarg_str acc_fetch_itfarg_str acc_fetch_timescale_info acc_fetch_type acc_fetch_type_str acc_fetch_value acc_free acc_handle_by_name acc_handle_calling_mod_m acc_handle_condition acc_handle_conn acc_handle_hiconn acc_handle_interactive_scope acc_handle_loconn acc_handle_modpath acc_handle_notifier acc_handle_object acc_handle_parent acc_handle_path acc_handle_pathin acc_handle_pathout acc_handle_port acc_handle_scope acc_handle_simulated_net acc_handle_tchk acc_handle_tchkarg1 acc_handle_tchkarg2 acc_handle_terminal acc_handle_tfarg acc_handle_itfarg acc_handle_tfinst acc_initialize acc_next acc_next_bit acc_next_cell acc_next_cell_load acc_next_child acc_next_driver acc_next_hiconn acc_next_input acc_next_load acc_next_loconn acc_next_modpath acc_next_net acc_next_output acc_next_parameter acc_next_port acc_next_portout acc_next_primitive acc_next_scope acc_next_specparam acc_next_tchk acc_next_terminal acc_next_topmod acc_object_in_typelist acc_object_of_type acc_product_type acc_product_version acc_release_object acc_replace_delays acc_replace_pulsere acc_reset_buffer acc_set_interactive_scope acc_set_pulsere acc_set_scope acc_set_value acc_vcl_add acc_vcl_delete acc_version

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acc_fetch_paramval() cannot be used on 64-bit platforms to fetch a string value of a parameter. Because of this, the function acc_fetch_paramval_str() has been added to the PLI for this use. acc_fetch_paramval_str() is declared in acc_user.h. It functions in a manner similar to acc_fetch_paramval() except that it returns a char *. acc_fetch_paramval_str() can be used on all platforms.

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Verilog PLI/VPI/DPI IEEE Std 1364 TF Routines

IEEE Std 1364 TF Routines

ModelSim Verilog supports the following TF (task and function) routines; Table D-4. Supported TF Routines Routines io_mcdprintf io_printf mc_scan_plusargs tf_add_long tf_asynchoff tf_iasynchoff tf_asynchon tf_iasynchon tf_clearalldelays tf_iclearalldelays tf_compare_long tf_copypvc_flag tf_icopypvc_flag tf_divide_long tf_dofinish tf_dostop tf_error tf_evaluatep tf_ievaluatep tf_exprinfo tf_iexprinfo tf_getcstringp tf_igetcstringp tf_getinstance tf_getlongp tf_igetlongp tf_getlongtime tf_igetlongtime tf_getnextlongtime tf_getp tf_igetp tf_getpchange tf_igetpchange tf_getrealp tf_igetrealp tf_getrealtime tf_igetrealtime tf_gettime tf_igettime tf_gettimeprecision tf_igettimeprecision tf_gettimeunit tf_igettimeunit tf_getworkarea tf_igetworkarea tf_long_to_real tf_longtime_tostr tf_message tf_mipname tf_imipname tf_movepvc_flag tf_imovepvc_flag tf_multiply_long tf_nodeinfo tf_inodeinfo tf_nump tf_inump tf_propagatep tf_ipropagatep tf_putlongp tf_iputlongp tf_putp tf_iputp tf_putrealp tf_iputrealp tf_read_restart tf_real_to_long tf_rosynchronize tf_irosynchronize tf_scale_longdelay tf_scale_realdelay tf_setdelay tf_isetdelay tf_setlongdelay tf_isetlongdelay tf_setrealdelay tf_isetrealdelay tf_setworkarea tf_isetworkarea tf_sizep tf_isizep tf_spname tf_ispname tf_strdelputp tf_istrdelputp tf_strgetp tf_istrgetp tf_strgettime tf_strlongdelputp tf_istrlongdelputp tf_strrealdelputp tf_istrrealdelputp tf_subtract_long tf_synchronize tf_isynchronize tf_testpvc_flag tf_itestpvc_flag tf_text tf_typep tf_itypep tf_unscale_longdelay tf_unscale_realdelay tf_warning tf_write_save

SystemVerilog DPI Access Routines

ModelSim SystemVerilog supports all routines defined in the "svdpi.h" file defined in P18002005.

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Verilog PLI/VPI/DPI Verilog-XL Compatible Routines

Verilog-XL Compatible Routines

The following PLI routines are not defined in IEEE Std 1364, but ModelSim Verilog provides them for compatibility with Verilog-XL.
char *acc_decompile_exp(handle condition)

This routine provides similar functionality to the Verilog-XL acc_decompile_expr routine. The condition argument must be a handle obtained from the acc_handle_condition routine. The value returned by acc_decompile_exp is the string representation of the condition expression.
char *tf_dumpfilename(void)

This routine returns the name of the VCD file.

void tf_dumpflush(void)

A call to this routine flushes the VCD file buffer (same effect as calling $dumpflush in the Verilog code).
int tf_getlongsimtime(int *aof_hightime)

This routine gets the current simulation time as a 64-bit integer. The low-order bits are returned by the routine, while the high-order bits are stored in the aof_hightime argument.

64-bit Support for PLI

The PLI function acc_fetch_paramval() cannot be used on 64-bit platforms to fetch a string value of a parameter. Because of this, the function acc_fetch_paramval_str() has been added to the PLI for this use. acc_fetch_paramval_str() is declared in acc_user.h. It functions in a manner similar to acc_fetch_paramval() except that it returns a char *. acc_fetch_paramval_str() can be used on all platforms.

Using 64-bit ModelSim with 32-bit Applications

If you have 32-bit PLI/VPI/DPI applications and wish to use 64-bit ModelSim, you will need to port your code to 64 bits by moving from the ILP32 data model to the LP64 data model. We strongly recommend that you consult the 64-bit porting guides for Sun and HP.

PLI/VPI Tracing
The foreign interface tracing feature is available for tracing PLI and VPI function calls. Foreign interface tracing creates two kinds of traces: a human-readable log of what functions were called, the value of the arguments, and the results returned; and a set of C-language files that can be used to replay what the foreign interface code did.

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Verilog PLI/VPI/DPI PLI/VPI Tracing

The Purpose of Tracing Files

The purpose of the logfile is to aid you in debugging PLI or VPI code. The primary purpose of the replay facility is to send the replay files to support for debugging co-simulation problems, or debugging PLI/VPI problems for which it is impractical to send the PLI/VPI code. We still need you to send the VHDL/Verilog part of the design to actually execute a replay, but many problems can be resolved with the trace only.

Invoking a Trace
To invoke the trace, call vsim with the -trace_foreign argument:

Syntax
vsim

-trace_foreign <action> [-tag <name>]

Arguments
<action>

Can be either the value 1, 2, or 3. Specifies one of the following actions: Table D-5. Values for <action> Argument Value 1 2 Operation create log only create replay only Result writes a local file called "mti_trace_<tag>" writes local files called "mti_data_<tag>.c", "mti_init_<tag>.c", "mti_replay_<tag>.c" and "mti_top_<tag>.c" writes all above files

3
-tag <name>

create both log and replay

Used to give distinct file names for multiple traces. Optional.

Examples
vsim -trace_foreign 1 mydesign

Creates a logfile.
vsim -trace_foreign 3 mydesign

Creates both a logfile and a set of replay files.

vsim -trace_foreign 1 -tag 2 mydesign

Creates a logfile with a tag of "2".

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The tracing operations will provide tracing during all user foreign code-calls, including PLI/VPI user tasks and functions (calltf, checktf, sizetf and misctf routines), and Verilog VCL callbacks.

Debugging PLI/VPI/DPI Application Code

ModelSim offers the optional C Debug feature. This tool allows you to interactively debug SystemC/C/C++ source code with the open-source gdb debugger. See C Debug for details. If you dont have access to C Debug, continue reading for instructions on how to attach to an external C debugger. In order to debug your PLI/VPI/DPI application code in a debugger, you must first: 1. Compile the application code with debugging information (using the -g option) and without optimizations (for example, dont use the -O option). 2. Load vsim into a debugger. Even though vsim is stripped, most debuggers will still execute it. You can invoke the debugger directly on vsimk, the simulation kernel where your application code is loaded (for example, "ddd `which vsimk`"), or you can attach the debugger to an already running vsim process. In the second case, you must attach to the PID for vsimk, and you must specify the full path to the vsimk executable (for example, "gdb $MTI_HOME/sunos5/vsimk 1234"). On Solaris, AIX, and Linux systems you can use either gdb or ddd. On HP-UX systems you can use the wdb debugger from HP. You will need version 1.2 or later. 3. Set an entry point using breakpoint. Since initially the debugger recognizes only vsim's PLI/VPI/DPI function symbols, when invoking the debugger directly on vsim you need to place a breakpoint in the first PLI/VPI/DPI function that is called by your application code. An easy way to set an entry point is to put a call to acc_product_version() as the first executable statement in your application code. Then, after vsim has been loaded into the debugger, set a breakpoint in this function. Once you have set the breakpoint, run vsim with the usual arguments. When the breakpoint is reached, the shared library containing your application code has been loaded. 4. In some debuggers, you must use the share command to load the application's symbols. At this point all of the application's symbols should be visible. You can now set breakpoints in and single step through your application code.

Troubleshooting a Missing DPI Import Function

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Verilog PLI/VPI/DPI Debugging PLI/VPI/DPI Application Code

DPI uses C function linkage. If your DPI application is written in C++, it is important to remember to use extern "C" declaration syntax appropriately. Otherwise the C++ compiler will produce a mangled C++ name for the function, and the simulator is not able to locate and bind the DPI call to that function. Also, if you do not use the -Bsymbolic argument on the command line for specifying a link, the system may bind to an incorrect function, resulting in unexpected behavior. For more information, see Correct Linking of Shared Libraries with -Bsymbolic.

HP-UX Specific Warnings

On HP-UX you might see some warning messages that vsim does not have debugging information available. This is normal. If you are using Exceed to access an HP machine from Windows NT, it is recommended that you run vsim in command line or batch mode because your NT machine may hang if you run vsim in GUI mode. Click on the "go" button, or use F5 or the go command to execute vsim in wdb. You might also see a warning about not finding "__dld_flags" in the object file. This warning can be ignored. You should see a list of libraries loaded into the debugger. It should include the library for your PLI/VPI/DPI application. Alternatively, you can use share to load only a single library.

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Appendix E Command and Keyboard Shortcuts

This appendix is a collection of the keyboard and command shortcuts available in the ModelSim GUI.

Command Shortcuts
You may abbreviate command syntax, but theres a catch the minimum number of characters required to execute a command are those that make it unique. Remember, as we add new commands some of the old shortcuts may not work. For this reason ModelSim does not allow command name abbreviations in macro files. This minimizes your need to update macro files as new commands are added. Multiple commands may be entered on one line if they are separated by semi-colons (;). For example:
vlog -nodebug=ports level3.v level2.v ; vlog -nodebug top.v

The return value of the last function executed is the only one printed to the transcript. This may cause some unexpected behavior in certain circumstances. Consider this example:
vsim -c -do "run 20 ; simstats ; quit -f" top

You probably expect the simstats results to display in the Transcript window, but they will not, because the last command is quit -f. To see the return values of intermediate commands, you must explicitly print the results. For example:
vsim -do "run 20 ; echo [simstats]; quit -f" -c top

Command History Shortcuts

You can review the simulator command history, or reuse previously entered commands with the following shortcuts at the ModelSim/VSIM prompt: Table E-1. Command History Shortcuts Shortcut !! !n !abc Description repeats the last command repeats command number n; n is the VSIM prompt number (e.g., for this prompt: VSIM 12>, n =12) repeats the most recent command starting with "abc"

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Command and Keyboard Shortcuts Main and Source Window Mouse and Keyboard Shortcuts

Table E-1. Command History Shortcuts (cont.) Shortcut ^xyz^ab^ up arrow and down arrow keys click on prompt Description replaces "xyz" in the last command with "ab" scrolls through the command history left-click once on a previous ModelSim or VSIM prompt in the transcript to copy the command typed at that prompt to the active cursor shows the last few commands (up to 50 are kept)

his or history

Main and Source Window Mouse and Keyboard Shortcuts

The following mouse actions and special keystrokes can be used to edit commands in the entry region of the Main window. They can also be used in editing the file displayed in the Source window and all Notepad windows (enter the notepad command within ModelSim to open the Notepad editor). Table E-2. Mouse Shortcuts Mouse - UNIX and Windows Click the left mouse button Click and drag the left mouse button Shift-click the left mouse button Double-click the left mouse button Double-click and drag the left mouse button Ctrl-click the left mouse button Click the left mouse button on a previous ModelSim or VSIM prompt Click the middle mouse button Click and drag the middle mouse button Result relocate the cursor select an area extend selection select a word select a group of words move insertion cursor without changing the selection copy and paste previous command string to current prompt paste selection to the clipboard scroll the window

Table E-3. Keyboard Shortcuts Keystrokes - UNIX and Windows Left Arrow Right Arrow
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Result move cursor left or right one character

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Table E-3. Keyboard Shortcuts (cont.) Keystrokes - UNIX and Windows Ctrl + Left Arrow Ctrl + Right Arrow Shift + Any Arrow Ctrl + Shift + Left Arrow Ctrl + Shift + Right Arrow Up Arrow Down Arrow Ctrl + Up Arrow Ctrl + Down Arrow Ctrl + Home Ctrl + End Backspace Ctrl + h (UNIX only) Delete Ctrl + d (UNIX only) Esc (Windows only) Alt Alt-F4 Home Ctrl + a (UNIX only) Ctrl + b Ctrl + d End Ctrl + e Ctrl + f (UNIX) Right Arrow (Windows) Ctrl + k Ctrl + n Ctrl + o (UNIX only) Ctrl + p Result move cursor left or right one word extend text selection extend text selection by one word Transcript Pane: scroll through command history Source Window: move cursor one line up or down Transcript Pane: moves cursor to first or last line Source Window: moves cursor up or down one paragraph move cursor to the beginning of the text move cursor to the end of the text delete character to the left delete character to the right cancel activate or inactivate menu bar mode close active window move cursor to the beginning of the line move cursor left delete character to the right move cursor to the end of the line move cursor right one character delete to the end of line move cursor one line down (Source window only under Windows) insert a new line character at the cursor move cursor one line up (Source window only under Windows)

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Table E-3. Keyboard Shortcuts (cont.) Keystrokes - UNIX and Windows Ctrl + s (UNIX) Ctrl + f (Windows) Ctrl + t Ctrl + u Page Down Ctrl + v (UNIX only) Ctrl + w (UNIX) Ctrl + x (Windows) Ctrl + s Ctrl + x (UNIX Only) Ctrl + y (UNIX) Ctrl + v (Windows) Ctrl + a (Windows Only) Ctrl + \ Ctrl + - (UNIX) Ctrl + / (UNIX) Ctrl + z (Windows) Meta + < (UNIX only) Meta + > (UNIX only) Page Up Meta + v (UNIX only) Meta + w (UNIX) Ctrl + c (Windows) F3 F4 Shift+F4 F5 Shift+F5 F8 F9 F10 F11 (Windows only)
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Result find reverse the order of the two characters on either side of the cursor delete line move cursor down one screen cut the selection save paste the selection select the entire contents of the widget clear any selection in the widget undoes previous edits in the Source window

move cursor to the beginning of the file move cursor to the end of the file move cursor up one screen copy selection Peforms a Find Next action in the Source Window. Change focus to next pane in main window Change focus to previous pane in main window Toggle between expanding and restoring size of pane to fit the entire main window Toggle on/off the pane headers. search for the most recent command that matches the characters typed (Main window only) run simulation continue simulation single-step
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Command and Keyboard Shortcuts List Window Keyboard Shortcuts

Table E-3. Keyboard Shortcuts (cont.) Keystrokes - UNIX and Windows F12 (Windows only) Result step-over

The Main window allows insertions or pastes only after the prompt; therefore, you dont need to set the cursor when copying strings to the command line.

List Window Keyboard Shortcuts

Using the following keys when the mouse cursor is within the List window will cause the indicated actions: Table E-4. List Window Keyboard Shortcuts Key - UNIX and Windows Left Arrow Right Arrow Up Arrow Down Arrow Page Up Ctrl + Up Arrow Page Down Ctrl + Down Arrow Tab Shift + Tab Action scroll listing left (selects and highlights the item to the left of the currently selected item) scroll listing right (selects and highlights the item to the right of the currently selected item) scroll listing up scroll listing down scroll listing up by page scroll listing down by page searches forward (down) to the next transition on the selected signal searches backward (up) to the previous transition on the selected signal (does not function on HP workstations) extends selection left/right opens the Find dialog box to find the specified item label within the list display

Shift + Left Arrow Shift + Right Arrow Ctrl + f (Windows) Ctrl + s (UNIX)

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Wave Window Mouse and Keyboard Shortcuts

The following mouse actions and keystrokes can be used in the Wave window. Table E-5. Wave Window Mouse Shortcuts Mouse action Ctrl + Click left mouse button and drag1 Ctrl + Click left mouse button and drag Ctrl + Click left mouse button and drag Click left mouse button and drag Ctrl + Click left mouse button on a scroll bar arrow Result zoom area (in)

zoom out

zoom fit

moves closest cursor scrolls window to very top or bottom (vertical scroll) or far left or right (horizontal scroll)

Click middle mouse button in scroll bar scrolls window to position of (UNIX only) click
1. If you enter zoom mode by selecting View > Zoom > Mouse Mode > Zoom Mode, you do not need to hold down the <Ctrl> key.

Table E-6. Wave Window Keyboard Shortcuts Keystroke s i Shift + i + o Shift + o f Shift + f l Shift + l r Shift + r Action bring into view and center the currently active cursor zoom in (mouse pointer must be over the cursor or waveform panes) zoom out (mouse pointer must be over the cursor or waveform panes) zoom full (mouse pointer must be over the cursor or waveform panes) zoom last (mouse pointer must be over the cursor or waveform panes) zoom range (mouse pointer must be over the cursor or waveform panes)

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Command and Keyboard Shortcuts Wave Window Mouse and Keyboard Shortcuts

Table E-6. Wave Window Keyboard Shortcuts Keystroke Up Arrow Down Arrow Action scrolls entire window up or down one line, when mouse pointer is over waveform pane scrolls highlight up or down one line, when mouse pointer is over pathname or values pane scroll pathname, values, or waveform pane left scroll pathname, values, or waveform pane right scroll waveform pane up by a page scroll waveform pane down by a page search forward (right) to the next transition on the selected signal - finds the next edge search backward (left) to the previous transition on the selected signal - finds the previous edge open the find dialog box; searches within the specified field in the pathname pane for text strings scroll pathname, values, or waveform pane left or right by a page

Left Arrow Right Arrow Page Up Page Down Tab Shift + Tab Ctrl + f (Windows) Ctrl + s (UNIX) Ctrl + Left Arrow Ctrl + Right Arrow

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Appendix F Setting GUI Preferences

The ModelSim GUI is programmed using Tcl/Tk. It is highly customizable. You can control everything from window size, position, and color to the text of window prompts, default output filenames, and so forth. Most user GUI preferences are stored as Tcl variables in the .modelsim file on Unix/Linux platforms or the Registry on Windows platforms. The variable values save automatically when you exit ModelSim. Some of the variables are modified by actions you take with menus or windows (e.g., resizing a window changes its geometry variable). Or, you can edit the variables directly either from the ModelSim > prompt or the Edit Preferences dialog.

Customizing the Simulator GUI Layout

You can customize the layout of panes, windows, toolbars, etc. This section discusses layouts and how they are used in ModelSim.

Layouts and Modes of Operation

ModelSim ships with three default layouts that correspond to three modes of operation. Table F-1. Predefined GUI Layouts Layout NoDesign Simulate Coverage Mode a design is not yet loaded a design is loaded a design is loaded with code coverage enabled

As you load and unload designs, ModelSim switches between the layouts.

Custom Layouts
You can create custom layouts or modify the three default layouts.

Creating Custom Layouts

To create a custom layout or modify one of the default layouts, follow these steps: 1. Rearrange the GUI as you see fit (see Navigating the Graphic User Interface for details).

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2. Select Layout > Save. Figure F-1. Save Current Window Layout Dialog Box

3. Specify a new name or use an existing name to overwrite that layout. 4. Click OK. The layout is saved to the .modelsim file (or Registry on Windows).

Assigning Layouts to Modes

You can assign which layout appears in each mode (no design loaded, design loaded, design loaded with coverage). Follow these steps: 1. Create your custom layouts as described above. 2. Select Layout > Configure. Example F-1. Configure Window Layouts Dialog Box

3. Select a layout for each mode. 4. Click OK. The layout assignment is saved to the .modelsim file (Registry on Windows).

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Setting GUI Preferences Navigating the Graphic User Interface

Automatic Saving of Layouts

By default any changes you make to a layout are saved automatically when you exit the tool or when you change modes. For example, if you load a design with code coverage, rearrange some windows, and then quit the simulation, the changes are saved to whatever layout was assigned to the "load with coverage" mode. To disable automatic saving of layouts, select Layout > Configure and uncheck Save Window Layout Automatically.

Resetting Layouts to Their Defaults

You can reset the layouts for the three modes to their original defaults. Select Layout > Reset. This command does not delete custom layouts.

Navigating the Graphic User Interface

This section discusses how to rearrange various elements of the GUI.

Manipulating Panes
Window panes (e.g., Workspace) can be positioned at various places within the parent window or they can be dragged out ("undocked") of the parent window altogether. Figure F-2. GUI: Window Pane

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Moving Panes
When you see a double bar at the top edge of a pane, it means you can modify the pane position. Figure F-3. GUI: Double Bar

Click-and drag the pane handle in the middle of a double bar (your mouse pointer will change to a four-headed arrow when it is in the correct location) to reposition the pane inside the parent window. As you move the mouse to various parts of the main window, a gray outline will show you valid locations to drop the pane. Or, drag the pane outside of the parent window, and when you let go of the mouse button, the pane becomes a free-floating window.

Docking and Undocking Panes

You can undock a pane by clicking the undock button in the heading of a pane. Figure F-4. GUI: Undock Button

To redock a floating pane, click on the pane handle at the top of the window and drag it back into the parent window, or click the dock icon. Figure F-5. GUI: Dock Button

Zooming Panes
You can expand panes to fill the entire Main window by clicking the zoom icon in the heading of the pane. Figure F-6. GUI: Zoom Button

To restore the pane to its original size and position click the unzoom button in the heading of the pane.

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Figure F-7. GUI: Zoom Button

Columnar Information Display

Many panes (e.g., Objects, Workspace, etc.) display information in a columnar format. You can perform a number of operations on columnar formats: Click and drag on a column heading to rearrange columns Click and drag on a border between column names to increase/decrease column size Sort columns by clicking once on the column heading to sort in ascending order; clicking twice to sort in descending order; and clicking three times to sort in default order. Hide or show columns by either right-clicking a column heading and selecting an object from the context menu or by clicking the column-list drop down arrow and selecting an object.

Quick Access Toolbars

Toolbar buttons provide access to commonly used commands and functions. Toolbars can be docked and undocked (moved to or from the main toolbar area) by clicking and dragging on the toolbar handle at the left-edge of a toolbar. Figure F-8. Toolbar Manipulation

You can also hide/show the various toolbars. To hide or show a toolbar, right-click on a blank spot of the main toolbar area and select a toolbar from the list. To reset toolbars to their original state, right-click on a blank spot of the main toolbar area and select Reset.

Simulator GUI Preferences

Simulator GUI preferences are stored by default either in the .modelsim file in your HOME directory on UNIX/Linux platforms or the Registry on Windows platforms.

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Setting Preference Variables from the GUI

To edit a variable value from the GUI, select Tools > Edit Preferences. The dialog organizes preferences by window and by name. The By Window tab primarily allows you to change colors and fonts for various GUI objects. For example, if you want to change the color of assertion messages in the Main window, you would select "Main window" in the first column, select "assertColor" in the second column, and click a color on the palette. Clicking OK or Apply changes the variable, and the change is saved when you exit ModelSim. Figure F-9. Preferences Dialog Box: By Window Tab

The By Name tab lists every Tcl variable in a tree structure. Expand the tree, highlight a variable, and click Change Value to edit the current value.

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Figure F-10. Preferences Dialog Box: By Name Tab

Saving GUI Preferences

GUI preferences are saved automatically when you exit the tool. If you prefer to store GUI preferences elsewhere, set the MODELSIM_PREFERENCES environment variable to designate where these preferences are stored. Setting this variable causes ModelSim to use a specified path and file instead of the default location. Here are some additional points to keep in mind about this variable setting: The file does not need to exist before setting the variable as ModelSim will initialize it. If the file is read-only, ModelSim will not update or otherwise modify the file. This variable may contain a relative pathname, in which case the file is relative to the working directory at the time the tool is started.

The modelsim.tcl File

Previous versions saved user GUI preferences into a modelsim.tcl file. Current versions will still read in a modelsim.tcl file if it exists. ModelSim searches for the file as follows:

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use MODELSIM_TCL environment variable if it exists (if MODELSIM_TCL is a list of files, each file is loaded in the order that it appears in the list); else use ./modelsim.tcl; else use $(HOME)/modelsim.tcl if it exists

Note that in versions 6.1 and later, ModelSim will save to the .modelsim file any variables it reads in from a modelsim.tcl file. The values from the modelsim.tcl file will override like variables in the .modelsim file.

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Appendix G System Initialization

ModelSim goes through numerous steps as it initializes the system during startup. It accesses various files and environment variables to determine library mappings, configure the GUI, check licensing, and so forth.

Files Accessed During Startup

The table below describes the files that are read during startup. They are listed in the order in which they are accessed. Table G-1. Files Accessed During Startup File modelsim.ini location map file Purpose contains initial tool settings; see Simulator Control Variables for specific details on the modelsim.ini file used by ModelSim tools to find source files based on easily reallocated "soft" paths; default file name is mgc_location_map contains defaults for fonts, colors, prompts, window positions, and other simulator window characteristics contains last working directory, project file, printer defaults, and other user-customized GUI characteristics contains user-customized settings for fonts, colors, prompts, other GUI characteristics; maintained for backwards compatibility with older versions (see The modelsim.tcl File) if available, loads last project file which is specified in the registry (Windows) or $(HOME)/.modelsim (UNIX); see What are Projects? for details on project settings

pref.tcl .modelsim (UNIX) or Windows registry modelsim.tcl

<project_name>.mpf

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Environment Variables Accessed During Startup

The table below describes the environment variables that are read during startup. They are listed in the order in which they are accessed. For more information on environment variables, see Environment Variables. Table G-2. Environment Variables Accessed During Startup Environment variable MODEL_TECH MODEL_TECH_OVERRIDE MODELSIM MGC_WD MGC_LOCATION_MAP MODEL_TECH_TCL HOME MGC_HOME TCL_LIBRARY Purpose set by ModelSim to the directory in which the binary executables reside (e.g., ../modeltech/<platform>/) provides an alternative directory for the binary executables; MODEL_TECH is set to this path identifies the pathname of the modelsim.ini file identifies the Mentor Graphics working directory identifies the pathname of the location map file; set by ModelSim if not defined identifies the pathname of all Tcl libraries installed with ModelSim identifies your login directory (UNIX only) identifies the pathname of the MGC tool suite identifies the pathname of the Tcl library; set by ModelSim to the same pathname as MODEL_TECH_TCL; must point to libraries supplied by Model Technology identifies the pathname of the Tk library; set by ModelSim to the same pathname as MODEL_TECH_TCL; must point to libraries supplied by Model Technology identifies the pathname of the [incr]Tcl library; set by ModelSim to the same path as MODEL_TECH_TCL; must point to libraries supplied by Model Technology identifies the pathname of the [incr]Tk library; set by ModelSim to the same pathname as MODEL_TECH_TCL; must point to libraries supplied by Model Technology identifies the pathname of the Tcl files that are used by ModelSim; set by ModelSim to the same pathname as MODEL_TECH_TCL; must point to libraries supplied by Model Technology creates an mti_trace_cosim file containing debugging information about FLI/PLI/VPI function calls; set to any value before invoking the simulator identifies the path to all Tcl libraries installed with ModelSim
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ITCL_LIBRARY

ITK_LIBRARY

VSIM_LIBRARY

MTI_COSIM_TRACE

MTI_LIB_DIR
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Table G-2. Environment Variables Accessed During Startup Environment variable MTI_VCO_MODE Purpose determines which version of ModelSim to use on platforms that support both 32- and 64-bit versions when ModelSim executables are invoked from the modeltech/bin directory by a Unix shell command (using full path specification or PATH search) identifies the pathname to a user preference file (e.g., C:\modeltech\modelsim.tcl); can be a list of file pathnames, separated by semicolons (Windows) or colons (UNIX); note that user preferences are now stored in the .modelsim file (Unix) or registry (Windows); ModelSim will still read this environment variable but it will then save all the settings to the .modelsim file when you exit the tool

MODELSIM_TCL

Initialization Sequence
The following list describes in detail ModelSims initialization sequence. The sequence includes a number of conditional structures, the results of which are determined by the existence of certain files and the current settings of environment variables. In the steps below, names in uppercase denote environment variables (except MTI_LIB_DIR which is a Tcl variable). Instances of $(NAME) denote paths that are determined by an environment variable (except $(MTI_LIB_DIR) which is determined by a Tcl variable). 1. Determines the path to the executable directory (../modeltech/<platform>). Sets MODEL_TECH to this path, unless MODEL_TECH_OVERRIDE exists, in which case MODEL_TECH is set to the same value as MODEL_TECH_OVERRIDE. 2. Finds the modelsim.ini file by evaluating the following conditions: use $(MODELSIM)/modelsim.ini if it exists; else use $(MGC_PWD)/modelsim.ini; else use ./modelsim.ini; else use $(MODEL_TECH)/modelsim.ini; else use $(MODEL_TECH)/../modelsim.ini; else use $(MGC_HOME)/lib/modelsim.ini; else set path to ./modelsim.ini even though the file doesnt exist

3. Finds the location map file by evaluating the following conditions: use MGC_LOCATION_MAP if it exists (if this variable is set to "no_map", ModelSim skips initialization of the location map); else
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use mgc_location_map if it exists; else use $(HOME)/mgc/mgc_location_map; else use $(HOME)/mgc_location_map; else use $(MGC_HOME)/etc/mgc_location_map; else use $(MGC_HOME)/shared/etc/mgc_location_map; else use $(MODEL_TECH)/mgc_location_map; else use $(MODEL_TECH)/../mgc_location_map; else use no map

4. Reads various variables from the [vsim] section of the modelsim.ini file. See Simulation Control Variables for more details. 5. Parses any command line arguments that were included when you started ModelSim and reports any problems. 6. Defines the following environment variables: use MODEL_TECH_TCL if it exists; else set MODEL_TECH_TCL=$(MODEL_TECH)/../tcl set TCL_LIBRARY=$(MODEL_TECH_TCL)/tcl8.3 set TK_LIBRARY=$(MODEL_TECH_TCL)/tk8.3 set ITCL_LIBRARY=$(MODEL_TECH_TCL)/itcl3.0 set ITK_LIBRARY=$(MODEL_TECH_TCL)/itk3.0 set VSIM_LIBRARY=$(MODEL_TECH_TCL)/vsim

7. Initializes the simulators Tcl interpreter. 8. Checks for a valid license (a license is not checked out unless specified by a modelsim.ini setting or command line option). 9. The next four steps relate to initializing the graphical user interface. 10. Sets Tcl variable MTI_LIB_DIR=$(MODEL_TECH_TCL) 11. Loads $(MTI_LIB_DIR)/vsim/pref.tcl. 12. Loads GUI preferences, project file, etc. from the registry (Windows) or $(HOME)/.modelsim (UNIX). 13. Searches for the modelsim.tcl file by evaluating the following conditions: use MODELSIM_TCL environment variable if it exists (if MODELSIM_TCL is a list of files, each file is loaded in the order that it appears in the list); else
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use ./modelsim.tcl; else use $(HOME)/modelsim.tcl if it exists

That completes the initialization sequence. Also note the following about the modelsim.ini file: When you change the working directory within ModelSim, the tool reads the [library], [vcom], and [vlog] sections of the local modelsim.ini file. When you make changes in the compiler or simulator options dialog or use the vmap command, the tool updates the appropriate sections of the file. The pref.tcl file references the default .ini file via the [GetPrivateProfileString] Tcl command. The .ini file that is read will be the default file defined at the time pref.tcl is loaded.

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Appendix H Logic Modeling SmartModels

You can use the Logic Modeling SWIFT-based SmartModel library with ModelSim. The SmartModel library is a collection of behavioral models supplied in binary form with a procedural interface that is accessed by the simulator. You must obtain SmartModel library from Logic Modeling along with the documentation that describes how to use it. This appendix only describes the specifics of using the library with ModelSim. Note The VHDL SmartModel interface is available as an add-on to ModelSim PE but is not available with ModelSim LE because it does not support VHDL.

VHDL SmartModel Interface

ModelSim VHDL interfaces to a SmartModel through a foreign architecture. The foreign architecture contains a foreign attribute string that associates a specific SmartModel with the architecture. On elaboration of the foreign architecture, the simulator automatically loads the SmartModel library software and establishes communication with the specific SmartModel. To enable the SmartModel interface you must do the following: Set the LMC_HOME environment variable to the root of the SmartModel library installation directory. Consult Logic Modeling's documentation for details. Uncomment the appropriate libswift entry in the modelsim.ini file for your operating system. If you are running the Windows operating system, you must also comment out the default libsm entry (precede the line with the ";" character) and uncomment the libsm entry for the Windows operating system.

The libswift and libsm entries are found under the [lmc] section of the default modelsim.ini file located in the ModelSim installation directory. The default settings are as follows:

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[lmc] ; The simulator's interface to Logic Modeling's SmartModel SWIFT software libsm = $MODEL_TECH/libsm.sl ; The simulator's interface to Logic Modeling's SmartModel SWIFT software ; (Windows NT) ; libsm = $MODEL_TECH/libsm.dll ; Logic Modeling's SmartModel SWIFT software (HP 9000 Series 700) ; libswift = $LMC_HOME/lib/hp700.lib/libswift.sl ; Logic Modeling's SmartModel SWIFT software (IBM RISC System/6000) ; libswift = $LMC_HOME/lib/ibmrs.lib/swift.o ; Logic Modeling's SmartModel SWIFT software (Sun4 Solaris) ; libswift = $LMC_HOME/lib/sun4Solaris.lib/libswift.so ; Logic Modeling's SmartModel SWIFT software (Windows NT) ; libswift = $LMC_HOME/lib/pcnt.lib/libswift.dll ; Logic Modeling's SmartModel SWIFT software (Linux) ; libswift = $LMC_HOME/lib/x86_linux.lib/libswift.so

The simulator automatically loads both the libsm and libswift libraries when it elaborates a SmartModel foreign architecture. libsm This variable points to the tools dynamic link library that interfaces the foreign architecture to the SmartModel software. By default, the libsm entry points to the libsm.sl supplied in the ModelSim installation directory indicated by the MODEL_TECH environment variable. ModelSim automatically sets the MODEL_TECH environment variable to the appropriate directory containing the executables and binaries for the current operating system. libswift This variable points to the Logic Modeling dynamic link library software that accesses the SmartModels.

Creating Foreign Architectures with sm_entity

The sm_entity tool automatically creates entities and foreign architectures for SmartModels.

Syntax
sm_entity [-] [-xe] [-xa] [-c] [-all] [-v] [-93] [<SmartModelName>...]

Arguments
- Read SmartModel names from standard input. -xe Do not generate entity declarations. -xa Do not generate architecture bodies. -c Generate component declarations. -all Select all models installed in the SmartModel library. -v Display progress messages. -93 Use extended identifiers where needed.

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<SmartModelName> Name of a SmartModel (see the SmartModel library documentation for details on SmartModel names).

Usage Flow
1. Create the entity and foreign architecture using the sm_entity tool. By default, the sm_entity tool writes an entity and foreign architecture to stdout, but you can redirect it to a file with the following syntax
% sm_entity -all > sml.vhd

2. Compile the entity and foreign architecture into a library named lmc. For example, the following commands compile the entity and foreign architecture:
% vlib lmc % vcom -work lmc sml.vhd

3. Generate a component declaration You will need to generate a component declaration for the SmartModels so that you can instantiate the SmartModels in your VHDL design. Add these component declarations to a package named sml (for example), and compile the package into the lmc library:
% sm_entity -all -c -xe -xa > smlcomp.vhd

4. Create a package of SmartModel component declarations Edit the resulting smlcomp.vhd file to turn it into a package as follows:
library ieee; use ieee.std_logic_1164.all; package sml is <component declarations go here> end sml;

5. Compile the package into the lmc library:

% vcom -work lmc smlcomp.vhd

6. Reference the SmartModels in your design. Add the following library and use clauses to your code:
library lmc; use lmc.sml.all;

Example Output
The following is an example of an entity and foreign architecture created by sm_entity for the cy7c285 SmartModel.
library ieee; use ieee.std_logic_1164.all;

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entity cy7c285 is generic (TimingVersion : STRING := "CY7C285-65"; DelayRange : STRING := "Max"; MemoryFile : STRING := "memory" ); port ( A0 : in std_logic; A1 : in std_logic; A2 : in std_logic; A3 : in std_logic; A4 : in std_logic; A5 : in std_logic; A6 : in std_logic; A7 : in std_logic; A8 : in std_logic; A9 : in std_logic; A10 : in std_logic; A11 : in std_logic; A12 : in std_logic; A13 : in std_logic; A14 : in std_logic; A15 : in std_logic; CS : in std_logic; O0 : out std_logic; O1 : out std_logic; O2 : out std_logic; O3 : out std_logic; O4 : out std_logic; O5 : out std_logic; O6 : out std_logic; O7 : out std_logic; WAIT_PORT : inout std_logic ); end; architecture SmartModel of cy7c285 is attribute FOREIGN : STRING; attribute FOREIGN of SmartModel : architecture is "sm_init $MODEL_TECH/libsm.sl ; cy7c285"; begin end SmartModel;

Entity Details
o

The entity name is the SmartModel name (you can manually change this name if you like). The port names are the same as the SmartModel port names (these names must not be changed). If the SmartModel port name is not a valid VHDL identifier, then sm_entity automatically converts it to a valid name. If sm_entity is invoked with the -93 option, then the identifier is converted to an extended identifier, and the resulting entity must also be compiled with the -93 option. If the -93 option had been specified in the example above, then WAIT would have been converted to \WAIT\. Note that in this example the port WAIT was converted to WAIT_PORT because wait is a VHDL reserved word. The port types are std_logic. This data type supports the full range of SmartModel logic states.

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The DelayRange, TimingVersion, and MemoryFile generics represent the SmartModel attributes of the same name. Consult your SmartModel library documentation for a description of these attributes (and others). Sm_entity creates a generic for each attribute of the particular SmartModel. The default generic value is the default attribute value that the SmartModel has supplied to sm_entity.

Architecture Details
o

The first part of the foreign attribute string (sm_init) is the same for all SmartModels. The second part ($MODEL_TECH/libsm.sl) is taken from the libsm entry in the initialization file, modelsim.ini. The third part (cy7c285) is the SmartModel name. This name correlates the architecture with the SmartModel at elaboration.

SmartModel Vector Ports

The entities generated by sm_entity only contain single-bit ports, never vectored ports. This is necessary because ModelSim correlates entity ports with the SmartModel SWIFT interface by name. However, for ease of use in component instantiations, you may want to create a custom component declaration and component specification that groups ports into vectors. You can also rename and reorder the ports in the component declaration. You can also reorder the ports in the entity declaration, but you can't rename them! The following is an example component declaration and specification that groups the address and data ports of the CY7C285 SmartModel:
component cy7c285 generic ( TimingVersion : STRING := "CY7C285-65"; DelayRange : STRING := "Max"; MemoryFile : STRING := "memory" ); port ( A : in std_logic_vector (15 downto 0); CS : in std_logic; O : out std_logic_vector (7 downto 0); WAIT_PORT : inout std_logic ); end component; for all: cy7c285 use entity work.cy7c285 port map (A0 => A(0), A1 => A(1), A2 => A(2), A3 => A(3), A4 => A(4), A5 => A(5), A6 => A(6), A7 => A(7), A8 => A(8), A9 => A(9), A10 => A(10),

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Logic Modeling SmartModels VHDL SmartModel Interface A11 => A(11), A12 => A(12), A13 => A(13), A14 => A(14), A15 => A(15), CS => CS, O0 => O(0), O1 => O(1), O2 => O(2), O3 => O(3), O4 => O(4), O5 => O(5), O6 => O(6), O7 => O(7), WAIT_PORT => WAIT_PORT );

Command Channel
The command channel is a SmartModel feature that lets you invoke SmartModel specific commands. These commands are documented in the SmartModel library documentation from Synopsys. ModelSim provides access to the Command Channel from the command line. The form of a SmartModel command is:
lmc {<instance_name> | -all} "<SmartModel command>"

instance_name is either a full hierarchical name or a relative name of a SmartModel instance. A relative name is relative to the current environment setting (see environment command). For example, to turn timing checks off for SmartModel /top/u1:
lmc /top/u1 "SetConstraints Off"

-all applies the command to all SmartModel instances. For example, to turn timing checks off for all SmartModel instances:
lmc -all "SetConstraints Off"

There are also some SmartModel commands that apply globally to the current simulation session rather than to models. The form of a SmartModel session command is:
lmcsession "<SmartModel session command>"

SmartModel Windows
Some models in the SmartModel library provide access to internal registers with a feature called SmartModel Windows. Refer to Logic Modelings SmartModel library documentation for details on this feature. The simulator interface to this feature is described below. Window names that are not valid VHDL or Verilog identifiers are converted to VHDL extended identifiers. For example, with a window named z1I10.GSR.OR, the tool treats the name as \z1I10.GSR.OR\ (for all commands including lmcwin, add wave, and examine). You must then use that name in all commands. For example,

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Logic Modeling SmartModels VHDL SmartModel Interface add wave /top/swift_model/\z1I10.GSR.OR\

Extended identifiers are case sensitive.

ReportStatus
The ReportStatus command displays model information, including the names of window registers. For example,
lmc /top/u1 ReportStatus

SmartModel Windows description:

WA "Read-Only (Read Only)" WB "1-bit" WC "64-bit"

This model contains window registers named wa, wb, and wc. These names can be used in subsequent window (lmcwin) commands.

SmartModel lmcwin Commands

Each of the following commands requires a window instance argument that identifies a specific model instance and window name. For example, /top/u1/wa refers to window wa in model instance /top/u1. lmcwin read displays the current value of a window.
lmcwin read <window_instance> [-<radix>]

The optional radix argument is -binary, -decimal, or -hexadecimal (these names can be abbreviated). The default is to display the value using the std_logic characters. For example, the following command displays the 64-bit window wc in hexadecimal:
lmcwin read /top/u1/wc -h

lmcwin write writes a value into a window.

lmcwin write <window_instance> <value>

The format of the value argument is the same as used in other simulator commands that take value arguments. For example, to write 1 to window wb, and all 1s to window wc:
lmcwin write /top/u1/wb 1 lmcwin write /top/u1/wc X"FFFFFFFFFFFFFFFF"

lmcwin enable enables continuous monitoring of a window.

lmcwin enable <window_instance>

The specified window is added to the model instance as a signal (with the same name as the window) of type std_logic or std_logic_vector. This signal's values can then be referenced in simulator commands that read signal values, such as the add list command

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shown below. The window signal is continuously updated to reflect the value in the model. For example, to list window wa:
lmcwin enable /top/u1/wa add list /top/u1/wa

lmcwin disable disables continuous monitoring of a window.

lmcwin disable <window_instance>

The window signal is not deleted, but it no longer is updated when the models window register changes value. For example, to disable continuous monitoring of window wa:
lmcwin disable /top/u1/wa

lmcwin release disables the effect of a previous lmcwin write command on a window net.
lmcwin release <window_instance>

Some windows are actually nets, and the lmcwin write command behaves more like a continuous force on the net.

Memory Arrays
A memory model usually makes the entire register array available as a window. In this case, the window commands operate only on a single element at a time. The element is selected as an array reference in the window instance specification. For example, to read element 5 from the window memory mem:
lmcwin read /top/u2/mem(5)

Omitting the element specification defaults to element 0. Also, continuous monitoring is limited to a single array element. The associated window signal is updated with the most recently enabled element for continuous monitoring.

Verilog SmartModel Interface

The SWIFT SmartModel library, beginning with release r40b, provides an optional library of Verilog modules and a PLI application that communicates between a simulator's PLI and the SWIFT simulator interface. The Logic Modeling documentation refers to this as the Logic Models to Verilog (LMTV) interface. To install this option, you must select the simulator type "Verilog" when you run Logic Modelings SmartInstall program.

Linking the LMTV Interface to the Simulator

Synopsys provides a dynamically loadable library that links ModelSim to the LMTV interface. Refer to Logic Modelings SmartModel library documentation for details on this feature.

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Index
Symbols
#, comment character, 534 $disable_signal_spy, 476 $enable_signal_spy, 477 $finish behavior, customizing, 576 $unit scope, visibility in SV declarations, 173 .ini control variables AssertFile, 569 AssertionDebug, 569 AssertionFormat, 569 AssertionFormatBreak, 570 AssertionFormatError, 570 AssertionFormatFail, 570 AssertionFormatFatal, 570 AssertionFormatNote, 570 AssertionFormatWarning, 571 BreakOnAssertion, 571 CheckPlusargs, 571 CheckpointCompressMode, 571 CommandHistory, 571 ConcurrentFileLimit, 572 CoverExcludeDefault, 572 CoverGenerate, 572 DatasetSeparator, 572 DefaultForceKind, 572 DefaultRadix, 573 DefaultRestartOptions, 573 DelayFileOpen, 573 DumpportsCollapse, 573 GenerateFormat, 573 GlobalSharedObjectList, 574 IgnoreError, 574 IgnoreFailure, 574 IgnoreNote, 574 IgnoreWarning, 574 IterationLimit, 575 License, 575 LockedMemory, 576 NumericStdNoWarnings, 576
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PathSeparator, 577 Resolution, 577 RunLength, 577 ScTimeUnit, 577 ShowUnassociatedScNameWarning, 578 ShowUndebuggableScTypeWarning, 578 Startup, 578 StdArithNoWarnings, 579 ToggleMaxIntValues, 579 TranscriptFile, 579 UCDBFilename, 579 UnbufferedOutput, 579 UseCsupV2, 580 UserTimeUnit, 580 Veriuser, 580 WarnConstantChange, 580 WaveSignalNameWidth, 580 WLFCacheSize, 581 WLFCollapseMode, 581 WLFCompress, 581 WLFDeleteOnQuit, 581 WLFFilename, 581 WLFOptimize, 581 WLFSaveAllRegions, 582 WLFSizeLimit, 582 WLFTimeLimit, 582 .ini variables set simulator control with GUI, 583 .modelsim file in initialization sequence, 664 purpose, 661 .so, shared object file loading PLI/VPI/DPI C applications, 616 loading PLI/VPI/DPI C++ applications, 623

Numerics
0-In tools setting environment variable, 552 1076, IEEE Std, 39

675

A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
differences between versions, 139 1364, IEEE Std, 39, 167 64-bit libraries, 133 64-bit time now variable, 591 Tcl time commands, 539 64-bit vsim, using with 32-bit FLI apps, 640

B
bad magic number error message, 303 base (radix) List window, 337 Wave window, 331 batch-mode simulations, 38 BindAtCompile .ini file variable, 562 binding, VHDL, default, 143 bitwise format, 358 blocking assignments, 184 bookmarks Source window, 94 Wave window, 323 break stop simulation run, 58 BreakOnAssertion .ini file variable, 571 breakpoints C code, 434 deleting, 94, 349 setting, 94 setting automatically in C code, 437 Source window, viewing in, 87 .bsm file, 373 bubble diagram Finite State Machines, 420 using the mouse, 421 buffered/unbuffered output, 579 busses RTL-level, reconstructing, 310 user-defined, 341 buswise format, 358

A
ACC routines, 637 accelerated packages, 132 access hierarchical objects, 463 limitations in mixed designs, 250 Active Processes pane, 60 see also windows, Active Processes pane aggregates, SystemC, 222 annotating differences, wave compare, 359 api_version in error message, 237 architecture simulator state variable, 590 archives described, 126 argc simulator state variable, 590 arguments passing to a DO file, 546 arguments, accessing commandl-line, 233 arithmetic package warnings, disabling, 588 array of sc_signal<T>, 222 AssertFile .ini file variable, 569 AssertionDebug .ini variable, 569 AssertionFormat .ini file variable, 569 AssertionFormatBreak .ini file variable, 570 AssertionFormatError .ini file variable, 570 AssertionFormatFail .ini file variable, 570 AssertionFormatFatal .ini file variable, 570 AssertionFormatNote .ini file variable, 570 AssertionFormatWarning .ini file variable, 571 assertions file and line number, 569 message display, 584 messages turning off, 588 setting format of messages, 569 warnings, locating, 569 auto find bp command, 437 auto step mode, C Debug, 437
676

C
C applications compiling and linking, 616 debugging, 431 C Debug, 431 auto find bp, 437 auto step mode, 437 debugging functions during elaboration, 439 debugging functions when exiting, 443 function entry points, finding, 437 initialization mode, 439 registered function calls, identifying, 437

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running from a DO file, 433 Stop on quit mode, 443 C++ applications compiling and linking, 623 C/C++ composite types, debugging elements of, 219 Call Stack pane, 60 cancelling scheduled events, performance, 165 case sensitivity named port associations, 268 causality, tracing in Dataflow window, 368 cdbg_wait_for_starting command, 433 cell libraries, 190 chasing X, 369 -check_synthesis argument warning message, 600 CheckPlusargs .ini file variable (VLOG), 571 CheckpointCompressMode .ini file variable, 571 CheckSynthesis .ini file variable, 562 cin support, SystemC, 231 class of sc_signal<T>, 222 cleanup SystemC state-based code, 217 clean-up of SystemC state-based code, 217 clock change, sampling signals at, 347 clock cycles display in timeline, 329 clocked comparison, 356 Code Coverage $coverage_save system function, 195 by instance, 382 columns in workspace, 63 condition coverage, 383, 405 Current Exclusions pane, 66 data types supported, 383 Details pane, 67 display filter toolbar, 70 enabling with vcom or vlog, 385 enabling with vsim, 386 excluding lines/files, 392 exclusion filter files used in multiple simulation runs, 396 expression coverage, 383, 406 important notes, 378 Instance Coverage pane, 67 Main window coverage data, 386 missed branches, 66 missed coverage, 65 pragma exclusions, 393 reports, 397 Source window data, 388 source window details, 68 statistics in Main window, 386 toggle coverage, 383 toggle coverage in Signals window, 390 toggle details, 68 vcover utility, 380 Workspace pane, 63 Code coverage IF conditions, 406 code profiling, 447 collapsing ports, and coverage reporting, 399 collapsing time and delta steps, 309 colorization, in Source window, 94 columns hide/showing in GUI, 657 moving, 657 sorting by, 657 combining signals, busses, 341 CommandHistory .ini file variable, 571 command-line arguments, accessing, 233 command-line mode, 37 commands event watching in DO file, 545 system, 537 VSIM Tcl commands, 538 comment character Tcl and DO files, 534 compare add signals, 353 adding regions, 354 by signal, 353 clocked, 356 difference markers, 358 displayed in list window, 360 icons, 359 options, 356 pathnames, 357 reference dataset, 352

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
reference region, 354 tab, 352 test dataset, 352 timing differences, 358 tolerance, 356 values, 359 wave window display, 357 compare by region, 354 compare commands, 351 compare signal, virtual restrictions, 341 compare simulations, 301 compilation multi-file issues (SystemVerilog), 173 compilation unit scope, 173 compile SystemC reducing non-debug compile time, 211 compile order auto generate, 116 changing, 115 SystemVerilog packages, 170 compiler directives, 199 IEEE Std 1364-2000, 200 XL compatible compiler directives, 201 compiling overview, 35 changing order in the GUI, 115 gensrc errors during, 237 grouping files, 116 order, changing in projects, 115 properties, in projects, 120 range checking in VHDL, 138 SystemC, 206 converting sc_main(), 207 exporting top level module, 207 for source level debug, 211 invoking sccom, 210 linking the compiled source, 215 modifying source code, 207 replacing sc_start(), 207 using sccom vs. raw C++ compiler, 212 Verilog, 168 incremental compilation, 169 XL uselib compiler directive, 175 XL compatible options, 174 VHDL, 137, 138 VITAL packages, 152 compiling C code, gcc, 617 component declaration generating SystemC from Verilog or VHDL, 286 generating VHDL from Verilog, 265 vgencomp for SystemC, 286 vgencomp for VHDL, 265 component, default binding rules, 143 Compressing files VCD tasks, 520 ConcurrentFileLimit .ini file variable, 572 configuration simulator state variable, 590 configurations instantiation in mixed designs, 264 Verilog, 177 connectivity, exploring, 365 construction parameters, SystemC, 233 context menus Library tab, 128 control function, SystemC, 251 control_foreign_signal() function, 250 convert real to time, 155 convert time to real, 154 Coverage INF, 404 coverage enable FSMs, 409 finite state machines, 409 for generate blocks, 378 fsm arc, 409 fsm details, 419 fsm exclusions, 429 fsm in the GUI, 417 fsm reports, 421 fsm states, 409 fsm transitions, 409 missed states, 418 see also Code Coverage setting default mode, 400 UCDB, 377 coverage reports, 397 default mode, 400

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reporting all signals, 399 sample reports, 401 xml format, 401 coverage toggle_ignore pragma, 395 $coverage_save system function, 195 CoverExcludeDefault .ini file variable, 572 CoverGenerate .ini file variable, 572 covreport.xsl, 401 CppOptions .ini file variable (sccom), 567 CppPath .ini file variable (sccom), 567 current exclusions pragmas, 393 Current Exclusions pane, 66 cursors adding, deleting, locking, naming, 319 link to Dataflow window, 365 measuring time with, 318 trace events with, 368 Wave window, 318 customizing via preference variables, 657 C code, 431 debugging the design, overview, 37 default binding BindAtCompile .ini file variable, 562 disabling, 144 default binding rules, 143 default coverage mode, setting, 400 Default editor, changing, 552 default SystemC parameter values, overriding, 233 DefaultForceKind .ini file variable, 572 DefaultRadix .ini file variable, 573 DefaultRestartOptions .ini variable, 573 DefaultRestartOptions variable, 589 delay delta delays, 144 modes for Verilog models, 190 DelayFileOpen .ini file variable, 573 deleting library contents, 127 delta collapsing, 309 delta simulator state variable, 590 deltas in List window, 344 referencing simulator iteration as a simulator state variable, 590 dependent design units, 138 descriptions of HDL items, 94 design library creating, 127 logical name, assigning, 128 mapping search rules, 130 resource type, 125 VHDL design units, 137 working type, 125 design object icons, described, 47 design portability and SystemC, 211 design units, 125 details code coverage, 67 DEVICE matching to specify path delays, 506 dialogs Runtime Options, 583 Direct Programming Interface, 607 directories

D
deltas explained, 144 dashed signal lines, 102 data types Code Coverage, 383 Dataflow window, 71, 363 extended mode, 363 pan, 367 zoom, 367 see also windows, Dataflow window dataflow.bsm file, 373 Dataset Browser, 306 Dataset Snapshot, 308 datasets, 301 managing, 306 opening, 304 reference, 352 restrict dataset prefix display, 307 test, 352 view structure, 305 DatasetSeparator .ini file variable, 572 debuggable SystemC objects, 219 debugging
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moving libraries, 130 disable_signal_spy, 465 DisableOpt .ini file variable, 559 display preferences Wave window, 328 distributed delay mode, 191 dividers Wave window, 332 DLL files, loading, 616, 623 DO files (macros) error handling, 549 executing at startup, 553, 578 parameters, passing to, 546 Tcl source command, 549 docking window panes, 655 documentation, 42 DOPATH environment variable, 552 DPI export TFs, 599 missing DPI import function, 642 registering applications, 611 use flow, 612 DPI access routines, 639 DPI export TFs, 599 DPI/VPI/PLI, 607 drivers Dataflow Window, 365 show in Dataflow window, 347 Wave window, 347 dumpports tasks, VCD files, 519 DumpportsCollapse .ini file variable, 573 protect compiler directive, 200 securing pre-compiled libraries, 134 end_of_construction() function, 232 end_of_simulation() function, 232 ENDFILE function, 150 ENDLINE function, 150 endprotect compiler directive, 200 entities default binding rules, 143 entity simulator state variable, 590 environment variables, 551 accessed during startup, 662 expansion, 551 referencing from command line, 556 referencing with VHDL FILE variable, 556 setting, 552 setting in Windows, 555 TranscriptFile, specifying location of, 579 used in Solaris linking for FLI, 616, 623 used in Solaris linking for PLI/VPI/DPI/FLI, 553 using with location mapping, 593 variable substitution using Tcl, 537 error cant locate C compiler, 599 Error .ini file variable, 586 errors "api_version" in, 237 bad magic number, 303 DPI missing import function, 642 getting more information, 596 libswift entry not found, 602 multiple definition, 238 out-of-line function, 238 severity level, changing, 596 SystemC loading, 236 SystemVerilog, missing declaration, 560 Tcl_init error, 600 void function, 238 VSIM license lost, 602 escaped identifiers, 189, 268 EVCD files exporting, 495 importing, 496 event order

E
Editing in notepad windows, 646 in the Main window, 646 in the Source window, 646 EDITOR environment variable, 552 editor, default, changing, 552 elements of C/C++ composite types, debugging, 219 embedded wave viewer, 366 empty port name warning, 599 enable_signal_spy, 466 encryption
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in Verilog simulation, 182 event queues, 182 event watching commands, placement of, 545 events, tracing, 368 exclusion filter files excluding udp truth table rows, 394 used in multiple simulation runs, 396 exclusions lines and files, 392 exit codes, 597 exiting tool, customizing, 576 expand environment variables, 551 expand net, 365 Explicit .ini file variable, 562 export TFs, in DPI, 599 Exporting SystemC modules to Verilog, 276 exporting SystemC modules to VHDL, 286 exporting top SystemC module, 207 Expression Builder, 326 configuring a List trigger with, 345 saving expressions to Tcl variable, 327 extended identifiers in mixed designs, 265, 286 signals in Objects window, 82 filters for Code Coverage used in multiple simulation runs, 396 Finite State Machines, 409 arc coverage, 409 bubble diagram, 420 coverage exclusions, 429 coverage reports, 421 disabling extraction using pragmas, 415 enable coverage, 409 enable recognition, 409 extraction reporting, 413 FSM Viewer, 420 recognition, 409 state coverage, 409 supported design styles, 412 supported types, 410 transition coverage, 409 types of coverage, 409 unsupported design styles, 413 viewing coverage in GUI, 417 fixed-point types, in SystemC compiling for support, 231 construction parameters for, 233 FLI debugging, 431 folders, in projects, 118 fonts controlling in X-sessions, 48 scaling, 47 force command defaults, 589 foreign model loading SmartModels, 667 foreign module declaration Verilog example, 270 VHDL example, 280 foreign module declaration, SystemC, 269 format file, 339 Wave window, 339 FPGA libraries, importing, 134 Function call, debugging, 60 function calls, identifying with C Debug, 437

F
F8 function key, 648 Fatal .ini file variable, 586 field descriptions coverage reports, 401 FIFOs, viewing SystemC, 223 File compression VCD tasks, 520 file compression SDF files, 499 file I/O TextIO package, 146 file-line breakpoints, 94 files .modelsim, 661 files, grouping for compile, 116 filter processes, 60 filtering
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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
functions SystemC control, 251 observe, 251 unsupported, 231 virtual, 311

H
Hazard .ini file variable (VLOG), 560 hazards limitations on detection, 186 hierarchical references SystemC/HDL designs, 251 hierarchical references, mixed-language, 250 hierarchy driving signals in, 467, 478 forcing signals in, 154, 472, 482 referencing signals in, 154, 469, 480 releasing signals in, 154, 474, 484 highlighting, in Source window, 94 history of commands shortcuts for reuse, 645 HOLD matching to Verilog, 506 HOME environment variable, 552 HOME_0IN environment variable, 552 HP aCC, restrictions on compiling with, 212

G
-g C++ compiler option, 220 g++, alternate installations, 211 gdb debugger, 431 generate blocks coverage, 378 generate statements, Veilog, 178 GenerateFormat .ini file variable, 573 GenerateLoopIterationMax .ini file variable, 559 GenerateRecursionDepthMax .ini variable, 559 generic support flow for VHDL instantiating SC, 287 SC instantiating VHDL, 280 generics passing to sc_foreign_module (VHDL), 281 SystemC instantiating VHDL, 280 VHDL, 255 generics, integer passing as template arguments, 283 generics, integer and non-integer passing as constructor arguments, 281 get_resolution() VHDL function, 153 global visibility PLI/FLI shared objects, 630 GLOBALPATHPULSE matching to specify path delays, 506 GlobalSharedObjectsList .ini file variable, 574 graphic interface, 313, 363 grouping files for compile, 116 grouping objects, Monitor window, 97 groups in wave window, 334 GUI_expression_format GUI expression builder, 326

I
I/O TextIO package, 146 icons shapes and meanings, 47 identifiers escaped, 189, 268 ieee .ini file variable, 557 IEEE libraries, 132 IEEE Std 1076, 39 differences between versions, 139 IEEE Std 1364, 39, 167 IgnoreError .ini file variable, 574 IgnoreFailure .ini file variable, 574 IgnoreNote .ini file variable, 574 IgnoreVitalErrors .ini file variable, 563 IgnoreWarning .ini file variable, 574 importing EVCD files, waveform editor, 496 importing FPGA libraries, 134 Incremental .ini file variable, 560 incremental compilation automatic, 171 manual, 171

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
with Verilog, 169 index checking, 138 INF coverage count, 404 $init_signal_driver, 478 init_signal_driver, 467 $init_signal_spy, 480 init_signal_spy, 154, 469 init_usertfs function, 442, 608 initialization of SystemC state-based code, 217 initialization sequence, 663 inlining VHDL subprograms, 139 input ports matching to INTERCONNECT, 505 matching to PORT, 505 instance code coverage, 382 instantiation in mixed-language design Verilog from VHDL, 264 VHDL from Verilog, 267 instantiation in SystemC-Verilog design SystemC from Verilog, 276 Verilog from SystemC, 269 instantiation in SystemC-VHDL design VHDL from SystemC, 279 instantiation in VHDL-SystemC design SystemC from VHDL, 285 INTERCONNECT matching to input ports, 505 interconnect delays, 510 IOPATH matching to specify path delays, 505 iteration_limit, infinite zero-delay loops, 146 IterationLimit .ini file variable, 575

L
-L work, 172 language templates, 91 language versions, VHDL, 139 libraries 64-bit and 32-bit in same library, 133 creating, 127 design libraries, creating, 127 design library types, 125 design units, 125 group use, setting up, 130 IEEE, 132 importing FPGA libraries, 134 mapping from the command line, 129 from the GUI, 129 hierarchically, 587 search rules, 130 modelsim_lib, 153 moving, 130 multiple libraries with common modules, 172 naming, 128 predefined, 131 refreshing library images, 133 resource libraries, 125 std library, 131 Synopsys, 132 Verilog, 172, 253 VHDL library clause, 131 working libraries, 125 working vs resource, 34 working with contents of, 127 library map file, Verilog configurations, 177 library mapping, overview, 35 library maps, Verilog 2001, 177 library simulator state variable, 590 library, definition, 34 libsm, 667 libswift, 667 entry not found error, 602 License .ini file variable, 575 licensing License variable in .ini file, 575 linking SystemC source, 215

K
keyboard shortcuts List window, 649 Main window, 646 Source window, 646 Wave window, 650 keywords SystemVerilog, 168

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
List pane see also pane, List pane List window, 75, 316 setting triggers, 345 waveform comparison, 360 see also windows, List window LM_LICENSE_FILE environment variable, 553 loading the design, overview, 36 Locals window, 77 see also windows, Locals window location maps, referencing source files, 593 locations maps specifying source files with, 593 lock message, 600 LockedMemory .ini file variable, 576 locking cursors, 319 log file overview, 301 see also WLF files Logic Modeling SmartModel command channel, 672 SmartModel Windows lmcwin commands, 673 memory arrays, 674 long simulations saving at intervals, 308 mapping data types, 252 libraries from the command line, 129 hierarchically, 587 symbols Dataflow window, 373 SystemC in mixed designs, 263 SystemC to Verilog, 259 SystemC to VHDL, 263 Verilog states in mixed designs, 254 Verilog states in SystemC designs, 258 Verilog to SytemC, port and data types, 258 Verilog to VHDL data types, 253 VHDL to SystemC, 256 VHDL to Verilog data types, 255 mapping libraries, library mapping, 129 mapping signals, waveform editor, 496 math_complex package, 132 math_real package, 132 MDI frame, 53 MDI pane tab groups, 54 memories displaying the contents of, 78 navigation, 80 saving formats, 80 selecting memory instances, 79 viewing contents, 79 viewing multiple instances, 79 memory modeling in VHDL, 156 memory allocation profiler, 448 memory leak, cancelling scheduled events, 165 Memory pane, 78 pane Memory pane see also Memory pane memory tab memories you can view, 78 Memory window, 78 see also windows, Memory window merging results from multiple simulation runs, 396 message system, 595

M
MacroNestingLevel simulator state variable, 591 macros (DO files), 545 creating from a saved transcript, 51 depth of nesting, simulator state variable, 591 error handling, 549 parameters as a simulator state variable (n), 591 passing, 546 total number passed, 590 startup macros, 588 Main window, 48 code coverage, 386 see also windows, Main window manuals, 42
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Message Viewer tab, 52 Messages, 52 messages, 595 bad magic number, 303 empty port name warning, 599 exit codes, 597 getting more information, 596 lock message, 600 long description, 596 message system variables, 585 metavalue detected, 600 redirecting, 579 sensitivity list warning, 600 suppressing warnings from arithmetic packages, 588 Tcl_init error, 600 too few port connections, 601 turning off assertion messages, 588 VSIM license lost, 602 warning, suppressing, 596 metavalue detected warning, 600 MGC_LOCATION_MAP env variable, 593 MGC_LOCATION_MAP variable, 553 MinGW gcc, 617, 624 missed coverage branches, 66 Missed Coverage pane, 65 missing DPI import function, 642 mixed-language simulation, 249 access limitations, 250 mode, setting default coverage, 400 MODEL_TECH environment variable, 553 MODEL_TECH_TCL environment variable, 553 modeling memory in VHDL, 156 MODELSIM environment variable, 553 modelsim.ini found by the tool, 663 default to VHDL93, 589 delay file opening with, 589 environment variables in, 587 force command default, setting, 589 hierarchical library mapping, 587 opening VHDL files, 589 restart command defaults, setting, 589 startup file, specifying with, 588 transcript file created from, 587 turning off arithmetic package warnings, 588 turning off assertion messages, 588 modelsim.tcl, 659 modelsim_lib, 153 path to, 558 MODELSIM_PREFERENCES variable, 554, 659 MODELSIM_TCL environment variable, 554 modes of operation, 37 Modified field, Project tab, 115 modules handling multiple, common names, 172 with unnamed ports, 266 Monitor window grouping/ungrouping objects, 97 monitor window, 96 mouse shortcuts Main window, 646 Source window, 646 Wave window, 650 .mpf file, 107 loading from the command line, 123 order of access during startup, 661 msgmode .ini file variable, 586 msgmode variable, 52 mti_cosim_trace environment variable, 554 mti_inhibit_inline attribute, 139 MTI_SYSTEMC macro, 211 MTI_TF_LIMIT environment variable, 554 multi-file compilation issues, SystemVerilog, 173 MultiFileCompilationUnit .ini file variable, 560 multiple document interface, 53 Multiple simulations, 301

N
n simulator state variable, 591 Name field Project tab, 114 name visibility in Verilog generates, 178 names, modules with the same, 172 negative timing
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$setuphold/$recovery, 197 algorithm for calculating delays, 187 check limits, 187 nets Dataflow window, displaying in, 71, 363 values of displaying in Objects window, 82 saving as binary log file, 301 waveforms, viewing, 98 Nlview widget Symlib format, 374 NoCaseStaticError .ini file variable, 563 NOCHANGE matching to Verilog, 508 NoDebug .ini file variable (VCOM), 563 NoDebug .ini file variable (VLOG), 560 NoIndexCheck .ini file variable, 563 NOMMAP environment variable, 555 non-blocking assignments, 184 NoOthersStaticError .ini file variable, 563 NoRangeCheck .ini file variable, 563 Note .ini file variable, 586 Notepad windows, text editing, 646 -notrigger argument, 347 NoVital .ini file variable, 564 NoVitalCheck .ini file variable, 564 Now simulator state variable, 591 now simulator state variable, 591 numeric_bit package, 132 numeric_std package, 132 disabling warning messages, 588 NumericStdNoWarnings .ini file variable, 576 VHDL subprogram inlining, 139 Optimize_1164 .ini file variable, 564 ordering files for compile, 115 organizing projects with folders, 118 organizing windows, MDI pane, 54 OSCI simulator, differences with vsim, 230 others .ini file variable, 559 overview, simulation tasks, 32

P
packages standard, 131 textio, 131 util, 153 VITAL 1995, 151 VITAL 2000, 151 page setup Dataflow window, 373 Wave window, 340 pan, Dataflow window, 367 panes docking and undocking, 655 Memory panes, 78 parameter support SC instantiating Verilog, 271 SystemC instantiating Verilog, 271 Verilog instantiating SC, 276 Verilog instantiating SystemC, 276 parameters making optional, 547 passing from Verilog to SC, 276 passing to sc_foreign_module (Verilog), 271 using with macros, 546 parameters (Verilog to SC) passing as constructor arguments, 271 passing integer as template arguments, 273 path delay mode, 191 path delays,matching to DEVICE statements, 506 path delays,matching to GLOBALPATHPULSE statements, 506 path delays,matching to IOPATH statements, 505

O
object defined, 41 objects virtual, 309 Objects window, 82 see also windows, Objects window objects, viewable SystemC, 219 observe function, SystemC, 251 observe_foreign_signal() function, 250 OnFinish .ini file variable, 576 operating systems supported, See Installation Guide optimizations
686

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path delays,matching to PATHPULSE statements, 506 pathnames comparisons, 357 hiding in Wave window, 329 PATHPULSE matching to specify path delays, 506 PathSeparator .ini file variable, 577 PedanticErrors .ini file variable, 564 performance cancelling scheduled events, 165 PERIOD matching to Verilog, 508 platforms supported, See Installation Guide PLI loading shared objects with global symbol visibility, 630 specifying which apps to load, 609 Veriuser entry, 609 PLI/VPI, 202 debugging, 431 tracing, 640 PLI/VPI/DPI, 607 registering DPIapplications, 611 specifying the DPI file to load, 629 PLIOBJS environment variable, 555, 609 PORT matching to input ports, 505 port collapsing, toggle coverage, 399 Port driver data, capturing, 524 ports, unnamed, in mixed designs, 266 ports, VHDL and Verilog, 253 Postscript saving a waveform in, 340 saving the Dataflow display in, 371 pragmas, 393 disabling fsm extraction, 415 precedence of variables, 590 precision, simulator resolution, 179, 250 PrefCoverage(DefaultCoverageMode), 400 PrefCoverage(pref_InitFilterFrom), 397 preference variables .ini files, located in, 557 editing, 657 saving, 657 preferences saving, 657 Wave window display, 328 PrefMain(EnableCommandHelp), 52 PrefMain(ShowFilePane) preference variable, 50 PrefMemory(ExpandPackedMem) variable, 79 primitives, symbols in Dataflow window, 373 printing Dataflow window display, 371 waveforms in the Wave window, 340 profile report command, 459 Profiler, 447 %parent fields, 453 clear profile data, 450 enabling memory profiling, 448 enabling statistical sampling, 450 getting started, 448 handling large files, 449 Hierarchical View, 453 interpreting data, 451 memory allocation, 448 memory allocation profiling, 450 profile report command, 459 Profile Report dialog, 461 Ranked View, 452 report option, 459 results, viewing, 451 statistical sampling, 448 Structural View, 454 unsupported on Opteron, 447 view_profile command, 451 viewing profile details, 455 Programming Language Interface, 202, 607 project tab information in, 114 sorting, 115 projects, 107 accessing from the command line, 123 adding files to, 110 benefits, 107 close, 114 code coverage settings, 385 compile order, 115 changing, 115

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
compiler properties in, 120 compiling files, 111 creating, 109 creating simulation configurations, 117 folders in, 118 grouping files in, 116 loading a design, 112 MODELSIM environment variable, 553 open and existing, 114 overview, 107 Protect .ini file variable (VLOG), 560 protect compiler directive, 200 protected types, 157 saving as binary log file, 301 waveforms, viewing, 98 REMOVAL matching to Verilog, 507 report simulator control, 551 simulator state, 551 reporting code coverage, 397 reports fsm extraction, 413 RequireConfigForAllDefaultBinding variable, 564 resolution in SystemC simulation, 216 mixed designs, 250 returning as a real, 153 verilog simulation, 179 VHDL simulation, 142 Resolution .ini file variable, 577 resolution simulator state variable, 591 resource libraries, 131 restart command defaults, 589 toolbar button, 58, 71, 104 results, saving simulations, 301 RetroChannelLimit .ini file variable (SCV), 568 RTL-level design busses reconstructing, 310 RunLength .ini file variable, 577 Runtime Options dialog, 583

Q
quick reference table of simulation tasks, 32 Quiet .ini file variable VCOM, 564 Quiet .ini file variable (VLOG), 561

R
race condition, problems with event order, 182 radix List window, 337 SystemVerilog types, 101, 331 Wave window, 331 range checking, 138 readers and drivers, 365 real type, converting to time, 155 rebuilding supplied libraries, 132 reconstruct RTL-level design busses, 310 RECOVERY matching to Verilog, 507 $recovery, 197 RECREM matching to Verilog, 507 redirecting messages, TranscriptFile, 579 reference region, 354 refreshing library images, 133 regions virtual, 312 registered function calls, 437 registers values of displaying in Objects window, 82
688

S
saveLines preference variable, 51 saving simulation options in a project, 117 waveforms, 301 sc_argc() function, 233 sc_argv() function, 233 sc_clock() functions, moving, 207 sc_cycle() function, 231 sc_fifo, 223 sc_fix and sc_ufix, 233 sc_fixed and sc_ufixed, 233 sc_foreign_module, 280
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sc_foreign_module (Verilog) and parameters, 271 sc_foreign_module (VHDL) and generics, 281 sc_initialize(), removing calls, 231 sc_main() function, 231 sc_main() function, converting, 207 SC_MODULE_EXPORT macro, 207 sc_signed and sc_unsigned, 233 sc_start() function, 231 sc_start() function, replacing in SystemC, 231 sc_start(), replacing, 207 sc_stop() behavior of, 233 behavior, customizing, 576 scaling fonts, 47 sccom using sccom vs. raw C++ compiler, 212 sccom -link command, 215, 287 sccomLogfile .ini file variable (sccom), 568 sccomVerbose .ini file variable (sccom), 568 scgenmod, using, 269, 279 ScTimeUnit .ini file variable, 577 ScvPhaseRelationName .ini variable (SCV), 568 SDF disabling timing checks, 511 errors and warnings, 501 instance specification, 500 interconnect delays, 510 mixed VHDL and Verilog designs, 510 specification with the GUI, 500 troubleshooting, 511 Verilog $sdf_annotate system task, 504 optional conditions, 509 optional edge specifications, 508 rounded timing values, 510 SDF to Verilog construct matching, 505 VHDL resolving errors, 502 SDF to VHDL generic matching, 501 SDF DEVICE matching to Verilog constructs, 506 SDF GLOBALPATHPULSE matching to Verilog constructs, 506 SDF HOLD matching to Verilog constructs, 506 SDF INTERCONNECT matching to Verilog constructs, 505 SDF IOPATH matching to Verilog constructs, 505 SDF NOCHANGE matching to Verilog constructs, 508 SDF PATHPULSE matching to Verilog constructs, 506 SDF PERIOD matching to Verilog constructs, 508 SDF PORT matching to Verilog constructs, 505 SDF RECOVERY matching to Verilog constructs, 507 SDF RECREM matching to Verilog constructs, 507 SDF REMOVAL matching to Verilog constructs, 507 SDF SETUPHOLD matching to Verilog constructs, 507 SDF SKEW matching to Verilog constructs, 507 SDF WIDTH matching to Verilog constructs, 508 $sdf_done, 196 searching Expression Builder, 326 Verilog libraries, 172, 268 sensitivity list warning, 600 set simulator control with GUI, 583 SETUP matching to Verilog, 506 SETUPHOLD matching to Verilog, 507 $setuphold, 197 severity, changing level for errors, 596 shared library building in SystemC, 215 shared objects loading FLI applications see FLI Reference manual loading PLI/VPI/DPI C applications, 616

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
loading PLI/VPI/DPI C++ applications, 623 loading with global symbol visibility, 630 Shortcuts text editing, 646 shortcuts command history, 645 command line caveat, 645 List window, 649 Main window, 646 Source window, 646 Wave window, 650 show drivers Dataflow window, 365 Wave window, 347 Show_ WarnMatchCadence .ini file variable, 561 Show_BadOptionWarning .ini file variable, 561 Show_Lint .ini file variable VCOM, 564 Show_Lint .ini file variable (VLOG), 561 Show_source .ini file variable VCOM, 565 Show_source .ini file variable (VLOG), 561 Show_VitalChecksOpt .ini file variable, 565 Show_VitalChecksWarning .ini file variable, 565 Show_WarnCantDoCoverage .ini file variable, 561 Show_WarnCantDoCoverage variable, 565 Show_Warning1 .ini file variable, 565 Show_Warning10 .ini file variable, 566 Show_Warning2 .ini file variable, 565 Show_Warning3 .ini file variable, 566 Show_Warning4 .ini file variable, 566 Show_Warning5 .ini file variable, 566 Show_Warning9 .ini file variable, 566 Show_WarnLocallyStaticError variable, 566 ShowUnassociatedScNameWarning variable, 578 ShowUndebuggableScTypeWarning variable, 578 signal groups in wave window, 334 signal interaction Verilog and SystemC, 256 Signal Spy, 154, 469 disable, 465, 476 enable, 466, 477 $signal_force, 482 signal_force, 154, 472 $signal_release, 484 signal_release, 154, 474 signals combining into a user-defined bus, 341 dashed, 102 Dataflow window, displaying in, 71, 363 driving in the hierarchy, 467 filtering in the Objects window, 82 hierarchy driving in, 467, 478 referencing in, 154, 469, 480 releasing anywhere in, 474 releasing in, 154, 484 sampling at a clock change, 347 transitions, searching for, 322 types, selecting which to view, 82 values of displaying in Objects window, 82 forcing anywhere in the hierarchy, 154, 472, 482 saving as binary log file, 301 virtual, 310 waveforms, viewing, 98 simulating batch mode, 37 command-line mode, 37 comparing simulations, 301 default run length, 583 iteration limit, 584 mixed language designs compilers, 249 libraries, 249 resolution limit in, 250 mixed Verilog and SystemC designs channel and port type mapping, 256 SystemC sc_signal data type mapping, 257 Verilog port direction, 258

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Verilog state mapping, 258 mixed Verilog and VHDL designs Verilog parameters, 253 Verilog state mapping, 254 VHDL and Verilog ports, 253 VHDL generics, 255 mixed VHDL and SystemC designs SystemC state mapping, 263 VHDL port direction, 263 VHDL port type mapping, 260 VHDL sc_signal data type mapping, 261 saving dataflow display as a Postscript file, 371 saving options in a project, 117 saving simulations, 301 saving waveform as a Postscript file, 340 SystemC, 203, 215 usage flow for SystemC only, 205 Verilog, 179 delay modes, 190 hazard detection, 186 resolution limit, 179 XL compatible simulator options, 188 VHDL, 142 viewing results in List pane, 75 viewing results in List window, 316 VITAL packages, 152 simulating the design, overview, 36 simulation basic steps for, 33 Simulation Configuration creating, 117 simulation task overview, 32 simulations event order in, 182 saving results, 301 saving results at intervals, 308 simulator control with .ini variables, 583 simulator resolution mixed designs, 250 returning as a real, 153 SystemC, 216 Verilog, 179 VHDL, 142 simulator state variables, 590 simulator, difference from OSCI, 230 sizetf callback function, 634 SKEW matching to Verilog, 507 sm_entity, 668 SmartModels creating foreign architectures with sm_entity, 668 invoking SmartModel specific commands, 672 linking to, 667 lmcwin commands, 673 memory arrays, 674 Verilog interface, 674 VHDL interface, 667 so, shared object file loading PLI/VPI/DPI C applications, 616 loading PLI/VPI/DPI C++ applications, 623 Source annotation Annotation, 90 source annotation, 90 source code pragmas, 393 source code, security, 134, 200 source files Debug, 90 source files, referencing with location maps, 593 source files, specifying with location maps, 593 source highlighting, customizing, 94 source libraries arguments supporting, 175 Source window, 87 code coverage data, 388 colorization, 94 tab stops in, 94 see also windows, Source window source-level debug SystemC, enabling, 220 specify path delays matching to DEVICE construct, 506 matching to GLOBALPATHPULSE construct, 506

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
matching to IOPATH statements, 505 matching to PATHPULSE construct, 506 Standard Developers Kit User Manual, 43 standards supported, 39 start_of_simulation() function, 232 startup environment variables access during, 662 files accessed during, 661 macro in the modelsim.ini file, 578 macros, 588 startup macro in command-line mode, 37 using a startup file, 588 Startup .ini file variable, 578 state variables, 590 statistical sampling profiler, 448 status bar Main window, 56 Status field Project tab, 114 std .ini file variable, 558 std_arith package disabling warning messages, 588 std_developerskit .ini file variable, 558 std_logic_arith package, 132 std_logic_signed package, 132 std_logic_textio, 132 std_logic_unsigned package, 132 StdArithNoWarnings .ini file variable, 579 STDOUT environment variable, 555 steps for simulation, overview, 33 struct of sc_signal<T>, 222 subprogram inlining, 139 subprogram write is ambiguous error, fixing, 148 Support, 43 Suppress .ini file variable, 586 sv_std .ini file variable, 558 symbol mapping Dataflow window, 373 symbolic link to design libraries (UNIX), 130 synopsys .ini file variable, 558 Synopsys libraries, 132 syntax highlighting, 94 synthesis rule compliance checking, 562 system calls VCD, 520 Verilog, 191 system commands, 537 system tasks proprietary, 195 VCD, 520 Verilog, 191 Verilog-XL compatible, 196 SystemC aggregates of signals/ports, 222 calling member import functions in SC scope, 242 cin support, 231 compiling for source level debug, 211 compiling optimized code, 210 component declaration for instantiation, 286 construction parameters, 233 control function, 251 converting sc_main(), 207 declaring/calling member import functions in SV, 242 exporting sc_main, example, 208 exporting top level module, 207 fixed-point types, 233 foreign module declaration, 269 generic support, instantiating VHDL, 280 hierarchical references in mixed designs, 251 instantiation criteria in Verilog design, 276 instantiation criteria in VHDL design, 285 linking the compiled source, 215 maintaining design portability, 211 mapping states in mixed designs, 263 VHDL, 263 mixed designs with Verilog, 249 mixed designs with VHDL, 249 observe function, 251 parameter support, Verilog instances, 271 prim channel aggregates, 222 reducing non-debug compile time, 211 replacing sc_start(), 207 sc_clock(), moving to SC_CTOR, 207 sc_fifo, 223

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
simulating, 215 source code, modifying for vsim, 207 stack space for threads, 235 state-based code, initializing and cleanup, 217 troubleshooting, 235 unsupported functions, 231 user defined signals and ports, viewable, 219 viewable objects, 219 viewable types, 218 viewable/debuggable objects, 219 viewing FIFOs, 223 virtual functions, 217 SystemC modules exporting for use in Verilog, 276 exporting for use in VHDL, 286 SystemVerilog keyword considerations, 168 multi-file compilation, 173 suppported implementation details, 39 SystemVerilog DPI specifying the DPI file to load, 629 SystemVerilog types radix, 101, 331 passing integer generics as, 283 passing integer parameters as, 273 testbench, accessing internal objectsfrom, 463 text and command syntax, 42 Text editing, 646 TEXTIO buffer, flushing, 150 TextIO package alternative I/O files, 150 containing hexadecimal numbers, 149 dangling pointers, 149 ENDFILE function, 150 ENDLINE function, 150 file declaration, 147 implementation issues, 148 providing stimulus, 151 standard input, 148 standard output, 148 WRITE procedure, 148 WRITE_STRING procedure, 149 TF routines, 639 TFMPC explanation, 601 time measuring in Wave window, 318 resolution in SystemC, 216 time resolution as a simulator state variable, 591 time collapsing, 309 time resolution in mixed designs, 250 in Verilog, 179 in VHDL, 142 time type converting to real, 154 time unit in SystemC, 216 timeline display clock cycles, 329 timescale directive warning investigating, 180 timing $setuphold/$recovery, 197 differences shown by comparison, 358 disabling checks, 511

T
tab groups, 54 tab stops Source window, 94 Tcl, ?? to 541 command separator, 536 command substitution, 535 command syntax, 532 evaluation order, 536 history shortcuts, 645 preference variables, 657 relational expression evaluation, 536 time commands, 539 variable substitution, 537 VSIM Tcl commands, 538 Tcl_init error message, 600 Technical support and updates, 43 temp files, VSOUT, 557 template arguments
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negative check limits described, 187 TMPDIR environment variable, 555 to_real VHDL function, 154 to_time VHDL function, 155 toggle coverage, 390 excluding bus bits, 395 excluding enum signals, 395 max VHDL integer values, 579 port collapsing, 399 reporting, duplication of elements, 399 reporting, ordering of nodes, 399 viewing in Signals window, 390 tolerance leading edge, 356 trailing edge, 356 too few port connections, explanation, 601 tool structure, 31 toolbar Dataflow window, 73 Main window, 57 tracing events, 368 source of unknown, 369 transcript disable file creation, 51, 588 file name, specifed in modelsim.ini, 587 saving, 51 using as a DO file, 51 Transcript window changing buffer size, 51 changing line count, 51 TranscriptFile .ini file variable, 579 triggers, in the List window, 345 triggers, in the List window, setting, 343 troubleshooting DPI, missing import funtion, 642 SystemC, 235 unexplained behaviors, SystemC, 235 TSSI in VCD files, 524 type converting real to time, 155 converting time to real, 154 Type field, Project tab, 114 types virtual, 312 types, fixed-point in SystemC, 231 types, viewable SystemC, 218

U
UCDB, 377 purpose, 378 UCDBFilename .ini file variable, 579 UnbufferedOutput .ini file variable, 579 undefined symbol, error, 236 unexplained behavior during simulation, 235 unexplained simulation behavior, 235 ungrouping in wave window, 336 ungrouping objects, Monitor window, 97 unit delay mode, 191 unknowns, tracing, 369 unnamed ports, in mixed designs, 266 unsupported functions in SystemC, 231 use clause, specifying a library, 131 use flow Code Coverage, 383 DPI, 612 SystemC-only designs, 205 UseCsupV2 .ini file variable, 580 user-defined bus, 309, 341 UserTimeUnit .ini file variable, 580 UseScv .ini file variable (sccom), 568 util package, 153

V
values of HDL items, 94 variables, 583 environment, 551 expanding environment variables, 551 LM_LICENSE_FILE, 553 precedence between .ini and .tcl, 590 setting environment variables, 552 simulator state variables current settings report, 551 iteration number, 590 name of entity or module as a variable, 590 resolution, 590
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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
simulation time, 590 values of displaying in Objects window, 82 saving as binary log file, 301 VCD files capturing port driver data, 524 case sensitivity, 516 creating, 515 dumpports tasks, 519 exporting created waveforms, 495 from VHDL source to VCD output, 520 stimulus, using as, 516 supported TSSI states, 524 VCD system tasks, 520 vcom enabling code coverage, 385 vcover utility, 380 Verilog ACC routines, 637 capturing port driver data with -dumpports, 524 cell libraries, 190 compiler directives, 199 compiling and linking PLI C applications, 616 compiling and linking PLI C++ applications, 623 compiling design units, 168 compiling with XL uselib compiler directive, 175 component declaration, 265 configurations, 177 DPI access routines, 639 event order in simulation, 182 generate statements, 178 instantiation criteria in mixed-language design, 264 instantiation criteria in SystemC design, 269 instantiation of VHDL design units, 267 language templates, 91 library usage, 172 mapping states in mixed designs, 254 mapping states in SystemC designs, 258 mixed designs with SystemC, 249 mixed designs with VHDL, 249 parameter support, instantiating SystemC, 276 parameters, 253 port direction, 258 sc_signal data type mapping, 257 SDF annotation, 502 sdf_annotate system task, 502 simulating, 179 delay modes, 190 XL compatible options, 188 simulation hazard detection, 186 simulation resolution limit, 179 SmartModel interface, 674 source code viewing, 87 standards, 39 system tasks, 191 TF routines, 639 to SystemC, channel and port type mapping, 256 XL compatible compiler options, 174 XL compatible routines, 640 XL compatible system tasks, 196 verilog .ini file variable, 558 Verilog 2001 disabling support, 562 Verilog PLI/VP/DPII registering VPI applications, 609 Verilog PLI/VPI 64-bit support in the PLI, 640 debugging PLI/VPI code, 641 Verilog PLI/VPI/DPI compiling and linking PLI/VPI C++ applications, 623 compiling and linking PLI/VPI/CPI C applications, 616 PLI callback reason argument, 632 PLI support for VHDL objects, 635 registering PLI applications, 608 specifying the PLI/VPI file to load, 629 Verilog-XL compatibility with, 167, 607 Veriuser .ini file variable, 580, 609 Veriuser, specifying PLI applications, 609 veriuser.c file, 635

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
VHDL compiling design units, 137 creating a design library, 137 delay file opening, 589 dependency checking, 138 file opening delay, 589 instantiation criteria in SystemC design, 279 instantiation from Verilog, 267 instantiation of Verilog, 253 language templates, 91 language versions, 139 library clause, 131 mixed designs with SystemC, 249 mixed designs with Verilog, 249 object support in PLI, 635 optimizations inlining, 139 port direction, 263 port type mapping, 260 sc_signal data type mapping, 261 simulating, 142 SmartModel interface, 667 source code viewing, 87 standards, 39 timing check disabling, 142 VITAL package, 132 VHDL utilities, 153, 154, 469, 480 get_resolution(), 153 to_real(), 154 to_time(), 155 VHDL-1987, compilation problems, 139 VHDL-1993, enabling support for, 567 VHDL-2002, enabling support for, 567 VHDL93 .ini file variable, 567 view_profile command, 451 viewing, 52 library contents, 127 waveforms, 301 viewing FIFOs, 223 virtual compare signal, restrictions, 341 virtual functions in SystemC, 217 virtual hide command, 310 virtual objects, 309 virtual functions, 311 virtual regions, 312 virtual signals, 310 virtual types, 312 virtual region command, 312 virtual regions reconstruct RTL hierarchy, 312 virtual save command, 311 virtual signal command, 310 virtual signals reconstruct RTL-level design busses, 310 reconstruct the original RTL hierarchy, 310 virtual hide command, 310 visibility of declarations in $unit, 173 VITAL compiling and simulating with accelerated VITAL packages, 152 disabling optimizations for debugging, 152 specification and source code, 151 VITAL packages, 152 vital95 .ini file variable, 559 vlog enabling code coverage, 385 vlog95compat .ini file variable, 562 VPI, registering applications, 609 VPI/PLI, 202 VPI/PLI/DPI, 607 compiling and linking C applications, 616 compiling and linking C++ applications, 623 VSIM license lost, 602 VSIM prompt, returning to, 576 vsim, differences with OSCI simulator, 230 VSOUT temp file, 557

W
WarnConstantChange .ini file variable, 580 Warning .ini file variable, 586 warnings empty port name, 599 exit codes, 597 getting more information, 596 messages, long description, 596 metavalue detected, 600 severity level, changing, 596

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
suppressing VCOM warning messages, 596 suppressing VLOG warning messages, 597 suppressing VSIM warning messages, 597 Tcl initialization error 2, 600 too few port connections, 601 turning off warnings from arithmetic packages, 588 waiting for lock, 600 watching a signal value, 96 wave groups, 334 add items to existing, 336 creating, 334 deleting, 336 drag from Wave to List, 336 drag from Wave to Transcript, 336 removing items from existing, 336 ungrouping, 336 Wave Log Format (WLF) file, 301 wave log format (WLF) file see also WLF files wave viewer, Dataflow window, 366 Wave window, 98, 314 compare waveforms, 357 docking and undocking, 98, 314 in the Dataflow window, 366 saving layout, 339 timeline display clock cycles, 329 values column, 359 see also windows, Wave window wave window dashed signal lines, 102 Waveform Compare adding clocks, 355 adding regions, 354 adding signals, 353 annotating differences, 359 clocked comparison, 356 compare by region, 354 compare by signal, 353 compare options, 356 compare tab, 352 comparison commands, 351 comparison method, 355 differences in text format, 360 flattened designs, 361 hierarchical designs, 361 icons, 359 initiating with GUI, 352 introduction, 349 leading edge tolerance, 356 list window display, 360 mixed-language support, 349 pathnames, 357 reference dataset, 352 reference region, 354 saving and reloading, 361 setup options, 350 signals with different names, 351 test dataset, 352 timing differences, 358 trailing edge tolerance, 356 using comparison wizard, 350 using the GUI, 351 values column, 359 wave window display, 357 Waveform Comparison created waveforms, using with, 496 difference markers, 358 waveform editor creating waveforms, 489 editing waveforms, 490 mapping signals, 496 saving stimulus files, 494 simulating, 494 Waveform Compare, using with, 496 waveform logfile overview, 301 see also WLF files waveforms, 301 optimize viewing of, 581 viewing, 98 WaveSignalNameWidth .ini file variable, 580 WIDTH matching to Verilog, 508 windows Active Processes pane, 60 code coverage statistics, 386 Dataflow window, 71, 363

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A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
toolbar, 73 zooming, 367 List window, 75, 316 display properties of, 337 formatting HDL items, 337 saving data to a file, 340 setting triggers, 343, 345 Locals window, 77 Main window, 48 status bar, 56 text editing, 646 time and delta display, 56 toolbar, 57 Memory window, 78 monitor, 96 Objects window, 82 Signals window VHDL and Verilog items viewed in, 82 Source window, 87 text editing, 646 viewing HDL source code, 87 Variables window VHDL and Verilog items viewed in, 77 Wave window, 98, 314 adding HDL items to, 317 cursor measurements, 318 display preferences, 328 display range (zoom), changing, 322 format file, saving, 339 path elements, changing, 580 time cursors, 318 zooming, 322 WLF file parameters cache size, 304 collapse mode, 304 compression, 303 delete on quit, 304 filename, 303 optimization, 303 overview, 303 size limit, 303 time limit, 303 WLF files collapsing events, 309 optimizing waveform viewing, 581 saving, 302 saving at intervals, 308 WLFCacheSize .ini file variable, 581 WLFCollapseMode .ini file variable, 581 WLFCompress .ini variable, 581 WLFDeleteOnQuit .ini variable, 581 WLFFilename .ini file variable, 581 WLFSaveAllRegions .ini variable, 582 WLFSizeLimit .ini variable, 582 WLFTimeLimit .ini variable, 582 work library, 126 creating, 127 workspace, 49 code coverage, 63 Files tab, 63 WRITE procedure, problems with, 148

X
X tracing unknowns, 369 .Xdefaults file, controlling fonts, 48 xml format coverage reports, 401 X-session controlling fonts, 48

Z
zero delay elements, 144 zero delay mode, 191 zero-delay loop, infinite, 146 zero-delay oscillation, 146 zero-delay race condition, 182 zoom Dataflow window, 367 saving range with bookmarks, 323 zooming window panes, 656

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Third-Party Information
This section provides information on third-party software that may be included in the ModelSim LE/PE product, including any additional license terms. This product may include Valgrind third-party software. Julian Seward. All rights reserved. THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. This product may use MinGW GCC third-party software. Red Hat, Inc. All rights reserved. Pipeline Associates, Inc. All rights reserved. Matthew Self. All rights reserved. National Research Council of Canada. All rights reserved. The Regents of the University of California. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Free Software Foundation, Inc. All rights reserved. Refer to the license file in your install directory: <install_directory>/docs/legal/mingw_gcc.pdf This software application may include GNU GCC third-party software. AT&T. All rights reserved. Permission to use, copy, modify, and distribute this software for any purpose without fee is hereby granted, provided that this entire notice is included in all copies of any software which is or includes a copy or modification of this software and in all copies of the supporting documentation for such software. THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. Refer to the license file in your install directory:

<install_directory>/docs/legal/gnu_gcc.pdf This software application may include GNU GCC third-party software. Doug Bell. All Rights Reserved. THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Refer to the license file in your install directory: <install_directory>/docs/legal/gnu_gcc.pdf This software application may include GNU third-party software distributed by The Free Software Foundation. Free Software Foundation. To view a copy of the GNU GPL, LGPL, Library, and Documentation licenses, refer to: http://www.fsf.org/licensing/licenses. Refer to the license file in your install directory: <install_directory>/docs/legal/gnu_gcc.pdf This software application may include GNU GCC third-party software. The Regents of the University of California. All rights reserved. THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. Refer to the license file in your install directory: <install_directory>/docs/legal/gnu_gcc.pdf This product may include freeWrap open source software Dennis R. LaBelle All Rights Reserved. Disclaimer of warranty: Licensor provides the software on an ``as is'' basis. Licensor does not warrant, guarantee, or make any representations regarding the use or results of the software with respect to it correctness, accuracy, reliability or performance. The entire risk of the use and performance of the software is assumed by licensee. ALL WARANTIES INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR MERCHANTABILITY ARE HEREBY EXCLUDED. This software application may include MinGW GNU diffutils version 2.7 third-party software.

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End-User License Agreement

The latest version of the End-User License Agreement is available on-line at: www.mentor.com/terms_conditions/enduser.cfm IMPORTANT INFORMATION USE OF THIS SOFTWARE IS SUBJECT TO LICENSE RESTRICTIONS. CAREFULLY READ THIS LICENSE AGREEMENT BEFORE USING THE SOFTWARE. USE OF SOFTWARE INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE OF THE TERMS AND CONDITIONS SET FORTH IN THIS AGREEMENT. ANY ADDITIONAL OR DIFFERENT PURCHASE ORDER TERMS AND CONDITIONS SHALL NOT APPLY.

END-USER LICENSE AGREEMENT (Agreement) This is a legal agreement concerning the use of Software between you, the end user, as an authorized representative of the company acquiring the license, and Mentor Graphics Corporation and Mentor Graphics (Ireland) Limited acting directly or through their subsidiaries (collectively Mentor Graphics). Except for license agreements related to the subject matter of this license agreement which are physically signed by you and an authorized representative of Mentor Graphics, this Agreement and the applicable quotation contain the parties' entire understanding relating to the subject matter and supersede all prior or contemporaneous agreements. If you do not agree to these terms and conditions, promptly return or, if received electronically, certify destruction of Software and all accompanying items within five days after receipt of Software and receive a full refund of any license fee paid. 1. GRANT OF LICENSE. The software programs, including any updates, modifications, revisions, copies, documentation and design data (Software), are copyrighted, trade secret and confidential information of Mentor Graphics or its licensors who maintain exclusive title to all Software and retain all rights not expressly granted by this Agreement. Mentor Graphics grants to you, subject to payment of appropriate license fees, a nontransferable, nonexclusive license to use Software solely: (a) in machine-readable, object-code form; (b) for your internal business purposes; (c) for the license term; and (d) on the computer hardware and at the site authorized by Mentor Graphics. A site is restricted to a one-half mile (800 meter) radius. Mentor Graphics standard policies and programs, which vary depending on Software, license fees paid or services purchased, apply to the following: (a) relocation of Software; (b) use of Software, which may be limited, for example, to execution of a single session by a single user on the authorized hardware or for a restricted period of time (such limitations may be technically implemented through the use of authorization codes or similar devices); and (c) support services provided, including eligibility to receive telephone support, updates, modifications, and revisions. EMBEDDED SOFTWARE. If you purchased a license to use embedded software development (ESD) Software, if applicable, Mentor Graphics grants to you a nontransferable, nonexclusive license to reproduce and distribute executable files created using ESD compilers, including the ESD run-time libraries distributed with ESD C and C++ compiler Software that are linked into a composite program as an integral part of your compiled computer program, provided that you distribute these files only in conjunction with your compiled computer program. Mentor Graphics does NOT grant you any right to duplicate, incorporate or embed copies of Mentor Graphics' real-time operating systems or other embedded software products into your products or applications without first signing or otherwise agreeing to a separate agreement with Mentor Graphics for such purpose. BETA CODE. Software may contain code for experimental testing and evaluation (Beta Code), which may not be used without Mentor Graphics explicit authorization. Upon Mentor Graphics authorization, Mentor Graphics grants to you a temporary, nontransferable, nonexclusive license for experimental use to test and evaluate the Beta Code without charge for a limited period of time specified by Mentor Graphics. This grant and your use of the Beta Code shall not be construed as marketing or offering to sell a license to the Beta Code, which Mentor Graphics may choose not to release commercially in any form. If Mentor Graphics authorizes you to use the Beta Code, you agree to evaluate and test the Beta Code under normal conditions as directed by Mentor Graphics. You will contact Mentor Graphics periodically during your use of the Beta Code to discuss any malfunctions or suggested improvements. Upon completion of your evaluation and testing, you will send to Mentor Graphics a written evaluation of the Beta Code, including its strengths, weaknesses and recommended improvements. You agree that any written evaluations and all inventions, product improvements, modifications or developments that Mentor Graphics conceived or made during or subsequent to this Agreement, including those based partly or wholly on your feedback, will be the exclusive property of Mentor Graphics. Mentor Graphics will have exclusive rights, title and interest in all such property. The provisions of this section 3 shall survive the termination or expiration of this Agreement.

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RESTRICTIONS ON USE. You may copy Software only as reasonably necessary to support the authorized use. Each copy must include all notices and legends embedded in Software and affixed to its medium and container as received from Mentor Graphics. All copies shall remain the property of Mentor Graphics or its licensors. You shall maintain a record of the number and primary location of all copies of Software, including copies merged with other software, and shall make those records available to Mentor Graphics upon request. You shall not make Software available in any form to any person other than employees and on-site contractors, excluding Mentor Graphics' competitors, whose job performance requires access and who are under obligations of confidentiality. You shall take appropriate action to protect the confidentiality of Software and ensure that any person permitted access to Software does not disclose it or use it except as permitted by this Agreement. Except as otherwise permitted for purposes of interoperability as specified by applicable and mandatory local law, you shall not reverse-assemble, reverse-compile, reverse-engineer or in any way derive from Software any source code. You may not sublicense, assign or otherwise transfer Software, this Agreement or the rights under it, whether by operation of law or otherwise (attempted transfer), without Mentor Graphics prior written consent and payment of Mentor Graphics then-current applicable transfer charges. Any attempted transfer without Mentor Graphics' prior written consent shall be a material breach of this Agreement and may, at Mentor Graphics' option, result in the immediate termination of the Agreement and licenses granted under this Agreement. The terms of this Agreement, including without limitation, the licensing and assignment provisions shall be binding upon your successors in interest and assigns. The provisions of this section 4 shall survive the termination or expiration of this Agreement. LIMITED WARRANTY. 5.1. Mentor Graphics warrants that during the warranty period Software, when properly installed, will substantially conform to the functional specifications set forth in the applicable user manual. Mentor Graphics does not warrant that Software will meet your requirements or that operation of Software will be uninterrupted or error free. The warranty period is 90 days starting on the 15th day after delivery or upon installation, whichever first occurs. You must notify Mentor Graphics in writing of any nonconformity within the warranty period. This warranty shall not be valid if Software has been subject to misuse, unauthorized modification or improper installation. MENTOR GRAPHICS' ENTIRE LIABILITY AND YOUR EXCLUSIVE REMEDY SHALL BE, AT MENTOR GRAPHICS' OPTION, EITHER (A) REFUND OF THE PRICE PAID UPON RETURN OF SOFTWARE TO MENTOR GRAPHICS OR (B) MODIFICATION OR REPLACEMENT OF SOFTWARE THAT DOES NOT MEET THIS LIMITED WARRANTY, PROVIDED YOU HAVE OTHERWISE COMPLIED WITH THIS AGREEMENT. MENTOR GRAPHICS MAKES NO WARRANTIES WITH RESPECT TO: (A) SERVICES; (B) SOFTWARE WHICH IS LICENSED TO YOU FOR A LIMITED TERM OR LICENSED AT NO COST; OR (C) EXPERIMENTAL BETA CODE; ALL OF WHICH ARE PROVIDED AS IS. 5.2. THE WARRANTIES SET FORTH IN THIS SECTION 5 ARE EXCLUSIVE. NEITHER MENTOR GRAPHICS NOR ITS LICENSORS MAKE ANY OTHER WARRANTIES, EXPRESS, IMPLIED OR STATUTORY, WITH RESPECT TO SOFTWARE OR OTHER MATERIAL PROVIDED UNDER THIS AGREEMENT. MENTOR GRAPHICS AND ITS LICENSORS SPECIFICALLY DISCLAIM ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT OF INTELLECTUAL PROPERTY.

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LIMITATION OF LIABILITY. EXCEPT WHERE THIS EXCLUSION OR RESTRICTION OF LIABILITY WOULD BE VOID OR INEFFECTIVE UNDER APPLICABLE LAW, IN NO EVENT SHALL MENTOR GRAPHICS OR ITS LICENSORS BE LIABLE FOR INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES (INCLUDING LOST PROFITS OR SAVINGS) WHETHER BASED ON CONTRACT, TORT OR ANY OTHER LEGAL THEORY, EVEN IF MENTOR GRAPHICS OR ITS LICENSORS HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. IN NO EVENT SHALL MENTOR GRAPHICS' OR ITS LICENSORS' LIABILITY UNDER THIS AGREEMENT EXCEED THE AMOUNT PAID BY YOU FOR THE SOFTWARE OR SERVICE GIVING RISE TO THE CLAIM. IN THE CASE WHERE NO AMOUNT WAS PAID, MENTOR GRAPHICS AND ITS LICENSORS SHALL HAVE NO LIABILITY FOR ANY DAMAGES WHATSOEVER. THE PROVISIONS OF THIS SECTION 6 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS AGREEMENT. LIFE ENDANGERING ACTIVITIES. NEITHER MENTOR GRAPHICS NOR ITS LICENSORS SHALL BE LIABLE FOR ANY DAMAGES RESULTING FROM OR IN CONNECTION WITH THE USE OF SOFTWARE IN ANY APPLICATION WHERE THE FAILURE OR INACCURACY OF THE SOFTWARE MIGHT RESULT IN DEATH OR PERSONAL INJURY. THE PROVISIONS OF THIS SECTION 7 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS AGREEMENT. INDEMNIFICATION. YOU AGREE TO INDEMNIFY AND HOLD HARMLESS MENTOR GRAPHICS AND ITS LICENSORS FROM ANY CLAIMS, LOSS, COST, DAMAGE, EXPENSE, OR LIABILITY, INCLUDING ATTORNEYS' FEES, ARISING OUT OF OR IN CONNECTION WITH YOUR USE OF SOFTWARE AS

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DESCRIBED IN SECTION 7. THE PROVISIONS OF THIS SECTION 8 SHALL SURVIVE THE EXPIRATION OR TERMINATION OF THIS AGREEMENT. 9. INFRINGEMENT. 9.1. Mentor Graphics will defend or settle, at its option and expense, any action brought against you alleging that Software infringes a patent or copyright or misappropriates a trade secret in the United States, Canada, Japan, or member state of the European Patent Office. Mentor Graphics will pay any costs and damages finally awarded against you that are attributable to the infringement action. You understand and agree that as conditions to Mentor Graphics' obligations under this section you must: (a) notify Mentor Graphics promptly in writing of the action; (b) provide Mentor Graphics all reasonable information and assistance to defend or settle the action; and (c) grant Mentor Graphics sole authority and control of the defense or settlement of the action. 9.2. If an infringement claim is made, Mentor Graphics may, at its option and expense: (a) replace or modify Software so that it becomes noninfringing; (b) procure for you the right to continue using Software; or (c) require the return of Software and refund to you any license fee paid, less a reasonable allowance for use. 9.3. Mentor Graphics has no liability to you if infringement is based upon: (a) the combination of Software with any product not furnished by Mentor Graphics; (b) the modification of Software other than by Mentor Graphics; (c) the use of other than a current unaltered release of Software; (d) the use of Software as part of an infringing process; (e) a product that you make, use or sell; (f) any Beta Code contained in Software; (g) any Software provided by Mentor Graphics licensors who do not provide such indemnification to Mentor Graphics customers; or (h) infringement by you that is deemed willful. In the case of (h) you shall reimburse Mentor Graphics for its attorney fees and other costs related to the action upon a final judgment. 9.4. THIS SECTION IS SUBJECT TO SECTION 6 ABOVE AND STATES THE ENTIRE LIABILITY OF MENTOR GRAPHICS AND ITS LICENSORS AND YOUR SOLE AND EXCLUSIVE REMEDY WITH RESPECT TO ANY ALLEGED PATENT OR COPYRIGHT INFRINGEMENT OR TRADE SECRET MISAPPROPRIATION BY ANY SOFTWARE LICENSED UNDER THIS AGREEMENT. 10. TERM. This Agreement remains effective until expiration or termination. This Agreement will immediately terminate upon notice if you exceed the scope of license granted or otherwise fail to comply with the provisions of Sections 1, 2, or 4. For any other material breach under this Agreement, Mentor Graphics may terminate this Agreement upon 30 days written notice if you are in material breach and fail to cure such breach within the 30 day notice period. If Software was provided for limited term use, this Agreement will automatically expire at the end of the authorized term. Upon any termination or expiration, you agree to cease all use of Software and return it to Mentor Graphics or certify deletion and destruction of Software, including all copies, to Mentor Graphics reasonable satisfaction. 11. EXPORT. Software is subject to regulation by local laws and United States government agencies, which prohibit export or diversion of certain products, information about the products, and direct products of the products to certain countries and certain persons. You agree that you will not export any Software or direct product of Software in any manner without first obtaining all necessary approval from appropriate local and United States government agencies. 12. RESTRICTED RIGHTS NOTICE. Software was developed entirely at private expense and is commercial computer software provided with RESTRICTED RIGHTS. Use, duplication or disclosure by the U.S. Government or a U.S. Government subcontractor is subject to the restrictions set forth in the license agreement under which Software was obtained pursuant to DFARS 227.7202-3(a) or as set forth in subparagraphs (c)(1) and (2) of the Commercial Computer Software - Restricted Rights clause at FAR 52.227-19, as applicable. Contractor/manufacturer is Mentor Graphics Corporation, 8005 SW Boeckman Road, Wilsonville, Oregon 97070-7777 USA. 13. THIRD PARTY BENEFICIARY. For any Software under this Agreement licensed by Mentor Graphics from Microsoft or other licensors, Microsoft or the applicable licensor is a third party beneficiary of this Agreement with the right to enforce the obligations set forth herein. 14. AUDIT RIGHTS. You will monitor access to, location and use of Software. With reasonable prior notice and during your normal business hours, Mentor Graphics shall have the right to review your software monitoring system and reasonably relevant records to confirm your compliance with the terms of this Agreement, an addendum to this Agreement or U.S. or other local export laws. Such review may include FLEXlm or FLEXnet report log files that you shall capture and provide at Mentor Graphics request. Mentor Graphics shall treat as confidential information all of your information gained as a result of any request or review and shall only use or disclose such information as required by law or to enforce its rights under this Agreement or addendum to this Agreement. The provisions of this section 14 shall survive the expiration or termination of this Agreement.

15. CONTROLLING LAW, JURISDICTION AND DISPUTE RESOLUTION. THIS AGREEMENT SHALL BE GOVERNED BY AND CONSTRUED UNDER THE LAWS OF THE STATE OF OREGON, USA, IF YOU ARE LOCATED IN NORTH OR SOUTH AMERICA, AND THE LAWS OF IRELAND IF YOU ARE LOCATED OUTSIDE OF NORTH OR SOUTH AMERICA. All disputes arising out of or in relation to this Agreement shall be submitted to the exclusive jurisdiction of Portland, Oregon when the laws of Oregon apply, or Dublin, Ireland when the laws of Ireland apply. Notwithstanding the foregoing, all disputes in Asia (except for Japan) arising out of or in relation to this Agreement shall be resolved by arbitration in Singapore before a single arbitrator to be appointed by the Chairman of the Singapore International Arbitration Centre (SIAC) to be conducted in the English language, in accordance with the Arbitration Rules of the SIAC in effect at the time of the dispute, which rules are deemed to be incorporated by reference in this section 15. This section shall not restrict Mentor Graphics right to bring an action against you in the jurisdiction where your place of business is located. The United Nations Convention on Contracts for the International Sale of Goods does not apply to this Agreement. 16. SEVERABILITY. If any provision of this Agreement is held by a court of competent jurisdiction to be void, invalid, unenforceable or illegal, such provision shall be severed from this Agreement and the remaining provisions will remain in full force and effect. 17. PAYMENT TERMS AND MISCELLANEOUS. You will pay amounts invoiced, in the currency specified on the applicable invoice, within 30 days from the date of such invoice. Any past due invoices will be subject to the imposition of interest charges in the amount of one and one-half percent per month or the applicable legal rate currently in effect, whichever is lower. Some Software may contain code distributed under a third party license agreement that may provide additional rights to you. Please see the applicable Software documentation for details. This Agreement may only be modified in writing by authorized representatives of the parties. Waiver of terms or excuse of breach must be in writing and shall not constitute subsequent consent, waiver or excuse. Rev. 060210, Part No. 227900