SCHOOL OF ELECTRICAL AND ELECTRONICS

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

UNIT IV SECA3019 REAL WORLD INTERFACING USING ARM

PROCESSOR

[Interfacing the peripherals to LPC2148: GSM and GPS using UART, on-chip ADC using
interrupt (VIC), EEPROM using I2C, SD card interface using SPI, on-chip DAC for waveform
generation]

89
4.1 GSM MODULE INTERFACING WITH LPC2148

GSM (Global System for Mobile Communications) is the technology that underpins
most of the world's mobile phone networks.
GSM is an open, digital cellular technology used for transmitting mobile voice and data
services.
GSM operates in the 900MHz and 1.8GHz bands GSM supports data transfer speeds
of up to 9.6 kbps, allowing the transmission of basic data services such as SMS.
The SIM300 module is a Triband GSM/GPRS solution in a compact plug in module
featuring an industry-standard interface

4.1.1 Features of GSM MODEM

Single supply voltage 3.2v-4.5v

Typical power consumption in SLEEP Mode: 2.5mA.
SIM300 tri-band
MT,MO,CB, text and PDU mode, SMS storage: SIM card
Supported SIM Card :1.8V,3V

Figure 4.1: GSM modules

GSM/GPRS module is used to establish communication between a computer and a

GSM-GPRS system.
Global System for Mobile communication (GSM) is an architecture used for mobile
communication in most of the countries.
Global Packet Radio Service (GPRS) is an extension of GSM that enables higher data
transmission rate

90
 SIM7600EI is a complete multi-band LTE/EDGE/GPRS/GSM module solution in LCC
type which supports LTE CAT1 up to 10Mbps for downlink and 5Mbps for uplink data
transfer.

Figure 4.2: GSM Module functional blocks

4.1.2 GSM Mobile Vs GSM Module

A GSM mobile is a complete system in itself with embedded processors that are
dedicated to provide an interface between the user and the mobile network.
The AT commands are served between the processors of the mobile termination and
the terminal equipment.
The mobile handset can also be equipped with a USB interface to connect with a
computer, but it may or may not support AT commands from the computer or an
external processor/controller.
The GSM/GPRS module, on the other hand, always needs a computer or external
processor/controller to receive AT commands from.
GSM/GPRS module itself does not provide any interface between the user and the
network, but the computer to which module is connected is the interface between user
and network.
An advantage that GSM/GPRS modules offer is that they support concatenated SMS
which may not be supported in some GSM mobile handsets

91
 Applications of GSM/GPRS module The GSM/GPRS module demonstrates the use of
AT commands. They can feature all the functionalities of a mobile phone through
computer like making and receiving calls, SMS, MMS etc. These are mainly employed
for computer based SMS and MMS services.

4.1.3 AT Commands

AT commands are used to control MODEMs.AT is the abbreviation for Attention.

These commands come from Hayes commands that were used by the Hayes smart
modems.
The Hayes commands started with AT to indicate the attention from the MODEM.
The dial up and wireless MODEMs need AT commands to interact with a computer.
AT commands with a GSM/GPRS MODEM

Table 4.1 GSM AT Commands

GSM AT Commands and their functions

AT Command Function of AT Command

ATD Dial

AT+CGMS Send SMS Message

AT+CMSS Send SMS Message from storage

AT+CMGL List SMS Messages

AT+CMGR Read SMS Messages

AT+CSCA? Service Centre Address

AT+CPMS To choose storage from ME or SM

AT+IPR=0 To choose auto from baud rate

AT+CMGF= To choose PDU Mode or Text Mode

92
 Figure 4.3: UART data format

4.1.4 Interfacing of GSM Module

Figure 4.4 shows interfacing of LPC2148 with GSM modem using UART protocol. MAX232
IC is used for voltage level shifting from 0V/5V to -12V/+12V.

Figure 4.4 GSM modem interfacing with LPC2148

Table 4.2 Pin assignment for GSM interfacing

UART DB-9 Connector LPC2148 Processor Lines

TXD-0 P0.0
UART0 (P1) ISP PGM
RXD-0 P0.1

TXD-1 P0.8
UART1 (P2)
RXD-1 P0.9

93
Algorithm for GSM module interfacing with LPC2148

1) Start

2) Initialise UART0 or UART1 serial interface using following instruction

PINSEL0=0X0000 0005;//Enable P0.0-TxD0,P0.1-RxD0

U0LCR=0X83; //8-BIT Character length, NO parity,1 stop bit
U0DLL=97; //Baud rate=9600@PCLK=15Mhz Set the data rate
U0LCR=0X03; Divisor Latch Access Bit (DLAB) to Zero

3) Transmit different AT commands through UART module using instruction

while(!(U0LSR&0X20));//Monitor TI flag

4) If transmission buffer is Empty, Transmit AT commands

U0THR=ch; // U0THR (UART0 Transmit Holding Register)

5) Provide delay while transmitting each command

6) To transmit a single character use PUTCH function & to transmit a string use PUTS
function

7) END

4.1.5 Example Program for GSM Interfacing

/**************************************************************************/
/* Project Name:- GSM Module Interfacing with LPC2148 using UART module */
/* Device:- LPC2148 */
/* Compiler:- KeilUvision4 */
/* Language:- Embedded C */
/**************************************************************************
****************/
#include<lpc21xx.h> //Includes LPC2148 register definitions
#include "serial.h"
unsigned char GsmSendMsg(unsigned char *msgStr);
void DelayMs(unsigned int count);

int main(void)
{
Uart0Init();
Uart0PutS("AT\r\n");

94
 DelayMs(500);
Uart0PutS("ATE0\r\n"); //Turn echo off
DelayMs(500);
Uart0PutS("ATD9503XXXXXX;\r\n"); //replace xxxxxxxxxx with number to call
DelayMs(20000);
Uart0PutS("ATH0\r\n"); //disconnect call
DelayMs(3000);
GsmSendMsg("WIKINOTE FOUNDATION");
while(1);
}

unsigned char GsmSendMsg(unsigned char *msgStr)

{
Uart0PutS("AT+CMGF=1\r\n");//Send SMS: Select Text mode
DelayMs(100);
Uart0PutS("AT+CMGS=\"9503XXXXXX\"\r\n"); //Send SMS to mobile number
DelayMs(100);
Uart0PutS(msgStr);
DelayMs(100);
Uart0PutCh(0x1A); //CNTL + Z
DelayMs(3000);
return (1);
}

void DelayMs(unsigned int count)

{
volatile unsigned int j,k;
for (j=0;j<count;j++)
for (k=0;k<6000;k++);
}

4.2. GPS MODULE INTERFACING

The SKG13BL is a complete GPS engine module that features super sensitivity, ultra
low power and small form factor. The GPS signal is applied to the antenna input of module,
and a complete serial data message with position, velocity and time information is presented at
the serial interface with NMEA protocol or custom protocol.

It is based on the high performance features of the MediaTek MT3337 single-

chip architecture, Its 165dBm tracking sensitivity extends positioning coverage into place
like urban canyons and dense foliage environment where the GPS was not possible before. The

95
small form factor and low power consumption make the module easy to integrate into portable
device like PNDs, mobile phones, cameras and vehicle navigation systems.

4.2.1 Features of GPS module

Ultra high sensitivity: -165dBm

Built-in 12 multi-tone active interference canceller

Low power consumption: Typical 22mA@3.3V

±10ns high accuracy time pulse (1PPS)

NMEA Output GGA,GSA,GSV,RMC

Advanced Features: AlwaysLocate; AIC

QZSS,SBAS(WAAS,EGNOS,MSAS,GAGAN)

UART interface: 4800/9600/38400/115200 bps

Small form factor: 15x13x2.2mm and RoHS compliant (Lead-free)

Figure 4.4 GPS module and GPS Antenna

Applications

LBS (Location Based Service)

PND (Portable Navigation Device)
Vehicle navigation system
Mobile phone
Extremely fast TTFF at low signal level

96
4.2.2 Interfacing of GPS Module

Figure 4.5 Interfacing Circuit for GPS receiver module

Table 4.3 Pin assignment with LPC 2148

UART DB-9 Connector LPC2148 Processor Lines

TXD-0 P0.0
UART0 (P1) ISP PGM
RXD-0 P0.1

TXD-1 P0.8
UART1 (P2)
RXD-1 P0.9

Algorithm for GPS module interfacing with LPC2148

1) Start

2) Initialise UART0 or UART1 serial interface using following instruction

PINSEL0=0X0000 0005;//Enable P0.0-TxD0,P0.1-RxD0

U0LCR=0X83; //8-BIT Character lenth,NO parity,1 stop bit
U0DLL=97; //Baud rate=9600@PCLK=15Mhz
U0LCR=0X03;//Dlab=0

3) Receive GPS Message of location and longitude through UART module using
function UARTGetch()

97
 4) Store single character in Variable GPSData

GPSDATA=Uart0Getch();

5) Copy each single received character in array lattitude and longitude

6) Send this array characters to LCD for displaying message

7) END

4.2.3 Example Program for GPS Interfacing

#include <lpc214x.h>
#include "serial.h"
#include "lcd.h"
unsigned int j;
unsigned char Gpsdata; // for incoming serial data
unsigned int finish =0; // indicate end of message
unsigned int pos_cnt=0; // position counter
unsigned int lat_cnt=0; // latitude data counter
unsigned int log_cnt=0; // longitude data counter
unsigned int flg =0; // GPS flag
unsigned int com_cnt=0; // comma counter
unsigned char lat[20]; // latitude array
unsigned char lg[20]; // longitude array
unsigned int i=0;
unsigned int fg=0;;
void gps(void);
int main(void)
{
lcd_init();
Uart0Init();
while(1)
{
gps();
lcdcmd(0x80);
DisplayLCD1("LT:");
DisplayLCD1(lat);
DisplayLCD1("N");
lcdcmd(0xC0);
DisplayLCD1("LG:");
DisplayLCD1(lg);
DisplayLCD1("E");
}
}

98
void gps()
{
while(finish==0){

Gpsdata = Uart0GetCh();
flg = 1;
if( Gpsdata=='$' && pos_cnt == 0) // finding GPRMC header
pos_cnt=1;
if( Gpsdata=='G' && pos_cnt == 1)
pos_cnt=2;
if( Gpsdata=='P' && pos_cnt == 2)
pos_cnt=3;
if( Gpsdata=='R' && pos_cnt == 3)
pos_cnt=4;
if( Gpsdata=='M' && pos_cnt == 4)
pos_cnt=5;
if( Gpsdata=='C' && pos_cnt==5 )
pos_cnt=6;
if(pos_cnt==6 && Gpsdata ==','){ // count commas in message
com_cnt++;
flg=0;
}

if(com_cnt==3 && flg==1){

lat[lat_cnt++] = Gpsdata; // latitude
flg=0;
}

if(com_cnt==5 && flg==1){

lg[log_cnt++] = Gpsdata; // Longitude
flg=0;
}

if( Gpsdata == '*' && com_cnt >= 5 && flg == 1){

lat[lat_cnt] ='\0'; // end of GPRMC message
lg[log_cnt] = '\0';
com_cnt = 0; // end of GPRMC message
lat_cnt = 0;
log_cnt = 0;
flg = 0;
finish = 1;

99
 }
}

finish = 0;
pos_cnt = 0;
}
///////$GPRMC,194530.000,A,3051.8007,N,10035.9989,W,1.49,111.67,310714,,,A*74

Note:- As we need to send AT Commands using UART , we need to add Program for
Serial Communication. Hence Add Serial.c and Serial.h file
Note:- As we want to display Lattitude and Longitude values on LCD we have to add
LCD.c and LCD.h files in our keil Project

4.3 LPC2148 INTERFACING WITH ON-CHIP (INTERNAL) ADC

Analog to Digital Converter (ADC) is used to convert analog signal/voltage into its
equivalent digital number so that microcontroller can process that numbers and make it human
readable. The ADC characterized by resolution. The resolution of ADC indicates the number
-built 10-bit
ADC. So for 10-bit ADC resolution is 10-bit and maximum value will be 210=1024. This means
our digital value or discrete level lies between 0 to 1023. There is one more term important to
understand while dealing with ADC and it is step size. Step size is the minimum change in
input voltage which can be resolved by ADC. The concept of step size is closely associated
with the resolution of ADC.

So in this case we can measure minimum 2.23 mV (Approx.) with our microcontroller. This
is how step size defines an accuracy of ADC circuit.

4.3.1 Features of ADC

2 internal ADC's - ADC0 (6 Channel), ADC1 (8 Channel)

Type: 10-bit, Successive Approximation type,

Supports burst mode (repeated conversion at 3-bit to 10-bit resolution)

Supports simultaneous conversion on both ADC's

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Conversion time: 2.44 micro-seconds

Start of Conversion by software control / on timer match /transition on a pin

Range: 0 V VREF (+3.3 V)

Max. clock frequency is 4.5 MHz, (by programming ADC Control (ADxCON
Register)

Figure 4.6 On-Chip ADC in LPC2148-Internal Diagram

Table 4.4 Pin Assignment for ADC in LPC2148

Block Symbol Description I/O

AD0.1 Channel 1 P0.28

AD0.2 Channel 2 P0.29

AD0.3 Channel 3 P0.30

ADC0
AD0.4 Channel 4 P0.25

AD0.6 Channel 6 P0.4

AD0.7 Channel 7 P0.5

ADC1 AD1.0 Channel 0 P0.6

101
 AD1.1 Channel 1 P0.8

AD1.2 Channel 2 P0.10

AD1.3 Channel 3 P0.12

AD1.4 Channel 4 P0.13

AD1.5 Channel 5 P0.15

AD1.6 Channel 6 P0.21

AD1.7 Channel 7 P0.22

4.3.2 ADC REGISTERS

1. ADxCON - ADC Control Register-32-bit register

Useful for Selection of analog input channel, clock frequency to ADC, Resolution,
conversion mode, method of issue of SoC, edge for conversion

Table 4.5 ADC Register Configuration

RESERVED EDGE START -- PDN -- CLKS BURST CLKDIV SEL

23- 19-
31-28 27 26-24 21 20 16 15-8 7-0
22 17

Bit Symbol Description

Select field:- Selects which of the AD0.7:0/AD1.7:0 pins is (are)

SEL
to be sampled and converted. For AD0, bit 0 selects Pin AD0.0,
(Channel
7-0 and bit 7 selects pin AD0.7. In software-controlled mode, only
Selection
bits)
one of these bits should be 1. In hardware scan mode, any value
containing 1 to 8 can be one

15-8 CLKDIV: Clock Division factor Value:- The APB clock (PCLK) is
divided by (this value plus one) to produce the clock for the A/D

102
 converter, which should be less than or equal to 4.5 MHz
Typically, software should program the smallest value in this
field that yields a clock of 4.5 MHz or slightly less, but in certain
cases (such as a high-impedance analog source) a slower clock
may be desirable.

0; ADC will not perform Repeated A to D Conversion

1; ADC will perform Repeated A to D Conversion The AD
converter does repeated conversions at the rate selected by the
CLKS field, scanning (if necessary) through the pins selected by
1s in the SEL field. The first conversion after the start
corresponds to the least-significant 1 in the SEL field, then
16 BURST higher numbered 1-bits (pins) if applicable. Repeated
conversions can be terminated by clearing this bit, but the

completed.

Remark: START bits must be 000 when BURST = 1 or

conversions will not start.

Clocks:- This field selects the number of clocks used for each
conversion in Burst mode, and the number of bits of accuracy of
the result in the RESULT bits of ADDR, between 11 clocks (10
bits) and 4 clocks (3 bits).

CLKS field - 19- No. of Clock cycles used per bit

18-17 conversion

19-17 CLKS 000 11 clocks cycles / 10 bit conversion

001 10 clocks/ 9 bits

010 9 clocks/ 8 bits

011 8 clocks/ 7 bits

103
 100 7 clocks/ 6 bits

101 6 clocks/ 5 bits

110 5 clocks/ 4 bits

111 4 clocks/ 3 bits

Power Down
21 PDN
PDN=1 The A/D converter is operational.
PDN=0 The A/D converter is in power-down mode.

START field - 26-25-24 Description

26-24
START
000 No start of Conversion

001 Start of Conversion Now

(In use only when START field contains Values from 010 TO
27 Edge
111)

15-8 CLKDIV: The APB clock (PCLK) is divided by (this value plus one) to produce
the clock for the A/D converter, which should be less than or equal to 4.5 MHz
Typically, software should program the smallest value in this field that yields a clock
of 4.5 MHz or slightly less, but in certain cases (such as a high-impedance analog
source) a slower clock may be desirable.
o The A/D Converters on the LPC2148 is also called as The conversion speed is
selectable by the user.
o A/D Clock frequency= [Pclk/(CLKDIV+1)] .....................<=4.5 MHz

104
2. A/D Global Start Register (ADxGSR)

Used to initiate simultaneous conversion on both ADCs

3. A/D Status Register (ADxSTAT)

Allows simultaneous checking of status of all A/D channels

Contains done, overrun, interrupt flags

5. A/D Data Registers (ADR0 ADR7)

Contains most recent converted data and EoC (Done) status on respected channel

Table 4.6 ADC DATA Register Configuration

DONE OVERRUN Reserved 10 bit A/D RESULT Reserved

31 30 29-16 15-6 5-0

6. Global Data Register

Contains done bit, most converted data, channel number

Table 4.7 ADC Global Data Register Configuration

Channel 10 bit A/D

DONE OVERRUN Reserved Reserved Reserved
Selection RESULT

29-28-
31 30 26-25-24 23-16 15-6 5-0
27

DONE (Bit 31)

o DONE= 1 ;when an A/D conversion is complete.
o D0NE=0 ;A/D conversion is in progress

105
For accurate results, you need to wait until this value is 1 before reading the RESULT bits.
(Please note that this value is cleared when you read this register.)

OVERRUN (Bit 30)

While not relevant to the examples used in this tutorial, this value with be 1 if the results
of one or more conversions were lost when converting in BURST mode. See the User's Manual
for further details. (As with DONE, this bit will be cleared when you read this register.)

RESULTS (Bits 15..6)

If DONE is 1 (meaning the conversion is complete), these 10 bits will contain a binary
number representing the results of our analog to digital conversion. It works by measuring the
voltage on the analog input pin divided by the voltage on the Vref pin.

Table 4.8 Analog value and its digital equivalent

Analog Input 10-bit Digital output Digital Output in HEX

0V 0000 0000 00 B 000H

3.3V 1111 1111 11 B 3FFH

Zero means that the voltage on the analog input pin was less than, equal to or close to
GND (Vssa), and 0x3FF (or 0011 1111 1111) indicates that the voltage on the analog input pin
was close to, equal to or greater than the the voltage on the Vref pin. Anything value between
these two extremes will be returned as a 10-bit number (between 0 and 1023).

6. Interrupt Enable Register

Enables interrupt on EOC channel

Programming ADC registers Examples (Construction of control words

4.3.3 ADC Design Example

Select ADC-0, Channel-1, Clock frequency 3.75 MHz (let PCLK is 15 MHz), burst mode
repeated conversion) and 10-bit resolution. Power-up ADC and issue start of conversion.

106
 Solution: AD0CR = 0x01210302; // configure SEL, CLKDIV, BURST CLKS & PDN bit
fields set START, signal start of conversion

1. Select ADC 1, Channels 0 to 7, clock frequency 4.5 MHz (assume PCLK is 30 MHz),
burst mode repeated conversion, 8-bit resolution.

Figure 4.7 On-chip interfacing with Peripherals

a) C Program for on-chip ADC using interrupt

#include <lpc214x.h>
#include "serial.h"
#include <stdio.h>
void delay(void);
void ADC_ISR(void) __attribute__ ((interrupt("IRQ")));
int adcdata;
float voltage;
unsigned char volt[3];
int i;
int main(void)
{
PINSEL0 = 0x00000005;
PINSEL1 = 0x01000000;
PINSEL2 = 0x00000000;

Uart0Init();
Uart0PutS("\n ADC o/p : ");

107
 AD0INTEN = 0x00000002; ///On completion of AD conversion channel1 will generate
an Interrupt
VICVectAddr0 = (unsigned int)ADC_ISR;
VICVectCntl0 = 0x20 | 18; //// VIRQ and Assign AD0 interrupt Slot0
VICIntEnable = 1 << 18; ///Enable AD0 interrupt channel of VIC

AD0CR = 0X01200402; // Channel AD0.1 , Clock 3Mhz, Burst Mode, 11 clocks per 10 bit ,
//AD conversion is operational, start conversion

while(1){

return 0;
}

void ADC_ISR()
{
if(AD0DR1 & 0x80000000) ///Monitor EOC bit from AD Data Register of Channel0
{
adcdata=(AD0DR1 & 0x0000FFC0);
adcdata=adcdata>>6; ///Right shift Digital Result by 6 bits
voltage=((adcdata/1023.0)*3.3);
sprintf(volt, "%.1f", voltage); ////Buffer, decimal value. 1 digit fractional value, float
volatage value
Uart0PutS(volt); ///print buffer on Hyperterminal
}
delay();
AD0INTEN = 0; ////Disable ADO Interrupr
VICVectAddr=0; ///End of ISR
}
void delay(void)
{
int i,j;
for(i=0;i<1000;i++)
for(j=0;j<10000;j++);
}

b) Embedded C Program for on-chip(Internal ADC) without Interrupt

#include<lpc214x.h>
#include<stdio.h>
#include "serial.h"
void delay(void);

108
int main()
{
int adcdata;
float voltage;
unsigned char volt[3];
PINSEL0=0X00000000;
PINSEL1=0X01000000; //Select P0.28 pin function as Analog i/p
Uart0Init();
AD0CR=0x00210402; ///CHANNEL1 OF ADC0, ad freq=3MHz,
while(1)
{
if(AD0DR1 & 0x80000000) ////EOC bit monitoring
{
adcdata=(AD0DR1 & 0x0000FFC0);
adcdata=adcdata>>6;
voltage=((adcdata/1023.0)*3.3);
sprintf(volt, "%.1f", voltage); ADC o/p=1.2
Uart0PutS("\n ADC o/p : ");
Uart0PutS(volt);
delay();
}
}
}
void delay(void)
{
int i,j;
for(i=0;i<1000;i++)
for(j=0;j<10000;j++);
}

4.4 Serial Communication Using UART in LPC2148

The characteristics of UART hardware in LPC2148 controller and its associated registers is briefly
discussed in this section. The important features of UART hardware in LPC2148 are:

UART1 is identical to UART0, with the addition of a modem interface.

16 byte Receive and Transmit FIFOs.

Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.

Built-in fractional baud rate generator with autobauding capabilities.
Mechanism that enables software and hardware flow control implementation.
Standard modem interface signals included with flow control (auto-CTS/RTS) fully

109
supported in hardware (LPC2144/6/8 only).

Figure 4.8 UART0 Architecture in LPC2148

110
U0FCR (FIFO Control Register)

8-BIT Byte Addressable register

This reg is used to enable TX & RX FIFO functionalities
U0FCR=0x07 is like SCON reg

Table 4.9 U0FCR (FIFO Control Register) bit assignment

FIFO TX RX
FIFO
U0FCR Control - - - - - FIFO FIFO
Enable
Register Reset Reset

U0LCR (Line Control Register)

8-BIT byte addressable register

Table 4.10 U0LCR (Line Control Register)bit assignment

UART0 Line Control Register (U0LCR - address 0xE000 C00C) bit description

Reset
Bit Symbol Value Description
Value

00 5 bit character length

Word Length
1:0 01 6 bit character length 0
Select

10 7 bit character length

11 8 bit character length

0 1 stop bit
2 Stop Bit Select 0

1 2 stop bits (1.5 if U0LCR[1:0]==00)

111
 0 Disable parity generation and checking
3 Parity Enable 0

1 Enable parity generation and checking

Odd parity. Number of 1s In the

00 transmitted character and the attached
parity bit will be odd.

5:4 Parity Select Even Parity. Number of is in the 0

01 transmitted character and the attached
parity bit will be even.

10 Forced "1" stick parity.

11 Forced "0" stick parity.

0 Disable break transmission

6 Break Control 0
Enable break transmission. Output pin
1 UARTO TXD Is forced to logic 0 when
UOLCR[6] Is active high.

Divisor Latch 0 Disable access to Divisor Latch

7 Access Bit
0
(DLAB)
1 Enable access to Divisor Latch

DLAB (Divisor Latch Buffer)

One high-low pulse across DLAB bit indicates baud rate is successfully loaded.

DLAB=1 baud rate is loading

DLAB=0 After loading baud rate DLAB must be zero.

112
U0LSR (Line Status Register)

8-bit byte addressable register

Consists of different flag bits, TI interrupt & RI interrupt flag bit

Table 4.11 U0LSR (Line Status Register) bit assignment

UART0 Line Status Register

Reset
Bit Symbol Value Description
value

U0LSR0 is set when the U0RBR holds an

unread character and is cleared when the
UART0 RBR FIFO is empty.
Receiver Data
0 0
Ready (RDR)
0 U0RBR is empty.

1 U0RBR contains valid data.

The overrun error condition is set as soon as

it occurs. An U0LSR read clears U0LSR1.
U0LSR1 is set when UART0 RSR has a
new character assembled and the UART0
RBR FIFO is full. In this case, the UART0
Overrun Error
1 RBR FIFO will not be overwritten and the 0
(OE)
character in the UART0 RSR will be lost.

0 Overrun error status is inactive.

1 Overrun error status is active.

When the parity bit of a received character

is in the wrong state, a parity error occurs.
An U0LSR read clears U0LSR[2]. Time of

113
 parity error detection is dependent on
U0FCR(0).

Note: A parity error is associated with the 0

2 Parity Error
character at the top of the UART0 RBR
FIFO.

0 Parity error status is Inactive.

When the stop bit of a received character is

a logic 0. a framing error occurs. 0 An
U0LSR read dears U0LSR[3]. The time of
the framing error detection is dependent on
U0FCR0. Upon detection of a framing error,
the Rx will attempt to resynchronize to the
data and assume that the bad stop bit is
actually an early start bit. However, it
Framing Error cannot be assumed that the next received
3 byte will be correct even if there is no 0
(FE)
Framing Error.

Note: A framing error is associated with the

character at the top of the UART0 RBR
FIFO.

0 Framing error status is inactive.

1 Framing error status is active.

When RXD0 is held in the spacing state (all

0's) for one full character transmission
(start, data, parity, stop), a break interrupt
occurs. Once the break condition has been
detected, the receiver goes idle until RXD0
Break goes to marking state (all 1s). An U0LSR
4 0
Interrupt (BI) read clears this status bit. The time of break
detection is dependent on U0FCR(0).

Note: The break interrupt is associated with

the character at the top of the UART0 RBR
FIFO.

0 Break interrupt status is inactive.

114
 1 Break interrupt status is active.

THRE is set immediately upon detection of

Transmitter an empty UART0 THR and is 1
Holding cleared on a U0THR write.
5 Register 1
Empty
(THRE) 0 U0THR contains valid data.

1 U0THR is empty.

TEMT is set when both U0THR and U0TSR

are empty; TEMT is cleared when either the
Transmitter U0TSR or the U0THR contain valid data.
6 Empty 1
(TEMT)
U0THR and/or the U0TSR contains valid
0
data.

1 U0THR and the U0TSR are empty.

UOLSR(7) is set when a character with a Rx

error such as framing error, parity error or
break interrupt, is loaded into the U0RBR.
This bit is cleared when the U0LSR register
is read and there are no subsequent errors in
Error in RX the UART0 FIFO.
7
FIFO (RXFE) 0

U0RBR contains no UART0 RX errors or

0
U0FCR[0]=0.

UART0 RBR contains at least one UART0

1
RX error.

115
DLR (Divisor Latch Register)

DLR is 16-bit register

Used to load baud rate
As the baud rate is 8-bit value, divide DLR into two parts DLM & DLL (8-bit each)

For 9600 baud rate

U0DLL=0x63; //(Pclk=12Mhz)
U0DLM=0x00

U0DLL:U0DLM=[Pclk/16*Desired Baud rate]

U0THR (Transmit Hold Register)

8-bit byte addressable reg.

Data can be loading to U0THR, whenever transmitting data

//THR buffer register is used only for transmitting

U0RBR (UART0 Receive Buffer Register)

8-bit byte addressable reg.

Data can be loading into U0RBR, whenever receiving data.
a = U0RBR //RBR buffer register is used only for transmitting

Figure 4.9 Circuit for serial communication with LPC2148 and PC

116
4.4.2 Algorithm for UART serial communication

1) Start
2) Initialise UART0 serial interface using following instruction

PINSEL0=0X0000 0005;//Enable P0.0-TxD0,P0.1-RxD0

U0LCR=0X83; //8-BIT Character lenth,NO parity,1 stop bit, DLAB=1

U0DLL=97; //Baud rate=9600@PCLK=15Mhz
U0LCR=0X03;//DLAB=0
3) LPC2148 will receive characters transmitted by PC

4) LPC2148 will transmit the characters received back to PC

3) Transmit different AT commands through UART module using instruction

while(!(U0LSR&0X20));//Monitor TI flag

4) If transmission buffer is Empty,Transmit single character at a time

U0THR=ch;

5) Provide delay while transmitting each command

6) To transmit a single character use PUTCH function & to transmit a string use PUTS
function
7) END

4.4.3 Embedded C program for Serial Transmission and Reception

#include<lpc21xx.h> //Includes LPC2148 register definitions

void Uart0Init (void) // Initialize Serial Interface

{
PINSEL0 = 0x00000005; //Enable RxD0 and TxD0
U0LCR = 0x83; // 8 bits, no Parity, 1 Stop bit
U0DLL = 97; // 9600 Baud Rate @ 15MHz PCLK
U0LCR = 0x03; // DLAB = 0
}

void Uart0PutCh (unsigned char ch) // Write character to Serial Port

{
U0THR = ch;
while (!(U0LSR & 0x20));
}

117
void Uart0PutS(unsigned char *str) //A function to send a string on UART0
{
while(*str)
{
Uart0PutCh(*str++);
}
}
unsigned char Uart0GetCh (void) // Read character from Serial Port
{
while (!(U0LSR & 0x01));
return (U0RBR);
}
int main()
{
unsigned char a;
Uart0Init();
while(1)
{
a=Uart0GetCh();
Uart0PutCh(a);
}
}

4.5 LPC2148 INTERFACING WITH EEPROM USING I2C

I2C is a two-wire synchronous serial communication protocol. SDA line is used for
transferring data and SCK is used for transferring clock information. Every device connected
to an I2C bus has a unique address.

Figure 4.10: I2C frame format

118
 I2C communication protocol involves communication between a slave and a master.
The device which initiates the communication and which provides the clock is referred to as a
master device. The devices which receive the clock signal and receive/transmit data according
to the clock signal is termed as a slave device. Each device on the bus is accessed using its
slave address.

START condition

STEP-1) First the MCU will issue a START condition. The devices connected to the
bus will listen to the START condition and will stay ready to begin the communication
process.

STEP-2) Then MCU will send the address of the device with which it needs to
communicate. Master indicates the action to be performed with the device whether to
read or write along with the address.

STEP-3) All devices connected to the bus will receive the address and will compare it
with its own address. If the addresses match with each other, the device will send back
an ACKNOWLEDGEMENT signal to the master device. If they
match they will simply wait for the bus to be released with a STOP condition.

STEP-4) Once the MCU sends the address and corresponding device acknowledges,
the MCU can start transmitting or receiving data.

STEP-5) When the data transmission or reception is complete, the MCU will stop
communicating by sending a STOP condition.

STOP condition

STEP-6) STOP condition indicates that the bus is released and it can be used by any
other master (if any) connected to the I2C bus.

After a master generate a start condition I2C bus will solely belong to it. The bus will
be freed only if the master generate a STOP condition. Any other master connected to
the bus can access the bus after a STOP is identified on the bus.
If the master device which uses the bus needs to communicate with a different slave it
should generate a RESTART. Instead if it tries to stop current communication and then
start again it may lose access to the bus. RESTART is nothing but a start signal without
a stop in the bus.

119
4.5.1 Features of I2C module in LPC2148

Two fast I2C buses (I2C0, I2C1)

Standard I2C compliant bus interfaces that may be configured as Master, Slave, or
Master/Slave.
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Programmable clock to allow adjustment of multiple I2C data transfer rates.
o Standard- 100 kbps
o Fast- 400 kbps
o High Speed- 3.4 Mbps
Bidirectional data transfer between masters and slaves.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I2C bus may be used for test and diagnostic purposes.

Applications

Interfaces to external I2C standard parts

Serial RAMs, ROMs

LCDs
Tone generators

Table 4.12 Pin Description for I2C communication

Pin Type Description LPC2148 Pins

SDA0/1 Input/Output I2C Serial Data P0.3 and P0.14

SCL0/1 Input/Output I2C Serial Clock P0.2 and P0.11

120
 Table 4.13 I2C Registers

Generic Reset I2Cn Register

Description Access
Name value name & Address

I2C Control Set

Register. When a one is
written to a bit of this I2C0CONSET -
register. the corresponding 0xE001 C000
I2CONSET bit in the I2C control register R/W 0x00
is set. Writing a zero has no I2C1CONSET -
effect on the corresponding 0xE005 C000
bit in the I2C control
register.

I2C Status Register. During

I2C operation, this register I2C0STAT -
provides detailed status 0xE001 C0004
I2STAT RO 0xF8
codes that allow software to
determine the next action I2C1STAT -
0xE005 C004
needed.

I2C Data Register. During

master or slave transmit
mode. data to be transmitted I2C0DAT -
is written to this register. 0xE001 C008
I2DAT R/W 0x00
During master or slave
receive mode, data that has I2C1DAT -
0xE005 C008
been received may be read
from this register.

I2C Slave Address

Register. Contains the 7 bit I2C0ADR -
slave address for operation of 0xE001 C00C
I2ADR the I2C interface in slave R/W 0x00
mode. and is not used in I2C1ADR -
master mode. The least 0xE005 C00C
significant bit determines

121
 whether a slave responds to
the general call address.

SCH Duty Cycle Register I2C0SCLH -

High Half 0xE001 C010
I2CSCLH R/W 0x04
Word. Determines the high
time of the RC clock. I2C1SCLH -
0xE005 C010

SCL Duty Cycle Register

Low Half
Word. Determines the low
time of the 12C clock. I2C0SCLL -
0xE001 C014
I2CSCLL I2nSCLL and I2nSCLH R/W 0x04
together determine the clock I2C1SCLL -
frequency generated by an 0xE005 C014
I2C master and certain times
used in slave mode.

I2C Control Clear

Register. When a one is
written to a bit of this
register. the corresponding I2C0CONCLR -
0xE001 C018
I2CONCLR bit in the I2C control register WO NA
is cleared. Writing a zero has I2C1CONCLR -
no effect on the 0xE005 C018
corresponding bit in the PC
control register.

Table 4.14 I2CxCONSET Register

Bit Symbol Description

0-1 -- Reserved

122
 Assert Acknowledge
2 AA
AA=1; request an acknowledge

I2C Serial Interrupt

3 SI
SI=1; indicate state change

STOP
4 STO
STO=1; sends stop condition

START
5 STA
STA=1; sends START condition

6 I2CEN I2CEN=1; I2C interface enable

7 - Reserved

4.5.2 Features of EEPROM IC (AT24C512)

The AT24C512 provides 524,288 bits of serial electrically erasable and programmable
read only memory (EEPROM) organized as 65,536 words of 8 bits each.
cascadable feature allows up to four devices to share a common two-wire
bus.
The device is optimized for use in many industrial and commercial applications where
low power and low-voltage operation are essential.
The devices are available in space saving8-pin PDIP, 8-lead EIAJ SOIC, 8-lead JEDEC
SOIC, 8-lead TSSOP, 8-lead Leadless Array (LAP), and 8-lead SAP packages. In
addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 3.6V)
versions.

123
 Figure 4.11 Pin details of EEPROM IC

Figure 4.12 Interfacing EEPROM IC with LPC2148

4.5.3 Algorithm for the Interfacing EEPROM

1) Start

2) Initialize I2C bus interface

PINSEL0=0X10400050; //Configure P0.11-SCL1 & P0.14-SD1

I2CSCLH=150;
I2CSCLL=150; //SET I2C frequency=[Pclk/(I2CSCLL+I2CSCH)]

3) Transmit the slave address(Page address,Page offset,No. of bytes)

4) Enable I2C bus interface

124
I2CCONSET=0X40;////I2CEN=1

5) Master (LPC2148) will transmit START signal

I2CCONSET=0X20;//STA=1

6) Transmit slave address(7-bit address,R/W=0; write operation)

7) Wait for acknowledgement

8) Tansmit Page address and page offset at which data is to be written

9) Wait for acknowledment

10) Transmit data using I2CDAT register

11) Wait for acknowledge

12) After successful transmission of data , master wil transmit STOP condition

I2CCONSET=0X10;//STO=1

13) Disable I2C interface

I2CCONCLR=0X40; //I2CENC=1

14) END

Example Program

#include <LPC214x.h>
#include <stdio.h>
#include "serial.h"

#define EEPROM_Addr 0xA0 //device address

#define I2Cwrite 0x00 //LSB bit 0 (write)
#define I2Cread 0x01 //LSB bit 1 (read)

#define I2C_ENABLE 1 << 6 //I2C Enable bit

#define I2C_START 1 << 5 //Start Bit
#define I2C_STOP 1 << 4 //Stop Bit
#define I2C_SI 1 << 3 //I2C interrupt flag
#define I2C_AACK 1 << 2 //assert ACK flag
unsigned char write_array[10] = {11,12,13,14,15,16,17,18,19,20};
unsigned char read_array[10];
unsigned char val[4];
void I2CInit(void)
{

125
 PINSEL0 |= 0x00000050; //P0.2 -> SCL0 P0.3 -> SDA0 I2C0CONCLR =
I2C_ENABLE | I2C_START | I2C_STOP | I2C_SI | I2C_AACK; //clear all the bits in
CONTROL register
//set I2C clock to work at 100Khz
I2C0SCLH = 0x4B ; //set the high time of i2c clock; (15mhz / 100khz / 2)
I2C0SCLL = 0x4B ; //set the low time of i2c clock;

I2C0CONSET = I2C_ENABLE ; //enable the I2C Interface

}
void I2CStart(void) //Function to initiate a start condition on the I2C bus
{
unsigned int status;
I2C0CONCLR = (I2C_START | I2C_STOP | I2C_SI | I2C_AACK); // clear all the bits in
CONCLR register
I2C0CONSET = (I2C_ENABLE ); //Enable the I2C interface
I2C0CONSET = (I2C_START); //set the STA bit
while(!((status=I2C0CONSET)& I2C_SI)); //wait till interrupt flag becomes set
}
void I2CStop(void)
{
unsigned int status;
I2C0CONCLR = I2C_START | I2C_SI | I2C_AACK; //clear all bits
I2C0CONSET = I2C_STOP; //set STOP bit
}
void I2Csend(unsigned char data)
{
unsigned int status;
I2C0DAT = data;
I2C0CONCLR = I2C_START | I2C_STOP ; // clear start bit for next operation
I2C0CONCLR = I2C_SI; // clear interrupt flag
while(!((status=I2C0CONSET)& I2C_SI)); //wait till interrupt flag becomes set
}

unsigned char I2Cget(void)

{
unsigned char data;
unsigned int status;

I2C0CONCLR = I2C_START | I2C_STOP;

I2C0CONCLR = I2C_SI; // clear interrupt flag
I2C0CONSET = I2C_AACK; // send ack to continue further data transfer
while(!((status=I2C0CONSET)& I2C_SI)); //wait till interrupt flag becomes set
data = I2C0DAT;
return data;

126
}

int main()
{
unsigned int i,j;
Uart0Init(); //initialize UART with 9600 baudrate
Uart0PutS("\r\nI2C EEPROM\r\n");
I2CInit(); //initialize I2C

/* Write Sequence */
Uart0PutS("\r\n Writing Data.....\r\n");
I2CStart(); //Assert START
I2Csend(EEPROM_Addr | I2Cwrite); //Device address with LSB bit 0
I2Csend(0x13); //Address higher byte
I2Csend(0x49); //Address lower byte
for(i=0;i<10;i++)
I2Csend(write_array[i]); //write the array to EEPROM
I2CStop();
//Assert STOP
for(i=0;i<10;i++)
{
sprintf(val,"%d",write_array[i]); //display read data
Uart0PutS(val);
Uart0PutS("\r\n");
}
/* Read Sequence */
Uart0PutS("\r\n Reading.....\r\n");
I2CStart(); //Assert START
I2Csend(EEPROM_Addr | I2Cwrite); //Device address with LSB bit 0 (Dummy Write)
I2Csend(0x13); //Address higher byte
I2Csend(0x49); //Address lower byte
I2CStart(); //Assert Restart
I2Csend(EEPROM_Addr | I2Cread); //Device address with LSB bit 1
for(i=0;i<10;i++)
read_array[i] = I2Cget(); //Read EEPROM
I2CStop(); //Assert STOP

/*Display Write and Read Data*/

127
for(i=0;i<10;i++)
{
sprintf(val,"%d",read_array[i]); //display read data
Uart0PutS(val);
Uart0PutS("\r\n");
}
while(1); //stop here forever
return 0;
}

4.6 SD CARD INTERFACING WITH LPC2148

4.6.1 Features of SPI Module in LPC2148

Single complete and independent SPI controller.

Compliant with Serial Peripheral Interface (SPI) specification.
Synchronous, Serial, Full Duplex Communication.
Combined SPI master and slave.
Maximum data bit rate of one eighth of the input clock rate.
8 to 16 bits per transfer

Table 4.15 SPI Pin Description in LPC2148

Pin Name Type Pin Description LPC2148 Pins

SCK0 Input / Output Serial Clock P0.4

SSEL0 Input Slave Select P0.7

MISO0 Input / Output Master In Slave Out P0.5

MOSI0 Input / Output Master Out Slave In P0.6

128
 Table 4.16 SPI Registers

Name Description Access

SPI Control Register. This register controls the operation of

S0SPCR R/W
the SPI.

Read
S0SPSR SPI Status Register. This register shows the status of the SPI.
Only

SPI Data Register. This bi-directional register provides the

transmit and receive data for the SPI. Transmit data is
S0SPDR R/W
provided to the SPI0 by writing to this register. Data received
by the SPI0 can be read from this register.

SPI Clock Counter Register. This register controls the

S0SPCCR R/W

SPI Interrupt Flag. This register contains the interrupt flag

S0SPINT R/W
for the SPI interface.

SPI Control Register (S0SPCR)

The S0SPCR register controls the operation of the SPI0 as per the configuration bits setting.

Table 4.17 SOSPCR Register description

Bits 15-12 11-8 7 6 5 4 3 2 1 0

Bit
Sym Reser BI SPI LS MS CP CP
Enab
bol ved TS E BF TR OL HA - -
le

Bits Symbol Description

0-1 Reserved -

0 ;The SPI controller sends and receives 8 bits of data per

BIT FIELD transfer.
2
ENABLE 1; The SPI controller sends and receives the number of
bits selected by bits field (11:8)

3 CPHA Clock Phase Control

129
 0; The data is sampled on first clock edge
1; The data is sampled on second clock edge

Clock Polarity
4 CPOL 0; Serial Clock (SCK) is active High
1; Serial Clock (SCK) is active High

Master mode select.

5 MSTR 0; The SPI operates in Slave mode.0
1 ;The SPI operates in Master mode.

LSB First controls which direction each byte is shifted

when transferred.
6 LSBF
0; SPI data is transferred MSB (bit 7) first.
1 ;SPI data is transferred LSB (bit 0) first.

Serial peripheral interrupt enable.

0; SPI interrupts are inhibited.0
7 SPIE
1; A hardware interrupt is generated each time the SPIF
or WCOL bits are activated

When bit 2 of this register is 1, this field controls the

number of bits per transfer:
1000 - 8 bits per transfer
1001- 9 bits per transfer
1010- 10 bits per transfer
11-8 BITS FIELD 1011 -11 bits per transfer
1100 -12 bits per transfer
1101 -13 bits per transfer
1110 -14 bits per transfer
1111 -15 bits per transfer
0000 -16 bits per transfer

15-
RESERVED Reserved
12

130
SPI STATUS REGISTER(S0SPSR)

The S0SPSR register controls the operation of the SPI0 as per the configuration bits setting.

Table 4.18 SOSPSR Register description

Bits 7 6 5 4 3 2 1 0

Symbol SPIF WCOL ROVR MODF ABRT - - -

Bits Symbol Description

0-2 Reserved -

Slave abort.
3 ABRT When 1, this bit indicates that a slave abort has occurred. This bit
is cleared by reading this register.

Mode fault.
when 1, this bit indicates that a Mode fault error has occurred.
4 MODF
This bit is cleared by reading this register, then writing the SPI
control register.

Read overrun.
5 ROVR When 1, this bit indicates that a read overrun has occurred. This
bit is cleared by reading this register.

Write collision.
When 1, this bit indicates that a write collision has occurred. This
6 WCOL
bit is cleared by reading this register, then accessing the SPI data
register.

SPI transfer complete flag.

7 SPIF When 1, this bit indicates when a SPI data transfer is complete.
When a master, this bit is set at the end of the last cycle of the

131
 transfer. When a slave, this bit is set on the last data sampling
edge of the SCK. This bit is cleared by first reading this register,
then accessing the SPI data register.

SPI Data Register (S0SPDR)

This bi-directional data register provides the transmit and receive data for the SPI.Transmit
data is provided to the SPI by writing to this register. Data received by the SPI can be read
from this register. When a master, a write to this register will start a SPI data transfer. Writes
to this register will be blocked from when a data transfer starts to when the SPIF status bit is
set, and the status register has not been read.

Table 4.19 SPI Data Register (S0SPDR)

Bits Symbol Description

Data
7-0
Low

If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or
15- Data all of these bits contain the additional transmit and receive bits.
8 HIGH When less than 16 bits are selected, the more significant among
these bits read as zeroes.

SPI Clock Counter Register (S0SPCCR)

number of PCLK cycles that make up an SPI clock.

The value of this register must always be an even number. As a result, bit 0 must
always be 0.
The value of the register must also always be greater than or equal to 8.

SPI (SCLK) Frequency = PCLK / SPCCR Value Max. Freq=1.875 Mhz

Note:-Violations of this can result in unpredictable behaviour

132
4.6.2 SD Cards

Digital (SD) cards are removable flash-

digital camera. Their small size, relative simplicity, low power consumption and low cost make
them an ideal solution for many applications.

Figure 4.13 SD Cards from different manufacturers

SD/MMC cards have their own architecture and signals.

These are universal low-cost, high-speed data storage cards.
MMCs work at 20 MHz, while SD cards work at up to 25 MHz's,
The two memories work in two different modes: SD mode and serial peripheral
interface (SPI).

Figure 4.13 SD card internals

133
 Table 4.20 SD card pin details

Figure 4.14 SD card Interfacing diagram with LPC2148

SD Memory interfaces to the host point-to-point (in Fig. an ARM microcontroller is the host).
This type of interfacing is very popular in the industry. In serial peripheral interface (SPI)
mode, you can use following signals of the host:

134
1. CS: Host to card chip-select signal

2. CLK: Host to card clock signal

3. MOSI (master -out slave-in): Host to card single bit data signal

4. MISO (master - in slave - out ) : Card to host single-bit data signal

Now many companies are manufacturing suitable hosts for the SD bus interface.

For example, Philips is manufacturing LPC2148 microcontroller with MOSI and MISO

Master-slave mode of communication is used for multiple slave devices in the SD

architecture.
MOSI is a unidirectional signal used to transfer serial data from the master to the slave.

is connected to data input (DI) of the SD/MMC card.

The MISO signal transfers serial data from the slave to the master. When the SD is a
slave, serial data is output on MISO signal. When the SD is a master, it clocks in serial
data from this signal.
SD memory cards use 1- or 4-bit bus width and star topology to connect multiple cards,
while MMC cards use 1-bit bus width and bus topology for reading multiple cards.

Steps to switch from SD-Bus mode to SPI Bus mode of Operation

All communications between the host and the card are controlled by the host.
Messages in the spi bus protocol consist of commands, responses and tokens.
The card returns a response to every command received and also a data response token
for every write command
The sd card wakes up in sd card mode, and it will enter the spi mode if its cs (chip
select or slave select) line is held low. When a reset command is sent to the card
The card can only be returned to the sd mode after a power down and power up
sequence then the spi mode is entered.
The card is in the non protected mode where CRC checking is not used CRC checking
can be turned on and off by sending command CRC_on_off command name cmd59 to
the card.

135
 Figure 4.15 Algorithm for R/W operation with SD card

4.6.3 Example Program for SD card Interfacing

/********************************/
Function for initializing SPI
/********************************/
void spi_init()
{
PINSEL0=0X00001505;// Select MOSI=P0.6, MISO=P0.5, SCK=P0.4,SSEL=P0.7
S0SPCCR=0X08; // clock is divided by 8 ( SPI Clock freq = PCLK / S0SPCCR Value)
S0SPCR=0X0020; // select as master mode
}
/********************************/
Function for sending a char
/********************************/
void spi_master(char a)
{
S0SPDR=a;
while(!(S0SPSR & 0X80)); // wait till SPIF=1 i.e., complete transfer of data
}
/********************************/
Function for receiving a char
/********************************/

136
char spi_slave(void)
{
while(!(S0SPSR & 0X80)); // wait till SPIF=1 i.e., complete reception of data

return S0SPDR; //pick-up received character which is arrived in S0SPDR

4.7 DIGITAL TO ANALOG CONVERTER (DAC) IN LPC2148

LPC2148 has one 10-bit DAC

Settling time software selectable
DAC output can drive max of 700 micro-Ampere or 350 micro-Ampere
DAC peripheral has only one register, DACR

Table 4.21 DAC Register Pin Description

Pin Type Description

Analog Output. After the selected settling time after the

AOUT Output DACR is written with a new value, the voltage on this pin (with
respect to VSSA) is VALUE/1024 * VREF.

Voltage Reference. This pin provides a voltage reference level

VREF Reference
for the D/A converter.

Analog Power and Ground. These should be nominally the

VDDA,
Power same voltages as V3 and VSSD, but should be isolated to
VSSA
minimize noise and error.

Table 4.22 Digital to Analog Control Register (DACR) Description

31-17 16 15-6 5-0

Reserved BIAS 10-bit Digital Value Reserved

Reset
Bit Symbol Value Description
value

137
 Reserved, user software should not write ones
5:0 - to reserved NA bits. The value read from a NA
reserved bit is not defined.

After the selected settling time after this field

is written with a 0 new VALUE, the voltage
15:6 VALUE 0
on the AOUT pin (with respect to VssA) is
VALUE/1024 * VREF.

The settling time of the DAC is 1 µs max, and

0 0
the maximum current is 700 µA.
16 BIAS
The settling time of the DAC is 2.5 µs and the
1
maximum current is 350 µA.

Reserved, user software should not write ones

31:17 - to reserved NA bits. The value read from a NA
reserved bit is not defined.

4.7.1 DAC Design Example

Configure DAC register for generating with 3.3V VREF & Select 350 micro AMPERE settling
time.

1. 0V,
2. 1.65V,
3. 3.3V

Note: AOUT= VREF * (10 bit Digital Value/Resolution)

Solution:

1. DACR = 0x00010000; //AOUT = 0V

2. DACR = 0x00018000; //AOUT = 1.65V
3. DACR = 0x0001FFC0; //AOUT = 3.3 V

138
 Figure 4.16 Configuring internal DAC of LPC2148

4.7.2 C-Program for Sine Waveform Generation using DAC in LPC2148

#include <lpc214x.h>
#include <stdint.h>
void delay_ms(uint16_t j)
{
uint16_t x,i;
for(i=0;i<j;i++)
{
for(x=0; x<6000; x++); /* loop to generate 1 milisecond delay with Cclk = 60MHz */
}
}

int main (void)

{
uint16_t value;

139
uint8_t i;
i = 0;
PINSEL1 = 0x00080000; /* P0.25 as DAC output */
uint16_t sin_wave[42] = {
512,591,665,742,808,873,926,968,998,1017,1023,1017,998,968,926,873,808,742,665,591,51
2,
436,359,282,216,211,151,97,55,25,6,0,6,25,55,97,151,211,216,282,359,436 };
while(1)
{
while(i !=42)
{
value = sin_wave[i];
DACR = ( (1<<16) | (value<<6) );///Bias bit=1, Digital Value left shifted by 6 bits
delay_ms(1);
i++;
}
i = 0;
}
}

4.7.3 C-code for Triangular Waveform Generation

#include <lpc214x.h>
#include <stdint.h>
void delay_ms(uint16_t j)
{
uint16_t x,i;
for(i=0;i<j;i++)
{
for(x=0; x<6000; x++); /* loop to generate 1 milisecond delay with Cclk = 60MHz */
}
}

int main (void)

{
uint16_t value;
uint8_t i;
i = 0;
PINSEL1 = 0x00080000; /* P0.25 as DAC output */
while(1)
{
value = 0;
while ( value != 1023 )
{

140
 DACR = ( (1<<16) | (value<<6) );
value++;
}
while ( value != 0 )
{
DACR = ( (1<<16) | (value<<6) );
value--;
}
}

4.7.4 C-Program for Square Waveform Generation

#include <lpc214x.h>
#include <stdint.h>
void delay_ms(uint16_t j)
{
uint16_t x,i;
for(i=0;i<j;i++)
{
for(x=0; x<6000; x++); /* loop to generate 1 milisecond delay with Cclk = 60MHz */
}
}

int main (void)

{
uint16_t value;
uint8_t i;
i = 0;
PINSEL1 = 0x00080000; /* P0.25 as DAC output */
while(1)
{
value = 1023;
DACR = ( (1<<16) | (value<<6) );
delay_ms(100);
value = 0;
DACR = ( (1<<16) | (value<<6) );
delay_ms(100);
}
}

141
TEXT / REFERENCE BOOKS

1. Tularam M Bansod " Microcontroller Programming (8051, PIC, ARM7 ARM Cortex)",
1st Edition, Shroff Publishers,2017
2. A Getting Started Guide for MDK Version 5- Reference Manual, Keil, 2015
3. Steve Furber, "ARM System-on-

Exercise Questions

1. Mention the key specifications of LPC2148 ARM processor.

2. How many I/O devices can be connected to LPC2148 by using UART interface?
3. Mention the four logic signals used in SPI protocols
4. Outline the logic signals used in I2C protocol.
5. Contrast SPI and I2C protocol.
6. Outline the role of shift register in master slave devices of SPI bus.
7. Give the specifications of on-chip DAC in LPC2148 processor.
8. Contrast GSM and GPS modems.
9. Design a circuit with LPC2148 ARM processor and develop a C code to measure the
intensity of ambient light and temperature and automatically control a AC lamp.
10. Design a circuit with LPC2148 ARM processor and develop a C code to read an analog
voltage and convert it to equivalent digital value.
11. Design a circuit with LPC2148 ARM processor and develop a C code to generate a
triangular waveform with a frequency of 1KHz using the DAC module.
12. Design a circuit with LPC2148 ARM processor and a GSM modem to control an
agriculture water pump-set, by sending SMS from a mobile phone.
13. Design a circuit with LPC2148 ARM processor and develop a C code to read data from
EEPROM using I2C protocol.
14. Develop a system model for a real-time data acquisition and logging system with SD
card storage unit.

142