NB1 NanoBoard Technical

Reference Manual
Technical hardware reference manual for the NB1 NanoBoard
FPGA implementation platform

Legacy documentation
refer to the Altium Wiki for current information
 CAUTION
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Copyright © 2008 Altium Limited.
The material provided with this notice is subject to various forms of national and international intellectual property
protection, including but not limited to copyright protection. You have been granted a non-exclusive license to use
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 NanoBoard NB1 Technical Reference

Table of Contents
Introduction to the Altium NB1 NanoBoard 2
Overview of the Altium NB1 NanoBoard ................................................................................2
Key Features of the Altium NB1 NanoBoard..........................................................................4
Functional Overview of the Altium NB1 NanoBoard ..............................................................5

Setting up the NanoBoard 6

What’s in the box....................................................................................................................6
System requirements .............................................................................................................7
Altium design software .................................................................................................7
Important note on FPGA vendor tools .........................................................................8
Setting up the NanoBoard......................................................................................................9
Testing the PC to NanoBoard connection..................................................................11
Downloading a test project to the NanoBoard......................................................................14
A note on changing FPGA daughter boards ........................................................................17
Troubleshooting NanoBoard connection problems ..............................................................18
Where to go to from here .....................................................................................................18

Operation of the Altium NB1 NanoBoard 19

NB1 NanoBoard board outline .............................................................................................20
NB1 NanoBoard Power Connectors ....................................................................................21
NanoBoard Resources.........................................................................................................21
5V Power Connectors (J6 and J7) ............................................................................21
NanoTalk Configuration Header.................................................................................22
NanoTalk Configuration LEDs....................................................................................22
Master and Slave I/O .................................................................................................24
System Clock .............................................................................................................25
FPGA Daughterboard Connectors (J8 and J9) ..........................................................26
User Board Connectors..............................................................................................28
NEXUS JTAG Connector and Port ............................................................................29
Static RAM, 256 Kb x 8, Configurable........................................................................29
Serial SPI Flash RAM ................................................................................................30
Dual 18 way USER HEADER A and B.......................................................................31
RS232 Serial Port (J1) ...............................................................................................32
CAN Port (J2).............................................................................................................32
PS2 Keyboard Port (J4) .............................................................................................33
PS2 Mouse Port (J5)..................................................................................................33
VGA Port (J3).............................................................................................................33
Audio Codec (J10 In and J11 Out).............................................................................34
Four channel I2C 8-Bit ADC and 10-Bit DAC ............................................................34
LCD character display................................................................................................35
Keypad array, 4x4 ......................................................................................................36

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Magnetic Audio Transducer ....................................................................................... 36

User Dip switch .......................................................................................................... 37
User LED array .......................................................................................................... 37
User Application TEST / RESET Button .................................................................... 37

Advanced NanoTalk Configuration 38

Altium NanoTalk Features ................................................................................................... 38
NanoTalk Operation.............................................................................................................38
Installing NanoTalk on the NB1 NanoBoard – ‘SYSTEM JTAG’ ............................... 38
NanoBoard Default Clock Frequency – ‘CLOCK1…CLOCK3’ .................................. 39
Standalone Configuration – ‘AUTO LOAD FPGA’ ..................................................... 39
Using the NanoBoard Status LEDs – ‘TEST0, TEST1’ ............................................. 40

Updating the NanoBoard firmware 42

Pre-update preparation ........................................................................................................ 42
Erasing the PROM ...............................................................................................................43
Downloading the new firmware............................................................................................ 43
Testing the NanoBoard ........................................................................................................ 44

NanoBoard Test Procedures 46

NanoBoard Test Overview................................................................................................... 46
Test Procedures................................................................................................................... 46
On-Board Voltage Regulation Test ...................................................................................... 48
Programming the On-Board FPGA ...................................................................................... 48
NanoBoard RAM Test.......................................................................................................... 49
Main Functional Test............................................................................................................ 51

Index 57

Revision History 59

Appendix A – NanoBoard and Daughterboard Schematics 59

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About This Manual

This document describes the board level operations of the Altium NB1 NanoBoard. The NanoBoard is
part of a development system that has been designed to allow Altium end users to design and
prototype systems based on FPGA or CPLD (PLD) devices from multiple vendors.
The basic system components are the NanoBoard NB1 mother board, providing development
infrastructure and application specific hardware, and a range of plug-in daughterboards that provide the
target field programmable devices. Typically the target PLD devices will be FPGA or CPLD types. It
provides a general purpose platform with a range of commonly used peripherals.
The NB1 is initially supplied with two daughterboards, the NBP11 Xilinx® Spartan®-3 XC3S1000-
4FG456C and the NBP2 Altera® Cyclone™ EP1C12Q240C7.
The manual includes schematic diagrams of all NanoBoard NB1 circuitry.

Notational Conventions
This document uses the following conventions.
• FPGA or CPLD devices may be collectively referred to as PLD or FPGA
• The NanoBoard may be referred to as the NB1.
• Interactive instructions are shown in a bold typeface, for example:
Continue
View » Devices
• Program listings, program examples and filenames are shown in a mono-spaced typeface, for
example:
Firmware_NB1_6_V1_08.mcs
• Reference to notations on printed circuit boards are referred to in single quotes, for example:
‘SYSTEM JTAG’

Information About Cautions

This manual may contain cautions.

Caution statements look like this.

A caution statement describes a situation that could potentially damage your software, or hardware, or
other equipment. The information in a caution is provided for your protection. Please read each caution
carefully.

Related Documents
Altium Designer - An Introduction software manual

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NanoBoard NB1 Technical Reference

Introduction to the Altium NB1 NanoBoard

This chapter provides a description of the Altium NB1 NanoBoard along with the key features and a
block diagram of the circuit board.

Overview of the Altium NB1 NanoBoard

The emergence of low-cost FPGA and CPLD devices from multiple vendors has resulted in the need
for a state of the art development system. The NB1 NanoBoard, in conjunction with the Altium
Designer PC-based development software allows hardware engineers and embedded systems
developers to develop and evaluate complex programmable logic-based systems.
In addition to providing schematic and PCB tools, the Altium Designer development system also allows
complete FPGA designs to be created, designed and debugged. FPGA projects can be created with
the schematic editor, using supplied schematic library components covering an extensive palette of IP
functions, including a range of industry-standard microcontrollers.
All or parts of an application can be written in VHDL. A range of Tasking embedded-system C
compilers, assemblers and debuggers are also included.
Every functional part of the NB1 NanoBoard was designed entirely with the DXP-based development
system. The NanoBoard was designed to reveal the power of this development system.
The NB1 allows rapid testing of designs for a range of PLD products, consisting of a motherboard with
a variety of commonly used peripherals and a range of plug-in FPGA or CPLD daughterboards.
The NanoBoard includes a unique communications protocol called NanoTalk, that provides connection
between a host PC running the software and the NanoBoard. NanoTalk provides the ability to
daisychain a number of NanoBoards, and communications access from the software to all resources
on the NanoBoard, or daisychained sequence of NanoBoards.

Two NB1 NanoBoards daisychained together

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Figure 1. PC connected to a NanoBoard.

Figure 2. PC with Daisychained NanoBoards and a User board.

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Key Features of the Altium NB1 NanoBoard

The NB1 NanoBoard has the following features:
• Altium NanoTalk parallel PC interface
• NanoTalk daisychain, in and out
• NanoBoard to NanoBoard user-defined communications, in and out
• NanoTalk configuration header
• NanoTalk configuration LEDs
• Xilinx Spartan IIE 100K NanoTalk controller with JTAG accessible flash configuration PROM
• Dual User Board JTAG Headers, 10 way
• Dual 100 way FPGA daughterboard connectors
• Programmable clock 6 to 200 MHz, programmable by Altium Designer or by a Daughterboard
FPGA application
• Fixed 20MHz reference clock
• Dual 5V Power daisychain power connectors with power switch and LED indicator
• RS232 Serial Port – DB9
• CAN Port – DB9
• VGA Port – DB15
• PS2 Mini DIN Mouse Port
• PS2 Mini DIN PC Keyboard Port
• LCD character display, 16 x 2 chars, high contrast, LED backlight
• Magnetic Audio transducer with PWM drive capability
• 8 way DIP switch
• LED array, 8 LEDS
• Serial SPI Flash ROM, up to 2 Mb
• 256 Kb x 8 FPGA configurable SRAM (128x16,128x8+128*8)
• Dual 18 way (20 pin headers) expansion headers with power supply selection links
• Four channel 8 Bit ADC, I2C
• Four channel 10 Bit DAC, I2C
• Screw Terminal Header for ADC and DAC
• ADC/DAC/I2C 14 pin expansion header
• Audio Codec, 8 bit mono with 2.5mm audio jacks
• User application reset/test button

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Functional Overview of the Altium NB1 NanoBoard

Figure 3. A block diagram of the NanoBoard configuration.

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Setting up the NanoBoard

This section gives step-by-step instructions on connecting the NanoBoard to your PC, and testing the
PC to NanoBoard connectivity. We suggest you read this section thoroughly before beginning the
installation and setup process.

CAUTION: Utilize standard antistatic procedures when handling or using the NB1 and
associated daughterboards and plug-ins. Always power the NB1 down when making
changes to the configuration, for example when removing or inserting daughterboards, or
adding or removing plug in devices to the NanoBoards expansion headers.

What’s in the box

A
C

K L
J M
E F
D G
H

Figure 4 - NanoBoard package contents

A – NanoBoard reference manual

B – NanoBoard and stand
C – 4 x Mains power cords (US, EU, UK and Australia)
D – NanoBoard power supply module
E – Altera Cyclone EP1C12 plug in FPGA daughter board
F – Xilinx Spartan-3 XC3S1000 plug in FPGA daughter board

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G – Power supply daisychain connector – for use with multiple NanoBoards

H – NanoTalk loopback cable – used for testing NanoBoard
J – NanoBoard daisychain cable – for connecting multiple NanoBoards
K – User board connector – for connecting to JTAG link on user-designed boards
L – 2 x User I/O connectors
M – Parallel cable – for connecting the NanoBoard to your PC
If any components of the system are missing or appear damaged, please contact your nearest Altium
representative.

System requirements
Before installing the software, please ensure that your computer meets the minimum system
requirements listed below.
Recommended system
To get the most from your Altium design software, we recommend a PC with the following
specifications:
• Windows XP (Professional or Home) or Windows 2000 Professional
• 3 GHz Pentium 4 processor or equivalent
• 1 GByte RAM
• 2 GByte hard disk space (Install + User Files)
• Dual monitors with 1280x1024 screen resolution
• 32-bit color, 64 MB graphics card
• Parallel port
Minimum requirements
The following computer specifications are the minimum needed to get adequate performance from your
design software:
• Windows XP (Professional or Home) or Windows 2000 Professional SP2
• 1.8 GHz processor
• 1 GByte RAM
• 2 GByte hard disk space (Install + User Files)
• Main monitor 1280x1024 screen resolution
• Strongly recommended: second monitor with minimum 1024x768 screen resolution
• 32-bit color, 32 MB graphics card
• Parallel port

Altium design software

To install your Altium design software you will need approximately 1GBytes of free disk space. To
begin the install process simply insert the product CD into your computer’s CD ROM drive. The
Installation Wizard will automatically start and guide you through the installation process.

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If the Installation Wizard does not start automatically, please run Setup.exe located in the \Setup
directory of the program CD.
The first time you run the software you will be required to activate it. Use the Active License options in
on the DXP License Management page that appears in the software to do this.
Once the installation of the software is complete, you should install the necessary FPGA vendor tools –
if not already present – and then connect the NanoBoard to your PC before starting the design system.

Important note on FPGA vendor tools

To place and route the FPGA design for the target FPGA device on the NanoBoard, FPGA vendor
tools are used. The FPGA vendor tools ARE NOT supplied with the system and must be sourced
independently.
Before you can download a design to the NanoBoard you must have the appropriate vendor tools
installed on your computer.
The NanoBoard comes supplied with two FPGA devices housed on plug in daughter boards – an
Altera Cyclone EP1C12 and a Xilinx Spartan-3 XC3S1000. Both of these devices are supported by the
respective vendor’s freely-downloadable tools available on the web, as well as by the commercial
versions of these tools.
In order to use both of the supplied FPGA daughter boards, you will need to install both the Altera and
Xilinx tools.
More information on the vendor tools for the supplied FPGA devices can be found on the respective
FPGA vendor’s web sites.
• Altera Quartus II Web Addition from www.altera.com
• Xilinx ISE WebPACK available from www.xilinx.com
Please note that Altium does not provide technical support for FPGA vendor tools. For information on
installing these tools, please refer to the information provided by the FPGA vendors.

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Setting up the NanoBoard

The NanoBoard is an integral part of Altium’s LiveDesign-enabled platform and allows FPGA designs
to be implemented and tested without the need to manufacture a physical prototype. The NanoBoard is
connected to your PC via the computer’s parallel port. The picture in Figure 5 shows an overview of the
NanoBoard and the location of the main components addressed during installation.

2 3

Figure 5. The NanoBoard. 1 = NanoTalk Parallel connector. 2 = Power switch. 3 = Power supply sockets.
4 = FPGA daughter board connector.

Please Note: Before using the NanoBoard, attach the backplate of the NanoBoard stand using the
thumbscrews provided.

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To set up the NanoBoard, refer to Figure 4 and complete the following steps:
1. Connect the supplied parallel cable to the parallel port of your PC. Connect the header plug of the
parallel cable to the NanoTalk Parallel header socket [1] at the top right of the NanoBoard,
ensuring that the red pin 1 marker on the cable is located on the side closest to the power switch,
as shown below.

2. Select one of the FPGA daughter boards and gently orient it over the daughter board sockets [4] on
the NanoBoard – the sockets are directional to ensure that the daughter board can only be inserted
in the correct orientation. Once located, press the daughter board firmly onto the NanoBoard.

3. Connect the plug of the power supply module to either of the power connectors [3] on the top edge
of the NanoBoard.
4. Connect the mains power cord to the power supply module and plug it in to a standard power
socket.
5. Turn on the NanoBoard power switch [2]. The LED next to the power switch shows that power is
available.

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Testing the PC to NanoBoard connection

Once you have connected the NanoBoard to your PC, you should check that the system software can
connect to the NanoBoard. To do this, follow the steps below:
1. Start your Altium design system by selecting the Altium Designer 6 icon from the Windows Start
menu.
2. The first time the system is run with a NanoBoard connected it will build a cache of supported
programmable devices. A progress dialog will appear on screen during this process. Building the
cache can take several minutes, depending on the speed of you computer. This only needs to be
done once.

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Once the system has started, you will be presented with the Home Page, which provides a jumping
off point to many of the features offered by the system.

3. Click on the Device Management and Connections icon.

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This will open the Devices view. Alternatively, you can select View » Devices from the menus.

4. Ensure that the Live checkbox is enabled and that the Connected indicator is green. This indicates
that the system is connected and communicating with the NanoBoard.

5. If the Device does not show the NanoBoard status as connected or no FPGA icon is visible, refer to
the section Troubleshooting NanoBoard connection problems later in this guide.

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Downloading a test project to the NanoBoard

To ensure that your design system and NanoBoard are functioning correctly installed, follow the steps
below to compile and synthesize an example project and download it the NanoBoard. For this test we
will use the FPGA_LedChaser_NanoBoard.PRJFPG example found in the Altium Designer
6\Examples\FPGA Hardware\LED Chaser - Hardware directory.
1. From the menus select File » Open.
2. Navigate to the Altium Designer 6\Examples\FPGA Hardware\LED Chaser -
Hardware directory.
3. In this directory, open the file FPGA_LedChaser_NanoBoard.PRJFPG. When the project has
loaded, the Projects panel on the left side of the workspace will display the files in this project.
4. If the Devices view is not active, select View » Devices from the menus to display it. The project
open will automatically be assigned to the FPGA device on the active NanoBoard. The screenshot
below shows this for the Spartan daughter board installed.

5. To process the project and download it to the NanoBoard, click the Program FPGA button in the
Devices view.

The system will automatically compile the source project files, synthesize the design, call the vendor
place and route tools to process the design for the target FPGA, and then download the design to the

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NanoBoard. This can take several minutes depending on the speed of your computer and which FPGA
daughter board is installed.

Please note: If the system fails during the Build processes, shown by a purple status indicator, this can
be because the FPGA vendor tools are not correctly installed or have not been properly activated.
Please refer to the information supplied with the FPGA vendor tools for information on installing and
activating these tools.
Once the design has been downloaded all of the process indicators will be green and the Results
Summary dialog will be shown. This indicates that the project has been successfully processed and
downloaded to the NanoBoard. Close the Results Summary dialog.

Congratulations! You have just reconfigured your NanoBoard to operate as a light chaser! If you look at
the NanoBoard you should see that the LED array to the right of the FPGA daughter board displays a
moving pattern.

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One additional thing to take note of is that the Devices view now shows icons representing some
virtual instruments (IO modules) running on the NanoBoard.

In this project, the IO modules are used to control the operation of the LED chase sequence. The icons
in the Devices view shows the system is communicating with these instruments running in the FPGA,
allowing you to interact and control the instruments for development and debugging purposes. Explore
the circuit schematics for more information on the operation of the IO modules. Double-click on an IO
module icon in the Devices view to access the front panel for that device.

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A note on changing FPGA daughter boards

When changing FPGA daughter boards, please take care not to damage the dual connectors that
attach the daughter board to the NanoBoard. The following procedure is recommended:
1. Ensure that the NanoBoard power is switched off.
2. Grip the two sides of the daughter between your thumb and fingers and gently pull the daughter
board upwards. Gently rocking the daughter board from side to side can help loosen the
connectors.
3. As the daughter board disengages, ensure that you keep the daughter board parallel to the
NanoBoard and pull it straight up until both connectors are fully disengaged.

4. Install a new daughter board by gently locating it over the daughter board sockets on the
NanoBoard in the correct orientation. Once located, press the daughter board firmly onto the
NanoBoard.
5. Switch the NanoBoard power on.
The system software interrogates the NanoBoard at regular intervals to determine the FPGA device
installed. If you change daughter boards, the system should automatically detect the change and show
the correct device in the Devices view. When the Devices view is active you can force the system to
poll the NanoBoard by pressing the F5 key.

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Troubleshooting NanoBoard connection problems

If, after completing the NanoBoard setup and installation procedures, the Devices view shows that the
system cannot connect to the NanoBoard or cannot detect the presence of an FPGA on the
NanoBoard, go through the following steps to try to correct the problem:
1. Ensure that the NanoBoard is switched on and that the power LED next to the power switch is
illuminated.
2. Ensure that the NanoBoard to PC cable is correctly plugged in to both the parallel port on the PC
and the NanoBoard.
3. Check that you have correctly installed an FPGA daughter board on the NanoBoard.
4. With the Devices view active (View » Devices), ensure that the Live checkbox is checked, and
select Tools » Refresh All from the menu.
5. With the Devices view active (View » Devices), select Tools » Scan NanoBoard Chain from the
menu. A dialog should appear, listing all the NanoBoard detected.
6. If the NanoBoard(s) are detected correctly, with the Devices view active (View » Devices), select
Tools » Scan Hard Chain from the menu. A dialog should appear, listing all the hard devices
(FPGAs and/or physical processors).
If, after completing all the above steps, the system still cannot establish a connection with the
NanoBoard and FPGA, then please contact your nearest Altium Sales & Support representative.
Please note: The system requires the presence of a working, standard parallel port on your computer.
The parallel port implementations on some computers do not strictly adhere to the standard, which may
cause communications with the NanoBoard to fail. If possible, reinstall the system on a different
computer to determine if this may be the problem.

Where to go to from here

Once you have completed the steps outlined in this guide, your system is installed and ready for use.
To help become familiar with your design system and its features, we suggest you read over the
following learning guides that can be found in the online help system. This can be activated by
selecting Help » Contents from the menus.
Getting Started with FPGA Design
Getting started with embedded software

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Operation of the Altium NB1 NanoBoard

This chapter describes the NB1 NanoBoard, major components, and how they interact. It also provides
information on the NanoBoards various interfaces in detail. NanoBoard schematics are provided in
Appendix A, and should be referred to as the final reference.
The NB1 was designed using Altium’s Schematic and PCB editors, as a two layer printed circuit board.
The internal routing capacity of the FPGA devices used in the NanoBoard and daughterboard has
allowed PCB tracks to be optimally placed to minimize vias and is the main determinant in producing a
two layer design for a relatively complex product. The component side of the PCB has been used for
signal routing, while the reverse side contains mainly power and ground tracks. Power and ground
distribution is facilitated using a star topology. All unused copper areas have been flood filled with
ground.
Many of the NB1 signals, particularly those originating in FPGA devices, have series resistors to
minimize ringing caused by reflection. The NB1 PCB provides a good example of techniques required
for using low cost medium speed FPGA devices.

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NB1 NanoBoard board outline

The NB1 NanoBoard is a 200.5 x 165mm (7.9” x 6.5”) two layer printed circuit board (PCB), powered
by an external 5 Volt regulated supply. Fig 2.1 indicates the layout of the NB1 and its various features.

Figure 6. Physical layout of the NB1 NanoBoard.

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NB1 NanoBoard Power Connectors

The NB1 NanoBoard is powered by a 5 volt regulated supply, available with the NB1. Typical current
requirements for the NB1 without any current supplied to expansion devices is 100 to 500 mA. Two
power connector jacks are provided (J6 and J7). These are connected in parallel so power can be
supplied to a chain of NanoBoards using one of the jacks to power the daisychained NB1s. The NB1
has a power toggle switch with LED indicator. The switch only controls power to the NanoBoard, not to
other NanoBoards in a daisychain configuration. If the total power consumption of a given NanoBoard
configuration, i.e. daisychained and/or with connected expansion devices then a higher current
capacity power supply may be required. Such a power source must provide a regulated 5 volt supply.
The NB1 has on board regulators that provide +3.3 volts, +1.8 volts for the Spartan IIE controller
FPGA, and a second programmed source to provide an appropriate voltage for FPGA device(s) for the
plug-in FPGA daughterboards. Each daughterboard module automatically programs the regulator to
suit its own internal voltage requirements.
Both the 3.3 volt and 5 volt supply buses can be selected to power various expansion devices that can
be connected to the NB1.

NanoBoard Resources
The NB1 has a variety of resources individually wired to target daughterboard FPGA IO pins. These
allow a wide variety of embedded examples to be executed on the NB1, in addition to providing a base
for developing new applications. Altium Designer provides schematic library components that allow the
NB1 resources to be easily incorporated in designs, these are available in the FPGA NanoBoard Port-
Plugin integrated library. An image of each component is shown with the following descriptions.
The library components automatically establish connectivity between the resource and FPGA IO pins,
allowing the same design to be built for different FPGA devices from different manufacturers. Altium
Designer’s Configuration Manager enables a single project to be targeted at different FPGA devices.
Library components can be placed into your FPGA design from the library: \Program
Files\Altium Designer 6\Library\Fpga\FPGA NanoBoard Port-Plugin.IntLib.
NanoTalk is instantiated in a Spartan IIE 100 FPGA, with a partner configuration flash PROM. Both
these devices are JTAG accessible from Altium Designer.

5V Power Connectors
(J6 and J7)
The NB1 requires a regulated 5 volt
supply as its primary power source.
Two parallel-connected jacks are
provided (J6 and J7). J6 is used to
connect a power source, leaving J7
as an output that can be used to
provide power to a daisychained
NB1, i.e. the next NB1 in a
daisychain.

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NanoTalk Configuration Header

Header JP2 allows the insertion of links (jumpers) to configure the operational mode of the NB1
NanoTalk controller and to set the default clock rate.
When no links are inserted, the NB1 is in its default operational state, with a default clock frequency of
50 MHz. This (no links inserted) is the configuration that is appropriate when first using the NanoBoard.
Refer to the Advanced NanoTalk Configuration chapter for details on how the configuration header is
used for advanced debugging, however the ‘AUTO LOAD FPGA’ link can be inserted to cause the
NanoBoard to automatically load the daughterboard FPGA with configuration data from NanoBoard
SPI flash PROM on power up. A valid bit file for the target daughterboard must first be written to the
SPI flash by Altium Designer before this function will operate successfully.
Details on programming the SPI flash PROM can be found in the application note Bootstrapping the
Daughter Board FPGA.

NanoTalk Configuration LEDs

The NanoTalk configuration LEDs (‘SL1..SL8’) indicate various circumstances, in conjunction with
links that can be inserted in header JP2, the NanoTalk Configuration Header. The Advanced NanoTalk
Configuration chapter details the advanced usage of this resource; however with no links installed the
LEDs are interpreted as follows:
SL1 – When the NanoBoard is powered up SL1 should illuminate, indicating that the Spartan IIE 100
NanoTalk controller has been successfully configured.

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SL2 – Illuminated when Hard JTAG signals are received from Altium Designer. This LED is driven by
the Hard JTAG TCK signal. NanoTalk uses a JTAG protocol to communicate with all relevant JTAG
hardware devices on the NanoBoard. So when SL2 illuminates Altium Designer is using the JTAG
protocol to communicate with physical JTAG-equipped hardware devices.
SL3 – Illuminated when Soft JTAG signals are received from Altium Designer. The LED is driven by the
Soft JTAG TCK signal. NanoTalk uses the JTAG protocol to communicate with virtual (soft) devices
instantiated in the daughterboard FPGA, providing resources to debug virtual hardware and embedded
software. So when SL3 illuminates Altium Designer is using a JTAG protocol to communicate with your
FPGA embedded design.
SL4 – Illuminated when SPI signals are received from Altium Designer. Altium Designer uses the SPI
protocol to communicate the SPI hardware devices on the NanoBoard. These include the SPI serial
flash PROM and adjustable clock.
SL5 – Indicates that a valid parallel cable is connected to the NanoBoard.
SL6, SL7 and SL8 – These LEDS provide a status value indicating success or failure in configuring a
daughterboard FPGA from bit file data held in the NanoBoards SPI serial flash PROM resource. The
daughterboard FPGA can be configured by Altium Designer, which occurs when a project is being
developed or debugged, or automatically from NanoBoard serial flash PROM when the NanoBoard is
powered up. The latter option allows the NanoBoard to run a stand-alone application, without being
connected to Altium Designer via the parallel port. The ‘AUTO LOAD FPGA’ link can be inserted to
cause the NanoBoard to automatically load the daughterboard FPGA from NanoBoard serial PROM on
power up. The Advanced NanoTalk Configuration chapter describes how these status LEDS are
interpreted.

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Master and Slave I/O

The NanoBoard can be connected in a daisychain configuration, allowing multiple NanoBoard
applications to be controller by Altium Designer. The Master and Slave I/O headers (HDR2 and HDR5
respectively) can be used to provide an application-defined communication resource between
daughterboard applications on separate NanoBoards in a daisychain. Each header provides four
daughterboard I/O signals. Since the signals Master and Slave I/O headers are connected to
daughterboard FPGA I/O pins, they can also be used for any other application-defined purpose.

Caution: Signals on HDR2 (Master I/O) are also shared with the
NanoBoard NB1 Audio Codec.

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System Clock
The NB1 NanoBoard has an SPI-based system clock generator that provides a fixed 20MHz clock and
a user-programmable clock providing frequencies from 6 to 200 MHz. Both clocks are available in the
daughterboard FPGA, i.e. connected to target FPGA GCLK pins.
On power up the NanoTalk controller configures the adjustable clock to a frequency determined by
links installed on the NanoTalk Configuration Header (JP2) ‘CLOCK0...CLOCK2’ locations. The default
frequency, with no links installed, is 50 MHz.
The adjustable clock can be programmed from a PC with Altium Designer using the Instrument
NanoBoard Controller. This allows frequency presets to common values, as well as any frequency
possible with the ICS clock device.
The adjustable clock can also be programmed by the daughterboard FPGA application at run time, via
the NanoTalk controller to daughterboard SPI interconnect.
The clock device is the ICS307-02. Datasheet available at www.icst.com.

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FPGA Daughterboard Connectors (J8 and J9)

J8 and J9 provide 200 pins that are used to mount an FPGA or CPLD daughterboard. The
daughterboards allow the NB1 NanoBoard to be used with a variety of target PLDs, which can be
FPGA or CPLD based, or a combination of devices. Daughterboards may be constructed with any
configuration that matches the pin out requirements of J8 and J9.
The NB1 daughterboard connectors map all of the NanoBoards I/O resources directly to daughterboard
FPGA or CPLD pins, as if the daughterboards FPGA or CPLD devices were mounted on the
NanoBoard.

In addition to the user-available IO, the daughterboard connectors provide connections for functions
required for the operation of NanoTalk, as follows:
Hard JTAG signals – all daughterboard devices that are JTAG-equipped are connected to signals
FPGA_TMS, FPGA_TCK, FPGA_TDI and FPGA_TDO. This allows the NanoBoard and Altium
Designer to address the daughterboard hardware using the JTAG protocol.
Soft JTAG signals – four FPGA I/O pins are reserved for JTAG signals that are utilized by the user
FPGA application. Altium Designer uses JTAG IP to communicate directly with the FPGA fabric,
allowing applications to be debugged live. These signals (NEXUS_TMS, NEXUS_TCK, NEXUS_TDI

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and NEXUS_TDO) are derived in the NanoBoards NanoTalk controller, implemented in a Spartan IIE
100K on the NanoBoard.
FPGA configuration signals – The NanoBoard can be operated and configured using Altium
Designer for development and debugging, however it is possible to create a standalone NanoBoard
application. Under these circumstances the daughterboard FPGA is configured at power up by the
NanoTalk controller, using data stored in the NanoBoards SPI serial flash memory resource.
Details on programming the SPI flash PROM can be found in the application note Bootstrapping the
Daughter Board FPGA.
Daughterboard identification signals – FPGA devices from different manufacturers and families
require differing auto configuration processes, so it is necessary for the NanoTalk controller to be able
to identify the family. Four signals (FPGA_ID0 … FPGA_ID3) are hardwired on the daughterboard to
provide the required identification to the NanoTalk controller.
Daughterboard to NanoBoard SPI bus – SPI devices on the NB1 are accessible from both Altium
Designer and the daughterboard. The NB1’s NanoTalk controller provides an SPI path from the
daughterboard to each of the NB1 SPI devices, i.e. the SPI serial flash memory and the programmable
clock. Daughterboard signals SPI_DIN, SPI_DOUT, SPI_CLK, SPI_SEL and SPI_MODE provide this
connectivity. In operation the daughterboard application communicates with the NanoTalk controller to
establish a path between the application and a specific NB1 SPI device then uses the SPI protocol
associated with the selected device to communicate with it.
Daughterboard auxiliary signals – future daughterboards are planned that require additional signals,
for example to provide resources for configuring daughterboard devices that require special
programming voltages. The four daughterboard auxiliary signals are FPGA_AUX0…FPGA_AUX3.
J8 and J9 provide three power supplies to the daughterboard, as well as ground signals. The power
supply voltages are 5V, 3.3 volts and a third programmable supply providing the internal voltage for the
target FPGA. The voltage programming signals are defined by the daughterboard, i.e. the
daughterboard determines the voltage supplied by a regulator on the NanoBoard (U11).

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User Board Connectors

The NB1 includes 2 User Board JTAG headers, User Board A (HDR6) and User Board B (HDR7). Use
these headers to include a User-designed board in the hard and soft JTAG chains, for design
download and debugging from within the software.
The presence of a User Board is determined by the signal level on pin 10 of the header, if this is low
the NanoBoard controller will route both the Hard and Soft JTAG chains via the header. If the User
board does not support the soft chain then route pin 5 (TDI_SOFT) to pin 6 (TDO_SOFT).
BSDL data for devices not known to the system can be added in the folder \Program
Files\Altium Designer 6\Library\Bsdl\Generic. Refer to the text files in this folder for
more details.

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NEXUS JTAG Connector and Port

The Nexus, or soft devices chain is implemented in the FPGA design by the inclusion of the
NEXUS_JTAG_CONNECTOR, which takes 4 pins on the target FPGA. The pin numbers will be
displayed on the schematic next to the component symbol when it has been synthesized for the target
device.
This is wired to the NEXUS_JTAG_PORT, the presence of which instructs the software to wire all
components that include the parameter NEXUS_JTAG_DEVICE=True into a JTAG chain.

Static RAM, 256 Kb x 8, Configurable

The NB1 provides two 128k x 8 static ram devices (RAM0-U15 and RAM1-U14), directly connected to
I/O pins on the target FPGA of an installed daughterboard. The SRAM devices have a common Chip
Select (CS) and address (RAM_ADDR0 - RAM_ADDR16) signals, but separate 8 bit data bus and
RD/WR signals for each chip.
The memory resource can be application-configured as single 128k x 16 address space, a single 256k
by 8 space, or two 128k x 8 spaces.
The NanoBoards LCD display is mapped into the same address space as RAM0. If the LCD is not
used in an application the LCD_E (active high) signal must be held low. Similarly, if the SRAM is not
used in application the memory CS (active low) signal must be held high, to eliminate bus contention. If
both LCD and SRAM are used in the same application the LCD_E signal and the memory CS signal
must be generated by the application’s memory mapping logic.
The 128k x 8 SRAM devices are IDT71V124SA15Y (access time = 15 nS).

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Serial SPI Flash RAM

The NanoBoard NB1 has a serial flash RAM resource, in two ST M25P40 low-cost 4-Mbit devices. The
NanoBoard PCB provides footprints for both M25P40 and M25P80 devices (8-Mbit devices).
The SPI flash RAMs can be erased or programmed by Altium Designer, via the NanoBoard Controller
instrument. The M25P40 and M25P80 devices support a serial data rate of 25MHz. Datasheets are
available at www.st.com.

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Dual 18 way USER HEADER A and B

A total of 36 daughterboard FPGA IO signals are terminated on NanoBoard 20 pin headers ‘USER
HEADER A’ (HDR9) and ‘USER HEADER B’(HDR10), 18 signals per header. These headers also
provide ground and either 3.3 volt or 5v power supplies, selectable using 4 pin supply select headers
‘JP5’ and ‘JP6’ respectively.
‘USER HEADER A’and ‘USER HEADER B’are provided to allow user defined hardware to be
interfaced to the daughterboard FPGA. Since the USER HEADER I/O can be configured as either input
or output, they are not provided as a NanoBoard component.
A range of devices with compatible 20 pin IDC header interfaces are available, e.g. www.burched.com.

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RS232 Serial Port (J1)

J1 (DB9F) provides a DTE RS232 port, with signals TXD, RXD, RTS and CTS. These signals are
derived from the daughterboard FPGA. RS232 level translation is provided by a MAX232 device.
www.maxim-ic.com.

CAN Port (J2)

J2 (DB9M) provides a CAN protocol transceiver, interfaced to two daughterboard FPGA I/O pins.
Header JP1 allows the user to insert a CAN load and configure the transceiver speed option.
The transceiver device is Microchip MCP2551, datasheet available at www.microchip.com.

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PS2 Keyboard Port (J4)

J4 (MINIDIN) provides a standard PS2 port, nominally for use with a PC keyboard. The port is directly
connected to daughterboard FPGA I/O pins.

PS2 Mouse Port (J5)

J5 (MINIDIN) provides a standard PS2 port, nominally for use with a PC mouse. The port is directly
connected to daughterboard FPGA I/O pins.

VGA Port (J3)

J5 (DB15) provides a VGA-compatible RGB video monitor port. The port is configured with two bits per
color, a total of six bits per pixel or 64 colors. The port is directly connected to six daughterboard FPGA
I/O pins.

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Audio Codec (J10 In and J11 Out)

The NanoBoard provides an SPI-based 8bit audio codec, together with relevant analogue pre and post
conditioning circuitry, terminated with stereo input and output jacks J10 and J11. It’s possible to
connect high impedance stereo headphones to J11.
The gain of the audio input stage is adjustable with ‘VR2’ over a range from 0.1 to 10. The NanoBoard
is shipped with the voltage gain set to 1.0. The built-in anti-aliasing and output filters are optimized for
an audio sample rate of 22050 Hz.

Caution: Some NanoBoard NB1 Audio Codec SPI signals are shared with HDR2 (Master I/O).

The SPI audio codec is Maxim MAX1104. A datasheet is available from www.maxim-ic.com.

Four channel I2C 8-Bit ADC and 10-Bit DAC

The NB1 is equipped with general purpose analogue to digital and digital to analogue converters, both
interfaced using the I2C protocol. The analogue signals are available via a screw terminal strip TS1,
providing four analogue inputs and four analogue outputs as well as a filtered 3.3V analogue supply
and ground. The same analogue signals are also available via HDR8, which additionally provides I2C
signals SDA and SCL and a 5 volt supply and power ground.
Digital to analogue conversion is provided by a Maxim MAX5841MEUB 8 bit DAC. The analogue to
digital conversion is provided by a Maxim MAX1037EKA-T 8 bit ADC.
The reference supply for the DAC is user-selectable via header JP4. The reference voltage can be the
analogue 3.3 volt supply (link on JP4 pins 3 and 4), or a precision 2.0 volt reference provided by the

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ADC converter chip. The 2.0 volt reference is derived from the ADC AIN3 pin, which can be
programmed either output the reference voltage or serve as the fourth ADC input.
The MAX1037 ADC converter provides four multiplexed analogue inputs, selectable by application
software via the I2C connection.
Datasheets for the MAX5841MEUB and the MAX1037EKA-T are available from www.maxim-ic.com.

LCD character display

The NB1 provides a 16 character by two line industry-standard LCD display, with a LED backlight
(LCD1). The LCD is memory-mapped to the same address space as the 128k SRAM RAM0. Internal
user-provided address mapping must be provided if the SRAM and LCD are used in the same
application.
The LCD may be mapped into any four byte section of the RAM0 address space by gating the LCD_E
(enable) signal. If the LCD is not used in an application the LCD_E (active high) signal must be held
low. Similarly, if the SRAM is not used in application the memory CS (active low) signal must be held
high, to eliminate bus contention. If both LCD and SRAM are used in the same application the LCD_E
signal and the memory CS signal must be generated by the application’s memory mapping logic.

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Keypad array, 4x4

User input can be entered using the keypad array, which consists of 16 miniature pushbuttons (SW1 ...
SW16) arranged in a 4 x 4 matrix. The keypad is organized so that a row-column scanning process can
read the status of each key.
The keypad has an escutcheon housing that features replaceable keypad overlays. The NB1 is
provided with an overlay organized in a similar way to a mobile phone keypad, though key assignment
is entirely defined by the user application.

Magnetic Audio Transducer

The NB1 has a magnetic audio transducer (‘SPKR1’) driven by a daughterboard FPGA signal. The
transducer may operate as a beeper when driven by audio frequency square-wave signals.
Alternatively the transducer may be driven by a pulse-width-modulated signal to produce more complex
sounds. The NB1 also has an audio codec for high quality 8 bit audio.

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User Dip switch

The NB1 provides an 8 way dip switch S2, each switch connected to an individual daughterboard
FPGA I/O signal. The dip switch is wired as an active low device, i.e. when the each switch is ON the
signal produced is low.

User LED array

The NB1 has eight red LEDs (‘LED0 ... LED7’), each driven by a separate daughterboard FPGA
signal. The LED signals are active high, i.e. a high level on the LED signal illuminates the LED.

User Application TEST / RESET Button

The NB1 has a button (SW17) labeled ‘TEST/RESET’ that is connected to daughterboard FPGA I/O
signal. The button’s function is entirely determined by the user application, i.e. it has no intrinsic
function unless defined by the user application.

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Advanced NanoTalk Configuration

This chapter describes the features and operation of the NanoTalk interface in detail and provides a
means of testing the NanoBoard for correct operation.

Altium NanoTalk Features

The Altium NanoTalk protocol provides a communication path between a PC running Altium Designer
and one or more NanoBoards like the NB1. Altium NanoTalk is implemented in a Spartan IIE 100k
FPGA device, U8. NanoTalk is field-upgradeable, by using Altium Designer to install configuration data
in U5, a Xilinx XCF01SVO20C flash configuration device.
Altium Designer uses NanoTalk to communicate with all appropriate resources (detailed in the
Operation of the Altium NB1 NanoBoard chapter) on each NanoBoard in a daisychain.
In addition to providing communications with NanoBoard resources, NanoTalk also provides JTAG
interfaces for communicating with user-supplied development boards. The NanoBoard NB1
implements two such ports, ‘USER BOARD A’ (HDR6) and ‘USER BOARD B’ (HDR7). These ports
provide conventional hardware JTAG communications (Hard JTAG), and additionally Altium Nexus
JTAG (Soft JTAG) communications if the user board(s) can support this feature.
NanoTalk can be configured using the NanoTalk configuration header JP2. The NanoTalk controller is
equipped with eight LEDs (‘SL1…SL8’) that can be used to indicate activity on various Hard JTAG and
Soft JTAG data paths, depending upon links inserted in header JP2.
NanoTalk has been designed to be plug-and-play, in the sense that all NanoTalk communications
paths automatically configure when daisychains or user board headers are connected. Altium Designer
scans the NanoTalk system and automatically maintains a map of all Hard JTAG and Soft JTAG
devices.

NanoTalk Operation
The NB1 uses the PC parallel port to connect the PC and the first NanoBoard in a daisychain. Future
versions of the NanoBoard may utilize USB or other protocols to provide this link.
Additional NanoBoards are connected to the first using 10 way IDC ribbon cables from the ‘NanoTalk
Slave’ (HDR4) on the first NanoBoard in a chain to ‘NanoTalk Master’ (HDR1) on the next NanoBoard in
the daisychain.
NanoTalk is run-time configurable with links installed on ‘JP2’. The default configuration is with no
links installed.

Installing NanoTalk on the NB1 NanoBoard – ‘SYSTEM JTAG’

The NB1 NanoBoard is shipped with NanoTalk installed, but future revisions of NanoTalk can be
installed at any time. To reconfigure NanoTalk JP2 link ‘SYSTEM JTAG’ must be installed. With this
link installed Altium Designer has Hard JTAG access only to U8 and U5, all other resources are
invisible to the software. In this mode it is possible to re-program U5 with configuration data loaded into
U8 on power up. This is described in detail in the section Updating the NanoBoard firmware.

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NanoBoard Default Clock Frequency – ‘CLOCK1…CLOCK3’

On power up the NanoTalk programs the NanoBoard system clock to a default frequency. With no links
installed this is 50 MHz; however other default clocks are possible, as follows:

CLOCK0 CLOCK1 CLOCK2 Default NanoBoard Clock

INSERTED 10 MHz

INSERTED INSERTED 20 MHz

INSERTED 30 MHz

INSERTED INSERTED 40 MHz

50 MHz

INSERTED INSERTED INSERTED 60 MHz

INSERTED INSERTED 75 MHz

INSERTED 100 MHz

Standalone Configuration – ‘AUTO LOAD FPGA’

The NB1 NanoBoard can be configured by Altium Designer during the development and debugging of
an application. The NanoTalk controller can also automatically configure the daughterboard FPGA at
power up, using configuration data stored in NanoBoard SPI flash memory (U6 and/or U7).
This occurs when valid configuration data for the target daughterboard FPGA is present in U6/U7 and
JP2’s ‘AUTO LOAD FPGA’ link is installed.
Altium Designer provides facilities to store a configuration bit file in U6/U7, when the target FPGA
application has been developed and debugged.
With no links installed in JP2’s ‘TEST0’ and ‘TEST1’ locations, LEDs ‘SL6’, ‘SL7’ and ‘SL8’ in
combination indicate the status of the auto load process as follows:

SL8 SL7 SL6 Auto Load Status

OFF OFF OFF No errors

OFF OFF ON Configuration failed: SPI memory did not respond

OFF ON OFF Configuration failed: No FPGA detected

OFF ON ON Configuration failed: An unknown FPGA was detected

ON OFF OFF Configuration failed: FPGA did not respond to PROGRAM

ON OFF ON Configuration failed: FPGA did not acknowledge load

ON ON OFF Configuration failed: FPGA indicated a load error

ON ON ON Configuration successful

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Using the NanoBoard Status LEDs – ‘TEST0, TEST1’

When debugging applications it is useful to have a visual indication of communications occurring on the
NanoBoard. LEDs SL1…SL8 are utilized to this using JP2’s ‘TEST0’ and ‘TEST1’ links.
With no links installed in ‘TEST0’ or ‘TEST1’ the behavior of SL1..SL8 is as described on the previous
page. The following tables indicate the functions of SL1..SL8 with all possible combinations of ‘TEST0’
and ‘TEST1’ links.

No TEST Links Installed – General Status and Configuration Errors

LED Interpretation

SL1 Always on (Motherboard FPGA has been configured)

SL2 Hardware device chain activity (Driven by TCK)

SL3 Software device chain activity (Driven by TCK)

SL4 SPI Bus activity (Driven of CLK)

SL5 Parallel Port cable detect

SL6 Configuration status code

SL7 Configuration status code

SL8 Configuration status code

TEST0 installed – Alternate Status

LED Interpretation

SL1 Always off. (Allows LNK7 to double up as a simple logic probe)

SL2 Hardware device chain activity (Driven by TDO)

SL3 Software device chain activity (Driven by TDO)

SL4 SPI Bus activity (Driven by DOUT)

SL5 Parallel Port C_CTRL status.

SL6 User Board A or B cable detect.

SL7 NanoTalk Master or Slave cable detect.

SL8 NanoTalk MODE pin activity.

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TEST1 installed – USER BOARD A and B Status

LED Interpretation

SL1 USER BOARD A Hard JTAG TDI Activity

SL2 USER BOARD A Hard JTAG TDO Activity

SL3 USER BOARD A Soft JTAG TDI Activity

SL4 USER BOARD A Soft JTAG TDO Activity

SL5 USER BOARD B Hard JTAG TDI Activity

SL6 USER BOARD B Hard JTAG TDO Activity

SL7 USER BOARD B Soft JTAG TDI Activity

SL8 USER BOARD B Soft JTAG TDO Activity

TEST0 and TEST1 installed

This combination is reserved.

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Updating the NanoBoard firmware

The NanoBoard firmware is the program that is loaded into the NanoBoard Controller when the board
is powered-up. The NanoBoard uses a Xilinx Spartan IIE-100K device (XC2S100E) as the controller for
the board. Referred to as the NanoBoard Controller, this device (U8 on the board) communicates with
the host PC via NanoTalk, managing JTAG communications with the following:
• FPGA Daughter Board
• Master/Slave daisy-chain
• User Board connectors (A and B)
• Flash RAMs (U6 and U7)
• The SPI Master clock.
The NanoBoard Controller also manages the following two areas of the board:
• LEDs SL1-SL8
• The following jumpers on JP2:
AUTO LOAD FPGA
CLOCK0
CLOCK1
CLOCK2
USER A – BYPASS SOFT
USER B – BYPASS SOFT
TEST 0
TEST 1
The firmware that is loaded into the NanoBoard Controller is stored in a Xilinx Serial PROM device
(XCF01S). This is U5 on the board.
On power-up, the firmware is automatically loaded into the NanoBoard Controller.

Pre-update preparation
Before the new version of firmware can be downloaded to the Serial PROM, the NanoBoard must first
be prepared as follows.
1. Turn off the NanoBoard.
2. Remove any FPGA Daughter Board that is currently plugged in.
3. Insert a jumper at JP2 ‘SYSTEM JTAG’ on the NanoBoard (to the bottom left of the parallel cable
connector). This is a fixed function jumper which, when inserted, switches control of the NanoBoard
from the NanoBoard Controller (Spartan IIE-100K) to a simple hardware chain, which involves the
NanoBoard Controller and the Xilinx Serial PROM. These will display in the Hard Devices chain in
the Devices view, as shown in Figure 7.
4. Power-up the NanoBoard.

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Erasing the PROM

Within the Altium Designer application, open the Devices view, if not already open. Ensure that the
Live check box is checked as this enables the auto-board-recognition system.
With the jumper inserted, the Xilinx Serial PROM device will appear in the Hard Devices chain, as
shown in Figure 7.

Figure 7. Accessing the Serial PROM device.

The Xilinx Serial PROM is a Flash memory device. Before it can be programmed with the new
firmware, it must first be cleared. To do this, right-click on its icon in the Hard Devices chain (Platform
Flash) and choose Reset Hard Device from the pop-up menu.
The erasing process will proceed, with progress shown in Altium Designer's Status bar. The process
takes approximately 15 seconds to complete.

Downloading the new firmware

The configuration for the Xilinx Serial PROM device is stored in a PROM file, using the Intel MCS-86
format. This is an ASCII hex file with extension .mcs.
To download the new configuration, right-click on the icon for the PROM in the Hard Devices chain of
the Devices view and select Choose File and Download from the pop-up menu.
The Choose Programming File For Xilinx XCF XCF01SVO20C dialog appears. Use this dialog to
navigate to the required programming file ( *.mcs) and click Open. By default, this file is located in the
\Program Files\Altium Designer 6\System folder.
A confirmation dialog will appear, asking whether you wish to verify the programming (of the PROM).
At this stage, the new firmware has not been downloaded. Click Yes to proceed with the download and
verification cycle.

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The download and verification will take approximately 30-40 seconds to complete. The progress is
shown in Altium Designer's Status bar. At the end of the cycle, an information dialog will appear with
the result of the download.
If any errors occur during the download and verification cycle, a warning dialog will appear. If this
happens, power-down the NanoBoard for a few seconds and then run the whole process again –
including the erasure of the PROM device's memory.

Testing the NanoBoard

Once the Xilinx Serial PROM device has been successfully programmed, the new firmware can be
tested as follows.
1. Power-down the NanoBoard and plug-in an FPGA Daughter Board.
2. Remove the jumper from JP2 ‘SYSTEM JTAG’.
3. Power-up the NanoBoard.
4. Ensure that the Live check box (at the top left of the Devices view) is checked to enable the auto-
board-recognition system.
5. In the Devices view, press F5 (Refresh). This forces a scan of the hardware to detect which
devices are currently connected. The NanoBoard Controller for the connected NanoBoard will
automatically be detected and appear in the NanoBoard Controllers chain. The version of the
firmware currently being used by the Controller is reflected beneath the Controller's icon (e.g.
V1.1.18). The FPGA device on the Daughter Board should be automatically detected and appear in
the Hard Devices chain.
6. Open an FPGA project that includes Nexus-enabled devices (e.g. Microprocessors, Counters,
Logic Analyzers) and program the FPGA on the Daughter Board. This will test that the Soft Devices
chain is functioning correctly.

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NanoBoard Controller chain

FPGA device on Daughter

Board detected and displayed
in Hard Device chain

Soft Device chain

Figure 8. Target FPGA device detection and test of the Soft Devices chain.

7. With the chosen design running in the FPGA, double-click on the icon for the NanoBoard Controller
(in the NanoBoard Controller chain of the Devices view). The Instrument Rack for the NanoBoard
Controllers will appear. Use the Instrument Panel to change the system clock frequency. This will
write the new clock frequency to the system clock, which, being an SPI device, will test that
communication to SPI devices is working correctly.
As well as writing the new frequency to the clock, the value will also be stored in the NanoBoard
Controller and will be read back to verify the change. The new frequency is persistent across
design sessions with respect to the software, but not persistent across hardware sessions.
Therefore, closing the application, relaunching and opening an FPGA project will result in the last
clock frequency entered being used. However, cycling the power on the NanoBoard will result in the
default clock frequency (50MHz) being used because the register used to store the chosen clock
frequency in the NanoBoard Controller is cleared on power-down.

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NanoBoard Test Procedures

This chapter describes test procedures for the NB1 NanoBoard, allowing the user to test the NB1
NanoBoard and verify correct operation.

NanoBoard Test Overview

The NB1 NanoBoard and its associated FPGA daughterboards are reconfigurable devices, providing a
platform that can be easily programmed to a large number of different applications. One such
application utilizes the reconfigurable nature of the NB1 to provide acceptance self-testing, either in
production or in the user environment. These test procedures are provided as an example in the Altium
Designer examples folder.

Test Procedures
Test procedures were developed to test the NB1 NanoBoard during its development phase to verify
correct operation. The test procedures allow the NB1 to be tested without any additional hardware, with
simple ribbon cables and with some additional electronic hardware. Thus there are several levels of
test setups, depending on the additional test hardware available:
On-Board Voltage Regulation Test
This test should be performed before the DUT is connected to any external hardware. It checks for the
integrity of the on-board voltage rails.
It requires:
• Current limited power supply unit (PSU) with voltage and current meter
• Digital Multi-Meter (DMM)
On-Board FPGA Programming
This can be performed with the DUT alone as it is shipped with no additional hardware.
RAM Test
This can be performed with the DUT alone as it is shipped with no additional hardware. The RAM test
firmware also allows the NanoBoard running it to act as a tester for the CAN bus communications.
Main Functional Test
Some tests can be performed without additional hardware, while others require either loop-back
cables, external hardware such as keyboard and monitor or custom test hardware such as the real time
clock adapter PCB.
The following matrix shows what functional blocks can be tested with the different test setups.

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Voltmeter/Ammeter

2nd NanoBoard

3rd NanoBoard
Loopback plug

PS2 Keyboard
Test Page

RTC PCB
Monitor
Cable
Power Supply and Rail Regulators 48 9
Power Toggle Switch 48
Power Indicator LED 48
PC Parallel Port Interface 48
Configuration Flash (U17) 48
User Flash (U5,U6) 54
JTAG Multiplexer (U4) 48
Clock Generator (U12) 54
RAM 49
Mode Selector Header (JTAG Link) 54
Speaker 55
LCD Display 53
LCD Backlight 55
16 Key Keypad 54
TEST/REST Button 53
User LEDs (LED0..LED7]) 53
FPGA Daughterboard Connector 49
VGA port 55 9
A/D and D/A 55 9
Audio Codec (U21) 55 9
RS-232 Port 54 9
Master I/O Port 55 9
Slave I/O Port 55 9
PS2 Keyboard Port 54 9
PS2 Mouse Port 54 9
CAN-Bus Port 55 9
NanoTalk Master Port 51 9
NanoTalk Slave Port 51 9
Crystal Oscillator Frequency 55 9
Clock Generator 54
User Headers 54 9
External I2C Bus 52 9

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On-Board Voltage Regulation Test

This test must be performed before any other hardware is connected to the DUT. It is performed to
make sure that no catastrophic faults in the power supply exist that could potentially damage external
hardware.
Parts Required:
• Variable Laboratory Power Supply Unit (PSU) with integrated voltage and current meters and
variable current limit.
• Cable with DC jack, wired centre positive to connect PSU to J6 on DUT
• Digital Multi-Meter (DMM)
Test Procedure:
• Remove all cabling and any daughterboards from the DUT.
• Set PSU output voltage to 5V±0.2V
• Short out PSU output and set current limit to 1A
• Toggle On/Off switch S1 and verify the functionality of power LED (‘LED8’), otherwise disconnect
PSU and reject DUT.
• Connect PSU output Jack to J6 on DUT, toggle On/Off switch S1 and verify the functionality of
power LED ‘LED8’ and verify current is 100mA ±20mA in the ON position and <0.1mA in the OFF
position, otherwise disconnect and reject DUT.
• Connect negative lead of multimeter to a GND pin on the DUT, for example ‘HDR14’ and verify the
output voltage on the centre pin of U9 is 1.8±0.1V, otherwise disconnect PSU and reject DUT.
• Verify the output voltage on the centre pin of U10 is 3.3±0.1V, otherwise disconnect PSU and
reject DUT.
• Verify the output voltage on the centre pin of U11 is 1.8±0.1V, otherwise disconnect PSU and
reject DUT.
• Switch off ‘S1’ and install Altera Cyclone EP1C12Q240C7 daughterboard in socket. Verify the
output voltage on the centre pin of U11 is 1.5±0.1V, otherwise disconnect PSU and reject DUT.

Programming the On-Board FPGA

This will load the firmware into the NanoBoard’s on-board Xilinx Spartan XC2S100E FPGA. Refer to
the section Updating the NanoBoard firmware in this manual for a more detailed description of this
process.
Parts Required:
• PC running Altium Designer
• NanoBoard Power Supply
• NanoBoard Ù PC NanoTalk Parallel Port Cable
Test Procedure:
• Connect NanoBoard power supply to J6, turn off S1
• Connect NanoTalk Parallel Port Cable from PC parallel port to HDR3 on DUT
• Insert Jumper into JP2 ‘SYSTEM JTAG’ position
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• Start Altium Designer and load Workspace NB1 Testing.DsnWrk, if not already loaded. Select
View » Devices and verify the Connected indicator status is green.
• Right-Click on the Xilinx Platform Flash device and select Choose File and Download, then
select the appropriate firmware MCS
file. Confirm Yes when prompted for
Verify Programming and verify correct
programming of the device.
• Remove Jumper from JP2 ‘SYSTEM
JTAG’ position.
• Switch off S1, wait for ~1s, then switch
‘S1’ back on. Uncheck the Live
checkbox ( )and recheck it again.
• Verify the green NanoBoard symbol is present in the JTAG chain.

NanoBoard RAM Test

This test will verify the integrity of the 256k x 8 Static Ram. Since the code executes from the
daughterboard FPGA’s internal RAM which is limited (8K for the Spartan device and 32K for the
Cyclone), this test is a separate project. In addition to the RAM test, the firmware can also echo CAN
bus signals for testing CAN bus communications with a second NanoBoard.
Test Setup:
• Open the project NanoBoardMemoryTester.PRJFPG
• Switch off ‘S1’ to power down the DUT
• Insert Xilinx® Spartan®-3 XC3S1000 daughterboard into daughterboard socket
• Switch on S1 and verify that the Spartan3 XC3S1000 appears in the JTAG chain.
• Select NanoboardMemoryTester / Memory Tester Spartan from the dropdown configuration
options list in the Devices view, then select Program FPGA ( ).
• Verify that the TSK51A_D processor appears in the JTAG chain. If the
embedded software status indicator is not green (Up to Date) choose
Compile first to compile the source. The indicator is now showing the green
Up to Date message.
• Choose Download to download the firmware.
Test Procedure:
• Adjust ‘CONTRAST’ pot (VR1) until top row on LCD is just visible.
• Right-click on the TSK51A_D processor icon and choose Continue
• The 256kB of RAM are split into 4 banks of 64kB. The top four addresses in each bank are
decoded to the LCD display which shares the data bus with RAM. The embedded software will
perform a basic memory test on each bank and report the result. Each bank should result in an –
OK message on the LCD display.
• The embedded software will then go into CAN bus echo mode which is used for the main test in
conjunction with a second NanoBoard.
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• Adjust ‘CONTRAST’ pot (VR1) for best contrast.

• Connect two 10 way to 20 way User Board JTAG cables from ‘USER HEADER A’ Ù ‘USER
BOARD A’ and ‘USER HEADER B’ Ù ‘USER BOARD B’. After a few seconds, two more
NanoBoard Icons should appear in the JTAG chain:

• Remove both User Board JTAG cables.

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Main Functional Test

This test tests as many on-board resources as practical. The sequencing of the tests is split into three
parts:
1. Tests that can be performed without additional hardware.
2. Tests that can be performed with simple loop-back cables and standard components (e.g. PS2
Keyboards).
3. Tests that require special cables and hardware.
Test Setup:
The following section describes the test setup required for running all tests. A subset of tests can be
performed if not all external cables and test-boards are available. The tests that require special
hardware will fail if the hardware is not connected.
Parts Required:
• Two known good NanoBoards, in the state at the end of the RAM Test.
• NanoBoard Power supply Plugpack (PSU)
• Two 2.5mm DC♂ Ù 2.5mm DC♂ cables
• 3.5mm stereo ♂ Ù 3.5mm stereo ♂ shielded audio cable
• Two 500mm 10-way NanoTalk IDC ribbon cables
• 300mm 10-way NanoTalk IDC ribbon cable
• 20-way IDC User Header Loop-back cable
• DB9 ♂ RS-232 Loop-back Adapter (RXDÙTXD and RTSÙCTS)
• DB9 ♀ Ù ♀ CAN cable
• Two PS2 Keyboards
• VGA color monitor
• Real Time Clock (RTC) Adapter PCB
• Small screwdriver
Test Preparation:
• Open the project NanoBoardTester.PRJFPG
• Turn off ‘S1’ on all three NanoBoards.
• Connect NanoBoard PSU Plugpack to ‘J6’ on DUT
• Connect DC cable from ‘J7’ on DUT to ‘J6’ on second NanoBoard. Label second NanoBoard.
• Connect DC cable from ‘J7’ on second NanoBoard to ‘J6’ on third NanoBoard. Label third
NanoBoard.
• Connect 500mm 10-way NanoTalk IDC ribbon cable from ‘NanoTalk Slave’ (HDR4) on DUT to
‘NanoTalk Master’ (HDR1) on the 2nd NanoBoard
• Connect 500mm 10-way NanoTalk IDC ribbon cable from ‘NanoTalk Master’ (HDR1) on DUT
to ‘NanoTalk Slave’ (HDR4) on the 3rd NanoBoard

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• Connect 300mm 10-way NanoTalk IDC ribbon cable from ‘Master I/O’ (HDR2) to ‘Slave I/O’
(HDR5) on DUT
• Connect 20-way IDC User Header Loop-back cable from ‘USER HEADER A’ (HDR9) to ‘USER
HEADER B’ (HDR10) on DUT
• Set jumper ‘JP4’ to position ‘3V3’
• Insert RTC Adapter PCB into ‘I2C/DAC/ADC’ header (HDR8) on DUT
• Connect 3.5mm stereo ♂ Ù 3.5mm stereo ♂ shielded audio cable from ‘AUDIO OUT’(J11)Ù
‘AUDIO IN’(J10) on DUT
• Plug DB9 ♂ RS-232 Loop-back Adapter into DUT’s RS232 connector
• Plug VGA color monitor into DUT’s VGA connector
• Plug the two PS2 keyboards into the DUT’s two PS2 sockets (‘J4, J5’)
• Connect DB9 ♀ Ù ♀ CAN cable from CAN-Socket on DUT to CAN-Socket on the 3rd NanoBoard.
• Switch all 8 DIP-switches on DUT to the “off” position
• Remove ‘NanoTalk Parallel’ cable from DUT and connect to ‘NanoTalk Parallel’
header on the 3rd NanoBoard.
• Power up all three NanoBoards by turning on S1 on each board
Test Procedure:

• Uncheck the Live checkbox ( ) and recheck it again.

• Verify that the Altium Designer Devices View shows three NanoBoards in the JTAG chain, the
leftmost will represent the 3rd NanoBoard, the middle DUT and the rightmost the 2nd NanoBoard:

3rd NB DUT 2nd NB

This verifies the correct operation of the NanoTalk Master and Slave connection.
• Disconnect ‘NanoTalk Slave’ connector from DUT. Verify that the 2nd NanoBoard disappears
from the JTAG chain and the Altium Designer Devices view is now showing two NanoBoard
Controller icons, the left representing the 3rd NanoBoard, the right representing DUT:

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3rd NB DUT

• Highlight the Spartan2E FPGA on the 3rd NanoBoard and in the configuration dropdown select
NanoboardMemoryTester / Memory Tester Spartan, then select Program FPGA
.
• Highlight DUT Spartan2E FPGA and in the configuration dropdown select NanoBoardTester /
NanoBoard Tester Spartan, then select Program FPGA .
• Verify that both TSK51A_D processors are present in the JTAG chain.
• Highlight the 3rd NanoBoard TSK51A_D processor. If the firmware status indicator is not green
(Up to Date) choose Compile first to compile the source. The firmware indicator is now showing
the green Up to Date message.
• Choose Download to download the firmware.
• Right-click on the 3rd NanoBoard TSK51A_D processor icon and choose Continue. Wait for the
memory test to conclude and the message Ready for CAN Bus Echo Test to appear on the 3rd
NanoBoard’s LCD display.
• Highlight DUT TSK51A_D processor. If the firmware status indicator is not green (Up to Date)
choose Compile first to compile the source. The firmware indicator is now
showing the green Up to Date message.
• Choose Download to download the firmware. We are now ready to conduct the main test.
• Right-click on the 3rd NanoBoard TSK51A_D processor icon and choose Continue.
• The main test sequence will run automatically. Any errors during the test will be indicated by an
ERROR message on the LCD display and an acoustic error indication. Error messages must be
acknowledged by pressing the ‘TEST/RESET’ button (SW17).
The main test sequence consists of the following tests:
• LCD and LED
After a brief Status Message, the LCD displays the full character set. Verify that there are no gaps
in the character sequences. At the same time each LED on the NanoBoard will be turned on
sequentially. Verify that each LED lights up independently of its neighbors.
• ADC Init

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This initializes the ADC converter and looks for a correct ACK response on the I2C bus.
• ADC Config
Writes the ADC configuration registers and verifies correct ACK response on the I2C bus.
• On-Board FLASH
Reads the device ID from both SPI flash chips
• Clock Generator
Programs the variable clock generator to two different frequencies and verifies the two frequencies
using the 20MHz crystal reference and an FPGA-internal hardware frequency counter.
• Keypad Test
This test verifies functionality of each key.
When prompted, press all keys on the keypad in any sequence. The keys recognized as activated
will be blocked out on the LCD display. As each key is pressed a unique acoustic indication is
given. Finish by pressing the ‘TEST/RESET’ button when prompted.
• DIP-Switches
This test verifies that each DIP switch is functional and independent of its neighbor.
Briefly move each DIP switch to the “on” position, then return to the “off” position. This can be
achieved quickly by running a fingernail along the row of DIP switches. As DIP switch is activated
an acoustic indication is given and the number of the DIP switch number is blocked out on the LCD
display. At the same time the DIP switch status is mirrored on the row of LEDs below.
• Config Jumpers
This test verifies that all configuration jumpers are functional and independent of their neighbors.
Briefly short out each position on the configuration jumper row (JP2). This can be done quickly by
running a small screwdriver tip along the header row. As each jumper is activated, an acoustic
indication is given and the number of the jumper number is blocked out on the LCD display. At the
same time the DIP switch status is mirrored on the row of LEDs to the right.
• PS2 Ports
This sends a command to each of the two PS2 keyboards connected to the DUT’s PS2 connectors
and checks for the correct response.
• RS-232 TXD->RXD
Sends a serial character sequence out through the RS-232 TXD output and verifies the response
on the RXD input. Requires a loop-back plug.
• RS-232 RTS->CTS
Sends a serial character sequence out through the RS-232 RTS output and verifies the response
on the CTS input. Requires a loop-back plug.
• User IO
Verifies correct wiring on ‘USER HEADER A’ and ‘USER HEADER B’.
Outputs a running pattern of 1 on ‘USER HEADER A’ and reads response back on ‘USER
HEADER B’. Requires a loop-back cable.

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• Master-Slave I/O
Verifies all signals on ‘Master I/O’ and’ Slave I/O’ headers. Outputs a running pattern of 1 on
‘Master I/O’ port and reads response back on ‘Slave I/O’ port. Requires Loop-back cable.
• Audio Codec Adj
Allows gain adjustment of audio codec. Outputs square wave on DAC and digitizes input signal on
ADC.
Adjust ‘VR2’ as prompted on the LCD until the message Any Key=Continue indicates a correct
gain of 1.0 in the signal path.
Press any key to proceed to the next test.
Requires an audio loop-back cable.
• CAN-BUS
Outputs a character on the CAN bus. The 3rd NanoBoard will toggle some bits the character with a
bit-mask and echo it back. On reception the character is masked with the same bit-mask and
compared to the transmitted character. The 3rd NanoBoard will acknowledge each character it
receives by flashing all LEDs for a short time. Requires CAN cable and second NanoBoard running
Memory Tester Software.
• Crystal Osc Freq
This test measures the frequency of the NanoBoard crystal oscillator. Since there is no second
fixed oscillator on the NanoBoard it uses an external real time clock chip (RTC) to generate the
reference timing for the frequency counter. This verifies the external I2C bus at the same time,
since the RTC chip is programmed via the external I2C bus.
Requires an RTC adapter PCB.
• ADC/DAC Test
This tests the A/D and D/A sections. NOTE: JP4 must be jumpered to ‘3V3’ for this test. The four
A/D and D/A sections are looped on the RTC adapter PCB. The firmware outputs different voltage
levels on each individual DAC and verifies the corresponding voltage on each ADC.
The two LEDs on the RTC adapter PCB indicate the presence of the +5V and +3.3V supply
voltages on HDR8.
Requires an RTC adapter PCB.
• LCD Backlight
At the end of the test sequence the LCD backlight will blink.
• VGA output
Observe the test pattern on the VGA color monitor. It must show three levels of intensity for all
three primary colors (red, green, blue), two levels of grey and black and white.
If all tests are successful, a SUCCESS message is displayed on the LCD and the speaker will sound
an acoustic success signal.
The LCD Backlight will blink and the LEDs on the two PS2 keyboards will show a pattern of lights on
the status LEDs.

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If one or more tests have failed, the number of failed tests is displayed on the LCD screen and the
speaker will sound an acoustic failure signal.
At this point individual tests can be performed by pressing the corresponding key on the Keypad (see
following table)

Key Test

‘TEST/RESET’ Repeat whole test sequence

1 LCD/LED

2 On-Board FLASH

3 Clock Generator

C 16 Key Keypad

4 Dip Switches

5 Config. Jumpers

6 PS2 Ports

D RS-232 TXD->RXD

7 RS-232 RTS->CTS

8 User IO

9 Master-Slave I/O

E Audio Codec Adj.

A CAN-BUS

0 Crystal Osc Freq

B ADC/DAC Test

F LCD/LED

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Index
A H
ADC...................... 4, 34, 35, 52, 53, 54, 55, 56 header........... 10, 22, 24, 28, 31, 34, 38, 52, 54
assembler ....................................................... 2 configuration....................................4, 22, 38
audio codec ...................................... 34, 36, 55 I
audio jacks...................................................... 4 I2C ..............................4, 34, 35, 47, 52, 54, 55
B Intellectual Property ..................................2, 26
button ..................................................... 36, 54 J
reset ............................................................ 4 JTAG 1, 4, 7, 21, 23, 26, 28, 29, 38, 41, 42, 44,
C 47, 48, 49, 50, 52, 53
CAN port................................................... 4, 32 K

clock keypad ....................................................36, 54

programmable..................................... 25, 27 L

reference..................................................... 4 LCD................. 4, 29, 35, 47, 49, 53, 54, 55, 56

system .......................................... 25, 39, 45 LED array............................................4, 15, 37

compiler .......................................................... 2 LEDs
configuration configuration..........................................4, 22

header............................................. 4, 22, 38 indicator.................................................4, 21

LEDs: .................................................... 4, 22 M

connector motherboard ...................................................2

daughterboard....................................... 4, 26 N

conventions .................................................... 1 NanoTalk . 2, 4, 7, 9, 10, 21, 22, 23, 25, 26, 27,
38, 39, 40, 42, 47, 48, 51, 52
D
Nexus................................................29, 38, 44
DAC........................................ 4, 34, 52, 55, 56
O
daisychain ............................ 2, 4, 7, 21, 24, 38
overview................................................2, 5, 46
daughterboard1, 2, 4, 6, 19, 21, 22, 23, 24, 25,
26, 27, 29, 31, 32, 33, 36, 37, 39, 46, 48, 49 P

daughterboard connectors........................ 4, 26 PCB ................ 2, 19, 20, 30, 46, 47, 51, 52, 55

debug ....................................................... 2, 23 port

DIP switch................................................. 4, 54 CAN.......................................................4, 32

E VGA.......................................................4, 33
expansion header ....................................... 4, 6 power connector .................................4, 10, 21
F programmable clock................................25, 27
Flash RAM.................................................... 42 PS2 ....................... 4, 33, 47, 51, 52, 54, 55, 56

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R switch
reference clock ...............................................4 DIP ....................................................... 4, 54
requirements.......................................7, 21, 26 T
reset button.....................................................4 test procedures ............................................ 46
RS232.................................................4, 32, 52 troubleshooting............................................. 18
S U
screw terminal...............................................34 user board .................................................... 38
Serial SPI Flash RAM ...................................30 V
SPI 4, 22, 23, 25, 27, 30, 34, 39, 40, 42, 45, 54 VGA port .................................................. 4, 33
SRAM .................................................4, 29, 35 VHDL ............................................................. 2

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Revision History
Date Version No. Revision

25-Jan-2004 1.0 New product release

12-Dec-2005 1.1 Path references updated for Altium Designer 6

8-Feb-2006 1.2 Updated to reference the Spartan-3 daughterboard

15-May-2008 1.3 Removed reference to 'FPGA Designer's Quickstart Guide'.

Appendix A – NanoBoard and Daughterboard Schematics

The following pages include the schematics for the:
• NB1 NanoBoard
• NBP2 Altera® Cyclone™ EP1C12Q240C7
• NBP11 Xilinx® Spartan®-3 XC3S1000-4FG456C

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 1 2 3 4

BOC_Audio.SchDoc BOC_DAUGHTER.SCHDOC BOC_SRAM.SchDoc

AUDIO_SPI_CSn AUDIO_SPI_CSn RAM_CS RAM_CS
BOC_Audio
JIOA[0..3] RAM_ADDR[0..16] RAM_ADDR[0..16]

RAM0_DATA[0..7] RAM0_DATA[0..7]
A BOC_Boot.SchDoc BOC_Spartan.SchDoc A
RAM0_WE RAM0_WE
TDO TDO JIOA[0..3] JIOA[0..3] RAM0_OE RAM0_OE
BOC_SRAM
BOC_Boot
TDI TDI JIOB[0..3] JIOB[0..3]
TCK TCK RAM1_DATA[0..7] RAM1_DATA[0..7]
TMS TMS FPGA_TDO FPGA_TDO RAM1_WE RAM1_WE
FPGA_TDI FPGA_TDI RAM1_OE RAM1_OE
N_TDO N_TDO FPGA_TCK FPGA_TCK
N_TDI N_TDI FPGA_TMS FPGA_TMS
BOC_LCD.SchDoc
N_TCK N_TCK
N_TMS N_TMS NEXUS_TDO NEXUS_TDO RAM_ADDR[0..16]
NEXUS_TDI NEXUS_TDI RAM0_DATA[0..7]
MODE_[1..8] MODE_[1..8] NEXUS_TCK NEXUS_TCK LCD_E LCD_E
NEXUS_TMS NEXUS_TMS LCD_BCKL LCD_BCKL BOC_LCD
MODE MODE BUZZER BUZZER
C_CTRL C_CTRL FPGA_DONE FPGA_DONE
PARALLEL PARALLEL FPGA_PROGRAM FPGA_PROGRAM
BOC_IO.SchDoc
FPGA_DIN FPGA_DIN
FPGA_CCLK FPGA_CCLK IO[0..35] IO[0..35] BOC_IO
FPGA_INIT FPGA_INIT
B FPGA_M[0..2] FPGA_M[0..2] B
BOC_RS232.SchDoc
FPGA_AUX[0..3] FPGA_AUX[0..3]
BOC_RTS BOC_RTS
BOC_CTS BOC_CTS
BOC_Spartan BOC_RS232
FPGA_INSTALLED FPGA_INSTALLED BOC_TX BOC_TX
FPGA_ID[0..3] FPGA_ID[0..3] BOC_RX BOC_RX
SPI_DIN SPI_DIN
SPI_CLK SPI_CLK
BOC_CAN.SchDoc
SPI_SEL SPI_SEL
SPI_DOUT SPI_DOUT CAN_TXD CAN_TXD
BOC_CAN
SPI_MODE SPI_MODE CAN_RXD CAN_RXD
C_SPI_CLOCK_SEL
FPGA_CLK_1 FPGA_CLK_1
BOC_ADC_DAC.SchDoc
C_SPI_DIN FPGA_CLK_2 FPGA_CLK_2
C_SPI_CLOCK_CLK SCL SCL
BOC_ADC_DAC
REF_CLK SDA SDA
FPGA_CLK
BOC_VGA_KB_MOUSE.SchDoc
C BOC_CLK_ADJ.SchDoc C
RED0 RED0
BOC_CLK_ADJ
REF_CLK REF_CLK RED1 RED1
C_SPI_CLOCK_CLK GREEN0 GREEN0
C_SPI_DIN FPGA_CLK FPGA_CLK GREEN1 GREEN1
C_SPI_CLOCK_SEL BLUE0 BLUE0
BOC_VGA_KB_MOUSE
BLUE1 BLUE1
HDRIVE HDRIVE
BOC_KB.SchDoc
VDRIVE VDRIVE
TEST TEST KBDATA KBDATA
BOC_KB
SWC[0..3] SWC[0..3] KBCLOCK KBCLOCK
SWR[0..3] SWR[0..3] MOUSEDATA MOUSEDATA
MOUSECLOCK MOUSECLOCK
BOC_LED_DIPSWITCH.SchDoc
BOC_PWR.SCHDOC
LED[0..7] LED[0..7]
BOC_LED_DIPSWITCH
SW[0..7] SW[0..7] VREF VREF BOC_PWR
BOC_DAUGHTER
D D
Altium Limited
Title Board-On-Chip Block Diagram L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:25 AM Sheet 01 of 16 Australia 2086

1 refer to the Altium Wiki for current information

2
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_Top.SchDoc
3 4
 1 2 3 4

A A

VCC VCCA VCCA C47

P0R7502
P0C4701 P0C4702

R75 VCCA 100nF

4R7 U20

P0R7501
3P0U2003

P0C4802 P0C4801
VDD
10P0U20010 AOUT3
C48 OUTD P0U2009
1P0U2001 9 AOUT2 VCCA TS1
10uF ADD OUTC P0U2008
VCC VCC 2P0U2002 8 AOUT1 1
P0TS101
Tant SCL OUTB P0U2007
5P0U2005 7 AOUT0 2
P0R7901

P0R7701
P0TS102
SDA OUTA
3
P0TS103

R79 R77 4P0U2004 6

P0U2006 VREF_AOUT 4
P0TS104
GND REF
4K7 4K7 5
P0R7902

P0R7702

P0TS105

MAX5841MEUB 6
P0TS106

SCL R78 SCL# Maxim 7

P0TS107
SCL P0R7801 P0R7802
B 100R JP4 8
P0TS108 B
VCCA 9
P0TS109

R76
P0JP402 2 1 P0JP401
SDA SDA# VCCA C49 10
P0TS1010
SDA P0R7601 P0R7602 P0JP404 4 3 P0JP403

100R P0C4901 P0C4902

Header 2X2 TS10
100nF
VCCA U21 VREF Header
8P0U2108
VDD
1
P0U2101 AIN0
AIN0 P0U2102
5P0U2105 2 AIN1
SCL AIN1 P0U2103
6P0U2106 3 AIN2
R80 SDA AIN2
P0U2104 4 AIN3
P0R8001 P0R8002 AIN3/REF
0R 7P0U2107

P0C5402 P0C5401

P0C5502 P0C5501

P0C5602 P0C5601

P0C5702 P0C5701
GND
MAX1037EKA-T C54 C55 C56 C57
Maxim 100pF 100pF 100pF 100pF

C VCCA HDR8 5V C
P0HDR8011 2 P0HDR802
SCL P0HDR8033
SDA
4 P0HDR804
AOUT0 P0HDR8055
AOUT1
6 P0HDR806
AOUT2 P0HDR8077
AOUT3
8 P0HDR808
AIN0 P0HDR8099
AIN1
10 P0HDR8010
AIN2 AIN3
11 12 P0HDR8012
P0HDR8011

13 14 P0HDR8014
P0HDR8013

Header 7X2
Analog GND Power GND

I2C/Analog Extension Header

D D
Altium Limited
Title Board-On-Chip Analog Interface L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:26 AM Sheet 14 of 16 Australia 2086

1 refer to the Altium Wiki for current information 2

File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_ADC_DAC.SchDoc
3 4
 1 2 3 4

5V
R61
P0R6101 P0R6102

10R

P0C3802 P0C3801

P0R6302
A A
C38 R63
10uF 10K

P0R6301
Tant

P0R6502

P0C3902 P0C3901
R65 C39
10K 10uF
P0R6501
Tant

GAIN ADJUST
Gain = 0.1 to 10
C37
J10 4 P0J1004 R71 C45 VR2
P0J1004A
P0J1004B P0R7101 P0R7102 P0C3701 P0C3702
3 P0J1003
P0J1003B
P0J1003A 10K P0C4501 P0C4502
100KP0VR20CW
P0VR20CCW
5 100nF

P0VR20W
P0J1005
P0J1005A
P0J1005B
B 2 P0J1002 R72 1uF B
P0J1002B
P0J1002A P0R7201 P0R7202
1 P0J1001
10K R62 U18
P0C5002 P0C5001

P0C5102 P0C5101

P0J1001B
P0J1001A P0R6201 P0R6202

ST-3150-5N 1K 1 P0U1801 8
P0U1808

C50 C51 OUT1 VDD P0U1807

2P0U1802 7
220pF 220pF IN1- OUT2 P0U1806
Line In 3P0U1803 6
IN1+ IN2- P0U1805
4P0U1804 5
GND IN2+
C40
OPA2340UA P0C4001 P0C4002

470pF
R66 R64
P0R6602 P0R6601 P0R6402 P0R6401

18K 4K7
J11 4 P0J1104 R73 C46
P0J1104A
P0J1104B P0R7301 P0R7302
3 P0J1103
P0J1103B
P0J1103A 560R P0C4602 P0C4601
5 P0J1105
P0J1105B
P0J1105A
VCC
2 P0J1102 R74 10uF JIOA[0..3]
P0C4202 P0C4201

P0R4502
P0J1102A
P0J1102B P0R7401 P0R7402
Tant JIOA[0..3]
1 P0J1101
560R
P0C5202 P0C5201

P0C5302 P0C5301

P0J1101B
P0J1101A
C ST-3150-5N C42 R45 C
C52 C53 100nF 4K7 VCC

P0R4501
Line Out 220pF 220pF

P0R4602
U19
RA19P0RA1905
1P0U1901 8
P0U1908 4
P0RA1904 5 JIOA0 R46
VDD DIN P0U1907
2P0U1902 7 3 6
P0RA1906
JIOA1 4K7

P0R4601
P0RA1903
R60 R67 GND DOUT P0U1906
3P0U1903 6 2
P0RA1902 7
P0RA1907
JIOA2
P0R6001 P0R6002
P0R6701 P0R6702 AIN SCLK P0U1905
470R 1K8 4P0U1904 5 1
P0RA1901 8
P0RA1908
AUDIO_SPI_CSn
OUT CS AUDIO_SPI_CSn
C43 100R
R68 MAX1104EUA
P0R6801 P0R6802 P0C4301 P0C4302

4K7
1uF
P0C4102 P0C4101

P0C3602 P0C3601

P0C4402 P0C4401

C41 C36 C44

4700pF 22nF 4700pF

D D
Altium Limited
Title Board-On-Chip Audio Interface L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:26 AM Sheet 03 of 16 Australia 2086

1 refer to the Altium Wiki for current information 2

File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_Audio.SchDoc
3 4
 1 2 3 4 5 6

N_TCK
N_TMS
N_TDI U8C
MODE VCC
CTRL 17 P0U8C017
VCCO
PAR_TMS 36 P0U8C036 1 VCC
A VCCO GND P0U8C01
A
PAR_TCK 53 P0U8C053 9
P0U8C09
VCCO GND
PAR_TDI 72 P0U8C072 16
P0U8C016

P0C7202 P0C7201

P0C7002 P0C7001

P0C6402 P0C6401

P0C6002 P0C6001

P0C5902 P0C5901

P0C6102 P0C6101

P0C6502 P0C6501

P0C7302 P0C7301
VCCO GND
25
P0U8C025
GND
P0C8102 P0C8101
90 P0U8C090 C72 C70 C64 C60 C59 C61 C65 C73

P0C8202 P0C8201

P0C8302 P0C8301

P0C8402 P0C8401

P0C8502 P0C8501

P0C8602 P0C8601

P0C8702 P0C8701

P0C8802 P0C8801
VCCO
108P0U8C0108 34
P0U8C034 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
VCCO GND
C81 C82 C83 C84 C85 C86 C87 C88 128P0U8C0128 45
P0U8C045
VCCO GND
1nF 1nF 1nF 1nF 1nF 1nF 1nF 1nF 144P0U8C0144 54
P0U8C054
VCCO GND
62
P0U8C062
GND
1V8 70
P0U8C070 1V8
GND
19 P0U8C019 81
P0U8C081
VCCINT GND
46 91
P0U8C091

P0C7102 P0C7101

P0C6802 P0C6801

P0C6602 P0C6601

P0C6202 P0C6201

P0C5802 P0C5801

P0C6302 P0C6301

P0C6702 P0C6701

P0C6902 P0C6901
P0U8C046
VCCINT GND
N_TDO 51 P0U8C051 99
P0U8C099
N_TDO VCCINT GND
N_TDI 61 P0U8C061 C71 C68 C66 C62 C58 C63 C67 C69
N_TDI VCCINT
N_TCK 110
P0U8C0110 100nF 100nF 100nF 100nF 100nF 100nF 100nF 100nF
N_TCK GND P0U8C0119
VCC N_TMS 88 P0U8C088 119
N_TMS VCCINT GND P0U8C0127
P0R2802
120 P0U8C0120 127
VCCINT GND P0U8C0136
MODE 130 P0U8C0130 136
MODE VCCINT GND
P0RA308

P0RA307

P0RA306

P0RA305

P0RA408

P0RA407

P0RA406

P0RA405

R28 135 P0U8C0135

VCCINT
8
7
6
5
8
7
6
5

4K7
P0R2801

RA3 RA4 MODE_[1..8]

MODE_[1..8]
4K7 4K7 XC2S100E-6TQ144C
P0RA301

P0RA302

P0RA303

P0RA304

P0RA401

P0RA402

P0RA403

P0RA404
1
2
3
4
1
2
3
4

JP2
B MODE_1 B
2 1P0JP202 P0JP201
MODE_2
4 3P0JP204 P0JP203
MODE_3
6 5P0JP206 P0JP205
MODE_4 PROGRAM
8 7P0JP208 P0JP207
MODE_5 VCC C10 DIN
10 9 P0JP2010
P0JP209
MODE_6
12 11 P0JP2012 P0JP2011 P0C1001 P0C1002
MODE_7 VCC
14 13 P0JP2014 P0JP2013 100nF
MODE_8
16 15 P0JP2016 P0JP2015
BOOT_JTAG_EN U8B

P0C1401 P0C1402

P0C1301 P0C1302

P0C1201 P0C1202
18 17 P0JP2018 P0JP2017 U3C
9
P0U3C09
U3A JP3 VCC VCC
Header 9X2 8
P0U3C08
1 105 P0U8B07474 INIT C14 C13 C12

P0R2501
P0U3A01 P0U8B0105
2 P0JP302 DIN INIT
10 3
P0U3A03
SPARTAN_M0 100nF 100nF 100nF

P0R4002
P0U3C010
1 P0JP301
Mode Select Header SN74LVC00AD
2
P0U3A02 R25
DONE
P0U8B07171
P0U3A07 Header 2 R40 4K7

P0R2502
SN74LVC00AD
1K 73

P0R4001
P0U3A014
U3B P0U8B073
PROGRAM
4
P0U3B04
U3D Configuration Mode Select VCC VCC VCC U5
VCC D6 6
P0U3B06 12 35 107
P0U8B0107 20 P0U502 2

P0R2701

P0R2601
P0U3D012 P0U8B035 P0U5020
M0 CCLK VCCJ P0U509 DNC
1 P0D601 5
P0U3B05 11
P0U3D011
33
P0U8B033 P0U5018 18 9
M1 VCCINTP0U5012 DNC
3
P0D603 13 VCC 37 R27 R26 19 12
P0R1901

P0U3D013 P0U8B037 P0U5019

SN74LVC00AD M2 VCCO DNC
2 4K7 4K7

P0R2702

P0R2602
P0D602
SN74LVC00AD
R19 CTRL P0U508 8 P0U501 1
OE/RESET D0

P0RA1008

P0RA1007

P0RA1006

P0RA1005
BAS40 4K7
P0R1902

8
7
6
5
PAR_TDO# R18 PAR_TDO 111
P0U8B0111 109
P0U8B0109 DONE 10 P0U5010
P0U5013 13
R17 P0R1801 P0R1802 TDI TDO CE CEO
C VCC_SENSE N_TDO# 47R RA10 143P0U8B0143 C
P0R1701 P0R1702 TCK
100R U4A 4K7 2P0U8B02 CCLK 3P0U503 P0U507 7

P0RA1001

P0RA1002

P0RA1003

P0RA1004
TMS CLK CF
VCC BOOT_EN 1
OE
P0U4A01

1
2
3
4
Printer Pin Names 2P0U4A02 18
P0U4A018 BOOT_TDI XC2S100E-6TQ144C BOOT_TDO-TDI 4 P0U504 P0U5017 17
A1 Y1 P0U4A016 TDI TDO
P0RA504

P0RA503

P0RA502

P0RA501

P0RA704

P0RA703

P0RA702

P0RA701

4P0U4A04 16 BOOT_TCK BOOT_TCK 6P0U506

A2 Y2 P0U4A014 TCK
4
3
2
1
4
3
2
1

HDR3 R16 N_TDO 6P0U4A06 14 BOOT_TMS BOOT_TMS 5 P0U505 P0U5014 14

P0R1601 P0R1602 A3 Y3 P0U4A012 TMS DNC
NC SELECTIN RA5 RA7 47R 8P0U4A08 12 P0U5015 15
26 13 P0HDR3013
P0HDR3026 A4 Y4 DNC
GND PE 4K7 4K7 11P0U5011 P0U5016 16
25 12 P0HDR3012 GND DNC
P0RA505

P0RA506

P0RA507

P0RA508

P0RA705

P0RA706

P0RA707

P0RA708

P0HDR3025
GND BUSY SN74LVC244ADB
P0U4A010
24 11 P0HDR3011 RA6 P0U4A020
5
6
7
8
5
6
7
8

P0HDR3024
VCC GND ACK BOOT_TDO BOOT_TDO XCF01SVO20C
23 10 P0HDR3010
P0HDR3023 100R P0RA601
GND D7 PU7 8 1 N_TCK
P0R2402

P0RA608
22 9 P0HDR309
P0HDR3022
GND D6 PU6# 7
P0RA607 2
P0RA602 N_TMS VCC
21 8 P0HDR308
P0HDR3021
R24 GND D5 PU5 6
P0RA606 3
P0RA603 N_TDI
20 7 P0HDR307
P0HDR3020
1K GND D4 PU4 5 4
P0RA604 MODE
P0R2401

P0RA605
19 6 P0HDR306
P0HDR3019
GND D3 PU3 8
P0RA808 1
P0RA801 CTRL VCC C11
18 5 P0HDR305
P0HDR3018
SELECT D2 PU2 7 2 PAR_TMS

P0RA904

P0RA903

P0RA902

P0RA901
P0RA802
P0RA807
17 4 P0HDR304

4
3
2
1
P0HDR3017 P0C1101 P0C1102
INIT D1 PU1 6
P0RA806 3
P0RA803 PAR_TCK
16 3 P0HDR303
P0HDR3016
100nF
ERROR D0 PU0 5
P0RA805 4
P0RA804 PAR_TDI RA9
15 2 P0HDR302
P0HDR3015
AUTOFD STROBE U4B 4K7
14 1 P0HDR301 RA8

P0RA905

P0RA906

P0RA907

P0RA908
P0HDR3014
BOC_EN 19
100R OE
P0U4B019

5
6
7
8
70246-2622
R22 C_CTRL 11P0U4B011 9
P0U4B09 TCK
P0R2201 P0R2202 C_CTRL A1 Y1 TCK
Parallel Port 1K 13P0U4B013
A2 Y2
7
P0U4B07 TDI
TDI
D N_TMS# 15P0U4B015 5
P0U4B05 TMS D
R23 A3 Y3 TMS
PARALLEL# PARALLEL 17P0U4B017 3
P0U4B03
P0R2301 P0R2302 PARALLEL A4 Y4 TDO
1K

Legacy documentation
P0C7602 P0C7601

SN74LVC244ADB
C76 TDO Altium Limited
100pF
Title Board-On-Chip Bootup Circuits L3, 12a Rodborough Rd
Frenchs Forest
Size: B Number: Revision: 1.06

refer to the Altium Wiki for current information

NSW
Date: 10/02/2006 Time: 10:53:26 AM Sheet 02 of 16 Australia 2086
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_Boot.SchDoc
1 2 3 4 5 6
 1 2 3 4

A A

5V C4
P0C401 P0C402

100nF 5V CAN Bus Connector

J2
5
P0J205

B 9
P0J209 B
5V U2 4
P0J204

3 P0U203 5
P0U205 8
P0J208
VDD VREF
CAN_TXD 3
P0J203 10
P0J2010
CAN_TXD
1P0U201 7
P0U207 CANH P0J207
7
TXD CANH
4 P0U204 6
P0U206 CANL P0J202
2 11
P0J2011

R4 RXD CANL
CAN_RXD 6
P0J206
CAN_RXD P0R401 P0R402
270R 2 P0U202 8
P0U208 1
P0J201
GND RS

P0R302
MCP2551 D Connector 9_MALE
R3
120R

P0R301
P0JP101

P0JP103
JP1

P0R202

Header 2X2
1
3
C R2 C
Insert Jumper 1-2 for High Speed Mode 15K Insert Jumper 3-4 for CAN Load
P0R201

2
P0JP104 4
P0JP102

D D
Altium Limited
Title Board-On-Chip CAN Interface L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:26 AM Sheet 13 of 16 Australia 2086

1 refer to the Altium Wiki for current information

2
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_CAN.SchDoc
3 4
 1 2 3 4

A VCC A

P0C3202 P0C3201
C32
100nF

VCC U13 VCC

1 P0U1301 P0U1304
4
E/D VDD
2 P0U1302
P0U1303
3 R54
GND OUT P0R5401 P0R5402

33R
QSMO_4200
R53
40MHz P0R5301 P0R5302

33R
CR1

2P0CR102 1
P0CR101

B B

QC49/SMD
20MHz
U12
1 P0U1201 16
P0U12016
P0C3102 P0C3101

P0C2802 P0C2801

X1/CLK X2 P0U12015
VCC 2P0U1202 15
NC NC P0U12014 R52
C31 C28 3P0U1203 14 VCC REF_CLK
VDD NC P0U12013 P0R5201 P0R5202 REF_CLK
Do Not Install Do Not Install 4P0U1204 13 33R
NC PDTS P0U12012
5P0U1205 12
GND DATA P0U12011 R51
6 P0U1206 11 FPGA_CLK
CLK2 CLK1 P0U12010 P0R5101 P0R5102 FPGA_CLK
7P0U1207 10 33R
NC NCP0U1209
8 P0U1208 9
SCLK STROBE
ICS307M-02

C VCC VCC C
P0C2902 P0C2901

P0C3002 P0C3001

C30 This PCB contains two possible clock devices, of

C29 10uF which only one is actually installed.
100nF Tant
Option A - Fixed 40MHz clock
C_SPI_CLOCK_CLK Install U13, C32, R53 and R54.
C_SPI_CLOCK_CLK
C_SPI_DIN
C_SPI_DIN
Option B - Adjustable Serial Mode Clock
C_SPI_CLOCK_SEL Install U12, CR1, C29, C30, R50, R51 and R52.
C_SPI_CLOCK_SEL
P0R5001

R50
1K
P0R5002

D D
Altium Limited
Title Board-On-Chip System Clock L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:27 AM Sheet 05 of 16 Australia 2086

1 refer to the Altium Wiki for current information

2
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_CLK_ADJ.SchDoc
3 4
 C
B

D
A

SPI_SEL
SPI_DIN
SPI_CLK
JIOB[0..3]

REF_CLK
JIOA[0..3]

FPGA_TDI

SPI_DOUT
FPGA_DIN

SPI_MODE
FPGA_INIT
FPGA_TCK

1
1

FPGA_CLK
FPGA_TMS
FPGA_TDO

NEXUS_TDI

FPGA_CCLK
NEXUS_TCK

FPGA_DONE
NEXUS_TMS
NEXUS_TDO

FPGA_CLK_2
FPGA_CLK_1
FPGA_M[0..2]

FPGA_ID[0..3]
FPGA_AUX[0..3]
AUDIO_SPI_CSn

FPGA_PROGRAM

FPGA_INSTALLED

SPI_SEL
SPI_DIN
SPI_CLK
JIOB[0..3]

REF_CLK
JIOA[0..3]

FPGA_TDI

SPI_DOUT
FPGA_DIN

SPI_MODE
FPGA_INIT

FPGA_CLK
FPGA_TCK
FPGA_TMS
FPGA_TDO

NEXUS_TDI

FPGA_CCLK
NEXUS_TCK

FPGA_DONE
NEXUS_TMS
NEXUS_TDO

FPGA_CLK_2
FPGA_CLK_1
FPGA_M[0..2]

FPGA_ID[0..3]
FPGA_AUX[0..3]
AUDIO_SPI_CSn

FPGA_PROGRAM

FPGA_INSTALLED
JIOB3
JIOB2
JIOB1
JIOB0
JIOA3
JIOA2
JIOA1
JIOA0

FPGA_M2
FPGA_M1
FPGA_M0

FPGA_ID3
FPGA_ID2
FPGA_ID1
FPGA_ID0
FPGA_AUX3
FPGA_AUX2
FPGA_AUX1
FPGA_AUX0
P0J902 P0J802
1 P0J901 2 FPGA_CLK P0J801
1 2 CAN_TXD
P0J904 P0J804
SDA P0J903
3 4 REF_CLK JIOA0 P0J803
3 4 CAN_RXD
P0J906 P0J806
SCL P0J905
5 6 SWC3 JIOA1 P0J805
5 6 RED0
P0J908 P0J808

2
2

IO0 P0J907
7 8 SWR3 JIOA2 P0J807
7 8 RED1
P0J9010 P0J8010
IO1 P0J909
9 10 SWR2 JIOA3 P0J809
9 10 GREEN0
P0J9012 P0J8012
IO2 P0J9011
11 12 SWR1 AUDIO_SPI_CSn P0J8011
11 12 GREEN1
P0J9014 P0J8014
IO3 P0J9013
13 14 SWC2 BOC_CTS P0J8013
13 14 BLUE0
P0J9016 P0J8016
IO4 P0J9015
15 16 SWC1 BOC_TX P0J8015
15 16 BLUE1
P0J8018
TEST

P0J9018
IO5 P0J9017
17 18 SWC0 BOC_RTS P0J8017
17 18 HDRIVE

SWR[0..3]
SWC[0..3]
P0J9020 P0J8020
IO6 P0J9019
19 20 SWR0 BOC_RX P0J8019
19 20 VDRIVE
P0J9022 P0J8022
IO7 P0J9021
21 22 LCD_BCKL RAM_ADDR0 P0J8021
21 22 KBCLOCK
P0J9024 P0J8024
IO8 P0J9023
23 24 BUZZER RAM_ADDR16 P0J8023
23 24 KBDATA
P0J9026 P0J8026
IO9 P0J9025
25 26 LCD_E RAM_ADDR1 P0J8025
25 26 MOUSECLOCK
P0J9028 P0J8028
IO10 P0J9027
27 28 RAM0_DATA7 RAM_ADDR15 P0J8027
27 28 MOUSEDATA
P0J9030 P0J8030
IO11 P0J9029
29 30 RAM0_DATA6 RAM_ADDR2 P0J8029
29 30 FPGA_CLK_1
TEST

P0J9032 P0J8032
IO12 P0J9031
31 32 RAM0_DATA5 RAM_ADDR14 P0J8031
31 32 FPGA_CLK_2
P0J9034 P0J8034
P0J9033 P0J8033
SWR[0..3]
SWC[0..3]

IO13 33 34 RAM0_DATA4 RAM_ADDR3 33 34 FPGA_INSTALLED

P0J9036 P0J8036
IO14 P0J9035
35 36 RAM0_DATA3 RAM_ADDR13 P0J8035
35 36 FPGA_ID3
P0J9038 P0J8038
IO15 P0J9037
37 38 RAM0_DATA2 RAM_CS P0J8037
37 38 FPGA_ID2
P0J9040 P0J8040
IO16 P0J9039
39 40 RAM0_DATA1 RAM1_OE P0J8039
39 40 FPGA_ID1
P0J9042 P0J8042
IO17 P0J9041
41 42 RAM0_DATA0 RAM0_OE P0J8041
41 42 FPGA_ID0
P0J9044 P0J8044
IO18 P0J9043
43 44 SW0 RAM1_DATA7 P0J8043
43 44 SPI_DIN
P0J9046 P0J8046
IO19 P0J9045
45 46 SW1 RAM1_DATA0 P0J8045
45 46 SPI_CLK
SWR3
SWR2
SWR1
SWR0
SWC3
SWC2
SWC1
SWC0

P0J9048 P0J8048
IO20 P0J9047
47 48 SW2 RAM1_DATA6 P0J8047
47 48 SPI_SEL
P0J9050 P0J8050
IO21 P0J9049
49 50 SW3 RAM1_DATA1 P0J8049
49 50 SPI_DOUT
P0J9052 P0J8052
IO22 P0J9051
51 52 SW4 RAM1_DATA5 P0J8051
51 52 SPI_MODE
P0J9054 P0J8054
IO23 P0J9053
53 54 SW5 RAM1_DATA2 P0J8053
53 54 FPGA_TDO
P0J9056 P0J8056
IO24 P0J9055
55 56 SW6 RAM1_DATA4 P0J8055
55 56 FPGA_M2
P0J9058 P0J8058

3
3

IO25 P0J9057
57 58 SW7 RAM1_DATA3 P0J8057
57 58 FPGA_M1
P0J9060 P0J8060
IO26 P0J9059
59 60 LED0 RAM_ADDR12 P0J8059
59 60 FPGA_M0
P0J9062 P0J8062
IO27 P0J9061
61 62 LED1 RAM1_WE P0J8061
61 62 FPGA_PROGRAM
P0J9064 P0J8064
IO28 P0J9063
63 64 LED2 RAM_ADDR11 P0J8063
63 64 FPGA_DIN
P0J9066 P0J8066
IO29 P0J9065
65 66 LED3 RAM_ADDR4 P0J8065
65 66 FPGA_CCLK
P0J9068 P0J8068
IO30 P0J9067
67 68 LED4 RAM_ADDR10 P0J8067
67 68 FPGA_INIT
SW[0..7]
LED[0..7]

P0J9070 P0J8070
IO31 P0J9069
69 70 LED5 RAM_ADDR5 P0J8069
69 70 FPGA_TMS
P0J9072 P0J8072
IO32 P0J9071
71 72 LED6 RAM_ADDR9 P0J8071
71 72 FPGA_TCK
P0J9074 P0J8074
IO33 P0J9073
73 74 LED7 RAM_ADDR6 P0J8073
73 74 FPGA_DONE
P0J9076 P0J8076
IO34 P0J9075
75 76 RAM_ADDR8 P0J8075
75 76 NEXUS_TDO
P0J9078 P0J8078
IO35 P0J9077
77 78 RAM_ADDR7 P0J8077
77 78 FPGA_TDI
P0J9080 P0J8080
P0J9079
79 80 RAM0_WE P0J8079
79 80 NEXUS_TMS
P0J9082 P0J8082
P0J9081
81 82 TEST P0J8081
81 82 NEXUS_TCK
SW[0..7]
LED[0..7]

P0J9084 P0J8084
P0J9083
83 84 JIOB0 P0J8083
83 84 NEXUS_TDI
P0J9086 P0J8086
P0J9085
85 86 JIOB1 P0J8085
85 86 FPGA_AUX0
P0J9088 P0J8088
P0J9087
87 88 JIOB2 P0J8087
87 88 FPGA_AUX1
P0J9090 P0J8090
P0J9089
89 90 JIOB3 P0J8089
89 90 FPGA_AUX2
P0J9092 P0J8092
P0J9091
91 92 P0J8091
91 92 FPGA_AUX3
P0J9094 P0J8094
P0J9093
93 94 P0J8093
93 94
P0J9096 P0J8096
P0J9095
95 96 P0J8095
95 96
P0J9098 P0J8098
P0J9097 P0J8097
VCC
VCC

97 98 97 98
P0J90100 P0J80100
P0J9099
99 100 P0J8099
99 100
SW7
SW6
SW5
SW4
SW3
SW2
SW1
SW0
LED7
LED6
LED5
LED4
LED3
LED2
LED1
LED0
VREF

P0J90MH2 P0J80MH2
P0J90MH1
MH1 MH2 P0J80MH1
MH1 MH2
P0J90MH2A
P0J90MH2B P0J80MH2A
P0J80MH2B
P0J90MH4 P0J80MH4
P0J90MH3
MH3 MH4 P0J80MH3
MH3 MH4
P0J90MH4B
P0J90MH4A P0J80MH4B
P0J80MH4A

4
4

5V
5V

J9
J8

VREF

VCCINT
VCCINT

53751-1009
53751-1009

Legacy documentation
RAM_ADDR9
RAM_ADDR8
RAM_ADDR7
RAM_ADDR6
RAM_ADDR5
RAM_ADDR4
RAM_ADDR3
RAM_ADDR2
RAM_ADDR1
RAM_ADDR0

RAM1_DATA7
RAM1_DATA6
RAM1_DATA5
RAM1_DATA4
RAM1_DATA3
RAM1_DATA2
RAM1_DATA1
RAM1_DATA0
RAM0_DATA7
RAM0_DATA6
RAM0_DATA5
RAM0_DATA4
RAM0_DATA3
RAM0_DATA2
RAM0_DATA1
RAM0_DATA0
RAM_ADDR16
RAM_ADDR15
RAM_ADDR14
RAM_ADDR13
RAM_ADDR12
RAM_ADDR11
RAM_ADDR10

Title

Size: B
Date: 10/02/2006
LCD_E

BUZZER
RAM_CS

RAM1_OE
RAM0_OE

RAM1_WE
RAM0_WE

LCD_BCKL

refer to the Altium Wiki for current information

Number:

5
5

RAM1_DATA[0..7]
RAM0_DATA[0..7]
RAM_ADDR[0..16]
RAM_CS

RAM1_OE
RAM0_OE

RAM1_WE
RAM0_WE

LCD_E

BUZZER
LCD_BCKL
RAM1_DATA[0..7]
RAM0_DATA[0..7]
RAM_ADDR[0..16]

Revision: 1.06
Time: 10:53:27 AM Sheet 08 of 16
Board-On-Chip Daughter Connectors
IO9
IO8
IO7
IO6
IO5
IO4
IO3
IO2
IO1
IO0

IO35
IO34
IO33
IO32
IO31
IO30
IO29
IO28
IO27
IO26
IO25
IO24
IO23
IO22
IO21
IO20
IO19
IO18
IO17
IO16
IO15
IO14
IO13
IO12
IO11
IO10

NSW
SCL
SDA

RED1
RED0

BLUE1
BLUE0

Australia 2086
Altium Limited

Frenchs Forest
VDRIVE
HDRIVE
GREEN1
GREEN0
BOC_TX
BOC_RX

KBDATA
BOC_CTS
BOC_RTS

CAN_TXD

KBCLOCK
CAN_RXD
IO[0..35]

MOUSEDATA

L3, 12a Rodborough Rd

MOUSECLOCK

6
6

SCL
SDA

RED1
RED0

BLUE1
BLUE0
IO[0..35]

VDRIVE
HDRIVE
GREEN1
GREEN0
BOC_TX
BOC_RX

KBDATA
BOC_CTS
BOC_RTS

CAN_TXD
CAN_RXD

KBCLOCK
MOUSEDATA
MOUSECLOCK

File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_DAUGHTER.SchDoc

C
B

D
A
 1 2 3 4

A A

VCC JP5 5V VCC JP6 5V

P0JP501 1 2 P0JP502 P0JP601 1 2 P0JP602

P0JP503 3 4 P0JP504 P0JP603 3 4 P0JP604

Header 2X2 Header 2X2

PWR_USER_1 PWR_USER_2

HDR9 HDR10
IO0 IO18
P0HDR9011 2 P0HDR902 P0HDR10011 2 P0HDR1002
B IO1 P0HDR9033
IO2 IO19 IO20 B
4 P0HDR904 P0HDR10033 4 P0HDR1004
IO3 P0HDR9055
IO4 IO21 IO22
6 P0HDR906 P0HDR10055 6 P0HDR1006
IO5 P0HDR9077
IO6 IO23 IO24
8 P0HDR908 P0HDR10077 8 P0HDR1008
IO7 P0HDR9099
IO8 IO25 IO26
10 P0HDR9010 P0HDR10099 10 P0HDR10010
IO9 IO10 IO27 IO28
11
P0HDR9011 12 P0HDR9012 11
P0HDR10011 12 P0HDR10012
IO11 IO12 IO29 IO30
13
P0HDR9013 14 P0HDR9014 13
P0HDR10013 14 P0HDR10014
IO13 IO14 IO31 IO32
15
P0HDR9015 16 P0HDR9016 15
P0HDR10015 16 P0HDR10016
IO15 IO16 IO33 IO34
17
P0HDR9017 18 P0HDR9018 17
P0HDR10017 18 P0HDR10018
IO17 IO35
19
P0HDR9019 20 P0HDR9020 19
P0HDR10019 20 P0HDR10020
Header 10X2 Header 10X2

USER HEADER A USER HEADER B

IO[0..35]
IO[0..35]
C C

D D
Altium Limited
Title Board-On-Chip User Header Ports L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:27 AM Sheet 11 of 16 Australia 2086

1 refer to the Altium Wiki for current information

2
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_IO.SchDoc
3 4
 1 2 3 4

VCC VCC

8
7
6
5

P0R5502P0R5501
RA18 R55 SW17
A 4K7 4K7 4
P0SW1704 3 A
P0SW1703

1
2
3
4
P0RA1808
P0RA1807
P0RA1806
P0RA1805
2
P0SW1702 1
P0SW1701

P0RA1801

P0RA1802

P0RA1803

P0RA1804
SWC0
SWC1
SWC2
SWC3
DTSM-61-NR TEST
TEST
TEST/RESET SWITCH

SWC[0..3]
SWC[0..3]
SWC0

SWC1

SWC2

SWC3
0 1 2 3
SW1 SW2 SW3 SW4
4
P0SW104 3
P0SW103
4
P0SW204 3
P0SW203
4
P0SW304 3
P0SW303
4
P0SW404 3
P0SW403

2
P0SW102 1
P0SW101
2
P0SW202 1
P0SW201
2
P0SW302 1
P0SW301
2
P0SW402 1
P0SW401

B B
DTSM-61-NR DTSM-61-NR DTSM-61-NR DTSM-61-NR SWR0

4 5 6 7
SW5 SW6 SW7 SW8
4
P0SW504 3
P0SW503
4
P0SW604 3
P0SW603
4
P0SW704 3
P0SW703
4
P0SW804 3
P0SW803

2
P0SW502 1
P0SW501
2
P0SW602 1
P0SW601
2
P0SW702 1
P0SW701
2
P0SW802 1
P0SW801

DTSM-61-NR DTSM-61-NR DTSM-61-NR DTSM-61-NR SWR1

8 9 A B
SW9 SW10 SW11 SW12
4
P0SW904 3
P0SW903
4
P0SW1004 3
P0SW1003
4
P0SW1104 3
P0SW1103
4
P0SW1204 3
P0SW1203

C 2
P0SW902 1
P0SW901
2
P0SW1002 1
P0SW1001
2
P0SW1102 1
P0SW1101
2
P0SW1202 1
P0SW1201 C

DTSM-61-NR DTSM-61-NR DTSM-61-NR DTSM-61-NR SWR2

B3FS

C D E F
SW13 SW14 SW15 SW16
4
P0SW1304 3
P0SW1303
4
P0SW1404 3
P0SW1403
4
P0SW1504 3
P0SW1503
4
P0SW1604 3
P0SW1603

2
P0SW1302 1
P0SW1301
2
P0SW1402 1
P0SW1401
2
P0SW1502 1
P0SW1501
2
P0SW1602 1
P0SW1601

DTSM-61-NR DTSM-61-NR DTSM-61-NR DTSM-61-NR SWR3

SWR[0..3]
SWR[0..3]

D D
Altium Limited
Title Board-On-Chip Keyboard L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:28 AM Sheet 06 of 16 Australia 2086

1 refer to the Altium Wiki for current information

2
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_KB.SchDoc
3 4
 1 2 3 4

LCD Supply Voltage 5V VCC_LCD

R30 LCD1
Install R30 for 5 Volt LCD P0R3001
0R P0R3002
1
GND

P0VR10CW
or VCC VR1 2
R31
P0VR10W VDD
Install R31 for 3.3 Volt LCD 20K 3P0LCD101

P0VR10CCW
P0R3101 P0R3102
Vo
P0LCD102

A 0R P0LCD103
A

RAM_ADDR[0..16]
RAM_ADDR[0..1] INSTALL R30
RAM_ADDR0 4P0LCD104 VCC_LCD
RS
RAM_ADDR1 5P0LCD105

P0C1702 P0C1701
R/W
LCD_E 6
P0LCD106
LCD_E E C17
LCD_BCKL
LCD_BCKL 100nF
7P0LCD107

P0R2901
DB0
8P0LCD108
DB1
VCC C33 R29 9P0LCD109
DB2
LCD Address Decoding 4K7 10P0LCD1010

P0R2902
P0C3301 P0C3302 DB3
11P0LCD1011
100nF DB4
Address Function Status 12P0LCD1012
DB5
======================================== U16 VCC 13P0LCD1013
DB6
???0H Write Command to LCD Write Only 1P0U1601 5
P0U1605
14P0LCD1014
NC VCC DB7
???1H Write Data to LCD Write Only 2
P0U1602 5V
A
???2H Read Status from LCD Read Only 3P0U1603 4
P0U1604
LCD_En 15P0LCD1015
GND Y LED+
???3H Read Data from LCD Read Only 16P0LCD1016
LED-
SN74LVC1G04DBV
B Address ??? is determined by internal FPGA decoding of 162A B
the LCD_E signal. VCC U17
20 P0U17020 19
P0U17019
VCC OE P0U1701
1
DIR R32
RA12 4K7 P0R3201 P0R3202
RAM0_DATA7 18P0U17018 2
P0U1702 LCD_D7 4
P0RA1204 5
P0RA1205
68R
B0 A0
RAM0_DATA6 17P0U17017 3
P0U1703 LCD_D6 3
P0RA1203 6
P0RA1206
B1 A1 R33
RAM0_DATA5 16P0U17016 4
P0U1704 LCD_D5 2
P0RA1202 7
P0RA1207
B2 A2 P0R3301 P0R3302
RAM0_DATA4 15P0U17015 5
P0U1705 LCD_D4 1
P0RA1201 8
P0RA1208
68R
B3 A3

P0Q103
RAM0_DATA3 14P0U17014 6
P0U1706 LCD_D3 4
P0RA1104 5
P0RA1105
B4 A4

3
RAM0_DATA2 13P0U17013 7
P0U1707 LCD_D2 3
P0RA1103 6
P0RA1106
B5 A5
RAM0_DATA1 12P0U17012 8
P0U1708 LCD_D1 2
P0RA1102 7
P0RA1107
Q1
B6 A6 R35
RAM0_DATA0 11P0U17011 9
P0U1709 LCD_D0 1 8
P0RA1108
1 2N7002

P0R3402
P0RA1101 P0Q101
B7 A7 P0R3501 P0R3502

P0Q102
560R

2
RAM0_DATA[0..7] 10
P0U17010 RA11 4K7 R34
RAM0_DATA[0..7] GND 10K

P0R3401
SN74LVC245ADB
VCC C34 5V
P0C3401 P0C3402
C C

P0Q202
100nF
P0R3801

2
1
P0Q201 Q2
R38
R37
4K7
P0R3802

BUZZER P0R3701 P0R3702

P0Q203
BSS84 C9
560R L1

3
P0L101 P0L102 P0C901 P0C902
330uH

P0SPKR101A
P0SPKR101
10uF
P0Q403

P0Q303
e.g. Farnell 3876895
3

1
Q4 Q3 Tant

P0C1802 P0C1801
SPKR1
P0R3901

1
P0Q401 1
P0Q301 C18 ABSM-1574-05 Transducer
R39
P0Q402

P0Q302

2N7002 2N7002 22nF

P0SPKR102A
P0SPKR102
2

10K
P0R3902

2
http://www.megastar.com/linecard/buzzmode/ABSM-1574-05-2.HTM
D D
Altium Limited
Title Board-On-Chip LCD Display L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:28 AM Sheet 10 of 16 Australia 2086

1 refer to the Altium Wiki for current information

2
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_LCD.SchDoc
3 4
 1 2 3 4

A A
LED[0..7]
LED[0..7]

LED0

LED1

LED2

LED3

LED4

LED5

LED6

LED7
P0LED001

P0LED101

P0LED201

P0LED301

P0LED401

P0LED501

P0LED601

P0LED701
HSMH-C170 HSMH-C170 HSMH-C170 HSMH-C170 HSMH-C170 HSMH-C170 HSMH-C170 HSMH-C170

P0LED002

P0LED102

P0LED202

P0LED302

P0LED402

P0LED502

P0LED602

P0LED702
LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7
LED0#

LED1#

LED2#

LED3#

LED4#

LED5#

LED6#

LED7#
P0RA2301

P0RA2302

P0RA2303

P0RA2304

P0RA2401

P0RA2402

P0RA2403

P0RA2404
B B
1
2
3
4

1
2
3
4
RA23 RA24
270R 270R
P0RA2308

P0RA2307

P0RA2306

P0RA2305

P0RA2408

P0RA2407

P0RA2406

P0RA2405
8
7
6
5

8
7
6
5
VCC
P0RA2108

P0RA2107

P0RA2106

P0RA2105

P0RA2208

P0RA2207

P0RA2206

P0RA2205
8
7
6
5
8
7
6
5

SW[0..7]
SW[0..7]
RA21 RA22
C 4K7 4K7 C
P0RA2101

P0RA2102

P0RA2103

P0RA2104

P0RA2201

P0RA2202

P0RA2203

P0RA2204
1
2
3
4
1
2
3
4

S2
16
P0S2016 1
P0S201
SW0
15
P0S2015 2
P0S202
SW1
14
P0S2014 3
P0S203
SW2
13
P0S2013 4
P0S204
SW3
12
P0S2012 5
P0S205
SW4
11
P0S2011 6
P0S206
SW5
10
P0S2010 7
P0S207
SW6
9
P0S209 8
P0S208
SW7

A6ER-8104

D D
Altium Limited
Title Board-On-Chip LEDs and DIP Switch L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:28 AM Sheet 07 of 16 Australia 2086

1 refer to the Altium Wiki for current information 2

File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_LED_DIPSWITCH.SchDoc
3 4
 1 2 3 4

U10
LM1084IS-ADJ 3V3 VCC
3 2
IN OUT

P0R4702 P0R4701
P0C2701

P0C2501

P0C1601
P0U1003
C16

1
C27 R47 C25

P0C2702

P0C2502

P0C1602
P0U1002
A 10uF 10uF 470uF 16V A
S1 120R
J6

1
1 PWR_IN
P0J601 3P0S103 5V Tant Tant
P0J601B
P0J601A
3 P0J603
2
P0S102

P0R4801
P0J603B
P0J603A
2 P0J602
1P0S101

P0C1502 P0C1501

P0U1001
P0J602B
P0J602A

KLD-0202-B R48
TL36WW050 C15 100R

P0R4802
470uF 16V

P0R4902
R49
J7 1 P0J701
100R

P0R4901
P0J701B
P0J701A P0D702
3 P0J703
P0J703B
P0J703A
2 P0J702
P0J702B
P0J702A
D7
KLD-0202-B SMBJ5341B
P0D701

6V2 5W
U9
LM1084IS-ADJ 1V8 1V8
3 P0U903 P0U902
2
IN OUT
B B

P0C2202 P0C2201

P0R4201

P0C2302 P0C2301

P0C2102 P0C2101
C21

1
C22 R42 C23

1P0U901
10uF 10uF 470uF 16V
120R

P0R4202
Tant Tant
GROUNDING POINTS

P0R4101
GJ1 GJ2 GJ3 R41
47R

P0R4102
1 P0GJ101 P0GJ201 1 P0GJ301 1

P0R4301
2 P0GJ102 P0GJ202 2 P0GJ302 2

Header 2 Header 2 Header 2 R43

5R6

P0R4302
GJ4 GJ5 GJ6
1 P0GJ401 P0GJ501 1 P0GJ601 1
2 P0GJ402 P0GJ502 2 P0GJ602 2

Header 2 Header 2 Header 2 U11

C LM1084IS-ADJ (Daughter Board Dependant) VCCINT C
3P0U1103 P0U1102 2
IN OUT
GJ7 GJ8

P0R5601
P0C2602 P0C2601

P0C2402 P0C2401
P0C3502 P0C3501
1 1

1
P0GJ701 P0GJ801
C26 R56 C35 C24

1P0U1101
2 P0GJ702 P0GJ802 2
10uF 10uF 470uF 16V
120R

P0R5602
Header 2 Header 2 Tant Tant

P0R5701
R57
47R
P0R5702
P0R5801

VREF
R58
5R6
P0R5802

VREF

D D
Altium Limited
Title Board-On-Chip Power Supply L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:28 AM Sheet 16 of 16 Australia 2086

1 refer to the Altium Wiki for current information 2

File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_PWR.SchDoc
3 4
 1 2 3 4

A A

P0C601
VCC DCE Serial Port
C6 U1 Use pin-for-pin DB9 Male-Female

P0C602

P0C301
100nF 1 P0U101 16
P0U1016
Cable to connect to a PC
C1+ VCC
3 2
P0U102 C3

P0C701

P0C302
P0U103
C1- V+
4 P0U104 100nF
C2+
B C7 5 B

P0C702
P0U105
C2-
100nF J1
BOC_TX 11
P0U1011 14
P0U1014
TX 1
P0J101
BOC_TX
6
P0J106

BOC_RTS 10
P0U1010 7
P0U107
RTS TX 2
P0J102 11
P0J1011
BOC_RTS
CTS 7
P0J107

BOC_RX R1 12
P0U1012 13
P0U1013
RX RX 3
P0J103 10
P0J1010
BOC_RX P0R101 P0R102

100R RTS 8
P0J108

BOC_CTS R9 9
P0U109 8
P0U108
CTS 4
P0J104
BOC_CTS P0R901 P0R902

100R 9
P0J109

15 6
P0U106 5
P0J105

P0C801
P0U1015
GND V-
MAX3232CSE C8 DB9 Female

P0C802
100nF

VCC
P0C201

P0C101

C C
C2 C1
P0C202

P0C102

10uF
100nF Tant

D D
Altium Limited
Title Board-On-Chip RS232 Serial Interface L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:28 AM Sheet 12 of 16 Australia 2086

1 refer to the Altium Wiki for current information

2
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_RS232.SchDoc
3 4
 1 2 3 4 5 6

VCC VCC VCC VCC

5
6
7
8

5
6
7
8

5
6
7
8

5
6
7
8
VCC
RA28 RA25 RA32 RA29 HDR1 VCC
RA1

P0RA2805

P0RA2806

P0RA2807

P0RA2808

P0RA2505

P0RA2506

P0RA2507

P0RA2508

P0RA3205

P0RA3206

P0RA3207

P0RA3208

P0RA2905

P0RA2906

P0RA2907

P0RA2908
P0RA101
4K7 4K7 4K7 4K7 MASTER_MODE 8 1 MASTER_TDO MASTER_TDI

P0R701
P0RA108
P0RA102 2
P0HDR102 1 P0HDR101
MASTER_TCK 7
P0RA107 2 MASTER_TMS MASTER_TCK
4
P0HDR104
3 P0HDR103

4
3
2
1

4
3
2
1

4
3
2
1

4
3
2
1
P0RA2804

P0RA2803

P0RA2802

P0RA2801

P0RA2504

P0RA2503

P0RA2502

P0RA2501

P0RA3204

P0RA3203

P0RA3202

P0RA3201

P0RA2904

P0RA2903

P0RA2902

P0RA2901
P0RA103
MASTER_TMS 6
P0RA106 3 MASTER_MODE R7
RA27P0RA2704 6
P0HDR106 5 P0HDR105
TDI_HARD_A 5 4 TDI_HARD_A# MASTER_TDI 5 4
P0RA104
1K

P0R702
P0RA2705 P0RA105
8
P0HDR108 7 P0HDR107
R8
TDO_HARD_A 6
P0RA2706 3
P0RA2703
TDO_HARD_A# HDR6 MASTER# MASTER
P0RA2702 4K7 10
P0HDR1010 9 P0HDR109 P0R801 P0R802
TCK_HARD 7
P0RA2707 2 TCK_HARD_A# 1K
P0RA2701
P0HDR6011 2 P0HDR602
TMS_HARD 8
P0RA2708 1 TMS_HARD_A# Header 5X2
A P0HDR6033 4 P0HDR604 A
100R P0HDR6055 6 P0HDR606
RA26P0RA2604 P0HDR6077 8 P0HDR608
NanoTalk Master
TDI_SOFT_A 5
P0RA2605 4 TDI_SOFT_A# P0HDR6099
5V
P0RA2603 10 P0HDR6010 R5
TDO_SOFT_A 6
P0RA2606 3 TDO_SOFT_A# P0R501 P0R502
LED8
P0LED801 P0LED802
Power
P0RA2602
TCK_SOFT_A 7
P0RA2607 2 TCK_SOFT_A# 70246-1022 270R HSMH-C170 HDR2
RA20P0RA2005
TMS_SOFT_A 8
P0RA2608 1
P0RA2601
TMS_SOFT_A# JIOA0 4
P0RA2004 5 JIOA0#
Spare LED 1 1
P0HDR201 2 P0HDR202
LED9 JIOA1 3
P0RA2003 6
P0RA2006
JIOA1#
100R R70
P0LED901 P0LED902
P0RA2007 3
P0HDR203 4 P0HDR204
JTAG_CNCT_A JTAG_CNCT_A# HSMH-C170 JIOA2 2
P0RA2002 7 JIOA2#
P0R7001 P0R7002
P0RA2008 5
P0HDR205 6 P0HDR206
100R JIOA3 1 8 JIOA3#
P0C7802 P0C7801

P0C7702 P0C7701
P0RA2001
RA14P0RA1408 7
P0HDR207 8 P0HDR208
User Board A SPL1 1
P0RA1401 8 SPL1# LED10
P0LED1001 P0LED1002
Spare LED 2
100R 9
P0HDR209 10 P0HDR2010
C78 C77 SPL2 2
P0RA1402 7
P0RA1407
SPL2# HSMH-C170
1nF 1nF SPL3 3
P0RA1403 6
P0RA1406
SPL3# Header 5X2
SPL4 4
P0RA1404
P0RA1405
5 SPL4# LED11 Spare LED 3
P0LED1101 P0LED1102

270R
HSMH-C170 Master I/O
JIOA[0..3]
RA31P0RA3104 Spare LED 4 JIOA[0..3]
TDI_HARD_B 5
P0RA3105 4 TDI_HARD_B# LED12
P0LED1201 P0LED1202
TDO_HARD_B 6
P0RA3106 3
P0RA3103
TDO_HARD_B# HDR7 HSMH-C170
P0RA3102
7
P0RA3107 2 TCK_HARD_B# P0HDR7011 2 P0HDR702 Spare LED 5
8
P0RA3108 1
P0RA3101
TMS_HARD_B# LED13
P0HDR7033 4 P0HDR704 P0LED1301 P0LED1302
HSMH-C170 HDR4 VCC
100R P0HDR7055 6 P0HDR706 R21
SLAVE_TDI SLAVE_TDO
RA30P0RA3004 P0HDR7077 8 P0HDR708 RA15P0RA1508 Spare LED 6 1
P0HDR401 2 P0HDR402 P0R2102 P0R2101
TDI_SOFT_B 5
P0RA3005 4 TDI_SOFT_B# P0HDR7099
SPL5 1
P0RA1501 8 SPL5# LED14 SLAVE_TCK SLAVE_TMS 4K7
10 P0HDR7010 P0LED1401 P0LED1402 3
P0HDR403 4 P0HDR404
TDO_SOFT_B 6
P0RA3006 3
P0RA3003
TDO_SOFT_B# SPL6 2
P0RA1502 7
P0RA1507
SPL6# HSMH-C170 SLAVE_MODE
5
P0HDR405 6 P0HDR406
TCK_SOFT_B 7
P0RA3007 2
P0RA3002
TCK_SOFT_B# 70246-1022 SPL7 3
P0RA1503 6
P0RA1506
SPL7#
Spare LED 7 7
P0HDR407 8 P0HDR408
TMS_SOFT_B 8
P0RA3008 1
P0RA3001
TMS_SOFT_B# SPL8 4
P0RA1504 5
P0RA1505
SPL8# LED15
P0LED1501 P0LED1502 9
P0HDR409 10 P0HDR4010
HSMH-C170 VCC
100R R69 270R
JTAG_CNCT_B JTAG_CNCT_B# Header 5X2

P0R2001
P0R6901 P0R6902
100R LED16 Spare LED 8
P0C8002 P0C8001

P0C7902 P0C7901

P0LED1601 P0LED1602
User Board B HSMH-C170 R20 NanoTalk Slave
C80 C79 NOTE: 1K

P0R2002
1nF 1nF C77, C78, C79, and C80 SLAVE R6 SLAVE#
P0R601 P0R602
are NOT fitted. 1K JIOB[0..3]
JIOB[0..3]
HDR5
RA17 P0RA1701
JIOB0# 8
P0RA1708 1 JIOB0
2
P0HDR502 1 P0HDR501
JIOB1# 7
P0RA1707 2
P0RA1702
JIOB1
4
P0HDR504 3 P0HDR503
JIOB2# 6
P0RA1706 3
P0RA1703
JIOB2
6
P0HDR506 5 P0HDR505
B JIOB3# 5
P0RA1705 4
P0RA1704
JIOB3 B
8
P0HDR508 7 P0HDR507

10
P0HDR5010 9 P0HDR509 100R
TDO Header 5X2 VCC
TDO
TDI
TDI
TCK
TCK MODE_6 Slave I/O
TMS MODE_5
TMS
MODE_4 MODE_7 FPGA_TDO
FPGA_TDO
MODE_3 MODE_8 FPGA_TDI
FPGA_TDI
MODE_2 N_TDO FPGA_TCK
FPGA_TCK
MODE_1 N_TCK FPGA_TMS
FPGA_TMS
N_TDO MASTER_TDI N_TMS
N_TDO
N_TDI MASTER_TMS N_TDI
N_TDI
N_TCK MASTER_TCK MODE
N_TCK
N_TMS MASTER_MODE C_CTRL NEXUS_TDO
N_TMS NEXUS_TDO
MASTER PARALLEL NEXUS_TDI
NEXUS_TDI
TCK NEXUS_TCK
R36 NEXUS_TCK
MASTER_TDO MASTER_TDO# TDI NEXUS_TMS
P0R3601 P0R3602 NEXUS_TMS
100R TMS
MODE_[1..8] TDO
MODE_[1..8]
106
104
P0U8A0103 103

102
101
100
I/O (DOUT, BUSY), L6P_YY P0U8A0104

I/O, VREF 2 P0U8A0102

I/O, L8N_YY P0U8A096

I/O (D3), L9N P0U8A093

I/O (TRDY) P0U8A087

I/O, VREF 3, L10N P0U8A084

I/O, VREF 3, L12N P0U8A078

I/O, VREF 3 P0U8A076

MODE_1 FPGA_DONE
98
97
96
95
94
93
P0U8A092 92

P0U8A089 89

87
86
85
84
83
82
80
79
78
P0U8A077 77

76
75
FPGA_DONE
MODE_2 U8A FPGA_PROGRAM
FPGA_PROGRAM
I/O, VREF 2, P0U8A0100

P0U8A097

P0U8A094

MODE_3 XC2S100E-6TQ144C FPGA_DIN

P0U8A083
P0U8A086

P0U8A080
P0U8A0101

FPGA_DIN
I/O (IRDY)
I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O
L7P

I/O, VREF 2, L9P

I/O (D4), L10P

I/O (D6), L12P

L7N
I/O (D2), L8P_YY

I/O, L11P_YY
I/O (D5), L11N_YY

I/O (D7), L13P_YY

P0U8A095
P0U8A098

P0U8A085

P0U8A079
MODE_4 FPGA_CCLK

P0U8A082

P0U8A075
P0U8A0106

FPGA_CCLK
MODE_5 FPGA_INIT
I/O (D1),

FPGA_INIT
MODE_6
MODE_7
MODE_8 FPGA_M[0..2]
FPGA_M[0..2]

MODE FPGA_M0
MODE
BANK 2 BANK 3 P0U8A069 69 SLAVE FPGA_M1
I/O, L14P_YY RA13P0RA1308
C_CTRL P0U8A068 68 SLAVE_TDI# 1
P0RA1301 8 SLAVE_TDI FPGA_M2
C_CTRL I/O, L14N_YY P0U8A067
JTAG_CNCT_A 67 SLAVE_TCK# 2
P0RA1302 7
P0RA1307 SLAVE_TCK
I/O
PARALLEL TMS_SOFT_A 112 P0U8A066 66 SLAVE_TMS# 3
P0RA1303 6
P0RA1306 SLAVE_TMS
PARALLEL I/OP0U8A0112
(CS), L5P_YY I/O, VREF 4
TCK_SOFT_A 113 65
P0U8A065 SLAVE_MODE 4
P0RA1304 5
P0RA1305
FPGA_AUX[0..3]
C I/O (WRITE),
P0U8A0113
L5N_YY I/O FPGA_AUX[0..3] C
TDO_SOFT_A 114 P0U8A064 64 SLAVE_TDO
I/O
P0U8A0114
I/O, VREF 4, L15P_YY 100R
TDI_SOFT_A 115 P0U8A0115 P0U8A063 63 SPL1
I/O, VREF 1 I/O, L15N_YY
BANK 4

TMS_HARD 116
P0U8A0116
P0U8A060 60 SPL2 FPGA_AUX0
I/O I/O, L16P_YY
C_SPI_CLOCK_CLK TCK_HARD 117 P0U8A059 59 SPL3 FPGA_AUX1
C_SPI_CLOCK_CLK I/O,P0U8A0117
VREF 1, L4P_YY I/O, L16N_YY
TDO_HARD_A 118 P0U8A0118 P0U8A058 58 SPL4 FPGA_AUX2
I/O, L4N_YY I/O, VREF 4 P0U8A057
C_SPI_CLOCK_SEL TDI_HARD_A 121 P0U8A0121 57 SPL5 FPGA_AUX3
C_SPI_CLOCK_SEL I/O, L3P_YY I/O
BANK 1

TMS_SOFT_B 122 P0U8A0122 P0U8A056 56 SPL6

I/O, L3N_YY I/O (DLL), L17P
C_SPI_DIN TCK_SOFT_B 123 P0U8A0123
C_SPI_DIN I/O, VREF 1
TDI_SOFT_B 124 55 FPGA_INSTALLED

P0R4402
P0U8A055
I/O
P0U8A0124
GCK0, I FPGA_INSTALLED
TDI_HARD_B 125
I/O (DLL), L2P
P0U8A0125
P0U8A052 52 R44
GCK1, I
FPGA_CLK 126 1K

P0R4401
P0U8A0126
GCK2, I
BANK 5

P0U8A050 50 SPL7
I/O (DLL), L17N
REF_CLK 129 P0U8A049 49 SPL8
GCK3, I
P0U8A0129
I/O, VREF 5
P0U8A048 48 TP_U8-48
P0U8A022

P0U8A027

I/O, L18P_YY
P0U8A012
BANK 0

VCC JTAG_CNCT_B 131 47 TP_U8-47

P0U8A07

P0U8A047
I/O (DLL), L2N
P0U8A0131
I/O, L18N_YY
TDO_SOFT_B 132 P0U8A0132 P0U8A044 44 FPGA_AUX3 FPGA_ID[0..3]
I/O, VREF 0 I/O, L19P_YY FPGA_ID[0..3]
TDO_HARD_B 133 P0U8A0133 P0U8A043 43 FPGA_AUX2
I/O, L1P_YY I/O, VREF 5, L19N_YY
U7 C_SPI_SEL_FLSH2 134 P0U8A0134 BANK 7 BANK 6 42
P0U8A042 FPGA_AUX1
I/O, L1N_YY I/O
P0U8A011

P0U8A024

P0U8A032
P0U8A010

P0U8A023

P0U8A031

C_SPI_SEL_FLSH1 1P0U701 P0U7088 C_SPI_DOUT 137 P0U8A0137 P0U8A041 41 FPGA_AUX0 FPGA_ID0

S VCCP0U707 I/O, L0P_YY I/O, VREF 5 P0U8A040 RA16P0RA1604
C_SPI_DOUT 2P0U702 7 C_SPI_SEL_FLSH1 138 40 NEXUS_TDI# 5
P0RA1605 4 NEXUS_TDI FPGA_ID1
Q HOLD I/O, P0U8A0138
VREF 0, L0N_YY I/O
P0U8A029
P0U8A05

3P0U703 6 C_SPI_CLK C_SPI_CLK 139 39 NEXUS_TCK# 6 3 NEXUS_TCK FPGA_ID2

P0U8A018

P0U706 P0U8A039 P0RA1603

P0RA1606
W C I/O
P0U8A0139
I/O, L20P_YY
I/O (IRDY) P0U8A015

I/O, VREF 6, L24N

I/O, VREF 6, L22N

4 P0U704 5 C_SPI_DIN C_SPI_DIN 140 P0U8A0140 38 NEXUS_TMS# 7 2 NEXUS_TMS FPGA_ID3

I/O, VREF 7, L27P

I/O, VREF 7, L25P

P0RA1602
P0C1901 P0C1902

P0U705 P0U8A038 P0RA1607

VSS D I/O, VREF 0 I/O, L20N_YY
I/O, L25N P0U8A013
P0U8A08

C_SPI_CLOCK_CLK 141 8 1 FPGA_TDO

I/O, L24P P0U8A021

P0U8A026

P0RA1601
P0RA1608
I/O
P0U8A0141
I/O, L26N_YY

I/O, L23N_YY

I/O, L21N_YY
I/O, L26P_YY

I/O, L23P_YY

I/O, L21P_YY

C19 M25P80-VMW6 C_SPI_CLOCK_SEL 142 100R

I/O
I/O, VREF 7

I/O, VREF 6

P0U8A0142
I/O (TRDY)

100nF SPI_DIN
I/O, L27N

SPI_DIN
I/O, L22P

SPI_CLK
SPI_CLK
SPI_SEL
SPI_SEL
I/O
I/O

I/O

I/O

I/O

I/O

I/O

SPI_DOUT
SPI_DOUT
14P0U8A014

20P0U8A020

28P0U8A028

30P0U8A030

SPI_MODE
3P0U8A03
4P0U8A04

6P0U8A06

SPI_MODE
VCC
5

7
8
10
11
12
13

15

18

21
22
23
24
26
27

29

31
32

U6 FPGA_CLK_1 FPGA_TDO#
C_SPI_SEL_FLSH2 1P0U601 P0U6088 FPGA_CLK_2 FPGA_TDI FPGA_CLK_1
S VCC FPGA_CLK_1
C_SPI_DOUT 2P0U602 P0U607 7 FPGA_INSTALLED NEXUS_TDO
Q HOLD
3P0U603 6
P0U606 C_SPI_CLK FPGA_ID3 FPGA_DONE FPGA_CLK_2
W C FPGA_CLK_2
D 4 P0U604 5
P0U605 C_SPI_DIN FPGA_ID2 FPGA_TCK D
P0C2002 P0C2001

VSS D
FPGA_ID1 FPGA_TMS
C20 M25P80-VMW6 FPGA_ID0 FPGA_INIT
100nF SPI_DIN FPGA_CCLK REF_CLK
REF_CLK
SPI_CLK FPGA_DIN
SPI_SEL FPGA_PROGRAM FPGA_CLK
FPGA_CLK

Legacy documentation
SPI_DOUT FPGA_M0
SPI_MODE FPGA_M1
FPGA_M2

Altium Limited
Title Board-On-Chip Programmable Logic L3, 12a Rodborough Rd

refer to the Altium Wiki for current information

Frenchs Forest
Size: C Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:29 AM Sheet 04 of 16 Australia 2086
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_Spartan.SchDoc

1 2 3 4 5 6
 1 2 3 4

RAM_CS

RAM1_OE
A RAM1_WE A

RAM0_OE
RAM0_WE

RAM_ADDR[0..16]
RAM_ADDR[0..16]
VCC VCC

24

24
8

8
U15 U14
VCC

VCC

VCC

VCC

VCC
RAM_ADDR16 32P0U15032 RAM_ADDR16 32P0U14032

P0R5901
P0U15024

P0U14024
A16 A16

P0U1508

P0U1408
RAM_ADDR15 31P0U15031 RAM_ADDR15 31P0U14031
A15 A15
RAM_ADDR14 30P0U15030 12
P0U15012 RAM_ADDR14 30P0U14030 P0U14012 12 R59
A14 WE A14 WE
RAM_ADDR13 29P0U15029 28
P0U15028
RAM_ADDR13 29P0U14029 P0U14028
28 4K7

P0R5902
A13 OE A13 OE
B RAM_ADDR12 21P0U15021 5
P0U1505 RAM_ADDR12 21P0U14021 P0U1405 5
B
A12 CS A12 CS
RAM_ADDR11 20P0U15020 RAM_ADDR11 20P0U14020
A11 A11
RAM_ADDR10 19P0U15019 RAM_ADDR10 19P0U14019
A10 A10
RAM_ADDR9 18
P0U15018 RAM_ADDR9 18
P0U14018
A9 A9
RAM_ADDR8 17
P0U15017 RAM_ADDR8 17
P0U14017
A8 A8
RAM_ADDR7 16
P0U15016 RAM_ADDR7 16
P0U14016
A7 A7
RAM_ADDR6 15
P0U15015 RAM_ADDR6 15
P0U14015
A6 A6
RAM_ADDR5 14
P0U15014 RAM_ADDR5 14
P0U14014
A5 A5
RAM_ADDR4 13
P0U15013 VCC RAM_ADDR4 13
P0U14013 VCC
A4 A4
RAM_ADDR3 4 RAM_ADDR3 4P0U1404

P0C7502 P0C7501

P0C7402 P0C7401
P0U1504
A3 A3
RAM_ADDR2 3
P0U1503 RAM_ADDR2 3P0U1403
A2 A2
RAM_ADDR1 2
P0U1502 C75 RAM_ADDR1 2P0U1402 C74
A1 A1
RAM_ADDR0 1
P0U1501 100nF RAM_ADDR0 1P0U1401 100nF
A0 A0
RAM0_DATA7 27P0U15027 RAM1_DATA7 27P0U14027
IO7 IO7
RAM0_DATA5 26P0U15026 RAM1_DATA6 26P0U14026
IO6 IO6
RAM0_DATA3 23P0U15023 RAM1_DATA5 23P0U14023
IO5 IO5
RAM0_DATA2 22P0U15022 RAM1_DATA4 22P0U14022
IO4 IO4
RAM0_DATA0 11P0U15011 RAM1_DATA3 11P0U14011
C IO3 IO3 C
RAM0_DATA1 10P0U15010 RAM1_DATA2 10P0U14010
IO2 IO2
RAM0_DATA4 7P0U1507 RAM1_DATA1 7P0U1407
GND P0U15025

GND P0U14025
P0U1509

P0U1409
IO1 IO1
RAM0_DATA6 6P0U1506 RAM1_DATA0 6P0U1406
IO0 IO0
GND

GND
9

25

25
RAM0_DATA[0..7] IDT71V124SA15Y IDT71V124SA15Y
RAM0_DATA[0..7]

RAM1_DATA[0..7]
RAM1_DATA[0..7]

D D
Altium Limited
Title Board-On-Chip Static Ram 128k L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:29 AM Sheet 09 of 16 Australia 2086

1 refer to the Altium Wiki for current information

2
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_SRAM.SchDoc
3 4
 1 2 3 4

VCC

VCC

P0C501
2

1
D1 D2 D3 D4 D5 C5

P0C502
A 10uF A
Tant

BAS40-04

BAS40-04

BAS40-04

BAS40-04

BAS40-04
P0D102 P0D101 P0D202 P0D201 P0D302 P0D301 P0D402 P0D401 P0D502 P0D501

J3

P0D103

P0D203

P0D303

P0D403

P0D503
Dsub-15-Female-HD

3
R10 RED# 1
P0J301 11
P0J3011
RED0 P0R1001 P0R1002

680R 6
P0J306

R11 GREEN# 2
P0J302 12
P0J3012
RED1 P0R1101 P0R1102

330R 7
P0J307 VGA
BLUE# 3
P0J303 13
P0J3013

8
P0J308

R12 4
P0J304 14
P0J3014

GREEN0 P0R1201 P0R1202

680R 9
P0J309

R13 5
P0J305 15
P0J3015
GREEN1 P0R1301 P0R1302

330R 10
P0J3010

B B

P0J3016

P0J3017
R14

16

17
BLUE0 P0R1401 P0R1402

680R
R15
BLUE1 P0R1501 P0R1502

330R

HDRIVE

VDRIVE

VCC
P0RA208

P0RA207

P0RA206

P0RA205
8
7
6
5

RA2 VCC PS2 KEYBOARD

4K7
J4
P0RA201

P0RA202

P0RA203

P0RA204

1
P0J401
1
2
3
4

2
P0J402

C 3
P0J403 C
KBDATA SP0J40S
4
P0J404

5
P0J405
KBCLOCK
6
P0J406

8918-P6

J5
1
P0J501

2
P0J502

3
P0J503
MOUSEDATA SP0J50S
4
P0J504

5
P0J505
MOUSECLOCK
6
P0J506

8918-P6
PS2 MOUSE

D D
Altium Limited
Title Board-On-Chip VGA, KB, and Mouse L3, 12a Rodborough Rd

Legacy documentation
Frenchs Forest
Size: A Number: Revision: 1.06
NSW
Date: 10/02/2006 Time: 10:53:29 AM Sheet 15 of 16 Australia 2086

1 refer to the Altium Wiki for current information 2

File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\NanoBoard-NB1\BOC_VGA_KB_MOUSE.SchDoc
3 4
 C
B

D
A

IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9
IO10
IO11
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
RED1
RED0
JIOA0
JIOA1
JIOA2
JIOA3

SWR3
SWC3
BLUE1
BLUE0

VDRIVE
HDRIVE
GREEN1
GREEN0

SCL
KBDATA

SDA
CAN_TXD

KBCLOCK
CAN_RXD

1
1

121
122
123
124
125
126
127
128
131
132
133
134
135
136
137
138
139
140
141
143
144
156
158
159
160
161
162
163
164
165
166
167
168
169
170
173
174
175
176
177
178
179
180

IOP0U1A0128
P0U1A0175

P0U1A0170

P0U1A0121
P0U1A0122
P0U1A0123
P0U1A0124
P0U1A0126
P0U1A0134
P0U1A0135
P0U1A0136
P0U1A0137
P0U1A0138
P0U1A0139
P0U1A0140
P0U1A0141
P0U1A0159
P0U1A0160
P0U1A0161
P0U1A0162
P0U1A0163
P0U1A0164
P0U1A0165
P0U1A0166
P0U1A0167
P0U1A0168
P0U1A0177
P0U1A0178
P0U1A0179
P0U1A0180

P0U1A0127
P0U1A0156
P0U1A0176

(DQ1R6)
IO (DQ1R0)

IO, DPCLK4
P0HDR102

IO, LVDS75n
IO, LVDS75p
IO, LVDS74n
IO, LVDS74p
IO, LVDS73p
IO, LVDS71n
IO, LVDS71p
IO, LVDS70n
IO, LVDS70p
IO, LVDS69n
IO, LVDS69p
IO, LVDS68n
IO, LVDS68p
IO, LVDS59p
IO, LVDS58n
IO, LVDS58p
IO, LVDS57n
IO, LVDS57p
IO, LVDS56n
IO, LVDS56p
IO, LVDS55n
IO, LVDS55p
IO, LVDS54n
IO, LVDS52n
IO, LVDS52p
IO, LVDS51n
IO, LVDS51p

IO, VREF2B3
IO, VREF1B3
IO, VREF0B3
P0HDR101
1 2 CAN_TXD
P0HDR202 P0HDR104

P0U1A0143
P0U1A0144

IO, PLL2_OUTn
IO, PLL2_OUTp
P0HDR201
1 2 FPGA_CLK JIOA0 P0HDR103
3 4 CAN_RXD
P0HDR204 P0HDR106
SDA P0HDR203
3 4 REF_CLK JIOA1 P0HDR105
5 6 RED0
P0HDR206 P0HDR108
P0HDR205 P0HDR107

IO, LVDS59n (DM1R)

SCL 5 6 SWC3 JIOA2 7 8 RED1

IO, DPCLK5 (DQS1R)

IO, LVDS73n (DQ1R7)

IO, LVDS72n (DQ1R5)
IO, LVDS72p (DQ1R4)
IO, LVDS54p (DQ1R3)
IO, LVDS53n (DQ1R2)
IO, LVDS53p (DQ1R1)
P0HDR208 P0HDR1010
IO0 P0HDR207
7 8 SWR3 BANK 3 JIOA3 P0HDR109
9 10 GREEN0

P0U1A0158

P0U1A0131
P0HDR2010 P0HDR1012

P0U1A0125
P0U1A0132
P0U1A0133
P0U1A0169
P0U1A0173
P0U1A0174
IO1 P0HDR209
9 10 SWR2 120 P0U1A0181 181 AUDIO_SPI_CSn P0HDR1011
11 12 GREEN1
P0U1A0120
P0HDR2012 IO, LVDS76n IO, LVDS50nP0U1A0182 P0HDR1014
IO2 P0HDR2011
11 12 SWR1 119 P0U1A0119 182 BOC_CTS P0HDR1013
13 14 BLUE0
P0HDR2014
IO, LVDS76p IO, LVDS50pP0U1A0183 P0HDR1016
IO3 P0HDR2013
13 14 SWC2 118 P0U1A0118 183 BOC_TX P0HDR1015
15 16 BLUE1
P0HDR2016 IO, LVDS77n IO, LVDS49nP0U1A0184 P0HDR1018
IO4 P0HDR2015
15 16 SWC1 117 P0U1A0117 184 BOC_RTS P0HDR1017
17 18 HDRIVE
P0HDR2018 IO, LVDS77p LVDS49p
IO, P0U1A0185 P0HDR1020
IO5 P0HDR2017
17 18 SWC0 116 P0U1A0116 185 BOC_RX P0HDR1019
19 20 VDRIVE
P0HDR2020 IO, LVDS78n (DQ1B0) (DQ0T0)
IO, LVDS48nP0U1A0186 P0HDR1022
IO6 P0HDR2019
19 20 SWR0 115 P0U1A0115 186 RAM_ADDR0 P0HDR1021
21 22 KBCLOCK
P0HDR2022
IO, LVDS78p (DQ1B1) (DQ0T1)
IO, LVDS48pP0U1A0187 P0HDR1024
IO7 P0HDR2021
21 22 LCD_BCKL 114 P0U1A0114 187 RAM_ADDR16 P0HDR1023
23 24 KBDATA
P0HDR2024
IO, LVDS79n (DQ1B2) (DQ0T2)
IO, LVDS47nP0U1A0188 P0HDR1026
IO8 P0HDR2023
23 24 BUZZER 113 P0U1A0113 188 RAM_ADDR1 P0HDR1025
25 26 MOUSECLOCK
P0HDR2026 IO, LVDS79p (DQ1B3) (DQ0T3)
IO, LVDS47pP0U1A0193 P0HDR1028
IO9 P0HDR2025
25 26 LCD_E 108 P0U1A0108 193 RAM_ADDR15 P0HDR1027
27 28 MOUSEDATA
P0HDR2028 IO, DPCLK6 IO, DPCLK3 (DQS0T)P0U1A0194 P0HDR1030
IO10 P0HDR2027
27 28 RAM0_DATA7 107 P0U1A0107 194 RAM_ADDR2 P0HDR1029
29 30 FPGA_CLK_1
P0HDR2030
IO, VREF0B4 IO, VREF0B2 P0U1A0195 P0HDR1032
IO11 P0HDR2029
29 30 RAM0_DATA6 106
P0U1A0106 195 RAM_ADDR14 P0HDR1031
31 32 FPGA_CLK_2
P0HDR2032
IO IO
P0U1A0196 P0HDR1034
IO12 P0HDR2031
31 32 RAM0_DATA5 105 P0U1A0105 196 RAM_ADDR3 P0HDR1033
33 34 FPGA_INSTALLED
P0HDR2034
IO, LVDS80n IO, LVDS46nP0U1A0197 P0HDR1036
IO13 P0HDR2033
33 34 RAM0_DATA4 104 P0U1A0104 197 RAM_ADDR13 P0HDR1035
35 36 FPGA_ID3
P0HDR2036 IO, LVDS80p IO, LVDS46pP0U1A0200 P0HDR1038
IO14 P0HDR2035
35 36 RAM0_DATA3 101 P0U1A0101 200 RAM_CS P0HDR1037
37 38 FPGA_ID2
P0HDR2038 IO, LVDS85n IO, LVDS41nP0U1A0201 P0HDR1040
IO15 P0HDR2037
37 38 RAM0_DATA2 100 P0U1A0100 201 RAM1_OE P0HDR1039
39 40 FPGA_ID1
P0HDR2040
IO, LVDS85p IO, LVDS41pP0U1A0202 P0HDR1042
IO16 P0HDR2039
39 40 RAM0_DATA1 99 P0U1A099 202 RAM0_OE P0HDR1041
41 42 FPGA_ID0
P0HDR2042
IO, LVDS86n IO, LVDS40nP0U1A0203 P0HDR1044
P0HDR2041 P0HDR1043
VCC

IO17 41 42 RAM0_DATA0 98 P0U1A098 203 RAM1_DATA7 43 44 SPI_DIN

P0HDR2044
IO, LVDS86p LVDS40p
IO, P0U1A0206 P0HDR1046
IO18 P0HDR2043
43 44 SW0 95 P0U1A095 206 RAM1_DATA0 P0HDR1045
45 46 SPI_CLK
P0HDR2046 IO, LVDS87n IO, LVDS39n (DM0T)P0U1A0207 P0HDR1048
IO19 P0HDR2045
45 46 SW1 94 P0U1A094 207 RAM1_DATA6 P0HDR1047
47 48 SPI_SEL

2
2

P0HDR2048
IO, LVDS87p (DM1B) IO, LVDS39pP0U1A0208 P0HDR1050
IO20 P0HDR2047
47 48 SW2 93 P0U1A093 208 RAM1_DATA1 P0HDR1049
49 50 SPI_DOUT
P0HDR2050
IO, VREF1B4 IO, VREF1B2P0U1A0213 P0HDR1052
IO21 P0HDR2049
49 50 SW3 88 P0U1A088 213 RAM1_DATA5 P0HDR1051
51 52 SPI_MODE
P0HDR2052
IO, LVDS92p IO, LVDS34pP0U1A0214 P0HDR1054
IO22 P0HDR2051
51 52 SW4 87 P0U1A087 214 RAM1_DATA2 P0HDR1053
53 54 FPGA_TDO
P0HDR2054 IO, LVDS93n IO, LVDS33nP0U1A0215 P0HDR1056
IO23 P0HDR2053
53 54 SW5 86 P0U1A086 215 RAM1_DATA4 P0HDR1055
55 56
P0HDR2056 IO, LVDS93p IO, LVDS33pP0U1A0216 P0HDR1058
IO24 P0HDR2055
55 56 SW6 85 P0U1A085 216 RAM1_DATA3 P0HDR1057
57 58 FPGA_M1
P0HDR2058
IO, LVDS94n IO, LVDS32nP0U1A0217 P0HDR1060
IO25 P0HDR2057
57 58 SW7 84 P0U1A084 217 RAM_ADDR12 P0HDR1059
59 60 FPGA_M0
P0HDR2060
IO, LVDS94p IO, LVDS32pP0U1A0218 P0HDR1062
IO26 P0HDR2059
59 60 LED0 83 P0U1A083 218 RAM1_WE P0HDR1061
61 62 FPGA_PROGRAM
IO, LVDS95n IO, LVDS31n

BANK 4
P0HDR2062 P0U1A0219 P0HDR1064
IO27 P0HDR2061
61 62 LED1 82 P0U1A082 219 RAM_ADDR11 P0HDR1063
63 64 FPGA_DIN
IO, LVDS95p IO, LVDS31p
BANK 2

P0HDR2064 P0U1A0222 P0HDR1066

IO28 P0HDR2063
63 64 LED2 79 P0U1A079 222 RAM_ADDR4 P0HDR1065
65 66 FPGA_CCLK
P0HDR2066
IO, LVDS96p IO, LVDS30pP0U1A0223 P0HDR1068
IO29 P0HDR2065
65 66 LED3 78 P0U1A078 223 RAM_ADDR10 P0HDR1067
67 68 FPGA_INIT
P0HDR2068
IO, LVDS97n IO, LVDS29nP0U1A0224 P0HDR1070
IO30 P0HDR2067
67 68 LED4 77 P0U1A077 224 RAM_ADDR5 P0HDR1069
69 70 FPGA_TMS
P0HDR2070
IO, LVDS97p (DQ1B4) IO, LVDS29pP0U1A0225 P0HDR1072
IO31 P0HDR2069
69 70 LED5 76 P0U1A076 225 RAM_ADDR9 P0HDR1071
71 72 FPGA_TCK
P0HDR2072
IO, LVDS98n (DQ1B5) IO, LVDS28nP0U1A0226 P0HDR1074
IO32 P0HDR2071
71 72 LED6 75 P0U1A075 226 RAM_ADDR6 P0HDR1073
73 74 FPGA_DONE
P0HDR2074 IO, LVDS98p IO, LVDS28pP0U1A0227 P0HDR1076
IO33 P0HDR2073
73 74 LED7 74 P0U1A074 227 RAM_ADDR8 P0HDR1075
75 76 NEXUS_TDO
P0HDR2076
IO, VREF2B4 IO, VREF2B2 P0U1A0228 P0HDR1078
IO34 P0HDR2075
75 76 SP15 73 P0U1A073 228 RAM_ADDR7 P0HDR1077
77 78 FPGA_TDI
P0HDR2078
IO, DPCLK7 (DQS1B) DPCLK2
IO,P0U1A0233 P0HDR1080
IO35 P0HDR2077
77 78 SP14 68 P0U1A068 233 RAM0_WE P0HDR1079
79 80 NEXUS_TMS
P0HDR2080
IO, LVDS99n (DQ1B6) (DQ0T4)
IO, LVDS27nP0U1A0234 P0HDR1082
SP0 P0HDR2079
79 80 SP13 67 P0U1A067 234 TEST P0HDR1081
81 82 NEXUS_TCK
P0HDR2082 IO, LVDS99p (DQ1B7) (DQ0T5)
IO, LVDS27pP0U1A0235 P0HDR1084
SP1 P0HDR2081
81 82 SP12 66 P0U1A066 235 JIOB0 P0HDR1083
83 84 NEXUS_TDI
P0HDR2084
IO, LVDS100n (DQ0T6)
IO, LVDS26nP0U1A0236 P0HDR1086
SP2 P0HDR2083
83 84 SP11 65 P0U1A065 236 JIOB1 P0HDR1085
85 86 FPGA_AUX0
P0HDR2086
IO, LVDS100p IO, LVDS26p (DQ0T7)P0U1A0237 P0HDR1088
SP3 P0HDR2085
85 86 SP10 64 P0U1A064 237 JIOB2 P0HDR1087
87 88 FPGA_AUX1
P0HDR2088
IO, LVDS101n IO, LVDS25nP0U1A0238 P0HDR1090
SP4 P0HDR2087
87 88 SP9 63 P0U1A063 238 JIOB3 P0HDR1089
89 90 FPGA_AUX2
P0HDR2090
IO, LVDS101p LVDS25p
IO,P0U1A0239 P0HDR1092
SP5 P0HDR2089
89 90 SP8 62 P0U1A062 239 P0HDR1091
91 92 FPGA_AUX3
P0HDR2092
IO, LVDS102n (DEV_OE)
IO, LVDS24nP0U1A0240 P0HDR1094
SP6 P0HDR2091
91 92 SP7 61 P0U1A061 240 P0HDR1093
93 94
P0HDR2094
IO, LVDS102p BANK 1 IO, LVDS24p (DEV_CLRn) P0HDR1096
P0HDR2093
93 94 P0HDR1095
95 96
P0HDR2096 P0HDR1098
P0HDR2095 P0HDR1097
VCC

95 96 97 98
P0HDR2098 P0HDR10100
P0HDR2097 P0HDR1099

VCC
97 98 99 100
P0HDR20100
P0HDR2099
99 100
U1A
HDR1

HDR2
54075-1009

P0U1A01

54075-1009
IO,P0U1A03
5V

IO, LVDS21pP0U1A08
P0U1A07

IO, LVDS20pP0U1A013
IO, DPCLK1P0U1A012

P0U1A021
IO, LVDS21nP0U1A011

IO, LVDS2p P0U1A054

IO, P0U1A053
IO, LVDS3p P0U1A049
IO,P0U1A048

5V

3
3

P0U1A039
P0U1A038
IO, LVDS23p (INIT_DONE)

IO
IO
IO, LVDS22p (CLKUSR)

IO, LVDS0n
IO, LVDS0p
IO, LVDS1n
IO, LVDS1p
IO, VREF2B1
LVDS4n
IO, LVDS4p
IO, LVDS5n
IO, LVDS5p
IO, LVDS6n
IO, LVDS6p
IO, LVDS7n
IO, PLL1_OUTn
IO, PLL1_OUTp
IO (ASDO)
IO, LVDS16p
IO, LVDS17n
IO, LVDS17p
IO, LVDS18n
IO, LVDS18p
IO, LVDS19n
IO, LVDS19p
IO, LVDS22n
LVDS23n

IO, LVDS2n (DQ0L7)

(DQ0L6)
DPCLK0
IO, LVDS3n (DQ0L5)
(DQ0L4)
IO (nCSO)
IO, VREF1B1
IO, LVDS20n (DQ0L3)
(DQ0L2)
(DQ0L1)
(DQ0L0)

IO, LVDS16n (DM0L)

(DQS0L)
P0U1A05
P0U1A04
P0U1A02

P0U1A055
P0U1A023
P0U1A020
P0U1A019
P0U1A018
P0U1A017
P0U1A016
P0U1A015
P0U1A014

P0U1A050

P0U1A060
P0U1A059
P0U1A058
P0U1A057
P0U1A047
P0U1A046
P0U1A045
P0U1A044
P0U1A043
P0U1A042
P0U1A041
P0U1A037
Cyclone EP1C12Q240C8

8
7
6
5
4
3
2
1

IO, VREF0B1 P0U1A06

60
59
58
57
56
55
54
53
50
49
48
47
46
45
44
43
42
41
39
38
37
P0U1A024 24
23
21
20
19
18
17
16
15
14
13
12
11

P0U1A056
VREF

VCCINT
P0R302 P0R301
P0R202 P0R201

SP6
SP5
SP4
SP3
SP2
SP1
SP0
R3
R2

47R

SPI_SEL

SPI_DIN
SPI_CLK

IO35
IO34
IO33
IO32
IO31
IO30
IO29
IO28
IO27
IO26
IO25
IO24
IO23
IO22
FPGA_AUX0
FPGA_AUX1
FPGA_AUX2
FPGA_AUX3

SPI_DOUT
SPI_MODE
INIT_DONE
VCCINT

NEXUS_TDI
NEXUS_TCK
NEXUS_TMS

MOUSEDATA
NEXUS_TDO#

MOUSECLOCK
DO NOT INSTALL

P0R902 P0R901
VCC

R9

P0R401
4K7

R4
100R
P0R402

FPGA_M1
FPGA_M0
FPGA_TDI
NEXUS_TDO

FPGA_DIN

FPGA_TCK
FPGA_TMS
FPGA_TDO P0R501
R5
100R
P0R502

FPGA_CLK_2
FPGA_CLK_1

4
4

FPGA_TDO#

29
28
U1D
35
34
25

CLK1,
CLK0,
33 P0U1B033
155P0U1B0155
U1B

P0U1D029
P0U1D028
32 P0U1B032
148 P0U1B0148
149 P0U1B0149
147 P0U1B0147

P0U1B035
P0U1B034
P0U1B025

TDI

nCE
TMS
TDO
TCK

nCEO

Legacy documentation
MSEL1
MSEL0
DATA0

LVDSCLK1n
LVDSCLK1p

Cyclone EP1C12Q240C8
Cyclone EP1C12Q240C8
nCONFIG
CONF_DONE

nSTATUS
DCLK
P0U1B0145

P0U1B026

Nanoboard LOGO - 48mm

P0U1B0146
P0U1B036

26
36
VCC

146
145

P0U1D0152
P0U1D0153

CLK3, LVDSCLK2n
CLK2, LVDSCLK2p
VCCINT

112
92
70
172
157
130
231
209
189
51
22
9
P0R701
P0R601

1R
R7
1R
R6

152
153

P0C2102 P0C2101 P0C702 P0C701 P0C2702 P0C2701 P0C1302 P0C1301

U1C

P0U1C09

P0U1C092
P0U1C070
P0U1C051
P0U1C022

P0C1901 P0C1902 P0C502 P0C501

P0U1C0112
P0U1C0172
P0U1C0157
P0U1C0130
P0U1C0231
P0U1C0209
P0U1C0189
P0R702
P0R602
C7

C21
C27
C13

FPGA_CCLK#
Cyclone EP1C12Q240C8

VCCIO4
VCCIO4
VCCIO4
VCCIO3
VCCIO3
VCCIO3
VCCIO2
VCCIO2
VCCIO2
VCCIO1
VCCIO1
VCCIO1
0.1uF
0.1uF
0.1uF
0.1uF

C5

10 P0U1C010
C19

GND
0.1uF
0.1uF

40 P0U1C040
GND P0C2202 P0C2201 P0C802 P0C801 P0C2802 P0C2801 P0C1402 P0C1401
P0R801

P0U1C027 27
R8

52 P0U1C052
GND VCCA_PLL1 P0C2001 P0C2002 P0C602 P0C601
33R

P0U1C0154
REF_CLK
C8

69 P0U1C069 154
C22
C28
C14

FPGA_CLK

GND VCCA_PLL2
0.1uF
0.1uF
0.1uF
0.1uF

C6

71 P0U1C071
C20

GND
P0R802

80 P0U1C080
GND P0C2302 P0C2301 P0C902 P0C901 P0C2902 P0C2901 P0C1502 P0C1501
0.001uF
0.001uF

89 P0U1C089 P0U1C081 81
GND VCCINT
P0U1C0191
C9

91 P0U1C091 191
C23
C29
C15

GND VCCINT
P0U1C0110
0.1uF
0.1uF
0.1uF
0.1uF

96 P0U1C096 110
refer to the Altium Wiki for current information
5
5

GND VCCINT
102P0U1C0102 P0U1C090 90
P0C2402 P0C2401 P0C1002 P0C1001 P0C3002 P0C3001 P0C1602 P0C1601
FPGA_INIT

GND VCCINT
P0U1C072 72
FPGA_CCLK

109P0U1C0109
FPGA_DONE

GND VCCINT
111P0U1C0111 P0U1C0211 211
Title
C24
C10
C30
C16

GND VCCINT
P0U1C097
VCC

0.1uF
0.1uF
0.1uF
0.1uF

129P0U1C0129 97
FPGA_PROGRAM

GND VCCINT
VCCINT

Size: C

142P0U1C0142 P0U1C0229 229

P0R1002 P0R1001 GND VCCINT P0C2502 P0C2501 P0C1102 P0C1101 P0C3102 P0C3101 P0C1702 P0C1701
P0U1C0198
VCC

198
3V3 Decoupling
1V5 Decoupling

171P0U1C0171
GND VCCINT
R10
4K7

190P0U1C0190 P0U1C0204 204

C25
C11
C31
C17

GND VCCINT
Date: 7/02/2006

P0U1C0220
0.1uF
0.1uF
0.1uF
0.1uF

220
PLL Decoupling

192P0U1C0192
P0R1102 P0R1101 GND VCCINT
P0U1C0103
VCC

103
VCCINT P0C2602 P0C2601 P0C1202 P0C1201 P0C3202 P0C3201 P0C1802 P0C1801
R11
4K7
VCCINT

P0R102 P0R101
GND
GNDA_PLL2
GNDG_PLL2
GNDG_PLL1
GNDA_PLL1
C26
C12
C32
C18

P0U1C031
P0U1C030

P0U1C0151
P0U1C0150

VCC
0.1uF
0.1uF
0.1uF
0.1uF

R1

Number: 1
4K7

P0C301 P0C302 P0C102 P0C101 P0C401 P0C402 P0C202 P0C201

GNDP0U1C0199
GNDP0U1C0205
GNDP0U1C0210
GNDP0U1C0212
GNDP0U1C0221
GNDP0U1C0230
P0U1C0232
31
30

199
205
210
212
221
230
232
151
150
C3
C1
C4
C2

10uF
10uF
10uF
10uF

2
P0U202
1P0U201

3 P0U203
U2

A
NC

GND

Cyclone EP1C12 Daughterboard

Time: 3:57:47 PM Sheet 1 of 1

Revision: 1.02
VCC

Y
VCC
C33

0.1uF

SN74LVC1G04DBV
P0C3302 P0C3301
P0R1301

4
5
R13

P0U205
270R

P0U204
VCC
P0R1302

NSW
P0LED102
P0LED201

LED1

Australia 2086
Altium Limited

Frenchs Forest
LED2

6
6

P0LED101
P0LED202

HSMG-C170
HSMH-C170

L3, 12a Rodborough Rd

P0R1202
R12
270R
P0R1201
VCC
C
B

D
A

File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\Daughter Boards\NBP2 Altera Cyclone PQ208 Rev1.02\NBP2 Altera Cyclone PQ208 Rev1.02.Sch
 1 2 3 4 5 6 7 8

VCC
Spartan III ID = 0 = 0x0
FPGA_PROGRAM_R R1
P0R101 P0R102
U4 U3 4k7
VCC SRAM0_A4 1 P0U301 44
P0U3044
SRAM0_A5 SRAM1_A4 1 P0U401 44
P0U4044
SRAM1_A5
A4 A5 P0U3043 A4 A5 P0U4043 R2
SRAM0_A3 2 P0U302 43 SRAM0_A6 SRAM1_A3 2 P0U402 43 SRAM1_A6 FPGA_TDO_R
A3 A6 P0U3042 A3 A6 P0U4042 P0R201 P0R202
SRAM0_A2 3 P0U303 42 SRAM0_A7 SRAM1_A2 3 P0U403 42 SRAM1_A7 4k7
A2 A7 P0U3041 TP1 A2 A7 P0U4041 TP2
SRAM0_A1 4 P0U304 41 SRAM0_OE SRAM1_A1 4 P0U404 41 SRAM1_OE
A1 OE P0U3040 A1 OE P0U4040

FPGA_PROGRAM_R
P0TP101 P0TP201
R3

FPGA_INSTALLED
TP3 SRAM0_A0 5 P0U305 40 SRAM0_UB (RD0) SRAM1_A0 5 P0U405 40 SRAM1_UB (RD1) FPGA_INIT
A0 UB P0U3039 A0 UB P0U4039 P0R301 P0R302
(3V3) SRAM0_E 6 P0U306 39 SRAM0_LB SRAM1_E 6 P0U406 39 SRAM1_LB 4k7
E LB P0U3038 E LB P0U4038

FPGA_DONE_R
FPGA_CCLK_R

FPGA_AUX0_R
MOUSECLOCK
SRAM0_D0 7 P0U307 38 SRAM0_D15 SRAM1_D0 7 P0U407 38 SRAM1_D15 TP4 TP5

FPGA_TDO_R

FPGA_TMS_R
MOUSEDATA

FPGA_TCK_R
FPGA_CLK_1
FPGA_CLK_2
D0 D15 P0U3037 D0 D15 P0U4037

NEXUS_TMS
FPGA_TDI_R
NEXUS_TDO

NEXUS_TCK

FPGA_AUX1
FPGA_AUX2
FPGA_AUX3
FPGA_M2_R
FPGA_M1_R
FPGA_M0_R

NEXUS_TDI
VCC SRAM0_D1 8 P0U308 37 SRAM0_D14 SRAM1_D1 8 P0U408 37 SRAM1_D14 (PRGB) (CCLK)

FPGA_INIT
SPI_MODE
FPGA_ID3
FPGA_ID2
FPGA_ID1
FPGA_ID0

FPGA_DIN
VCC D1 D14 P0U3036 VCC D1 D14 P0U4036

KBCLOCK

SPI_DOUT
CAN_RXD
CAN_TXD
SRAM0_D2 9 36 SRAM0_D13 SRAM1_D2 9 36 SRAM1_D13 U1C

KBDATA

SPI_CLK

P0TP401

P0TP501
P0U309 P0U409

GREEN0
GREEN1

HDRIVE
VDRIVE

SPI_SEL
SPI_DIN
D2 D13 P0U3035 D2 D13 P0U4035
SRAM0_D3 10 P0U3010 35 SRAM0_D12 SRAM1_D3 10 P0U4010 35 SRAM1_D12

BLUE0
BLUE1

P0TP301
D3 D12 P0U3034 D3 D12 P0U4034

RED0
RED1
A 11 P0U3011 34 11 P0U4011 34 FPGA_CCLK_R R5 100R FPGA_CCLK AA22 P0U1C0AA22 P0U1C0A1
A1 A
VCC VSS P0U3033 VCC VSS P0U4033 P0R501 P0R502 GND CCLK
12 P0U3012 33 12 P0U4012 33 FPGA_DONE_R R6 100R FPGA_DONE AB21 P0U1C0AB21 P0U1C0A22
A22
VSS VCC P0U3032 VSS VCC P0U4032 P0R601 P0R602
GND DONE
SRAM0_D4 13 P0U3013 32 SRAM0_D11 SRAM1_D4 13 P0U4013 32 SRAM1_D11 P0U1C0B2 B2

P0HDR10100
P0HDR1010

P0HDR1012

P0HDR1014

P0HDR1016

P0HDR1018

P0HDR1020

P0HDR1022

P0HDR1024

P0HDR1026

P0HDR1028

P0HDR1030

P0HDR1032

P0HDR1034

P0HDR1036

P0HDR1038

P0HDR1040

P0HDR1042

P0HDR1044

P0HDR1046

P0HDR1048

P0HDR1050

P0HDR1052

P0HDR1054

P0HDR1056

P0HDR1058

P0HDR1060

P0HDR1062

P0HDR1064

P0HDR1066

P0HDR1068

P0HDR1070

P0HDR1072

P0HDR1074

P0HDR1076

P0HDR1078

P0HDR1080

P0HDR1082

P0HDR1084

P0HDR1086

P0HDR1088

P0HDR1090

P0HDR1092

P0HDR1094

P0HDR1096

P0HDR1098
D4 D11 P0U3031 D4 D11 P0U4031 GND
P0HDR102

P0HDR104

P0HDR106

P0HDR108

100
SRAM0_D5 14 P0U3014 31 SRAM0_D10 VCC SRAM1_D5 14 P0U4014 31 SRAM1_D10 FPGA_PROGRAM A2P0U1C0A2 P0U1C0B21
B21
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
D5 D10 P0U3030 D5 D10 P0U4030 R8 PROG_B GND
2
4
6
8
SRAM0_D6 15 P0U3015 30 SRAM0_D9 SRAM1_D6 15 P0U4015 30 SRAM1_D9 VCC FPGA_PROGRAM_R 8P0R808 1
P0R801 P0U1C0C9
C9
D6 D9 P0U3029 D6 D9 P0U4029 GND
HDR1 SRAM0_D7 16 P0U3016 29 SRAM0_D8 SRAM1_D7 16 P0U4016 29 SRAM1_D8 FPGA_M0_R 7P0R807 2
P0R802
FPGA_M0 AB2P0U1C0AB2 P0U1C0C14 C14
54075-1009-HD1 (WR0) SRAM0_W 17 P0U3017D7 D8 P0U3028
28 SRAM0_A18 (NC on 256kx8) (WR1) SRAM1_W 17 P0U4017D7 D8 P0U4028
28 SRAM1_A18 (NC on 256kx8) FPGA_M1_R 6P0R806 3
P0R803
FPGA_M1 AA1P0U1C0AA1
M0 GND
P0U1C0J3
J3
P0TP601 W A8 P0U3027 P0TP701 W A8 P0U4027 M1 GND
TP6 SRAM0_A8 18 P0U3018 27 SRAM0_A9 TP7 SRAM1_A8 18 P0U4018 27 SRAM1_A9 FPGA_M2_R 5P0R805 4
P0R804
FPGA_M2 AB3P0U1C0AB3 P0U1C0J9
J9
A18 A9 P0U3026 A18 A9 P0U4026 M2 GND
+5 SRAM0_A17 19 P0U3019 26 SRAM0_A10 SRAM1_A1719 P0U4019 26 SRAM1_A10 P0U1C0J10 J10
A17 A10 P0U3025 A17 A10 P0U4025 R9 P0R901 100R GND
P0HDR1011

P0HDR1013

P0HDR1015

P0HDR1017

P0HDR1019

P0HDR1021

P0HDR1023

P0HDR1025

P0HDR1027

P0HDR1029

P0HDR1031

P0HDR1033

P0HDR1035

P0HDR1037

P0HDR1039

P0HDR1041

P0HDR1043

P0HDR1045

P0HDR1047

P0HDR1049

P0HDR1051

P0HDR1053

P0HDR1055

P0HDR1057

P0HDR1059

P0HDR1061

P0HDR1063

P0HDR1065

P0HDR1067

P0HDR1069

P0HDR1071

P0HDR1073

P0HDR1075

P0HDR1077

P0HDR1079

P0HDR1081

P0HDR1083

P0HDR1085

P0HDR1087

P0HDR1089

P0HDR1091

P0HDR1093

P0HDR1095

P0HDR1097

P0HDR1099
P0HDR101

P0HDR103

P0HDR105

P0HDR107

P0HDR109

SRAM0_A16 20 P0U3020 25 SRAM0_A11 SRAM1_A1620 P0U4020 25 SRAM1_A11 FPGA_TDI_R 8P0R908 1 FPGA_TDI B1P0U1C0B1 P0U1C0J11
J11
A16 A11 P0U3024 A16 A11 P0U4024 TDI GND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
SRAM0_A15 21 P0U3021 24 SRAM0_A12 SRAM1_A1521 P0U4021 24 SRAM1_A12 FPGA_TDO_R 7P0R907 2
P0R902
FPGA_TDO B22P0U1C0B22 P0U1C0J12
J12
A15 A12 P0U3023 A15 A12 P0U4023 TDO GND
SRAM0_A14 22 P0U3022 23 SRAM0_A13 SRAM1_A1422 P0U4022 23 SRAM1_A13 FPGA_TCK_R 6P0R906 3
P0R903
FPGA_TCK A21P0U1C0A21 P0U1C0J13 J13
A14 A13 A14 A13 TCK GND
FPGA_TMS_R 5P0R905 4
P0R904
FPGA_TMS A20P0U1C0A20 P0U1C0J14
J14
TMS GND
SRAM 512Kx16 TSOP44 SRAM 512Kx16 TSOP44 P0U1C0J20
J20
AUDIO_SPI_CSn

100R R7 GND
RAM_ADDR16

RAM_ADDR15

RAM_ADDR14

RAM_ADDR13

RAM_ADDR12

RAM_ADDR11

RAM_ADDR10
RAM1_DATA7
RAM1_DATA0
RAM1_DATA6
RAM1_DATA1
RAM1_DATA5
RAM1_DATA2
RAM1_DATA4
RAM1_DATA3
TP8 FPGA_AUX0_R FPGA_AUX0 B3 P0U1C0K9 K9
RAM_ADDR0

RAM_ADDR1

RAM_ADDR2

RAM_ADDR3

RAM_ADDR4

RAM_ADDR5
RAM_ADDR9
RAM_ADDR6
RAM_ADDR8
RAM_ADDR7
P0U1C0B3
P0R702 P0R701 HSWAP_EN P0U1C0K10
GND
(VCCAUX = 2.5V) 100R K10

RAM1_WE

RAM0_WE
(2V5) GND

RAM1_OE
RAM0_OE
BOC_CTS

BOC_RTS

VCCAUX VCCINT P0U1C0K11 K11

RAM_CS
BOC_RX
BOC_TX

P0TP801
GND
G7P0U1C0G7 P0U1C0K12 K12

P0R1001
JIOA0
JIOA1
JIOA2
JIOA3

JIOB0
JIOB1
JIOB2
JIOB3
VCCINT GND

TEST
G8P0U1C0G8 P0U1C0K13
K13

P0TP1001

P0TP1101

P0TP1201
P0TP901
VCCINT GND
R10 G15P0U1C0G15 P0U1C0K14 K14
VCCINT GND
82R/1% G16P0U1C0G16 P0U1C0L9 L9

P0R1002
VCCINT GND
VREF TP9 TP10 TP11 TP12 H7P0U1C0H7 P0U1C0L10
L10

P0R1101
VCCINT GND
(TDI) (TDO) (TCK) (TMS) H16P0U1C0H16 P0U1C0L11 L11
VCCINT GND
R11 R7P0U1C0R7 P0U1C0L12 L12
VCCINT GND
680R/1% R16P0U1C0R16 P0U1C0L13
L13

P0R1102
VCCINT GND
T7P0U1C0T7 P0U1C0L14 L14
VCCINT GND
T8P0U1C0T8 P0U1C0M9 M9
VCCINT GND
T15P0U1C0T15 P0U1C0M10
M10
VCCINT GND
T16P0U1C0T16 P0U1C0M11 M11

FPGA_CLK_1
VCCINT GND
SRAM1_A13
SRAM1_A11
SRAM1_A12
SRAM1_D14
SRAM1_D13

SRAM1_A10

SRAM1_D15

SRAM1_A18

SRAM1_D10

SRAM1_D12
SRAM1_D11

SRAM1_A14
SRAM1_A15

SRAM1_A16
SRAM1_A17
M12
SRAM1_UB
SRAM1_OE

P0U1C0M12
SRAM1_LB
SRAM1_A9

SRAM1_D8
SRAM1_A7

SRAM1_D9
SRAM1_D3
SRAM1_A6

SRAM1_D2

SRAM1_D1

SRAM1_A5

SRAM1_D0

SRAM1_A0

SRAM1_A1

SRAM1_A3
SRAM1_A2

SRAM1_D4

SRAM1_A8

SRAM1_D6
SRAM1_D7

SRAM1_A4

SRAM1_D5
FPGA_CLK
GND

SRAM1_W
SRAM1_E

REF_CLK
VCCAUX P0U1C0M13
M13
GND
A6 P0U1C0M14 M14
JIOA3

JIOA2

JIOA1

JIOA0

SWC3

SWR3
SWR2

SWR1
P0U1C0A6
VCCAUX GND
RED0

A17 N9

SDA

SCL
P0U1C0N9

SP5

SP4

SP2

SP3

SP1
SP0
P0U1C0A17

IO0

IO1
IO2

IO3

IO4

IO5
IO6

IO7
VCCAUX GND
F1
P0U1C0F1
P0U1C0N10
N10
VCCAUX GND
F22P0U1C0F22
P0U1C0N11 N11
VCCAUX GND
U1B U1
P0U1C0U1 P0U1C0N12 N12
A10

D10

D11

A11

A12

D12

A13

P0U1B0D13 D13

A14

D14

P0U1B0A15 A15

D15

A16

D16

D17

A18

P0U1B0D18 D18

A19
VCCAUX GND
B10
C10

C11
B11

B12
C12

P0U1B0B13 B13

C13

P0U1B0B14 B14

B15

B16
C16

B17
P0U1B0C17 C17

P0U1B0B18 B18

C18

P0U1B0B19 B19

C19
B20
E10

E11

P0U1B0E12 E12

E13

P0U1B0E14 E14

P0U1B0E15 E15

E16

P0U1B0E17 E17
F10

F11

F12

F13

F14

F16

F17
IO P0U1A0A10

IO_L29N_0 P0U1A0D10

P0U1B0A12

IO_L31P_1 P0U1B0F12

IO/VREF_1 P0U1B0F13

P0U1B0E16
IO P0U1B0F16

P0U1B0F17
A3
A4

D5
A5

D6

D7

A7

D8

A8

A9

D9
IO_L15N_0 P0U1A0F6

IO_L27N_0 P0U1A0D9
B4
C5

B5

B6
C6

B7
C7

B8

B9

XC3S400-5FG456C U22 N13

P0U1B0F14

IO_L24P_1 P0U1B0A16
P0U1B0B16
NC P0U1B0C16
NC P0U1B0D16
E5

E6

E7

E8

E9
F6

F7

F9
IO_L09N_0 P0U1A0E5

IO_L16N_0 P0U1A0A7
NC P0U1A0B7

IO/VREF_0 P0U1A0D8
NC P0U1A0E8

P0U1C0N13
P0U1C0U22
VCCAUX GND
U1A AB6 P0U1C0N14 N14
P0U1C0AB6
VCCAUX GND
P0U1A0E10

P0U1A0B10

P0U1A0E11
P0U1A0F10

P0U1A0C10

P0U1A0F11

P0U1A0D11

P0U1B0A13

P0U1B0C13

P0U1B0E13

P0U1B0A14

P0U1B0D14

P0U1B0B15

P0U1B0D15

P0U1B0B17

P0U1B0D17

P0U1B0C18
P0U1A0C5

P0U1A0A5

P0U1A0D6

P0U1A0B6

P0U1A0D7

P0U1A0A8

P0U1A0E9

P0U1A0A9
P0U1A0A3

P0U1A0D5

P0U1A0B5

P0U1A0E6

P0U1A0C6

P0U1A0E7

P0U1A0C7

P0U1A0F7

P0U1A0B8

P0U1A0F9

P0U1A0B9

XC3S400-5FG456C AB17P0U1C0AB17 P0U1C0P3 P3

VCCAUX GND
IO/VREF_0
IO_L01P_0/VRN_0
IO_L01N_0/VRP_0
IO_L06P_0
IO_L06N_0
IO_L09P_0

IO_L10P_0
IO_L10N_0
IO_L15P_0

IO_L16P_0

IO/VREF_0

IO_L24P_0
IO_L24N_0
IO_L25P_0
IO_L25N_0
IO_L27P_0

IO_L28P_0
IO_L28N_0
IO_L29P_0

IO_L30N_0
IO_L30P_0
IO_L31N_0
IO_L31P_0/VREF_0
IO_L32N_0/GCLK7
IO_L32P_0/GCLK6

IO_L32N_1/GCLK5
IO_L32P_1/GCLK4
IO_L31N_1/VREF_1

IO_L30N_1
IO_L30P_1
IO_L29N_1
IO_L29P_1

IO_L28N_1
IO_L28P_1
IO_L27N_1
IO_L27P_1

IO_L25P_1
IO_L25N_1
IO_L24N_1

IO_L16N_1
IO_L16P_1
IO_L15N_1
IO_L15P_1

IO_L10N_1/VREF_1
IO_L10P_1
IO_L09N_1
IO_L09P_1
IO_L06N_1/VREF_1
IO_L06P_1
IO_L01N_1/VRP_1
IO_L01P_1/VRN_1
NC

NC

NC

NC

NC

NC
IO

IO

IO

IO

IO

IO

IO

IO
B P9 B

P0U1B0C19

P0U1B0B20
P0U1A0A11

P0U1B0C12
P0U1A0A4

P0U1A0B4

P0U1A0C11

P0U1A0B11

P0U1B0B12
P0U1C0P9

P0U1B0D12

P0U1B0A18

P0U1B0A19
GND
VCC P0U1C0P10 P10
GND
P0U1A0C20 C20 SWC2 C8P0U1C0C8 P0U1C0P11 P11
IO_L01N_2/VRP_2 VCCO_0 GND
P0U1A0C21 C21 SWC0 F8P0U1C0F8 P0U1C0P12 P12
IO_L01P_2/VRN_2 P0U1A0C22 VCCO_0 GND
C22 SWC1 G9P0U1C0G9 P0U1C0P13 P13
IO VCCO_0 GND
RAM1_DATA7 M1 P0U1A0M1 P0U1A0D19 D19 IO8 AUDIO_SPI_CSN C2
P0U1B0C2 P0U1B0M22 M22 SW1 G10P0U1C0G10 P0U1C0P14 P14
IO_L40P_6/VREF_6 IO_L16P_2 IO IO_L40N_3/VREF_3 VCCO_0 GND
RAM0_OE M2 P0U1A0D20 D20 IO10 CAN_RXD C3 P0U1B0M21 M21 SW2 G11P0U1C0G11 P0U1C0P20 P20
IO_L40N_6P0U1A0M2 IO_L16N_2 P0U1B0C3
IO_L01N_7/VRP_7 IO_L40P_3 VCCO_0 GND
SPI_SEL M3 P0U1A0D21 D21 LCD_BCKL CAN_TXD C4 P0U1B0M20 M20 IO23 P0U1C0Y9 Y9
IO_L39P_6
P0U1A0M3
IO_L17N_2 IO_L01P_7/VRN_7
P0U1B0C4
IO_L39N_3 GND
SPI_DOUT M4 P0U1A0D22 D22 SWR0 BOC_RTS D1 P0U1B0D1 P0U1B0M19 M19 IO24 G12P0U1C0G12 P0U1C0Y14 Y14
IO_L39N_6P0U1A0M4 IO_L17P_2/VREF_2 IO_L16N_7 IO_L39P_3 VCCO_1 GND
SP7 M5 P0U1A0M5 P0U1A0F18 F18 IO16 BOC_CTS C1 P0U1B0C1 P0U1B0M18 M18 IO21 G13P0U1C0G13 P0U1C0AA2 AA2
IO_L38P_6 IO_L19P_2 IO_L16P_7/VREF_7 IO_L38N_3 VCCO_1 GND
SP9 M6 P0U1A0E18 E18 IO9 BLUE0 E4 P0U1B0E4 P0U1B0M17 M17 IO28 G14P0U1C0G14 P0U1C0AA21 AA21
IO_L38N_6P0U1A0M6 IO_L19N_2 IO_L17N_7 IO_L38P_3 VCCO_1 GND
RAM1_DATA6 N1 P0U1A0N1
BANK 0 P0U1A0E19 E19 IO11 GREEN0 D4 P0U1B0D4 BANK 1 P0U1B0N22 N22 SW3 C15P0U1C0C15 P0U1C0AB1 AB1
IO_L35P_6 IO_L20N_2 IO_L17P_7 IO_L35N_3 VCCO_1 GND
RAM1_DATA0 N2 P0U1A0E20 E20 IO12 BOC_TX D2 P0U1B0D2 P0U1B0N21 N21 SW4 F15P0U1C0F15 P0U1C0AB22 AB22
IO_L35N_6P0U1A0N2 IO_L20P_2 IO_L19P_7 IO_L35P_3 VCCO_1 GND
RAM1_DATA1 N3 P0U1A0E21 E21 LCD_E RED1 D3 P0U1B0N20 N20 IO25
IO_L34P_6
P0U1A0N3
IO_L21N_2 IO_L19N_7/VREF_7
P0U1B0D3
IO_L34N_3
SPI_MODE N4 P0U1A0N4 P0U1A0E22 E22 BUZZER GREEN1 E3 P0U1B0E3 P0U1B0N19 N19 IO26 H20P0U1C0H20 P0U1C0H3 H3
IO_L34N_6/VREF_6 IO_L21P_2 IO_L20P_7 IO_L34P_3/VREF_3 P0U1B0N18 VCCO_2 VCCO_7
N5 P0U1A0N5 P0U1A0G17 G17 IO17 BLUE1 F4 P0U1B0F4 N18 H17P0U1C0H17 P0U1C0H6 H6
NC IO_L22N_2 IO_L20N_7 NC P0U1B0N17 VCCO_2 VCCO_7
N6 P0U1A0N6 P0U1A0G18 G18 RAM0_DATA4 RAM_ADDR0 E1 P0U1B0E1 N17 J16P0U1C0J16 P0U1C0J7 J7
NC IO_L22P_2 IO_L21N_7 NC P0U1B0P22 VCCO_2 VCCO_7
P1 P0U1A0P1 P0U1A0G19 G19 IO15 BOC_RX E2 P0U1B0E2 P22 K16P0U1C0K16 P0U1C0K7 K7
NC IO_L23P_2 IO_L21P_7 NC VCCO_2 VCCO_7
P2 P0U1A0P2 P0U1A0F19 F19 IO13 VDRIVE G6 P0U1B0G6 P21
P0U1B0P21 L16P0U1C0L16 P0U1C0L7 L7
NC IO_L23N_2/VREF_2 IO_L22N_7 NC P0U1B0P18 VCCO_2 VCCO_7
P4 P0U1A0P4 P0U1A0F20 F20 IO14 HDRIVE F5 P0U1B0F5 P18
NC IO_L24N_2 IO_L22P_7 NC P0U1B0P17
P5 P0U1A0P5 P0U1A0F21 F21 RAM0_DATA7 RAM_ADDR16 F2 P0U1B0F2 P17 M16P0U1C0M16 P0U1C0M7 M7
NC IO_L24P_2 IO_L23N_7 NC VCCO_3 VCCO_6
R1 P0U1A0R1 H19
P0U1A0H19 RAM_ADDR2 F3 P0U1B0F3 P19
P0U1B0P19 N16P0U1C0N16 P0U1C0N7 N7
NC NC P0U1A0G20 IO_L23P_7 NC P0U1B0R19 VCCO_3 VCCO_6
R2 P0U1A0R2 G20 KBCLOCK H5 P0U1B0H5 R19 P16P0U1C0P16 P0U1C0P7 P7
NC NC IO_L24N_7 NC P0U1B0R21 VCCO_3 VCCO_6
R5 P0U1A0R5 P0U1A0G21 G21 RAM0_DATA5 G5 P0U1B0G5 R21 R20P0U1C0R20 P0U1C0R3 R3
NC IO_L27N_2 IO_L24P_7 NC VCCO_3 VCCO_6
P6 P0U1A0P6 P0U1A0G22 G22 RAM0_DATA6 G3P0U1B0G3 R22
P0U1B0R22 R17P0U1C0R17 P0U1C0R6 R6
NC IO_L27P_2 P0U1A0H18 NC NC VCCO_3 VCCO_6
RAM1_DATA4 T1 H18 G4P0U1B0G4 P0U1B0T21 T21 LED0
BANK 6

BANK 2

BANK 7

BANK 3
IO_L27P_6
P0U1A0T1
NC P0U1A0J17 NC IO_L27P_3
RAM1_DATA2 T2 J17 RAM_ADDR15 G1 P0U1B0G1 P0U1B0T22 T22 SW7 U15P0U1C0U15 P0U1C0U8 U8
IO_L27N_6P0U1A0T2 NC IO_L27N_7 IO_L27N_3 VCCO_4 VCCO_5
R4 P0U1A0R4 H21
P0U1A0H21 RAM_ADDR1 G2 T19
P0U1B0T19 Y15P0U1C0Y15 P0U1C0Y8 Y8
NC NC P0U1A0H22 IO_L27P_7/VREF_7
P0U1B0G2
NC P0U1B0T20 VCCO_4 VCCO_5
T3 P0U1A0T3 H22 H1P0U1B0H1 T20 T14P0U1C0T14 P0U1C0T9 T9
NC NC P0U1A0J18 NC NC VCCO_4 VCCO_5
RAM1_DATA3 U2 J18 H2P0U1B0H2 P0U1B0T18 T18 IO29 T13P0U1C0T13 P0U1C0T10 T10
IO_L24P_6
P0U1A0U2
NC NC IO_L24P_3 VCCO_4 VCCO_5
RAM_ADDR12 U3 J19
P0U1A0J19 J4P0U1B0J4 P0U1B0R18 R18 SW5 T12P0U1C0T12 P0U1C0T11 T11
IO_L24N_6/VREF_6 P0U1A0U3
NC P0U1A0J21 NC IO_L24N_3 VCCO_4 VCCO_5
JIOB0 U4 J21 H4P0U1B0H4 P0U1B0U20 U20 SW6
IO_L23N_6P0U1A0U4 NC P0U1A0J22 NC IO_L23P_3/VREF_3
RAM1_DATA5 T4 J22 J5P0U1B0J5 P0U1B0U21 U21 LED1
IO_L23P_6
P0U1A0T4
NC NC IO_L23N_3
JIOB2 T5 K17
P0U1A0K17 J6P0U1B0J6 P0U1B0T17 T17 XC3S400-5FG456C
IO_L22P_6
P0U1A0T5
NC P0U1A0K18 NC IO_L22N_3
JIOB3 T6 K18 J1P0U1B0J1 P0U1B0U18 U18 IO32
IO_L22N_6P0U1A0T6 NC NC IO_L22P_3
RAM1_WE V1 P0U1A0K19 K19 IO18 J2P0U1B0J2 P0U1B0V21 V21 LED3
IO_L21P_6
P0U1A0V1
IO_L34N_2/VREF_2 NC IO_L21P_3
RAM_ADDR11 V2 P0U1A0K20 K20 RAM0_DATA3 K5P0U1B0K5 P0U1B0V22 V22 LED2
IO_L21N_6P0U1A0V2 IO_L34P_2 NC IO_L21N_3
NEXUS_TCK V3 P0U1A0K21 K21 RAM0_DATA1 K6P0U1B0K6 P0U1B0V20 V20 IO33
IO_L20P_6
P0U1A0V3
IO_L35N_2 NC IO_L20P_3
NEXUS_TMS V4 P0U1A0K22 K22 RAM0_DATA2 RAM_ADDR14 K3 P0U1B0K3 P0U1B0U19 U19 IO31
IO_L20N_6P0U1A0V4 IO_L35P_2 IO_L34N_7 IO_L20N_3
C FPGA_AUX1 V5 P0U1A0L17 L17 IO27 KBDATA K4 P0U1B0K4 P0U1B0W20 W20 IO34 C
IO_L19N_6P0U1A0V5 IO_L38N_2 IO_L34P_7 IO_L19P_3
TEST U5 P0U1A0L18 L18 IO20 RAM_ADDR13 K1 P0U1B0K1 P0U1B0W21 W21 LED5
IO_L19P_6
P0U1A0U5
IO_L38P_2 IO_L35N_7 IO_L19N_3
RAM_ADDR4 W1 P0U1A0L19 L19 IO22 RAM_ADDR3 K2 P0U1B0K2 P0U1B0W19 W19 SRAM0_A5
IO_L17P_6/VREF_6 P0U1A0W1
IO_L39N_2 IO_L35P_7 IO_L17P_3/VREF_3
RAM_ADDR10 W2 BANK 4 P0U1A0L20 L20 IO19 MOUSEDATA L5 P0U1B0L5 BANK 5 P0U1B0V19 V19 IO35
IO_L17N_6P0U1A0W2 IO_L39P_2 IO_L38N_7 IO_L17N_3
W3 P0U1A0L21 L21 SW0 MOUSECLOCK L6 P0U1B0L6 P0U1B0Y22 Y22 LED6
IO_L16P_6
P0U1A0W3
IO_L40N_2 IO_L38P_7 IO_L16P_3
NEXUS_TDI W4 P0U1A0L22 L22 RAM0_DATA0 SPI_DIN L3 P0U1B0L3 P0U1B0W22 W22 LED4 VCCAUX
IO_L31P_4/DOUT/BUSY

IO_L16N_6P0U1A0W4 IO_L40P_2/VREF_2 IO_L39N_7 IO_L16N_3 C58 C1 C59 C5 C6 C19 C20 C21 C22 C23 C24
RAM_ADDR5 Y1P0U1A0Y1 SPI_CLK L4 P0U1B0L4 P0U1B0Y19 Y19 SRAM0_A1
IO IO_L39P_7 IO_L01P_3/VRN_3

P0C5801

P0C5901

P0C1901

P0C2001

P0C2101

P0C2201

P0C2301

P0C2401
P0C101

P0C501

P0C601
IO_L01N_5/RDWR_B
RAM_ADDR9 Y2 RAM1_OE L1 Y20 SRAM0_A4
IO_L06N_4/VREF_4

IO_L27N_5/VREF_5
P0U1B0Y20

IO_L29P_5/VREF_5
IO_L01P_6/VRN_6 IO_L40N_7/VREF_7 IO_L01N_3/VRP_3
IO_L27N_4/DIN/D0

P0U1A0Y2 P0U1B0L1
IO_L32N_4/GCLK1

IO_L32N_5/GCLK3
IO_L31N_4/INIT_B
IO_L32P_4/GCLK0

IO_L32P_5/GCLK2
IO_L01N_4/VRP_4
IO_L01P_4/VRN_4

IO_L10P_5/VRN_5
IO_L10N_5/VRP_5
NEXUS_TDO Y3 RAM_CS L2 P0U1B0L2 Y21
P0U1B0Y21 LED7

IO_L01P_5/CS_B
IO_L01N_6/VRP_6 IO_L40P_7 IO

P0C5802

P0C5902

P0C1902

P0C2002

P0C2102

P0C2202

P0C2302

P0C2402
P0C102

P0C502

P0C602
P0U1A0Y3
IO_L30N_4/D2

IO_L28N_5/D6

IO_L31N_5/D4
IO_L30P_4/D3

IO_L27P_4/D1

IO_L28P_5/D7

IO_L31P_5/D5
10uF 220uF/4V 10uF 220nF 220nF 10nF 10nF 10nF 10nF 10nF 10nF
IO_L29N_4
IO/VREF_4
IO_L28N_4

IO_L25N_4

IO_L24N_4

IO_L16N_4

IO/VREF_4
IO_L15N_4

IO_L10N_4

IO_L09N_4

IO/VREF_4

IO_L06N_5

IO_L09N_5

IO_L15N_5
IO_L16N_5

IO/VREF_5

IO_L24N_5

IO_L25N_5

IO_L29N_5

IO_L30N_5

IO/VREF_5
IO_L29P_4

IO_L28P_4

IO_L25P_4

IO_L24P_4

IO_L16P_4

IO_L15P_4

IO_L10P_4

IO_L09P_4

IO_L06P_4

IO_L06P_5

IO_L09P_5

IO_L15P_5

IO_L16P_5

IO_L24P_5

IO_L25P_5

IO_L27P_5

IO_L30P_5
P0U1A0Y12

P0U1B0Y4
P0U1A0W18
P0U1A0AA14

P0U1B0W10
P0U1B0W9
P0U1A0AA12

P0U1A0AB12

P0U1B0AA11
P0U1A0W12

P0U1A0AA20

P0U1A0AB20

P0U1B0AA5

P0U1B0AB5

P0U1B0Y11
P0U1B0AA3
AB14 P0U1A0AB14
P0U1A0U12

P0U1A0V12

P0U1B0AA9

P0U1B0AB9

P0U1B0V11

P0U1B0W11
AB13 P0U1A0AB13

AA15 P0U1A0AA15

AA18 P0U1A0AA18

AB10 P0U1B0AB10

AB11 P0U1B0AB11
AA13 P0U1A0AA13

AB15 P0U1A0AB15

AA17 P0U1A0AA17

AB18 P0U1A0AB18

AA10 P0U1B0AA10
Y13 P0U1A0Y13

U13 P0U1A0U13

U14 P0U1A0U14

V16 P0U1A0V16

Y16 P0U1A0Y16
Y17 P0U1A0Y17

V17 P0U1A0V17

V18 P0U1A0V18

AB4 P0U1B0AB4

AA6 P0U1B0AA6

AB8 P0U1B0AB8

Y10 P0U1B0Y10
V13 P0U1A0V13

V14 P0U1A0V14

W16 P0U1A0W16

W17 P0U1A0W17

Y18 P0U1A0Y18

AA4 P0U1B0AA4

AA8 P0U1B0AA8
NC
NC
NC
NC

NC
NC

NC
NC
NC
NC

NC
Y5 P0U1B0Y5

W6 P0U1B0W6

U6 P0U1B0U6

W8 P0U1B0W8
VCCINT

W5 P0U1B0W5

V6 P0U1B0V6

Y6 P0U1B0Y6

V8 P0U1B0V8

V9 P0U1B0V9
IO

IO

IO

IO

IO
IO

IO
IO

IO
C60 C7 C8 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34
P0U1A0AA16

P0U1A0AB16

P0U1A0AA19

P0U1A0AB19
P0U1A0V15

P0U1A0W15

P0U1B0AA7

P0U1B0AB7
P0U1A0W13

P0U1A0W14

P0U1A0U16

P0U1A0U17

P0U1B0U10

P0U1B0V10

P0U1B0U11
P0U1B0W7

P0U1B0Y7

P0U1B0U9

P0C6001

P0C2501

P0C2601

P0C2701

P0C2801

P0C2901

P0C3001

P0C3101

P0C3201

P0C3301

P0C3401
P0C701

P0C801
P0U1B0U7

P0U1B0V7
AA12
AB12
W12
Y12
U12
V12

W13
AA14

W14

V15
W15
AA16
AB16
U16

U17

W18

AA19
AB19
AA20
AB20

AA3
Y4

AA5
AB5

U7
V7
W7
Y7
AA7
AB7

W9
AA9
AB9
U9
W10

U10
V10

U11
V11
W11
Y11
AA11

P0C6002

P0C2502

P0C2602

P0C2702

P0C2802

P0C2902

P0C3002

P0C3102

P0C3202

P0C3302

P0C3402
P0C702

P0C802
RAM_ADDR6
RAM_ADDR8

RAM_ADDR7
FPGA_AUX2 10uF 220nF 220nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF

FPGA_AUX3
FPGA_CLK_2
FPGA_INIT

SRAM0_D5
SRAM0_D7
SRAM0_D6
SRAM0_D8
SRAM0_D9
SRAM0_D10
FPGA_DIN

SRAM0_D12
SRAM0_D11
SRAM0_D4
SRAM0_D3

SRAM0_D13
SRAM0_D14
SRAM0_D15
SRAM0_D2
SRAM0_D1
SRAM0_D0
IO30
SRAM0_LB
SRAM0_UB
SRAM0_A0
SRAM0_E
SRAM0_A6
SRAM0_OE
SRAM0_A7

SRAM0_A3
SRAM0_A2

SRAM0_A13

SRAM0_A12

SRAM0_A11
SRAM0_A10

SRAM0_A14

SRAM0_A17
SRAM0_A15
SRAM0_A16

SRAM0_A18
SRAM0_A9

SRAM0_A8
RAM0_WE

SRAM0_W
JIOB1
SP10

SP11

SP14
SP12

SP15
SP13
VCC

SP8

SP6
C61 C2 C62 C9 C10 C11 C12 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45

P0C6101

P0C6201

P0C1001

P0C1101

P0C1201

P0C3501

P0C3601

P0C3701

P0C3801

P0C3901

P0C4001

P0C4101

P0C4201

P0C4301

P0C4401

P0C4501
P0C201

P0C901
P0C6102

P0C6202

P0C1002

P0C1102

P0C1202

P0C3502

P0C3602

P0C3702

P0C3802

P0C3902

P0C4002

P0C4102

P0C4202

P0C4302

P0C4402

P0C4502
P0C202

P0C902
P0TP1301

P0TP1401

10uF 220uF/4V 10uF 220nF 220nF 220nF 220nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF
TP13 (INIT) TP14 (DIN)
RAM0_DATA7
RAM0_DATA6
RAM0_DATA5
RAM0_DATA4
RAM0_DATA3
RAM0_DATA2
RAM0_DATA1
RAM0_DATA0

TP15 TP16 VCC

LED1 C64 C3 C63 C13 C14 C15 C16 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56
VCC (VCCINT = 1.25V)
LCD_BCKL
FPGA_CLK

(5V) (1V25)

P0C6401

P0C6301

P0C1301

P0C1401

P0C1501

P0C1601

P0C4601

P0C4701

P0C4801

P0C4901

P0C5001

P0C5101

P0C5201

P0C5301

P0C5401

P0C5501

P0C5601
P0C301
REF_CLK

VCC +5 U2 LM1084IS-ADJ VCCINT

BUZZER

P0TP1501

P0TP1601
R12 3 P0U203 P0U2022
LCD_E
SWC3
SWR3
SWR2
SWR1
SWC2
SWC1
SWC0
SWR0

IN OUT

P0C6402

P0C6302

P0C1302

P0C1402

P0C1502

P0C1602

P0C4602

P0C4702

P0C4802

P0C4902

P0C5002

P0C5102

P0C5202

P0C5302

P0C5402

P0C5502

P0C5602
P0C302
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7

VREF
SP15
SP14
SP13
SP12
SP11
SP10

P0LED102 P0LED101 P0R1202 P0R1201

SW0
SW1
SW2
SW3
SW4
SW5
SW6
SW7

270R
SP9
SP7
SP8

P0R1401

P0C401
HSMH-C170
C4 10uF 220uF/4V 10uF 220nF 220nF 220nF 220nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF 10nF
P0U201

R14

P0C402
100

220uF/4V
P0HDR20100
P0HDR2010

P0HDR2012

P0HDR2014

P0HDR2016

P0HDR2018

P0HDR2020

P0HDR2022

P0HDR2024

P0HDR2026

P0HDR2028

P0HDR2030

P0HDR2032

P0HDR2034

P0HDR2036

P0HDR2038

P0HDR2040

P0HDR2042

P0HDR2044

P0HDR2046

P0HDR2048

P0HDR2050

P0HDR2052

P0HDR2054

P0HDR2056

P0HDR2058

P0HDR2060

P0HDR2062

P0HDR2064

P0HDR2066

P0HDR2068

P0HDR2070

P0HDR2072

P0HDR2074

P0HDR2076

P0HDR2078

P0HDR2080

P0HDR2082

P0HDR2084

P0HDR2086

P0HDR2088

P0HDR2090

P0HDR2092

P0HDR2094

P0HDR2096

P0HDR2098
P0HDR202

P0HDR204

P0HDR206

P0HDR208

Do Not Mount
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98

D D
2
4
6
8

P0C1701

P0C6501

P0R1402
1

C18 VCC
HDR2 VCC C17 C65
P0C1702

P0C6502

54075-1009-HD2 P0C1801 P0C1802

220nF 10uF
P0R1501

P0C5701
P0R401

220nF
R4 R15 C57

P0C5702
P0HDR2011

P0HDR2013

P0HDR2015

P0HDR2017

P0HDR2019

P0HDR2021

P0HDR2023

P0HDR2025

P0HDR2027

P0HDR2029

P0HDR2031

P0HDR2033

P0HDR2035

P0HDR2037

P0HDR2039

P0HDR2041

P0HDR2043

P0HDR2045

P0HDR2047

P0HDR2049

P0HDR2051

P0HDR2053

P0HDR2055

P0HDR2057

P0HDR2059

P0HDR2061

P0HDR2063

P0HDR2065

P0HDR2067

P0HDR2069

P0HDR2071

P0HDR2073

P0HDR2075

P0HDR2077

P0HDR2079

P0HDR2081

P0HDR2083

P0HDR2085

P0HDR2087

P0HDR2089

P0HDR2091

P0HDR2093

P0HDR2095

P0HDR2097

P0HDR2099
P0HDR201

P0HDR203

P0HDR205

P0HDR207

P0HDR209

+5 4K7 U5 0R 10nF

Legacy documentation
P0R1502
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99

P0R402

1P0U501 P0U5055 LED2

NC VCC
FPGA_DONE_R 2 VCC
P0U502
A R13
3 P0U503 4
P0U504
GND Y P0LED202 P0LED201 P0R1301 P0R1302
270R
IO10
IO11
IO12
IO13
IO14
IO15
IO16
IO17
IO18
IO19
IO20
IO21
IO22
IO23
IO24
IO25
IO26
IO27
IO28
IO29
IO30
IO31
IO32
IO33
IO34
IO35

SN74LVC1G04DBV HSMG-C170 Altium Limited

SDA
SCL

Spartan III BGA456 Daughterboard

SP0
SP1
SP2
SP3
SP4
SP5
SP6
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
IO8
IO9

Title
VCCAUX L3, 12a Rodborough Rd

refer to the Altium Wiki for current information

Frenchs Forest
Size: A2 Number: 1 Revision: 1.01
NSW
Date: 7/02/2006 Time: 4:13:15 PM Sheet 1 of 1 Australia 2086
File: C:\Program Files\Altium Designer 6\Examples\Reference Designs\Daughter Boards\NBP11 Xilinx Spartan-III BGA456 Rev1.01\NB

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