High-Speed Board Design:

Designing with DDR4 and PCI

Express®
Jon Burnett
Board Solutions Hardware Design
Power Integrity, Signal Integrity

September 2019 | Session #AMF-SOL-T3518

Company Public – NXP, the NXP logo, and NXP secure connections for a smarter world are trademarks of NXP
B.V. All other product or service names are the property of their respective owners. © 2019 NXP B.V.
Agenda
• DDR Bus Topology Overview
− Data Bus
− MCK and Address Bus
• Example of DDR TOOLS ‒ QCVS
• PCB Design Considerations for DDR
− Basic IO buffer model simulations
• High Speed SERDES Background
• PCB Design Items:
− Length & Loss (Insertion Loss)
− Discontinuities (Return Loss)
• IBIS-AMI Simulation Examples

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DDR Bus Topology Overview

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DDR Bus Overview
• Source Synchronous Buses
• Large, parallel buses
− DDR2, DDR3 DIMM – 240 pins; DDR4 DIMM – 288 pins
− ~150 signals 64-bit data

• Bus timing
− Strobe to Data (DQS to DQ)
▪ DDR Double Data Rate – DDR bus is DQ
− Clock to Address/Command/Control (MCK to
ADDR,CMD,CNTL)
▪ Not Double Data Rate
− Clock to Strobe (MCK to DQS)

• PCB Applications
− DIMM-based
− Memory-Down Discrete-Memory based

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 CPU: Address Bus
DIMM-based Design
• PCBs with DIMM connector
• High Level Overview Figures for Context
− Note Data vs. Address Bus
− Number of Layers
DDR DIMM Connector − Alternating Layers for Byte Lanes
− Mostly/usually stripline (Internal Layer) routes

CPU Data Bus CPU Data Bus

DDR DIMM Connector

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Memory Down/Discrete Memory Example
Lighter loads often; If lower layer count PCB, can be congested

Address Address

Byte Byte
Lanes Lanes

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Hardware SPEC

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Hardware Spec DDR Items
• Pin Out
− Like shown before
− Ball Map Pattern
▪ Optimized for DDR routing

• Pin Listing
− Signal Listing
− Includes supply voltage, IO buffer type

• Impedances
− Lists targeted DDR IO buffer impedances
− Based on calibrated IO buffer

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Hardware Spec DDR Items (2)
• Supply Voltages
− Absolute Maximum Ratings
− Recommended Operating Conditions
▪ Voltage Tolerance
− Power Sequencing

• DC Specs
− Vref
▪ As relates to GVdd and Trained Values

• AC Specs
− Read and write specs
− Setup and Hold values (pre DDR4)
− Valid data eye

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DDR Tools ‒ QCVS

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DDR QCVS Tool
Tool can be used to choose optimal
driver strength, ODT values, CLK_ADJ
position (plus many more features).

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One Solution is to Follow Routing Rules and Configure With
QCVS

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Basic Simulation Examples

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MCK, ADDR Bus Topology
• Show ADDR, MCK
• Driver
Controller

• Receiver
• PCB
Controller
• Termination on Board (Rtt)
• Mention DDR2 vs. DDR3 style
− DDR2 tee structure
− DDR3 fly by routing

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Tee vs. Daisy Chain
• Basic options for connecting multiple loads
• Tee to multiple, parallel route
• Daisy chain, serial route

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Tee Route Waveforms
• Tee Route
• Signals arrive at destinations at same time – split at tee and reflect at receivers
• Simpler means for accounting for clocks
• Design with strong driver and series resistor optimization (typically)

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Daisy Chain Route: Unterminated
• Voltage divider at driver
• Wave propagates down transmission line
• Receivers near driver experience stairstep as they “wait” for reflection
− ~300 ps between first and last RX
− Waveforms do not arrive at the same time for receivers like in tee route

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Daisy Chain Route: Unterminated (Eye)
• Eye vs Transient Plot
− Waveforms for all but the end receiver exhibit stairsteps
▪ Since reflection from the end of the transmission line, due to no termination
▪ Supply voltage is 1.50V; Stairstep in this case is ~0.75V

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Daisy Chain Route: Terminated
• Voltage divider at driver
• Wave propagates down transmission line but no reflection at end now
− Waveform will be reduced swing
• Delays are similar
− ~300 ps between first and last RX

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Daisy Chain: Terminated, Unterminated
• Driver Stairstep amount is similar
• Receiver Amplitude is similar
• DC offset depends on termination voltage

Unterminated

Terminated Mid Point (DDR3 DQ) Terminated Tied to 0V (LPDDR4 DQ) Terminated Tied to Supply Voltage (DDR4 DQ)

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Daisy Chain Route: Terminated (Eye)
• Eye vs Transient Plot
− Notice that the eye does not show stairstep characteristics for this end terminated case

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Daisy Chain Unterminated vs Terminated

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Show DDR2 (Tee) vs DDR3 (Daisy Chain) Type of
Waveform/Route
• Series terminated for Tee
• End terminated for Daisy Chain
• Both can produce a monotonic signal at the receivers when constructed properly
− End terminated will require the ability to account for shifted signals, like for MCK

Tee Daisy Chain

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Timing Budgets
• Micron App Notes laid good groundwork
− Broke out bus timing into parameters like ISI, Crosstalk, Static Matching
• Automated tools
− Use memory and controller timing models
− Use timing specs to build pass-fail cases for DDR bus conditions
▪ MCK-Address
▪ DQS-DQ Read
▪ DQS-DQ Write
▪ DQS-MCK
• Many specs to check against, especially if include JEDEC signal quality
specs
• Timing for the PCB and controller may be tighter, since memory can take >
33% of budget

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Simulation Side Note on Probing
and MBPS

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Data Eye, Bit Time and Unit Interval
Note: GHz vs. Gbps

Clock: 1.0 GHz

• Rising Edge to Rising Edge:
1000 ps
• Bit Time: 500 ps
• Data Rate: 1/Bit Time or 1/UI=
1/500ps or 2 Gbps

So Data Rate is 2x “Clock”

Data Eye

Bit Time or Unit Interval (UI)

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Die vs. Pin Probing
• Important for Read Timing
Simulations if CPU has larger
package size
− This is a series of plots from the DDR3 and
DDR4 app notes.
− Simulated vs measured data for read
signals into the controller
• Package length for the controllers
can be long as compared to edge
rates
− Memory packages usually have shorter
package delays

• When probing at the pin, location

could be a long distance from the
end of the transmission line.

• For SI work, probe at the die.

• With knowledge of the package

length and RX loading, can predict
signal at die.

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Detailed DDR Simulations

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Data Eye Detail Example: Driver Impedance Change
• Show Eye Height for TX driver impedance change
− Get similar amplitude for Driver Impedance 50 ohms and ODT 120 ohms (green
waveform on right) as Driver Impedance 30 ohm and ODT 60 ohms (blue waveform on
left)
▪ Similar observations for other combinations of weaker driver, weaker ODT vs stronger driver,
stronger ODT (need to observe eye width, set up & hold, signal quality, too)

Driver 30 ohms; PCB Zo = 50; Vary ODT: 30, 40, 60, 120 Driver 50 ohms; PCB Zo = 50; Vary ODT: 30, 40, 60, 120

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PCB Impedance Change
• Data DQ: Single memory load PCB Zo = 60; TX = 30; ODT = 40; EW = 607
• Driver Impedance = 30 ohms
• ODT = 40 ohms
• Alter PCB Zo
− 60, 50, 40 ohms
• Use PRBS pattern for TX PCB Zo = 50; TX = 30; ODT = 40; EW = 616

• Track Eye Width:

− Zo 60: 607 ps
− Zo 50: 616 ps
− Zo 40: 620 ps
PCB Zo = 40; TX = 30; ODT = 40; EW = 620

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Pre Layout Pre Route: MCK and MA
• Routing • Driver characteristics
− RX load spacing − Impedance: Strong, weak?
− Stub Lengths − Edge Rate
• PCB impedance • Termination
− Can Zo other than 50 ohms be used? − Strong, weak?
− Can multiple impedances be used? − Power considerations?
− Lead In
▪ Driver to 1st memory load
Lead-in Region Loaded Memory Region
− Memory Load
▪ 1st to last memory load

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Loaded PCB Region
• Can use distributed memory load to calculate loaded PCB impedance (approximate) for
that region

• Example:
− PCB trace impedance = 50 ohms
▪ Inductance per inch = 8.73 nH
▪ Capacitance per inch = 3.48 pF
− Capacitance per memory = 1.0 pF
− Spacing for memory = 0.575 inches
− Number of memory loads = 4

− Loaded capacitance for the 4 x 0.575 inch (2.3 inch) region is 4 pF

▪ 4 pF/2.3 inch = 1.74 pF/inch
▪ Add to capacitance per inch (intrinsic for PCB) = 3.48 + 1.74 pF = 5.22 pF

− Loaded PCB impedance = sqrt (L/C) = sqrt (8.73*1000/5.22) = 40.9 ohms

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Loaded PCB Region Waveforms
• Can design PCB route prior to memory region and Rtt value to match
loaded impedance for the memory region
− See below for the 50 ohm PCB trace that has a 40.9 ohm loaded impedance
− Waveforms most affected are the initial 2-3 RX loads

PCB Zo = 50 for all routes, Rtt = 50 PCB Zo = 40 lead in; 50 memory;, Rtt = 40

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Loaded PCB Region/Values
• Approximate loaded region with
transmission line of adjusted impedance
and delay

• Examples of loaded impedance values*:

− PCB 50 ohms, 4 x 1 pF loads: 41 ohms
− PCB 45 ohms, 4 x 1 pF loads: 37 ohms
− PCB 40 ohms, 4 x 1 pF loads: 34 ohms All PCB impedance = Rtt

− PCB 62 ohms, 4 x 2 pF loads: 41 ohms

− PCB 50 ohms, 4 x 2 pF loads: 35 ohms
− PCB 45 ohms, 4 x 2 pF loads: 33 ohms
Tune Lead In Zo and Rtt
▪ * depends on length of loaded region (pF/length)
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Aside: Loaded Transmission Line (from MECL System
Design Handbook)

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Stub Length – Shorter is Better
• Example: stub lengths of 2, 20, 100, 200,
400 mils
− Delays approximately: 0.35, 3.5, 17.4, 34.8, 69.6 ps, 400 mil
respectively
− Plots are of first (green), second (blue) and last (pink)
loads for a 16 load bus
− Memory package length could be 20-35 ps (like the
200 mil case here)
200 mil

2 mil 20 mil 100 mil

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Stub Length – Faster Edge Rates Worse
• Same as prior slide, except for a faster
edge rate driver
− Example: stub lengths of 2, 20, 100, 200, 400 mils
▪ Delays approximately: 0.35, 3.5, 17.4, 34.8, 69.6 ps,
respectively 400 mil

▪ Plots are of first (green), second (blue) and last (pink)

loads for a 16 load bus
▪ Memory package length could be 20-35 ps (like the 200
mil case here)

200 mil

2 mil 20 mil 100 mil

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100 mil Stub; Slower and Faster Edge Rates

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Example of Microstrip/External Layer vs. Stripline/Internal
Layer Coupling
• Be careful with routing on external layer for higher-speed signals
• Routing guideline may cause for signals on external layers to be spaced 2-3x
more than internal layers

External Layer Separation 3X Internal Layer Separation 1X

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Address, Daisy Chain Bus Items to Optimize
• Make stubs short
• Minimize receiver loading
• Try to use slower edge rate driver
• Examine loaded PCB trace region
− Consider matching Lead In PCB impedance to loaded PCB impedance
− Consider matching Rtt to Lead In PCB and Loaded PCB Impedance
• Examine different Rtt values and PCB values within the limits of your design
− May not be able to use < 40 ohm traces on a ~50 ohm PCB with layer limitations
▪ Might consider slightly higher impedance values in memory region to offset for loading effects
 Have not done this on internal DN PCB designs

Fast edge, 300 mil stub, Zo same Fast edge, 300 mil stub, Zo tuned Slow edge, 300 mil stub, Zo same

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DDR4 Items

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DDR4 Feature: Pseudo-Open Drain (from FTF-NET-F0149)

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DDR4: Vary Driver Impedance
• Note change in Eye Center Level (DDR4 has Voltage Level Training)

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DDR4: Vary ODT Value
• Note change in Eye Center Level (DDR4 has Voltage Level Training)

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DDR3 vs DDR4: Notice DDR3 Centered at GVdd/2

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 Summary
• DDR Bus PCB-based Design can be complex and time consuming.
− Many signals
− Many opportunities for coupling
− Many settings for driver strength, termination, possibly PCB impedances
− Faster speeds bring faster edge rates, which exacerbate routing traits, like stub lengths
− Optimize routing where possible, but PCB layout and stackup may restrict options
▪ Margins may still be good, so it may not be necessary to make timing
• Automated tools based on IBIS models can help speed process and provide many
checks vs a large number of JEDEC-based specs.
• NXP has multiple documents to assist in PCB design.
• NXP has useful QCVS tool for DDR configuration.
− Complements IBIS simulation for driver strength and ODT value optimization.
• FAE and Hotline support is available for questions related to DDR and PCB
design.

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References
• NXP QCVS DDR Tool User Guide
• NXP AN3940, Hardware and Layout Design Considerations for DDR3
SDRAM Memory Interfaces
• NXP AN5097, Hardware and Layout Design Considerations for DDR4
SDRAM Memory Interfaces
• NXP AN4039, PowerQUICC and QorIQ DDR3 SDRAM Controller Register
Setting Considerations

• Micron Technical Notes

− TN-46-07, DDR333 Design Guide For Two-DIMM Systems.
− TN-47-01, DDR2-533 Design Guide For Two-DIMM Unbuffered Systems.
− TN-41-08, Design Guide for Two DDR3-1066 UDIMM Systems.

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High-Speed SERDES, With PCIe

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Agenda
• DDR Bus Topology Overview
− Data Bus
− MCK and Address Bus
• Example of DDR TOOLS ‒ QCVS
• PCB Design Considerations for DDR
− Basic IO buffer model simulations
• High Speed SERDES Background
• PCB Design Items:
− Length & Loss (Insertion Loss)
− Discontinuities (Return Loss)
• IBIS-AMI Simulation Examples

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IBIS-AMI Model Sections
• IBIS-AMI model
− Top level is “.ibs” file, like standard IBIS
▪ Has pin listing, signal to model name mapping, diff pair listing, etc.
▪ Uses standard analog modeling for driver impedance, capacitive loading, edge rates, etc.
• “analog IBIS”

− Parameter file – “.ami” file

▪ Text file that is readable by user
▪ Sets values to be used in DLL model file

− DLL
▪ Where algorithms are modeled in AMI language
▪ Compiled to protect the proprietary TX and RX model information
▪ IBIS >= 5.1 compliant allows it to run in multiple tools

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Pre- and Post-RX EQ Waveform Probing Locations
Probe at RX Pin

IBIS or SPICE,
No EQ

For TX EQ, could probe at RX Probe Here for Pre RX or Probe Here for Post
pin or prior to see EQ effects No RX AMI EQ Waveform RX EQ Waveform

With EQ TX EQ RX EQ

IBIS 2-tap IO IO IBIS-AMI

or Buffer Buffer
IBIS-AMI (IBIS) (IBIS)

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SERDES TX and RX EQ Notes

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SerDes IBIS-AMI Model and Transmitter Configuration
• TX Model includes Equalization Options
− No Equalization
− 2-Tap (Post-Cursor, De-emphasis)
− 3-Tap (Pre-Cursor, Post-Cursor)

• TX Model includes Amplitude Adjustment

− Matches to protocol
− Usually full swing

• TX Model: Post-Cursor (1)

− Ranges from: 0 to 2-3x Ratio
▪ PCIe used dB ration (-3.5 dB, -6.0 dB)
− Some designs include a second post-cursor

• TX Model: Pre-Cursor
− Smaller ratio than Post-Cursor, typically

• RX Model: May Include Adaptive Equalization

− Some models may have ability to communicate from RX to TX (Backchannel)

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Example of TX and TX EQ Control: Amplitude and
De-emphasis
1.100X (Red)

0.170X (Pink)

~ +/- 550 mV
To
~ +/- 85 mV

1.0X is +/- 500 mV (Blue)

No EQ (Gold)

3.00 X (Light Blue)

Orange waveform:
2.0X setting
Ratio: +/- 250 mV
Vs. +/-500 mV = 2.0X

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Basic TX EQ: 2-tap De-emphasis:
Alter Post-Cursor Setting

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TX EQ (TX Green; RX Red)
TX: 2x 330mV Vs. 2x 500 mV TX: 2x 250 mV Vs 2x 500 mV
or 1/.66=1.5 or 1/0.50=2.0

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TX EQ: -3.5 or 1.5x ratio
TX: Has 2x 330mV Vs. 2x 500 mV RX

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TX EQ: -6.0 or 2.0x Ratio
TX: 2x 250 mV Vs 2x 500 mV or RX
1/0.50=2.0

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TX EQ @ RX
TX 1.5 TX 2.0

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Printed Circuit Board (PCB)
Considerations

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Checklist from PCI-Express End Point App Note
• Layout and Routing Guidelines based on 8Gbps rules • Breakout routing of diff pairs per guideline; avoid dog-bone in
− AC coupling caps placed symmetrically? Near one end of the BGA area
channel? • Neckdown of trace width / spacing in breakout areas per
− AC coupling caps located near TX end when connector is guideline; care with impedance matching
implemented in system • Differential vias:
− TX and RX data and REFCLKs routed as diff pairs − Thru-hole vs. microvia choice; each meets aspect ratio requirements
− Diff pairs routed symmetrically? − Four or fewer vias in TX channel
− No stubs anywhere in the diff pair routing − Two or fewer vias in RX channel
− No routing over plane splits or anti-pads − Use smallest via possible; pads removed from via on internal layers
− Oblique routing used for diff pairs − Increase via pair anti-pad to match impedance
− Add GND stitching vias near diff pair vias
− Diff pair (P-N) matching to within 10 mils for TX and RX data diff
pairs − Back-drill thru-hole differential vias to remove stubs
− Diff pair (P-N) matching to within 5 mil for REFCLK diff pairs • Cutout GND underneath pads of components in differential
− Max length of all diff pairs on add-in card < 4 inches
pairs
• Remove all reference planes underneath edge fingers of add-
− Diff pair length matching near the location of mismatch; within
guidelines for sectional jogs? in cards
− Lane-to-lane skew within tolerance • Add-in card comply with mechanical form factor dimensions
− Serpentine bends within guideline (no sharp angles)

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Pads: Connector, AC Cap, Device
• Consider cutting out plane under pad
(since pads are much wider than trace
width for the chosen PCB impedance)
− AC cap pads
− Connector pads
− BGA pads
− Padsare cut out to
~match pad width Top & Gnd Gnd

▪ Reduces capacitance
& reduces impedance
discontinuity
▪ Connector footprints
may specify pad cutouts

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PCB Vias
• PCB Vias (diff pair) often will be
<100 ohms on thicker single lam
boards
− ~100 mil PCB, 10 mil drill, ~40 mil pitch
• Consider creating larger antipad for
planes in the stackup to reduce
capacitance and raise impedance\
• Work with PCB Fab House to use
best drill size
− Small drill usually raises via impedance
− Small drill size may be more costly

• Remove unused pads on vias

• Diff pair Vias from board with
antipad cutouts shown
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BGA Breakout Dual Track with Neck Down

• Breakout on which
layer?
− Top Layer
− Bottom Layer
− Internal Layers
▪ Via Stubs due to internal
layer choice?
▪ Stripline with short via stub
▪ Stripline with micro via or
back drilled via
− Trace Width Management
▪ Neckdowns? Dual Track
Routing?
▪ Dog Bones, Via in Pad? Dog Bone Via Stubs
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Fiber Weave Effects
• Be careful about routing high speed signals, like SERDES diff pairs, on 90 degree
angles so that the traces line up with the fibers in the PCB materials
− This could lead to one signal of the diff pair having a different effective dielectric constant than the other, which
then will create skew between the two signals in the diff pair
• Consider using materials with a tighter, flatter weave so that effects are minimized.
• Route at offset, oblique angle to avoid the weave lining up with a signal in the diff pair

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Connectors
• Connectors may not have as much
impedance control as we would like for
higher speeds
− Cost is primary factor
• Need to consider the PCB pad, pin, via
design that is associated with the
connector
− Beaware of stubs in the connector or at
connector pins/connections
• Pay attention to TDR edge rate values
in SERDES protocol specs
− Slower speed protocols may use a slower edge
rate, which may mask some of the impedance
discontinuity
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IBIS-AMI Examples

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PCB Materials – 10.3125 Gbps

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Insertion Loss vs Material
• Examine how insertion loss of different materials affect signal
• Same length
• Materials – different loss tangent, dissipation factor (Df)
• Loss at 5 GHz:
− Material A (low-cost, high-loss): -15.9 dB
− Material B (less low cost, medium loss): - 12.5 dB
− Material C (medium-high cost, low loss): - 10.3 dB
− Material D (high cost, very low loss): -9.6 dB

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Insertion Loss for Df: 10.3125Gbps (~ -10 to -16 dB)

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10.3125Gbps: No EQ
Material C: -10.3 dB at 5GHz Material D: -9.6 dB at 5GHz

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10.3125Gbps: No EQ
Material C: -10.3 dB at 5GHz Material D: -9.6 dB at 5GHz

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10.3125Gbps: TX EQ -6.0 dB
Material A: -15.9 dB at 5GHz Material B: -12.5 dB at 5GHz

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10.3125Gbps: TX EQ -6.0 dB
Material C: -10.3 dB at 5GHz Material D: -9.6 dB at 5GHz

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10.3125Gbps: TX EQ Best
Material A: -15.9 dB at 5GHz, 38 Material B: -12.5 dB at 5GHz, 2

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10.3125Gbps: TX EQ Best
Material C: -10.3 dB at 5GHz, 2 Material D: -9.6 dB at 5GHz, 2

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Results: 10.3125GbpsTX EQ for DF Change
• TX EQ helps offset material loss
• Best TX EQ setting varies with material
− This is with no RX EQ
• With TX EQ, all pass
− Best result: second highest loss material using the -6.0 dB TX EQ setting.

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PCB Materials – 16 Gbps

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16 Gbps TX EQ for DF Change
• Examine how insertion loss of different materials affect signal
• Same length
• Materials – different loss tangent, dissipation factor (Df)
• Loss at 8 GHz:
− Material A (low-cost, high-loss): -24.6 dB
− Material B (less low cost, medium loss): - 18.8 dB
− Material C (medium-high cost, low loss): - 15.2 dB
− Material D (high cost, very low loss): - 13.9 dB

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Insertion Loss for Df: 16 Gbps (~ -14 to -25 dB vs
~ -10 to -16 dB)

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16 GbpsTX EQ: TX EQ Best
Material A: -24.6 dB at 8GHz, 38 Material B: -18.8 dB at 8GHz, 38

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16 GbpsTX EQ: TX EQ Best
Material C: -15.2 dB at 8GHz, 38 Material D: -13.9 dB at 8GHz, 38

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Results: 16 GbpsTX EQ for DF Change
• TX EQ helps offset material loss at higher frequency
− Now with more loss, 10G Base-KR TX EQ works best for this case

• Best result was lowest loss material with 10G Base-KR TX EQ

− Second highest loss material ~10% worse, and it would be passing.

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PCB Materials – 16 Gbps
Add RX EQ

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16 GbpsTX EQ + RX EQ: TX EQ Best
Material A: -24.6 dB at 8GHz, 57 Material B: -18.8 dB at 8GHz, 4, 57

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16 GbpsTX EQ + RX EQ: TX EQ Best
Material C: -15.2 dB at 8GHz, 0 Material D: -13.9 dB at 8GHz, 0

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Results: 16 GbpsTX EQ + RX EQ for DF Change
• Adding RX EQ makes all cases pass with good margin at 16 Gbps.
• TX EQ value can be optimized to improve eye opening.
• Largest eye opening is for lowest-loss material
− Highest-loss material is 6% worse
▪ Passing with a large margin, too.

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PCB Trace Width – 16 Gbps

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Insertion Loss vs. Trace Width
• Wider trace widths for the differential pair signals reduces insertion
loss
• Similar study here for narrow vs wide trace widths using the NXP
(new) IBIS-AMI model

• Loss at 8 GHz
− Trace Width 4 mils: -16.9 dB
− Trace Width 7 mils: -12.3 dB
− Trace Width 10 mils: -10.0 dB
− Trace Width 15 mils: -8.1 dB

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Insertion Loss for Trace Width, 16 Gbps (~ -8 to -17 dB)

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16 Gbps: TX EQ Best
Trace Width 4: -16.9 dB at 8GHz, 38 Trace Width 7: -12.3 dB at 8GHz, 38

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16 Gbps: TX EQ Best
Trace Width 10: -10.0 dB at 8GHz, 2 Trace Width 15: -8.1 dB at 8GHz, 2

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Results: 16 GbpsTX EQ for Trace Width Change
• TX EQ helps offset loss from narrow traces
• Wider traces producing more open eyes
• TX EQ helps all trace widths pass
−4 mil is 20% smaller eye opening than 15 mil
−7 mil is 6% smaller eye opening than 15 mil
− All pass
− Not including RX EQ, analogous results as higher/lower material study

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Return Loss: Imperfect
Interconnect, Discontinuities

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Insertion Loss, Return Loss
• Prior Channels have been with minimal return loss
• Now see how adding discontinuities to the channel impact insertion loss
− Vias
− Connectors
− Pads
− Impedance discontinuities due to routing (breakout, serpentines)

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How Does Degraded Insertion Loss Look?

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16G, No TX EQ
Smooth Insertion Loss Rough Insertion Loss

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16G, TX EQ -6.0 dB
Smooth Insertion Loss Rough Insertion Loss

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16G, Best TX EQ Settings
Smooth Insertion Loss, 0 Rough Insertion Loss, 0

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Results: Insertion Loss, Return Loss
• Adding more return loss to the channel creates rougher insertion
loss
• Rougher insertion loss impacts the functioning of the TX EQ and
RX EQ
− TX EQ and RX EQ are designed to offset smooth insertion loss
• The advantages from spending extra $$ for better materials can
be offset by issues with return loss

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Return Loss: Via Stub Length

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Examine Impact of Via Stub Length
• Use very short channel (500 mils in length)
− Low insertion loss
− Potentially high return loss due to via stubs
• Alter length of via stubs at each end of the channel
• Alter TX EQ to see if it might help reduce impact of stubs

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No TX EQ
2 mil stub 10 mil stub

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No TX EQ
20 mil stub 30 mil stub

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Best TX EQ Setting
2 mil stub, 0 10 mil stub, 0

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Best TX EQ Setting
20 mil stub, 19 30 mil stub, 19

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Examine Impact of Via Stub Length
• Use very short channel (500 mils in length)
− Low insertion loss
− Potentially high return loss due to via stubs
• Alter length of via stubs at each end of the channel
• Examine how bit period relates to impact of channel/via stub
• Examine how results change for different TX and RX Models
− Traits of TX and RX will affect overall channel

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Long Via Stub (Layer 3 – Layer 18): Alter Speed
8 Gbps 16 Gbps

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Long Via Stub (Layer 3 – Layer 18): alter RX
Higher Speed RX; Higher Speed TX Lower Speed RX ; Higher Speed TX

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Long Via Stub (Layer 3 – Layer 18): alter TX
Higher Speed TX; Lower Speed RX Lower Speed TX; Lower Speed RX

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Results: Examine Impact of Via Stub Length
• Short stub lengths may have minimal impacts
− Depends on channel, TX EQ
• Longer stubs may create channel that will not work
− TX EQ settings may not help to offset
− RX EQ settings may not help to offset
• TX and RX traits have effects on results
− Beyond only the circuit’s ability to offset loss
− Often capacitive loads are decreased for faster TX and RX designs
− Capacitive load can impact overall channel characteristics
• TX EQ may have limits on how it can be set (protocol?)
− Limited TX EQ may create scenario where impact of via stub is exaggerated
• Both TX EQ and RX EQ are most effective with smooth insertion loss channels
− Smooth insertion loss channels require return loss to be optimized
− TX EQ and RX EQ can open closed eye if the channel characteristic is suitable
▪ High return loss channels often will be problematic

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Concluding Notes

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Concluding Notes
• Key items for PCB channel design for >= 8-16 Gbps
− Discontinuities need to be better managed
▪ Connectors are better (PCIe special case)
▪ Short via stubs (back drilling or good layer choice) may be okay
− TX EQ and RX EQ can help lower cost of PCB
▪ May not need more expensive materials or wider trace routes

• PCB materials and trace widths are part of overall look at channel
− Common question is length of channel
− Channel design, insertion loss, return loss all have impacts
− TX EQ and RX EQ are often noted in terms of insertion loss that they can help offset

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Questions?
Thanks for your Time and Attention!

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