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Apply DIT algorithm to compute DFT of the given sequence. 𝑥(𝑛) =

13. BTL3 Applying
{1,0,0,0,0,0,0,0}. (13)
𝑛𝜋
Compute the DFT of the sequence 𝑥(𝑛) = 𝑐𝑜𝑠 where 𝑁 = 4 using BTL1 Remembering
14. 2
DIF FFT algorithm. (13)
PART - C

Formulate the 8-point DFT using FFT

1. BTL6 Creating
1 𝑓𝑜𝑟 0 ≤ 𝑛 ≤ 6
𝑥(𝑛) = (15)
{
0 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒

Evaluate the 8 point for the given sequence using DIT FFT algorithm
2. BTL5 Evaluating
1 𝑓𝑜𝑟 −3≤𝑛 ≤3
𝑥(𝑛) = (15)
{
0 𝑜𝑡ℎ𝑒𝑟𝑤𝑖𝑠𝑒
1,1,1,0,0,0,2,2
3. Estimate the DFT of the sequence 𝑥(𝑛) = { } (15) BTL5 Evaluating
↑
Using linear convolution construct 𝑦(𝑛) = 𝑥(𝑛) ∗ ℎ(𝑛) for the
4. sequence 𝑥(𝑛) = {1,2, −1,2,3, −2, −3, −1,1,1,2, −1} and ℎ(𝑛) = BTL6 Creating
{1,2}. Compare the result by solving the problem using Overlap add
method & Overlap save method. (15)

UNIT II – INFINITE IMPULSE RESPONSE FILTERS

Characteristics of practical frequency selective filters. Characteristics of commonly used analog filters -
Butterworth filters, Chebyshev filters. Design of IIR filters from analog filters (LPF, HPF, BPF, BRF) -
Approximation of derivatives, Impulse invariance method, Bilinear transformation. Frequency
transformation in the analog domain. Structure of IIR filter - Direct form I, Direct form II, Cascade, Parallel
realizations.
PART - A
BT
Q.No Questions Competence
Level
1. List the different types of filters based on frequency response. BTL 1 Remembering

2. Write the properties of Butterworth filter. BTL 1 Remembering

3. Compare IIR and FIR filters. BTL 2 Understanding

4. Why do we go for analog approximation to design a digital filter? BTL 4 Analyzing

5. Mention the requirements for the digital filter to be stable and BTL 1 Remembering
causal.
6. Justify why impulse invariant method is not preferred in the design BTL 5 Evaluating
of IIR filter other than LPF?

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7. Write the properties of Butterworth filter. BTL 1 Remembering

8. Compare Butterworth with Chebyshev filters. BTL 2 Understanding
9. Outline the steps in design of a digital filter from analog filters. BTL 2 Understanding

10. Identify the expression for location of poles of normalized BTL 3 Applying
Butterworth filter.
11. Discuss the need for prewarping. BTL 1 Remembering
1
Convert the given analog transfer function 𝐻(𝑠) = into digital BTL 6 Creating
12. 𝑠+𝑎
by impulse invariant method.
Use the backward difference for the derivative to convert analog BTL 3 Applying
13. 1
LPF with system function (𝑠) = 𝑆+2 .
14. Justify why the Butterworth response is called a maximally flat BTL 4 Analyzing
response.
15. Distinguish between recursive and non-recursive realization. BTL 4 Analyzing

16. Sketch the frequency response of an odd and even order Chebyshev BTL 5 Evaluating
low pass filters.
1
Compute 𝐻(𝑧) for the IIR filter whose 𝐻(𝑠) = with 𝑇 = 0.1𝑠𝑒𝑐 BTL 6 Creating
17. 𝑠+6
using Bilinear transformation.
18. Mention the advantages of cascade realization. BTL 2 Understanding

19. Develop the Direct Form II representation of a Second order IIR BTL 3 Applying
system.
20. What is the advantage of direct form II realization when compared BTL 1 Remembering
to direct form I realization?
PART - B
Given the specification ∝𝑝= 3𝑑𝐵; ∝𝑠= 16𝑑𝐵; 𝑓𝑝 = 1𝐾𝐻𝑧; 𝑓𝑠 =
1 BTL3 Applying
2𝐾𝐻𝑧. Solve for H(s) using Chebyshev approximation. (13)

For the given specifications, design an analog Butterworth filter

2 0.9 ≤ |𝐻(𝑗𝛺)| ≤ 1 𝑓𝑜𝑟 0 ≤ 𝛺 ≤ 0.2𝜋 BTL6 Creating
|𝐻(𝑗𝛺)| ≤ 0.2 𝑓𝑜𝑟 0.4𝜋 ≤ 𝛺 ≤ 𝜋 (13)

Choose an analog Butterworth filter that has a 2𝑑𝐵 pass band

3 attenuation at a frequency of 20 𝑟𝑎𝑑⁄𝑠𝑒𝑐 & at least 10𝑑𝐵 stop band BTL1 Remembering

attenuation at 30 𝑟𝑎𝑑⁄𝑠𝑒𝑐. (13)

Convert the analog filter into a digital filter whose system function
is
4 (𝑠) = 𝑆+0.2 . Use impulse invariance technique. Assume 𝑇 = BTL3 Applying
(𝑆+0.2)2+9
1𝑠𝑒𝑐. (13)

5 Enumerate the steps for IIR filter design by impulse invariance with BTL1 Remembering
example. (13)

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6 Analyze the design of discrete time IIR filter from analog filter. (13) BTL4 Analyzing

An Analog filter has a transfer function

10
𝐻(𝑠) =
7 (𝑆2 + 7𝑆 + 10) BTL2 Understanding

Design a digital filter equivalent to this using impulse invariant

method for 𝑇 = 0.2𝑠𝑒𝑐. (13)
Apply Bilinear transformation to determine (𝑧) for Butterworth
filter satisfying the following specifications.
8 BTL3 Applying
0.8 ≤ |𝐻(𝑒𝑗𝜔)| ≤ 1 0 ≤ 𝜔 ≤ 𝜋/4
|𝐻(𝑒𝑗𝜔)| ≤ 0.2 𝜋/2 ≤ 𝜔 ≤ 𝜋 (13)
Find the system function H(z) of the Chebyshevs low pass digital
filter with the specifications
9 ∝𝑝= 1𝑑𝐵 𝑟𝑖𝑝𝑝𝑙𝑒 𝑖𝑛 𝑡ℎ𝑒 𝑝𝑎𝑠𝑠 𝑏𝑎𝑛𝑑 0 ≤ 𝜔 ≤ 0.2𝜋; BTL1 Remembering
∝𝑠= 15𝑑𝐵 𝑟𝑖𝑝𝑝𝑙𝑒 𝑖𝑛 𝑡ℎ𝑒 𝑠𝑡𝑜𝑝 𝑏𝑎𝑛𝑑 0.3𝜋 ≤ 𝜔 ≤ 𝜋;
using bilinear transformation assume 𝑇 = 1𝑠𝑒𝑐. (13)
Explain the conversion of analog BPF into digital IIR filter using BTL2 Understanding
10 backward difference for the derivative 𝐻𝑎 (𝑠) =
1
(13)
(𝑠+0.2)2+8
Determine the cascade form and parallel form implementation of the
11 system governed by the transfer function BTL5 Evaluating
1+𝑍 −1
𝐻(𝑠) = −1
(13)
1+2𝑍
Simplify the following pole – zero IIR filter into a lattice ladder
12 structure. BTL4 Analyzing
[1+2𝑧−1+2𝑧−2+𝑧−3]
𝐻(𝑧) = [1+(13 𝑧−1+(5)𝑧−2+ 1)𝑧−3] (13)
) (
24 8 3
Analyze a digital Chebyshev filter to satisfy the constraints
0.707 ≤ |𝐻(𝑒𝑗𝜔)| ≤ 1 0 ≤ 𝜔 ≤ 0.2𝜋
13 BTL4 Analyzing
|𝐻(𝑒𝑗𝜔)| ≤ 0.1 0.5𝜋 ≤ 𝜔 ≤ 𝜋

using Bilinear transformation and assuming 𝑇 = 1𝑠𝑒𝑐 . (13)

Obtain the direct form I direct form II and cascade form realization
14 of the following system functions 𝑦(𝑛) = 0.1𝑦(𝑛 − 1) + BTL1 Remembering
0.2(𝑛 − 2) + 3𝑥(𝑛) + 3.6𝑥(𝑛 − 1) + 0.6𝑥(𝑛 − 2). (13)

Part C
Design a third order Butterworth digital filter using impulse invariant BTL 6 Creating
1. technique. Assume the sampling period 𝑇 = 1𝑠𝑒𝑐 (15)

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For the given specifications, design an Chebyshev digital filter using BTL 5 Evaluating
impulse invariance transformation.
2.
0.9 ≤ |𝐻(𝜔)| ≤ 1 𝑓𝑜𝑟 0 ≤ 𝜔 ≤ 0.25𝜋
|𝐻(𝜔)| ≤ 0.24 𝑓𝑜𝑟 0.5𝜋 ≤ 𝜔 ≤ 𝜋 (15)

Propose a digital Butterworth filter with the following BTL 6 Creating

specifications : 0.707 ≤ |𝐻(𝑒𝑗𝜔)| ≤ 1 0 ≤ 𝜔 ≤ 0.5𝜋
3. |𝐻(𝑒𝑗𝜔)| ≤ 0.2 0.75𝜋 ≤ 𝜔 ≤ 𝜋

using bilinear transformation determine system function 𝐻(𝑍)

assuming 𝑇 = 1𝑠𝑒𝑐 . (15)
Evaluate the direct form I, direct form II, cascade and parallel form BTL 5 Evaluating
realization of LTI system governed by the equation: (15)
3 3 1
4. 𝑦(𝑛) = − 𝑦(𝑛 − 1) + 𝑦(𝑛 − 2) + 𝑦(𝑛 − 3) + 𝑥(𝑛) +
8 32 64
3(𝑛 − 1) + 2𝑥(𝑛 − 2).

UNIT III - FINITE IMPULSE RESPONSE FILTERS

Design of FIR filters - symmetric and Anti-symmetric FIR filters - design of linear phase FIR filters using
Fourier series method - FIR filter design using windows (Rectangular, Hamming and Hanning window),
Frequency sampling method. FIR filter structures - linear phase structure, direct form realizations
PART - A
BT
Q.No Questions Competence
Level
Order the different structures of FIR and draw the Direct Form I BTL 4 Analyzing
1.
realization of FIR.
2. Outline the advantages of FIR filters. BTL 2 Understanding
What is the necessary and sufficient condition for the linear phase BTL 1 Remembering
3.
characteristic of an FIR filter?
Develop the frequency response of linear phase LTI system with BTL 3 Applying
4.
constant phase delay and constant group delay.
5. How are the phase distortion and delay distortion introduced? BTL 1 Remembering

6. What do you understand by linear phase response? BTL 2 Understanding

Apply the condition for a digital filter to be causal and stable and BTL 3 Applying
7.
mention the reason why FIR filter is always stable?
Discuss the two concepts that leads to the Fourier series method for BTL 6 Creating
8.
designing FIR filters.

9. Classify the types of impulse response for linear phase FIR filters? BTL 4 Analyzing

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10. Define Gibbs phenomenon. BTL 1 Remembering

Summarize the need for employing window technique for FIR filter BTL 2 Understanding
11.
design?
12. Label the desirable characteristics of FIR filter using windows. BTL 1 Remembering
13. Sketch the frequency response of N-point rectangular windows. BTL 3 Applying
14. Compare Hamming and Hanning window. BTL 5 Evaluating
Analyze the mathematical problem involved in the design of window BTL 4 Analyzing
15.
function?
16. List the desirable characteristics of Kaiser window spectrum. BTL 1 Remembering
17. Elaborate the errors arise due to quantization of numbers. BTL 6 Creating
18. Name the different types of number representation. BTL 1 Remembering
19. What did you infer from limit cycle oscillations? BTL 2 Understanding
20. Explain the noise power spectrum. BTL 5 Evaluating
PART - B
Evaluate the direct form I & II structure of the system function BTL 5 Evaluating
1.
𝐻(𝑧) = 1 + 2𝑧−1 − 3𝑧−2 + 4𝑧−3 + 5𝑧−4 (13)
Realize a direct form and linear phase FIR structures with the
following impulse response. Which is the best realization and why?
2. 1 1 1 BTL 6 Creating
ℎ(𝑛) = 𝛿(𝑛) + 𝛿(𝑛 − 1) − 𝛿(𝑛 − 2) + 𝛿(𝑛 − 3) + 𝛿(𝑛 − 4).
3 4 3
(13)
11
(i) Consider an FIR lattice filter with coefficients 𝑘 = ; 𝑘 = ;
1 2 2 3
1
= . Find the FIR filter coefficients for the direct form structure.
3 4
3. (7) BTL 1 Remembering
(ii) An FIR filter is given by the difference equation 𝑦(𝑛) = 2𝑥(𝑛) +
4 (𝑛 − 1) + 3 𝑥(𝑛 − 2) + 2 𝑥(𝑛 − 3). Draw its lattice form. (6)
5 2 3
Show that an FIR filter has linear phase if the unit sample response
4. satisfies the condition ℎ(𝑛) = ℎ(𝑁 − 1 − 𝑛). Also discuss symmetric BTL 1 Remembering
and antisymmetric case of FIR filter when 𝑁 is even. (13)
Design an ideal low pass filter with a frequency response
𝜋 𝜋
1 𝑓𝑜𝑟 − ≤ 𝜔 ≤
5. 𝐻𝑑(𝑒𝑗𝜔) = { 2 2 BTL 4 Analyzing
𝜋
0 𝑓𝑜𝑟 ≤ |𝜔| ≤ 𝜋
2
Find the values of ℎ(𝑛) for 𝑁 = 11. Find (𝑧). (13)
Using a rectangular window technique, Illustrate a low pass filter
with pass band gain of unity, cut-off frequency of 1000 Hz and BTL 2 Understanding
6.
working at a sampling frequency of 5 KHz. The length of the impulse
response should be 7. (13)
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By Choosing N = 7,design a filter with

𝜋
𝑒−𝑗3𝜔 ; 𝑓𝑜𝑟|𝜔| ≤
7. 𝐻𝑑(𝜔) = { 4 BTL 1 Remembering
𝜋
0 ; ≤ |𝜔| ≤ 𝜋
4
Using Hamming window. (13)
(i) A band reject filter of length 7 is required it is to have lower and
upper cut off frequencies of 3kHz and 5 kHz respectively. The
sampling frequency is 20 kHz. Discover the filter coefficient using BTL 4 Analyzing
8.
hanning window. (11)
(ii) Inspect the frequency domain characteristics for Rectangular and
Hanning Window. (2)
(i) How to design a FIR band stop filter to reject frequencies in the
range 1.2 to 1.8 rad/sec using hamming window, with length 𝑁 = 6.
9. (10) BTL 1 Remembering
(ii) Label the linear phase structure of the above band stop FIR filter.
(3)
10. Develop the procedure of designing FIR filters by windows. (13) BTL 3 Applying
Construct a low pass filter using frequency sampling method with the
11. following specifications; cut off frequency 𝜔𝐶 = 𝜋/4 and N=15 and BTL 3 Applying
plot the magnitude response. (13)
Demonstrate the coefficients of a linear phase FIR filter of length
𝑀 = 15 which has a symmetric unit sample response and a
frequency response that satisfies the conditions.
12. 1 𝑘 = 0,1,2,3,4 BTL 2 Understanding
2𝜋𝑘
𝐻𝑟 ( ) = { 0.4 𝑘=5}
15
0 𝑘 = 6,7
(13)
Examine the design procedure of FIR filter using frequency sampling BTL 4 Analyzing
13.
method. (13)
14. Explain about the limit cycle oscillations in detail. (13) BTL 2 Understanding
PART - C
(i) Realize the linear phase FIR filter with the following impulse
1 1
response ℎ(𝑛) = 𝛿(𝑛) + 𝛿(𝑛 − 1) + 𝛿(𝑛 − 4) − 𝛿(𝑛 − 2) +
2 4
1 (𝑛 − 3). (7)
1. 2 BTL 5 Evaluating
(ii) Explain the steps involved by the general process of designing a
digital filter. (4)
(iii) Justify the advantages of FIR filters. (4)
Prove that an FIR filter has linear phase if the unit sample response
2. satisfies the condition ℎ(𝑛) = ℎ(𝑁 − 1 − 𝑛). Also discuss symmetric BTL 5 Evaluating
and antisymmetric case of FIR filter when N is odd. (15)

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Develop an ideal high pass filter using hanning window with a

frequency response
𝜋
3. 1 𝑓𝑜𝑟 ≤ |𝜔| ≤ 𝜋 BTL 6 Creating
4
𝐻𝑑(𝑒𝑗𝜔) = { 𝜋
0 𝑓𝑜𝑟 |𝜔| ≤
4
Assume 𝑁 = 11. (15)
Design a FIR filter approximating the ideal frequency response
𝜋
𝑒−𝑗𝜔 ; 𝑓𝑜𝑟|𝜔| ≤
4. 𝐻𝑑(𝜔) = { 6 BTL 6 Creating
𝜋
0 ; ≤ |𝜔| ≤ 𝜋
6
(15)

UNIT - IV FINITE WORD LENGTH EFFECTS

Fixed point and floating point number representation - ADC - quantization - truncation and rounding -
quantization noise - input / output quantization - coefficient quantization error - product quantization error -
overflow error - limit cycle oscillations due to product quantization and summation - scaling to prevent
overflow.
PART - A
BT
Q.No Questions Competence
Level
1. Point out the effects of finite word length in digital filters. BTL4 Analyzing
2. List the different types of fixed point arithmetic. BTL1 Remembering
3. Assess the advantages of floating point arithmetic. BTL5 Evaluating
4. Develop the differences between fixed point and floating point BTL3 Applying
number representations.
5. Examine the different quantization methods. BTL4 Analyzing
6. Define truncation. BTL1 Remembering
7. Point out the causes of round off noise error. BTL1 Remembering
8. Outline the quantization error. BTL2 Understanding
9. Why we select rounding over truncation in realizing digital filter. BTL5 Evaluating
10. Differentiate truncation with rounding errors. BTL4 Analyzing
11. Develop the types of quantization errors occur in digital system. BTL6 Creating
12. What do you understand by input quantization error? BTL2 Understanding
13. Construct truncation error for sign magnitude representation and for BTL6 Creating
2‟s complement representation.
14. Write about the over flow oscillations. BTL 1 Remembering

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15. Explain limit cycles. BTL2 Understanding

16. Illustrate zero input limit cycle oscillation. BTL3 Applying
17. State about the dead band of a filter. BTL1 Remembering
18. Compute the method to eliminate overflow limit cycles. BTL3 Applying
19. What do you infer from signal scaling? BTL2 Understanding
20. Discuss about the saturation arithmetic. BTL1 Remembering
PART - B
(i) Explain the characteristics of a limit cycle oscillation with respect
to the system described by the equation 𝑦(𝑛) = 0.95𝑦(𝑛 − 1) +
1. BTL2 Understanding
𝑥(𝑛). Estimate the dead band of the filter. (Assume sign
magnitude is 5 bit). (7)
(ii) Illustrate Zero input limit cycle oscillation. (6)
(i) Describe in detail about finite word length effects in digital
filters. (6)
(ii) Determine the variance of the round of noise power at the output
2. BTL1 Remembering
of cascade realization of the filter is as described by the transfer
function 𝐻(𝑧) = 𝐻1(𝑧) 𝐻2(𝑧).Where
1 1
𝐻 (𝑧) = 𝑎𝑛𝑑 𝐻 (𝑧) = . (7)
1 1−0.5𝑧−1 2 1−0.25𝑧−1
Derive the steady state output noise power and find the steady state
3. variance of the noise in the output due to quantization of input for the BTL6 Creating
first order filter 𝑦(𝑛) = 𝑎 𝑦(𝑛 − 1) + 𝑥(𝑛) (13)
4. Summarize the need for scaling and derive the scaling factor for a BTL2 Understanding
second order IIR filter. (13)
(i) Explain in detail the input quantization error and coefficient
quantization error and its effect on digital filter design, with an
5. example. (6) BTL2 Understanding
(ii) Illustrate quantization noise. Summarize the expression for
quantization noise power at the output ADC. (7)
Analyze the behavior of limit cycle oscillation with respect to the
system described by the following equation𝑦(𝑛) = 0.87 𝑦(𝑛 − 1) +
6. 𝑥(𝑛). Determine the dead band of the system when 𝑥(𝑛) = 0 and BTL4 Analyzing
(−1) = 0.61. Assume that the product is quantized to 4 bits by
rounding. (13)

(i) Compute the equation for steady state input noise power and steady
7. state output noise power (or) quantization noise power. (10) BTL3 Applying
(ii) Solve for the effect of signal scaling on SNR. (3)

8. (i) Deduct the errors during resulting from truncation and rounding.
BTL5 Evaluating

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(10)
(ii)Explain the various formats of the fixed point representation of
binary numbers. (3)
For the second order IIR filter, the system function is,
1
𝐻(𝑍) = BTL1 Remembering
9. (1 − 0.5𝑧 )(1 − 0.45𝑧−1)
−1

Examine the effect of shift in pole location with 3 bit coefficient

representation in direct and cascade forms. (13)
The input to the system (𝑛) = 0.999𝑦(𝑛 − 1) + 𝑥(𝑛) is applied to
10. BTL4 Analyzing
an ADC. Calculate the power produced by the quantization noise at
the output of the filter if the input is quantized to 8 & 16 bits. (13)
11. Describe Limit Cycle oscillation. (13) BTL1 Remembering

(i) Order the following numbers in floating point format with five bits
for mantissa and three bits for exponent.
12. (a) 710 (4) BTL4 Analyzing
(b) 0.2510 (3)
(ii) Compare fixed and floating point representation. (6)
𝑧
An IIR causal filter has the system function 𝐻(𝑧) = .Assume
𝑧−0.97
that the input signal is zero valued and the computed output signal BTL3 Applying
13. values are rounded to one decimal place. Show that under those stated
conditions, the filter output exhibits dead band effect. What is the dead
band range? (13)

14. Describe the quantization process and errors introduced due to BTL1 Remembering
quantization (13)
PART –C
The output of an A/D converter is applied to a digital filter with the
0.5z
system function; H(z) = . Formulate the output noise power BTL6 Creating
1. z−0.5
from the digital filter when the input signal is quantized to have 8
bits. (15)
Develop the output round off noise power for the system having
1
2. transfer function 𝐻(𝑧) = Which is realized in BTL5 Evaluating
(1−0.5𝑧−1)(1+0.4𝑧−1)
cascade form? Assume the word length is 4 bits. (15)
Find effect of coefficient quantization on pole locations of the second
order IIR system realised in Direct Form I and in Cascade. Assume
word length of 4 bits through truncation. The transfer function of the
3. realization is given as follows. BTL5 Evaluating
1
Direct Form I 𝐻(𝑧) =
1−0.9𝑧−1+0.2𝑧−2
1
Cascade form 𝐻(𝑧) = (15)
(1−0.5𝑧−1) (1−0.4𝑧−1)

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Consider the transfer function where 𝐻(𝑧) = 𝐻1(𝑧) 𝐻2(𝑧)

Let 𝐻(𝑧) = 𝐻1(𝑧) 𝐻2(𝑧) i.e.,
1 1
4. H1 (z) = and H2 (z) = BTL6 Creating
1−0.5z−1 1−0.4z−1
Produce the output round off noise power. Assume b = 3. (excluding
Sign Bit) (15)

UNIT V - INTRODUCTION TO DIGITAL SIGNAL PROCESSORS

DSP functionalities - circular buffering – DSP architecture – Fixed and Floating point architecture principles
– Programming – Application examples.
PART - A
BT Competence
Q.No Questions
Level
1. What is the role of the pipeline operation in a DS Processor? BTL 1 Remembering
2. Write a program to add to numbers in DSP Processor. BTL 4 Analyzing
3. Specify the features of a Digital Signal Processor over Microcontroller? BTL 3 Applying
4. Mention the buses used in digital signal processors? BTL 1 Remembering
5. List the features to select digital signal processor. BTL 5 Evaluating
6. Outline the stages in pipelining process BTL 2 Understanding
7. Define circular buffering BTL 1 Remembering
8. Differentiate fixed and floating number systems BTL 4 Analyzing
9. Contrast the difference between Von Neumann architecture &
BTL 2 Understanding
Harvard architecture.
10. Brief about MAC. BTL 1 Remembering
11. Categorize the addressing modes of TMS320C54XX processor. BTL 2 Understanding
12. Give the applications of digital signal processing. BTL 3 Applying
13. How the DS Processor pipeline differs from micro controller. BTL 4 Analyzing
14. Enumerate the advantages and disadvantages of VLIW architecture. BTL 2 Understanding
15. Describe about instruction set and classify. BTL 1 Remembering
16. Show the various addressing modes of TMS32050. BTL 5 Evaluating
17. Examine the arithmetic instructions of C5x processor. BTL 6 Creating
18. Explain any two logical instruction of DS processor. BTL 1 Remembering
19. Examine the major components present in TMS32050. BTL 6 Creating
20. Illustrate the need of accumulator. BTL 3 Applying
PART - B
1. Explain the various types of addressing modes of digital signal
BTL 1 Remembering
processor with suitable example. (13)
2. (i) How will you understand the term “MAC”? Brief note. (8)
BTL 3 Applying
(ii) List the instruction set of DS processor. (5)
3. (i) What are the conditions used to select a DS processor? (5)
BTL 1 Remembering
(ii) Explain in detail about few applications of digital signal
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processor. (8)
(i) Brief note about pipelining, specify its importance. (6)
4. (ii) Mention the advantages & disadvantages of various BTL 2 Understanding
architectures. (7)
5. Draw the various architecture used in digital signal processor.
BTL 4 Analyzing
Explain each in brief. (13)
6. Define addressing mode. With example explain about each
BTL 1 Remembering
addressing mode. (13)
7. With neat sketch explain the architecture of TMS320C54x processor. BTL 2 Understanding
8. Give detailed node about arithmetic instructions. (13) BTL 1 Remembering
9. Evaluate about fixed point architecture. (13) BTL 5 Evaluating
(i) Write the applications of digital signal processing. (5)
10. (ii) Compose a simple program to generate square and saw tooth BTL 3 Applying
wave form. (8)
11. Enumerate the onchip peripherals in „c5x. (13) BTL 4 Analyzing
12. (i) Specify the role of accumulator in DS processor. (5)
BTL 2 Understanding
(ii) Show the functionality of barrel shifter. (8)

13. Elaborate about any two computational blocks of digital signal

BTL 4 Analyzing
processor. (13)
14. Describe the principle of operation of floating point architecture with
BTL 6 Creating
necessary diagram. (13)
PART C
1. Elaborate in detail about the architecture of TMS 320C5416 Digital Signal
BTL 6 Creating
Processor with neat sketches. (15)
2. Discuss in detail, any six instructions used in TMS320C50X
BTL 5 Evaluating
processors. (13)
Evaluate the Following;
i) Block diagram representation for the functional stages of DS
3. Processor. (5) BTL 6 Creating
ii) Addressing Modes of a DS Processor. (5)
iii) Multiplier Accumulator unit of one type of a DS Processor. (5)
With neat figures explain the Architecture for one type of Digital Signal
4. Processor with specifying the special function registers and give one BTL 5 Evaluating
application. (15)

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