PRELIMINARY

KM6161002A, KM6161002AI CMOS SRAM

Document Title
64Kx16 Bit High Speed Static RAM(5V Operating), Revolutionary Pin out.
Operated at Commercial and Industrial Temperature Range.

Revision History
Rev. No. History Draft Data Remark

Rev. 0.0 Initial release with Preliminary. Apr. 22th, 1995 Preliminary

Rev. 1.0 Release to final Data Sheet. Feb. 29th, 1996 Final
1.1. Delete Preliminary

Rev. 2.0 Update D.C parameters. Jul. 16th, 1996 Final

2.1. Update D.C parameters.
Previous spec. Updated spec.
Items
(12/15/17/20ns part) (12/15/17/20ns part)
Icc 220/210/200/190mA 190/185/185/180mA
Isb 30mA 25mA
Isb1 10mA 8mA

Rev. 3.0 Add Industrial Temperature Range parts

Jun. 2nd, 1997 Final
3.1. Add Industrial Temperature Range parts with the same parame-
ters as Commercial Temperature Range parts.
3.1.1. Add KM6161002AI parts for Industrial Temperature
Range.
3.1.2. Add ordering information.
3.1.3. Add the condition for operating at Industrial Temp. Range.
3.2. Add the test condition for Voh1 with Vcc=5V±5% at 25°C
3.3. Add timing diagram to define tWP1 as ″(Timing Wave Form of
Write Cycle(OE=Low fixed)″

Rev. 4.0 Feb. 25th, 1998 Final

4.1. Delete 17ns Part

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the
right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters
of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev 4.0
-1- February 1998

This datasheet has been downloaded from http://www.digchip.com at this page

 PRELIMINARY
KM6161002A, KM6161002AI CMOS SRAM

64K x 16 Bit High-Speed CMOS Static RAM

FEATURES GENERAL DESCRIPTION
• Fast Access Time 12, 15, 20ns(Max.) The KM6161002A is a 1,048,576-bit high-speed Static Random
• Low Power Dissipation Access Memory organized as 65,536 words by 16 bits. The
Standby (TTL) : 25mA(Max.) KM6161002A uses 16 common input and output lines and has
(CMOS) : 8mA(Max.) an output enable pin which operates faster than address access
Operating KM6161002A - 12 : 190mA(Max.) time at read cycle. Also it allows that lower and upper byte
KM6161002A - 15 : 185mA(Max.) access by data byte control(UB, LB). The device is fabricated
KM6161002A - 20 : 180mA(Max.) using SAMSUNG′s advanced CMOS process and designed for
• Single 5.0V ±10% Power Supply high-speed circuit technology. It is particularly well suited for
• TTL Compatible Inputs and Outputs use in high-density high-speed system applications. The
• I/O Compatible with 3.3V Device KM6161002A is packaged in a 400mil 44-pin plastic SOJ or
• Fully Static Operation TSOP2 forward.
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration PIN CONFIGURATION (Top View)
• Data Byte Control : LB:I/O1~I/O8, UB:I/O9~I/O16
• Standard Pin Configuration A0 1 44 A15
KM6161002AJ : 44-SOJ-400 A1 2 43 A14
KM6161002AT : 44-TSOP2-400F A2 3 42 A13
A3 4 41 OE
A4 5 40 UB
CS 6 39 LB
ORDERING INFORMATION
I/O1 7 38 I/O16
KM6161002A -12/15/20 Commercial Temp. I/O2 8 37 I/O15
KM6161002AI -12/15/20 Industrial Temp. I/O3 9 36 I/O14
I/O4 10 SOJ/ 35 I/O13
Vcc 11 34 Vss
Vss 12
TSOP2 33 Vcc
FUNCTIONAL BLOCK DIAGRAM
I/O5 13 32 I/O12
I/O6 14 31 I/O11
Clk Gen. Pre-Charge Circuit I/O7 15 30 I/O10
I/O8 16 29 I/O9
A1 WE 17 28 N.C.
A2
A5 18 27 A12
A3
Row Select

A6 19 26 A11
A4 Memory Array A7 20 25 A10
A5 512 Rows
A6 128x16 Columns A8 21 24 A9
A7 N.C. 22 23 N.C.
A8
A9

Data I/O Circuit & PIN FUNCTION

I/O1 ~I/O8
Cont. Column Select
Pin Name Pin Function
Data
I/O9 ~I/O16 A0 - A15 Address Inputs
Cont.
Gen. WE Write Enable
CLK
CS Chip Select
A0 A10 A11 A12 A13 A14 A15
OE Output Enable
LB Lower-byte Control(I/O1~I/O8)

WE UB Upper-byte Control(I/O9~I/O16)
OE I/O1 ~ I/O16 Data Inputs/Outputs
VCC Power(+5.0V)
UB
LB VSS Ground
CS N.C No Connection

Rev 4.0
-2- February 1998
 PRELIMINARY
KM6161002A, KM6161002AI CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to VSS VIN, VOUT -0.5 to 7.0 V
Voltage on VCC Supply Relative to VSS VCC -0.5 to 7.0 V
Power Dissipation PD 1.0 W
Storage Temperature TSTG -65 to 150 °C
Operating Temperature Commercial TA 0 to 70 °C
Industrial TA -40 to 85 °C
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)

Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.2 - VCC + 0.5** V
Input Low Voltage VIL -0.5* - 0.8 V
NOTE: The above parameters are also guaranteed at industrial temperature range.
* VIL(Min) = -2.0V a.c(Pulse Width≤10ns) for I≤20mA
** VIH(Max) = VCC + 2.0V a.c (Pulse Width≤10ns) for I≤20mA

DC AND OPERATING CHARACTERISTICS(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

Parameter Symbol Test Conditions Min Max Unit
Input Leakage Current ILI VIN = VSS to VCC -2 2 µA
Output Leakage Current ILO CS=VIH or OE=VIH or WE=VIL -2 2 µA
VOUT = VSS to VCC
Operating Current ICC Min. Cycle, 100% Duty 12ns - 190 mA
CS=VIL, VIN = VIH or VIL,
15ns - 185
IOUT=0mA
20ns - 180
Standby Current ISB Min. Cycle, CS=VIH - 25 mA
ISB1 f=0MHz, CS ≥VCC-0.2V, - 8 mA
VIN≥VCC-0.2V or VIN≤0.2V
Output Low Voltage Level VOL IOL=8mA - 0.4 V
Output High Voltage Level VOH IOH=-4mA 2.4 - V
VOH1* IOH1=-0.1mA - 3.95 V
NOTE: The above parameters are also guaranteed at industrial temperature range.
* VCC=5.0V, Temp=25°C

CAPACITANCE*(TA=25°C, f=1.0MHz)
Item Symbol Test Conditions MIN Max Unit
Input/Output Capacitance CI/O VI/O=0V - 8 pF
Input Capacitance CIN VIN=0V - 6 pF
* NOTE : Capacitance is sampled and not 100% tested.

Rev 4.0
-3- February 1998
 PRELIMINARY
KM6161002A, KM6161002AI CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)
TEST CONDITIONS
Parameter Value
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below

NOTE: The above test conditions are also applied at industrial temperature range.

Output Loads(A) Output Loads(B)

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
+5.0V +5.0V

480Ω 480Ω
DOUT DOUT

255Ω 30pF* 255Ω 5pF*

* Including Scope and Jig Capacitance

READ CYCLE
KM6161002A-12 KM6161002A-15 KM6161002A-20
Parameter Symbol Unit
Min Max Min Max Min Max
Read Cycle Time tRC 12 - 15 - 20 - ns
Address Access Time tAA - 12 - 15 - 20 ns
Chip Select to Output tCO - 12 - 15 - 20 ns
Output Enable to Valid Output tOE - 6 - 7 - 9 ns
UB, LB Access Time tBA - 6 - 7 - 9 ns
Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns
Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns
UB, LB Enable to Low-Z Output tBLZ 0 - 0 - 0 - ns
Chip Disable to High-Z Output tHZ 0 6 0 7 0 9 ns
Output Disable to High-Z Output tOHZ 0 6 0 7 0 9 ns
UB, LB Disable to High-Z Output tBHZ 0 6 0 7 0 9 ns
Output Hold from Address Change tOH 3 - 3 - 3 - ns

NOTE: The above parameters are also guaranteed at industrial temperature range.

Rev 4.0
-4- February 1998
 PRELIMINARY
KM6161002A, KM6161002AI CMOS SRAM
WRITE CYCLE
KM6161002A-12 KM6161002A-15 KM6161002A-20
Parameter Symbol Unit
Min Max Min Max Min Max
Write Cycle Time tWC 12 - 15 - 20 - ns
Chip Select to End of Write tCW 8 - 10 - 12 - ns
Address Set-up Time tAS 0 - 0 - 0 - ns
Address Valid to End of Write tAW 8 - 10 - 12 - ns
Write Pulse Width(OE High) tWP 8 - 10 - 12 - ns
Write Pulse Width(OE Low) tWP1 12 - 15 - 20 - ns
UB, LB Valid to End of Write tBW 8 - 10 - 12 - ns
Write Recovery Time tWR 0 - 0 - 0 - ns
Write to Output High-Z tWHZ 0 6 0 7 0 9 ns
Data to Write Time Overlap tDW 6 - 7 - 9 - ns
Data Hold from Write Time tDH 0 - 0 - 0 - ns
End Write to Output Low-Z tOW 3 - 3 - 3 - ns

NOTE: The above parameters are also guaranteed at industrial temperature range.

TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)
tRC
Address
tAA
tOH
Data Out Previous Valid Data Valid Data

Rev 4.0
-5- February 1998
 PRELIMINARY
KM6161002A, KM6161002AI CMOS SRAM

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC
Address

tAA tHZ(3,4,5)
tCO
CS

tBA tBHZ(3,4,5)

UB, LB

tBLZ(4,5) tOHZ
tOE
OE
tOLZ tOH
tLZ(4,5)
Data out High-Z Valid Data

NOTES(READCYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL
levels.
4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=VIL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OE Clock)

tWC
Address

tAW
tWR(5)
OE

tCW(3)

CS

tBW

UB, LB

tAS(4) tWP(2)

WE

tDW tDH

Data in High-Z Valid Data High-Z

tOHZ(6)

Data out

Rev 4.0
-6- February 1998
 PRELIMINARY
KM6161002A, KM6161002AI CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(2) (OE =Low fixed)

tWC
Address

tAW
tWR(5)
tCW(3)
CS

tBW

UB, LB

tAS(4) tWP1(2)

WE
tDW tDH
High-Z
Data in Valid Data
tWHZ(6) tOW (10) (9)

High-Z
Data out

TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)

tWC
Address
tAW
tWR(5)
tCW(3)
CS

tBW

UB, LB

tAS(4) tWP(2)

WE

tDW tDH
High-Z High-Z
Data in Valid Data
tLZ
tWHZ(6)
High-Z High-Z(8)
Data out

Rev 4.0
-7- February 1998
 PRELIMINARY
KM6161002A, KM6161002AI CMOS SRAM

TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LB Controlled)

tWC
Address

tAW
tCW(3) tWR(5)
CS

tBW

UB, LB
tAS(4)
tWP(2)

WE

tDW tDH
High-Z
Data in Valid Data
tBLZ
tWHZ(6)
High-Z High-Z(8)
Data out

NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE
going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write
to the end of write.
3. tCW is measured from the later of CS going low to end of write.
4. AS is measured from the address valid to the beginning of write.
5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
applied.

FUNCTIONAL DESCRIPTION
I/O Pin
CS WE OE LB UB Mode Supply Current
I/O1~I/O8 I/O9~I/O16
H X X* X X Not Select High-Z High-Z ISB, ISB1
L H H X X Output Disable High-Z High-Z ICC
L X X H H
L H L L H Read DOUT High-Z ICC
H L High-Z DOUT
L L DOUT DOUT
L L X L H Write DIN High-Z ICC
H L High-Z DIN
L L DIN DIN
* NOTE : X means Don′t Care.

Rev 4.0
-8- February 1998
 PRELIMINARY
KM6161002A, KM6161002AI CMOS SRAM

PACKAGE DIMENSIONS

44-SOJ-400 Units:millimeters/Inches

#44 #23

9.40 ±0.25

10.16
0.400
11.18 ±0.12
0.370 ±0.010
0.440 ±0.005

0.20 +0.10
-0.05
0.008 +0.004
-0.002

#1 #22
28.98 MAX 0.69 MIN
1.141 0.027
25.58 ±0.12
1.125 ±0.005
1.19
( )
0.047 3.76
1.27
( 0.050 ) 0.148 MAX
0.10 MAX
+0.10 0.004
0.43 -0.05 +0.10
0.017 +0.004 0.71 -0.05
( 0.95 ) -0.002 1.27
0.0375 0.050 0.028 +0.004
-0.002

44-TSOP2-400F Units:millimeters/Inches
0~8°
0.25
( )
0.010

#44 #23
0.45 ~0.75
0.018 ~ 0.030
0.400
10.16

11.76 ±0.20
0.463 ±0.008

( 0.50 )
0 0.020
#1 #22 + 0.1
0.05
18.81 0.15 - .00 4
+0
MAX. 02
0.741 0.006 - 0.0
18.41 ±0.10
0.725 ±0.004
1.00 ±0.10 1.20 0.10 MAX
MAX.
0.039 ±0.004 0.047 0.004
0.05
0.35 ±0.10 0.80 MIN.
( 0.805 ) 0.002
0.032 0.014 ±0.004 0.0315

Rev 4.0
-9- February 1998