5N Rt8129a

RT8129A
High Efficiency Single Synchronous Buck PWM Controller

General Description Features
The RT8129A is a high efficiency single phase  Wide Input Voltage Range : 2.5V to 25V
synchronous buck controller with 5V/12V supply  High Light Load Efficiency
voltage. The RT8129A integrates a Constant-On-Time  Integrated High Driving Capability N-MOSFET
(COT) PWM controller and a MOSFET drivers with Gate
internal bootstrap diodes, which is specifically designed  Drivers and Embedded Switching Boot Diode
to improve converter efficiency at light load condition.  Single IC Supply Voltage : 4.5V to 13.2V
At light load condition, it automatically operates in the  Power-Good Indicator
diode emulation mode to reduce switching frequency  Enable/Disable Control
and improve conversion efficiency.  Internal Soft-Start
Other features include power good indication,

 Programmable Current Limit Threshold
enable/disable control and internal soft-start function.

 Under Voltage Protection
The RT8129A also provide protection functions

 Over Voltage Protection
including Over Voltage Protection (OVP), Under

 Thermal Shutdown
Voltage Protection (UVP), current limit and thermal

Applications
shutdown.
 Motherboard, Memory/Chip-set Power
This device uses lossless low-side MOSFET RDS(ON)  Graphic Card, GPU/Memory Core Power
current sense technique for current limit with adjustable  Low Voltage, High Current DC/DC Regulator
threshold set by connecting a resistor between the
LGATE/OCSET and GND. Marking Information
With above functions, the RT8129A provides 5N= : Product Code
customers a cost-effective solution for high efficiency 5N=YM YMDNN : Date Code
power conversion. The RT8129A is available in the DNN
WDFN-10L 3x3 package.
Simplified Application Circuit

VIN
RT8129A
VCC VCC BOOT
UGATE
PHASE VOUT
VPGOOD PGOOD LGATE/
OCSET
Enable EN
FB
GND
Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
DS8129A-01 October 2015 www.richtek.com
1
RT8129A
Ordering Information Pin Configurations
RT8129A (TOP VIEW)
Package Type
QW : WDFN-10L 3x3 (W-Type) BOOT 1 10 PGOOD
PHASE 2 9 NC
GND
Lead Plating System UGATE 3 8 FB
G : Green (Halogen Free and Pb Free) LGATE/OCSET 4 7 EN
GND 5 11 6 VCC
Note :
Richtek products are : WDFN-10L 3x3
 RoHS compliant and compatible with the current
requirements of IPC/JEDEC J-STD-020.
 Suitable for use in SnPb or Pb-free soldering processes.
Functional Pin Description

Pin No. Pin Name Pin Function
Bootstrap Supply for High Side Gate Driver. Connect this pin to a power
source VCC through a bootstrap diode, and connect a 0.1F or greater
1 BOOT
ceramic capacitor from this pin to the PHASE pin to supply the power for
high side gate driver.
Switch Node. Connect this pin to the switching node of Buck converter.
Connect this pin to the Source of high-side MOSFET together with the Drain
2 PHASE of low-side MOSFET and the inductor. The PHASE voltage is sensed for
zero current detection and over current protection when low side MOSFET
is on.
High Side MOSFET Gate Driver Output. This pin provides the gate drive for
3 UGATE the converter's high-side MOSFET. Connect this pin to the Gate of high-side
MOSFET.
Low Side MOSFET Gate Driver Output. Connect this pin to the Gate of low
side MOSFET. This pin is also used for current limit threshold setting.
4 LGATE/OCSET
Connect a resistor (ROCSET) from this pin to the GND pin to set the current
limit threshold.
5, Ground. The Exposed Pad must be soldered to a large PCB and connected
GND
11 (Exposed Pad) to GND for maximum power dissipation.
Supply Voltage Input. It is recommended to connect a 4.7F ceramic
6 VCC capacitor from this pin to the GND pin. VCC also powers the low side gate
driver.
Enable Control Input. Drive EN higher than 2V to turn on the controller,
7 EN lower than 0.8V to turn it off. If the EN pin is open, it will be pulled to high by
internal circuit.
This pin is used for output voltage feedback input and it is also monitored for
power good indication, over voltage and under voltage protections.
8 FB
Connect this pin to the converter output through voltage divider resistors for
output voltage regulation.
9 NC No Internal Connection.
Power Good Indication Output. This pin provides an open drain output.
Connect this pin to a voltage source through a pull up resistor. The PGOOD
10 PGOOD
voltage goes high to indicate the output voltage is in regulation. This pin can
be left open if the power good indication function is not used.
www.richtek.com DS8129A-01 October 2015
2
RT8129A
Function Block Diagram
Trigger
BOOT
TON Generator
PHASE 1-Shot R
COMP
VREF +
- S Q UGATE
Min TOFF PHASE

Latch 1-Shot VCC
+ OV
S1 Q Trigger
125% VREF -
Latch LGATE/OCSET
FB - UV
S1 Q
75% VREF + GND
PGOOD
PGOOD Thermal ASM
Monitor Shutdown 10µA
±10% VREF
Sample
+
+ gm and Hold
LDO& -
VCC SS REF -
POR
EN
VREF
Operation
The RT8129A integrates a Constant-On-Time (COT) process, PGOOD is actively held low and is allowed to
PWM controller and MOSFET driver so that the be pulled high after soft start process is completed and
external circuit is easily designed and the components no protection occur. In addition, if the FB pin voltage is
are reduced. higher than 110% of VREF or lower than 90% of VREF
The controller provides the PWM signal which relies on during operation, PGOOD will be pulled low
the FB voltage comparing with internal reference immediately.
voltage. The synchronous UGATE driver is turned on at Soft-Start
the beginning of each cycle. After the internal one-shot
An internal current source charges an internal capacitor
timer expires, the UGATE driver will be turned off. The
to build the soft-start ramp voltage.
pulse width of this one-shot is determined by the
The output voltage will track the internal ramp voltage
controller's input voltage and the output voltage to keep
during soft-start interval. The typical soft-start time is
the frequency fairly constant over the input voltage and
2ms.
output voltage range. Another one-shot sets a
minimum off-time. Current Limit
Enable The current limit circuit employs a unique “valley”

current sensing algorithm. If the magnitude of the
The RT8129A remains in shutdown if the EN pin
current sense signal at PHASE is above the current
voltage is lower than 0.8V. When the EN pin voltage
limit threshold, the PWM is not allowed to initiate a new
rises above the2V, the RT8129A will begin a new
cycle. Thus, the current to the load exceeds the
initialization and soft-start cycle.
average output inductor current, the output voltage falls
PGOOD and eventually crosses the under-voltage protection
The power good output is an open-drain architecture, threshold, inducing IC shutdown.
and it requires a pull-up resistor. During soft-start
3
RT8129A
Over Voltage Protection (OVP) Under Voltage Protection (UVP)
The FB voltage can be continuously monitored for over The output voltage can be continuously monitored for
voltage protection. When the FB voltage exceeds under voltage protection. When the FB voltage is less
125% of the reference voltage, UGATE goes low and than 75% of the reference voltage, under voltage
LGATE is forced high. The controller is latched until protection is triggered and then both UGATE and
VCC is re-supplied and exceeds the POR rising LGATE gate drivers are forced low. The controller is
threshold voltage. latched until VCC or EN pin voltage is re-supplied and
There is a 5s delay built into the under voltage exceeds the POR rising threshold voltage.
protection circuit to prevent false transitions. There is a 3s delay built into the under voltage
protection circuit to prevent false transitions.
4
RT8129A
Absolute Maximum Ratings (Note 1)
 VCC to GND ------------------------------------------------------------------------------------------------------------ 0.3V to 15V
 Other Pins --------------------------------------------------------------------------------------------------------------- 0.3V to 6.5V
 BOOT to PHASE
DC--------------------------------------------------------------------------------------------------------------------------0.3V to 15V
<100ns --------------------------------------------------------------------------------------------------------------------0.3V to 20V
 PHASE to GND
DC------------------------------------------------------------------------------------------------------------------------- 5V to 25V
<100ns ------------------------------------------------------------------------------------------------------------------- 10V to 30V
 BOOT to GND
DC------------------------------------------------------------------------------------------------------------------------- 0.3V to 40V
<100ns ------------------------------------------------------------------------------------------------------------------- 0.3V to 45V
 UGATE to GND
DC------------------------------------------------------------------------------------------------------------------------- 0.3V to 40V
<100ns ------------------------------------------------------------------------------------------------------------------- 10V to 45V
 UGATE to PHASE
DC------------------------------------------------------------------------------------------------------------------------- 0.3V to 15V
<40ns --------------------------------------------------------------------------------------------------------------------- 5V to 20V
 LGATE to GND
DC------------------------------------------------------------------------------------------------------------------------- 0.3V to 15V
<100ns ------------------------------------------------------------------------------------------------------------------- 5V to 20V
 Power Dissipation, PD @ TA = 25C
WDFN-10L 3x3 -------------------------------------------------------------------------------------------------------- 3.27W
 Package Thermal Resistance (Note 2)
WDFN-10L 3x3, JA -------------------------------------------------------------------------------------------------- 30.5C/W
WDFN-10L 3x3, JC -------------------------------------------------------------------------------------------------- 7.5C/W
 Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------- 260C
 Junction Temperature ------------------------------------------------------------------------------------------------ 150C
 Storage Temperature Range --------------------------------------------------------------------------------------- 65C to 150C
 ESD Susceptibility (Note 3)
 HBM (Human Body Model) ----------------------------------------------------------------------------------------- 2kV
Recommended Operating Conditions (Note 4)

 Power Input Voltage, VIN ------------------------------------------------------------------------------------------- 2.5V to 25V
 Control Voltage, VCC ------------------------------------------------------------------------------------------------ 4.5V to 13.2V
 Ambient Temperature Range--------------------------------------------------------------------------------------- 40C to 85C
 Junction Temperature Range -------------------------------------------------------------------------------------- 40C to 125C
5
RT8129A
Electrical Characteristics
(TA = 25C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit

PWM Controller
VCC rising -- -- 4.4
VCC POR Threshold V
VCC falling 3.9 -- --
Reference Voltage VREF -- 0.8 -- V
Reference and Error Amplifier
FB Error Comparator
Excluding 1 -- 1 %
Threshold
External Resistive Divider Tolerance
Output Voltage Range 0.8 -- 3.3 V
PWM Frequency FSW (Note 5) 270 300 330 kHz
Minimum On-Time TON(MIN) -- 70 -- ns
Minimum Off-Time TOFF(MIN) -- 300 -- ns
EN Threshold
EN Internal Pull Migh Current VEN = 0V -- 10 40 A
Logic-High VENH 2 -- --
EN Input Voltage V
Logic-Low VENL -- -- 0.8
PGOOD
Over-Voltage Until Measured at FB, with respect to
-- 880 902 mV
PGOOD Goes Low reference, no load
Under-Voltage Until Measured at FB, with respect to
-- 720 -- mV
PGOOD Goes Low reference, no load
Falling edge, FB forced below
Fault Propagation Delay -- 1 -- s
PGOOD trip threshold
Output Low Voltage ISINK = 1mA -- -- 0.4 V
Leakage Current ILEAK High state, forced to 5V -- -- 1 A
Driver
VBOOT − VPHASE = 12V,
UGATE Gate Driver Source RUGATEsr -- 1.5 3 
ISOURCE = 100mA
VBOOT − VPHASE = 12V,
UGATE Gate Driver Sink RUGATEsk -- 2.25 4 
ISINK = 10mA
LGATE Gate Driver Source RLGATEsr VCC = 12V, ISOURCE = 100mA -- 1.5 3 
LGATE Gate Driver Sink RLGATEsk VCC = 12V, ISOURCE = 10mA -- 1 2 
From UG falling to LG rising,
5 20 --
Dead Time PHASE = 1.5V ns
From LG falling to UG rising 5 20 --
Internal Boot Charging
VCC to BOOT, 10mA -- -- 80 
Switch on Resistance
6
RT8129A
Parameter Symbol Test Conditions Min Typ Max Unit
Protection
Current Limit Setting Current IOCSET 9.5 10 10.5 A
Current Limit Threshold Offset -20 -- 20 mV
Over Voltage Protection
VOVP 0.95 1 1.03 V
Threshold
OVP latch delay -- 5 -- s
Under Voltage Protection
VUVP 0.57 0.6 0.63 V
Threshold
Voltage Ramp Soft-Start Time From FB 0% to FB 100% 1.2 2 2.8 ms
Thermal Shutdown Threshold TSD 145 -- 165 C
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect
device reliability.
Note 2. JA is measured at TA = 25C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. JC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. No production tested. Test condition VIN = 7V, VOUT = 1.25V, IOUT = 10A using application circuit.
Typical Application Circuit
VIN
DBOOT
C5 CIN
RT8129A
R1 6 VCC RBOOT CBOOT
VCC BOOT 1
C4 C1 3 Q1
UGATE
RUGATE LOUT
2
PHASE VOUT
RPGOOD RLGATE
VPGOOD 10 LGATE/ 4
PGOOD Q2 R3
OCSET R2 C6 COUT
7 ROCSET C3 RFB1
EN
C2
8
Enable FB
GND
5, C7 RFB2
11 (Exposed Pad)
7
RT8129A
Typical Operating Characteristics
Efficiency vs. Load Current Efficiency vs. Load Current
100 100
90 90
80 80
70 VIN = 5V 70 VIN = 5V
Efficiency (%)
Efficiency (%)
60 VIN = 12V 60 VIN = 12V
50 VIN = 19V 50 VIN = 19V
40 40
30 30
20 20
10 10
VCC = 5V, VOUT = 1.05V, VNN VCC = 5V, VOUT = 1.2V, DDRIV
0 0
0.01 0.1 1 10 0.01 0.1 1 10
Load Current (A) Load Current (A)
Efficiency vs. Load Current Efficiency vs. Load Current

100 100
90 90
80 80
70 VIN = 5V 70 VIN = 5V
Efficiency (%)
Efficiency (%)
60 VIN = 12V 60 VIN = 12V

50 VIN = 19V 50 VIN = 19V
40 40
30 30
20 20
10 10
VCC = 5V, VOUT = 1.35V, DDRIII-L VCC = 5V, VOUT = 1.5V, DDRIII
0 0
0.01 0.1 1 10 0.01 0.1 1 10 100
Frequency vs. Load Current Frequency vs. Load Current

350 350
VCC = 5V, VOUT = 1.05V, VNN VCC = 5V, VOUT = 1.2V, DDRIV
300 300
Frequency (kHz)1
Frequency (kHz)1
250 250
VIN = 5V
200 200
VIN = 12V
VIN = 5V
150 VIN = 19V 150
VIN = 12V
100 100 VIN = 19V
50 50
0 0
0.01 0.1 1 10 0.01 0.1 1 10
8
RT8129A
Frequency vs. Load Current Frequency vs. Load Current
350 350
VCC = 5V, VOUT = 1.35V, DDRIII-L VCC = 5V, VOUT = 1.5V, DDRIII
300 300
Frequency (kHz)1
Frequency (kHz)1
250 250
200 200
150 150
VIN = 5V
100 100
VIN = 5V
VIN = 12V
VIN = 12V
50 VIN = 19V 50
VIN = 19V
0 0
0.01 0.1 1 10 0.01 0.1 1 10
Frequency vs. Load Current Output Voltage vs. Load Current

350 1.060
VIN = 12V, VOUT = 1.2V
VCC = 5V
300
VCC = 12V
Frequency (kHz)1
1.055
Output Voltage (V)
250 VIN = 19V

VIN = 12V
200
VIN = 5V
1.050
150
100
1.045
50 VCC = 5V, VOUT = 1.05V,

R1 = 2.49k, R2 = 7.87k, VNN
0 1.040
0.01 0.1 1 10 0.01 0.1 1 10
Output Voltage vs. Load Current Output Voltage vs. Load Current
1.205 1.365
1.204
1.203 1.363
Output Voltage (V)
Output Voltage (V)
1.202
1.201 1.361
VIN = 19V
1.200 VIN = 19V
VIN = 12V
1.199 VIN = 12V 1.359 VIN = 5V
1.198 VIN = 5V
1.197 1.357
VCC = 5V, VOUT = 1.2V, VCC = 5V, VOUT = 1.35V,
1.196
R1 = 1k, R2 = 2k, DDRIV R1 = 2.49k, R2 = 3.57k, DDRIII-L
1.195 1.355
0.01 0.1 1 10 0.01 0.1 1 10
9
RT8129A
Output Voltage vs. Load Current VREF vs. Temperature
1.530 0.804
0.803
Output Voltage (V)
1.525
0.802
VCC = 12V
VREF (V)
0.801
VIN = 19V
1.520 VCC = 5V
VIN = 12V 0.800
VIN = 5V
0.799
1.515
VCC = 5V, VOUT = 1.5V, 0.798

R1 = 1k, R2 = 1.1k, DDRIII VIN = 12V, No Load
1.510 0.797
0.01 0.1 1 10 -50 -25 0 25 50 75 100 125
Load Current (A) Temperature (°C)
Quiescent Current vs. VCC Shutdown Current vs. VCC

6 Shutdown Current (mA)1 2.5
5
Quiescent Current (mA)
2.0
4
1.5
3
1.0
2
0.5
1
VIN = 12V, VOUT = 1.2V, DDR IV, No Load VIN = 12V, VOUT = 1.2V, DDR IV, No Load
0 0.0
0 2.5 5 7.5 10 12.5 15 0 2.5 5 7.5 10 12.5 15
VCC (V) VCC (V)
Power On from EN Power Off from EN
EN
EN
(5V/Div)
(5V/Div)
VOUT VOUT
(500mV/Div) (500mV/Div)
PHASE PHASE
(10V/Div) (10V/Div)
PGOOD PGOOD
(10V/Div) (10V/Div)
VIN = 12V, VCC = 5V, VOUT = 1.2V, No Load VIN = 12V, VCC = 5V, VOUT = 1.2V, Load = 100mA
Time (1ms/Div) Time (5ms/Div)
10
RT8129A
Power On from VCC Power Off from VCC
VCC
VCC
(5V/Div)
(5V/Div)
VOUT VOUT
PHASE PHASE
(10V/Div) (10V/Div)
PGOOD PGOOD
(10V/Div) (10V/Div)
VIN = 12V, VOUT = 1.2V, No Load VIN = 12V, VOUT = 1.2V, Load = 100mA
Time (1ms/Div) Time (5ms/Div)
Load Transient Response Load Transient Response
ILoad
(10A/Div) ILoad
(10A/Div)
VIN = 12V, VCC = 5V

VOUT
VOUT
(30mV/Div)
VIN = 12V, VCC = 5V (30mV/Div)
PHASE PHASE
(10V/Div) (10V/Div)
LGATE LGATE
(10V/Div) (10V/Div)
VOUT = 1.2V, Load = 0.1 to 10A VOUT = 1.2V, Load = 10 to 0.1A
Time (20µs/Div) Time (20µs/Div)
OVP UVP
PGOOD PGOOD
(10V/Div) (10V/Div)
FB VOUT
PHASE PHASE
(10V/Div) (10V/Div)
LGATE LGATE
(10V/Div) (10V/Div)
VIN = 12V, VCC = 5V, VOUT = 1.2V, No Load VIN = 12V, VCC = 5V, VOUT = 1.2V
Time (50µs/Div) Time (20µs/Div)
11
RT8129A
OCP
VIN = 12V, VCC = 5V,

VOUT = 1.2V,
ROCSET = 13k,
ILoad
(10A/Div)
VOUT
(500mV/Div)
PHASE
(10V/Div)
LGATE
(10V/Div) RDS,ON(VGS=4.5V) = 7.4m
Time (50µs/Div)
12
RT8129A
Application Information
The RT8129A is a single-phase synchronous buck current is also reduced, and eventually comes to the
PWM controller with integrated drivers which is point that its valley touches zero current, which is the
optimized for high performance graphic microprocessor boundary between continuous conduction and
and computer applications. A COT (Constant-On-Time) discontinuous conduction modes. By emulating the
PWM controller and two MOSFET drivers with internal behavior of diodes, the low-side MOSFET allows only
bootstrap diodes are integrated so that the external partial of negative current when the inductor
circuit is easily designed and the component count is freewheeling current reach negative level. As the load
reduced. current is further decreased, it takes longer and longer
The topology solves the poor load transient timing to discharge the output capacitor to the level that
problems of fixed-frequency current-mode PWM and requires the next “ON” cycle. In reverse, when the
avoids the problems caused by widely varying output current increases from light load to heavy load,
switching frequencies in conventional constant-on-time the switching frequency increases to the preset value
and constant off-time PWM schemes. as the inductor current reaches the continuous
condition.
RT8129A also features complete fault protection
functions including OVP, UVP and Current Limit. The switching waveforms may appear noisy and
asynchronous when light loading causes
PWM Operation diode-emulation operation, but this is a normal
The RT8129A integrates a Constant-On-Time PWM operating condition that results in high light-load
controller, and the controller provides the PWM signal efficiency. Trade-offs in DEM noise vs. light-load
which relies on the FB voltage comparing with internal efficiency is made by varying the inductor value.
reference voltage as shown in Figure 1. Referring to Generally, low inductor values produce a broader
the function block diagram of TON generator, the efficiency vs. load curve, while higher values result in
synchronous UGATE driver will be turned on at the higher full-load efficiency (assuming that the coil
beginning of each cycle. After the internal one-shot resistance remains fixed) and less output voltage ripple.
timer expires, the UGATE driver will be turned off. The The disadvantages for using higher inductor values
pulse width of this one shot is determined by the include larger physical size and degrade load-transient
converter's input voltage and the output voltage to keep response (especially at low input-voltage levels).
the frequency fairly constant over the input voltage
Enable and Disable
range. Another one-shot sets a minimum off-time.
The EN pin allows for power sequencing between the
VFB controller bias voltage and another voltage rail. The
VPEAK RT8129A remains in shutdown if the EN pin is lower
than 800mV. When EN pin rises above the 2V, the
VFB
RT8129A will begin a new initialization and soft-start
VVALLEY
cycle.
VREF
t Power-On Reset (POR), UVLO
tON
Power-on reset (POR) occurs when VCC rises above
Figure 1. Constant On-Time PWM Control to approximately 4.4V (typical), the RT8129A will reset
the fault latch and preparing the PWM for operation.
Diode-Emulation Mode
Below 4V (typical), the VCC under voltage-lockout
In diode-emulation mode, the RT8129A automatically (UVLO) circuitry inhibits switching by keeping UGATE
reduces switching frequency at light-load conditions to and LGATE low.
maintain high efficiency. As the output current
decreases from heavy-load condition, the inductor
13
RT8129A
VIN Detection Power-Good Output (PGOOD)
When VCC exceeds its POR rising threshold, LGATE The power good output is an open drain architecture,
will be forced low UGATE and UGATE will output and it requires a pull-up resistor. During soft-start,
continuous pulses (~25kHz, 100ns), for input voltage PGOOD is actively held low and is allowed to transition
VIN detection. If the PHASE pin voltage exceeds 1V for high after soft start is completed. In addition, if the FB
3 consecutive cycles when the UGATE is turned on, pin voltage is higher than 110% of VREF or lower than
VIN is recognized as ready. The controller will initiate 90% of VREF, PGOOD will go low immediately.
soft-start operation.
Current Limit
Soft-Start The RT8129A provides cycle-by-cycle current limit
The RT8129A provides an internal soft-start function. control by detecting the PHASE voltage drop across
The soft-start function is used to prevent large inrush the low-side MOSFET when it is turned on. The current
current and output voltage overshoot while the limit circuit employs a unique “valley” current sensing
converter is being powered-up. The soft-start function algorithm. If the magnitude of the current sense signal
automatically begins after the chip is enabled. at PHASE is above the current limit threshold, the
When soft-start process starts, an internal current PWM is not allowed to initiate a new cycle.
source charges the internal soft-start capacitor such In an over-current condition, the current to the load
that the internal soft-start voltage ramps up uniformly. exceeds the average output inductor current. Thus, the
The FB voltage will track the internal soft-start voltage output voltage falls and eventually crosses the
during the soft-start interval. The PWM pulse width under-voltage protection threshold, inducing IC
increases gradually to limit the input current. After the shutdown.
internal soft-start voltage exceeds the reference
Current Limit Threshold Setting
voltage, the FB voltage no longer tracks the soft-start
voltage but rather follows the reference voltage. Current limit threshold is externally programmed by
Therefore, both the duty cycle of the UGATE and the adding a resistor (ROCSET) between LGATE and GND.
input current are limited during the soft-start interval. If Once VCC exceeds the POR threshold, an internal
the protection is not triggered during soft-start process, current source IOCSET flows through ROCSET. The
the soft-start process is finished until the signal Internal voltage across ROCSET is stored as the over current
SSOK goes high, Figure 2 shows the internal soft-start protection threshold VOCSET. After that, the current
sequence. source is switched off.
VCC POR
Threshold
ROCSET can be determined using the following
VCC
equation :
EN
FB
0.8V
2V
ROCSET 
IVALLEY  RLGDS(ON) 
Internal IOCSET
SS
Internal Where IVALLEY represents the desired inductor limit

SSOK
current (valley inductor current) and IOCSET is current
PGOOD limit setting current.
If ROCSET is not present, there is no current path for
UGATE IOCSET to build the OCP threshold. In this situation, the
OCP threshold is internally preset to 640mV. The
LGATE
POR Soft Start Normal operation Off

recommended range for ROCSET is 5k to 60k which
VIN Detection
Diode Emulation with
OCP
Programming Ultrasonic Mode
LGATE turns on to
discharge output voltage
means the threshold voltage range is 50mV to 600mV.
(Load Current Dependent) if the phase voltage >1V
Figure 2. Soft-Start Sequence
14
RT8129A
Output Over-Voltage Protection (OVP) VOUT
The voltage on the FB pin is monitored for over-voltage

RFB1
protection. When the FB voltage exceeds than 1V FB
(typically 125% x VREF), over voltage protection is RFB2
triggered and low-side MOSFET is forced on. This
activates low-side MOSFET to discharge the output
capacitor. The RT8129A is latched once OVP is Figure 4. Setting VOUT with a Resistive Voltage Divider
triggered and can only be released by VCC power-on
MOSFET Gate Driver
reset. A 5s delay is used in OVP detection circuit to
The RT8129A integrates high current gate drivers for
prevent false trigger.
the MOSFET to obtain high efficiency power
Output Under-Voltage Protection (UVP) conversion in synchronous buck topology. A dead time
The voltage on the FB pin is monitored for under is used to prevent the crossover conduction for high
voltage protection. When the FB voltage is less than side and low side MOSFET. Because both the two gate
0.6V (typically 75% x VREF) during normal operation, signals are off during the dead time, the inductor
under voltage protection is triggered and then UGATE current freewheels through the body diode of the low
and LGATE gate drivers are forced low. The RT8129A side MOSFET. The freewheeling current and the
is latched once UVP is triggered and can only be forward voltage of the body diode contribute to the
released by VCC or EN power-on reset. There is a 3s power loss. The RT8129A employs adaptive dead time
delay built into the UVP circuit to prevent false control scheme to ensure safe operation without
transitions. During soft-start, the UVP blanking time is sacrificing efficiency. Furthermore, elaborate logic
equal to PGOOD blanking time. circuit is implemented to prevent short through
conduction. For high output current applications, two or
Output Voltage Setting
more power MOSFET are usually paralleled to reduce
The output voltage waveform is shown as Figure 3, RDS(ON).
which can be adjusted from 0.8V to 3.3V by setting the The gate driver needs to provide more current to switch
feedback resistors, RFB1 and RFB2 (see Figure 4). on/off these paralleled MOSFET. The gate driver with
Choose RFB2 to be approximately 10k and solve for lower source/sink current capability result in longer
RFB1 using the equation below : rising/ falling time in gate signals, and therefore higher
switching loss. The RT8129A embeds high current gate
 R 
VOUT  VREF   1  FB1  drivers to obtain high efficiency power conversion.
 RFB2 
where the VREF is 0.8V (typical). Inductor Selection

Inductor plays an importance role in step-down
VOUT
converters because the energy from the input power
rail is stored in it and then released to the load. From
VOUT
ΔVOUT the viewpoint of efficiency, the dc resistance (DCR) of
VVALLEY
inductor should be as small as possible to minimize the
copper loss. In addition, because inductor cost most of
t
tON the board space, its size is also important. Low profile
inductors can save board space especially when the
Figure 3. Output Voltage Waveform
height has limitation. However, low DCR and low profile
inductors are usually cost ineffective.
Additionally, larger inductance results in lower ripple
current, which means the lower power loss. However,
the inductor current rising time increases with
15
RT8129A
inductance value. This means the transient response MOSFET Selection
will be slower. Therefore, the inductor design is a The majority of power loss in the step-down power
trade-off between performance, size and cost. conversion is due to the loss in the power MOSFET.
In general, inductance is designed such that the ripple For low-voltage high-current applications, the duty
current ranges between 20% ~ 40% of full load current. cycle of the high-side MOSFET is small. Therefore, the
The inductance can be calculated using the following switching loss of the high-side MOSFET is of concern.
equation. Power MOSFETs with lower total gate charge are
VIN  VOUT V preferred in such kind of application.
LMIN   OUT
FSW  k  IOUT_rated VIN However, the small duty cycle means the low-side
MOSFET is on for most of the switching cycle.
where k is the ratio between inductor ripple current and
Therefore, the conduction loss tends to dominate the
rated output current.
total power loss of the converter. To improve the overall
Input Capacitor Selection efficiency, the MOSFET with low RDS(ON) are preferred
Voltage rating and current rating are the key in the circuit design. In some cases, more than one
parameters in selecting input capacitor. Generally, MOSFET are connected in parallel to further decrease
input capacitor has a voltage rating 1.5 times greater the on-state resistance. However, this depends on the
than the maximum input voltage is a conservatively low-side MOSFET driver capability and the budget.
safe design. Thermal Considerations
The input capacitor is used to supply the input RMS For continuous operation, do not exceed absolute
current, which can be approximately calculated using
maximum junction temperature. The maximum power
the following equation.
dissipation depends on the thermal resistance of the
VOUT  V  IC package, PCB layout, rate of surrounding airflow,
IRMS  IOUT    1  OUT 
VIN  VIN 
and difference between junction and ambient
The next step is to select proper capacitor for RMS temperature. The maximum power dissipation can be
current rating. Use more than one capacitor with low
calculated by the following formula :
equivalent series resistance (ESR) in parallel to form a
PD(MAX) = (TJ(MAX)  TA) / JA
capacitor bank is a good design. Besides, placing
ceramic capacitor close to the drain of the high-side where TJ(MAX) is the maximum junction temperature,
MOSFET is helpful in reducing the input voltage ripple TA is the ambient temperature, and JA is the junction
at heavy load. to ambient thermal resistance.
Output Capacitor Selection For recommended operating condition specifications,
The output filter capacitor must have ESR low enough the maximum junction temperature is 125C. The
to meet output ripple and load transient requirement, junction to ambient thermal resistance, JA, is layout
yet have high enough ESR to satisfy stability dependent. For WDFN-10L 3x3 package, the thermal
requirements. Also, the capacitance must be high
resistance, JA, is 30.5C/W on a standard JEDEC
enough to absorb the inductor energy going from a full
51-7 four-layer thermal test board. The maximum
load to no load condition without triggering the OVP
circuit. Organic semiconductor capacitor(s) or special power dissipation at TA = 25C can be calculated by
polymer capacitor(s) are recommended. the following formula :
PD(MAX) = (125C  25C) / (30.5C/W) = 3.27W for
WDFN-10L 3x3 package
16
RT8129A
The maximum power dissipation depends on the Layout Consideration
operating ambient temperature for fixed TJ(MAX) and
Layout is very important in high frequency switching
thermal resistance, JA. The derating curve in Figure 5
converter design. If designed improperly, the PCB
allows the designer to see the effect of rising ambient
could radiate excessive noise and contribute to the
temperature on the maximum power dissipation.
converter instability. Certain points must be considered
3.5 before starting a layout for RT8129A.
Maximum Power Dissipation (W)1
Four-Layer PCB
3.0
 Connect RC low pass filter as close as possible VCC
pin.
2.5
 Keep current protection setting network as close as
2.0
possible to the IC. Routing of the network should
1.5
avoid coupling to high-voltage switching node.
1.0  Connections from the drivers to the respective gate
0.5 of the high-side or the low-side MOSFET should be
0.0 as short as possible to reduce stray inductance.
0 25 50 75 100 125
 All sensitive analog traces and components such as
Ambient Temperature (°C)
FB, EN, PGOOD, and VCC should be placed away
Figure 5. Derating Curve of Maximum Power from high-voltage switching nodes such as PHASE,
Dissipation LGATE, UGATE, or BOOT nodes to avoid coupling.
Use internal layer(s) as ground plane(s) and shield
the feedback trace from power traces and
components.
 Power sections should connect directly to ground
plane(s) using multiple vias as required for current
handling (including the chip power ground
connections). Power components should be placed
to minimize loops and reduce losses.
17
RT8129A
Outline Dimension
Dimensions In Millimeters Dimensions In Inches

Symbol
Min Max Min Max
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.180 0.300 0.007 0.012
D 2.950 3.050 0.116 0.120
D2 2.300 2.650 0.091 0.104
E 2.950 3.050 0.116 0.120
E2 1.500 1.750 0.059 0.069
e 0.500 0.020
L 0.350 0.450 0.014 0.018
W-Type 10L DFN 3x3 Package
Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume
responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and
reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
18

5N Rt8129a

Uploaded by

Copyright:

Available Formats

5N Rt8129a

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

5N Rt8129a

Uploaded by

Copyright:

Available Formats

RT8129A

High Efficiency Single Synchronous Buck PWM Controller

Other features include power good indication,

enable/disable control and internal soft-start function.

The RT8129A also provide protection functions

including Over Voltage Protection (OVP), Under

Voltage Protection (UVP), current limit and thermal

Simplified Application Circuit

Functional Pin Description

Min TOFF PHASE

Enable The current limit circuit employs a unique “valley”

Recommended Operating Conditions (Note 4)

Parameter Symbol Test Conditions Min Typ Max Unit

Typical Application Circuit

60 VIN = 12V 60 VIN = 12V

50 VIN = 19V 50 VIN = 19V

Efficiency vs. Load Current Efficiency vs. Load Current

60 VIN = 12V 60 VIN = 12V

Frequency vs. Load Current Frequency vs. Load Current

Frequency vs. Load Current Output Voltage vs. Load Current

250 VIN = 19V

50 VCC = 5V, VOUT = 1.05V,

VCC = 5V, VOUT = 1.5V, 0.798

Load Current (A) Temperature (°C)

Quiescent Current vs. VCC Shutdown Current vs. VCC

Power On from EN Power Off from EN

Time (1ms/Div) Time (5ms/Div)

Time (1ms/Div) Time (5ms/Div)

Load Transient Response Load Transient Response

VIN = 12V, VCC = 5V

Time (20µs/Div) Time (20µs/Div)

Time (50µs/Div) Time (20µs/Div)

VIN = 12V, VCC = 5V,

Internal Where IVALLEY represents the desired inductor limit

POR Soft Start Normal operation Off

Figure 2. Soft-Start Sequence

The voltage on the FB pin is monitored for over-voltage

where the VREF is 0.8V (typical). Inductor Selection

Output Capacitor Selection For recommended operating condition specifications,

Dimensions In Millimeters Dimensions In Inches

W-Type 10L DFN 3x3 Package

Richtek Technology Corporation

You might also like

Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.