Chapter Two

BASIC ARCHITECTURE OF THE 8088 AND 8086

MICROPROCESSORS
2.1 ARCHTECTURE OF 8086/8088

To improve the performance by implementing the parallel processing concept the CPU of the 8086 /8088
is divided into two independent sections.

They are
1. Bus Interface Unit (BIU) and
2. Execution Unit.(EI).
The BIU sends out addresses ,fetches instructions ,read data from ports and memory and writes data to
ports and memory.i.e the BIU handles all transfers data and addresses on the buses required by the
execution Unit . Whereas the Execution Unit decodes the instructions and executes the instructions.

The Execution Unit : The Execution Unit consists of a control system , a 16-bit ALU, 16-bit Flag
register and four general purpose registers(AX,BX,CX,DX), pointer registers (SP,BP) and Index
registers(SI,DI) of each 16-bits . The control circuitry controls the internal operations .The decoder in the
execution unit decodes the instructions fetched from the memory into a series of actions. The ALU can
add ,subtract, perform operations like logical AND,OR,XOR, increment, decrement, complement ,and
shifting the binary numbers.

Bus Interface Unit : The BIU consists of a 6-byte long instruction register called Queue. And four stack
segment registers (ES,CS,SS,DS) , one Instruction Pointer(IP) and an adder circuit to calculate the 20bit
physical address of a location. This bus interface unit will perform all the external bus operations. They
are fetching the instructions from the memory, read/write data from/into memory or port and also
supporting the instruction Queue etc. The BIU fetches up to six instruction bytes from the memory and
stores these pre-fetched bytes in a first –in first out register set called Queue. When the execution unit is
ready for the execution of the instruction ,instead of fetching the byte from the memory ,it reads the byte
from the Queue .This will increase the overall speed of microprocessor .Fetching the next instruction
while the current instruction executes is called pipelining or parallel processing.

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 Fig.2.1 Architecture of 8086 Microprocessor

2.2 MEMORY ORGANIZATION

The 8086 processor provides a 20-bit address to access any location of the 1 MB memory space. The
memory is organized as a linear array of 1 million bytes, addressed as 00000(H) to FFFFF(H). The
memory is logically divided into code, data, extra data, and stack segments of up to 64K bytes each.
Physically, the memory is organized as a high bank (D15 - D8) and a low bank (D7 –D0) of 512 K 8-
bitbytes addressed in parallel by the processor's address lines A19 -A1. Byte data with even addresses is
transferred on the D7 – D0 bus lines while odd addressed byte data (A0 HIGH) is transferred on the
D15-D8 bus lines. The processor provides two enable signals, BHE and A0 , to selectively allow reading
from or writing into either an odd byte location, even byte location, or both. The instruction stream is
fetched from memory as words and is addressed internally by the processor to the byte level as necessary.

2.3 Segment Registers

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There are four 16-bit segment registers namely code segment register(CS),Stack segment
register(SS),Data segment register(DS) and Extra segment register(ES).The code segment register is
used for addressing the 64kB memory location in the code segment of the memory ,where the code of
the executable program is stored. Similarly the DS register points to the data segment of the 64kB
memory where the data is stored. The Extra segment register also refers to essentially another data
segment of the memory space. The SS register is useful for addressing stack segment of memory. So, the
CS,DS,SS and ES segment registers respectively contains the segment addresses for the code, data, stack
and extra segments of the memory.

2.4 Instruction Pointer Register

It is a 16-bit register which always points to the next instruction to be executed within the currently
executing code segment. So, this register contains the 16-bit offset address pointing to the next
instruction code within the 64kB of the code segment area. Its content is automatically incremented as
the execution of the next instruction takes place.

2.5 Flag Register

This register is also called status register. It is a 16 bit register which contains six status flags and three
control flags. So, only nine bits of the 16 bit register are defined and the remaining seven bits are
undefined. Normally this status flag bits indicate the status of the ALU after the arithmetic or logical
operations. Each bit of the status register is a flip/flop. The Flag register contains Carry flag, Parity flag,
Auxiliary flag Zero flag, Sign flag ,Trap flag, Interrupt flag, Direction flag and overflow flag as shown in
the diagram. The CF,PF,AF,ZF,SF,OF are the status flags and the TF,IF and CF are the control flags.

Flag Register

CF- Carry Flag: This flag is set, when there is a carry out of MSB in case of addition or a borrow in case
of subtraction.

PF - Parity Flag : This flag is set to 1, if the lower byte of the result contains even number of 1’s else (for
odd number of 1s ) set to zero.

AF - Auxilary Carry Flag: This is set, if there is a carry from the lowest nibble, i.e, bit three during
addition, or borrow for the lowest nibble, i.e, bit three, during subtraction.

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 ZF- Zero Flag: This flag is set, if the result of the computation or comparison performed by the
previous instruction is zero.

SF- Sign Flag : This flag is set, when the result of any computation is negative

TF - Tarp Flag: If this flag is set, the processor enters the single step execution mode.

IF- Interrupt Flag: If this flag is set, the maskable interrupt INTR of 8086 is enabled and if it is
zero ,the interrupt is disabled.It can be set by using the STI instruction and can be cleared by executing
CLI instruction.

DF- Direction Flag: This is used by string manipulation instructions. If this flag bit is ‘0’, the string is
processed beginning from the lowest address to the highest address, i.e., auto incrementing mode.
Otherwise, the string is processed from the highest address towards the lowest address, i.e., auto
incrementing mode.

OF- Over flow Flag: This flag is set, if an overflow occurs, i.e, if the result of a signed operation is
large enough to accommodate in a destination register. The result is of more than 7-bits in size in case of
8-bit signed operation and more than 15-bits in size in case of 16-bit sign operations, then the overflow
will be set.

2.6 The Basic System Components

The basic operational design of a computer system is called its architecture. John Von Neumann, a
pioneer in computer design, is given credit for the architecture of most computers in use today. For
example, the 80x86 family uses the Von Neumann architecture (VNA). A typical Von Neumann
system has three major components: the central processing unit (CPU), memory, and input/output (I/O).
The way a system designer combines these components impacts system performance.

CPU Memory

Interconnect

Input/output Fig 2.2 High-level view a computer system

In VNA machines, like the 80x 86 families, the CPU is where all the action takes place. All
computations occur inside the CPU. Data and CPU instructions reside in memory until
required by the CPU. To the CPU, most I/O devices look like memory because the CPU can store data to
an output device and read data from an input device. The major difference between memory and I/O

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locations is the fact that I/O locations are generally associated with external devices in the
outside world.

2.6.1 The System Bus

The system bus connects the various components of a VNA machine. The 80x86 family has three major
busses: the address bus, the data bus, and the control bus. A bus is a collection of wires on which
electrical signals pass between components in the system. These busses vary from processor to processor.
However, each bus carries comparable information on all processors; e.g., the data bus may have a
different implementation on the 80386 than on the 8088, but both carry data between the processor, I/O,
and memory.

The system bus is the communication medium for data transfers. Such data transfers are called the bus
transactions. Some examples of bus transactions are memory read, memory write, I/O read, I/O write,
and interrupt. Depending on the processor and the type of bus used, there may be other types of
transactions. Every bus transaction involves a master and a slave. The master is the initiator of the
transaction and the slave is the target of the transaction. For example, when the processor wants to read
data from the memory, it initiates a bus transaction, also called a bus cycle, in which the processor is the
bus master and memory is the slave. The processor usually acts as the master of the system bus, while
components like memory are usually slaves.

2.6.2 The Data Bus

The 80x86 processors use the data bus to shuffle data between the various components in a computer
system. The size of this bus varies widely in the 80x 86 families. Indeed, this bus defines the “size” of
the processor. The width of the data bus indicates the size of the data transferred between the processor
and memory or I/O device. On typical 80x86 systems, the data bus contains eight, 16, 32, or 64 lines.
Having an eight bit data bus does not limit the processor to eight bit data types. It simply means that the
processor can only access one byte of data per memory cycle. Therefore, the eight bit bus on an 8088 can
only transmit half the information per unit time (memory cycle) as the 16 bit bus on the 8086. Therefore,
processors with a 16 bit bus are naturally faster than processors with an eight bit bus. Likewise,
processors with a 32 bit bus are faster than those with a 16 or eight bit data bus. The size of the
data bus affects the performance of the system more than the size of any other bus.

2.6.3 The Address Bus

The data bus on an 80x86 family processor transfers information between a particular memory location
or I/O device and the CPU. The only question is, “Which memory location or I/O device?” The address

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bus answers that question. To differentiate memory locations and I/O devices, the system designer
assigns a unique memory address to each memory element and I/O device. When the software
wants to access some particular memory location or I/O device, it places the corresponding
address on the address bus. Circuitry associated with the memory or I/O device recognizes this address
and instructs the memory or I/O device to read the data from or place data on the data bus. In either case,
all other memory locations ignore the request. Only the device whose address matches the value on the
address bus responds. With a single address line, a processor could create exactly two unique addresses:

zero and one. With n address lines, the processor can provide 2 n unique addresses (since there are 2 n
unique values in an n-bit binary number). Therefore, the number of bits on the address bus
will determine the maximum number of addressable memory and I/O locations. The 8088 and 8086,
for example, have 20 bit address busses. Therefore, they can access up to 1,048,576 (or 220)
memory locations.

For example, the 8086 processor has a 20-bit address bus and a 16-bit data bus. The amount of physical
memory that this processor can address is 220 bytes and each data transfer involves 16 bits.

2.6.4 The Control Bus

The control bus is an eclectic collection of signals that control how the processor communicates with
the rest of the system. Consider for a moment the data bus. The CPU sends data to
memory and receives data from memory on the data bus. This prompts the question, “Is it sending
or receiving?” There are two lines on the control bus, read and write, which specify the
direction of data flow. Other signals include system clocks, interrupt lines, status lines, and so on. The
exact make up of the control bus varies among processors in the 80x 86 families. However, some control
lines are common to all processors and are worth a brief mention.

The read and write control lines control the direction of data on the data bus. When both contain a
logic one, the CPU and memory-I/O are not communicating with one another. If the read
line is low (logic zero), the CPU is reading data from memory (that is, the system is transferring data
from memory to the CPU). If the write line is low, the system transfers data from the CPU to memory.

2.7 The Processor

The processor acts as the controller of all actions or services provided by the system. It can be thought of
as executing the following cycle forever:

1. Fetch an instruction from the memory;

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 2. Decode the instruction (i.e., identify the instruction);

3. Execute the instruction (i.e., perform the action specified by the instruction).

2.7.1 The System Clock

The system clock provides a timing signal to synchronize the operations of the system. A clock is a
sequence of 1’s and 0’s, as shown in Figure 2.1. The clock frequency is measured in the number of
cycles per second. This number is referred to as Hertz (Hz). We often use the abbreviations MHz and
GHz to represent 106 and 109 cycles per second, respectively.

The system clock defines the speed at which the system operates. All processor operations take multiple
clock cycles. For example, transfer of data from a memory location to Pentium takes three clock cycles.
Thus, the higher the clock rate, the faster the system can work. The clock period is defined as the length
of time taken by one clock cycle.

One clock cycle

Time
Fig 2.3 the system clock
2.8 Number of Address
One of the characteristics that shape the architecture of a processor is the number of addresses used in
its instructions. Most processors use either two or three addresses. For example, the MIPS processor uses
three addresses whereas the Pentium uses two addresses. However, it is possible to design systems with
one or even zero address.

2.8.1 Three-Address Machines

In three-address machines, instructions carry all three addresses explicitly. Most current processors use
three addresses. Table 2.1 gives some sample instructions of a three-address machine.

Instruction Semantics
add dest,src1,src2 Adds the two values at src1and src2and stores
the result in dest

sub dest,src1,src2 Subtracts the second source operand at src2

from the first at src1and stores the result in dest

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mult dest,src1,src2 Multiplies the two values at src1 and src2
and stores the result in dest

Table 2.1 Sample Three-Address Machine Instructions

Example:- A = B + C * D - E + F + A is converted to the following code: -
mult T,C,D ; T1 = C*D
add T,T1,B ; T2 = B + C*D
sub T,T2,E ; T3 = B + C*D - E
add T,T3,F ; T = B + C*D - E + F
add A,A,T ; A = B + C*D - E + F + A
2.8.2 Two-Address Machines
In two-address machines, one address doubles as a source and destination. Usually, we use dest to
indicate that the address is used for destination. But you should note that this address also supplies one of
the source operands. The Pentium is an example processor that uses two addresses. Table 2.2 gives some
sample instructions of a two-address machine.

Instruction Semantics
Mov dest,src Copies the value at src to dest

add dest,src Adds the two values at src and dest and stores
the result in dest

sub dest,src Subtracts the second source operand at src

from the first at dest & stores the result in dest

mult dest,src Multiplies the two values at src and dest and
stores the result in dest

Table 2.2 Sample Two-Address Machine Instructions

Example: - A = B + C * D - E + F + A is converted to the following code:

mov T,C ;T=C
mult T,D ; T = C*D
add T,B ; T = B + C*D
sub T,E ; T = B + C*D - E
add T,F ; T = B + C*D - E + F
add A,T ; A = B + C*D - E + F + A

2.9 Pointer and Index Registers

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These registers can be used either as 16- or 32-bit registers. The two index registers play a special role in
string processing instructions. In addition, they can be used as general-purpose data registers.
The pointer registers are mainly used to maintain the stack. Even though they can be used
as general-purpose data registers, they are almost exclusively used for maintaining the stack.

2.10 Status Flags

Six flags in the flags register, are used to monitor the outcome of arithmetic, logical, and related
operations. By now you are familiar with the purpose of some of these flags. The six flags are the zero
flag (ZF), carry flag (CF), overflow flag (OF), sign flag (SF), auxiliary flag (AF), and parity flag (PF).
For obvious reasons, these six flags are called the status flags.

2.11 What Is a Stack?

Conceptually, a stack is a last-in–first-out (LIFO) data structure. The operation of a stack is analogous to
the stack of trays you find in cafeterias. The first tray removed from the stack would be the last tray that
had been placed on the stack. There are two operations associated with a stack: insertion and deletion. If
we view the stack as a linear array of elements, stack insertion and deletion operations are restricted to
one end of the array. Thus, the only element that is directly accessible is the element at the top-of-stack
(TOS). In the stack terminology, insert and delete operations are referred to as push and pop operations,
respectively.
There is another related data structure, the queue. A queue can be considered as a linear array with
insertions done at one end of the array and deletions at the other end. Thus, a queue is a first-in–first-out
(FIFO) data structure.
As an example of a stack, let us assume that we are inserting numbers 1000 through 1003 into a stack
in ascending order. The arrow points to the top-of-stack. When the numbers are deleted from the stack,
the numbers will come out in the reverse order of insertion. That is, 1003 is removed first, then 1002,
and so on. After the deletion of the last number, the stack is said to be in the empty state.
2.11.1 Pentium Implementation of the Stack
The memory space reserved in the stack segment is used to implement the stack. The registers SS and
ESP are used to implement the Pentium stack. The top-of-stack, which points to the last item inserted
into the stack, is indicated by SS:ESP, with the SS register pointing to the beginning of the stack segment,
and the ESP register giving the offset value of the last item inserted.

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 Fig 2.4 Deletion of data items from the stack: The arrow points to the top-of-stack.

The key Pentium stack implementation characteristics are as follows:

• Only words (i.e., 16-bit data) or double words (i.e., 32-bit data) are saved on the stack, never a single
byte.

• The stack grows toward lower memory addresses. Since we graphically represent memory with
addresses increasing from the bottom of a page to the top, we say that the stack grows “downward.”

• Top-of-stack (TOS) always points to the last data item placed on the stack. TOS always points to the
lower byte of the last word inserted into the stack.

When the stack is initialized, TOS points to the byte just outside the reserved stack area. It is an error to
read from an empty stack, as this causes stack underflow.

When a word is pushed onto the stack, ESP is first decremented by two, and then the word is stored at
SS:ESP. Since the Pentium uses little-endian byte order, the higher-order byte is stored in the higher
memory address. For instance, when we push 21ABH, the stack expands by two bytes, and ESP is
decremented by two to point to the last data item.

The stack full condition is indicated by the zero offset value (i.e., ESP = 0). If we try to insert a data item
into a full stack, stack overflow occurs. Both stack underflow and overflow are programming errors and
should be handled with care. Retrieving a 32-bit data item from the stack causes the offset value to
increase by four to point to the next data item on the stack.

2.11.2 Stack Operations

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The Pentium instruction set has several instructions to support stack operations. These include the basic
instructions like push and pop that operate on single registers. In addition, separate instructions are
provided to push and pop the flags register as well as the complete register set.

Basic Instructions
The Pentium allows the push and pop operations on word or doubleword data items.

The syntax is

push source
pop destination
The operand of these two instructions can be a 16- or 32-bit general-purpose register, segment register,
or a word or doubleword in memory. In addition, source for the push instruction can be an immediate
operand of size 8, 16, or 32 bits.

2.11.3 Uses of the Stack

The stack is used for three main purposes: as a scratchpad to temporarily store data, for transfer of
program control, and for passing parameters during a procedure call.

2.11.4 Temporary Storage of Data

The stack can be used as a scratchpad to store data on a temporary basis. For example,
consider exchanging the contents of two 32-bit variables that are in the memory: value1
and value2. We cannot use
xchg value1,value2 ; illegal
because both operands of xchg are in the memory. The code
mov EAX,value1
mov EBX,value2
mov value1,EBX
mov value2,EAX
works, but it uses two 32-bit registers. This code requires four memory operations. However,
due to the limited number of general-purpose registers, finding spare registers that can be used
for temporary storage is nearly impossible in almost all programs.

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What if we need to preserve the contents of the EAX and EBX registers? In this case, we need to save
and restore these registers as shown below:
;save EAX and EBX registers on the stack
push EAX
push EBX
;EAX and EBX registers can now be used
mov EAX,value1
mov EBX,value2
mov value1,EBX
mov value2,EAX
;restore EAX and EBX registers from the stack
pop EBX
pop EAX
This code requires eight memory accesses. Because the stack is a LIFO data structure, the sequence of
pop instructions is a mirror image of the push instruction sequence.

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