f133 Datasheet v1.2

F133
The Most Cost-Effective Decoding Platform Processor
Features
 RISC CPU
 Memories
- Embedded with 64 MB DDR2, clock frequency up to 533 MHz
- Three SD/MMC host controller (SMHC) interfaces: SD3.0/SDIO3.0/eMMC5.0
 Video Engine
- H.265/H.264/MPEG-1/MPEG-2/MPEG-4/JPEG/VC1/Xvid/Sorenson Spark decoding, up to 1080p@60fps
- JPEG/MJPEG encoding, up to 1080p@60fps
 Video and Graphics
- Allwinner SmartColor2.0 post processing for an excellent display experience
- Supports de-interlacer (DI) up to 1080p@60fps
- Supports Graphic 2D (G2D) hardware accelerator including rotate, mixer, LBC decompression functions
 Video Output
- RGB interface up to 1920 x 1080@60fps
- Dual link LVDS interface up to 1920 x 1080@60fps
- 4-lane MIPI DSI up to 1920 x 1200@60fps
- CVBS OUT interface, supporting NTSC and PAL format
 Video Input
- 8-bit digital camera interface
- CVBS IN interface, supporting NTSC and PAL format (only for F133-B)
 Analog Audio Codec
- 2 DACs and 3 ADCs
- Analog audio interfaces: HPOUTL/R, MICIN3P/N, LINEINL/R, FMINL/R
 Two I2S/PCM external interfaces (I2S1, I2S2)
 Maximum 8 digital PDM microphones (DMIC)
 OWA TX and OWA RX, compliance with S/PDIF interface
 Security System
- AES, DES, 3DES, RSA, MD5, SHA, HMAC
- Integrated 2 Kbits OTP storage space
 External Peripherals
- USB 2.0 DRD (USB0) and USB 2.0 HOST (USB1)
- 10/100/1000 Mbps Ethernet port with RGMII and RMII interfaces
- Up to 6 UART controllers (UART0, UART1, UART2, UART3, UART4, UART5)
- Up to 2 SPI controllers (SPI0, SPI1)
- Up to 4 TWI controllers (TWI0, TWI1, TWI2, TWI3)
- CIR RX and CIR TX
- 8 independent PWM channels (PWM0 to PWM7)
- 1-ch GPADC
- 4-ch TPADC
- LEDC
- CAN (only for F133-B)
 Package
- eLQFP128, 14 mm x 14 mm x 1.4 mm
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Revision History
Revision Date Description
1.0 May 24, 2021 Initial release version.
1.1 June 11, 2021 Add caution description in section 7.2.
1.2 August 16, 2021 Add CAN for F133-B
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Contents
The Most Cost-Effective Decoding Platform Processor .......................................................................................................i
Revision History.....................................................................................................................................................................i
Contents ............................................................................................................................................................................... ii
Figures ................................................................................................................................................................................. vi
Tables ................................................................................................................................................................................ viii
About This Documentation .................................................................................................................................................1
1 Overview ......................................................................................................................................................................3
1.1 Device Difference .................................................................................................................................................3
2 Features........................................................................................................................................................................4
2.1 CPU Architecture ..................................................................................................................................................4
2.2 Memory Subsystem..............................................................................................................................................4
2.2.1 Boot ROM (BROM) ...............................................................................................................................4
2.2.2 SDRAM .................................................................................................................................................4
2.2.3 SMHC ....................................................................................................................................................4
2.3 Video Engine ........................................................................................................................................................5
2.4 Video and Graphics ..............................................................................................................................................5
2.4.1 Display Engine (DE)...............................................................................................................................5
2.4.2 De-interlacer (DI) ..................................................................................................................................6
2.4.3 Graphic 2D (G2D) .................................................................................................................................6
2.5 Video Output .......................................................................................................................................................6
2.5.1 RGB and LVDS LCD ................................................................................................................................6
2.5.2 MIPI DSI ................................................................................................................................................7
2.5.3 CVBS OUT .............................................................................................................................................7
2.6 Video Input ..........................................................................................................................................................7
2.6.1 Parallel CSI ............................................................................................................................................7
2.6.2 CVBS IN (Only for F133-B) ....................................................................................................................7
2.7 System Peripherals ...............................................................................................................................................8
2.7.1 Timer ....................................................................................................................................................8
2.7.2 High Speed Timer (HSTimer)................................................................................................................8
2.7.3 Platform-Level Interrupt Controller (PLIC) ...........................................................................................8
2.7.4 DMAC ...................................................................................................................................................8
2.7.5 Clock Controller Unit (CCU) ..................................................................................................................9
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2.7.6 Thermal Sensor Controller (THS) ..........................................................................................................9

2.7.7 LDO Power ............................................................................................................................................9
2.7.8 RTC .......................................................................................................................................................9
2.7.9 I/O Memory Management Unit (IOMMU) ........................................................................................ 10
2.8 Audio Subsystem ............................................................................................................................................... 10
2.8.1 Audio Codec ...................................................................................................................................... 10
2.8.2 I2S/PCM............................................................................................................................................. 11
2.8.3 DMIC.................................................................................................................................................. 11
2.8.4 One Wire Audio (OWA) ..................................................................................................................... 11
2.9 Security System ................................................................................................................................................. 12
2.9.1 Crypto Engine (CE)............................................................................................................................. 12
2.9.2 Security ID (SID)................................................................................................................................. 13
2.10 External Peripherals .......................................................................................................................................... 13
2.10.1 USB DRD ............................................................................................................................................ 13
2.10.2 USB HOST .......................................................................................................................................... 14
2.10.3 EMAC ................................................................................................................................................. 14
2.10.4 UART .................................................................................................................................................. 14
2.10.5 SPI and SPI_DBI ................................................................................................................................. 15
2.10.6 Two Wire Interface (TWI) .................................................................................................................. 16
2.10.7 CIR Receiver (CIR_RX) ........................................................................................................................ 16
2.10.8 CIR Transmitter (CIR_TX) ................................................................................................................... 16
2.10.9 PWM.................................................................................................................................................. 16
2.10.10 General Purpose ADC (GPADC) ..........................................................................................................17
2.10.11 Touch Panel ADC (TPADC) ..................................................................................................................17
2.10.12 LEDC .................................................................................................................................................. 18
2.10.13 CAN ................................................................................................................................................... 18
2.11 Package ............................................................................................................................................................. 18
3 Block Diagram ........................................................................................................................................................... 19
4 Pin Description .......................................................................................................................................................... 21
4.1 Pin Quantity ...................................................................................................................................................... 21
4.2 Pin Characteristics ............................................................................................................................................. 21
4.3 GPIO Multiplex Function ................................................................................................................................... 28
4.4 Detailed Signal Description ............................................................................................................................... 31
5 Electrical Characteristics ........................................................................................................................................... 40
5.1 Parameter Conditions ....................................................................................................................................... 40
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5.1.1 Minimum and Maximum Values ....................................................................................................... 40

5.1.2 Typical Values .................................................................................................................................... 40
5.1.3 Temperature Definitions ................................................................................................................... 40
5.2 Absolute Maximum Ratings .............................................................................................................................. 40
5.3 Recommended Operating Conditions ............................................................................................................... 42
5.4 Power Consumption Parameters ...................................................................................................................... 44
5.5 DC Electrical Characteristics .............................................................................................................................. 45
5.6 SDIO Electrical Characteristics........................................................................................................................... 46
5.7 GPADC Electrical Characteristics ........................................................................................................................47
5.8 Audio Codec Electrical Characteristics .............................................................................................................. 48
5.9 External Clock Source Characteristics ............................................................................................................... 49
5.9.1 High-speed Crystal/Ceramic Resonator Characteristics .................................................................... 49
5.9.2 Low-speed Crystal/Ceramic Resonator Characteristics ..................................................................... 50
5.10 Internal Reset Electrical Characteristics .............................................................................................................51
5.11 External Memory Electrical Characteristics .......................................................................................................52
5.11.1 SMHC AC Electrical Characteristics ....................................................................................................52
5.12 External Peripheral Electrical Characteristics .....................................................................................................57
5.12.1 LCD AC Electrical Characteristics ........................................................................................................57
5.12.2 CSI AC Electrical Characteristics ........................................................................................................ 59
5.12.3 EMAC AC Electrical Characteristics.................................................................................................... 60
5.12.4 SPI AC Electrical Characteristics .........................................................................................................62
5.12.5 SPI_DBI AC Electrical Characteristics ................................................................................................. 63
5.12.6 UART AC Electrical Characteristics .................................................................................................... 65
5.12.7 TWI AC Electrical Characteristics ....................................................................................................... 66
5.12.8 I2S/PCM AC Electrical Characteristics ................................................................................................67
5.12.9 DMIC AC Electrical Characteristics .................................................................................................... 69
5.12.10 OWA AC Electrical Characteristics ..................................................................................................... 69
5.12.11 CIR_RX AC Electrical Characteristics ...................................................................................................70
5.13 Power-On and Power-Off Sequence ...................................................................................................................70
5.13.1 Power-On Sequence ...........................................................................................................................70
5.13.2 Power-Off Sequence .......................................................................................................................... 71
6 Package Thermal Characteristics ................................................................................................................................73
7 Pin Assignment...........................................................................................................................................................74
7.1 Pin Map ..............................................................................................................................................................74
7.2 Package Dimension ............................................................................................................................................76
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8 Carrier, Storage and Baking Information ................................................................................................................... 77

8.1 Carrier ............................................................................................................................................................... 77
8.1.1 Matrix Tray Information .................................................................................................................... 77
8.2 Storage ...............................................................................................................................................................78
8.2.1 Moisture Sensitivity Level (MSL) ........................................................................................................78
8.2.2 Bagged Storage Conditions ............................................................................................................... 79
8.2.3 Out-of-bag Duration .......................................................................................................................... 79
8.3 Baking ................................................................................................................................................................ 79
9 Reflow Profile ............................................................................................................................................................ 81
10 FT/QA/QC Test........................................................................................................................................................... 83
10.1 FT Test ............................................................................................................................................................... 83
10.2 QA Test .............................................................................................................................................................. 83
10.3 QC Test .............................................................................................................................................................. 83
11 Part Marking.............................................................................................................................................................. 84
11.1 F133-A ............................................................................................................................................................... 84
11.2 F133-B ............................................................................................................................................................... 84
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Figures
Figure 3-1 F133 System Block Diagram ............................................................................................................................... 19
Figure 3-2 F133 Intelligent Speaker Solution ...................................................................................................................... 20
Figure 5-1 SDIO Voltage Waveform .................................................................................................................................... 46
Figure 5-2 SMHC HS-SDR Mode Output Timing Diagram ................................................................................................... 52
Figure 5-3 SMHC HS-SDR Mode Input Timing Diagram ...................................................................................................... 53
Figure 5-4 SMHC HS-DDR Mode Output Timing Diagram ................................................................................................... 53
Figure 5-5 SMHC HS-DDR Mode Input Timing Diagram...................................................................................................... 54
Figure 5-6 SMHC HS200 Mode Output Timing Diagram ..................................................................................................... 55
Figure 5-7 SMHC HS200 Mode Input Timing Diagram ........................................................................................................ 56
Figure 5-8 HV_IF Interface Vertical Timing ......................................................................................................................... 57
Figure 5-9 HV_IF Interface Horizontal Timing ..................................................................................................................... 58
Figure 5-10 CSI Data Sample Timing ................................................................................................................................... 59
Figure 5-11 RGMII Interface Transmit Timing ..................................................................................................................... 60
Figure 5-12 RGMII Interface Receive Timing....................................................................................................................... 60
Figure 5-13 RMII Interface Transmit Timing ....................................................................................................................... 61
Figure 5-14 RMII Interface Receive Timing ......................................................................................................................... 61
Figure 5-15 SPI Writing Timing............................................................................................................................................ 62
Figure 5-16 SPI Reading Timing........................................................................................................................................... 62
Figure 5-17 DBI 3-line Serial Interface Timing..................................................................................................................... 63
Figure 5-18 DBI 4-line Serial Interface Timing..................................................................................................................... 64
Figure 5-19 UART RX Timing ............................................................................................................................................... 65
Figure 5-20 UART nCTS Timing............................................................................................................................................ 65
Figure 5-21 UART nRTS Timing............................................................................................................................................ 66
Figure 5-22 TWI Timing ....................................................................................................................................................... 66
Figure 5-23 I2S/PCM Timing in Master Mode ..................................................................................................................... 67
Figure 5-24 I2S/PCM Timing in Slave Mode ........................................................................................................................ 68
Figure 5-25 DMIC Timing .................................................................................................................................................... 69
Figure 5-26 OWA Timing ..................................................................................................................................................... 69
Figure 5-27 CIR_RX Timing .................................................................................................................................................. 70
Figure 5-28 Power-On Timing ............................................................................................................................................. 71
Figure 5-29 Power-Off Timing ............................................................................................................................................. 72
Figure 7-1 F133 Pin Map ..................................................................................................................................................... 74
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Figure 7-2 F133 Package Dimension ................................................................................................................................... 76

Figure 8-1 F133 Tray Dimension Drawing ........................................................................................................................... 78
Figure 9-1 Lead-free Reflow Profile .................................................................................................................................... 81
Figure 9-2 Measuring the Reflow Soldering Process .......................................................................................................... 82
Figure 11-1 F133-A Marking................................................................................................................................................ 84
Figure 11-2 F133-B Marking ................................................................................................................................................ 84
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Tables
Table 1-1 Device Feature Differences ................................................................................................................................... 3
Table 4-1 F133 Pin Quantity................................................................................................................................................ 21
Table 4-2 Pin Characteristics ............................................................................................................................................... 22
Table 4-3 GPIO Multiplex Function ..................................................................................................................................... 28
Table 4-4 Detailed Signal Description ................................................................................................................................. 31
Table 5-1 Absolute Maximum Ratings ................................................................................................................................ 40
Table 5-2 Recommended Operating Conditions ................................................................................................................. 42
Table 5-3 Power Consumption Parameters ........................................................................................................................ 44
Table 5-4 DC Electrical Characteristics ................................................................................................................................ 45
Table 5-5 3.3 V SDIO Electrical Parameters ........................................................................................................................ 46
Table 5-6 1.8 V SDIO Electrical Parameters ........................................................................................................................ 47
Table 5-7 GPADC Electrical Characteristics ......................................................................................................................... 47
Table 5-8 Audio Codec Typical Performance Parameters................................................................................................... 48
Table 5-9 High-speed 24 MHz Crystal Circuit Characteristics ............................................................................................. 49
Table 5-10 Crystal Circuit Parameters................................................................................................................................. 50
Table 5-11 Low-speed 32.768 kHz Crystal Circuit Characteristics ...................................................................................... 51
Table 5-12 Internal Reset Electrical Characteristics ............................................................................................................ 51
Table 5-13 SMHC HS-SDR Mode Output Timing Constants ................................................................................................ 52
Table 5-14 SMHC HS-SDR Mode Input Timing Constants ................................................................................................... 53
Table 5-15 SMHC HS-DDR Mode Output Timing Constants ............................................................................................... 54
Table 5-16 SMHC HS-DDR Mode Input Timing Constants .................................................................................................. 54
Table 5-17 SMHC HS200 Mode Output Timing Constants .................................................................................................. 55
Table 5-18 SMHC HS200 Mode Input Timing Constants ..................................................................................................... 56
Table 5-19 LCD HV_IF Interface Timing Constants.............................................................................................................. 58
Table 5-20 CSI Interface Timing Constants ......................................................................................................................... 59
Table 5-21 RGMII Transmit Timing Constants .................................................................................................................... 60
Table 5-22 RGMII Receive Timing Constants ...................................................................................................................... 60
Table 5-23 RMII Transmit Timing Constants ....................................................................................................................... 61
Table 5-24 RMII Receive Timing Constants ......................................................................................................................... 61
Table 5-25 SPI Timing Constants ......................................................................................................................................... 62
Table 5-26 DBI 3-line Serial Interface Timing Parameters .................................................................................................. 63
Table 5-27 DBI 4-line Serial Interface Timing Parameters .................................................................................................. 64
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Table 5-28 UART Timing Constants ..................................................................................................................................... 66

Table 5-29 TWI Timing Parameters..................................................................................................................................... 67
Table 5-30 I2S/PCM Timing Constants in Master Mode ..................................................................................................... 67
Table 5-31 I2S/PCM Timing Constants in Slave Mode ........................................................................................................ 68
Table 5-32 DMIC Timing Constants ..................................................................................................................................... 69
Table 5-33 OWA Timing Constants ..................................................................................................................................... 69
Table 5-34 CIR_RX Timing Constants .................................................................................................................................. 70
Table 6-1 F133 Package Thermal Characteristics................................................................................................................ 73
Table 7-1 Pin Map Difference between F133-A and F133-B ............................................................................................... 74
Table 8-1 Matrix Tray Carrier Information .......................................................................................................................... 77
Table 8-2 F133 Packing Quantity Information .................................................................................................................... 77
Table 8-3 MSL Summary ..................................................................................................................................................... 78
Table 8-4 Bagged Storage Conditions ................................................................................................................................. 79
Table 8-5 Out-of-bag Duration ............................................................................................................................................ 79
Table 9-1 Lead-free Reflow Profile Conditions ................................................................................................................... 81
Table 11-1 F133-A Marking Definitions .............................................................................................................................. 84
Table 11-2 F133-B Marking Definitions............................................................................................................................... 85
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About This Documentation
Purpose
The documentation describes features of each module, pin/signal characteristics, current consumption,
interface timing, thermal and package, and part reliability of the F133 processor. For details about register
descriptions of each module, see the F133_User_Manual.
Intended Audience
The document is intended for:
 Hardware designers and maintenance personnel for electronics
 Sales personnel for electronic parts and components
Conventions
Symbol Conventions
The symbols that may be found in this document are defined as follows.
Symbol Description
WARNING Indicates potential risk of injury or death exists if the instructions are not obeyed.
CAUTION Indicates potential risk of equipment damage, data loss, performance

degradation, or unexpected results exists if the instructions are not obeyed.
NOTE Provides additional information to emphasize or supplement important points of

the main text.
Table Content Conventions

The table content conventions that may be found in this document are defined as follows.
Symbol Description
- The cell is blank.
Numerical Conventions
The expressions of data capacity, frequency, and data rate are described as follows.
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Type Symbol Value
1K 1024
Data capacity 1M 1,048,576
1G 1,073,741,824
1k 1000
Frequency, data rate 1M 1,000,000
1G 1,000,000,000

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1 Overview
F133 is an advanced application processor designed for the video decoding platform. It integrates a 64-bit
processor with RISC CPU instruction architecture to provide the most efficient computing power. F133
supports full format decoding such as H.265, H.264, MPEG-1/2/4, JPEG, VC1, and so on. The independent
hardware encoder can encode in JPEG or MJPEG. Integrated multi ADCs/DACs and I2S/PCM/DMIC/OWA
audio interfaces can work seamlessly with the CPU to accelerate multimedia algorithms and provide the
perfect voice interaction solution. F133 supports rich display output interfaces to meet the requirements of
the screen display in differentiated markets. F133 can be used in network video machines, advertising
machines, digital photo frames, car MP5, and so on.
1.1 Device Difference

The F133 is configured with different sets of features in different devices. Table 1-1 shows the feature
differences across different devices.
Table 1-1 Device Feature Differences
Contents F133-A F133-B
CVBS IN No support Support
CAN No support Support

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2 Features
2.1 CPU Architecture
• RISC CPU
• 32 KB I-cache and 32 KB D-cache
2.2 Memory Subsystem

2.2.1 Boot ROM (BROM)
• On-chip memory
• Supports system boot from the following devices:
- SD card
- eMMC
- SPI NOR Flash
- SPI NAND Flash
• Supports mandatory upgrade process through USB and SD card
• Supports GPIO pin and eFuse module to select the boot media type
2.2.2 SDRAM
• Embedded with 64 MB DDR2
• Supports clock frequency up to 533 MHz for DDR2
2.2.3 SMHC
• Three SD/MMC host controller (SMHC) interfaces
• The SMHC0 controls the devices that comply with the protocol Secure Digital Memory (SD mem-version
3.0)
• The SMHC1 controls the device that complies with the protocol Secure Digital I/O (SDIO-version 3.0)
• The SMHC2 controls the device that complies with the protocol Multimedia Card (eMMC-version 5.0)
• Maximum performance:
- SDR mode 150 MHz@1.8 V IO pad
- DDR mode 50 MHz@1.8 V IO pad
- DDR mode 50 MHz@3.3 V IO pad
• Supports 1-bit or 4-bit data width
• Supports block size of 1 to 65535 bytes

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• Internal 1024-Bytes RX FIFO and 1024-Bytes TX FIFO

• Supports card insertion and removal interrupt
• Supports hardware CRC generation and error detection
• Supports descriptor-based internal DMA controller
2.3 Video Engine

• Video decoding
- H.265 MP@L4.1 up to 1080p@60fps
- H.264 BP/MP/HP@L4.2 up to 1080p@60fps
- H.263 BP up to 1080p@60fps
- MPEG-4 SP/ASP L5 up to 1080p@60fps
- MPEG-2 MP/HL up to 1080p@60fps
- MPEG-1 MP/HL up to 1080p@60fps
- Xvid up to 1080p@60fps
- Sorenson Spark up to 1080p@60fps
- WMV9/VC-1 SP/MP/AP up to 1080p@60fps
- MJPEG up to 1080p@30fps
• Video encoding
- JPEG/MJPEG up to 1080p@60fps
- Supports input picture scaler up/down
2.4 Video and Graphics

2.4.1 Display Engine (DE)
• Output size up to 2048 x 2048
• Supports two alpha blending channels for main display and one channel for aux display
• Supports four overlay layers in each channel, and has an independent scaler
• Supports potter-duff compatible blending operation
• Supports LBC buffer decoder
• Supports dither output to TCON
• Supports input format Semi-planar YUV422/YUV420/YUV411 and Planar YUV422/YUV420/YUV411,
ARGB8888/XRGB8888/RGB888/ARGB4444/ARGB1555/RGB565/palette
• Supports SmartColor2.0 for excellent display experience
- Adaptive detail/edge enhancement
- Adaptive color enhancement

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- Adaptive contrast enhancement and fresh tone rectify

• Supports write back for aux display
2.4.2 De-interlacer (DI)

• Supports YUV420 (Planar/NV12/NV21) and YUV422 (Planar/NV16/NV61) data format
• Supports video resolution from 32x32 to 2048x1280 pixel
• Supports Inter-field interpolation/motion adaptive de-interlace method
• Performance: module clock 600M for 1080p@60Hz YUV420
2.4.3 Graphic 2D (G2D)

• Supports layer size up to 2048 x 2048 pixels
• Supports pre-multiply alpha image data
• Supports color key
• Supports two pipes Porter-Duff alpha blending
• Supports multiple video formats 4:2:0, 4:2:2, 4:1:1 and multiple pixel formats (8/16/24/32 bits graphics
layer)
• Supports memory scan order option
• Supports any format convert function
• Supports 1/16× to 32× resize ratio
• Supports 32-phase 8-tap horizontal anti-alias filter and 32-phase 4-tap vertical anti-alias filter
• Supports window clip
• Supports FillRectangle, BitBlit, StretchBlit and MaskBlit
• Supports horizontal and vertical flip, clockwise 0/90/180/270 degree rotate for normal buffer
• Supports horizontal flip, clockwise 0/90/270 degree rotate for LBC buffer
2.5 Video Output

2.5.1 RGB and LVDS LCD
• Supports RGB interface with DE/SYNC mode, up to 1920 x 1080@60fps
• Supports serial RGB/dummy RGB interface, up to 800 x 480@60fps
• Supports LVDS interface with dual link, up to 1920 x 1080@60fps
• Supports LVDS interface with single link, up to 1366 x 768@60fps
• Supports i8080 interface, up to 800 x 480@60fps
• Supports BT656 interface for NTSC and PAL

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• RGB666 and RGB565 with dither function

• Gamma correction with R/G/B channel independence
2.5.2 MIPI DSI

• Compliance with MIPI DSI v1.01
• Supports 4-lane MIPI DSI, up to 1280 x 720@60fps and 1920 x 1200@60fps
• Supports non-burst mode with sync pulse/sync event and burst mode
• Supports pixel format: RGB888, RGB666, RGB666 loosely packed and RGB565
• Supports continuous and non-continuous lane clock modes
• Supports bidirectional communication of all generic commands in LP through data lane 0
• Supports low power data transmission
• Supports ULPS and escape modes
2.5.3 CVBS OUT

• 1-channel CVBS output
• Supports NTSC and PAL format
• Plug status auto detecting
• 10 bits DAC output
2.6 Video Input

2.6.1 Parallel CSI
• Supports 8-bit digital camera interface (RAW8/YUV422/YUV420)
• Supports BT656, BT601 interface (YUV422)
• Supports ITU-R BT.656 time-multiplexed format up to 2*1080p@30fps in DDR sample mode
• Maximum pixel clock of 148.5 MHz
• Supports de-interlacing for interlace video input
• Supports conversion from YUV422 to YUV420, YUV422 to YUV400, YUV420 to YUV400
• Supports horizontal and vertical flip
2.6.2 CVBS IN (Only for F133-B)

• 2-channel CVBS input and 1-channel CVBS decoder
• Supports NTSC and PAL format
• Supports YUV422/YUV420 format
• With 1 channel 3D comb filter

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• Detection for signal locked and 625 lines

• Programmable brightness, contrast, and saturation
• 10-bit video ADCs
2.7 System Peripherals

2.7.1 Timer
• The timer module implements the timing and counting functions, which includes timer0, timer1,
watchdog, and audio video synchronization (AVS)
• The timer0/timer1 is a 32-bit down counter. The timer0 and timer1 are completely consistent
• The watchdog is used to transmit a reset signal to reset the entire system when an exception occurs in
the system
• The AVS is used to synchronize the audio and video. The AVS sub-block includes AVS0 and AVS1, which
are completely consistent
2.7.2 High Speed Timer (HSTimer)

• The HSTimer module consists of HSTimer0 and HSTimer1. HSTimer0 and HSTimer1 are down counters
that implement timing and counting functions. They are completely consistent.
• Configurable 56-bit down timer
• Supports 5 prescale factors
• The clock source is synchronized with AHB0 clock, much more accurate than other timers
• Supports 2 working modes: periodic mode and single counting mode
• Generates an interrupt when the count is decreased to 0
2.7.3 Platform-Level Interrupt Controller (PLIC)

• Sampling, priority arbitration and distribution for external interrupt sources
• The interrupt can be configured as machine mode and super user mode
• Up to 256 interrupt source sampling, supporting level interrupt and pulse interrupt
• 32 levels of interrupt priority
• Maintains independently the interrupt enable for each interrupt mode (machine/super user)
• Maintains independently the interrupt threshold for each interrupt mode (machine/super user)
• Configurable access permission for PLIC registers
2.7.4 DMAC
• Up to 16-ch DMA
• Provides 32 peripheral DMA requests for data reading and 32 peripheral DMA requests for data writing

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• Flexible data width of 8/16/32/64-bit

• Programmable DMA burst length
• Supports linear and IO address modes
• Supports data transfer types with memory-to-memory, memory-to-peripheral, peripheral-to-memory,
peripheral-to-peripheral
• Supports transferring data with a linked list
• DRQ response includes waiting mode and handshake mode
• DMA channel supports pause function
• Memory devices support non-aligned transform
2.7.5 Clock Controller Unit (CCU)

• 8 PLLs
• One on-chip RC oscillator
• Supports one external 24 MHz DCXO and one external 32.768 kHz oscillator
• Supports clock configuration and clock generation for corresponding modules
• Supports software-controlled clock gating and software-controlled reset for corresponding modules
2.7.6 Thermal Sensor Controller (THS)

• One thermal sensor located in CPU
• Temperature accuracy: ±3°C from 0°C to +100°C, ±5°C from -25°C to +125°C
• Averaging filter for thermal sensor reading
• Supports over-temperature protection interrupt and over-temperature alarm interrupt
2.7.7 LDO Power

• Integrated 2 LDOs (LDOA, LDOB)
• LDOA: 1.8 V power output, LDOB: 1.35 V/1.5 V/1.8 V power output
• LDOA for IO and analog module, LDOB for SDRAM
• Input voltage is 2.4 V to 3.6 V
2.7.8 RTC
• Implements time counter and timing wakeup
• Provides a 16-bit counter for counting day, 5-bit counter for counting hour, 6-bit counter for counting
minute, 6-bit counter for counting second
• External connect a 32.768 kHz low-frequency oscillator for count clock

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• Timer frequency is 1 kHz

• Configurable initial value by software anytime
• Supports timing alarm, and generates interrupt and wakeup the external devices
• 8 general purpose registers for storing power-off information
2.7.9 I/O Memory Management Unit (IOMMU)

• Supports virtual address to physical address mapping by hardware implementation
• Supports VE, CSI, DE, G2D, DI parallel address mapping
• Supports VE, CSI, DE, G2D, DI bypass function independently
• Supports VE, CSI, DE, G2D, DI pre-fetch independently
• Supports VE, CSI, DE, G2D, DI interrupt handing mechanism independently
• Supports 2 levels TLB (level1 TLB for special using, and level2 TLB for sharing)
• Supports TLB Fully cleared and Partially disabled
• Supports trigger PTW behavior when TLB miss
• Supports checking the permission
2.8 Audio Subsystem

2.8.1 Audio Codec
• Two audio digital-to-analog converter (DAC) channels
- Supports 16-bit and 20-bit sample resolution
- 8 kHz to 192 kHz DAC sample rate
- 100 ± 2 dB SNR@A-weight, -85 ± 3 dB THD+N
• One audio output:
- One stereo headphone output: HPOUTL/R
• Three audio analog-to-digital converter (ADC) channels
- Supports 16-bit and 20-bit sample resolution
- 8 kHz to 48 kHz ADC sample rate
- 95 ± 3dB SNR@A-weight, -80 ± 3dB THD+N
• Three audio inputs:
- One differential microphone input: MICIN3P/3N, or one single-end microphone input: MICIN3P
- One stereo LINEIN input: LINEINL/R
- One stereo FMIN input: FMINL/R
• Supports Dynamic Range Controller adjusting the DAC playback and ADC recording
• One 128x20-bits FIFO for DAC data transmit, one 128x20-bits FIFO for ADC data receive

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• Programmable FIFO thresholds

• Supports interrupts and DMA
• Internal HPLDO output for HPVCC
• Internal ALDO output for AVCC
2.8.2 I2S/PCM
• Two I2S/PCM external interfaces (I2S1, I2S2) for connecting external power amplifier and MIC ADC
• Compliant with standard Philips Inter-IC sound (I2S) bus specification
- Left-justified, Right-justified, PCM mode, and Time Division Multiplexing (TDM) format
- Programmable PCM frame width: 1 BCLK width (short frame) and 2 BCLKs width (long frame)
• Transmit and Receive data FIFOs
- Programmable FIFO thresholds
- 128 depth x 32-bit width TXFIFO and 64 depth x 32-bit width RXFIFO
• Supports multiple function clock
- Clock up to 24.576 MHz Data Output of I2S/PCM in Master mode (Only if the IO PAD and Peripheral
I2S/PCM satisfy Timing Parameters)
- Clock up to 12.288 MHz Data Input of I2S/PCM in Master mode
• Supports TX/RX DMA slave interface
• Supports multiple application scenarios
- Up to 16 channels (fs = 48 kHz) which has adjustable width from 8-bit to 32-bit
- Sample rate from 8 kHz to 384 kHz (CHAN = 2)
- 8-bit u-law and 8-bit A-law companded sample
• Supports master/slave mode
2.8.3 DMIC
• Supports maximum 8 digital PDM microphones
• Supports sample rate from 8 kHz to 48 kHz
2.8.4 One Wire Audio (OWA)

• One OWA TX and one OWA RX
• Compliance with S/PDIF interface
• IEC-60958 and IEC-61937 transmitter and receiver functionality
- IEC-60958 supports 16-bit, 20-bit, and 24-bit data formats

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- IEC-61937 uses the IEC-60958 series for the conveying of non-linear PCM bit streams, each
sub-frame transmits 16-bit
• TXFIFO and RXFIFO
- One 128×24bits TXFIFO and one 64×24bits RXFIFO for audio data transfer
- Programmable FIFO thresholds
• Supports TX/RX DMA slave interface
• Supports multiple function clock
- Separate clock for OWA TX and OWA RX
- The clock of TX function includes 24.576 MHz and 22.579 MHz frequency
- The clock of RX function includes 24.576*8MHz frequency
• Supports hardware parity on TX/RX
- Hardware parity checking on the receiver
- Hardware parity generation on the transmitter
• Supports channel status capture on the receiver
• Supports channel sample rate capture on the receiver
• Supports insertion detection for the receiver
• Supports channel status insertion for the transmitter
• Supports interrupts and DMA
2.9 Security System

2.9.1 Crypto Engine (CE)
• Supports Symmetrical algorithm for encryption and decryption: AES, DES, TDES
- Supports ECB, CBC, CTS, CTR, CFB, OFB mode for AES
- Supports 128/192/256-bit key for AES
- Supports ECB, CBC, CTR mode for DES/TDES
• Supports Hash algorithm for tamper proofing: MD5, SHA, HMAC
- Supports SHA1, SHA224, SHA256, SHA384, SHA512 for SHA
- Supports HMAC-SHA1, HMAC-SHA256 for HMAC
- Supports multi-package mode for MD5/SHA1/SHA224/SHA256/SHA384/SHA512
• Supports Asymmetrical algorithm for signature verification: RSA
- RSA supports 512/1024/2048-bit width
• Supports 160-bit hardware PRNG with 175-bit seed
• Supports 256-bit hardware TRNG
• Internal DMA controller for data transfer with memory

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2.9.2 Security ID (SID)

• Supports 2 Kbits eFuse
• Backup eFuse information by using SID_SRAM
• Burning the key to the SID
• Reading the key use status in the SID
• Loading the key to the CE
2.10 External Peripherals

2.10.1 USB DRD
• One USB 2.0 DRD (USB0), with integrated USB 2.0 analog PHY
• Complies with USB2.0 Specification
• Supports USB Host function
- Compatible with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0
- Compatible with Open Host Controller Interface (OHCI) Specification, Version 1.0a
- Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s), and Low-Speed (LS, 1.5 Mbit/s)
- Supports only 1 USB Root port shared between EHCI and OHCI
• Supports USB Device function
- Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s)
- Supports bi-directional endpoint0 (EP0) for Control transfer
- Up to 10 user-configurable endpoints (EP1+, EP1-, EP2+, EP2-, EP3+, EP3-, EP4+, EP4-, EP5+, EP5-)
for Bulk transfer, Isochronous transfer and Interrupt transfer
- Up to (8 KB + 64 Bytes) FIFO for all EPs (including EP0)
- Support interface to an external Normal DMA controller for every EP
• Supports an internal DMA controller for data transfer with memory
• Supports High-Bandwidth Isochronous & Interrupt transfers
• Automated splitting/combining of packets for Bulk transfers
• Supports point-to-point and point-to-multipoint transfer in both Host and Peripheral modes
• Includes automatic ping capabilities
• Soft connect/disconnect function
• Performs all transaction scheduling in hardware
• Power optimization and power management capabilities
• Device and host controller share a 8K SRAM and a physical PHY

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2.10.2 USB HOST

• One USB 2.0 HOST (USB1), with integrated USB 2.0 analog PHY
• Complies with USB2.0 Specification
• Supports USB2.0 Host function
- Compatible with Enhanced Host Controller Interface (EHCI) Specification, Version 1.0
- Compatible with Open Host Controller Interface (OHCI) Specification, Version 1.0a
- Supports High-Speed (HS, 480 Mbit/s), Full-Speed (FS, 12 Mbit/s) and Low-Speed (LS, 1.5 Mbit/s)
Device
- Supports only 1 USB Root port shared between EHCI and OHCI
• An internal DMA Controller for data transfer with memory
2.10.3 EMAC
• One EMAC interface for connecting external Ethernet PHY
• 10/100/1000 Mbit/s Ethernet port with RGMII and RMII interfaces
• Compliant with IEEE 802.3-2002 standard
• Supports both full-duplex and half-duplex operations
• Provides the management data input/output (MDIO) interface for PHY device configuration and
management with configurable clock frequencies
• Programmable frame length to support Standard or Jumbo Ethernet frames with sizes up to 16 KB
• Supports a variety of flexible address filtering modes
• Separate 32-bit status returned for transmission and reception packets
• Optimization for packet-oriented DMA transfers with frame delimiters
- Supports linked-list descriptor list structure
- Descriptor architecture, allowing large blocks of data transfer with minimum CPU intervention; each
descriptor can transfer up to 4 KB of data
- Comprehensive status reporting for normal operation and transfers with errors
• 4 KB TXFIFO for transmission packets and 16 KB RXFIFO for reception packets
• Programmable interrupt options for different operational conditions
2.10.4 UART
• Up to 6 UART controllers (UART0, UART1, UART2, UART3, UART4, UART5)
• UART0, UART4, UART5: 2-wire; UART1, UART2, UART3: 4-wire
• Compatible with industry-standard 16450/16550 UARTs
• Supports IrDA-compatible slow infrared (SIR) format
• Two separate FIFOs: one is RX FIFO, and the other is TX FIFO

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- Each of them is 64 bytes (For UART0)

- Each of them is 256 bytes (For UART1, UART2, UART3, UART4, and UART5)
• The working reference clock is from the APB bus clock
- Speed up to 4 Mbit/s with 64 MHz APB clock
- Speed up to 1.5 Mbit/s with 24 MHz APB clock
• 5 to 8 data bits for RS-232 characters, or 9 bits RS-485 format
• 1, 1.5 or 2 stop bits
• Programmable parity (even, odd, or no parity)
• Supports TX/RX DMA slave controller interface
• Supports software/hardware flow control
• Supports RX DMA Master interface (Only for UART1)
• Supports auto-flow by using CTS & RTS (Only for UART1/2/3)
2.10.5 SPI and SPI_DBI

• Up to 2 SPI controllers (SPI0, SPI1)
• The SPI0 only supports SPI mode; The SPI1 supports SPI mode and display bus interface (DBI) mode
• SPI mode:
- Full-duplex synchronous serial interface
- Master/slave configurable
- Mode0 to Mode3 are supported for both transmit and receive operations
- 8-bit wide by 64-entry FIFO for both transmit and receive data
- Polarity and phase of the Chip Select (SPI-CS) and SPI Clock (SPI-CLK) are configurable
- Supports 3-wire/4-wire SPI
- Supports programmable serial data frame length: 1-bit to 32-bit
- Supports Standard SPI, Dual-Output/Dual-Input SPI, Dual IO SPI, Quad-Output/Quad-Input SPI
• DBI mode:
- Supports DBI Type C 3 Line/4 Line Interface Mode
- Supports 2 Data Lane Interface Mode
- Supports RGB111/444/565/666/888 video format
- Maximum resolution of RGB666 240 x 320@30Hz with single data lane
- Maximum resolution of RGB888 240 x 320@60Hz or 320 x 480@30Hz with dual data lane
- Supports Tearing effect
- Supports software flexible control video frame rate

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2.10.6 Two Wire Interface (TWI)

• Up to 4 TWI controllers (TWI0, TWI1, TWI2, TWI3)
• Compliant with I2C bus standard
• Supports standard mode (up to 100 kbit/s) and fast mode (up to 400 kbit/s)
• Supports 7-bit and 10-bit device addressing modes
• Supports master mode or slave mode
• Master mode features:
- Supports the bus arbitration in the case of multiple master devices
- Supports clock synchronization and bit and byte waiting
- Supports packet transmission and DMA
• Slave mode features:
- Interrupt on address detection
• The TWI controller includes one TWI engine and one TWI driver. And the TWI driver supports packet
transmission and DMA mode when TWI works in master mode
2.10.7 CIR Receiver (CIR_RX)

• One CIR_RX interface (IR-RX)
• Full physical layer implementation
• Supports NEC format infra data
• Supports CIR for remote control or wireless keyboard
• 64x8 bits FIFO for data buffer
• Sample clock up to 1 MHz
2.10.8 CIR Transmitter (CIR_TX)

• One CIR_TX interface (IR-TX)
• Supports arbitrary wave generator
• Configurable carrier frequency
• Supports handshake mode and waiting mode of DMA
• 128 bytes FIFO for data buffer
2.10.9 PWM
• Supports 8 independent PWM channels (PWM0 to PWM7)
- Supports PWM continuous mode output
- Supports PWM pulse mode output, and the pulse number is configurable

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- Output frequency range: 0 to 24 MHz or 100 MHz

- Various duty-cycle: 0% to 100%
- Minimum resolution: 1/65536
• Supports 4 complementary pairs output
- PWM01 pair (PWM0 + PWM1), PWM23 pair (PWM2 + PWM3), PWM45 pair (PWM4 + PWM5),
PWM67 pair (PWM6 + PWM7)
- Supports dead-zone generator, and the dead-zone time is configurable
• Supports 4 group of PWM channel output for controlling stepping motors
- Supports any plural channels to form a group, and output the same duty-cycle pulse
- In group mode, the relative phase of the output waveform for each channel is configurable
• Supports 8 channels capture input
- Supports rising edge detection and falling edge detection for input waveform pulse
- Supports pulse-width measurement for input waveform pulse
2.10.10 General Purpose ADC (GPADC)

• 1-ch successive approximation register (SAR) analog-to-digital converter (ADC)
• 12-bit sampling resolution and 8-bit precision
• 64 FIFO depth of data register
• Power reference voltage: AVCC, analog input voltage range: 0 to AVCC
• Maximum sampling frequency up to 1 MHz
• Supports three operation modes: single conversion mode, continuous conversion mode, burst
conversion mode
2.10.11 Touch Panel ADC (TPADC)

• 12 bit SAR type A/D converter
• Configurable sample frequency up to 1 MHz
• One 32x12 FIFO for storing A/D conversion result
• Supports DMA slave interface
• Supports 4-wire resistive touch panel input detection
- Supports pen down detection with programmable sensitivity
- Supports single touch coordinate measurement
- Supports dual touch detection
- Supports touch pressure measurement with programmable threshold
- Supports median and averaging filter for noise reduction
- Supports X and Y coordinate exchange function

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• Supports Aux ADC with up to 4 channels
2.10.12 LEDC
• LEDC is used to control the external intelligent control LED lamp
• Configurable LED output high/low level width
• Configurable LED reset time
• LEDC data supports DMA configuration mode and CPU configuration mode
• Maximum 1024 LEDs serial connect
• LED data transfer rate up to 800 kbit/s
2.10.13 CAN (only for F133-B)

• Supports industry-standard AMBA Peripheral Bus (APB) and it is fully compliant with the AMBA
Specification, Revision 2.0
• Supports APB 32-bit bus width operation
• Supports the CAN 2.0A and 2.0B protocol specification
• Supports one-shot transmission option
• Supports two configurable filter modes
• Supports listen only mode
• Supports self-test mode
2.11 Package
• eLQFP128, 14 mm x 14 mm x 1.4 mm

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3 Block Diagram
Figure 3-1 shows the system block diagram of the F133.
Figure 3-1 F133 System Block Diagram
Video Input RISC CPU Connectivity

CVBS IN USB2.0 DRD
I-cache 32 KB D-cache 32 KB USB2.0 HOST

Parallel CSI
SDIO3.0
SPI x2
Video Output Display Engine Internal System (Suppo rts SPI Nand/Nor Flash)
MIPI DSI DE CCU TWI x4
RGB DI PLIC UART x6
DMA 100M/1000M EMAC

Dual link LVDS G2D
Thermal Sensor GPADC (1-ch)
CVBS OUT Video Engine
Timer
Video Decoding TPADC (4-ch)
Audio H.265/H.264
High Speed Timer
PWM (8-ch)
Audio Codec Video Encoding
JPEG/MJPEG IOMMU
LEDC
I2S/PCM x2
Memory Security System CIR TX
DMIC SIP 64 MB DDR2 Crypto Engine
CIR RX
OWA IN/OUT SD3.0/eMMC5.0 SID CAN
Note: F133-A does not support CVBS IN and CAN interfaces.
Figure 3-2 shows the intelligent speaker solution of the F133.

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Figure 3-2 F133 Intelligent Speaker Solution

SPEAKER
USB USB LY8006 3.5mm

TVIN RTP KEY
Port Port headphones
Ethernet
RGMII(SDIO) USB0 USB1 TVIN0/1 TPADC GPADC HPOUTL/R
(WIFI)
UART1 LINEINL/R LINEIN
TF Card SMHC0 C906 FMINL/R FM
NOR/NAND/E SiP 64MB DDR2 MIC

SPI0 MICIN3N/P
MMC
RISC-V
Internal
DMIC DMIC
Reset Circuit
DAC HPOUT IIS
TVOUT TVOUT
24MHz Crystal DCXO DMA INTC
IR-TX/RX IR-TX/RX
32.768KHz OSC/32K
Crystal RTC Thermal Sensor UART DEBUG
Internal
LDOA/LDOB
LDO 1.8 V
5V Adapter
DCDC 3.3V PWM7
Power RGB/LVDS/
12V Adapter
DCDC 0.96 V Supply DSI Panel
PWM0~6 RGB/LVDS/
CAN1 NCSI TWI0/2
/LEDC DSI
Note: CAN is only for F133-B

CAN
CAMERA CTP LED
BUS

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4 Pin Description
4.1 Pin Quantity
Table 4-1 lists the pin quantity of the F133.
Table 4-1 F133 Pin Quantity
Pin Type F133-A Quantity F133-B Quantity
I/O 99 101
NC 7 2
Power 18 21
Ground 1 1
DDR Power 3 3
Total 128 128
4.2 Pin Characteristics

Table 4-2 lists the characteristics of the F133 pins from the following seven aspects.
[1].Ball#: Package ball numbers associated with each signal.
[2].Pin Name: The name of the package pin.
[3].Type: Denotes the signal direction
I (Input),
O (Output),
I/O (Input/Output),
OD (Open-Drain),
A (Analog),
AI (Analog Input),
AO (Analog Output),
P (Power),
G (Ground)
[4].Ball Reset State: The state of the terminal at reset. PU: pull up; PD: pull down; Z: high impedance.
[5].Pull Up/Down: Denotes the presence of an internal pull-up or pull-down resistor. Pull-up and pull-down
resistors can be enabled or disabled via software.
[6].Default Buffer Strength: Defines the default drive strength of the associated output buffer. The maximum
drive strength of each GPIO is 6 mA.
[7].Power Supply: The voltage supply for the IO buffers of the terminal.

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Table 4-2 Pin Characteristics
Ball Reset Pull Default Buffer Power

Ball#[1] Pin Name[2] Type[3]
State[4] Up/Down[5] [6]
Strength (mA) Supply[7]
SDRAM
48 VCC-DRAM0 P NA NA NA NA
49 VCC-DRAM1 P NA NA NA NA
50 VDD18-DRAM P NA NA NA NA
GPIOB
86 PB2 I/O Z PU/PD 4 VCC-IO
GPIOC
19 PC2 I/O Z PU/PD 4 VCC-IO
18 PC3 I/O PU PU/PD 4 VCC-IO
GPIOD
55 PD0 I/O Z PU/PD 4 VCC-PD

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65 VCC-LVDS P NA NA NA NA
66 VCC-PD P NA NA NA NA
GPIOE
44 PE0 I/O Z PU/PD 4 VCC-PE

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34 VCC-PE P NA NA NA NA
GPIOF
7 PF0 I/O Z PU/PD 4 VCC-IO
GPIOG
120 PG0 I/O Z PU/PD 4 VCC-PG

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128 VCC-PG P NA NA NA NA
System
27 RESET I, OD NA NA NA VCC-RTC
GPADC
101 GPADC0 AI NA NA NA AVCC
TPADC
102 TP-X1 AI NA NA NA AVCC
103 TP-X2 AI NA NA NA AVCC
104 TP-Y1 AI NA NA NA AVCC
105 TP-Y2 AI NA NA NA AVCC
USB
114 USB0-DM A I/O NA NA NA VCC-IO
115 USB0-DP A I/O NA NA NA VCC-IO
113 USB1-DM A I/O NA NA NA VCC-IO

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112 USB1-DP A I/O NA NA NA VCC-IO
CVBS OUT
78 TVOUT0 AO NA NA NA VCC-TVOUT
77 VCC-TVOUT P NA NA NA NA
CVBS IN (Only for F133-B) (1)
108 TVIN0 AI NA NA NA VCC-TVIN
109 TVIN1 AI NA NA NA VCC-TVIN
110 TVIN-VRP P NA NA NA VCC-TVIN
111 TVIN-VRN P NA NA NA VCC-TVIN
107 VCC-TVIN P NA NA NA NA
Audio Codec
87 MICIN3P AI NA NA NA AVCC
88 MICIN3N AI NA NA NA AVCC
93 FMINR AI NA NA NA AVCC
94 FMINL AI NA NA NA AVCC
95 LINEINR AI NA NA NA AVCC
96 LINEINL AI NA NA NA AVCC
98 HPOUTR AO NA NA NA HPVCC
99 HPOUTL AO NA NA NA HPVCC
100 HPOUTFB AI NA NA NA HPVCC
97 HPVCC P NA NA NA NA
92 VRA1 AO NA NA NA AVCC
90 VRA2 AO NA NA NA AVCC
89 AVCC P NA NA NA NA
91 AGND G NA NA NA NA

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RTC & PLL
25 X32KIN AI NA NA NA VCC-RTC
24 X32KOUT AO NA NA NA VCC-RTC
26 VCC-RTC P NA NA NA NA
20 VCC-PLL P NA NA NA NA
DCXO
23 DXIN AI NA NA NA VCC-PLL
22 DXOUT AO NA NA NA VCC-PLL
21 REFCLK-OUT AO NA NA NA VCC-PLL
NC
47 NC NA NA NA NA NA
106 NC0 NA NA NA NA NA
Power
29 LDO-IN P NA NA NA NA
28 LDOA-OUT P NA NA NA NA
30 LDOB-OUT P NA NA NA NA
83 VCC-IO P NA NA NA NA
46 VDD-SYS0 P NA NA NA NA
116 VDD-CORE0 P NA NA NA NA
117 VDD-CORE1 P NA NA NA NA
(1) For F133-A, these pins (107, 108, 109, 110, 111) are NC.

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4.3 GPIO Multiplex Function

The following table provides a description of the F133 GPIO multiplex function.
NOTE
For each GPIO, Function0 is input function; Function1 is output function; Function9 to Function13 are reserved.
Table 4-3 GPIO Multiplex Function
Pin GPIO IO
Function2 Function3 Function4 Function5 Function6 Function7 Function8 Function14
Name Group Type
PB2 I/O LCD0-D0 I2S2-DOUT2 TWI0-SDA I2S2-DIN2 LCD0-D18 UART4-TX PB-EINT2
PB3 I/O LCD0-D1 I2S2-DOUT1 TWI0-SCK I2S2-DIN0 LCD0-D19 UART4-RX PB-EINT3
PB4 I/O LCD0-D8 I2S2-DOUT0 TWI1-SCK I2S2-DIN1 LCD0-D20 UART5-TX PB-EINT4

GPIOB
PB5 I/O LCD0-D9 I2S2-BCLK TWI1-SDA PWM0 LCD0-D21 UART5-RX PB-EINT5
PB6 I/O LCD0-D16 I2S2-LRCK TWI3-SCK PWM1 LCD0-D22 UART3-TX CPUBIST0 PB-EINT6
PB7 I/O LCD0-D17 I2S2-MCLK TWI3-SDA IR-RX LCD0-D23 UART3-RX CPUBIST1 PB-EINT7
PC2 I/O SPI0-CLK SDC2-CLK PC-EINT2
PC3 I/O SPI0-CS0 SDC2-CMD PC-EINT3
PC4 I/O SPI0-MOSI SDC2-D2 BOOT-SEL0 PC-EINT4

GPIOC
PC5 I/O SPI0-MISO SDC2-D1 BOOT-SEL1 PC-EINT5
PC6 I/O SPI0-WP SDC2-D0 UART3-TX TWI3-SCK DBG-CLK PC-EINT6
PC7 I/O SPI0-HOLD SDC2-D3 UART3-RX TWI3-SDA TCON-TRIG PC-EINT7
PD0 I/O LCD0-D2 LVDS0-V0P DSI-D0P TWI0-SCK PD-EINT0
PD1 I/O LCD0-D3 LVDS0-V0N DSI-D0N UART2-TX PD-EINT1
PD2 I/O LCD0-D4 LVDS0-V1P DSI-D1P UART2-RX PD-EINT2
PD3 I/O LCD0-D5 LVDS0-V1N DSI-D1N UART2-RTS PD-EINT3
PD4 I/O LCD0-D6 LVDS0-V2P DSI-CKP UART2-CTS PD-EINT4
PD5 I/O LCD0-D7 LVDS0-V2N DSI-CKN UART5-TX PD-EINT5
PD6 I/O LCD0-D10 LVDS0-CKP DSI-D2P UART5-RX PD-EINT6
PD7 I/O LCD0-D11 LVDS0-CKN DSI-D2N UART4-TX PD-EINT7
PD8 I/O LCD0-D12 LVDS0-V3P DSI-D3P UART4-RX PD-EINT8
PD9 GPIOD I/O LCD0-D13 LVDS0-V3N DSI-D3N PWM6 PD-EINT9
PD10 I/O LCD0-D14 LVDS1-V0P SPI1-CS/DBI-CSX UART3-TX PD-EINT10
PD11 I/O LCD0-D15 LVDS1-V0N SPI1-CLK/DBI-SCLK UART3-RX PD-EINT11
PD12 I/O LCD0-D18 LVDS1-V1P SPI1-MOSI/DBI-SDO TWI0-SDA PD-EINT12
PD13 I/O LCD0-D19 LVDS1-V1N SPI1-MISO/DBI-SDI/ UART3-RTS PD-EINT13

DBI-TE/DBI-DCX
PD14 I/O LCD0-D20 LVDS1-V2P SPI1-HOLD/DBI-DCX UART3-CTS PD-EINT14

/DBI-WRX
PD15 I/O LCD0-D21 LVDS1-V2N SPI1-WP/DBI-TE IR-RX PD-EINT15
PD16 I/O LCD0-D22 LVDS1-CKP DMIC-DATA3 PWM0 PD-EINT16
PD17 I/O LCD0-D23 LVDS1-CKN DMIC-DATA2 PWM1 PD-EINT17

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Pin GPIO IO
Name Group Type
PD18 I/O LCD0-CLK LVDS1-V3P DMIC-DATA1 PWM2 PD-EINT18
PD19 I/O LCD0-DE LVDS1-V3N DMIC-DATA0 PWM3 PD-EINT19
PD20 I/O LCD0-HSYNC TWI2-SCK DMIC-CLK PWM4 PD-EINT20
PD21 I/O LCD0-VSYNC TWI2-SDA UART1-TX PWM5 PD-EINT21
PD22 I/O OWA-OUT IR-RX UART1-RX PWM7 PD-EINT22
RGMII-RXCTRL
PE0 I/O NCSI0-HSYNC UART2-RTS TWI1-SCK LCD0-HSYNC PE-EINT0
/RMII-CRS-DV
RGMII-RXD0/
PE1 I/O NCSI0-VSYNC UART2-CTS TWI1-SDA LCD0-VSYNC PE-EINT1
RMII-RXD0
RGMII-RXD1/
PE2 I/O NCSI0-PCLK UART2-TX TWI0-SCK CLK-FANOUT0 UART0-TX PE-EINT2
RMII-RXD1
RGMII-TXCK/
PE3 I/O NCSI0-MCLK UART2-RX TWI0-SDA CLK-FANOUT1 UART0-RX PE-EINT3
RMII-TXCK
RGMII-TXD0/
PE4 I/O NCSI0-D0 UART4-TX TWI2-SCK CLK-FANOUT2 R-JTAG-MS PE-EINT4
RMII-TXD0
RGMII-TXD1/
PE5 I/O NCSI0-D1 UART4-RX TWI2-SDA LEDC-DO R-JTAG-DI PE-EINT5
RMII-TXD1
GPIOE
RGMII-TXCTRL
PE6 I/O NCSI0-D2 UART5-TX TWI3-SCK OWA-IN R-JTAG-DO PE-EINT6
/RMII-TXEN
RGMII-CLKIN/
PE7 I/O NCSI0-D3 UART5-RX TWI3-SDA OWA-OUT R-JTAG-CK PE-EINT7
RMII-RXER
PE8 I/O NCSI0-D4 UART1-RTS PWM2 UART3-TX MDC PE-EINT8
PE9 I/O NCSI0-D5 UART1-CTS PWM3 UART3-RX MDIO PE-EINT9
PE10 I/O NCSI0-D6 UART1-TX PWM4 IR-RX EPHY-25M PE-EINT10
PE11 I/O NCSI0-D7 UART1-RX RGMII-TXD2 PE-EINT11
PE12 I/O TWI2-SCK NCSI0-FIELD RGMII-TXD3 PE-EINT12
PE13 I/O TWI2-SDA PWM5 DMIC-DATA3 RGMII-RXD2 PE-EINT13
PF0 I/O SDC0-D1 R-JTAG-MS I2S2-DOUT1 I2S2-DIN0 PF-EINT0
PF1 I/O SDC0-D0 R-JTAG-DI I2S2-DOUT0 I2S2-DIN1 PF-EINT1
PF2 I/O SDC0-CLK UART0-TX TWI0-SCK LEDC-DO OWA-IN PF-EINT2
PF3 GPIOF I/O SDC0-CMD R-JTAG-DO I2S2-BCLK PF-EINT3
PF4 I/O SDC0-D3 UART0-RX TWI0-SDA PWM6 IR-TX PF-EINT4
PF5 I/O SDC0-D2 R-JTAG-CK I2S2-LRCK PF-EINT5
PF6 I/O OWA-OUT IR-RX I2S2-MCLK PWM5 PF-EINT6
RGMII-RXCTRL/
PG0 I/O SDC1-CLK UART3-TX PWM7 PG-EINT0
RMII-CRS-DV
RGMII-RXD0/
PG1 I/O SDC1-CMD UART3-RX PWM6 PG-EINT1
RMII-RXD0
GPIOG RGMII-RXD1/
PG2 I/O SDC1-D0 UART3-RTS UART4-TX PG-EINT2
RMII-RXD1
RGMII-TXCK/
PG3 I/O SDC1-D1 UART3-CTS UART4-RX PG-EINT3
RMII-TXCK
PG4 I/O SDC1-D2 UART5-TX RGMII-TXD0/ PWM5 PG-EINT4

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Pin GPIO IO
Name Group Type
RMII-TXD0
RGMII-TXD1/
PG5 I/O SDC1-D3 UART5-RX PWM4 PG-EINT5
RMII-TXD1
PG6 I/O UART1-TX TWI2-SCK RGMII-TXD2 PWM1 PG-EINT6
PG7 I/O UART1-RX TWI2-SDA RGMII-TXD3 OWA-IN PG-EINT7
PG8 I/O UART1-RTS TWI1-SCK RGMII-RXD2 UART3-TX PG-EINT8
PG9 I/O UART1-CTS TWI1-SDA RGMII-RXD3 UART3-RX PG-EINT9
PG10 I/O PWM3 TWI3-SCK RGMII-RXCK CLK-FANOUT0 IR-RX PG-EINT10
PG11 I/O I2S1-MCLK TWI3-SDA EPHY-25M CLK-FANOUT1 TCON-TRIG PG-EINT11
RGMII-TXCTRL/
PG12 I/O I2S1-LRCK TWI0-SCK CLK-FANOUT2 PWM0 UART1-TX PG-EINT12
RMII-TXEN
RGMII-CLKIN/
PG13 I/O I2S1-BCLK TWI0-SDA PWM2 LEDC-DO UART1-RX PG-EINT13
RMII-RXER
PG14 I/O I2S1-DIN0 TWI2-SCK MDC I2S1-DOUT1 SPI0-WP UART1-RTS PG-EINT14
PG15 I/O I2S1-DOUT0 TWI2-SDA MDIO I2S1-DIN1 SPI0-HOLD UART1-CTS PG-EINT15

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4.4 Detailed Signal Description

Table 4-4 shows the detailed function description of every signal based on the different interface.
[1].Signal Name: The name of every signal.
[2].Description: The detailed function description of every signal.
[3].Type: Denotes the signal direction:
I (Input),
O (Output),
I/O (Input/Output),
OD (Open-Drain),
A (Analog),
AI (Analog Input),
AO (Analog Output),
A I/O (Analog Input/Output),
P (Power),
G (Ground)
Table 4-4 Detailed Signal Description
Signal Name[1] Description[2] Type[3]
DRAM
VDD18-DRAM DRAM Controller Power Supply P
VCC-DRAM0, VCC-DRAM1 DRAM Power Supply P
System Control
BOOT-SEL[1:0] Boot Media Select I
RESET Reset Signal (low active) I, OD
Clock
X32KIN Clock Input of 32.768 kHz Crystal AI
X32KOUT Clock Output of 32.768 kHz Crystal AO
VCC-RTC RTC Power P
VCC-PLL PLL Power Supply P
DCXO

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REFCLK-OUT Digital Compensated Crystal Oscillator Clock Fanout AO
DXIN Digital Compensated Crystal Oscillator Input AI
DXOUT Digital Compensated Crystal Oscillator Output AO
USB
USB0-DM USB DRD Data Signal DM A I/O
USB0-DP USB DRD Data Signal DP A I/O
USB1-DM USB HOST Data Signal DM A I/O
USB1-DP USB HOST Data Signal DP A I/O
GPADC
GPADC0 General Purpose ADC Input Channel 0 AI
TPADC
TP-X1 Touch Panel X1 Input AI
TP-X2 Touch Panel X2 Input AI
TP-Y1 Touch Panel Y1 Input AI
TP-Y2 Touch Panel Y2 Input AI
CVBS OUT
TVOUT0 TV CVBS Output AO
VCC-TVOUT TV CVBS DAC Power P
CVBS IN (Only for F133-B)
TVIN0 TV CVBS Input 0 AI
TVIN1 TV CVBS Input 1 AI
TVIN-VRP TV CVBS ADC Positive Reference Voltage P
TVIN-VRN TV CVBS ADC Negative Reference Voltage P
VCC-TVIN TV CVBS ADC Power P
AUDIO CODEC

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HPOUTR Headphone Right Output AO
HPOUTL Headphone Light Output AO
HPOUTFB Pseudo Differential Headphone Ground Reference AI
HPVCC Headphone Power P
MICIN3P Microphone Differential Positive Input 3 AI
MICIN3N Microphone Differential Negative Input 3 AI
FMINR FMIN Right Input AI
FMINL FMIN Left Input AI
LINEINR LINEIN Right Single-End Input AI
LINEINL LINEIN Left Single-End Input AI
VRA1 Internal Reference Voltage AO
VRA2 Internal Reference Voltage AO
AVCC Power Supply for Analog Part P
AGND Analog Ground G
LCD
LCD-D[23:0] LCD Data Output O
LCD Clock
LCD0-CLK O
The pixel data are synchronized by this clock
LCD Vertical Sync

LCD0-VSYNC O
It indicates one new frame
LCD Horizontal Sync

LCD0-HSYNC O
It indicates one new scan line
LCD0-DE LCD Data Output Enable O
TCON-TRIG LCD Sync (TCON outputs to LCD for sync) O
LVDS
LVDS0-CKP LVDS0 Positive Port of Clock O

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LVDS0-CKN LVDS0 Negative Port of Clock O
LVDS0-V[3:0]P LVDS0 Positive Port of Data Channel [3:0] O
LVDS0-V[3:0]N LVDS0 Negative Port of Data Channel [3:0] O
LVDS1-CKP LVDS1 Positive Port of Clock O
LVDS1-CKN LVDS1 Negative Port of Clock O
LVDS1-V[3:0]P LVDS1 Positive Port of Data Channel [3:0] O
LVDS1-V[3:0]N LVDS1 Negative Port of Data Channel [3:0] O
DSI
DSI-D[3:0]P DSI Differential Data [3:0] Positive Signal O
DSI-D[3:0]N DSI Differential Data [3:0] Negative Signal O
DSI-CKP DSI Differential Clock Positive Signal O
DSI-CKN DSI Differential Clock Negative Signal O
Parallel CSI
NCSI0-PCLK Parallel CSI Pixel Clock I
NCSI0-MCLK Parallel CSI Master Clock O
NCSI0-HSYNC Parallel CSI Horizontal Synchronous I
NCSI0-VSYNC Parallel CSI Vertical Synchronous I
NCSI0-D[7:0] Parallel CSI Data Bit I
NCSI0-FIELD Parallel CSI Field Index I
SMHC
SDC0-CMD Command Signal for SD Card I/O, OD
SDC0-CLK Clock for SD Card O
SDC0-D[3:0] Data Input and Output for SD Card I/O
SDC1-CMD Command Signal for SDIO WIFI I/O, OD
SDC1-CLK Clock for SDIO WIFI O

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SDC1-D[3:0] Data Input and Output for SDIO WIFI I/O
SDC2-CMD Command Signal for eMMC I/O, OD
SDC2-CLK Clock for eMMC O
SDC2-D[3:0] Data Input and Output for eMMC I/O
I2S/PCM
I2S1-MCLK I2S1 Master Clock O
I2S1-LRCK I2S1/PCM1 Sample Rate Clock/Sync I/O
I2S1-BCLK I2S1/PCM1 Bit Rate Clock I/O
I2S1-DOUT[1:0] I2S1/PCM1 Serial Data Output Channel [1:0] O
I2S1-DIN[1:0] I2S1/PCM1 Serial Data Input Channel [1:0] I
I2S2-MCLK I2S2 Master Clock O
I2S2-LRCK I2S2/PCM2 Sample Rate Clock/Sync I/O
I2S2-BCLK I2S2/PCM2 Bit Rate Clock I/O
I2S2-DOUT[2:0] I2S2/PCM2 Serial Data Output Channel [2:0] O
I2S2-DIN[2:0] I2S2/PCM2 Serial Data Input Channel [2:0] I
DMIC
DMIC-CLK Digital Microphone Clock Output O
DMIC-DATA[3:0] Digital Microphone Data Input I
EMAC
RGMII-RXD3 RGMII Receive Data3 I
RGMII-RXD2 RGMII Receive Data2 I
RGMII-RXD1/RMII-RXD1 RGMII/RMII Receive Data1 I
RGMII-RXD0/RMII-RXD0 RGMII/RMII Receive Data0 I
RGMII-RXCK RGMII Receive Clock I
RGMII Receive Control/RMII Carrier Sense Receive

RGMII-RXCTRL/RMII-CRS-DV I
Data Valid

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RGMII Transmit Clock from External/RMII Receive

RGMII-CLKIN/RMII-RXER I
Error
RGMII-TXD3 RGMII Transmit Data3 O
RGMII-TXD2 RGMII Transmit Data2 O
RGMII-TXD1/RMII-TXD1 RGMII/RMII Transmit Data1 O
RGMII-TXD0/RMII-TXD0 RGMII/RMII Transmit Data0 O
RGMII/RMII Transmit Clock

RGMII-TXCK/RMII-TXCK For RGMII, IO type is output; I/O
For RMII, IO type is input
RGMII-TXCTRL/RMII-TXEN RGMII Transmit Control/RMII Transmit Enable O
MDC RGMII/RMII Management Data Clock O
MDIO RGMII/RMII Management Data Input/Output I/O
EPHY-25M 25 MHz Output for EMAC PHY O
OWA
OWA-IN One Wire Audio Input I
OWA-OUT One Wire Audio Output O
LEDC
LEDC-DO Intelligent Control LED Signal Output O
Interrupt
PB-EINT[7:2] GPIO B Interrupt I
PC-EINT[7:2] GPIO C Interrupt I
PD-EINT[22:0] GPIO D Interrupt I
PE-EINT[13:0] GPIO E Interrupt I
PF-EINT[6:0] GPIO F Interrupt I
PG-EINT[15:0] GPIO G Interrupt I
CIR Receiver

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IR-RX Consumer Infrared Receiver I
CIR Transmitter
IR-TX Consumer Infrared Transmitter O
PWM
PWM[7:0] Pulse Width Modulation Output Channel [7:0] I/O
SPI&SPI_DBI
SPI0-CS SPI0 Chip Select Signal, Low Active I/O
SPI0 Clock Signal

SPI0-CLK I/O
Provides serial interface timing.
SPI0-MOSI SPI0 Master Data Out, Slave Data In I/O
SPI0-MISO SPI0 Master Data In, Slave Data Out I/O
SPI0 Write Protect, Low Active

Protects the memory area against all program or
SPI0-WP erase instructions. I/O
It also can be used for serial data input and output
for SPI Quad Input or Quad Output mode.
SPI0 Hold Signal

Pauses any serial communication with the device
SPI0-HOLD without deselecting or resetting it. I/O
SPI1-CS SPI1 Chip Select Signal, Low Active I/O
SPI1 Clock Signal

SPI1-CLK I/O
Provides serial interface timing.
SPI1-MOSI SPI1 Master Data Out, Slave Data In I/O
SPI1-MISO SPI1 Master Data In, Slave Data Out I/O
SPI1 Write Protect, Low Active
SPI1-WP Protects the memory area against all program or I/O

erase instructions.

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SPI1 Hold Signal

Pauses any serial communication with the device
SPI1-HOLD without resetting it. I/O
DBI-CSX Chip Select Signal, Low Active I/O
DBI-SCLK Serial Clock Signal I/O
DBI-SDO Data Output Signal I/O
Data Input Signal

DBI-SDI The data is sampled on the rising edge and the I/O
falling edge
Tearing Effect Input

DBI-TE It is used to capture the external TE signal edge. The I/O
rising and falling edge is configurable.
DCX pin is the select output signal of data and

command.
DBI-DCX I/O
DCX = 0: register command;
DCX = 1: data or parameter.
When DBI operates in dual data lane format, the

DBI-WRX I/O
RGB666 format 2 can use WRX to transfer data
UART
UART0-TX UART0 Data Transmit O
UART0-RX UART0 Data Receive I
UART1-CTS UART1 Data Clear to Send I
UART1-RTS UART1 Data Request to Send O

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TWI
TWI0-SCK TWI0 Serial Clock Signal I/O
TWI0-SDA TWI0 Serial Data Signal I/O
JTAG
R-JTAG-MS RISC JTAG Mode Select I
R-JTAG-CK RISC JTAG Clock Signal I
R-JTAG-DO RISC JTAG Data Output O
R-JTAG-DI RISC JTAG Data Input I

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5 Electrical Characteristics
5.1 Parameter Conditions
5.1.1 Minimum and Maximum Values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of
ambient temperature, supply voltage, and frequencies by tests in production on 100% of the devices with
ambient temperature at Ta = 25 °C and Ta = Ta max.
Data based on characterization results, design simulation, and/or technology characteristics are indicated in
the table footnotes and are not tested in production.
5.1.2 Typical Values

Unless otherwise specified, the typical data are based on Ta = 25 °C. They are given only as design guidelines.
5.1.3 Temperature Definitions

 Ambient Temperature— the temperature of the surrounding environment.
 Junction Temperature— the hottest temperature of the silicon chip inside the package.
 Absolute Maximum Junction Temperature— the temperature beyond which damage occurs to the device.
The device may not function or meet expected performance at this temperature.
 Recommended Operating Temperature— the junction temperature at which the device operates
continuously at the designated performance over the designed lifetime. The reliability of the device may
be degraded if the device operates above this temperature. Some devices will not function electrically
above this temperature.
5.2 Absolute Maximum Ratings

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Table 5-1
specifies the absolute maximum ratings.
CAUTION
Stresses beyond those listed under Table 5-1 may affect reliability or cause permanent damage to the device.
These are stress ratings only. Functional operation of the device at these or any other conditions beyond
those indicated under Section 5.3, Recommended Operating Conditions, is not implied. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.
Table 5-1 Absolute Maximum Ratings
Symbol Parameter Min(1) Max(1) Unit

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AVCC Power Supply for Analog Part -0.3 2.16 V
HPVCC Headphone Power -0.3 2.16 V
VCC-PD Digital GPIO D Power -0.3 3.96 V
VCC-PE Digital GPIO E Power -0.3 3.96 V
VCC-PG Digital GPIO G Power -0.3 3.96 V
VCC-IO Power Supply for 3.3 V Digital Part -0.3 3.96 V
VCC-RTC Power Supply for RTC -0.3 TBD V
VCC-PLL Power Supply for System PLL -0.3 TBD V
VCC-LVDS Power Supply for LVDS -0.3 TBD V
VCC-TVOUT Power Supply for TVOUT -0.3 TBD V
VCC-TVIN Power Supply for TVIN -0.3 TBD V
VCC-DRAM0,
Power Supply for DRAM IO and DDR2 -0.3 TBD V
VCC-DRAM1
VDD18-DRAM Power Supply for DRAM Controller -0.3 TBD V
VDD-CORE0,
Power Supply for CPU and System -0.3 TBD V
VDD-CORE1
VDD-SYS0,
VDD-SYS1, Power Supply for System -0.3 TBD V
VDD-SYS2
LDO-IN Internal LDOA/B Input Voltage -0.3 3.96 V
Internal LDOA Output Voltage for Analog Device and

LDOA-OUT -0.3 2.16 V
IO
LDOB-OUT Internal LDOB Output Voltage for VCC-DRAM -0.3 2.16 V
TSTG Storage Temperature -40 150 °C
Tj Working Junction Temperature -20 125 °C
Human Body Model (HBM)(3) -4000 4000 V

Electrostatic
VESD
Discharge(2)
Charged Device Model (CDM)(4) -500 500 V

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Latch-up I-test performance current-pulse injection

Pass
on each IO pin(5)
ILatch-up
Latch-up over-voltage performance voltage injection
Pass
on each IO pin(6)
(1) The min/max voltages of power rails are guaranteed by design, not tested in production.
(2) Electrostatic discharge (ESD) to measure device sensitivity/immunity to damage caused by electrostatic
discharges into the devices.
(3) Level listed above is the passing level per ESDA/JEDEC JS-001-2017.
(4) Level listed above is the passing level per ESDA/JEDEC JS-002-2018.
(5) Based on JESD78E; each device is tested with IO pin injection of ±200 mA at room temperature.
(6) Based on JESD78E; each device is tested with a stress voltage of 1.5 x Vddmax at room temperature.
5.3 Recommended Operating Conditions

Table 5-2 describes operating conditions of the F133.
NOTE
Logic functions and parameter values are not assured out of the range specified in the recommended
operating conditions.
Table 5-2 Recommended Operating Conditions
Symbol Parameter Min Typ Max Unit
Ambient Operating Temperature (when

-20 - 85 °C
VCC-DRAM0/1 uses external power)
Ta
Ambient Operating Temperature (when
-20 - 70 °C
VCC-DRAM0/1 uses internal LDO)
Tj Working Junction Temperature Range -20 - 110(1) °C
AVCC Power Supply for Analog Part 1.782 1.8 1.818 V
HPVCC Headphone Power 1.782 1.8 1.818 V
Digital GPIO D Power

VCC-PD V
1.8 V voltage 1.62 1.8 1.98

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3.3 V voltage 2.97 3.3 3.63
Digital GPIO E Power

1.8 V voltage 1.62 1.8 1.98
VCC-PE V
2.8 V voltage 2.52 2.8 3.08
3.3 V voltage 2.97 3.3 3.63
Digital GPIO G Power

VCC-PG 1.8 V voltage 1.62 1.8 1.98 V
3.3 V voltage 2.97 3.3 3.63
Power Supply for Digital Part

VCC-IO 2.97 3.3 3.63 V
3.3 V voltage
VCC-RTC Power Supply for RTC TBD 1.8 TBD V
VCC-PLL Power Supply for System PLL TBD 1.8 TBD V
VCC-LVDS Power Supply for LVDS TBD 1.8 TBD V
VCC-TVOUT Power Supply for TVOUT TBD 3.3 TBD V
VCC-TVIN Power Supply for TVIN TBD 1.8 TBD V
VCC-DRAM0,
Power Supply for DRAM IO and DDR2 TBD 1.8 TBD V
VCC-DRAM1
VDD18-DRAM Power Supply for DRAM Controller 1.7 1.8 1.95 V
VDD-CORE0,
Power Supply for CPU and System TBD 0.9 TBD V
VDD-CORE1
VDD-SYS0,
VDD-SYS1, Power Supply for System TBD 0.9 TBD V
VDD-SYS2
LDO-IN Internal LDOA/B Input Voltage 2.4 3.3 3.6 V
Internal LDOA Output Voltage for Analog

LDOA-OUT 1.782 1.8 1.818 V
Device and IO
1.31 1.35(2) 1.39

Internal LDOB Output Voltage for
LDOB-OUT 1.455 1.5 1.545 V
VCC-DRAM
1.746 1.8 1.854

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(1). The chip junction temperature in normal working condition should be less than or equal to the maximum
junction temperature in Table 5-2.
(2). The default voltage of LDOB-OUT is 1.35 V.
5.4 Power Consumption Parameters

The current consumption is a function of several parameters and factors such as the operating voltage,
ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching
rate, program location in memory and executed binary code.
The current consumption is measured as described in the following table.
NOTE
Since the data presented in the following table is based on empirical measurements on small sample size, the
results presented are not guaranteed.
Table 5-3 Power Consumption Parameters
Sub Power
Parameter Condition Typ Max Unit
Parameter Supply
VDD-CORE0,
CPU 0.9 V - TBD mA
VDD-CORE1
Internal VDD-SYS0,
Core VDD-SYS1,
Power
SYS VDD-SYS2, 0.9 V - TBD mA
VDD-CORE0,
VDD-CORE1
VCC-IO For GPIO, voltage 3.3 V, N=19 - 114 mA
VCC-PD For GPIO, voltage 3.3 V, N=23 - 138 mA

GPIO Power
VCC-PE For GPIO, voltage 3.3 V, N=14 - 84 mA
VCC-PG For GPIO, voltage 3.3 V, N=16 - 96 mA
Memory I/O Power VCC-DRAM SIP 64 MB DDR2 - TBD mA
LVDS Power VCC-LVDS 1.8 V, 700 MHz dual link - 50 mA
CVBS OUT Power VCC-TVOUT 3.3 V - TBD mA
CVBS IN Power VCC-TVIN 1.8 V - TBD mA

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Sub Power
Parameter Condition Typ Max Unit
Parameter Supply
24 MHz Crystal
VCC-PLL 1.8 V - 2 mA
Oscillator
RTC Power VCC-RTC 1.8 V - 0.01 mA
1.8 V, 48 kHz sample rate,

ADC Analog Power AVCC - TBD mA
5-chs are enabled
1.8 V, 48 kHz sample rate,

DAC Analog Power AVCC - TBD mA
2-chs are enabled
USB Power VCC-IO 2 x USB, 3.3 V - 35 mA
General equation for estimated, maximum power consumption of an group IO power supply:
Imax = N x 6 mA
Where:
N—Number of IO pins supplied by the power line.
The maximum power consumption for each IO is 6 mA.
5.5 DC Electrical Characteristics

Table 5-4 summarizes the DC electrical characteristics of the F133. For the interfaces of GPIO function port,
refer to the DC parameters in Table 5-4 unless otherwise stated.
Table 5-4 DC Electrical Characteristics
(VCC-IO/VCC-PD/VCC-PE/VCC-PG)
VIH High-Level Input Voltage 0.7 * VCC-IO - VCC-IO + 0.3 V
VIL Low-Level Input Voltage -0.3 - 0.3 * VCC-IO V
PC3 to PC7, PF3,

12 15 18 kΩ
PF6
Input Pull-up
RPU
Resistance PG0 to PG5 26 33 40 kΩ
Other GPIOs 80 100 120 kΩ
PC3 to PC7, PF3,

12 15 18 kΩ
Input Pull-down PF6
RPD
Resistance
PG0 to PG5 26 33 40 kΩ

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Other GPIOs 80 100 120 kΩ
IIH High-Level Input Current - - 10 uA
IIL Low-Level Input Current - - 10 uA
VOH High-Level Output Voltage VCC-IO – 0.3 - VCC-IO V
VOL Low-Level Output Voltage 0 - 0.2 V
IOZ Tri-State Output Leakage Current -10 - 10 uA
CIN Input Capacitance - - 5 pF
COUT Output Capacitance - - 5 pF
5.6 SDIO Electrical Characteristics

The SDIO electrical parameters are related to different supply voltage.
Figure 5-1 SDIO Voltage Waveform
Table 5-5 shows 3.3 V SDIO electrical parameters.

Table 5-5 3.3 V SDIO Electrical Parameters
VDD Power voltage 2.7 - 3.6 V
VCCQ I/O voltage 2.7 3.6 V
VOH Output high-level voltage 0.75 * VCCQ - - V
VOL Output low-level voltage - - 0.125 * VCCQ V

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VIH Input high-level voltage 0.625 * VCCQ - VCCQ + 0.3 V
VIL Input low-level voltage VSS – 0.3 - 0.25 * VCCQ V
Table 5-6 shows 1.8 V SDIO electrical parameters.

Table 5-6 1.8 V SDIO Electrical Parameters
VDD Power voltage 2.7 - 3.6 V
VCCQ I/O voltage 1.7 1.95 V
VOH Output high-level voltage VCCQ – 0.45 - - V
VOL Output low-level voltage - - 0.45 V
VIH Input high-level voltage 0.625 * VCCQ (1) - VCCQ + 0.3 V
VIL Input low-level voltage VSS – 0.3 - 0.35 * VCCQ (2) V
(1).0.7 * VCCQ for MMC4.3 or lower.

(2).0.3 * VCCQ for MMC4.3 or lower.
5.7 GPADC Electrical Characteristics

The GPADC contains a 1-ch analog-to-digital (ADC) converter. The GPADC is a type of successive approximation
register (SAR) converter. Table 5-7 lists GPADC electrical characteristics.
Table 5-7 GPADC Electrical Characteristics
Parameter Min Typ Max Unit
ADC Resolution - 12 - bits
Full-scale Input Range 0 - AVCC V
Quantizing Error - 8 - LSB
Clock Frequency - - 1 MHz
Conversion Time - 14 - ADC Clock Cycles

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5.8 Audio Codec Electrical Characteristics

Test Conditions:
VDD-SYS = 0.9 V, AVCC = 1.8 V, Ta = 25 °C, 1 kHz sinusoid signal, DAC fs = 48 kHz, ADC fs = 16 kHz, Input gain =
0 dB, 16-bit audio data unless otherwise stated.
Table 5-8 Audio Codec Typical Performance Parameters
Symbol Parameter Test Conditions Min Typ Max Unit
DAC to HPOUTL or HPOUTR
Full-scale 0dBFS 1 kHz - 540 - Vrms
SNR (A-weighted) 0data - 95 - dB

DAC Path
THD+N 0dBFS 1 kHz - -85 - dB
R_0dB_L_0data 1 kHz
Crosstalk - TBD - dB
L_0dB_R_0data 1 kHz
LINEINLR via ADC
Output Level 1.7 Vpp, 1 kHz - 875 - mFFS
SNR (A-weighted) 0 Vpp - 94 - dB
THD+N 1.7 Vpp, 1 kHz - -88 - dB
FMINLR via ADC
Output Level 1.7 Vpp, 1 kHz - 875 - mFFS
SNR (A-weighted) 0 Vpp - 94 - dB
THD+N 1.7 Vpp, 1 kHz - -88 - dB

ADC Path
MICIN via ADC
Output Level - 880 - mFFS

MICP=3.3Vpp/2, MICN=3.3Vpp/2,
SNR (A-weighted) - 98 - dB
1 kHz, 0 dB Gain
THD+N - -90 - dB

1 kHz, 6 dB Gain
THD+N - -93 - dB
Output Level MICP=0.788Vpp/2, MICN=0.788Vpp/2, - 880 - mFFS

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Symbol Parameter Test Conditions Min Typ Max Unit
1 kHz,12 dB Gain
THD+N - -85 - dB

1 kHz, 18 dB Gain
THD+N - -83 - dB

1 kHz,24 dB Gain
THD+N - -80 - dB

1 kHz,30 dB Gain
THD+N - -73 - dB

1 kHz,36 dB Gain
THD+N - -65 - dB
5.9 External Clock Source Characteristics

5.9.1 High-speed Crystal/Ceramic Resonator Characteristics
The high-speed external clock can be supplied with a 24 MHz crystal resonator (oscillation mode). The 24 MHz
crystal resonator provides 24 MHz reference clock which is connected to the DXIN and DXOUT terminals.
Table 5-9 High-speed 24 MHz Crystal Circuit Characteristics
fX24M_IN Crystal parallel resonance frequency - 24 - MHz
Crystal frequency stability and tolerance at

-50 - +50 ppm
25 °C (1)
Oscillation mode Fundamental -
C0 Shunt capacitance (2) - 6.5 - pF
1. The 50 ppm frequency stability and tolerance can meet the requirement of F133. We recommend
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selecting 20 ppm crystal devices. If the REFCLK-OUT (24 MHz fanout) is used for Wi-Fi chip, the crystal
uses the recommended specification or the specified model for Wi-Fi chip.
2. The 6.5 pF is only a simulation value. The crystal shunt capacitance (C0) is given by the crystal
manufacturer.
Table 5-10 Crystal Circuit Parameters
Symbol Parameter
C1 C1 capacitance
C2 C2 capacitance
CL Equivalent load capacitance, specified by the crystal manufacturer
C0 Crystal shunt capacitance, specified by the crystal manufacturer
Cshunt Total shunt capacitance
Frequency stability mainly requires that the total load capacitance (CL) be constant. The crystal manufacturer
typically specifies a total load capacitance which is the series combination of C1, C2, and Cshunt.
The total load capacitance is CL = [(C1 * C2)/(C1 + C2)] + Cshunt.
 C1 and C2 represent the total capacitance of the respective PCB trace, load capacitor, and other
components (excluding the crystal) connected to each crystal terminal. C1 and C2 are usually the same
size.
 Cshunt is the crystal shunt capacitance (C0) plus any mutual capacitance (Cpkg + CPCB) seen across the DXIN
and DXOUT signals.
In the application, the crystal resonator and the load capacitors must be placed close to the oscillator pins in
order to minimize output distortion and the startup stabilization time. Refer to the crystal resonator
manufacturer for more details on the resonator characteristics.
NOTE
For the above capacitances of 24 MHz crystal circuit, refer to the capacitance recommended in the
F133_Schematic_Diagram.
5.9.2 Low-speed Crystal/Ceramic Resonator Characteristics

The F133 contains an RC oscillation circuit that generates a 32.768 kHz clock, meanwhile, the DCXO module
can calibrate the RC oscillation circuit regularly. If the product does not have a high requirement for the
accuracy of the system clock, the external 32.768 kHz crystal circuit can be omitted and the internal RC
oscillation circuit can be adopted, meanwhile, the relevant clock configuration needs to be turned on by the

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software.
The F133 also can connect to a 32.768 kHz crystal resonator (oscillation mode). The 32.768 kHz crystal
resonator provides 32.768 kHz reference clock which is connected to the X32KIN and X32KOUT terminals. In
the application, the crystal resonator and the load capacitors must be placed close to the oscillator pins to
minimize output distortion and the startup stabilization time. Refer to the crystal resonator manufacturer for
more details on the resonator characteristics.
Table 5-11 Low-speed 32.768 kHz Crystal Circuit Characteristics
fX32K_IN Crystal parallel resonance frequency - 32.768 - kHz
Crystal frequency stability and tolerance at

- - - ppm
25 °C (1)
Oscillation mode Fundamental -
C0 Shunt capacitance (2) - 1.1 - pF
1. The F133 has no requirement for the frequency stability and tolerance of 32.768 kHz crystal. If the actual
product has requirement for the accuracy of timing function, the 20 ppm stability and tolerance is
recommended.
2. The 1.1 pF is only a simulation value. The crystal shunt capacitance (C0) is given by the crystal
manufacturer.
NOTE
For capacitances of 32.768 kHz crystal circuit, refer to the capacitance recommended in the
F133_Schematic_Diagram.
5.10 Internal Reset Electrical Characteristics

Table 5-12 Internal Reset Electrical Characteristics
Parameter Test Condition Min Typ Max Unit
Power-on threshold voltage

of VDD-SYS on which the Ta= -20°C to 85°C - 0.4 - V
reset signal is excited
Reset active timeout period Ta= -20°C to 85°C - 64 - ms
Reset open-drain output

Ta= -20°C to 85°C, pull up 3.3 V -0.3 - 0.3*VCC V
voltage

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5.11 External Memory Electrical Characteristics

5.11.1 SMHC AC Electrical Characteristics
5.11.1.1 HS-SDR Mode
NOTE
IO voltage is 1.8 V or 3.3 V.
Figure 5-2 SMHC HS-SDR Mode Output Timing Diagram
Table 5-13 SMHC HS-SDR Mode Output Timing Constants
Parameter Symbol Min Typ Max Unit
CLK
Clock frequency tCK 0 50 50 MHz
Duty cycle DC 45 50 55 %
Output CMD, DATA (referenced to CLK)
CMD, Data output

tODLY - 0.25 0.5 UI
delay time
Data output delay

tOSKEW 0.5 - 0.8 ns
skew time
(1). The Unit Interval (UI) is 1-bit nominal time. For example, UI=20 ns at 50 MHz.
(2). The driver strength level of GPIO is 2 for test.

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Figure 5-3 SMHC HS-SDR Mode Input Timing Diagram
Table 5-14 SMHC HS-SDR Mode Input Timing Constants
CLK
Input CMD, DATA (referenced to CLK 50 MHz)
Data input delay in

SDR mode. It includes
Clock’s PCB delay
time, Data’s PCB tIDLY - - - ns
delay time and
device’s data output
delay
Data input skew time

tISKEW 0.5 - 0.8 ns
in SDR mode
5.11.1.2 HS-DDR Mode

Figure 5-4 SMHC HS-DDR Mode Output Timing Diagram

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Table 5-15 SMHC HS-DDR Mode Output Timing Constants
CLK
CMD, Data output

delay time in DDR tODLY_DDR - 0.25 0.25 UI
mode
Data output delay

tOSKEW_DDR 0.5 - 0.8 ns
skew time
Figure 5-5 SMHC HS-DDR Mode Input Timing Diagram
Table 5-16 SMHC HS-DDR Mode Input Timing Constants
CLK
Input CMD, DATA (referenced to CLK 50 MHz)
Data input delay in

DDR mode. It tIDLY_DDR - - - ns
includes Clock’s PCB
delay time, Data’s

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PCB delay time and

device’s data output
delay
Data input skew time

tISKEW_DDR 0.5 - 0.8 ns
in DDR mode
5.11.1.3 HS200 Mode

Figure 5-6 SMHC HS200 Mode Output Timing Diagram
Table 5-17 SMHC HS200 Mode Output Timing Constants
CLK
Clock frequency tCK 0 - 150 MHz
CMD, Data output

tODLY - 0.25 0.5 UI
delay time
Data output delay

tOSKEW 0.5 - 0.8 ns
skew time

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Figure 5-7 SMHC HS200 Mode Input Timing Diagram
Table 5-18 SMHC HS200 Mode Input Timing Constants
Parameter Symbol Min Typ Max Unit Remark
CLK
Max:
Clock period tPERIOD 6.66 - - ns
150 MHz
Rise time, fall

tTLH, tTHL - - 0.2 UI
time
Input CMD, DATA (referenced to CLK)
Input delay tPH 0 - 2 UI
Input delay
variation due to
temperature dPH -350[3] - 1550[4] ps
change after
tuning
CMD, Data valid

tVW 0.575 - - UI
window
(3). Temperature variation: -20oC.

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Parameter Symbol Min Typ Max Unit Remark
(4). Temperature variation: 90oC.
5.12 External Peripheral Electrical Characteristics

5.12.1 LCD AC Electrical Characteristics
Figure 5-8 HV_IF Interface Vertical Timing

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Figure 5-9 HV_IF Interface Horizontal Timing
Table 5-19 LCD HV_IF Interface Timing Constants
DCLK cycle time tDCLK 5 - - ns
Hsync period time tHT - HT+1 - tDCLK
Hsync width tHSPW - HSPW+1 - tDCLK
Hsync back porch tHBP - HBP+1 - tDCLK
Vsync period time tVT - VT/2 - tHT
Vsync width tVSPW - VSPW+1 - tHT

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Vsync back porch tVBP - VBP+1 - tHT
(1) Vsync: Vertical sync, indicates one new frame.

(2) Hsync: Horizontal sync, indicates one new scan line.
(3) DCLK: Dot clock, pixel data are sync by this clock.
(4) LDE: LCD data enable.
(5) LD[23..0]: 24Bit RGB/YUV output from input FIFO for panel.
5.12.2 CSI AC Electrical Characteristics

Figure 5-10 CSI Data Sample Timing
tperiod
thigh-level
PCLK
tdst tdhd
DATA
Table 5-20 CSI Interface Timing Constants
Pclk period tperiod 6.73 - - ns
Pclk frequency 1/tperiod - - 148.5 MHz
Pclk duty thigh-level/tperiod 40 50 60 %
Data input setup time tdst 0.6 - - ns
Data input hold time tdhd 0.6 - - ns

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5.12.3 EMAC AC Electrical Characteristics

5.12.3.1 RGMII
Figure 5-11 RGMII Interface Transmit Timing
Tclk
RGMII_TX_CLK
Tisu Tiph
RGMII/TBI Input
Topv
RGMII Output
Toph
Table 5-21 RGMII Transmit Timing Constants
RGMII_TX_CLK clock period Tclk 8 - DC ns
RGMII/TBI input setup prior to RGMII_TX_CLK Tisu 2.8 - - ns
RGMII/TBI input data hold after RGMII_TX_CLK Tiph 0.1 - - ns
RGMII output data valid after RGMII_TX_CLK Topv - - 0.85 ns
RGMII output data hold after RGMII_TX_CLK Toph 0 - - ns
Figure 5-12 RGMII Interface Receive Timing
Tclk
RGMII_RX_CLK
Tisu
RGMII Input
Tiph
Topv
Toph
RGMII/TBI Output
Table 5-22 RGMII Receive Timing Constants

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RGMII_RX_CLK clock period Tclk 8 - DC ns
RGMII input setup prior to RGMII_RX_CLK Tisu 2.6 - - ns
RGMII input data hold after RGMII_RX_CLK Tiph 0.8 - - ns
RGMII/TBI input data valid after RGMII_RX_CLK Topv - - 5.2 ns
RGMII output data hold after RGMII_RX_CLK 0.1

Toph - - ns
TBI output data hold after RGMII_RX_CLK 0.5
5.12.3.2 RMII
Figure 5-13 RMII Interface Transmit Timing
Table 5-23 RMII Transmit Timing Constants
Reference clock period Tref_clk - 20 - ns
TXD/TXEN to REF_CLK setup time Ts 4 - - ns
TXD/TXEN to REF_CLK hold time Th 2 - - ns
Figure 5-14 RMII Interface Receive Timing
Table 5-24 RMII Receive Timing Constants
Reference clock period Tref_clk - 20 - ns

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REF_CLK rising edge to RX_DV/RXD Td - 10 12 ns
5.12.4 SPI AC Electrical Characteristics

Figure 5-15 SPI Writing Timing
CS# th(cs)
ts(cs)
SCLK
th(mo) td(mo)
MOSI MSB LSB
MISO
Figure 5-16 SPI Reading Timing
CS#
Left offs et2.4 ns

Internal
SCLK
Actual
SCLK th(mi)
ts(mi)
MISO MSB LSB
MOSI
Table 5-25 SPI Timing Constants
CS# active setup time ts(cs) - 2T(1) - ns
CS# active hold time th(cs) - 2T(1) - ns
Data output delay time td(mo) - T(1)/2-3 - ns
Data output hold time th(mo) - T(1)/2-3 - ns
Data input setup time ts(mi) 0.2 - - ns
Data input hold time th(mi) 0.2 - - ns

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(1).T is the cycle of clock.
5.12.5 SPI_DBI AC Electrical Characteristics

Figure 5-17 DBI 3-line Serial Interface Timing
CSX tcsh
tcss
twc/trc
SCL
twrl/trdl
twrh/trdh
tds tdh
SDI
(write)
tod
tacc
SDO
(read)
Table 5-26 DBI 3-line Serial Interface Timing Parameters
Signal Parameter Symbol Min Max Unit
Chip select setup time (Write) tcss 15 ns

CSX
Chip select setup time (Read) tcsh 60 ns
Write cycle twc 16 ns

SCL
Control pulse “H” duration twrh 7 ns
(write)
Control pulse “L” duration twrl 7 ns
Read cycle trc 150 ns

SCL
Control pulse “H” duration trdh 60 ns
(read)
Control pulse “L” duration trdl 60 ns
SDI/SDO Data setup time tds 7 ns
(write) Data hold time tdt 7 ns
SDI/SDO Read access time tracc 10 50 ns

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(read)
Output disable time tod 15 50 ns
Figure 5-18 DBI 4-line Serial Interface Timing
CSX tcsh
tcss
DCX
tas tah
twc/trc
SCL
twrl/trdl
twrh/trdh
tds tdh
SDI
(write)
tod
tacc
SDO
(read)
Table 5-27 DBI 4-line Serial Interface Timing Parameters
Chip select setup time (Write) tcss 15 ns

CSX
Chip select setup time (Read) tcsh 60 ns
Address setup time tas 10 ns

DCX
Address hold time (Write/Read) tah 10 ns
Write cycle twc 16 ns

SCL
Control pulse “H” duration twrh 7 ns
(write)
Control pulse “L” duration twrl 7 ns
Read cycle trc 150 ns

SCL
Control pulse “H” duration trdh 60 ns
(read)
Control pulse “L” duration trdl 60 ns

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SDI/SDO Data setup time tds 7 ns
(write) Data hold time tdt 7 ns
SDI/SDO Read access time tracc - 50 ns
(read) Output disable time tod 15 50 ns
5.12.6 UART AC Electrical Characteristics

Figure 5-19 UART RX Timing
Register Setting:
Data length(DLS in LCR[1:0]) = 3 (8bit)
Stop bit length(STOP in LCR[2]) = 1 (2bit)
Parity enable(PEN in LCR[3]) = 1
RX start data parity stop
RX FIFO
vaild data
DATA
tRXSF
Figure 5-20 UART nCTS Timing
TX start data parity stop start
nCTS
tDCTS tACTS

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Figure 5-21 UART nRTS Timing
Register Setting:
RTS Trigger level(RT in FCR[7:6]) = 3 (De-asserted nRTS when FIFO valid data number reach FIFO depth-2)
RX FIFO (1)
FD -3 FD-2 0
DATA NUM
nRTS
tDRTS tARTS
Note (1): FD: FIFO Depth
Table 5-28 UART Timing Constants
RX start to RX FIFO tRXSF 10.5 * BRP(1) - 11 * BRP(1) ns
Delay time of de-asserted

tDCTS - - BRP(1) ns
nCTS to TX start
Step time of asserted nCTS to

tACTS BRP(1)/4 - - ns
stop next transmission
Delay time of de-asserted

tDRTS - - BRP(1) ns
nRTS
Delay time of asserted nRTS tARTS - - BRP(1) ns
(1). BRP: Baud-Rate Period.
5.12.7 TWI AC Electrical Characteristics

Figure 5-22 TWI Timing

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Table 5-29 TWI Timing Parameters
Standard mode Fast mode

Parameter Symbol Unit
Min Max Min Max
SCK clock frequency Fsck 0 100 0 400 kHz
Setup time in Start Tsu-STA 4.7 - 0.6 - us
Hold time in Start Thd-STA 4.0 - 0.6 - us
Setup time in Data Tsu-DAT 250 - 100 - ns
Hold time in Data Thd-DAT 5.0 - - - ns
Setup time in Stop Tsu-STO 4.0 - 6.0 - us
SCK low level time Tlow 4.7 - 1.3 - us
SCK high level time Thigh 4.0 - 0.6 - ns
SCK/SDA falling time Tf - 300 20 300 ns
SCK/SDA rising time Tr - 1000 20 300 ns
5.12.8 I2S/PCM AC Electrical Characteristics

Figure 5-23 I2S/PCM Timing in Master Mode
Table 5-30 I2S/PCM Timing Constants in Master Mode
LRCK delay Td(LRCK) - - 10 ns
LRCK to DOUT delay (For LJF) Td(DO-LRCK) - - 10 ns
BCLK to DOUT delay Td(DO-BCLK) - - 10 ns

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DIN setup Ts(DI) 4 - - ns
DIN hold Th(DI) 4 - - ns
BCLK rise time Tr - - 8 ns
BCLK fall time Tf - - 8 ns
Figure 5-24 I2S/PCM Timing in Slave Mode
Table 5-31 I2S/PCM Timing Constants in Slave Mode
LRCK setup Ts(LRCK) 4 - - ns
LRCK hold Th(LRCK) 4 - - ns
LRCK to DOUT delay (For LJF) Td(DO-LRCK) - - 10 ns
BCLK to DOUT delay Td(DO-BCLK) - - 10 ns
DIN setup Ts(DI) 4 - - ns
DIN hold Th(DI) 4 - - ns
BCLK rise time Tr - - 4 ns
BCLK fall time Tf - - 4 ns

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5.12.9 DMIC AC Electrical Characteristics

Figure 5-25 DMIC Timing
Table 5-32 DMIC Timing Constants
DMIC_DATA (Right) setup time to falling edge

TRSU 15 - - ns
of DMIC_CLK
DMIC_DATA (Right) hold time from falling

TRH 0 - - ns
edge of DMIC_CLK
DMIC_DATA (Left) setup time to rising edge

TLSU 15 - - ns
of DMIC_CLK
DMIC_DATA (Left) hold time from rising edge

TLH 0 - - ns
of DMIC_CLK
5.12.10 OWA AC Electrical Characteristics

Figure 5-26 OWA Timing
OWA_OUT
Tf(OWA_OUT) Tr(OWA_OUT)
OWA_IN
Tf(OWA_IN) Tr(OWA_IN)
Table 5-33 OWA Timing Constants
OWA_OUT rise time Tr(OWA_OUT) - - 8 ns
OWA_OUT fall time Tf(OWA_OUT) - - 8 ns
OWA_IN rise time Tr(OWA_IN) - - 4 ns

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OWA_IN fall time Tf(OWA_IN) - - 4 ns
5.12.11 CIR_RX AC Electrical Characteristics

Figure 5-27 CIR_RX Timing
Address #Address Command #Command
IR_NEC
Tlh Tll Tp T1 T0
Tf
Table 5-34 CIR_RX Timing Constants
Frame period Tf - 67.5 - ms
Lead code high time Tlh - 9 - ms
Lead code low time Tll - 4.5 - ms
Pulse time Tp - 560 - us
Logical 1 low time T1 - 1680 - us
Logical 0 low time T0 - 560 - us
5.13 Power-On and Power-Off Sequence

5.13.1 Power-On Sequence
Figure 5-28 shows an example of the power-on sequence for the F133 device. The description of the
power-on sequence is as follows.
• The consequent steps in power-on sequence should not start before the previous step supplies have
been stabilized within 90–110% of their nominal voltage, unless stated otherwise.
• VCC-RTC must be ramped no later than other power rails.
• VCC-IO must be ramped before VDD-SYS and VDD-CORE with a minimum delay of 2 ms.
• VCC-DRAM needs be stable before SDRAM driver initialization.
• During the entire power on sequence, the RESET signal must be held on low until all other power rails
(except 24 MHz CLK) are stable for more than 64 ms.
• 24MHz clock starts oscillating after the RESET signal is released.

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Figure 5-28 Power-On Timing
1.8 V
VCC-RTC
90%
1.8 V
90%
VCC-PLL
VCC-TVIN
VCC-LVDS
VDD18-DRAM 1.8 V/1.5 V
90%
VCC-DRAM0/1
1.8 V/3.3 V
90%
VCC-PE
VCC-PG
3.3 V
VCC-IO 90%
VCC-PD
VCC-TVOUT T1>2 ms
LDO-IN 0.9 V
90%
VDD-SYS0/1/2
VDD-CORE0/1
24M CLK
RESET 10%
T2>64 ms
5.13.2 Power-Off Sequence

The power-off requirements are as follows.
• After the RESET signal goes low, the 24 MHz clock starts to stop oscillating.
• No special restrictions for other power rails.

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Figure 5-29 Power-Off Timing
DCIN
1.8 V
VCC-RTC
VCC-PLL
VCC-TVIN
VCC-LVDS
VDD18-DRAM
1.8 V
VCC-DRAM0/1
1.8 V/1.5 V
VCC-PE
VCC-PG
VCC-IO 1.8 V/3.3 V

VCC-PD
VCC-TVOUT
LDOIN
HPLDOIN 3.3 V
VDD-SYS
VDD-CORE
0.9 V
24M CLK
RESET

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6 Package Thermal Characteristics

The maximum chip junction temperature (TJ max) must never exceed the values given in Table 5-2
Recommended Operating Conditions.
The maximum chip-junction temperature TJ max, in degrees Celsius, may be calculated using the following
equation:
TJ max = Ta max + (PD max x θJA)
Where:
Ta max is the maximum ambient temperature in °C.
PD max is the maximum power dissipation.
θJA is the package junction-to-ambient thermal resistance, in °C/W.
°C/W = degrees Celsius per watt.
Failure to maintain a junction temperature within the range specified reduces operating lifetime, reliability,
and performance, and may cause irreversible damage to the system. It is useful to calculate the exact power
consumption and junction temperature to determine which the temperature will be best suited to the
application. Therefore, the product should include thermal analysis and thermal design to ensure the
operating junction temperature of the device is within functional limits.
The following tables show the thermal resistance characteristics of the F133. These data are based on JEDEC
JESD51 standard, because the actual system design and temperature could be different from JEDEC JESD51,
these simulating data are a reference only and may not represent actual use-case values, please prevail in the
actual application condition test.
Table 6-1 F133 Package Thermal Characteristics
Symbol Parameter Min Typ(1) Max Unit
θJA Junction-to-Ambient Thermal Resistance - 20.36 - °C/W
θJB Junction-to-Board Thermal Resistance - 7.43 - °C/W
θJC Junction-to-Case Thermal Resistance - 5.52 - °C/W
1. Reference document: JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions – Natural
Convection (Still Air). Available from www.jedec.org.

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7 Pin Assignment
7.1 Pin Map
For F133, eLQFP128, 14 mm x 14 mm package is offered. The following figure shows the pin map of the F133.
Figure 7-1 F133 Pin Map
The pin map difference between F133-A and F133-B is as follows.

Table 7-1 Pin Map Difference between F133-A and F133-B
Pin No. F133-A F133-B
107 NC VCC-TVIN
108 NC TVIN0

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Pin No. F133-A F133-B
109 NC TVIN1
110 NC TVIN-VRP
111 NC TVIN-VRN

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7.2 Package Dimension

Figure 7-2 shows the top, bottom, and side views of F133 package dimension.
Figure 7-2 F133 Package Dimension
CAUTION
Make sure to use the second set of exposed pad size (D3/E3: 5.72 mm REF or 0.225 inch REF) to design the
PCB footprint because the F133 package is designed according to this size.

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8 Carrier, Storage and Baking Information

8.1 Carrier
8.1.1 Matrix Tray Information
Table 8-1 shows the F133 matrix tray carrier information.
Table 8-1 Matrix Tray Carrier Information
Item Color Size Note
Tray Black 315 mm x 136 mm x 7.62 mm 90 Qty/Tray
Vacuum packing
Silvery
Aluminum foil bags 540 mm x 300 mm x 0.14 mm Including HIC and desiccant
white
Printing: RoHS symbol
Pearl cotton cushion

White 12 mm x 680 mm x 185 mm
(Vacuum bag)
Left-Right:
Pearl cotton cushion
(The Gap between 12 mm x 180 mm x 85 mm
White
vacuum bag and inner Front-Back:
box)
12 mm x 350 mm x 70 mm
Printing: RoHS symbol

Inner Box White 396 mm x 196 mm x 96 mm
10 Tray/Inner box
Carton White 420 mm x 410 mm x 320 mm 6 Inner box/Carton
Table 8-2 shows the F133 packing quantity.

Table 8-2 F133 Packing Quantity Information
Full Inner Box Full Carton

Sample Size (mm) Qty/Tray Tray/Inner Box Inner Box/Carton
Qty Qty
F133-A,
14 x 14 90 10 900 6 5400
F133-B
Figure 8-1 shows tray dimension drawing of the F133.

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Figure 8-1 F133 Tray Dimension Drawing
8.2 Storage
Reliability is affected if any condition specified in Section 8.2.2 and Section 8.2.3 has been exceeded.
8.2.1 Moisture Sensitivity Level (MSL)

A package’s MSL indicates its ability to withstand exposure after it is removed from its shipment bag, a low
MSL device sample can be exposed on the factory floor longer than a high MSL device sample. Table 8-3
defines all MSL.
NOTE
The F133 device samples are classified as MSL3.
Table 8-3 MSL Summary
MSL Out-of-bag floor life Comments
1 Unlimited ≤30°C / 85%RH
2 1 year ≤30°C / 60%RH
2a 4 weeks ≤30°C / 60%RH
3 168 hours ≤30°C / 60%RH

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MSL Out-of-bag floor life Comments
4 72 hours ≤30°C / 60%RH
5 48 hours ≤30°C / 60%RH
5a 24 hours ≤30°C / 60%RH
6 Time on Label (TOL) ≤30°C / 60%RH
8.2.2 Bagged Storage Conditions

Table 8-4 defines the shelf life of the F133 device samples.
Table 8-4 Bagged Storage Conditions
Packing mode Vacuum packing
Storage temperature 20–26°C
Storage humidity 40–60%RH
Shelf life 12 months
8.2.3 Out-of-bag Duration

It is defined by the device MSL rating. The out-of-bag duration of the F133 is as follows.
Table 8-5 Out-of-bag Duration
Storage temperature 20–26°C
Storage humidity 40–60%RH
Moisture sensitive level (MSL) 3
Floor life 168 hours
For no mention of storage rules in this document, refer to the latest IPC/JEDEC J-STD-020C.
8.3 Baking
It is not necessary to bake the F133 if the conditions specified in Section 8.2.2 and Section 8.2.3 have not
been exceeded. It is necessary to bake the F133 if any condition specified in Section 8.2.2 and Section 8.2.3
has been exceeded.

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It is necessary to bake the F133 if the storage humidity condition has been exceeded, we recommend that the
device sample removed from its shipment bag for more than 2 days shall be baked to guarantee production.
Baking conditions: 125°C, 8 hours, nitrogen protection. Note that the baking should not exceed 1 times due to
a risk of deformation.

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9 Reflow Profile
All Allwinner chips provided for clients are lead-free RoHS-compliant products.
The reflow profile recommended in this document is a lead-free reflow profile that is suitable for pure
lead-free technology of lead-free solder paste. If customers need to use lead solder paste, contact Allwinner
FAE.
Figure 9-1 shows the appropriate reflow profile.

Figure 9-1 Lead-free Reflow Profile
Table 9-1 Lead-free Reflow Profile Conditions
QTI typical SMT reflow profile conditions (for reference only)
Step Reflow condition
Environment N2 purge reflow usage (yes/no) Yes, N2 purge used
If yes, O2 ppm level O2 < 1500 ppm
A Preheat ramp up temperature range 25°C -> 150°C
B Preheat ramp up rate 1.5–2.5 °C/s
C Soak temperature range 150°C -> 190°C
D Soak time 80–110 s
E Liquidus temperature 217°C
F Time above liquidus 60–90 s

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QTI typical SMT reflow profile conditions (for reference only)
Step Reflow condition
G Peak temperature 240–250°C
H Cool down temperature rate ≤4°C/s
The method of measuring the reflow soldering process is as follows.

Fix the thermocouple probe of the temperature measuring line at the connection point between the pin
(solderable end) of the packaged device and the pad by using high-temperature solder wire or
high-temperature tape, fix the packaged device at the pad by using high-temperature tape or other methods,
and cover over the thermocouple probe. See Figure 9-2.
Figure 9-2 Measuring the Reflow Soldering Process
NOTE
To measure the temperature of the QFP-packaged chip, place the temperature probe directly at the pin.
If possible, the more accurate measuring way is to drill the packaged device, or drill the PCB, and fix the
thermocouple probe through the drilled hole at the pad.

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10 FT/QA/QC Test
10.1 FT Test
FT test is the finished product testing after the chip is packaged, and it is a functional test of all modules for
each produced chip.
10.2 QA Test
QA test is a system-level sampling test for good-quality chips. According to the application level of the chip, a
certain percentage of good-quality chips are selected for system-level testing to make the chip work in a
typical application scenario, and judge whether the chip works normally in this scenario.
10.3 QC Test
QC test is a module-level sampling test for good-quality chips. According to the chip application level, a
certain percentage of good-quality chips are selected for module-level functional testing to monitor whether
the chip production process is normal.

Confidential
11 Part Marking
11.1 F133-A
Figure 11-1 shows the F133-A marking.
Figure 11-1 F133-A Marking
Table 11-1 describes the F133-A marking definitions.

Table 11-1 F133-A Marking Definitions
No. Marking Description Fixed/Dynamic
1 ALLWINNERTECH Allwinner logo or name Fixed
2 F133-A Product name Fixed
3 LLLLLAA Lot number Dynamic
4 XXX1 Date code Dynamic
11.2 F133-B
Figure 11-2 shows the F133-B marking.
Figure 11-2 F133-B Marking
Table 11-2 describes the F133-B marking definitions.

Confidential
Table 11-2 F133-B Marking Definitions
No. Marking Description Fixed/Dynamic
1 ALLWINNERTECH Allwinner logo or name Fixed
2 F133-B Product name Fixed
3 LLLLLAA Lot number Dynamic
4 XXX1 Date code Dynamic

Copyright© 2021 Allwinner Technology Co.,Ltd. All Rights Reserved.
This documentation is the original work and copyrighted property of Allwinner Technology Co.,Ltd (“Allwinner”). No
part of this document may be reproduced, modify, publish or transmitted in any form or by any means without prior
written consent of Allwinner.
Trademarks and Permissions
Allwinner and the Allwinner logo (incomplete enumeration) are trademarks of Allwinner Technology Co.,Ltd. All other
trademarks, trade names, product or service names mentioned in this document are the property of their respective
owners.
Important Notice and Disclaimer
The purchased products, services and features are stipulated by the contract made between Allwinner Technology
Co.,Ltd (“Allwinner”) and the customer. All or part of the products, services and features described in this document
may not be within the purchase scope or the usage scope. Please read the terms and conditions of the contract and
relevant instructions carefully before using, and follow the instructions in this documentation strictly. Allwinner
assumes no responsibility for the consequences of improper use (including but not limited to overvoltage, overclock, or
excessive temperature).
The information in this document is provided just as a reference or typical applications, and is subject to change
without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents.
Allwinner is not responsible for any damage (including but not limited to indirect, incidental or special loss) or any
infringement of third party rights arising from the use of this document. All statements, information, and
recommendations in this document do not constitute a warranty or commitment of any kind, express or implied.
No license is granted by Allwinner herein express or implied or otherwise to any patent or intellectual property of
Allwinner. Third party licences may be required to implement the solution/product. Customers shall be solely
responsible to obtain all appropriately required third party licences. Allwinner shall not be liable for any licence fee or
royalty due in respect of any required third party licence. Allwinner shall have no warranty, indemnity or other
obligations with respect to third party licences.

Copyright © 2021 Allwinner Technology Co.,Ltd. All Rights Reserved.
Allwinner Technology Co.,Ltd.

No.9 Technology Road 2, High-Tech Zone,
Zhuhai, Guangdong Province, China
Contact US:
Service@allwinnertech.com
www.allwinnertech.com

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F133

The Most Cost-Effective Decoding Platform Processor

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved

Revision Date Description

1.0 May 24, 2021 Initial release version.

1.1 June 11, 2021 Add caution description in section 7.2.

1.2 August 16, 2021 Add CAN for F133-B

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. i

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. ii

2.7.6 Thermal Sensor Controller (THS) ..........................................................................................................9

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. iii

5.1.1 Minimum and Maximum Values ....................................................................................................... 40

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. iv

8 Carrier, Storage and Baking Information ................................................................................................................... 77

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. v

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. vi

Figure 7-2 F133 Package Dimension ................................................................................................................................... 76

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. vii

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. viii

Table 5-28 UART Timing Constants ..................................................................................................................................... 66

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. ix

About This Documentation

CAUTION Indicates potential risk of equipment damage, data loss, performance

NOTE Provides additional information to emphasize or supplement important points of

Table Content Conventions

- The cell is blank.

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. 1

Type Symbol Value

Data capacity 1M 1,048,576

Frequency, data rate 1M 1,000,000

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. 2

1.1 Device Difference

Table 1-1 Device Feature Differences

Contents F133-A F133-B

CVBS IN No support Support

CAN No support Support

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. 3

2.2 Memory Subsystem

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. 4

• Internal 1024-Bytes RX FIFO and 1024-Bytes TX FIFO

2.3 Video Engine

2.4 Video and Graphics

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. 5

- Adaptive contrast enhancement and fresh tone rectify

2.4.2 De-interlacer (DI)

2.4.3 Graphic 2D (G2D)

2.5 Video Output

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. 6

• RGB666 and RGB565 with dither function

2.5.2 MIPI DSI

2.5.3 CVBS OUT

2.6 Video Input

2.6.2 CVBS IN (Only for F133-B)

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. 7

• Detection for signal locked and 625 lines

2.7 System Peripherals

2.7.2 High Speed Timer (HSTimer)

2.7.3 Platform-Level Interrupt Controller (PLIC)

Copyright© Allwinner Technology Co.,Ltd. All Rights Reserved. 8