JOURNAL OF INFORMATION, KNOWLEDGE AND RESEARCH IN

ELECTRONICS AND COMMUNICATION

ON CHIP DECOULING CAPACITOR

1
ROHINI N. DEOKAR , 2 P. R. THORAT
1, 2
Department of Electronics Engineering, Savitribai Phule Womens Engg. college,
B.A.M.U. University, Aurangabad, Maharashtra, India.

rohinideokar30@gmail.com, Thorat.popat.r.@gmail.com
ABSTRACT : Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling
capacitors have traditionally been allocated into the white space available on the die based on an unsystematic
or ad hoc approach. In this way, large decoupling capacitors are often placed at a significant distance from the
current load, compromising the signal integrity of the system. This issue of power delivery cannot be alleviated
by simply increasing the size of the on-chip decoupling capacitors. To be effective, the on-chip decoupling
capacitors should be placed physically close to the current loads. The area occupied by the on chip decoupling
capacitor, however, is directly proportional to the magnitude of the capacitor. The minimum impedance
between the on-chip decoupling capacitor and the current load is therefore fundamentally affected by the
magnitude of the capacitor. A distributed on-chip decoupling capacitor network is proposed in this paper. A
system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the
required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on
chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution
grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Techniques
presented in this paper are applicable not only for current technologies, but also provide an efficient placement
of the on chip decoupling capacitors in future technology generations. Index Terms Power distribution systems,
power distribution grids, decoupling capacitors, power noise.

1. INTRODUCTION
On-chip decoupling capacitors (decaps) are widely the power distribution system (PDS). Decaps acts as
used to reduce power supply noise. Capacitors play a a local source of energy for a short period. With the
critical role in the stable operation of digital scaling of CMOS technologies the power supply
electronics by protecting sensitive microchips from voltage is lowered, clock frequency has gone up, and
noise on the power signal which can cause more functionality is integrated on-chip resulting in
anomalous behaviors. Capacitors used in this higher simultaneous switching noise (SSN). As a
application are called decoupling capacitors and result signal integrity of on-chip power supply has
should be placed as close as possible to each become a major concern. Placement and sizing of
microchip to be most effective, as all circuit traces decaps, effective utilization of on-chip whitespace,
act as antennas and will pick up noise from the resonant free voltage responses for a wide range of
surrounding environment. Decoupling and by-pass frequencies are some of the key challenges faced
capacitors are also used in any area of a circuit to with the shift towards deep submicron regime.
reduce the overall impact of electrical noise. Decoupling capacitors are used to reduce unwanted
A decoupling capacitor is a capacitor used AC signals riding on DC supply circuits and also in
to decouple one part of an electrical network (circuit) places in a circuit where AC signals need to be
from another. Noise caused by other circuit elements eliminated. These are usually placed between the DC
is shunted through the capacitor, reducing the effect it supply and the ground of the circuit or directly across
has on the rest of the circuit. For example, if the another component. Decoupling capacitors known as
voltage level for a device is fixed, changing power “charge reservoirs” are placed between power and
demands are manifested as changing current demand. ground lines to maintain low target impedance and to
The power supply must accommodate these reduce the noise in power distribution network. Low
variations in current draw with as little change as impedance and resonant free response are two
possible in the power supply voltage. When the requirements for maintaining power and signal
current draw in a device changes, the power supply integrity of the PDS. Power distribution system
can’t respond to that change instantaneously. (PDS) spans different levels of hierarchy consisting
Decoupling is the process of breaking coupling of voltage regulator module, power distribution
between portions of systems and circuits to ensure network on board, on package and on-chip the power
proper operation. Typically, designs use NMOS distribution system (PDS). Decaps acts as a local
decaps between standard-cell blocks and source of energy for a short period. With the scaling
NMOS+PMOS decaps within the blocks. Decoupling of CMOS technologies the power supply voltage is
capacitors (decap) are often used to filter out noise in lowered, clock frequency has gone up, and more

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functionality is integrated on-chip resulting in higher act as antennas and will pick up noise from the
simultaneous switching noise (SSN). As a result surrounding environment. Decoupling and by-pass
signal integrity of on-chip power supply has become capacitors are also used in any area of a circuit to
a major concern. Placement and sizing of decaps, reduce the overall impact of electrical noise.
effective utilization of on-chip whitespace, resonant Typically, designs use NMOS decaps between
free voltage responses for a wide range of standard-cell blocks and NMOS+PMOS decaps
frequencies are some of the key challenges faced within the blocks. Starting at the 90nm CMOS
with the shift towards deep submicron regime. technology node, the traditional decap designs may
Decoupling capacitors are used to reduce unwanted no longer be suitable due to increased concerns
AC signals riding on DC supply circuits and also in regarding thin-oxide gate leakage and electrostatic
places in a circuit where AC signals need to be discharge (ESD) reliability. This thesis investigates
eliminated. These are usually placed between the DC new decap design approaches that address gate
supply and the ground of the circuit or directly across leakage and ESD. A cross-coupled design is
another component. Decoupling capacitors known as described that has been recently introduced by cell
“charge reservoirs” are placed between power and library developers to handle ESD problems. Three
ground lines to maintain low target impedance and to modifications of the cross-coupled design are
reduce the noise in power distribution network. Low introduced here and the tradeoffs among transient
impedance and resonant free response are two response, gate leakage and ESD performance are
requirements for maintaining power and signal analyzed. The modifications offer designers greater
integrity of the PDS. Power distribution system flexibility in decoupling capacitor design for 90nm
(PDS) spans different levels of hierarchy consisting and below. To improve the power-grid noise
of voltage regulator module, power distribution reduction capability in the areas between blocks, two
network on board, on package and on-chip. versions of a switched-decap design are proposed.
the power distribution system (PDS). Decaps acts as One provides excellent decap performance but
a local source of energy for a short period. With the consumes large power, whereas the other saves
scaling of CMOS technologies the power supply power but suffers from excessive delay. A novel low-
voltage is lowered, clock frequency has gone up, and power voltage regulator using switched decaps is
more functionality is integrated on-chip resulting in proposed to better balance performance and power
higher simultaneous switching noise (SSN). As a consumption. Decoupling capacitors (decap) are
result signal integrity of on-chip power supply has often used to filter out noise in the power distribution
become a major concern. Placement and sizing of system (PDS). Decaps acts as a local source of
decaps, effective utilization of on-chip whitespace, energy for a short period. With the scaling of CMOS
resonant free voltage responses for a wide range of technologies the power supply voltage is lowered,
frequencies are some of the key challenges faced clock frequency has gone up, and more functionality
with the shift towards deep submicron regime. is integrated on-chip resulting in higher simultaneous
Decoupling capacitors are used to reduce unwanted switching noise (SSN). As a result signal integrity of
AC signals riding on DC supply circuits and also in on-chip power supply has become a major concern.
places in a circuit where AC signals need to be Placement and sizing of decaps, effective utilization
eliminated. These are usually placed between the DC of on-chip whitespace, resonant free voltage
supply and the ground of the circuit or directly across responses for a wide range of frequencies are some of
another component. Decoupling capacitors known as the key challenges faced with the shift towards deep
“charge reservoirs” are placed between power and submicron regime.
ground lines to maintain low target impedance and to 1.1 How a decoupling capacitor works?
reduce the noise in power distribution network. Low A decoupling capacitor serves as a storage device for
impedance and resonant free response are two small amounts of energy. In situations like the one
requirements for maintaining power and signal mentioned above, in which a device’s output must
integrity of the PDS. Power distribution system fluctuate current or voltage levels without putting
(PDS) spans different levels of hierarchy consisting strain on its power supply, a decoupling capacitor is
of voltage regulator module, power distribution fastened to the device in between its output and
network on board, on package and on-chip [1]. power supply in order to buffer any changes that
Histroy: occur. At high frequencies, a decoupling capacitor is
On-chip decoupling capacitors (decaps) are widely able to maintain power levels to a device’s output
used to reduce power supply noise. Capacitors play a while the device’s power supply has time to adjust t
critical role in the stable operation of digital the changes.
electronics by protecting sensitive microchips from
noise on the power signal which can cause
anomalous behaviors. Capacitors used in this
application are called decoupling capacitors and
should be placed as close as possible to each
microchip to be most effective, as all circuit traces

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ELECTRONICS AND COMMUNICATION
reduced with low inductance surface mount ceramic
capacitors connected directly to the power supply
pins of the IC. All decoupling capacitors must
connect directly to a low impedance ground plane in
order to be effective. Short traces or via are required
for this connection to minimize additional series
inductance. Ferrite beads (nonconductive ceramics
manufactured from the oxides of nickel, zinc,
manganese, or other compounds) are also useful for
decoupling in power supply filters.

Figure.1: Decoupling capacitor

1.2 What is proper decoupling and why is it

necessary

Most ICs suffer performance degradation of some

type if there is ripple and noise on the power supply
pins. A digital IC will incur a reduction in its noise
margin and a possible increase in clock jitter. For
high performance digital ICs, such as
microprocessors and FPGAs, the specified tolerance
on the supply (±5%, for example) includes the sum of
the dc error, ripple, and noise. The digital device will
meet specifications if this voltage remains within the
tolerance. The traditional way to specify the
sensitivity of an analog IC to power supply variations Graph 1: Power Supply Rejection vs. Frequency
is the power supply rejection ratio (PSRR). For an For the AD8099 High Performance Op Amp
amplifier, PSRR is the ratio of the change in output
voltage to the change in power supply voltage, At low frequencies (<100 kHz), ferrites are inductive;
expressed as a ratio (PSRR) or in dB (PSR). thus they are useful in low-pass LC filters. Above
PSRR can be referred to the output (RTO) or referred 100 kHz, ferrites becomes resistive (high Q). Ferrite
to the input (RTI). The RTI value is equal to the RTO impedance is a function of material, operating
value divided by the gain of the amplifier. Graph 1 frequency range, dc bias current, number of turns,
shows how the PSR of a typical high performance size, shape, and temperature. The ferrite beads may
amplifier (AD8099) degrades with frequency at not always be necessary, but they will add extra high
approximately 6 dB/octave (20 dB/decade). Curves frequency noise isolation and decoupling, which is
are shown for both the positive and negative supply. often desirable. Possible caveats here would be to
Although 90 dB at dc, the PSR drops rapidly at verify that the beads never saturate, especially when
higher frequencies where more and more unwanted op amps are driving high output currents. When a
energy on the power line will couple to the output ferrite saturates it becomes nonlinear and loses its
directly. Therefore, it is necessary to keep this high filtering properties. Note that some ferrites, even
frequency energy from entering the chip in the first before full saturation occurs, can be nonlinear.
place. This is generally done with a combination of Therefore, if a power stage is required to operate with
electrolytic capacitors (for low frequency a low distortion output, the ferrite should be checked
decoupling), ceramic capacitors (for high frequency in a prototype if it is operating near this saturation
decoupling), and possibly ferrite beads. Power supply region.
rejection of data converters and other analog and
mixed-signal circuits may or may not be specified on 2. ON CHIP DECOUPLING CAPACITOR
the data sheet. However, it is very common to show As integrated circuit (IC) technology scales, more
recommended power supply decoupling circuits in and more transistors are being placed within a single
the applications section of the data sheet for chip, while the clock frequency continues to increase
practically all linear and mixed-signal ICs [3]. into the gigahertz range. The result is that large
Low frequency noise requires larger electrolytic transient currents are drawn from the power supply
capacitors which act as charge reservoirs to transient rails in just a few hundred picoseconds in modern
currents. High frequency power supply noise is best custom and application-specific integrated circuit

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ELECTRONICS AND COMMUNICATION
(ASIC) chips. Meanwhile, the supply voltage is To illustrate the IR drop, all the nodes in the power
scaled with technology to reduce overall power grid are initially charged to VDD with no activity in
consumption, and as a consequence, the circuitry the circuit. As the second inverter starts to switch, the
becomes more prone to power-supply noise. The wire resistance along the VDD line creates voltage
management and regulation of the quality of the on- drops as current flows from the external voltage
chip power supply is a major challenge. The power source towards the second inverter. Similarly, the
grid, which provides VDD and VSS (or ground) ground grid is subject to the same type of problem
signals throughout the chip, experiences fluctuations when the outputs of the buffers switch low, except
in value due to a variety of noise sources. If the that the voltage level of the ground line will increase.
supply voltage noise or variation is excessively large, This is sometimes referred to as ground bounce. In
it may lead to problems such as delay variation, practice, IR drop can be caused by simultaneous
timing unpredictability, or even improper switching of clock buffers, bus drivers, memory
functionality. A commonly used metric, noise budget, decoder drivers, and so on, when there is high
is defined as the maximum allowable noise activity in the circuit. These simultaneous switching
amplitude. Typically, it is required to keep the power activities can happen anywhere on the chip. Thus, all
supply noise within a certain percentage (e.g., 10%) regions in the chip are susceptible to IR drop. In a
of the nominal supply voltage VDD. Namely, 10% of wire-bond (e.g., dual-inline) package, the supply
VDD – VSS is typically the noise budget, a rule-of- voltage level remains relatively high at the periphery
thumb used in the industry. Circuit designers must of chip where the voltage supply I/O pads are
ensure that the chip operates correctly if the located, and drops noticeably at the centre of the
maximum voltage difference between VDD and VSS chip. In contrast, in a flip-chip (or ball-grid array)
is 10% or smaller than the nominal value [2]. package, the centre of the die has rather high voltage
In today’s advanced deep-submicron (DSM) level, whereas the periphery of the die experiences
technology, the power grid noise is due to two main larger IR drops.
issues: A common technique for reducing power supply
(1) As the power lines made of metal wires become noise and keeping the noise within the noise budget is
thinner, the wire resistance R increases. When logic through the use of on-chip decoupling capacitors
gates switch and a current I flow through the power (decaps). Decaps are essentially capacitors that hold a
lines to deliver charge to the gates, the voltage drop reservoir of charge and are placed close to the power
∆V at the gates is ∆V1 = IR⋅. This type of power- pads and near any large drivers. When large drivers
supply noise is known as IR drop. switch, the decaps provide instantaneous current to
(2) Due to package pin inductance and thin- the drivers to reduce IR drop and Ldi/dt effects, and
interconnect inductance, the power lines experience hence keep the supply voltage relatively constant. As
inductance effect when the current flow changes with shown in Figure 2, the on-chip decap delivers current
respect to time. This second source of voltage drop is to charge up the load capacitance of the second
given by ∆V2 =IR+ L dI/dt. The two power supply inverter when it switches. The supply voltage level is
noise components are illustrated in Figure 2, which relatively constant at the inverter tap point since the
depicts two inverters connected to an off-chip voltage decap is nearby, so ∆V is minimal.[4]
supply through the on-chip power grid. Considering
the two components together, the overall voltage 2.1 On chip decoupling capacitor using NMOS &
drop ∆V at any point in the power grid. PMOS
The concept of the proposed on-chip decoupling
capacitors with series resistors and ideal switches is
shown in Fig.3.-(a). In order to change the ESR of
on-chip decoupling capacitors, resistors and switches
are connected to the decoupling capacitors
additionally. Fig.3-(b) shows also the proposed
scheme of on-chip decoupling capacitors in a CMOS
process. The proposed scheme has NMOS capacitors
and PMOS switches that can be controlled by digital
bit of the ESR controller. In order to control the total
resistance of ESR linearly, the resistance of their
parallel combination should be an arithmetical series.
As the result, sizes of PMOS switch can be decide
[2].

Figure 2 : Use of decoupling capacitor for power

grid.

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(a) (b)

Figure 3 (a) Conceptual scheme of on-chip Figure 4 : Decoupling capacitor implemented using
decoupling capacitors with series resistors and an NMOS device.
ideal switches. While satisfying ESD reliability and gate leakage
(b) The proposed scheme of on-chip limitations, decap designs must also meet the
decoupling capacitors in a CMOS process transient performance requirements. Since a 90nm
process (or below) usually provides the capability of
2.2 Decoupling capacitor for NMOS running at gigahertz frequencies, the decap must
A standard decap is usually made from NMOS respond in the order of a hundred picoseconds.
transistors in a CMOS process. As shown in Figure 4, 2.3 Cross-Coupled Decap
the gate of the NMOS transistor is connected to Knowing that the standard N+P decap design for
VDD, whereas source, drain and substrate of the standard cells may no longer be suitable for 90nm
transistor are tied to VSS. This approach is technology due to increased ESD risk, a new cross-
considered effective because the thin-oxide coupled decap design has been proposed to address
capacitance of the transistor gate provides a higher this issue. In the new cross coupled design (Figure 5),
capacitance than any other oxide capacitance the drain of the PMOS connects to the gate of the
available in a standard CMOS fabrication process. NMOS, whereas the drain of the NMOS is tied to the
For this MOS decap, the first-order calculation of the gate of the PMOS.
capacitance is WLCOX, where W is the transistor
width, L is the transistor length, and COX is the
oxide capacitance per unit area. Accurate capacitance
model needs to include the parasitic fringing and
overlap capacitance of the transistor. At the 90nm
technology node, the oxide thickness of a transistor is
reduced to roughly 2.0nm or less. The thin oxide
causes two new problems possible electrostatic
discharge (ESD) induced oxide breakdown and gate
tunneling leakage . Potential ESD oxide breakdown
increases the likelihood that an IC will be
permanently damaged during an ESD event, and
hence raises a reliability concern. Higher gate
tunneling leakage increases the total static power
consumption of the chip. As technology scales
further down, with a thinner oxide, the result is an
Figure 5 : Cross-coupled decap schematic
even higher ESD risk and more gate leakage. The
standard decap design using NMOS transistors
From the layout perspective, this cross-coupled
experiences these two problems and therefore
circuit can be seen simply as a terminal-swapped
becomes rather inappropriate for 90nm and below
version of the standard decap. In other words, the
[4].
decap transistor areas need not to be modified, while
only the metal wire connections are modified. Thus,

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this new design does not require additional area in control transistor needs to be large to have the
layout, compared to the standard design. Both channel resistance small since a large resistance will
transistors in this design are still in the linear region. reduce the transient response of the decap. When in
In the standard decap design, the gates of the power saving mode, the Ctrl signal is turned low so
transistors are directly connected to either VDD or that the control transistor operates in the sub
VSS, depending on the transistor type. In this case, threshold regime. The node V_GND can be
the gate of the NMOS device is connected to VDD considered a virtual ground (floating), where the
through the channel resistance of the PMOS device. voltage at V_GND can be determined by the series
Similarly, the gate of the PMOS device is tied the resistance of Reff of the decap and the channel
channel resistance of the NMOS device and then resistance of the control transistor. In this
connected to VSS. The added channel resistance to configuration, the gate leakage saving is projected to
the gate provides the input resistance Rin for ESD be 99% in a 70nm process [4].
protection. The input resistance can help to limit the The basic idea of the gated decap is from multi-
maximum current flow to the decap so that the threshold CMOS (MTCMOS). The control transistor
voltage seen from the gate of the decap is also limited comes from the concept of the sleep transistor in
[1]. MTCMOS. As expected, the control transistor should
2.4 Gate Decouping have a high VT to keep the sub threshold leakage
A new decap structure that saves gate leakage. The small. The largest challenge of this gated decap
structure is called gated decap, as shown in Figure 6. would be the proper selection of the Ctrl signal. At
A control transistor is inserted between the standard the top level, the Ctrl signal can be driven by the
NMOS-only decap and the VSS line. The source and hardware/software interface. When there is no
drain of the decap are connected to the source of the activity in the system, the operating system
control transistor, making the node a virtual ground (software) will set up the signal to force the chip into
(V_GND). The drain of the control transistor is tied power saving or standby mode. From the hardware
to the real VSS. As shown in Figure the substrate of architectural level, the Ctrl signal can be managed by
the decap is still attached to VSS. There are two some self-predictive architecture. At the circuit level,
major components in gate leakage: leakage current it is desired that the gated decap is self-maintained,
from gate to channel (Igc), and from gate to substrate and no external circuitry is required to control it on or
(Igb). The current Igc can be partitioned into two: off. In that case, it may need to have a special clock,
leakage current from gate to source (Igcs) and from as shown in Figure 6 Before the regular clock rises,
gate to drain (Igcd) . The amount of gate leakage the Ctrl signal can be set high to allow some setup
from gate to substrate Igb is roughly 10x smaller than time for the decap to fully setup. When the regular
the leakage from gate to channel Igc . Thus, the clock falls, the Ctrl signal can also fall
substrate of the decap does not need to be tied simultaneously to save power. The time period when
through the control transistor, and the leakage current the Ctrl signal is low can be considered as the power
Igb is neglected. saving period.
3. CONCLUSIONS AND FUTURE SCOPE
With this system capacitor used to decouple one
part of an electric network from another. As
technology scales further into the deep submicron
regime, with increasing clock frequency and
decreasing supply voltage, maintaining the quality of
power supply becomes a critical issue. On-chip
power supply noise, due to IR drop and Ldi/dt
effects, has a great impact on delay variation, and
may even cause improper functionality. Power supply
noise can be reduced by placing decoupling
capacitors close to power pads and large drivers
throughout the power distribution system. Decaps
provide instantaneous current to the switching drivers
and keep the power supply within certain noise
budgets.
A number of issues regarding decoupling capacitors
Figure.6: Basic gate schematic. will have to be addressed in the near future. First,
There are two modes of operation of the circuit: knowing that the thin-oxide decaps leak a significant
active mode and power saving mode. When in the amount of current in 90nm and below, it is important
active mode, the Ctrl signal of the control transistor is to place only the necessary amount of decaps in a
turned high. The gated decap operates almost like the certain design to avoid overdesign. The use of thick-
standard decap, except that there is a small channel oxide decaps may not solve the issue completely
resistance of the control transistor. The size of the because the effective capacitance is much less for

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thick-oxide devices and the total free area for decaps
is limited. Also, the active decaps provide better
noise reduction performance but at a cost of
increased standby power requirement, compared to
the passive decaps. Therefore, to determine the
optimal number of thick-oxide, thin-oxide and active
decaps to be placed into a design remains a
challenge.
4. APPLICATIONS
Decoupling capacitors are often used in devices that
have several settings, such as power tools, hair
dryers, and conventional ovens. They allow a device
to switch back and forth between varying settings,
such as speed or temperature, before the device’s
power supply is able to maintain that setting. Devices
could still have varying settings without a decoupling
capacitor, but the effect would not be instantaneous
and the user would have to wait for the power supply
to adjust itself to the new setting.
5. ADVANTAGES
Decoupling capacitors are advantageous because
they are small and hardly noticeable, do not require
any additional energy, and allow devices to change
between various settings instantaneously.
Decoupling capacitors also prevent damage to the
power supply from occurring by buffering any
fluctuations that occur in the device’s output. This is
especially true in devices that contain a loop-back
mechanism that induces unused energy from the
device’s output back into the device’s input.
6. REFERENCES
[1] N. Na; T. Budell, C. Chiu, E. Tremble, and
I Wemple, “The Effects of On-Chip and Package
Decoupling Capacitors and an Efficient ASIC
Decoupling Methodology,” Proceedings of Electronic
Components and Technology (ECTC '04), Volume 1,
pp. 556-567, June 2004.
[2] H. Su, S. S. Sapatnekar, and S. R. Nassif,
“Optimal Decoupling Capacitor Sizing and
Placement for Standard-Cell Layout Designs,” IEEE
Transactions on Computer-Aided Design of
Integrated Circuits and Systems, Volume 22, Issue 4,
pp. 428-436, April 2003.
[3] D. A. Hodges, H. G. Jackson and R. A. Saleh,
Analysis and Design of Digital Integrated Circuits in
Deep Submicron Technology, 3rd Ed, McGraw-Hill,
2004.
[4] J. Chia, “Design, Layout and Placement of On-
Chip Decoupling Capacitors in IP Blocks”, M.A.Sc
Thesis, University of British Columbia, 2004.

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