TLV 733 P

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TLV733P
SBVS235C – OCTOBER 2014 – REVISED JULY 2019
TLV733P Capacitor-Free, 300-mA, Low-Dropout Regulator

in 1-mm × 1-mm X2SON Package
1 Features 3 Description
•
1 Input Voltage Range: 1.4 V to 5.5 V The TLV733 series of low-dropout linear regulators
(LDOs) are ultra-small, low quiescent current LDOs
• Stable Operation With or Without Capacitors that can source 300 mA with good line and load
• Foldback Overcurrent Protection transient performance. These devices provide a
• Packages: typical accuracy of 1%.
– 1.0-mm × 1.0-mm X2SON (4) The TLV733 series is designed with a modern
– SOT-23 (5) capacitor-free architecture to ensure stability without
an input or output capacitor. The removal of the
• Very Low Dropout: 125 mV at 300 mA (3.3 VOUT)
output capacitor allows for a very small solution size,
• Accuracy: 1% typical, 1.4% maximum and can eliminate inrush current at startup. However,
• Low IQ: 34 µA the TLV733 series is also stable with ceramic output
• Available in Fixed-Output Voltages: capacitors if an output capacitor is necessary. The
TLV733 also provides foldback current control during
1.0 V to 3.3 V
device power-up and enabling if an output capacitor
• High PSRR: 50 dB at 1 kHz is used. This functionality is especially important in
• Active Output Discharge battery-operated devices.
The TLV733 provides an active pull-down circuit to
2 Applications quickly discharge output loads when disabled.
• Tablets The TLV733 series is available in standard DBV
• Smartphones (SOT-23) and DQN (X2SON) packages.
• Notebook and Desktop Computers
Device Information(1)
• Portable Industrial and Consumer Products
PART NUMBER PACKAGE BODY SIZE (NOM)
• WLAN and Other PC Add-On Cards
SOT-23 (5) 2.90 mm × 1.60 mm
• Camera Modules TLV733P
X2SON (4) 1.00 mm × 1.00 mm
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Typical Application Circuit Dropout Voltage vs Output Current

180
VOUT = 3.3 V
IN OUT 160 VOUT = 1.8 V
CIN TLV733 COUT 140
EN GND 120
Optional Optional
VDO (mV)
ON 100
OFF 80
60
40
20
0
0 30 60 90 120 150 180 210 240 270 300
IOUT (mA) D020
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV733P
SBVS235C – OCTOBER 2014 – REVISED JULY 2019 www.ti.com
Table of Contents
1 Features .................................................................. 1 8 Application and Implementation ........................ 16
2 Applications ........................................................... 1 8.1 Application Information............................................ 16
3 Description ............................................................. 1 8.2 Typical Applications ............................................... 18
4 Revision History..................................................... 2 9 Power Supply Recommendations...................... 20
5 Pin Configuration and Functions ......................... 4 10 Layout................................................................... 20
6 Specifications......................................................... 5 10.1 Layout Guidelines ................................................. 20
6.1 Absolute Maximum Ratings ...................................... 5 10.2 Layout Examples................................................... 20
6.2 ESD Ratings.............................................................. 5 11 Device and Documentation Support ................. 21
6.3 Recommended Operating Conditions....................... 5 11.1 Device Support .................................................... 21
6.4 Thermal Information .................................................. 5 11.2 Documentation Support ........................................ 21
6.5 Electrical Characteristics........................................... 6 11.3 Receiving Notification of Documentation Updates 21
6.6 Typical Characteristics .............................................. 7 11.4 Community Resources.......................................... 21
7 Detailed Description ............................................ 13 11.5 Trademarks ........................................................... 21
7.1 Overview ................................................................. 13 11.6 Electrostatic Discharge Caution ............................ 21
7.2 Functional Block Diagram ....................................... 13 11.7 Glossary ................................................................ 22
7.3 Feature Description................................................. 14 12 Mechanical, Packaging, and Orderable
7.4 Device Functional Modes........................................ 15 Information ........................................................... 22
4 Revision History
Changes from Revision B (November 2015) to Revision C Page
• Changed description of EN pin from 0.9 V to VEN(HI) and from 0.35 V to VEN(LO) .................................................................. 4
• Deleted typical specifications from VEN(HI) and VEN(LO) parameters ....................................................................................... 6
• Added maximum specification to ILIM parameter ................................................................................................................... 6
• Changed Shutdown and Output Enable title from Shutdown and changed first paragraph................................................. 14
• Added DBV package to last paragraph of Power Dissipation section.................................................................................. 17
• Added (3) to Device Nomenclature table ............................................................................................................................. 21
Changes from Revision A (December 2014) to Revision B Page
• Changed Low Dropout Feature bullet value from 122 mV to 125 mV to match value in Electrical Characteristics ............. 1
• Changed VOUT labels on front page plot ................................................................................................................................. 1
• Changed min junction temperature value from –55 to –40 in Absolute Maximum Ratings table .......................................... 5
• Changed max junction temperature value from 160 to 150 in Absolute Maximum Ratings table ........................................ 5
• Changed max storage temperature value from 150 to 160 in Absolute Maximum Ratings table.......................................... 5
• Added test condition to line regulation parameter in Electrical Characteristics table............................................................. 6
• Changed unit for line regulation parameter from mV/V to mV ............................................................................................... 6
• Added test condition to load regulation parameter in Electrical Characteristics table .......................................................... 6
Changes from Original (October 2014) to Revision A Page
• Changed top page header information for data sheet to reflect device family instead of individual devices......................... 1
• Changed Input Voltage Range Features bullet to be first in list ............................................................................................. 1
• Changed Typical Application Circuit on front page; corrected error in optional capacitor identification ................................ 1
• Changed format of I/O column contents and order of packages in Pin Functions table ....................................................... 4
• Moved storage temperature range specification to Absolute Maximum Ratings table ......................................................... 5
• Changed Handling Ratings table title to ESD Ratings, updated table format ........................................................................ 5
• Added new first row to the VDO parameter in the Electrical Characteristics table .................................................................. 6
2 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated
Product Folder Links: TLV733P

TLV733P
www.ti.com SBVS235C – OCTOBER 2014 – REVISED JULY 2019
• Changed condition text for Figure 34 .................................................................................................................................. 17

• Added Evaluation Module subsection ................................................................................................................................. 21
• Deleted Related Links section ............................................................................................................................................. 21
Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

TLV733P
5 Pin Configuration and Functions
DBV Package DQN Package

5-Pin SOT-23 4-Pin 1-mm × 1-mm X2SON
Top View Top View
IN EN
IN 1 5 OUT 4 3
GND 2
EN 3 4 NC
1 2
OUT GND
Pin Functions
PIN
NO.
NAME DQN DBV I/O DESCRIPTION
Enable pin. Drive EN greater than VEN(HI) to turn on the regulator.
EN 3 3 I
Drive EN less than VEN(LO) to put the LDO into shutdown mode.
GND 2 2 — Ground pin
Input pin. A small capacitor is recommended from this pin to ground.
IN 4 1 I
See the Input and Output Capacitor Selection section for more details.
NC N/A 4 — No internal connection
Regulated output voltage pin. For best transient response, use a small 1-μF
OUT 1 5 O ceramic capacitor from this pin to ground.
See the Input and Output Capacitor Selection section for more details.
The thermal pad is electrically connected to the GND node.
Thermal pad — —
Connect to the GND plane for improved thermal performance.

TLV733P
6 Specifications
6.1 Absolute Maximum Ratings
over operating junction temperature range (unless otherwise noted); all voltages are with respect to GND (1)
MIN MAX UNIT
VIN –0.3 6.0
Voltage VEN –0.3 VIN + 0.3 V
VOUT –0.3 3.6
Current IOUT Internally limited A
Output short-circuit duration Indefinite
Operating junction, TJ –40 150
Temperature °C
Storage, Tstg –65 160
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input range, VIN 1.4 5.5 V
Output range, VOUT 1.0 3.3 V
Output current, IOUT 0 300 mA
Enable range, VEN 0 VIN V
Junction temperature, TJ –40 125 °C
6.4 Thermal Information

TLV733P
THERMAL METRIC (1) DQN (X2SON) DBV (SOT-23) UNIT
4 PINS 5 PINS
RθJA Junction-to-ambient thermal resistance 218.6 228.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 164.8 151.5 °C/W
RθJB Junction-to-board thermal resistance 164.9 55.8 °C/W
ψJT Junction-to-top characterization parameter 5.6 31.4 °C/W
ψJB Junction-to-board characterization parameter 163.9 54.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 131.4 N/A °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

TLV733P
6.5 Electrical Characteristics

At operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted). All typical values at TJ = 25°C.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage 1.4 5.5 V
TJ = 25°C –1% 1%
DC output accuracy
–40°C ≤ TJ ≤ +125°C –1.4% 1.4%
VIN rising 1.3 1.4
UVLO Undervoltage lockout V
VIN falling 1.25
ΔVO(ΔVI) Line regulation ΔVI = VIN(nom) to VIN(nom) + 1 1 mV
ΔIO = 1 mA to DQN package 16
ΔVO(ΔIO) Load regulation mV
300 mA DBV package 25
VOUT = 1.1 V, –40°C ≤ TJ ≤ 85°C 460
1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤ 85°C 420
1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤ 85°C 370
1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤ 85°C 270
2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤ 85°C 260
VOUT = 0.98 ×
VDO Dropout voltage (1) VOUT(nom), VOUT = 3.3 V, –40°C ≤ TJ ≤ 85°C 125 220 mV
IOUT = 300 mA
1.2 V ≤ VOUT < 1.5 V, –40°C ≤ TJ ≤ 125°C 450
1.5 V ≤ VOUT < 1.8 V, –40°C ≤ TJ ≤ 125°C 400
1.8 V ≤ VOUT < 2.5 V, –40°C ≤ TJ ≤ 125°C 300
2.5 V ≤ VOUT < 3.3 V, –40°C ≤ TJ ≤ 125°C 290
VOUT = 3.3 V, –40°C ≤ TJ ≤ 125°C 125 270
IGND Ground pin current IOUT = 0 mA 34 60 µA
ISHDN Shutdown current VEN ≤ 0.35 V, 2.0 V ≤ VIN ≤ 5.5 V, TJ = 25°C 0.1 1 µA
f = 100 Hz 68
Power-supply VOUT = 1.8 V,
PSRR f = 10 kHz 35 dB
rejection ratio IOUT = 300 mA
f = 100 kHz 28
Vn Output noise voltage BW = 10 Hz to 100 kHz, VOUT = 1.8 V, IOUT = 10 mA 120 µVRMS
EN pin high voltage
VEN(HI) 0.9 V
(enabled)
EN pin low voltage
VEN(LO) 0.35 V
(disabled)
IEN EN pin current VEN = 5.5 V 0.01 µA
Time from EN assertion to 98% × VOUT(nom), VOUT = 1.0
250
V, IOUT = 0 mA
tSTR Startup time µs
Time from EN assertion to 98% × VOUT(nom), VOUT = 3.3
800
V, IOUT = 0 mA
Pull-down resistor VIN = 2.3 V 120 Ω
ILIM Output current limit 360 700 mA
Short-circuit current VOUT shorted to GND, VOUT = 1.0 V 150
IOS mA
limit VOUT shorted to GND, VOUT = 3.3 V 170
Shutdown, temperature increasing 160
Tsd Thermal shutdown °C
Reset, temperature decreasing 140
(1) Dropout voltage for the TLV73310P is not valid at room temperature. The device engages undervoltage lockout (VIN < UVLOFALL) before
the dropout condition is met.

TLV733P
6.6 Typical Characteristics

at operating temperature range (TJ = –40°C to +125°C), VIN = VOUT(nom) + 0.5 V or 2.0 V (whichever is greater), IOUT = 1 mA,
VEN = VIN, and CIN = COUT = 1 µF (unless otherwise noted)
1.03 1.004
TJ = -40 qC TJ = -40 qC
1.02 TJ = 0 qC TJ = 0 qC
1
TJ = 25 qC TJ = 25 qC
TJ = 85 qC TJ = 85 qC
1.01 TJ = 125 qC 0.996 TJ = 125 qC
VOUT (V)
VOUT (V)
1 0.992
0.99 0.988
0.98 0.984
0.97 0.98
0.96 0.976
0 50 100 150 200 250 300 0 50 100 150 200 250 300
Current (mA) D001
Current (mA) D005
TLV73310PDBV TLV73310PDQN
Figure 1. 1.0-V Load Regulation vs IOUT and Temperature Figure 2. 1.0-V Load Regulation vs IOUT and Temperature
1.816 1.8
TJ = -40 qC TJ = -40 qC
1.808 TJ = 0 qC 1.797 TJ = 0 qC
TJ = 25 qC TJ = 25 qC
TJ = 85 qC TJ = 85 qC
1.8 TJ = 125 qC 1.794 TJ = 125 qC
VOUT (V)
VOUT (V)
1.792 1.791
1.784 1.788
1.776 1.785
1.768 1.782
1.76 1.779
0 50 100 150 200 250 300 0 50 100 150 200 250 300
Current (mA) D002
Current (mA) D006
Figure 3. 1.8-V Load Regulation vs IO and Temperature Figure 4. 1.8-V Load Regulation vs IOUT and Temperature
3.345 3.32
TJ = -40 qC TJ = -40 qC
3.33 TJ = 0 qC 3.312 TJ = 0 qC
TJ = 25 qC TJ = 25 qC
TJ = 85 qC TJ = 85 qC
3.315 TJ = 125 qC 3.304 TJ = 125 qC
VOUT (V)
VOUT (V)
3.3 3.296
3.285 3.288
3.27 3.28
3.255 3.272
3.24 3.264
0 50 100 150 200 250 300 0 50 100 150 200 250 300
Current (mA) D003
Current (mA) D007
Figure 5. 3.3-V Load Regulation vs IOUT and Temperature Figure 6. 3.3-V Load Regulation vs IOUT and Temperature

TLV733P
Typical Characteristics (continued)

400 390
TJ = -40 qC TJ = -40 qC
360
350 TJ = 0 qC TJ = 0 qC
TJ = 25 qC 330 TJ = 25 qC
TJ = 85 qC TJ = 85 qC
300 TJ = 125 qC 300 TJ = 125 qC
270
VDO (mV)
VDO (mV)
250 240
210
200
180
150 150
120
100
90
50 60
0 30 60 90 120 150 180 210 240 270 300 0 30 60 90 120 150 180 210 240 270 300
Current (mA) D024
Current (mA) D025
Figure 7. 1.2-V Dropout Voltage vs IOUT and Temperature Figure 8. 1.2-V Dropout Voltage vs IOUT and Temperature
275 300
TJ = -40 qC TJ = -40 qC
250
TJ = 0 qC TJ = 0 qC
225 TJ = 25 qC 250 TJ = 25 qC
TJ = 85 qC TJ = 85 qC
200 TJ = 125 qC TJ = 125 qC
200
175
VDO (mV)
VDO (mV)
150
150
125
100
100
75
50 50
25
0 0
0 30 60 90 120 150 180 210 240 270 300 0 30 60 90 120 150 180 210 240 270 300
Current (mA) D008
Current (mA) D010
300 300
TJ = -40 qC TJ = -40 qC
TJ = 0 qC TJ = 0 qC
250 TJ = 25 qC 250 TJ = 25 qC
TJ = 85 qC TJ = 85 qC
TJ = 125 qC TJ = 125 qC
200 200
VDO (mV)
VDO (mV)
150 150
100 100
50 50
0 0
0 30 60 90 120 150 180 210 240 270 300 0 30 60 90 120 150 180 210 240 270 300
Current (mA) D009
Current (mA) D011

TLV733P

1.816 70
TJ = -40qC TJ = -40qC
1.814 TJ = 0qC 65 TJ = 0qC
1.812 TJ = 25qC TJ = 25qC
TJ = 85qC 60 TJ = 85qC
1.81 TJ = 125qC TJ = 125qC
55
1.808
IGND (PA)
VOUT (V)
50
1.806
45
1.804
40
1.802
1.8 35
1.798 30
1.796 25
2 2.5 3 3.5 4 4.5 5 5.5 0 30 60 90 120 150 180 210 240 270 300
VIN (V) D019
IOUT (mA) D012
TLV73318PDBV
Figure 13. 1.8-V Regulation vs VIN (Line Regulation) and Figure 14. Ground Pin Current vs IOUT and Temperature
Temperature
40 100
TJ = 25qC TJ = -40qC
35 TJ = 0qC
TJ = 25qC
30 10 TJ = 85qC
TJ = 125qC
25
ISHDN (PA)
IGND (PA)
20 1
15
10 0.1
0 0.01
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0 1 2 3 4 5 6
VIN (V) D013
VIN (V) D015
IOUT = 0 mA
Figure 15. Ground Pin Current vs VIN Figure 16. Shutdown Current vs VIN and Temperature
0.675 1
VEN(LO)
0.65 VEN(HI) 0.9
0.625 0.8
Enable Threshold (V)
0.6 0.7
0.575 0.6
VOUT (V)
0.55 0.5
0.525 0.4
0.5 0.3 TJ = -40°C
TJ = 0°C
0.475 0.2 TJ = 25°C
0.45 0.1 TJ = 85°C
TJ = 125°C
0.425 0
-40 -20 0 20 40 60 80 100 120 140 150 200 250 300 350 400 450 500 550 600 650 700
TJ (qC) Output Current (mA) D023
D014
TLV73310PDBV
Figure 17. Enable Threshold vs Temperature Figure 18. 1.0-V Foldback Current Limit vs
IOUT and Temperature

TLV733P

2 3.5
1.75 3
1.5
2.5
1.25
VOUT (V)
VOUT (V)
2
1
1.5
0.75
TJ = -40°C 1 TJ = -40°C
0.5 TJ = 0°C TJ = 0°C
TJ = 25°C TJ = 25°C
0.25 TJ = 85°C 0.5 TJ = 85°C
TJ = 125°C TJ = 125°C
0 0
150 200 250 300 350 400 450 500 150 200 250 300 350 400 450 500
Output Current (mA) D021
Output Current (mA) D022
TLV73318PDBV TLV73333PDBV
Figure 19. 1.8-V Foldback Current Limit vs Figure 20. 3.3-V Foldback Current Limit vs
IOUT and Temperature IOUT and Temperature
80 10
No Output Capacitor VOUT = 1 V
70 1-PF Output Capacitor VOUT = 1.8 V
VOUT = 3.3 V
60
Noise Density (PV/—Hz)
1
50
PSRR (dB)
40
30 0.1
20
10
0.01
0 0.005
10 100 1k 10k 100k 1M 10 100 1k 10k 100k 1M
Frequency (Hz) D017
Frequency (Hz) D016
TLV73318PDQN, IOUT = 300 mA IOUT = 300 mA
Figure 21. Power-Supply Rejection Ratio vs Frequency Figure 22. Output Spectral Noise Density
VIN (2 V/div)
VIN (2 V/div)
VOUT (1 V/div, VOUT (1 V/div,

AC Coupled) AC Coupled)
Time (20 µs/div) Time (20 µs/div)

TLV73318PDBV, IOUT = 10 mA, 1-µF output capacitor TLV73318PDBV, IOUT = 300 mA, 1-µF output capacitor
Figure 23. Line Transient Figure 24. Line Transient

TLV733P

VOUT (200 mV/div, VOUT (200 mV/div,

AC Coupled) AC Coupled)
ILOAD (100 mA/div) ILOAD (100 mA/div)

TLV73310PDBV, VIN = 2.0 V, 1-µF output capacitor, output TLV73310PDBV, VIN = 2.0 V, no output capacitor, output current
current slew rate = 0.25 A/µs slew rate = 0.25 A/µs
Figure 25. 1.0-V, 50-mA to 300-mA Load Transient Figure 26. 1.0 V, 50-mA to 300-mA Load Transient
VOUT (100 mV/div, VOUT (100 mV/div,

AC Coupled) AC coupled)
ILOAD (100 mA/div)
ILOAD (200 mA/div)

TLV73333PDBV, VIN = 3.8 V,1-µF output capacitor, output current TLV73333PDBV, VIN = 3.8 V, no output capacitor, output current
slew rate = 0.25 A/µs slew rate = 0.25 A/µs
Figure 27. 3.3 V, 50-mA to 300-mA Load Transient Figure 28. 3.3 V, 50-mA to 300-mA Load Transient
VEN (500 mV/div)
VIN (1 V/div)
VOUT (1 V/div)
ILOAD (200 mA/div)

VOUT (500 mV/div)

TLV73318PDBV, RL = 6.2 Ω, VEN = VIN, 1-µF output capacitor TLV73318PDBV, RL = 6.2 Ω, 1-µF output capacitor
Figure 29. VIN Power-Up and Power-Down Figure 30. Startup with EN

TLV733P

VOUT (500 mV/div)
VEN (500 mV/div)
VOUT (500 mV/div)
ILOAD (200 mA/div)

TLV73318PDBV, IOUT = 300 mA, 1-µF output capacitor TLV73318PDBV, 1-µF output capacitor
Figure 31. Shutdown Response with Enable Figure 32. Foldback Current Limit Response

TLV733P
7 Detailed Description
7.1 Overview
The TLV733 belongs to a new family of next-generation, low-dropout regulators (LDOs). These devices consume
low quiescent current and deliver excellent line and load transient performance. These characteristics, combined
with low noise, good PSRR with low dropout voltage, make this family of devices ideal for portable consumer
applications.
This family of regulators offers foldback current limit, shutdown, and thermal protection. The operating junction
temperature for this family of devices is –40°C to 125°C.
7.2 Functional Block Diagram
IN OUT
Current
Limit
Thermal
Shutdown
UVLO
120 W
EN Bandgap
Logic
TLV733
GND

TLV733P
7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)
The TLV733 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is
greater than the rising UVLO voltage, UVLORISE. This circuit ensures that the device does not exhibit any
unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry.
During UVLO disable, the output is connected to ground with a 120-Ω pulldown resistor.
7.3.2 Shutdown and Output Enable

The enable pin (EN) is active high. Enable the device by forcing the EN pin to exceed VEN(HI). Turn off the device
by forcing the EN pin to drop below VEN(LO). If shutdown capability is not required, connect EN to IN. There is no
internal pulldown resistor connected to the EN pin.
The TLV733 has an internal pulldown MOSFET that connects a 120-Ω resistor to ground when the device is
disabled. The discharge time after disabling depends on the output capacitance (COUT) and the load resistance
(RL) in parallel with the 120-Ω pulldown resistor. The time constant is calculated in Equation 1:
120 · RL
t= · COUT
120 + RL (1)
7.3.3 Internal Foldback Current Limit

The TLV733 has an internal foldback current limit that protects the regulator during fault conditions. The current
allowed through the device is reduced as the output voltage falls. When the output is shorted, the LDO supplies a
typical current of 150 mA. The output voltage is not regulated when the device is in current limit. In this condition,
the output voltage is the product of the regulated current and the load resistance. When the device output is
shorted, the PMOS pass transistor dissipates power [(VIN – VOUT) × IOS] until thermal shutdown is triggered and
the device turns off. After the device cools down, the internal thermal shutdown circuit turns the device back on.
If the fault condition continues, the device cycles between current limit and thermal shutdown. See the Thermal
Information table for more details.
The foldback current-limit circuit limits the current allowed through the device to current levels lower than the
minimum current limit at nominal VOUT current limit (ILIM) during startup. See Figure 18 to Figure 20 for typical
foldback current limit values. If the output is loaded by a constant-current load during startup, or if the output
voltage is negative when the device is enabled, then the load current demanded by the load may exceed the
foldback current limit and the device may not rise to the full output voltage. For constant-current loads, disable
the output load until the TLV733 has fully risen to its nominal output voltage.
The TLV733 PMOS pass element has an intrinsic body diode that conducts current when the voltage at the OUT
pin exceeds the voltage at the IN pin. Do not force the output voltage to exceed the input voltage because
excessively high current may flow through the body diode.
7.3.4 Thermal Shutdown

Thermal shutdown protection disables the output when the junction temperature rises to approximately 160°C.
Disabling the device eliminates the power dissipated by the device, allowing the device to cool. When the
junction temperature cools to approximately 140°C, the output circuitry is again enabled. Depending on power
dissipation, thermal resistance, and ambient temperature, the thermal protection circuit may cycle on and off.
This cycling limits regulator dissipation, protecting it from damage as a result of overheating.
Activating the thermal shutdown feature usually indicates excessive power dissipation as a result of the product
of the (VIN –VOUT) voltage and the load current. For reliable operation, limit junction temperature to 125°C
maximum. To estimate the margin of safety in a complete design, increase the ambient temperature until the
thermal protection is triggered; use worst-case loads and signal conditions.
The TLV733 internal protection circuitry protects against overload conditions but is not intended to be activated in
normal operation. Continuously running the TLV733 into thermal shutdown degrades device reliability.

TLV733P
7.4 Device Functional Modes

7.4.1 Normal Operation
The device regulates to the nominal output voltage under the following conditions:
• The input voltage has previously exceeded the UVLO rising voltage and has not decreased below the UVLO
falling threshold.
• The input voltage is greater than the nominal output voltage added to the dropout voltage.
• The enable voltage has previously exceeded the enable rising threshold voltage and not decreased below the
enable falling threshold.
• The output current is less than the current limit.
• The device junction temperature is less than the thermal shutdown temperature.
7.4.2 Dropout Operation

If the input voltage is lower than the nominal output voltage plus the specified dropout voltage, but all other
conditions are met for normal operation, the device operates in dropout mode. In this condition, the output
voltage is the same the input voltage minus the dropout voltage. The transient performance of the device is
significantly degraded because the pass device is in a triode state and no longer controls the current through the
LDO. Line or load transients in dropout may result in large output voltage deviations.
7.4.3 Disabled
The device is disabled under the following conditions:
• The input voltage is less than the UVLO falling voltage, or has not yet exceeded the UVLO rising threshold.
• The enable voltage is less than the enable falling threshold voltage or has not yet exceeded the enable rising
threshold.
• The device junction temperature is greater than the thermal shutdown temperature.
When the device is disabled, the active pulldown resistor discharges the output.
Table 1 shows the conditions that lead to the different modes of operation.
Table 1. Device Functional Mode Comparison

PARAMETER
OPERATING MODE
VIN VEN IOUT TJ
VIN > VOUT(nom) + VDO
Normal mode VEN > VEN(HI) IOUT < ILIM TJ < 160°C
and VIN > UVLORISE
Dropout mode UVLORISE < VIN < VOUT(nom) + VDO VEN > VEN(HI) IOUT < ILIM TJ < 160°C
Disabled mode
(any true condition VIN < UVLOFALL VEN < VEN(LO) — TJ > 160°C
disables the device)

TLV733P
8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information

8.1.1 Input and Output Capacitor Selection
The TLV733 uses an advanced internal control loop to obtain stable operation both with and without the use of
input or output capacitors. Dynamic performance is improved with the use of an output capacitor, and may be
improved with an input capacitor. An output capacitance of 0.1 μF or larger generally provides good dynamic
response. Use X5R- and X7R-type ceramic capacitors because these capacitors have minimal variation in value
and equivalent series resistance (ESR) over temperature.
Although an input capacitor is not required for stability, increased output impedance from the input supply may
compromise the performance of the TLV733. Good analog design practice is to connect a 0.1-µF to 1-µF
capacitor from IN to GND. This capacitor counteracts reactive input sources and improves transient response,
input ripple, and PSRR. Use an input capacitor if the source impedance is greater than 0.5 Ω. Use a higher-value
capacitor if large, fast, rise-time load transients are anticipated, or if the device is located several inches from the
input power source.
Figure 33 shows the transient performance improvements with an external 1-µF capacitor on the output versus
no output capacitor. The data in this figure are taken with an increasing load step from 50 mA to 300 mA, and the
peak output voltage deviation (load transient response) is measured. For low output current slew rates,
(< 0.1 A/µs), the transient performance of the device is similar with or without an output capacitor. As the current
slew rate is increased, the peak voltage deviation is significantly increased. For loads that exhibit fast current
slew rates above 0.1 A/µs, use an output capacitor. For best performance, the maximum recommended output
capacitance is 100 µF.
35
1-PF COUT
Peak Output Voltage Change (%VOUT)
30 COUT Removed
25
20
15
10
0
0.01 0.1 1
Output Load Transient Slew Rate (A/Ps) D027
TLV73333PDBV, output current stepped from 50 mA to 300 mA, output voltage change measured at positive dI/dt
Figure 33. Output Voltage Deviation vs Load Step Slew Rate
Some applications benefit from the removal of the output capacitor. In addition to space and cost savings, the
removal of the output capacitor lowers inrush current as a result of eliminating the required current flow into the
output capacitor upon startup. In these cases, take care to ensure that the load is tolerant of the additional output
voltage deviations.

TLV733P
Application Information (continued)

8.1.2 Dropout Voltage
The TLV733 uses a PMOS pass transistor to achieve low dropout. When (VIN – VOUT) is less than the dropout
voltage (VDO), the PMOS pass device is in the linear region of operation and the input-to-output resistance is the
RDS(ON) of the PMOS pass element. VDO scales approximately with output current because the PMOS device
behaves like a resistor in dropout mode. As with any linear regulator, PSRR and transient response degrade as
(VIN – VOUT) approaches dropout operation. See Figure 7 to Figure 12 for typical dropout values.
8.1.3 Power Dissipation

The ability to remove heat from the die is different for each package type, presenting different considerations in
the printed circuit board (PCB) layout. The PCB area around the device that is free of other components moves
the heat from the device to ambient air. Performance data for JEDEC high-K boards are given in the Thermal
Information table. Using heavier copper increases the effectiveness in removing heat from the device. The
addition of plated through-holes to heat-dissipating layers also improves heatsink effectiveness.
Power dissipation (PD) depends on input voltage and load conditions. PD is equal to the product of the output
current and voltage drop across the output pass element, as shown in Equation 2.
PD = (VIN – VOUT) × IOUT (2)
Figure 34 shows the maximum ambient temperature versus the power dissipation of the TLV733 in the DQN and
DBV packages. This figure assumes the device is soldered on JEDEC standard high-K layout with no airflow
over the board. Actual board thermal impedances vary widely. If the application requires high power dissipation,
having a thorough understanding of the board temperature and thermal impedances is helpful to make sure the
TLV733 does not operate continuously above a junction temperature of 125°C.
125
120 TLV733 DQN, High-K Layout
Maximum Ambient Temperature (qC)
115 TLV733 DBV, High-K Layout

110
105
100
95
90
85
80
75
70
65
60
55
0 0.03 0.06 0.09 0.12 0.15 0.18 0.21 0.24 0.27 0.3
Power Dissipation (W) D028
TLV733, high-K layout
Figure 34. Maximum Ambient Temperature vs Device Power Dissipation

TLV733P
8.2 Typical Applications

8.2.1 DC-DC Converter Post Regulation
VOUT VOUT
1.8 V 1.5 V
IN OUT
DC-DC CIN COUT

TLV733 Load
Converter 1 µF 1 µF
EN GND
ON
OFF
Figure 35. DC-DC Converter Post Regulation
8.2.1.1 Design Requirements
Table 2. Design Parameters

PARAMETER DESIGN REQUIREMENT
Input voltage 1.8 V, ±5%
Output voltage 1.5 V, ±1%
Output current 200-mA dc, 300-mA peak
Output voltage transient deviation < 10%, 1-A/µs load step from 50 mA to 200 mA
Maximum ambient temperature 85°C
8.2.1.2 Design Considerations

Input and output capacitors are required to achieve the output voltage transient requirements. Capacitance
values of 1 µF are selected to give the maximum output capacitance in a small, low-cost package.
Figure 7 shows the 1.2-V option dropout voltage. Given that dropout voltages are higher for lower output-voltage
options, and given that the 1.2-V option dropout voltage is typically less than 300 mV at 125°C, then the 1.5-V
option dropout voltage is typically less than 300 mV at 125°C.
Verify that the maximum junction temperature is not exceeded by referring to Figure 34.
8.2.1.3 Application Curve
VIN (500 mV/div)
VOUT (500 mV/div)
IOUT (100 mA/div)
Time (50 µs/div)

Figure 36. 1.8-V to 1.5-V Regulation at 300 mA

TLV733P
8.2.2 Capacitor-Free Operation from Battery Input Supply
IN OUT
TLV733
VBAT Load
EN GND
Figure 37. Capacitor-Free Operation from Battery Input Supply
8.2.2.1 Design Requirements
Table 3. Design Parameters

PARAMETER DESIGN REQUIREMENT
Input voltage 3.0 V to 1.8 V (two 1.5-V batteries)
Output voltage 1.0 V, ±1%
Input current 200 mA, maximum
Output load 100-mA dc
Maximum ambient temperature 70°C
8.2.2.2 Design Considerations

An input capacitor is not required for this design because of the low impedance connection directly to the battery.
No output capacitor allows for the minimal possible inrush current during startup, ensuring the 200-mA maximum
input current is not exceeded.
Verify that the maximum junction temperature is not exceeded by referring to Figure 34.
8.2.2.3 Application Curve
VIN (1 V/div)
VOUT (500 mV/div)
IIN (100 mA/div)
Time (50 µs/div)

Figure 38. No Inrush Startup, 3.0-V to 1.0-V Regulation

TLV733P
9 Power Supply Recommendations

Connect a low output impedance power supply directly to the IN pin of the TLV733. Inductive impedances
between the input supply and the IN pin can create significant voltage excursions at the IN pin during startup or
load transient events. If inductive impedances are unavoidable, use an input capacitor.
10 Layout
10.1 Layout Guidelines

• Place input and output capacitors as close to the device as possible.
• Use copper planes for device connections, in order to optimize thermal performance.
• Place thermal vias around the device to distribute the heat.
• Do not place a thermal via directly beneath the thermal pad of the DQN package. A via can wick solder or
solder paste away from the thermal pad joint during the soldering process, leading to a compromised solder
joint on the thermal pad.
10.2 Layout Examples

VOUT VIN
1 TLV733
4
COUT*
CIN*
2 3
GND PLANE
Represents via used for

application specific connections
*not required
Figure 39. Layout Example for the DQN Package
VIN VOUT
1 5
CIN* 2 COUT*
3 4
GND PLANE
Represents via used for

application specific connections
*not required
Figure 40. Layout Example for the DBV Package

TLV733P
11 Device and Documentation Support
11.1 Device Support

11.1.1 Development Support
11.1.1.1 Evaluation Module

An evaluation module (EVM) is available to assist in the initial circuit performance evaluation using the TLV733.
The TLV73312PEVM-643 evaluation module (and related user guide) can be requested at the Texas Instruments
website through the product folders or purchased directly from the TI eStore.
11.1.2 Device Nomenclature
Table 4. Device Nomenclature (1) (2)

PRODUCT VOUT
xx(x) is the nominal output voltage. For output voltages with a resolution of 100 mV, two digits are used
in the ordering number; otherwise, three digits are used (for example, 28 = 2.8 V; 125 = 1.25 V).
P indicates an active output discharge feature. All members of the TLV733 family will actively discharge
the output when the device is disabled.
TLV733xx(x)Pyyyz(3)
yyy is the package designator.
z is the package quantity. R is for reel (3000 pieces), T is for tape (250 pieces).
(3) indicates an alternative tape and reel orientation. 3 indicates that pin 1 is in quadrant 3. See the
Package Materials Information addendum for more information.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder on www.ti.com.
(2) Output voltages from 1.0 V to 3.3 V in 50-mV increments are available. Contact the factory for details and availability.
11.2 Documentation Support

11.2.1 Related Documentation
Texas Instruments, TLV73312PDQN-643 Evaluation Module user guide
11.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

TLV733P
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

TLV733P
PACKAGE OUTLINE
DQN0004A X2SON - 0.4 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
4215302/D 06/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
4. Features may not exist. Recommend use of pin 1 marking on top of package for orientation purposes.

TLV733P
EXAMPLE BOARD LAYOUT

4215302/D 06/2016
NOTES: (continued)
5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271) .
6. If any vias are implemented, it is recommended that vias under paste be filled, plugged or tented.

TLV733P
EXAMPLE STENCIL DESIGN

4215302/D 06/2016
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

PACKAGE OPTION ADDENDUM
www.ti.com 6-Dec-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TLV73310PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCCQ Samples
TLV73310PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCCQ Samples
TLV73310PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FG Samples
TLV73310PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FG Samples
TLV73311PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZBLW Samples
TLV73311PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZBLW Samples
TLV73311PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GR Samples
TLV73311PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GR Samples
TLV73312PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCDQ Samples
TLV73312PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCDQ Samples
TLV73312PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FI Samples
TLV73312PDQNR3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FI Samples
TLV73312PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FI Samples
TLV73315PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCFQ Samples
TLV73315PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCFQ Samples
TLV73315PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FJ Samples
TLV73315PDQNR3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FJ Samples
TLV73315PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FJ Samples
TLV73318PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCGQ Samples
TLV73318PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCGQ Samples
Addendum-Page 1
(6)
TLV73318PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FK Samples
TLV73318PDQNR3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FK Samples
TLV73318PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FK Samples
TLV73325PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCHQ Samples
TLV73325PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCHQ Samples
TLV73325PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FL Samples
TLV73325PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FL Samples
TLV733285PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZDRW Samples
TLV733285PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZDRW Samples
TLV733285PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GZ Samples
TLV733285PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GZ Samples
TLV73328PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZDQW Samples
TLV73328PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZDQW Samples
TLV73328PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GY Samples
TLV73328PDQNR3 ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GY Samples
TLV73328PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GY Samples
TLV73330PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZDMW Samples
TLV73330PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 ZDMW Samples
TLV73330PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GW Samples
TLV73330PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 GW Samples
TLV73333PDBVR ACTIVE SOT-23 DBV 5 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 VCIQ Samples
Addendum-Page 2
(6)
TLV73333PDBVT ACTIVE SOT-23 DBV 5 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 VCIQ Samples
TLV73333PDQNR ACTIVE X2SON DQN 4 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FM Samples
TLV73333PDQNT ACTIVE X2SON DQN 4 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 FM Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 3
OTHER QUALIFIED VERSIONS OF TLV733P :
• Automotive : TLV733P-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com 12-Jan-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLV73310PDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV73310PDBVT SOT-23 DBV 5 250 178.0 8.4 3.23 3.17 1.37 4.0 8.0 Q3
TLV73310PDQNR X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV73310PDQNT X2SON DQN 4 250 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q2
TLV73312PDQNR3 X2SON DQN 4 3000 180.0 9.5 1.16 1.16 0.5 4.0 8.0 Q3
Pack Materials-Page 1
Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1

Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV73310PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV73310PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV73310PDQNR X2SON DQN 4 3000 184.0 184.0 19.0
TLV73310PDQNT X2SON DQN 4 250 184.0 184.0 19.0
TLV73311PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV73311PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV73312PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV73312PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV73312PDQNR3 X2SON DQN 4 3000 184.0 184.0 19.0
TLV73315PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV73315PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV73315PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0
TLV73315PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV73318PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV73318PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV73325PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV73325PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV733285PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV733285PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV733285PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0
TLV733285PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV73328PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV73328PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV73330PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV73330PDBVR SOT-23 DBV 5 3000 210.0 185.0 35.0
TLV73330PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV73330PDBVT SOT-23 DBV 5 250 210.0 185.0 35.0
TLV73333PDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV73333PDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
PACKAGE OUTLINE
DBV0005A SCALE 4.000
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
C
3.0
2.6 0.1 C
1.75 1.45
B A
1.45 0.90
PIN 1
INDEX AREA
1 5
2X 0.95
3.05
2.75
1.9 1.9
2
4
3
0.5
5X
0.3
0.15
0.2 C A B (1.1) TYP
0.00
0.25
GAGE PLANE 0.22
TYP
0.08
8
TYP 0.6
0 TYP SEATING PLANE
0.3
4214839/F 06/2021
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3 4
(R0.05) TYP (2.6)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
SOLDER MASK METAL METAL UNDER OPENING
OPENING SOLDER MASK
EXPOSED METAL EXPOSED METAL
0.07 MAX 0.07 MIN

ARROUND ARROUND
NON SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/F 06/2021
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A SOT-23 - 1.45 mm max height
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
2 (1.9)
2X(0.95)
3 4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/F 06/2021
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

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TLV733P Capacitor-Free, 300-mA, Low-Dropout Regulator

Typical Application Circuit Dropout Voltage vs Output Current

CIN TLV733 COUT 140

Changes from Revision A (December 2014) to Revision B Page

Changes from Original (October 2014) to Revision A Page

2 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated

Product Folder Links: TLV733P

• Changed condition text for Figure 34 .................................................................................................................................. 17

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 3

5 Pin Configuration and Functions

DBV Package DQN Package

4 Submit Documentation Feedback Copyright © 2014–2019, Texas Instruments Incorporated

Product Folder Links: TLV733P

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 5

6.5 Electrical Characteristics

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Product Folder Links: TLV733P

6.6 Typical Characteristics

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 7

Typical Characteristics (continued)

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Product Folder Links: TLV733P

Typical Characteristics (continued)

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 9

Typical Characteristics (continued)

VOUT (1 V/div, VOUT (1 V/div,

Time (20 µs/div) Time (20 µs/div)

Figure 23. Line Transient Figure 24. Line Transient

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Product Folder Links: TLV733P

Typical Characteristics (continued)

VOUT (200 mV/div, VOUT (200 mV/div,

ILOAD (100 mA/div) ILOAD (100 mA/div)

Time (20 µs/div) Time (20 µs/div)

VOUT (100 mV/div, VOUT (100 mV/div,

ILOAD (100 mA/div)

ILOAD (200 mA/div)

Time (20 µs/div) Time (50 µs/div)

VEN (500 mV/div)

ILOAD (200 mA/div)

Time (100 µs/div) Time (100 µs/div)

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 11

Typical Characteristics (continued)

VOUT (500 mV/div)

VEN (500 mV/div)

VOUT (500 mV/div)

ILOAD (200 mA/div)

Time (100 µs/div) Time (100 µs/div)

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7.2 Functional Block Diagram

Copyright © 2014–2019, Texas Instruments Incorporated Submit Documentation Feedback 13

7.3 Feature Description

7.3.2 Shutdown and Output Enable