USBLC6-2

Datasheet

Very low capacitance ESD protection

Features
• 2 data-line protection
• Protects VBUS
• Very low capacitance: 3.5 pF max.
• Very low leakage current: 150 nA max.
• SOT-666 and SOT23-6L packages
• RoHS compliant
Benefits
• Very low capacitance between lines to GND for optimized data integrity and
speed
• Low PCB space consumption: 2.9 mm² max for SOT-666 and 9 mm² max for
SOT23-6L
I/O1 1 6 I/O1
• Enhanced ESD protection: IEC 61000-4-2 level 4 compliance guaranteed at
device level, hence greater immunity at system level
GND 2 5 VBUS
• ESD protection of VBUS
• High reliability offered by monolithic integration
I/O2 3 4 I/O2 • Low leakage current for longer operation of battery powered devices
• Fast response time
• Consistent D+ / D- signal balance:
Functional diagram (top view)
– Very low capacitance matching tolerance I/O to GND = 0.015 pF
– Compliant with USB 2.0 requirements
Complies with the following standards:
• IEC 61000-4-2 level 4:
– 15 kV (air discharge)
– 8 kV (contact discharge)

Product status link

Applications
USBLC6-2
• USB 2.0 ports up to 480 Mb/s (high speed)
• Compatible with USB 1.1 low and full speed
• Ethernet port: 10/100 Mb/s
• SIM card protection
• Video line protection
• Portable electronics

Description
The USBLC6-2SC6 and USBLC6-2P6 are monolithic application specific devices
dedicated to ESD protection of high speed interfaces, such as USB 2.0, Ethernet
links and video lines.
The very low line capacitance secures a high level of signal integrity without
compromising in protecting sensitive chips against the most stringently characterized
ESD strikes.

DS4260 - Rev 7 - December 2021 www.st.com

For further information contact your local STMicroelectronics sales office.
 USBLC6-2
Characteristics

1 Characteristics

Table 1. Absolute ratings (Tamb = 25 °C)

Symbol Parameter Value Unit

IEC 61000-4-2 level 4 standard:

Air discharge 15
VPP Peak pulse voltage kV
Contact discharge 15
MIL STD883G-Method 3015-7 25
Tstg Storage temperature range -55 to +150 °C

Tj Operating junction temperature range -40 to +150 °C

TL Maximum lead temperature for soldering during 10 s at 5 mm 260 °C

Table 2. Electrical characteristics (Tamb = 25 °C)

Value
Symbol Parameter Test conditions Unit
Min. Typ. Max.

IRM Leakage current VRM = 5.25 V 10 150 nA

Breakdown voltage
VBR between IR = 1 mA 6 V
VBUS and GND

VF Forward voltage IF = 10 mA 1.1 V

IPP = 1 A, 8/20 μs
12
Any I/O pin to GND
VCL Clamping voltage V
IPP = 5 A, 8/20 μs
17
Any I/O pin to GND
Capacitance
Ci/o-GND between I/O and VR = 1.65 V 2.5 3.5
GND pF

ΔCi/o-GND 0.015

Capacitance
Ci/o-i/o VR = 1.65 V 1.2 1.7
between I/O pF
ΔCi/o-i/o 0.04

DS4260 - Rev 7 page 2/20

 USBLC6-2
Characteristics (curves)

1.1 Characteristics (curves)

Figure 2. Line capacitance versus frequency (typical

Figure 1. Capacitance versus voltage (typical values)
values)

C(pF)
3.0 C(pF)
2.8
CO=I/O-GND
2.6
2.5 2.4
VOSC=30mVRMS
2.2 Tj=25°C
F=1MHz VLINE=0V to 3.3V
2.0
2.0 VOSC=30mVRMS
Tj=25°C 1.8
1.6
1.5
Cj=I/O-I/O
1.4
1.2
1.0 1.0
0.8
0.6
0.5
0.4
Data line voltage (V)
0.2 F(MHz)
0.0
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
1 10 100 1000

Figure 3. Relative variation of leakage current versus

Figure 4. Frequency response
junction temperature (typical values)

S21(dB)
IRM [Tj ] / I R M[T j = 25 °C] 0.00

100
VBUS = 5 V
-5.00

-10.00

10

-15.00

F(Hz)
Tj (°C) -20.00
100.0k 1.0M 10.0M 100.0M 1.0G
1
25 50 75 100 125 150

DS4260 - Rev 7 page 3/20

 USBLC6-2
Technical information

2 Technical information

2.1 Surge protection

The USBLC6-2 is particularly optimized to perform surge protection based on the rail to rail topology.
The clamping voltage VCL can be calculated as follow:
VCL+ = VTRANSIL + VF for positive surges
VCL- = - VF for negative surges
with: VF = VT + Rd.Ip
(VF forward drop voltage) / (VT forward drop threshold voltage)
and VTRANSIL = VBR + Rd_TRANSIL.IP
Calculation example
We assume that the value of the dynamic resistance of the clamping diode is typically:
Rd = 0.5 Ω and VT = 1.1 V
We assume that the value of the dynamic resistance of the transil diode is typically:
Rd_TRANSIL = 0.5 Ω and VBR = 6.1 V For an IEC 61000-4-2 surge level 4 (Contact Discharge: Vg = 8 kV, Rg = 330
Ω), VBUS = +5 V, and if in first approximation, we assume that:
Ip = Vg / Rg = 24 A.
So, we find:
VCL+ = +31.2 V
VCL- = -13 V
Note: The calculations do not take into account phenomena due to parasitic inductances.

2.2 Surge protection application example

If we consider that the connections from the pin VBUS to VCC, from I/O to data line and from GND to PCB GND
plane are done by tracks of 10 mm long and 0.5 mm large, we assume that the parasitic inductances LVBUS, LI/O
and LGND of these tracks are about 6 nH. So when an IEC 61000-4-2 surge occurs on data line, due to the rise
time of this spike (tr = 1 ns), the voltage VCL has an extra value equal to LI/O.dl/dt + LGND.dI/dt.
The dI/dt is calculated as:
dI/dt = Ip/tr = 24 A/ns
The overvoltage due to the parasitic inductances is:
LI/O.dl/dt = LGND.dI/dt = 6 nH x 24 A/ns = 144 V
By taking into account the effect of these parasitic inductances due to unsuitable layout, the clamping voltage will
be:
VCL+ = +31.2 + 144 + 144 = 319.2 V
VCL- = -13.1 - 144 - 144 = -301.1 V
We can significantly reduce this phenomena with simple layout optimization. It is for this reason that some
recommendations have to be followed (see ).

DS4260 - Rev 7 page 4/20

 USBLC6-2
Surge protection application example

Figure 5. ESD behavior: parasitic phenomena due to unsuitable layout

ESD surge on data line VCL+

VBUS
Data line

L I/O L I/O di L VBUS L I/O di + L GND di

dt dt dt Positive
Surge
VCC pin

VF

VTRANSIL VTRANSIL + VF
VCL
I/O pin
t
t r = 1 ns
GND pin
t r = 1 ns
L GND L GND di t
dt
- VF

VCL + = VTRANSIL + VF + LI/O di + LGND di surge > 0

dt dt Negative
-L I/O di - L GND di Surge
VCL- = -VF - LI/O di - L GND di surge > 0
dt dt
dt dt
V TRANSIL VBR + Rd.Ip =

VCL-

DS4260 - Rev 7 page 5/20

 USBLC6-2
How to ensure good ESD protection

2.3 How to ensure good ESD protection

While the USBLC6-2 provides high immunity to ESD surge, efficient protection depends on the layout of the
board. In the same way, with the rail to rail topology, the track from data lines to I/O pins, from VCC to VBUS pin
and from GND plane to GND pin must be as short as possible to avoid overvoltages due to parasitic phenomena
(see Figure 6. ESD behavior: layout optimization and Figure 5. ESD behavior: parasitic phenomena due to
unsuitable layout for layout consideration).

Figure 6. ESD behavior: layout optimization Figure 7. ESD behavior: measurement conditions

1 6
ESD SURGE

2 5
TEST BOARD
IN OUT
3 4

USBLC6-2SC6
Unsuitable layout

1 6 +5 V

2 5

3 4

Optimized layout

Figure 8. ESD response to IEC 61000-4-2 (+15 kV air Figure 9. ESD response to IEC 61000-4-2 (-15 kV air
discharge) discharge)

Note: Important: A good precaution to take is to put the protection device as close as possible to the disturbance
source (generally the connector).

DS4260 - Rev 7 page 6/20

 USBLC6-2
Crosstalk behavior

2.4 Crosstalk behavior

2.4.1 Crosstalk phenomenon

Figure 10. Crosstalk phenomenon

RG1
Line 1

VG1 RL1 α 1 VG1 + β12VG2

RG2
Line 2

VG2 RL2 α 2VG2 + β21VG1

DRIVERS RECEIVERS

The crosstalk phenomenon is due to the coupling between 2 lines. The coupling factor (β12 or β21) increases
when the gap across lines decreases, particularly in silicon dice. In the above example the expected signal on
load RL2 is α2VG2, in fact the real voltage at this point has got an extra value β21VG1. This part of the VG1 signal
represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken
into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The
perturbed line will be more affected if it works with low voltage signal or high load impedance (few kΩ).

Figure 11. Analog crosstalk measurements

TEST BOARD

NETWORK ANALYSER
USBLC6-2SC6

NETWORK ANALYSER PORT 2

PORT 1
Vbus

Figure 11. Analog crosstalk measurements shows the measurement circuit for the analog application. In usual
frequency range of analog signals (up to 240 MHz) the effect on disturbed line is less than -55 dB (see
Figure 12. Analog crosstalk results).

DS4260 - Rev 7 page 7/20

 USBLC6-2
Crosstalk behavior

Figure 12. Analog crosstalk results

dB
0.00

- 30.00

- 60.00

- 90.00

F (Hz)
- 120.00
100.0k 1.0M 10.0M 100.0M 1.0G

As the USBLC6-2 is designed to protect high speed data lines, it must ensure a good transmission of operating
signals. The frequency response (Figure 4. Frequency response) gives attenuation information and shows that
the USBLC6-2 is well suitable for data line transmission up to 480 Mbit/s while it works as a filter for undesirable
signals like GSM (900 MHz) frequencies, for instance.

DS4260 - Rev 7 page 8/20

 USBLC6-2
Application examples

2.5 Application examples

Figure 13. USB 2.0 port application diagram using USBLC6-2

DEVICE- + 3.3V + 5V HUB-

UPSTREAM RPU Protecting
DOWNSTREAM
TRANSCEIVER USB Bus Switch TRANSCEIVER
SW2 connector
SW1

VBUS VBUS
RX LS/FS + VBUS RX LS/FS +
RX HS + RX HS +
TX HS + D+ TX HS +
RX LS/FS - RX LS/FS -
RX HS - RX HS -
TX HS - D- TX HS -

GND GND
RS GND RS
TX LS/FS + TX LS/FS +

TX LS/FS -
RS USBLC6-2SC6 RS
TX LS/FS -

RPD RPD

DEVICE- + 3.3V
UPSTREAM RPU
TRANSCEIVER USB
SW2 connector
SW1

VBUS
RX LS/FS +
VBUS RX LS/FS +
RX HS + RX HS +
TX HS + D+ TX HS +
RX LS/FS - RX LS/FS -
RX HS - RX HS -
TX HS - D- TX HS -

GND GND
RS GND RS
TX LS/FS + USBLC6-4SC6 TX LS/FS +
RS USBLC6-2P6 RS
TX LS/FS - TX LS/FS -

RPD RPD

Mode SW1 SW2

Low Speed LS Open Closed
Full Speed FS Closed Open
High Speed HS Closed then open Open

DS4260 - Rev 7 page 9/20

 USBLC6-2
PSpice model

Figure 14. T1/E1/Ethernet protection

+VCC

USBLC6-2SC6
Tx 100nF

SMP75-8

DATA

TRANSCEIVER

+VCC

USBLC6-2SC6
Rx 100nF

SMP75-8

2.6 PSpice model

Figure 15. PSpice model shows the PSpice model of one USBLC6-2 cell. In this model, the diodes are defined by
the PSpice parameters given in Figure 16. PSpice parameters.

Figure 15. PSpice model

LI/O RI/O RI/O LI/O

D+in D+out
MODEL = Dlow MODEL = Dhigh

LGND RGND MODEL = Dzener RI/O LI/O

GND VBUS

MODEL = Dlow MODEL = Dhigh

LI/O RI/O RI/O LI/O

D-in D-out

Note: This simulation model is available only for an ambient temperature of 27 °C.

DS4260 - Rev 7 page 10/20

 USBLC6-2
PSpice model

Figure 16. PSpice parameters Figure 17. USBLC6-2 PCB layout considerations

Dlow Dhigh Dzener LI/O 750p

BV 50 50 7.3 RI/O 110m D+out

D+in 1
CJ0 0.9p 2.0p 40p LGND 550p
VBUS
IBV 1m 1m 1m RGND 60m GND
M 0.3333 0.3333 0.3333 CBUS = 100nF
D-in
RS 0.2 0.52 0.84
VJ 0.6 0.6 0.6 D-out
USBLC6-2
TT 0.1u 0.1u 0.1u

DS4260 - Rev 7 page 11/20

 USBLC6-2
Package information

3 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

3.1 SOT23-6L package information

Figure 18. SOT23-6L package outline

c A1
θ L
A H
E

D b
e

A2

Table 3. SOT23-6L package mechanical data

Dimensions

Ref. Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

A 0.9 1.45 0.0354 0.0571

A1 0 0.15 0 0.0059
A2 0.9 1.3 0.0354 0.0512
b 0.30 0.5 0.0118 0.0197
c 0.09 0.2 0.0035 0.0079
D 2.8 3.05 0.1102 0.1201
E 1.5 1.75 0.0591 0.0689
e 0.95 0.0374
H 2.6 3 0.1024 0.1181
L 0.3 0.6 0.0118 0.0236
θ 0 10 0 0.3937

1. Value in inches are converted from mm and rounded to 4 decimal digits

DS4260 - Rev 7 page 12/20

 USBLC6-2
SOT23-6L package information

Figure 19. Footprint recommendations, dimensions in mm (inches)

0.60
(0.024)

1.20
(0.047)

3.50 2.30
1.10
(0.138) (0.091)
0.95 (0.043)
(0.037)

DS4260 - Rev 7 page 13/20

 USBLC6-2
SOT-666 package information

3.2 SOT-666 package information

Figure 20. SOT-666 package outline

b

L1

D E1

A
A3
L2
E

Table 4. SOT-666 package mechanical data

Dimensions

Ref. Millimeters Inches(1)

Min. Typ. Max. Min. Typ. Max.

A 0.45 0.62 0.018 0.025

A3 0.08 0.18 0.003 0.007
b 0.17 0.34 0.007 0.013
D 1.50 1.70 0.059 0.067
E 1.50 1.70 0.059 0.067
E1 1.10 1.30 0.043 0.051
e 0.50 0.020
L1 0.19 0.007
L2 0.10 0.30 0.004 0.012

1. Value in inches are converted from mm and rounded to 4 decimal digits

DS4260 - Rev 7 page 14/20

 USBLC6-2
SOT-666 package information

Figure 21. Footprint recommendations, dimensions in mm

0.50

0.62 2.60

0.99

0.30

DS4260 - Rev 7 page 15/20

 USBLC6-2
Packing information

3.3 Packing information

Figure 22. Marking layout (refer to ordering information

Figure 23. Package orientation in reel
table for marking)

X X X X

Figure 25. Reel dimensions (mm)

Figure 24. Tape and reel orientation

Figure 26. Inner box dimensions (mm)

DS4260 - Rev 7 page 16/20

 USBLC6-2
Packing information

Figure 27. Tape and reel outline

Table 5. Tape and reel mechanical data

Dimensions

Ref. Millimeters

Min. Typ. Max.

P1 3.9 4 4.1
P0 3.9 4 4.1
D0 1.45 1.5 1.6
D1 1
F 3.45 3.5 3.55
K0 1.3 1.4 1.6
P2 1.95 2 2.05
W 7.9 8 8.3

DS4260 - Rev 7 page 17/20

 USBLC6-2
Ordering information

4 Ordering information

Figure 28. Ordering information scheme

USB LC 6 - 2 xxx

Product Designation
Low capacitance
Breakdown Voltage
6 = 6 Volts
Number of lines protected
2 = 2 lines
Packages
SC6 = SOT23-6L
P6 = SOT-666

Table 6. Ordering information

Order code Marking Package Weight Base qty. Delivery mode

USBLC6-2SC6 (1) UL26 SOT23-6L 16.7 mg 3000 Tape and reel

USBLC6-2P6(1) F SOT-666 2.9 mg 3000 Tape and reel

1. The marking code can be rotated by 90° to differentiate assembly location.

DS4260 - Rev 7 page 18/20

 USBLC6-2

Revision history
Table 7. Document revision history

Date Version Changes

14-Mar-2005 1 Initial release.

07-Jun-2005 2 Format change to figure 3; no content changed.
Added marking illustrations - Figures 21 and 23. Added ECOPACK statement.
20-Mar-2008 3 Updated operating junction temperature range in absolute ratings, page 2.
Technical information section updated. Reformatted to current standards.
Updated leakage current for VRM = 5.25 V as specified in USB standard.
27-Jun-2011 4
Updated marking illustrations Figure 21 and Figure 23.
24-Oct-2011 5 Updated legal statement.
16-Oct-2020 6 Minor text changes.
Updated Section ■ Disclaimer
24-Dec-2021 7
Updated Section 1 Characteristics

DS4260 - Rev 7 page 19/20

 USBLC6-2

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DS4260 - Rev 7 page 20/20