®

SP6128A

Low Voltage, Synchronous Step Down PWM Controller

Ideal for 2A to 10A, Small Footprint, DC-DC Power Converters

■ Optimized for Single Supply, 3V - 5.5V Applications GL 1 14 BST

■ High Efficiency: Greater Than 95% Possible PVCC 2 13 GH

■ Discontinuous Startup for Precharged Output VCC 3

SP6128A 12 SWN

■ Accurate Fixed 300kHz Frequency Operation PGND 4 14 pin TSSOP 11 ISET

■ Fast Transient Response GND 5 10 VFB

■ Internal Soft Start Circuit COMP 6 9 NC

■ Accurate 0.8V Reference Allows Low Output NC 7 8 NC

Voltages
■ Resistor Programmable Output Voltage Now Available in Lead Free Packaging
■ Resistor Programmable Overcurrent Threshold APPLICATIONS
■ Loss-less Current Limit with High Side RDS(ON) ■ DSP
Sensing ■ Microprocessor Core
■ Hiccup Mode Current Limit Protection ■ I/O & Logic
■ Dual N-Channel MOSFET Synchronous Driver ■ Industrial Control
■ Quiescent Current: 500µA, 30µA in Shutdown ■ Distributed Power
■ 14 pin TSSOP ■ Low Voltage Power

DESCRIPTION
The SP6128A is a fixed frequency, voltage mode, synchronous PWM controller designed to
work from a single 5V or 3.3V input supply, providing excellent AC and DC regulation for high
efficiency power conversion. Requiring only few external components, the SP6128A pack-
aged in an 14-pin TSSOP, is especially suited for low voltage applications where cost, small
size and high efficiency are critical. The operating frequency is internally set to 300kHz,
allowing small inductor values and minimizing PC board space. The SP6128A drives two
N-channel power MOSFETs for improved efficiency and includes an accurate 0.8V reference
for low output voltage applications.
TYPICAL APPLICATION CIRCUIT
3V to 5.5V

C5 C6 C7
D1 10µF 10µF 10µF
MBR0530

Q1
1 14 R3 FDS6690A
R1 GL BST C4 8k
5 1µF
2 13
PVCC SP6128A GH L1 1.0µH 2.5V/10A
3 12
VCC SWN
4 11
PGND ISET
C1 5 10 D2 C8 C9 C10 C11
GND VFB STPS2L25U 10µF 10µF 10µF 470µF
2.2µF
6 9 Q2
COMP NC
FDS6690A
7 8
NC NC
R4
C12 1.7k
4.7nF

C3
68pF
R5
800
R2 7.87k C2 4.7n

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

1
 ABSOLUTE MAXIMUM RATINGS
VCC, PVCC ......................................................................................... 7V Junction Temperature, TJ ................................ 125°C
BST .................................................................. 13.2V Lead Temperature (Soldering, 10 sec) ............ 300°C
BST-SWN .............................................................. 7V ESD Rating. ................................................ 2kV HBM
SWN ............................................................ -1V to 7V Thermal Resistance θJC ............................. 31.7°C/W
GH ............................................... -0.3V to BST +0.3V
GH-SWN ............................................................... 7V These are stress ratings only and functional operation
All other pins ................................ -0.3V to VCC + 0.3V of the device at these ratings or any other above those
Peak Output Current < 10µs indicated in the operation sections of the specifications
GH,GL .................................................................. 2A below is not implied. Exposure to absolute maximum
Storage Temperature ........................ -65°C to 150°C rating conditions for extended periods of time may
Power Dissipation .............................................. 1.3W affect reliability.

ELECTRICAL CHARACTERISTICS
Unless otherwise specified: -40°C < TA < 85°C, 3.0V < PVCC = VCC < 5.5V, CCOMP = 22nF, CGH = CGL = 3.3nF, VFB = 0.8V,
SWN = GND = 0V, typical value for design guideline only.

PARAMETER MIN TYP MAX UNITS CONDITIONS

QUIESCENT CURRENT
VCC Supply Current 0.5 1.0 mA No Switching
PVCC Supply Current 1 20 µA No Switching, GH = Low
VCC Supply Current(Disabled) 30 60 µA COMP=0V
PVCC Supply Current (Disabled) 1 20 µA COMP=0V
ERROR AMPLIFIER
Error Amplifier Transconductance 0.6 ms
COMP Sink Current 10 35 65 µA VFB = 0.9V, COMP = 0.9V, No Faults
COMP Source Current 10 35 65 µA VFB = 0.7V, COMP = 2V
COMP Output Impedance 3 MΩ
VFB Input Bias Current 130 nA
Error Amplifier Reference 0.788 0.8 0.812 V Trimmed with Error Amp in Unity Gain
OSCILLATOR & DELAY PATH
Internal Oscillator Frequency 270 300 330 kHz
Maximum Controlled Duty Cycle 90 % Loop in control - 100% DC Possible
Minimum Duty Cycle 0 % Comp=0.7V
Minimum GH Pulse Width 150 250 ns PVCC > 4.5V, Ramp up COMP voltage
until GH starts switching
CURRENT LIMIT
ISET Pin Sink Current 10 12.5 15 µA Temp = 25 °C
ISET Current Temperature Coefficient 3400 ppm/°C
Current Limit Time Constant 15 µs
Overcurrent Comparator 100 125 150 mV VISET - VSWN, Temp = 25°C
Threshold Voltage
Threshold Voltage Temperature 3400 ppm/°C
Coefficient

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

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 ELECTRICAL CHARACTERISTICS
Unless otherwise specified: -40°C < TA < 85°C, 3.0V < PVCC = VCC < 5.5V, CCOMP = 22nF, CGH = CGL = 3.3nF, VFB = 0.8V,
SWN = GND = 0V, typical value for design guideline only.

PARAMETER MIN TYP MAX UNITS CONDITIONS

SOFT START, SHUTDOWN, UVLO
Internal Soft Start Slew Rate 0.1 0.3 0.6 V/ms COMP pin, on transition from shutdown
COMP Discharge Current 183 µA COMP = 0.5V, Fault Initiated
COMP Clamp Voltage 0.55 0.65 0.75 V VFB = 0.9V
COMP Clamp Current 10 30 65 µA COMP = 0.5V, VFB = 0.9V
Shutdown Threshold Voltage 0.29 0.34 0.39 V Measured at COMP Pin
Shutdown Input Pull-up Current 2 5 10 µA COMP = 0.2V, Measured at COMP pin
VCC Start Threshold 2.63 2.8 2.95 V
VCC Stop Threshold 2.47 2.7 2.9 V
GATE DRIVERS
GH Rise Time 60 110 ns PVCC > 4.5V
GH Fall Time 60 110 ns PVCC > 4.5V
GL Rise Time 60 110 ns PVCC > 4.5V
GL Fall Time 60 110 ns PVCC > 4.5V
GH to GL Non-Overlap Time 0 100 140 ns PVCC > 4.5V, measured at 2volt threshold
GL to GH Non-Overlap Time 0 100 140 ns PVCC > 4.5V, measured at 2volt threshold

PIN DESCRIPTION
PIN N0. PIN NAME DESCRIPTION
1 GL High current driver output for the low side MOSFET switch. It is always low if GH is high.
GL swings from PGND to PVCC.
2 PVCC Positive input supply for the low side gate driver. It's recommended to tie the PVCC to the
VCC pin.
3 VCC Positive input supply for the logic circuitry. Properly bypass this pin to GND with a low ESL/
ESR ceramic capacitor or RC filter.
4 PGND Power ground pin.
5 GND Signal ground pin.
6 COMP Output of the Error Amplifier. It is internally connected to the inverting input of the PWM
comparator. A lead-lag network is typically connected to the COMP pin to compensate the
feedback loop in order to optimize the dynamic performance of the voltage mode control
loop. Sleep mode can be invoked by pulling the COMP pin below 0.3V with an external
open-drain or open-collector transistor. An internal 5µA pull-up ensures start-up.
7, 8, 9 NC No connect.
10 VFB Feedback Voltage Pin. It is the inverting input of the Error Amplifier and serves as the
output voltage feedback point for the Buck converter. The output voltage is sensed and
can be adjusted through an external resistor divider.
11 ISET Overcurrent program pin. A resistor programs the overcurrent threshold. The overcurrent
comparator sets the fault latch and terminates gate pulses when VISET > VSWN and the high
side MOSFET is turned on. This prevents excessive power dissipation in the external
power MOSFETs during an overload condition. An internal delay circuit prevents false
shutdowns that might otherwise occur during very short, mild overload conditions,due to
load transients.
12 SWN Lower supply rail for the GH high-side gate driver. It also connects to the Current Limit
comparator. Connect this pin to the switching node at the junction between the two
external power MOSFET transistors. This pin monitors the voltage drop across the RDS(ON)
of the high side N-channel MOSFET while it is conducting.
13 GH High current driver output for the high side MOSFET switch. It is always low if GL is high or
during a fault. GH swings from SWN to BST.
14 BST High side driver supply pin. Connect BST to the external boost diode and capacitor as
shown in the application schematic on page 1.

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

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 FUNCTIONAL DIAGRAM

1V -
DRIVER ENABLE
0.8V
Reference +
2 PVCC
-
SHUTDOWN
350mV + 14 BST
FAULT GM
ERROR
0.27V/ms AMP 5µA PWM COMP RESET
SOFTSTART + Dominant PWM 13 GH
- Logic Synchronous
R Driver
-
+ Q 1 GL
VFB 10

S
COMP 6 12 SWN

VCC 3 4 PGND

UVLO 5 GND
750mV RAMP F = 300kHz
-
2.8V ON
2.7V OFF
+ Reset
Dominant

Over Current S COMP

GH FAULT
Q
15µA
SHUTDOWN R
ISET 11 +
SWN -

OPERATION

General Overview
The SP6128A is a constant frequency, voltage High efficiency is obtained through the use of
mode, synchronous PWM controller designed synchronous rectification. Synchronous regula-
for low voltage, DC/DC step down converters. tors replace the catch diode in the standard buck
It is intended to provide complete control for a converter with a low R DS(ON) N-channel
high power, high efficiency, precisely regulated MOSFET switch allowing for significant ef-
output voltage from a highly integrated 14-pin ficiency improvements. The SP6128A in-
solution. cludes two fast MOSFET drivers with inter-
The internal free-running oscillator accurately nal non-overlap circuitry and drives a pair of
sets the PWM frequency at 300kHz without N-channel power transistors. The SP6128A
requiring any external elements and allows the includes an internal 0.27V/ms soft-start cir-
use of physically small, low value external com- cuit that provides controlled ramp up of the
ponents without compromising performance. A output voltage, preventing overshoot and in-
transconductance amplifier is used for the error rush current at power up.
amplifier, which compares an attenuated sample Current limiting is implemented by monitoring
of the output voltage with a precision, 0.8V the voltage drop across the RDS(ON) of the high
reference voltage. The output of the error ampli- side N-channel MOSFET while it is conducting,
fier (COMP), is compared to a 0.75V peak-to- thereby eliminating the need for an external
peak ramp waveform to provide PWM control. sense resistor. The overcurrent threshold can be
The COMP pin provides access to the output of programmed by a single resistor.
the error amplifier and allows the use of external
components to stabilize the voltage loop.

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

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 OPERATION: continued

When the overcurrent threshold is exceeded, the UVLO

overcurrent comparator sets the fault latch and Assuming that there is not shutdown condition
terminates the output pulses. The controller present, then the voltage on the VCC pin deter-
stops switching and goes through a hiccup se- mines operation of the SP6128A. As VCC rises,
quence. This prevents excessive power dissipa- the UVLO block monitors VCC and keeps the
tion in the external power MOSFETs during an high side and low side MOSFETS off and the
overload condition. An internal delay circuit internal SS voltage low until VCC reaches 2.8V.
prevents that very short and mild overload con- If no faults are present, the SP6128A will ini-
ditions, that could occur during a load transient, tiate a soft start when VCC exceeds 2.8 V.
activate the current limit circuit.
Hysteresis (about 100mV) in the UVLO com-
A low power sleep mode can be invoked in the parator provides noise immunity at start-up.
SP6128A by externally forcing the COMP pin
below 0.3V. Quiescent supply current in sleep Soft Start
mode is typically less than 30µA. An internal Soft start is required on step-down controllers to
5µA pull-up current at the COMP pin brings the prevent excess inrush current through the power
SP6128A out of shutdown mode. train during start-up. Typically this is managed
An internal 0.8V 1.5% reference allows out- by sourcing a controlled current into a timing
put voltage adjustment for low voltage appli- capacitor and then using the voltage across this
cations. capacitor to slowly ramp up either the error amp
The SP6128A also includes an accurate under- reference or the error amp output (COMP). The
voltage lockout that shuts down the controller control loop creates narrow width driver pulses
when the input voltage falls below 2.7V. Output while the output voltage is low and allows these
overvoltage protection is achieved by turning pulses to increase to their steady-state duty
off the high side switch and turning on the low cycle as the output voltage increases to its regu-
side N-channel MOSFET 100% of the time. lated value. As a result of controlling the induc-
tor volt*second product during startup, inrush
Enable current is also controlled.
Low quiescent mode or “Sleep Mode” is initi- In the SP6128A the duration of the soft-start is
ated by pulling the COMP pin below 0.3V with controlled by an internal timing circuit that
an external open-drain or open-collector tran- provides a 0.3V/mS slew-rate, which is used
sistor. Supply current is reduced to 30µA (typi- during startup and overcurrent to set the hiccup
cal) in shutdown. On power-up, assuming that time. The SP6128A implements soft-start by
VCC has exceeded the UVLO start threshold ramping up the error amplifier reference voltage
(2.8V), an internal 5µA pull-up current at the providing a controlled slew-rate of the output
COMP pin brings the SP6128A out of shutdown voltage, thereby preventing overshoot and in-
mode and ensures start-up. During normal oper- rush current at power up.
ating conditions and in absence of a fault, an The presence of the output capacitor creates extra
internal clamp prevents the COMP pin from current draw during startup. Simply stated, dVOUT/
swinging below 0.6V. This guarantees that dur- dt requires an average sustained current in the
ing mild transient conditions, due either to line output capacitor and this current must be consid-
or load variations, the SP6128A does not enter ered while calculating peak inrush current and
shutdown unless it is externally activated. over current thresholds. An approximate expres-
During Sleep Mode, the high side and low side sion to determine the excess inrush current due to
MOSFETS are turned off and the internal soft the dVOUT/dt of the output capacitor COUT is:
start voltage is held low. VOUT
Iinrush = COUT x (0.27 V/ms) x 0.8V

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

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 OPERATION: continued
As the figure shows, the SS voltage controls a
variety of signals. First, provided all the exter- COMP
nal fault conditions are removed, an internal
5µA pull-up at the COMP pin brings the 1V
SP6128A out of shutdown mode. The internal 0.7 V
timing circuit is then activated and controls the 0.3 V
ramp-up of the error amp reference voltage. The 0V
COMP pin is pulled to 0.7V by the internal
clamp and then gradually charges preventing
the error amplifier from forcing the loop to
maximum duty cycle. As the COMP voltage Internal SS
crosses about 1V (valley voltage of the PWM Voltage
ramp), the driver begins to switch the high side
MOSFET with narrow pulses in an effort to
keep the converter output regulated . The
Error Amp
SP6128A operates at low duty cycle as the Reference
COMP voltage increases above 1V. As the error Voltage
amp reference ramps upward, the driver pulses 0.8 V
widen until a steady state value is reached and
the output voltage is regulated to the final value
ending the soft start charge cycle. 0V

Hiccup Mode I(L)

When the converter enters a fault mode, the
SP6128A holds the high side and low side Inductor
MOSFETs off for a finite period of time. Provided Current
that the SP6128A is enabled, this time is set by the
internal charge of the soft-start capacitor. In the 0A
event of an overcurrent condition, the current V(VCC)
sense comparator sets the fault latch, which in turn
discharge the internal SS capacitor, the COMP pin FAULT
and holds the output drivers off. During this con-
dition, the SP6128A stays off for the time it takes 0V
to discharge the COMP pin down to the 0.29V
shutdown threshold. At this point, the fault latch V(VCC)
is reset, but before the SP6128A is allowed to
attempt restart, the COMP pin has to charge back
SWN
to 1V before any output switching can be initiated. Voltage
Then, the regulator attempts to restart normally by 0V
delivering short gate pulses and if the overcurrent
condition is still present, the cycle will repeat itself. TIME
However, if upon restart, the overcurrent condi-
tion is still present, the SP6128A will detect the
fault and remain in a fault state until the internal
soft start voltage reaches about VCC-1V thereby
increasing the MOSFET off-time. This protection
scheme minimizes thermal stress to the regulator
components as the overcurrent condition persists.

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

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 OPERATION: continued
A more detailed description of the waveform is shown below.

SP6128A OVER CURRENT (HICCUP MODE)

Test Conditions BST = 5.0V

VFB = 0.7V SWN - tied to GND through 1k Resistor
VCC = PVCC = 5.0V COMP – released from GND

Overcurrent Detected Internal SSTART rises until

GH Turns Off ~ VCC-1V, then gives command
Fault Mode Enabled to attempt RESTART

GH
COMP Clamps
~ 3V

COMP

After pop, COMP

retains internal
ENABLE SSTART slope
Part

Attempt 5µA PULLUP slope to 0.3V; Internal SSTART

RESTART 35µA PULLUP to 0.7V passes V(VFB), COMP
pops to ~ internal
SSTART voltage +0.7V

Over Current Protection

Over current protection on the SP6128A is imple- current condition upon reaching a CMOS in-
mented through detection of an excess voltage verter threshold. There are many advantages to
condition across the high side NMOS switch this approach. First, the filtering action of the
during conduction. This is typically referred to gated scheme protects against false and undesir-
as high side RDS(ON) detection and eliminates the able triggering that could occur during a minor
need of an external sense resistor. The over transient overload condition or supply line noise.
current comparator charges an internal sam- Furthermore, the total amount of time to trigger
pling capacitor each time VSWN is lower than the fault depends on the on-time of the high side
(VISET - 140mV) and the GH voltage is high. The NMOS switch. Fifteen, 1µs pulses are equiva-
discharge/charge current ratio on the sampling lent to thirty, 500ns pulses or one, 15µs pulse,
capacitor is about 2%. Therefore, provided that however, depending on the period, each sce-
the over current condition persists, the capacitor nario takes a different amount of total time to
voltage will be pumped up during each time GH trigger a fault. Therefore, the fault becomes an
switches high. This voltage will trigger an over indicator of average power in the high side

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

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 OPERATION: continued
switch. The ISET current has a temperature coef- consists of one high side NMOS, 4Ω driver, GH,
ficient in an effort to first order match the and one low side, 4 Ω, NMOS driver, GL,
thermal characteristics of the RDS(ON) of the high optimized for driving external power MOSFET’s
side NMOS switch. It assumed that the SP6128A in a synchronous buck topology. The output
will be used in compact designs where there is a drivers also provide gate drive non-overlap
high amount of thermal coupling between the mechanism that provides a dead time between
high side switch and the controller. GH and GL transitions to avoid potential shoot-
through problems in the external MOSFETs.
Discontinuous Start Up
The following figure shows typical waveforms
Today’s distributed power systems require mul- for the output drivers.
tiple supply voltages, such as core and I/O As with all synchronous designs, care must be
voltages. In many applications, there’s require- taken to ensure that the MOSFETs are properly
ment on the maximum voltage difference al- chosen for non-overlap time, enhancement gate
lowed between these supplies at any time. This drive voltage, “on” resistance RDS(ON), reverse
requirement can be potentially violated during transfer capacitance Crss, input voltage and
power start up when individual power supply maximum output current.
ramps up in sequence or in different slew rates.
As a solution, system designers often pre-charge
power supplies through an external circuit prior GATE DRIVER TEST CONDITIONS
to start up. Unfortunately, under this condition 5V
90 %
many existing synchronous controllers turn on
the low side MOSFET during soft start for a GH(GL) FALL TIME
2V
long period of time, thereby, discharging the 10 %
output capacitors. The discharge period creates 5V
90 %
a number of problems. One is the obvious prob- RISE TIME
2V
lem of losing the intended pre-charged output GL(GH)
10 %
voltage. Another problem is a build up of exces-
sive and unchecked current in the low side NON-OVERLAP
MOSFET and inductor. Lastly, this uncontrolled
discharge current creates conditions that could V(BST)

damage either the distributed power supplies or

GH
the rather expensive “load” ICs. Voltage

To prevent soft start from discharging the pre- 0V

charged output, SP6128A has built-in discon- V(VCC)

tinuous start up. This operation disables the low

GL
side MOSFET driver GL during start up until Voltage
either there is GH pulse or the internal SSTART
0V
reaches Vcc-1V. This feature eliminates the
V(VCC=VIN)
output discharging path during start up. During
the steady state operation, the GL is fully en- SWN
Voltage
gaged, and the operation is identical to regular
~0V
synchronous buck converters. - V(Diode) V

Output Drivers ~ 2*V(VIN)

The SP6128A, unlike some other bipolar con- BST

Voltage
troller IC’s, incorporates gate drivers with rail-
to-rail swing that help prevent spurious turn on ~ V(VIN)

due to capacitive coupling. The driver stage TIME

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

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 PACKAGE: TSSOP

PLASTIC THIN SMALL

OUTLINE
(TSSOP)
DIMENSIONS
in inches (mm)
Minimum/Maximum
Symbol 14 Lead
D 0.193/0.201
(4.90/5.10)
e 0.026 BSC
(0.65 BSC)

0.126 BSC (3.2 BSC)

0.252 BSC (6.4 BSC)
1.0 OIA
0.169 (4.30)
0.177 (4.50)

0.039 (1.0)

0’-8’ 12’REF

e/2

0.039 (1.0)

0.043 (1.10) Max

D

0.033 (0.85)
0.037 (0.95)

0.007 (0.19) 0.002 (0.05)

0.012 (0.30) 0.006 (0.15)

(θ2)

0.008 (0.20)

0.004 (0.09) Min

0.004 (0.09) Min

Gage
Plane

0.010 (0.25) (θ3) 0.020 (0.50) (θ1)

0.026 (0.75)
1.0 REF

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

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 ORDERING INFORMATION

Part Number Operating Temperature Range Package Type

SP6128AEY ............................................ -40˚C to +85˚C ...................................... 14-Pin TSSOP
SP6128AEY/TR ...................................... -40˚C to +85˚C ...................................... 14-Pin TSSOP
SP6128AHY ........................................... -40˚C to +105˚C ..................................... 14-Pin TSSOP
SP6128AHY/TR ..................................... -40˚C to +105˚C ..................................... 14-Pin TSSOP
SP6128ACY .............................................. 0˚C to +70˚C ....................................... 14-Pin TSSOP
SP6128ACY/TR ........................................ 0˚C to +70˚C ....................................... 14-Pin TSSOP

Available in lead free packaging. To order add "-L" suffix to part number.
Example: SP6128AEY/TR = standard; SP6128AEY-L/TR = lead free

/TR = Tape and Reel

Pack quantity is 2,500 for TSSOP.

Corporation

ANALOG EXCELLENCE
Sipex Corporation

Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Rev. 08/19/05 SP6128A Low Voltage, Synchronous Step Down PWM Controller © Copyright 2005 Sipex Corporation

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