UNIT III - IO INTERFACING

Memory interfacing and I/O interfacing – Parallel communication Interface –

Programming and Applications. Serial communication applications interface –
Interrupt controller – DMA controller –programming and applications.

1. MEMORY INTERFACING AND I/O INTERFACING

o While executing a program, the microprocessor needs to access memory frequently to
read instruction code and data stored in memory; the interfacing circuit enables that
access.

o Memory has some signal requirements to write into and read from its registers.
o Similarly the microprocessor initiates a set of signals when it wants to read from and
write into memory.

o The Input/output devices such as keyboards and displays are the communication channels
to the outside world. Latches and buffers are used for I/O interfacing.

MEMORY DEVICES AND INTERFACING

Any application of a microprocessor based system requires the transfer of data between external
circuitry to the microprocessor and microprocessor to the external circuitry. Most of the peripheral
devices are designed and interfaced with a CPU either to enable it to communicate with the user or an
external process and to ease the circuit operations so that the microprocessor works more efficiently.

The use of peripheral integrated devices simplifies both the hardware circuits and software
considerable. The following are the devices used in interfacing of Memory and General I/O devices:

• 74LS138 (Decoder / Demultiplexer).

• 74LS373 / 74LS374 3-STATE Octal D-Type Transparent Latches.
• 74LS245 Octal Bus Transceiver: 3-State.

74LS138 (Decoder / Demultiplexer)

The LS138 is a high speed 1-of-8 Decoder/ Demultiplexer fabricated with the low power
Schottky barrier diode process. The decoder accepts three binary weighted inputs (A0, A1, A2) and
when enabled provides eight mutually exclusive active LOW Outputs (O0–O7).
The LS138 can be used as an 8-output demultiplexer by using one of the active LOW Enable
inputs as the data input and the other Enable inputs as strobes. The Enable inputs which are not used
must be permanently tied to their appropriate active HIGH or active LOW state.
 Fig. 3.1 Pin diagram of 74138

74LS373 / 74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered

Flip-Flops
These 8-bit registers feature totem-pole 3-STATE outputs designed specifically for
implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight
latches of the 74LS373 are transparent D type latches meaning that while the enable (G) is HIGH the Q
outputs will follow the data (D) inputs.
When the enable is taken LOW the output will be latched at the level of the data that was set up. The
eight flip-flops of the 74LS374 are edge-triggered D-type flip flops. On the positive transition of the
clock, the Q outputs will be set to the logic states that were set up at the D inputs.
Main Features
 Choice of 8 latches or 8 D-type flip-flops in a single package
 3-STATE bus-driving outputs
 Full parallel-access for loading
 Buffered control inputs
 P-N-P inputs reduce D-C loading on data lines

Fig. 3.2 Connection diagram of 74LS373 Fig 3.3 Pin of 74LS245

74LS245 Octal Bus Transceiver: 3-State
The 74LS245 is a high-speed Si-gate CMOS device. The 74LS245 is an octal transceiver featuring non-
inverting 3-state bus compatible outputs in both send and receive directions. The 74LS245 features an
Output Enable (OE) input for easy cascading and a send/receive (DIR) input for direction control. OE
controls the outputs so that the buses are effectively isolated. All inputs have a Schmitt-trigger action.
These octal bus transceivers are designed for asynchronous two-way communication between
data buses. The 74LS245 is a high-speed Si-gate CMOS device. The 74LS245 is an octal transceiver
featuring non-inverting 3-state bus compatible outputs in both send and receive directions.
The 74LS245 features an Output Enable (OE) input for easy cascading and a send/receive (DIR)
input for direction control. OE controls the outputs so that the buses are effectively isolated. All inputs
have a Schmitt-trigger action. These octal bus transceivers are designed for asynchronous two-way
communication between data buses.

Memory Devices And Interfacing

The memory interfacing circuit is used to access memory quit frequently to read instruction codes and
data stored in the memory. The read / write operations are monitored by control signals. Semiconductor
memories are of two types. Viz. RAM (Random Access Memory) and ROM (Read Only Memory) The
Semiconductor RAM’s are broadly two types-
static RAM and
dynamic RAM

Memory structure and its requirements

The read / write memories consist of an array of registers in which each register has unique address. The
size of memory is N * M as shown in figure.

Where N is number of register and M is the word length, in number of bits. As shown in figure(a)
memory chip has 12 address lines Ao–A11, one chip select (CS), and two control lines, Read (RD) to
enable output buffer and Write (WR) to enable the input buffer.

The internal decoder is used to decoder the address lines. Figure(b) shows the logic diagram of a typical
EPROM (Erasable Programmable Read-Only Memory) with 4096 (4K) register. It has 12 address lines
A0 – A11, one chip select (CS), one read control signal. Since EPROM does not require the (WR)
signal.
EPROM (or EPROMs) is used as a program memory and RAM (or RAMs) as a data memory. When
both, EPROM and RAM are used, the total address space 1 Mbytes is shared by them.

Address Decoding Techniques

 Absolute decoding
 Linear decoding
 Block decoding

Absolute Decoding:
In the absolute decoding technique the memory chip is selected only for the specified logic level on the
address lines: no other logic levels can select the chip. Below figure the memory interface with absolute
decoding. Two 8K EPROMs (2764) are used to provide even and odd memory banks. Control signals
BHE and Ao are use to enable output of odd and even memory banks respectively. As each memory
chip has 8K memory locations, thirteen address lines are required to address each locations,
independently. All remaining address lines are used to generate an unique chip select signal. This
address technique is normally used in large memory systems.

Fig 3.4 Absolute decoding

Linear Decoding:
In small system hardware for the decoding logic can be eliminated by using only required number of
addressing lines (not all). Other lines are simple ignored. This technique is referred as linear decoding or
partial decoding. Control signals BHE and Ao are used to enable odd and even memory banks,
respectively. Figure shows the addressing of 16K RAM (6264) with linear decoding. The address line
A19 is used to select the RAM chips. When A19 is low, chip is selected, otherwise it is disabled. The
status of A14 to A18 does not affect the chip selection logic. This gives you multiple addresses (shadow
addresses). This technique reduces the cost of decoding circuit, but it gas drawback of multiple
addresses
 Fig 3.5 Linear decoding
Block Decoding:
In a microcomputer system the memory array is often consists of several blocks of memory chips. Each
block of memory requires decoding circuit. To avoid separate decoding for each memory block special
decoder IC is used to generate chip select signal for each block.

Fig. 3.6 Static Memory interfacing

Static Memory Interfacing

The general procedure of static memory interfacing with 8086 as follows:
1. Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bitbank is
called ‘odd address memory bank’ and the lower 8-bit bank is called ‘even address memory bank’.
2. Connect available memory address lines of memory chips with those of the microprocessor and
also connect the memory RD and WR inputs to the corresponding processor control signals. Connect
the 16-bit data bus of the memory bank with that of the microprocessor 8086.
3. The remaining address lines of the microprocessor, BHE and Ao are used for decoding the
required chip select signals for the odd and even memory banks. The CS of memory is derived from
 the output of the decoding circuit.
4. As a good and efficient interfacing practice, the address map of the system should be continuous
as far as possible

Dynamic RAM Interfacing

The basic Dynamic RAM cell uses a capacitor to store the charge as a representation of data.
This capacitor is manufactured as a diode that is reverse-biased so that the storage capacitance comes
into the picture. This storage capacitance is utilized for storing the charge representation of data but the
reverse-biased diode has a leakage current that tends to discharge the capacitor giving rise to the
possibility of data loss.
To avoid this possible data loss, the data stored in a dynamic RAM cell must be refreshed after a
fixed time interval regularly. The process of refreshing the data in the RAM is known as refresh cycle.
This activity is similar to reading the data from each cell of the memory, independent of the requirement
of microprocessor, regularly. During this refresh period all other operations (accesses) related to the
memory subsystem are suspended.
The advantages of dynamic RAM. Like low power consumption, higher packaging density and
low cost, most of the advanced computer systems are designed using dynamic RAMs. Also the refresh
mechanism and the additional hardware required makes the interfacing hardware, in case of dynamic
RAM, more complicated, as compared to static RAM interfacing circuit.

INTERFACING I/O PORTS

I/O ports or input/output ports are the devices through which the microprocessor communicates with
other devices or external data sources/destinations. Input activity, as one may expect, is the activity that
enables the microprocessor to read data from external devices, for example keyboard, joysticks, mouser
etc. the devices are known as input devices as they feed data into a microprocessor system.
Output activity transfers data from the microprocessor top the external devices, for example
CRT display, 7-segment displays, printer, etc, the devices that accept the data from a microprocessor
system are called output devices.

Steps in Interfacing an I/O Device

The following steps are performed to interface a general I/O device with a CPU:
1. Connect the data bus of the microprocessor system with the data bus of the I/O port.
2. Derive a device address pulse by decoding the required address of the device and use it as
the chip select of the device.
3. Use a suitable control signal, i.e. IORD and /or IOWR to carry out device operations, i.e.
connect IORD to RD input of the device if it is an input devise, otherwise connect IOWR to
WR input of the device. In some cases the RD or WR control signals are combined with the
device address pulse to generate the device select pulse.

Input Port
The input device is connected to the microprocessor through buffer. The simplest form of a input port is
a buffer as shown in the figure. This buffer is a tri-state buffer and its output is available only when
enable signal is active. When microprocessor wants to read data from the input device (keyboard), the
control signals from the microprocessor activates the buffer by asserting enable input of the buffer. Once
the buffer is enabled, data from the device is available on the data bus. Microprocessor reads this data by
initiating read command.
Output Port
It is used to send the data to the output device such as display from the microprocessor. The simplest
form of the output port is a latch.

Fig.3.7 I/O interfacing

The output device is connected to the microprocessor through latch as shown in the figure. When
microprocessor wants to send data to the output device it puts the data on the data busand activates the
clock signal of the latch, latching the data from the data bus at the output of latch. It is then available at
the output of latch for the output device.

I/O Interfacing Techniques

Input/output devices can be interfaced with microprocessor systems in two ways:
1. I/O mapped I/O
2. Memory mapped I/O

1. I/O mapped I/O (Isolated I/O)

8086 has special instructions IN and OUT to transfer data through the input/output ports in I/O mapped
I/O system. The IN instruction copies data from a port to the Accumulator. If an 8-bit port is read data
will go to AL and if 16-bit port is read the data will go to AX. The OUT instruction copies a byte from
AL or a word from AX to the specified port. The M/IO’ signal is always low when 8086 is executing
these instructions. In this address of I/O device is 8-bit or 16-bit. It is 8-bit for Direct addressing and 16-
bit for Indirect addressing.
 Using isolated I/O a microcomputer system, the I/O devices are treated separate from memory.
 The part of the I/O address space from address 0000H through 00FFH is referred to as Page 0 as
shown in figure.
 Supports byte and word I/O ports 64K independent byte-wide I/O ports
 32K independent aligned word-wide I/O ports

Advantages of isolated I/O

 Complete memory address space available for use by memory
 Special instructions have been provided in the instruction set of the 8086 to perform isolated I/O
operation. This instructions tailored to maximize performance
Disadvantage of Isolated I/O
 All inputs/outputs must take place between an I/O port and accumulator (AL or AX) register
2. Memory mapped I/O
In this type of I/O interfacing, the 8086 uses 20 address lines to identify an I/O device. The I/O device is
connected as if it is a memory device. The 8086 uses same control signals and instructions to access I/O
as those of memory, here RD and WR signals are activated indicating memory bus cycle.

DIFFERENCE BETWEEN MEMORY MAPPED IO & IO MAPPED IO

S. No MEMORY MAPPED IO IO MAPPED IO

1. IO is treated as Memory. IO is treated as IO.
2. 16-Bit addressing. 8- Bit addressing.
3. More Decoder Hardware. Less Decoder Hardware.
16 8
4. Can address 2 = 64k locations Can address 2 =256 locations
5. Less Memory Space Available Whole Memory Address space is available
6. Memory Instructions are used. Special Instructions are used like IN,OUT
 7. Memory control signals are used. Special control signals are used.
8. Data transfer between register and IO Data transfer between accumulator and IO.

o Some of the peripheral devices developed by Intel for 8085/8086/8088 based system are:

• 8255 - Parallel Communication Interface

• 8251 - Serial Communication Interface
• 8254 - Programmable Timer
• 8279 - Keyboard / Display Controller

o The microprocessor can communicate with external world or other systems using two
types of communication interfaces. They are:
• Parallel Communication Interface
• Serial Communication Interface

2. PARALLEL COMMUNICATION INTERFACE (8255)

 The 8255 chip is also called as Programmable Peripheral Interface/Programmable Input Output.
 The Intel’s 8255 is designed for use with Intel’s 8-bit, 16-bit and higher capability microprocessors
 The 8255 is a 40 pin integrated circuit (IC), designed to perform a variety of interface functions in a
computer environment.
 It is flexible and economical.
8255A Pin Diagram / 8255A Signals
  8255 has 24 input/output lines which may be individually programmed.
 2 groups of I/O pins are named as
• Group A (Port-A & Port C Upper)
• Group B (Port-B & Port C Lower)
 3 ports(each port has 8 bit)
• Port A lines are identified by symbols PA0-PA7
• Port B lines are identified by symbols PB0-PB7
• Port C lines are identified by PC4-PC7 , PC3-PC0
 D0 -D7 - Data input/output lines for the device. All information read from and written
to the 8255 occur via these 8 data lines.
 CS (Chip Select) - If this line is a logic 0, the microprocessor can read and write to the 8255.
 RESET - The 8255 is placed into its reset state if this input line is logic 1.
 RD - This is the input line driven by the microprocessor and should be low to indicate read
operation to 8255.
 WR - This is an input line driven by the microprocessor. A low on this line indicates write
operation.
 A1-A0 - These are the address input lines and are driven by the microprocessor.
 VCC – Power Supply
 GND – Ground Reference.

Block Diagram/Architecture of 8255 A

The 8255 consists of four sections namely

o Data Bus Buffer
o Read/Write Control Logic
o Group A and Group B Control
o Port A, Port B ,Port C
1. Data Bus Buffer
o This is a tri-state bidirectional buffer used to interface the 8255 to system data bus.
o Data is transmitted or received by the buffer on execution of input or output instruction
by the CPU.
o Using IN or OUT instructions, CPU can read or write the data from/to the data bus
buffer.
o It can also be used to transfer control words and status information between CPU and
8255A.
2. Read/Write Control Logic
o This block controls the Chip Selection (CS), Read (RD) and Write (WR) operations.
o It consists of A0 and A1 signals which are generally connected to the CPU address
lines A0 and A1 respectively.
o When CS (Chip Select) signal goes LOW, different values of A0 and A1 select one of
the I/O ports or control register.

3. Group A and Group B controls

• These blocks receive control from the CPU and issues commands to their respective
ports.
• Group A-PA and PCU (PC7 –PC4)
• Group B –PB and PCL (PC3 –PC0)
4. Port A, Port B, Port C
 Port A: This has an 8 bit latched/buffered O/P and 8 bit input latch. It can be
programmed in 3 modes –mode 0, mode 1, mode 2.
 Port B: It can be programmed in mode 0, mode 1.
 Port C: It can be programmed in mode 0.
Control Word Register
 Modes of Operation of 8255

o 8255 can be operated in two basic modes:

– Bit Set/Reset Mode
Set/Reset bits in Port C
– I/O Mode
I/O mode is further divided into 3 modes:
• Simple I/O mode (Mode 0)
• Handshake/Strobe I/O mode (Mode 1)
• Bidirectional Data Transfer mode (Mode 2)

 BSR (Bit Set/Reset) Mode

Set/Reset bits in Port C

  I/O Mode

The I/O mode is divided into three modes :

1. Mode 0 – Basic I/O Mode

2. Mode 1 – Handshake/Strobe I/O Mode
3. Mode 2 – Bi-directional data transfer mode

1. Mode 0 – Basic I/O mode

o Ports A and B are used as Simple I/O Ports.
o Port C as two 4-bit ports
o Features
o Outputs are latched
o Inputs are not latched
o Ports do not have handshake or interrupt capability

2. Mode 1 – Handshake/Strobe I/O Mode

o Handshake signals are exchanged between the microprocessor and peripherals prior
to data transfer.
o Features:
o Two Groups (Group A and Group B).
o Each group contains one 8-bit data port and one 4-bit control/data port. The
8-bit data port can be either input or output
o The 4-bit port is used for control and status of the 8-bit data port.
o If Port A is in mode 1 (input), then PC3, PC4, PC5 are used as control signals.
o If Port B is in mode 1 (input), then PC0, PC1, PC2are used as control signals.
o Both inputs and outputs are latched

Mode 1: Input control signals

 STB (Strobe Input): This signal (active low) is generated by a peripheral device that it has
transmitted a byte of data. The 8255, in response to, generates IBF and INTR.
 IBF (Input buffer full): This signal is an acknowledgement by the 8255 to indicate that the
input latch has received the data byte. This is reset when the microprocessor reads the data.
 INTR (Interrupt Request): This is an output signal that may be used to interrupt the
microprocessor. This signal is generated if , IBF and INTE are all at logic 1.
 INTE (Interrupt Enable): This is an internal flip-flop to a port and needs to be set to
generate the INTR signal. The two flip-flops INTEA and INTEB are set /reset using the
BSR mode. The INTEA is enabled or disabled through PC4, and INTEB is enabled or
disabled through PC2.

3. Mode 2 – Bi-directional data transfer mode

o This mode provides a means for communicating with a peripheral device or

structure on a single 8-bit bus for both transmitting and receiving data
(bidirectional bus I/O).
o Features:
o Used in Group A only.
o Port A only acts as bi-directional bus port
o Port C (PC3-PC7) is used for handshaking purpose

Mode 2 Control Signals

 INTERFACING 8255 WITH 8086 PROBLEM

EXAMPLE 1:
EXAMPLE 2:
 3. SERIAL COMMUNICATION INTERFACE (8251)

UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER

TRANSMITTER(USART)

o Programmable chip designed for synchronous and asynchronous serial data transmission
o 28 pin DIP
o Converts the parallel data into a serial stream of bits suitable for serial transmission.
o Receives a serial stream of bits and convert it into parallel data bytes to be read
by a microprocessor

8251 PIN DIAGRAM /8251 SIGNALS

o Data Bus: Bi-directional, tri-state, 8-bit Data Bus. This pin allows transfer of bytes
between the CPU and the 8251A.
o RD (Read): A low on this input allows the CPU to read data or status bytes from 8251A
o WR (Write): A low on this input allows the CPU to write data or command
word to the8251A.
o CLK (Clock): The CLK input is used to generate internal device timing.
o RESET: A high on this input forces the 8251A into an “Idle” mode.
o C/D (Control /Data): This input in conjunction with the WR and RD inputs, informs the
8251A that the word on the Data Bus is either data character control word or status
information.
o CS (Chip Select): A low on this input allows communication between CPU and 8251A.
o Modem Control Signals :
 DSR (Data Set Ready): This input signal is used to test modem
conditions such as Data Set Ready.
 DTR (Data Terminal Ready): This output signal is used to tell modem
that Data Terminal is ready.
 RTS (Request to Send): This output signal is asserted to begin transmission.
 CTS (Clear to Send) : A low on this input enables the 8251A to
transmit serial data if the TxE bit in the command byte is set to a
“one”.
o Transmitter Signals :
 TxD: Transmit data: This output signal outputs a composite serial
stream of data on the falling edge of TxC.
 TxRDY (Transmitter Ready): This output signal indicates the CPU that
the transmitter is ready to accept a data character.
 TxE (Transmitter Empty) : This output signal indicates that the transmitter
has no character to transmit.
 TxC (Transmitter Clock) : This clock input controls the rate at which
the character is to be transmitted.

o Receiver Signals :
 RxD (Receiver data) : This input receives a composite serial stream of data
on the rising edge of RxC.
 RxRDY (Receiver Ready) : This output indicates that the 8251 Pin
Diagram contains a character that is ready to be input to the CPU.
 RxC (Receiver Clock) :This clock input controls the rate at which
the character is to be received.
 o SYNDET (Sync Detect)/ BRKDET (Break Detect): This pin is used in synchronous
mode for detection of synchronous characters and may be used as either input or
output.

8251 BLOCK DIAGRAM/ARCHITECTURE

The 8251 consists of 5 sections.

1. Read/Write Control Logic
2. Transmitter
3. Receiver
4. Data Bus Buffer
5. Modem Controller

Read/Write Control Logic :

o Interfaces the chip with MPU
o Determine the functions according to the control word
o Monitors data flow

Transmitter :
o Accepts parallel data and converts it into serial data
o Two registers
o Buffer Register - To hold eight bits
o Output Register - Converts eight bits into a stream of serial bits
 o Transmits data on TxD pin with appropriate framing bits(Start and Stop)
o Signals associated with Transmitter section :
o TxD – Transmit Data
– Serial bits are transmitted on this line
o TxC – Transmitter Clock
– Controls the rate at which bits are transmitted
o TxRDY – Transmitter Ready
– Can be used either to interrupt the MPU or indicate the status
o TxE – Transmitter Empty
– Logic 1 on this line indicate that the output register is empty
Receiver :
o Accepts serial data from peripheral and converts it into parallel data
o The section has two registers :
o Input Register
o Buffer Register
o Signals associated with Receiver Section :
o RxD – Receive Data
- Bits are received serially on this line and converted into parallel
bytein the receiver input
o RxC – Receiver Clock
o RxRDY – Receiver Ready
- It goes high when the USART has a character in the buffer
register and is ready to transfer it to the MPU.

Data Bus Buffer :

o Data Bus is a 8 bit Bidirectional bus.
o It allows transfer of bytes between the CPU and the 8251A.

Modem Controller :
o Used to establish data communication modems over telephone line
o Signals associated with Modem Controller Section :
– DSR (Data Set Ready): This input signal is used to test modem conditions such
as Data Set Ready.
– DTR (Data Terminal Ready): This output signal is used to tell modem that
Data Terminal is ready.
– RTS (Request to Send): This output signal is asserted to begin transmission.
– CTS (Clear to Send) : A low on this input enables the 8251A to transmit serial
data if the TxE bit in the command byte is set to a “one”.

OPERATING MODES OF 8251 / CONTROL WORDS

Operating Modes of 8251: - 2 modes
1. Asynchronous mode
2. Synchronous mode

Asynchronous Mode (Transmission)

When a data character is sent to 8251A by the CPU, it adds start bits prior to the serial data bits, followed
by optional parity bit and stop bits using the asynchronous mode instruction control word format. This
sequence is then transmitted using TXD output pin on the falling edge of TXC.
Asynchronous Mode (Receive)

A falling edge on RXD input line marks a start bit. The receiver requires only one stop bit to mark end of
the data bit string, regardless of the stop bit programmed at the transmitting end. The 8-bit character is then
loaded into the into parallel I/O buffer of 8251.

RXRDY pin is raised high to indicate to the CPU that a character is ready for it. If the previous character
has not been read by the CPU, the new character replaces it, and the overrun flag is set indicating that the
previous character is lost.

The control words of Block Diagram of 8251 Microcontroller are split into two formats.
 Mode instruction (Setting of Function)
 Command instruction (Setting of Operation)
 8251 Mode Register – Asynchronous Mode Format

Synchronous Mode (Transmission)

The TXD output is high until the CPU sends a character to 8251 which usually is a SYNC character. When
CTS line goes low, the first character is serially transmitted out. Characters are shifted out on the falling
edge of TXC .Data is shifted out at the same rate as TXC , over TXD output line. If the CPU buffer
becomes empty, the SYNC character or characters are inserted in the data stream over TXD output.

Synchronous Mode (Receiver)

In this mode, the character synchronization can be achieved internally or externally. The data on RXD pin
is sampled on rising edge of the RXC. The content of the receiver buffer is compared with the first SYNC
character at every edge until it matches. If 8251 is programmed for two SYNC characters, the subsequent
received character is also checked. When the characters match, the hunting stops. The SYNDET pin set
high and is reset automatically by a status read operation. In the external SYNC mode, the synchronization
is achieved by applying a high level on the SYNDET input pin that forces 8251 out of HUNT mode. The
high level can be removed after one RXC cycle. The parity and overrun error both are checked in the same
way as in asynchronous mode.
 8251 Mode Register – Synchronous Mode Format

8251 Command Register

The command instruction controls the actual operations of the selected format like enable transmit/receive,
error reset and modem control. A reset operation returns 8251 back to mode instruction format.
8251 Status Register
This definition is used by the CPU to read the status of the active 8251 to confirm if any error condition or other
conditions like the requirement of processor service has been detected during the operation.
 4. INTERRUPT CONTROLLER (8259)

The 8259 is known as the Programmable Interrupt Controller (PIC) microprocessor. In 8085 and
8086 there are five hardware interrupts and two hardware interrupts respectively. By adding 8259,
we can increase the interrupt handling capability. This chip combines the multi-interrupt input
source to single interrupt output. This provides 8-interrupts from IR0 to IR7.

Features of Intel 8259 PIC are as follows:

1. Intel 8259 is designed for Intel 8085 and Intel 8086 microprocessor.
2. It can be programmed either in level triggered or in edge triggered interrupt level.
3. We can mask individual bits of interrupt request register.
4. We can increase interrupt handling capability upto 64 interrupt level by cascading further 8259 PICs.
5. Clock cycle is not required.

Pin Diagram / Signals of 8259

PIN Name Description and Purposes

Vcc and Gnd It is the Power supply and ground pins. +5V power supply is used in this chip.

D7-D0 For communication with the processor, there are Eight bi-directional data pins.

RD’ It is an active low control input line. It is used to read contents of the internal registers. It is
connected to IOR’ or MEMR’ of the system bus.

WR’ It is an active low-input pin which is activated by the processor to write the control information to
8259. It is connected to IOWR’ or MEMW’ of the system bus.

CS’ For selecting the chip it is used an active low input pin.

A0 An address input pin used along with RD* and WR* which is used to identify the various command
 PIN Name Description and Purposes

words. It is connected to one of the address lines of the system address bus.

IR0-IR7 There are Eight asynchronous interrupt request inputs. These signals are generated by peripherals.
These interrupt requests can be programmed for level-trigger or edge-triggered mode.

INT A strong active high-output pin which interrupts the processor. Always connected to the INTR
interrupt input of 8085. The INT output is only activated when the interrupt request is valid.

INTA’ It is termed as an active low-input pin. The 8259 receives the signal from INTA* to the output of
8086. 8086 sends the two consecutive INTA* signals, the 8259 sends a 3-byte CALL instruction to
the 8086 via D7-0 pins. The two bytes termed as second and third bytes of the CALL instruction
contains the ISS address which depends on the IR input of 8259 that is going to be serviced.

CAS:2-0 These are bi-directional 3-bit cascaded lines. Used only when there are multiple 8259s in the
system. The interrupt control system might have a master 8259 and maximum eight Slave 8259s.
In master mode, these lines function as output lines. In this mode, the PIC places a 3-bit slave
identification number on cascade lines.

SP’ /EN’ SP’/EN’ stands for “slave program/enable buffer”. This pin serves dual function. In non buffered
mode, it functions as SP’ input line. SP’ is used to distinguish between master and slave PICs. In
buffered mode it functions as an EN’ output line. In this mode, it is used to enable data buffers.
Block Diagram of 8259

Block Description

Data Bus Buffer This block is used to communicate between 8259 and 8085/8086 by acting
as buffer. It takes the control word from 8085/8086 and send it to the 8259.
After selection of Interrupt by 8259 (based on priority of the interrupt), it
transfers the opcode of the selected interrupts and address of ISR to the
other connected microprocessor. It can send maximum 8-bit at a time.

R/W Control Logic This block works when the value of pin CS is 0. This block is used to flow
 Block Description

the data depending upon the inputs of RD and WR. These are active low
pins for read and write.

Control Logic It controls the functionality of each block. It has pin INTR which is
connected with other microprocessors for taking the interrupt request. The
INT pin is used to give the output. If 8259 is enabled, and also the interrupt
flags of other microprocessors are high then this causes the value of the
output INT pin high, and in this way 8259 responds to the requests made
by other microprocessors.

Interrupt Request This unit stores the interrupt requests generated by the peripheral devices
Register that are requesting the service from the processor.

Interrupt Service This register unit stores the interrupts which are currently being executed
Register by the processor.

Interrupt Mask Register It is a programmable register. It is used to mask unwanted interrupt

requests, by writing appropriate command words.

Priority Resolver This logic unit decides that among all the interrupt request present in the
IRR which holds the highest priority and needs to be executed first.

Cascade Buffer To increase the Interrupt handling capability, we can cascade more number
of pins, by using cascade buffer. When we are going to increase the
interrupt capability, CAS lines are used to control multiple interrupts.
It permits the operation of the system in two modes: master
mode and slave mode.
In the master mode of operation, it acts as a cascaded buffer. Whereas in
slave mode, this unit acts as a comparator.
Programming 8259A (Command Words of 8259)
The 8259 Programmable Interrupt Controller requires two types of command words.
 Initialization Command Words (ICWs) and
 Operational Command Words (OCWs).

Initialization command words(ICW) :

 ICW is given during the initialization of 8259 i.e. before its start functioning.
 ICW1 and ICW2 commands are compulsory for initialization.
 ICW3 command is given during a cascaded configuration.
 If ICW4 is needed, then it is specified in ICW1.
 The sequence order of giving ICW commands is fixed i.e. ICW1 is given first and then ICW2 and
then ICW3.
 Any of the ICW commands can not be repeated, but the entire initialization process can be repeated
if required.
Operating command words(OCW) :
 OCW is given during the operation of 8259 i.e. microprocessor starts using 8259.
 OCW commands are not compulsory for 8259.
 The sequence order of giving OCW commands is not fixed.
 The OCW commands can be repeated.
Initialization sequence of 8259 :

Initialization Command Word 1 (ICW1):

A write command issued to the 8259 with A0 = 0 and D4 = 1 is interpreted as ICW1, which starts the initialization
sequence. It specifies,

1. Single or multiple 8259As in the system

2. 4 or 8 bit interval between the interrupt vector locations.
3. The address bits A7 – A5 of the CALL instruction. (3 bits of lower byte address of CALL are
given by user, rest bits are inserted by 8259A)
4. Edge triggered or level triggered interrupts.
5. ICW4 is needed or not.
Initialization Command Word 2 (ICW2):

A write command following ICW1, with A0 = 1 is interpreted as ICW2. This is used to load the high order byte of
the interrupt vector address of all the interrupts.

Initialization Command Word 3 (ICW3):

ICW3 command word is used when there is more than one 8259 present in the system i.e. when SNGL bit in
ICW1 is 0, then it will load 8-bit slave register.

Initialization Command Word 4 (ICW4):

It is loaded only, if the D0 bit of ICW1 is seta The format of ICW4 is shown in Fig. 14.79.

It specifies,

 Whether to use special fully nested mode or non special fully nested mode.
 Whether to use buffered mode or non buffered mode.
 Whether to use Automatic EOI or Normal EOI.
 CPU used, 8086/8088 or 8085.
Operation Command Word 1 (OCW 1):

It is used to set and reset the mask bits in IMR(interrupt mask register). M7 – M0 describes 8 mask bits

Operation Command Word 2 (OCW2):

A Write command with A0 = 1 and D4 D3 = 00 is interpreted as OCW2. The R (Rotate), SL (Select-Level), EOI
bits control the Rotate and End Of Interrupt Modes and combinations of the two. L 2-L0 are used to specify the
interrupt level to be acted upon when the SL bit is active.
Operation Command Word 3 (OCW3):

OCW3 is used to read the status of the registers; and to set or reset the Special Mask and Polled modes.
8259 Status Read Operations:

The status of the Interrupt Request Register, the Interrupt-Service Register, and the Interrupt Mask Regiter of the
8259 may be read by issuing appropriate Read commands as described further.

IRR Status Read:

An OCW3 with RR (Read Register) = 1 and RIS (Read ISR) = 0 set up the 8259 for a status read of the Interrupt
Request Register.

When the 8259 is not in the Polled mode, after it is set up for. an IRR status read operation, all Read commands
with A0=1 cause the 8259 to send the IRR status word.

ISR Status Read:

An OCW3 with RR = 1 and ISR = 1 sets up the 8259 for a status read of the Interrupt-Service Register. A
subsequent read command issued to the 8259 will cause the 8259 to send the contents of the ISR onto the data
bus.

IMR Status Read:

A Read command issued to the 8259 Programmable Interrupt Controller with A0 = 1 (with RD, CS = 0 ) causes
the 8259 to put the contents of the Interrupt Mask Register on the data bus. OCW3 is not required for a status read
of the IMR.

Operating Modes of 8259

The various Operating Modes of 8259 Programmable Interrupt Controller are :

1. Fully Nested Mode of 8259,

2. Special Fully Nested Mode in 8259 (SFNM)
3. Rotating Priority Mode of 8259,
4. Special Mask Mode in 8259, and
5. Polled Mode in 8259.
1.Fully nested mode :
 It is the default mode of operation of 8259.
 Here, IR0 has the highest priority and IR7 has the lowest priority. When any interrupt requests
occurs then the highest priority interrupt request is serviced first and its vector address is placed on
data bus and its corresponding bit in ISR register is set until the processor executes the EOI
command before returning the interrupt service routine or AEOI(Automatic end of interrupt bit is
set) until the falling of the last INTA’.
 When the ISR bit is set for an interrupt, then all the equal and lower priority interrupts are masked,
but a higher level interrupt request can occur and which will be acknowledged only if the
microprocessor interrupt enables flag IF= 1.
 It is suitable for a single 8259 configuration.
 The priority mechanism can be easily programmed.

2. Special fully nested mode (SFNM) :

This mode is used by master 8259 in a cascaded mode. Its priority structure is fixed and is the same as fully
nested mode (i.e. IR0 has the highest priority and IR7 has the lowest priority).
In a special fully nested mode, the master will only serve higher priority interrupt from a slave, whose another
interrupt is currently in service.
3. Rotating priority modes :
There are two rotating priority modes –
1. Automatic rotation mode
 It is used when various interrupt sources are of the same priority. In this mode, after a device is
serviced, it gets the lowest priority. All other priorities rotate according to it.
 Example: If IR4 has just been serviced, it will get the lowest priority.
2. Specific Rotation Mode
 Here, the programmer can alter priorities by programming the lowest priority and thus fixing all
other priorities.
 For example: If IR6 is programmed as the lowest priority, then IR7 will have the highest priority.

4. Special mask mode (SMM) :

In SMM, 8259 enables interrupts of all levels (lower or higher) except the one that is currently in service.
Because we are especially masking the request of the priority level of interrupt, which is the same asthe
current interrupt priority level, therefore it is called special mask mode.

5. Poll mode :
In this mode the INT output is not used. The microprocessor checks the status of interrupt requests by issuing poll
command. The microprocessor reads contents of 8259A after issuing poll command. During this read operation
the 8259A provides polled word and sets ISR bit of highest priority active interrupt request FORMAT.

5. DMA CONTROLLER (8257)

DIRECT MEMORY ACCESS (DMA ) CONTROLLER (8257):

It is designed by Intel to transfer data at the fastest rate. It allows the device to transfer the data directly
to/from memory without any interference of the CPU. Using a DMA controller, the device requests the CPU
to hold its data, address and control bus, so the device is free to transfer data directly to/from the memory.
The DMA data transfer is initiated only after receiving HLDA signal from the CPU.

The sequences of operations performed by a DMA are

 Initially, when any device has to send data to the memory, the device has to send DMA
request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to assert
the HLDA signal.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
 will relinquish the bus and acknowledges the HOLD request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations over
buses between the memory interfaced with Microprocessor and I/O devices.

FEATURES OF 8257
 It has four channels that can be used over four I/O devices.
 Each channel has 16-bit address and 14-bit counter.
 Each channel can transfer data up to 64 KB.
 Each channel can be programmed independently.
 Each channel can perform read transfer, write transfer and verify transfer operations.
 It operates in 2 modes, i.e., Master mode and Slave mode.

8257 PIN DESCRIPTION

The pin configuration of DMA Controller (8257) is shown in Figure 3and the descriptions are as follows:

DRQ0−DRQ3
These are the four individual channel DMA request inputs, which are used by the peripheral devices for
using DMA services. When the fixed priority mode is selected, then DRQ0 has the highest priority and DRQ3
has the lowest priority.

DACK0 − DACK3
These are the active-low DMA acknowledge lines, which updates the requesting peripheral about the
status of their request by the CPU. These lines can also act as strobe lines for the requesting devices.

D0 − D7
These are bidirectional, data lines which are used to interface the system bus with the internal data bus
of DMA controller. In the Slave mode, it carries command words to 8257 and status word from 8257. In the
master mode, these lines are used to send higher byte of the generated address to the latch. This address is
further latched using ADSTB signal.
 IOR
It is an active-low bidirectional tri-state input line, which is used by the CPU to read internal registers of
8257 in the Slave mode. In the master mode, it is used to read data from the peripheral devices during a
memory write cycle.

IOW
It is an active low bi-direction tri-state line, which is used to load the contents of the data bus to the 8-bit
mode register or upper/lower byte of a 16-bit DMA address register or terminal count register. In the master
mode, it is used to load the data to the peripheral devices during DMA memory read cycle.
CLK
It is a clock frequency signal which is required for the internal operation of 8257.

RESET
This signal is used to RESET the DMA controller by disabling all the DMA channels.

A0 - A3
These are the four least significant address lines. In the slave mode, they act as an input, which selects
one of the registers to be read or written. In the master mode, they are the four least significant memory address
output lines generated by8257.

CS
It is an active-low chip select line. In the Slave mode, it enables the read/write operations to/from
8257. In the master mode, it disables the read/write operations to/from 8257.

READY
It is an active-high asynchronous input signal, which makes DMA ready by inserting wait states.

HRQ
This signal is used to receive the hold request signal from the output device. In the slave mode, it is
connected with a DRQ input line 8257. In Master mode, it is connected with HOLD input of the CPU.
HLDA
It is the hold acknowledgement signal which indicates the DMA controller that the bus has been granted
to the requesting peripheral by the CPU when it is set to1.

MEMR
It is the low memory read signal, which is used to read the data from the addressed memory locations
during DMA read cycles.

MEMW
It is the active-low three state signal which is used to write the data to the addressed memory location
during DMA write operation.

ADSTB

It is a control output line used to split data and address line through latches.

AEN
This signal is used to disable the address bus/data bus.
 TC
It stands for ‘Terminal Count’, which indicates the present DMA cycle to the present peripheral
devices.

MARK
The mark will be activated after each 128 cycles or integral multiples of it from the beginning. It
indicates thecurrent DMA cycle is the 128th cycle since the previous MARK output to the selected
peripheral device.
Vcc
It is the power signal which is required for the operation of the circuit.

INTERNAL ARCHITECTURE OF 8257:

The functional Block Diagram of DMA controller(8257) is shown in Figure and the description are as follows:
Itconsists of five functional blocks:
1. Data bus buffer
2. Control logic
3. Read/write logic
4. Priority Resolver
5. DMA channels

Data Bus Buffer:

It has 8-bit Tristate, bidirectional buffer interfaces the internal bus of 8257 with the external system bus under
the control of various control signals.

Read/Write Logic:
In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals, decodes the Ao-A3 lines
and either writes the contents of the data bus to the addressed internal register or reads the selected register
dependingupon whether IOW or IOR signal is activated. In master mode, the read/write logic generates the IOR and
IOW signals to control the dataflow to or from the selected peripheral.

Control Logic:
The control logic controls the sequences of operations and generates the required control signals like AEN,
ADSTB, MEMR,MEMW, TC and MARK along with the address lines A4-A7, in master mode.

Priority Resolver:
The priority resolver resolves the priority of the four DMA channels depending upon whether normal
priority or rotating priority is programmed.
DMA CHANNELS / Register Organization of 8257:
The 8257 performs DMA operation over four independent DMA channels with thefollowing Registers.
 6. APPLICATIONS OF 8255 – TRAFFIC LIGHT CONTROLLER
 Traffic light controller interface module is designed to simulate the function of four way traffic light
controller.
 Combinations of red, amber and green LEDs are provided to indicate Halt, Wait and Go signals for
vehicles.
 Combination of red and green LEDs are provided for pedestrian crossing.
 36 LEDs are arranged in the form of an intersection.
 A typical junction is represented in the Figure.
 Each road is named North (N), South (S), East (E) and West ( W).
LED ARRANGEMENTS

 At the left corner of each road, a group of five LEDs (Red, Amber and 3 Green) are arranged in the
form of a T-section to control the traffic of that road.
 LED’s L1, L10, L19 & L28 (Red) are for the stop signal for the vehicles on the road N, S, W, & E
respectively. 
 L2, L11, L20 & L29 (Amber) indicates wait state for vehicles on the Road N, S, W, & E
respectively. 
 L3, L4 & L5 (Green) are for left, strait and right turn for the vehicles on road S.
 Similarly, L12-L13-L14(Green), L23-L22-L21(Green) & L32-L31-L30(Green) simulates same
function for the roads E, N, W respectively. 
 A total of 16 LED’s (2 Red & 2 Green at each road) are provided for pedestrian crossing. 
 L7-L9. L16-L18, L25-L27 & L34-L36 (Green) when ON allows pedestrians to cross.
 L6- L8, L15-L17, L24-L26 & L33-L35 (Red) when ON alarms the pedestrians to wait.

INTERFACING WITH 8255

 To minimize the hardware pedestrian’s indicator LEDs (both red and green are connected to
same port lines (PC4 to PC7) with red inverted.
 Red LEDs L10 & L28 are connected to port lines PC2 & PC3 while L1 & L19are connected to
lines PC0 & PC1 after inversion. All other LED’s (amber andgreen) are connected to port A & B.

WORKING

 8255 is interfaced with 8086 in I/O mapped I/O and all ports are output ports.
 The working assumes no entry of vehicles from North to West, from road East to South.
 At the beginning , all red LEDs are switched ON, and all other LEDsare switched OFF.
 Amber LED is switched ON before switching over to proceed state from Halt state.
The sequence of traffic followed is given below.
 From road north to East, from road east to north, from road south to west from roadwest to south, from
road west to north.
 From road north to East, from road south to west, from road south to north, fromroad south to east,
from road north to south, from road south to north. 
 Pedestrian crossing at roads west & east.
 From road east to west, from road west to east, pedestrian crossing at roads north& south.

7.APPLICATIONS OF 8255 - LED DISPLAY

o Light Emitting Diodes (LED) is the most commonly used components, usually for
displaying pins digital states.

o Typical uses of LEDs include alarm devices, timers and confirmation of user input such
as a mouse click or keystroke.

o LED Displays are available in two very common formats.

1. 7 segment displays
2. 5 by 7 dot-matrix displays

Seven-Segment displays
o 7 segment displays are generally used as numerical indicators and consists of a number
of LEDs arranged in seven segments.
o Any number between 0 to 9 can be indicated by lighting the appropriate segments.
o The seven segments are labeled a to g and dot is labeled as h.
o By forward biasing different LED segments, we can display the digits 0 through 9.

o LED indicators are of two type’s namely - common anode type and common cathode type.
o In a common anode type all the anodes are connected together.
o In a common cathode type all the cathodes are connected together
o Anode is connected through a resistor to GND & the Cathode is connected to the
Microprocessor pin.
o When the Port Pin is HIGH the LED is OFF & when the Port Pin LOW, the LED is turned ON.
 Common Anode Type Common Cathode Type

Interfacing LED
o We now want to flash a LED.
o It works by turning ON a LED & then turning it OFF & then looping back to START.
o A delay is generated between the flashing of LEDs.

o For common anode, when anode is connected to positive supply, a low voltage is applied
to a cathode to turn it on.
o Here BCD to seven segment decoder, IC7447 is used to apply low voltages at cathodes
according to BCD input applied to 7447.
o To limit the current through LED segments resistors are connected in series with the segments.

Port Pin assignment with 8086

Interfacing LED with 8255