2018 International Conference on Field-Programmable Logic and Applications

Demonstration of Object Detection for Event-driven

Cameras on FPGAs and GPUs
Masayuki Shimoda Shimpei Sato Hiroki Nakahara
Tokyo Institute of Technology, Japan Tokyo Institute of Technology, Japan Tokyo Institute of Technology, Japan
Email:shimoda@reconf.ict.e.titech.ac.jp Email: satos@ict.e.titech.ac.jp Email: nakahara@ict.e.titech.ac.jp

I. A BSTRACT




 
We demonstrate an object detection system using a sliding
window method for an event-driven camera[3] which outputs a
subtracted frame (usually a binary value) when changes are de-  

tected in captured images. Fig. 1 shows the overall architecture   
   




 
   
  


   

   

of the object detector using a sliding window. First, our system       

extracts the object region candidates by applying a sliding

window to the picture output by an event-driven camera. Since Fig. 1. Overview of an object detector system using sliding window for an
the event-driven camera outputs are binary, the sliding window event-driven camera
determines whether an object exists or not based on the

proportion of white pixels inside the bounding box as shown in
 

 

 

 





Fig. 2. It reduces the number of proposed regions from 1,485

to average 10. The extracted pictures are resized to 40 × 40  


size and applied to the ABCNN (All Binarized Convolutional
Neural Network[7]), which is a BCNN (Binarized Convo- 

 

 

 





lutional Neural Network[4]) in which the first convolutional 







layer is done in binary form as well. All binarization is found
to improve both the area and computation time, while the
Fig. 2. Sliding window using an event-driven camera
classification accuracy decreases. If the ABCNN infers the
detected object as human, then it draws a box on the proposed
region. Since more than one bounding box is commonly drawn identify object region candidates. Since this scan is typically
against a single detected object, non-maximum suppression performed on RGB three-channel pictures, all regions are
is used to reduce the extras to a single box. The proposed normally selected. However, when an event-driven camera is
system is implemented on an FPGA and a GPU to show the used, the picture is output in binary form and candidate regions
comparison of them. are only proposed when the ratio of white pixels exceeds a
certain threshold. This leads to a significant reduction in CNN
II. E VENT-D RIVEN C AMERA
computation requirements. In the case of the pedestrian dataset
An event-driven camera is a camera that only outputs a used in this paper, the number of RGB picture candidates is
picture when the captured image changes. Such cameras work normally in the thousands, while a binary bitmap picture is
by extracting contrast differences between two successive used, the number drops to between zero and 20.
frames. If no object motions are detected, then the camera does
not output anything. Once motions are observed, the camera IV. A LL BINARIZED CNN
subtracts the background with the reference image stored in An ABCNN is a BCNN in which the first convolutional
pixel memory, converts the input into binary form by using a layer is done in binary form as well. Since it does not require
preset threshold, and then outputs the binary images. Use of a multi-bit precision convolutional layer to process the input
an event-based sensor leads to a reduction in input/output (IO) data, all computations can be done in binary. To realize an
energy when compared with a frame-based camera. One of ABCNN, it is necessary to use another method to decompose
the more practical use scenarios of an event-driven camera is the input data into binary form. It reduces resource and energy
security monitoring. expenditures while increasing performance and providing a
comparable level of accuracy.
III. S LIDING WINDOW
One of the commonly used object region methods is called V. DATASET P REPARATION
the sliding window. A bounding box moves along the dx Since there is currently no dataset available for the output
and dy axes from top left to down right on the picture to of an event-driven camera, it is necessary to make an imitation

978-1-5386-8517-4/18/$31.00 ©2018 IEEE 461

DOI 10.1109/FPL.2018.00090
 Shift Register (2L+K)
ARM Cortex A-9 Processor DDR3 Memory
x00 x01 x02 x03 x04 x22 x21 x20 x14 x13 x12 x11 x10 x04 x03 x02 x01 x00
x10 x11 x12 x13 x14
AXI-BUS x20 x21 x22 x23 x24 Binarized MACs
x30 x31 x32 x33 x34 (EXNORs + Adder Tree)
Weight x40 x41 x42 x43 x44 Sign
Cache Write
Binarized Parallel Pipelined
Binarized Feature Map
(L=5, K=3)
+ Bit
Ctrl
Logic

Re g i s t e r
F.map In F. Binary
map 2D Convoluonal
Counter
On- Integer Buffer Binarized Integer
Circuit
Chip Weight Bias
Bias Bias Mem 1 Mem 1
Mem. Buffer

Sh i f t
Sign
Write
Binarized
Max-Pooling (OR gate) + Bit
Ctrl
Logic

Binarized Ave-Pooling Counter

(1’s counter)
Binarized Integer
Weight Bias
Mem 2 Mem 2

Fig. 3. Overall architecture

Fig. 4. Parallel pipelined binarized 2D convolutional circuit

dataset. Accordingly, we referred to an existing work[3] and

created a dataset using the following procedure: realized by Chainer. The experimental results are shown in
Table. I. The GPU system power consumption was 2.5 watts
1) Convert three-channel RGB into grayscale
while the FPGA consumed only 0.2 watts, thus indicating that
2) Let po be a base pixel value, pn be a pixel value above
our proposed method achieves a 92% power reduction. As
the base pixel, pe be a pixel value on the right of the
for performance, the FPGA system was 4.3 times faster than
base pixel. Then, apply the following conversion:
the comparable GPU system, and regarding performance per
max(|pE − po |, |pN − po |) power consumption (FPS/W), the FPGA was 54.2 times higher
Vs = ,
max(pE , po , pN ) than the GPU. Thus, our proposed method is more suitable for
where Vs is an intermediate value. the embedded systems based on cameras with fixed angles and
3) By using the following threshold, we convert the inter- position (such as security cameras).
mediate value into binary:
TABLE I
Vo = sgn(Vs − Vth ), E VALUATE EVENT- BASED OBJECT DETECTION SYSTEM

Mobile GPU FPGA

where Vo is a converted pixel value on the base pixel.
Platform Jetson TX2 zcu102
Using the above steps, RGB three-channel 8-bit width images Speed [avg. FPS] 3.0 13.0
were converted into bitmap images. Power [watts] 2.5 0.2
Efficiency [FPS/watt] 1.2 65.0
VI. I MPLEMENTED C IRCUIT
Fig. 3 shows the overall circuit[5]. Since the on-chip R EFERENCES
BRAMs realize the memory part of the architecture, this
[1] PETS 2009 Benchmark Data,
circuit provides increased power efficiency. Since a binarized http://www.cvg.reading.ac.uk/PETS2009/a.html
convolutional circuit is shared among all convolutional layers, [2] Chainer: A powerful, flexible, and intuitive framework of neural net-
this circuit achieves a reduction in area. We improved conven- works, http://chainer.org/
[3] L. Benini, “Deep Learning with Low Precision Hardware”,
tional binarized convolutional circuit[8] to make it possible to http://si.epfl.ch/files/content/sites/si/files/shared/Logic2017.
compute MACs in parallel. Fig. 4 shows the parallel kernel [4] M. Courbariaux, I. Hubara, D. Soudry, R.E.Yaniv, Y. Bengio, “Binarized
computation circuit. Since the kernel number of each layer neural networks: Training deep neural networks with weights and activa-
tions constrained to +1 or -1”, Computer Research Repository (CoRR),
used in this paper is fixed at 64, we create a convolutional 2016.
circuit that has two binarized MAC circuits to compute in [5] H. Nakahara, T. Fujii and S. Sato,“A Fully Connected Layer Elimination
parallel, and then we also confirmed this improvement does for a Binarized Convolutional Neural Network on an FPGA, ”FPL, pp.1-
4, 2017.
not affect the area significantly. [6] H. Nakahara, H. Yonekawa, T. Fujii, M. Shimoda and S. Sato, “ A
demonstration of the GUINNESS: A GUI based neural NEtwork Syn-
VII. D EMONSTRATION theSizer for an FPGA, ”FPL, pp.1, 2017.
[7] M. Shimoda, S. Sato, and H. Nakahara, “ All Binarized Convolutional
We demonstrate an ABCNN with a software emulated Neural Network and Its implementation on an FPGA, ”The International
event-driven camera on a zcu102 FPGA evaluation board Conference on Field-Programmable Technology (FPT 2017), pp.291-
and a Jetson TX2 GPU (NVIDIA Corp.) using the PETS 294, 2017.
[8] H. Yonekawa and H. Nakahara, “An On-chip Memory Batch Normaliza-
2009 Benchmark Data[1]. We developed the ABCNN circuit tion Free Binarized Convolutional Deep Neural Network on an FPGA”,
using the GUINNESS[6] development environment based on IPDPS, pp. 98-105, 2017.
Chainer[2] that generates base circuit, and GPU model is

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