TPS2044, TPS2054

QUAD POWER-DISTRIBUTION SWITCHES

SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

D 135-mΩ -Maximum (5-V Input) High-Side TPS2044

D PACKAGE
MOSFET Switch (TOP VIEW)
D 500 mA Continuous Current per Channel
D Short-Circuit and Thermal Protection With
GND1
IN1
1
2
16
15
OC1
OUT1
Overcurrent Logic Output
EN1 3 14 OUT2
D Operating Range . . . 2.7-V to 5.5-V EN2 4 13 OC2
D Logic-Level Enable Input GND2 5 12 OC3
D 2.5-ms Typical Rise Time IN2 6 11 OUT3
D Undervoltage Lockout EN3 7 10 OUT4

D 20-µA-Maximum Standby Supply Current

EN4 8 9 OC4

D Bidirectional Switch TPS2054

D 16-pin SOIC Package D PACKAGE
(TOP VIEW)
D Ambient Temperature Range, –40°C to 85°C
D 2-kV Human-Body-Model, 200-V GND1 1 16 OC1
Machine-Model ESD Protection IN1 2 15 OUT1

D UL Listed – File No. E169910

EN1
EN2
3
4
14
13
OUT2
OC2
GND2 5 12 OC3
description
IN2 6 11 OUT3
The TPS2044 and TPS2054 quad power- 7 10 EN3 OUT4
distribution switches are intended for applications 8 9 EN4 OC4
where heavy capacitive loads and short circuits
are likely to be encountered. The TPS2044 and the TPS2054 incorporate in single packages four 135-mΩ
N-channel MOSFET high-side power switches for power-distribution systems that require multiple power
switches. Each switch is controlled by a logic enable that is compatible with 5-V logic and 3-V logic. Gate drive
is provided by an internal charge pump that controls the power-switch rise times and fall times to minimize
current surges during switching. The charge pump, requiring no external components, allows operation from
supplies as low as 2.7 V.
When the output load exceeds the current-limit threshold or a short is present, the TPS2044 and TPS2054 limit
the output current to a safe level by switching into a constant-current mode, pulling the overcurrent (OCx) logic
output low. When continuous heavy overloads and short circuits increase the power dissipation in the switch
causing the junction temperature to rise, a thermal protection circuit shuts off the switch to prevent damage.
Recovery from a thermal shutdown is automatic once the device has cooled sufficiently. Internal circuitry
ensures the switch remains off until valid input voltage is present.
The TPS2044 and TPS2054 are designed to limit at 0.9-A load. These power-distribution switches are available
in 16-pin small-outline integrated-circuit (SOIC) packages and operate over an ambient temperature range of
–40°C to 85°C.
AVAILABLE OPTIONS
RECOMMENDED PACKAGED DEVICES
TYPICAL SHORT-CIRCUIT
MAXIMUM CONTINUOUS
TA ENABLE CURRENT LIMIT AT 25°C SOIC
LOAD CURRENT
(A) (D)†
(A)
–40°C to 85°C Active low 0.5 0.9 TPS2044D
–40°C to 85°C Active high 0.5 0.9 TPS2054D
† The D package is available taped and reeled. Add an R suffix to device type (e.g., TPS2044DR)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Copyright  1999, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

TPS2044 functional block diagram

OC1

GND1 Thermal
Sense

EN1

Current
Driver
Limit
Charge
Pump
†
CS OUT1
UVLO
Power Switch

†
IN1 CS OUT2

Charge
Pump
Current
Driver
Limit
OC2
EN2
Thermal
Sense

OC3

GND2 Thermal
Sense

EN3

Current
Driver
Limit
Charge
Pump
†
CS OUT3
UVLO
Power Switch

†
IN2 CS OUT4

Charge
Pump
Current
Driver
Limit
OC4
EN4
Thermal
Sense

† Current sense

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

Terminal Functions
TERMINAL
NO. I/O DESCRIPTION
NAME
TPS2044 TPS2054
EN1 3 – I Enable input. logic low turns on power switch, IN1-OUT1.
EN2 4 – I Enable input. Logic low turns on power switch, IN1-OUT2.
EN3 7 – I Enable input. Logic low turns on power switch, IN2-OUT3.
EN4 8 – I Enable input. Logic low turns on power switch, IN2-OUT4.
EN1 – 3 I Enable input. Logic high turns on power switch, IN1-OUT1.
EN2 – 4 I Enable input. Logic high turns on power switch, IN1-OUT2.
EN3 – 7 I Enable input. Logic high turns on power switch, IN2-OUT3.
EN4 – 8 I Enable input. Logic high turns on power switch, IN2-OUT4.
GND1 1 1 Ground.
GND2 5 5 Ground.
IN1 2 2 I Input voltage.
IN2 6 6 I Input voltage.
OC1 16 16 O Overcurrent. Logic output active low, IN1-OUT1
OC2 13 13 O Overcurrent. Logic output active low, IN1-OUT2
OC3 12 12 O Overcurrent. Logic output active low, IN2-OUT3
OC4 9 9 O Overcurrent. Logic output active low, IN2-OUT4
OUT1 15 15 O Power-switch output, IN1-OUT1
OUT2 14 14 O Power-switch output, IN1-OUT2
OUT3 11 11 O Power-switch output, IN2-OUT3
OUT4 10 10 O Power-switch output, IN2-OUT4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

detailed description
power switch
The power switch is an N-channel MOSFET with a maximum on-state resistance of 135 mΩ (VI(INx) = 5 V).
Configured as a high-side switch, the power switch prevents current flow from OUTx to INx and INx to OUTx
when disabled. The power switch supplies a minimum of 500 mA per switch.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the power switch. To limit large current surges and reduce the associated
electromagnetic interference (EMI) produced, the driver incorporates circuitry that controls the rise times and
fall times of the output voltage. The rise and fall times are typically in the 2-ms to 4-ms range.
enable (ENx or ENx)
The logic enable disables the power switch and the bias for the charge pump, driver, and other circuitry to reduce
the supply current to less than 20 µA when a logic high is present on ENx (TPS2044) or a logic low is present
on ENx (TPS2054). A logic zero input on ENx or logic high on ENx restores bias to the drive and control circuits
and turns the power on. The enable input is compatible with both TTL and CMOS logic levels.
overcurrent (OCx)
The OCx open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
current sense
A sense FET monitors the current supplied to the load. The sense FET measures current more efficiently than
conventional resistance methods. When an overload or short circuit is encountered, the current-sense circuitry
sends a control signal to the driver. The driver in turn reduces the gate voltage and drives the power FET into
its saturation region, which switches the output into a constant current mode and holds the current constant
while varying the voltage on the load.
thermal sense
The TPS2044 and TPS2054 implement a dual-threshold thermal trip to allow fully independent operation of the
power distribution switches. In an overcurrent or short-circuit condition the junction temperature rises. When
the die temperature rises to approximately 140°C, the internal thermal sense circuitry checks to determine which
power switch is in an overcurrent condition and turns off that switch, thus isolating the fault without interrupting
operation of the adjacent power switch. Hysteresis is built into the thermal sense, and after the device has cooled
approximately 20 degrees, the switch turns back on. The switch continues to cycle off and on until the fault is
removed. The (OCx) open-drain output is asserted (active low) when overtemperature or overcurrent occurs.
undervoltage lockout
A voltage sense circuit monitors the input voltage. When the input voltage is below approximately 2 V, a control
signal turns off the power switch.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Input voltage range, VI(INx) (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Output voltage range, VO(OUTx) (see Note1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VI(INx) + 0.3 V
Input voltage range, VI(ENx) or VI(ENx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 6 V
Continuous output current, IO(OUTx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internally limited
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table
Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 125°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260°C
Electrostatic discharge (ESD) protection: Human body model MIL-STD-883C . . . . . . . . . . . . . . . . . . . . . . 2 kV
Machine model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.2 kV
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING
D 725 mW 5.6 mW/°C 464 mW 377 mW

recommended operating conditions

TPS2044 TPS2054
UNIT
MIN MAX MIN MAX
Input voltage, VI(INx) 2.7 5.5 2.7 5.5 V
Input voltage, VI(ENx) or VI(ENx) 0 5.5 0 5.5 V
Continuous output current, IO(OUTx) 0 500 0 500 mA
Operating virtual junction temperature, TJ –40 125 –40 125 °C

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TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(ENx) = 0 V, VI(ENx) = Hi (unless otherwise noted)

power switch
TPS2044 TPS2054
PARAMETER TEST CONDITIONS† UNIT
MIN TYP MAX MIN TYP MAX
VI(INx) = 5 V, TJ = 25°C,
80 95 80 95
IO = 0.5 A
Static drain-source on-state VI(INx) = 5 V, TJ = 85°C,
90 120 90 120
resistance, 5-V operation IO = 0.5 A
VI(INx) = 5 V, TJ = 125°C,
100 135 100 135 mΩ
IO = 0.5 A
rDS(
DS(on))
VI(INx) = 3.3 V, TJ = 25°C,
85 105 85 105
IO = 0.5 A
Static drain-source on-state VI(INx) = 3.3 V, TJ = 85°C,
100 135 100 135
resistance, 3.3-V operation IO = 0.5 A
VI(INx) = 3.3 V, TJ = 125°C,
115 150 115 150
IO = 0.5 A
VI(INx) = 5.5 V, TJ = 25°C,
2.5 2.5
CL = 1 µF, RL = 10 Ω
tr Rise time
time, output ms
VI(INx) = 2.7 V, TJ = 25°C,
3 3
CL = 1 µF, RL = 10 Ω
VI(INx) = 5.5 V,
TJ = 25°C,
4.4 4.4
CL = 1 µF, RL = 10 Ω
tf Fall time
time, output ms
VI(INx) = 2.7 V, TJ = 25°C,
2.5 2.5
CL = 1 µF, RL = 10 Ω
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

enable input ENx or ENx

TPS2044 TPS2054
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
VIH High-level input voltage 2.7 V ≤ VI(INx) ≤ 5.5 V 2 2 V
4.5 V ≤ VI(INx) ≤ 5.5 V 0.8 0.8 V
VIL Low level input voltage
Low-level
2.7 V≤ VI(INx) ≤ 4.5 V 0.4 0.4
TPS2044 VI(ENx) = 0 V or VI(ENx) = VI(IN) –0.5 0.5
II Input current µA
TPS2054 VI(ENx) = VI(INx) or VI(ENx) = 0 V –0.5 0.5
ton Turnon time CL = 100 µF, RL=10 Ω 20 20 ms
toff Turnoff time CL = 100 µF, RL=10 Ω 40 40

current limit
TPS2044 TPS2054
PARAMETER TEST CONDITIONS† UNIT
MIN TYP MAX MIN TYP MAX
VI(INx) = 5 V, OUT connected to GND,
IOS Short-circuit output current 0.7 0.9 1.1 0.7 0.9 1.1 A
Device enable into short circuit
† Pulse-testing techniques maintain junction temperature close to ambient temperature; thermal effects must be taken into account separately.

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

electrical characteristics over recommended operating junction temperature range, VI(IN)= 5.5 V,
IO = rated current, VI(ENx) = 0 V, VI(ENx) = Hi (unless otherwise noted) (continued)

supply current
TPS2044 TPS2054
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
TJ = 25°C 0.03 2
Su ly
Supply TPS2044
VI(ENx) = VI(INx) –40°C ≤ TJ ≤ 125°C 20
current,, No Load
µA
low-level on OUTx TJ = 25°C 0.03 2
output
t t VI(EN
I(ENx)) = 0 V TPS2054
–40°C ≤ TJ ≤ 125°C 20
TJ = 25°C 160 200
Su ly
Supply VI(ENx) = 0 V TPS2044
current,, No Load –40°C ≤ TJ ≤ 125°C 200
µA
high-level on OUTx TJ = 25°C 160 200
output
t t VI(EN
I(ENx)) = VI(IN
I(INx)) TPS2054
–40°C ≤ TJ ≤ 125°C 200

Leakage
g
OUTx VI(ENx) = VI(INx) –40°C ≤ TJ ≤ 125°C TPS2044 200
connected µA
current VI(ENx) = 0 V –40°C ≤ TJ ≤ 125°C TPS2054 200
to ground
Reverse VI(EN) = 0 V TPS2044 0.3
IN = high
g
leakage TJ = 25°C µA
impedance VI(EN) = Hi TPS2054 0.3
current

undervoltage lockout
TPS2044 TPS2054
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
Low-level input voltage 2 2.5 2 2.5 V
Hysteresis TJ = 25°C 100 100 mV

overcurrent OCx
TPS2044 TPS2054
PARAMETER TEST CONDITIONS UNIT
MIN TYP MAX MIN TYP MAX
Sink current† VO = 5 V 10 10 mA
Output low voltage IO = 5 mA, VOL(OCx) 0.5 0.5 V
Off-state current† VO = 5 V, VO = 3.3 V 1 1 µA
† Specified by design, not production tested.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

PARAMETER MEASUREMENT INFORMATION

OUTx

tr tf
RL CL
VO(OUTx) 90% 90%
10% 10%
TEST CIRCUIT

VI(ENx) 50% 50% VI(ENx) 50% 50%

ton toff ton toff

VO(OUTx) 90% VO(OUTx) 90%

10% 10%

VOLTAGE WAVEFORMS

Figure 1. Test Circuit and Voltage Waveforms

VI(EN)
VI(EN)
(5 V/div)
(5 V/div)

VI(IN) = 5 V VI(IN) = 5 V
TA = 25°C VO(OUT) TA = 25°C
VO(OUT)
CL = 0.1 µF (2 V/div) CL = 0.1 µF
(2 V/div)

0 1 2 3 4 5 6 7 8 9 10 0 1000 2000 3000 4000 5000

t – Time – ms t – Time – ms

Figure 2. Turnon Delay and Rise Time Figure 3. Turnoff Delay and Fall Time
with 0.1-µF Load with 0.1-µF Load

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

PARAMETER MEASUREMENT INFORMATION

VI(EN) VI(EN)
(5 V/div) (5 V/div)

VI(IN) = 5 V VI(IN) = 5 V
TA = 25°C TA = 25°C
VO(OUT) VO(OUT) CL = 1 µF
CL = 1 µF
(2 V/div) RL = 10 Ω
(2 V/div) RL = 10 Ω

0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10 12 14 16 18 20
t – Time – ms t – Time – ms

Figure 4. Turnon Delay and Rise Time Figure 5. Turnoff Delay and Fall Time
with 1-µF Load with 1-µF Load

VI(IN) = 5 V
VI(IN) = 5 V
TA = 25°C
TA = 25°C

VI(EN)
(5 V/div)

VO(OUT)
(2 V/div)

IO(OUT) IO(OUT)
(0.2 A/div) (0.5 A/div)

0 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 70 80 90 100
t – Time – ms t – Time – ms

Figure 6. TPS2044, Short-Circuit Current, Figure 7. TPS2044, Threshold Trip Current

Device Enabled into Short with Ramped Load on Enabled Device

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

PARAMETER MEASUREMENT INFORMATION

VI(IN) = 5 V
TA = 25°C
RL = 10 Ω

VI(EN) VO(OC)
(5 V/div) 470 µF (5 V/div)

220 µF

100 µF

VI(IN) = 5 V
Load Ramp,1A/100 ms
IO(OUT) TA = 25°C
IO(OUT)
(0.5 A/div)
(o.2 A/div)

0 2 4 6 8 10 12 14 16 18 20 0 20 40 60 80 100 120 140 160 180 200

t – Time – ms t – Time – ms

Figure 8. Inrush Current with 100-µF, 220-µF Figure 9. Ramped Load on Enabled Device
and 470-µF Load Capacitance

VI(IN) = 5 V VI(IN) = 5 V
TA = 25°C TA = 25°C

VO(OC) VO(OC)
(5 V/div) (5 V/div)

IO(OUT) IO(OUT)
(0.5 A/div) (1 A/div)

0 400 800 1200 1600 2000 0 20 40 60 80 100 120 140 160 180 200
t – Time – µs t – Time – µs
Figure 10. 4-Ω Load Connected to Enabled Device Figure 11. 1-Ω Load Connected
to Enabled Device

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 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

TYPICAL CHARACTERISTICS

TURNON DELAY TURNOFF DELAY

vs vs
INPUT VOLTAGE INPUT VOLTAGE
6 17
CL = 1 µF CL = 1 µF
RL = 10 Ω 16 RL = 10 Ω
5.5 TA = 25°C TA = 25°C
15
Turn-On Delay – ms

Turn-Off Delay – ms
5
14

4.5 13

12
4
11

3.5
10

3 3
2.5 3 3.5 4 4.5 5 5.5 6 2.5 3 3.5 4 4.5 5 5.5 6
VI – Input Voltage – V VI – Input Voltage – V

Figure 12 Figure 13

RISE TIME FALL TIME

vs vs
LOAD CURRENT LOAD CURRENT
3 3.5
VI(INx) = 5 V VI(INx) = 5 V
CL = 1 µF TA = 25°C
TA = 25°C CL = 1 µF
2.9 3.3
r t – Rise Time – ms

f t – Fall Time – ms

2.8 3.1

2.7 2.9

2.6 2.7

2.5 2.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
IL – Load Current – A IL – Load Current – A

Figure 14 Figure 15

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TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

TYPICAL CHARACTERISTICS

SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT DISABLED

vs vs
JUNCTION TEMPERATURE JUNCTION TEMPERATURE
200 2000

I I(IN) – Supply Current, Output Disabled – nA

I I(IN) – Supply Current, Output Enabled – µ A

1800
VI(INx) = 5.5 V
180 VI(INx) = 5 V 1600 VI(INx) = 5.5 V
VI(INx) = 5 V
1400

1200 VI(INx) = 4 V
160 VI(INx) = 4 V
1000
VI(INx) = 2.7 V 800 VI(INx) = 2.7 V
140
600
VI(INx) = 3.3 V
400
120
200

0
100 –200
–50 –25 0 25 50 75 100 125 150 –50 –25 0 25 50 75 100 125 150
TJ – Junction Temperature – °C TJ – Junction Temperature – °C
Figure 16 Figure 17

SUPPLY CURRENT, OUTPUT ENABLED SUPPLY CURRENT, OUTPUT DISABLED

vs vs
INPUT VOLTAGE INPUT VOLTAGE
200 2000
– Supply Current, Output Disabled – nA
I I(IN) – Supply Current, Output Enabled – µ A

TJ = 125°C TJ = 125°C
1600
180 TJ = 85°C

1200
160

800
TJ = 25°C
140
TJ = 0°C 400
TJ = 25°C
TJ = 85°C
TJ = –40°C
120
0
I I(IN)

TJ = –40°C TJ = 0°C

100 –400
2.5 3 3.5 4 4.5 5 5.5 6 2.5 3 3.5 4 4.5 5 5.5 6
VI – Input Voltage – V VI – Input Voltage – V

Figure 18 Figure 19

12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

TYPICAL CHARACTERISTICS

STATIC DRAIN-SOURCE ON-STATE RESISTANCE STATIC DRAIN-SOURCE ON-STATE RESISTANCE

vs vs
JUNCTION TEMPERATURE INPUT VOLTAGE

r DS(on) – Static Drain-Source On-State Resistance – mΩ

r DS(on) – Static Drain-Source On-State Resistance – m Ω

175 175
IO = 0.5 A VI(INx) = 2.7 V
IO = 0.5 A

150 150
VI(INx) = 3.3 V

TJ = 125°C
125 125

TJ = 85°C
100 100
VI(INx) = 4.5 V
TJ = 25°C

75 75 TJ = 0°C

VI(INx) = 5 V
TJ = –40°C
50 50
–50 –25 0 25 50 75 100 125 150 2.5 3 3.5 4 4.5 5 5.5 6
TJ – Junction Temperature – °C VI – Input Voltage – V
Figure 20 Figure 21

INPUT-TO-OUTPUT VOLTAGE SHORT-CURCUIT OUTPUT CURRENT

vs vs
LOAD CURRENT INPUT VOLTAGE
100 0.95
VI(INx) – VI(OUTx) – Input-to-Output Voltage – mV

TA = 25°C
I OS – Short-circuit Output Current – A

75 TJ = –40°C

0.9 TJ = 25°C
VI(INx) = 2.7 V
VI(INx) = 3.3 V
50
TJ = 125°C

0.85
VI(INx) = 5 V
25
VI(INx) = 4.5 V

0 0.8
0.1 0.2 0.4 0.5 0.6 2.5 3 3.5 4 4.5 5 5.5 6
IL – Load Current – A VI – Input Voltage – V
Figure 22 Figure 23

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TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

TYPICAL CHARACTERISTICS

THRESHOLD TRIP CURRENT SHORT-CIRCUIT OUTPUT CURRENT

vs vs
INPUT VOLTAGE JUNCTION TEMPERATURE
1.2 0.95
TA = 25°C
Load Ramp = 1 A/10 ms

I OS – Short-circuit Output Current – A

1.175
Threshold Trip Current – A

VI(INx) = 5 V
0.9

VI(INx) = 4 V
1.15

VI(INx) = 2.7 V
0.85
1.125

1.1 0.8
2.5 3 3.5 4 4.5 5 5.5 6 –50 –25 0 25 50 75 100 125
VI – Input Voltage – V TJ – Junction Temperature – °C

Figure 24 Figure 25

UNDERVOLTAGE LOCKOUT CURRENT LIMIT RESPONSE

vs vs
JUNCTION TEMPERATURE PEAK CURRENT
2.5 500
VI(INx) = 5 V
450
TA = 25°C
UVLO – Undervoltage Lockout – V

2.4 400
Current Limit Response – µ s

Start Threshold 350

2.3 300

Stop Threshold 250

2.2 200

150

2.1 100

50

2 0
–50 –25 0 25 50 75 100 125 150 0 2.5 5 7.5 10 12.5
TJ – Junction Temperature – °C Peak Current – A

Figure 26 Figure 27

14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

TYPICAL CHARACTERISTICS
OVERCURRENT RESPONSE TIME (OCx)
vs
PEAK CURRENT
8
VI(INx) = 5 V
TA = 25°C

6
Response Time – µ s

0
0 2.5 5 7.5 10 12.5
Peak Current – A

Figure 28

APPLICATION INFORMATION

Power Supply 2
IN1
2.7 V to 5.5 V 15
6 OUT1 Load
IN2 0.1 µF 22 µF

14
OUT2 Load
16 0.1 µF 22 µF
OC1
13
OC2
12
OC3 11
9 OUT3 Load
OC4
0.1 µF 22 µF
3
EN1
4
EN2 10
7 OUT4 Load
EN3 0.1 µF 22 µF
8
EN4 1
GND1
5
GND2

Figure 29. Typical Application

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 15

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

APPLICATION INFORMATION

power-supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between INx and GND, close to the device, is recommended.
Placing a high-value electrolytic capacitor on the output pin(s) is recommended when the output load is heavy.
This precaution reduces power-supply transients that may cause ringing on the input. Additionally, bypassing
the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to short-circuit
transients.

overcurrent
A sense FET checks for overcurrent conditions. Unlike current-sense resistors, sense FETs do not increase the
series resistance of the current path. When an overcurrent condition is detected, the device maintains a
constant output current and reduces the output voltage accordingly. Complete shutdown occurs only if the fault
is present long enough to activate thermal limiting.
Three possible overload conditions can occur. In the first condition, the output has been shorted before the
device is enabled or before VI(INx) has been applied (see Figure 6). The TPS2044 and TPS2054 sense the short
and immediately switch into a constant-current output.
In the second condition, the short occurs while the device is enabled. At the instant the short occurs, very high
currents may flow for a short time before the current-limit circuit can react. After the current-limit circuit has
tripped (reached the overcurrent trip threshhold) the device switches into constant-current mode.
In the third condition, the load has been gradually increased beyond the recommended operating current. The
current is permitted to rise until the current-limit threshold is reached or until the thermal limit of the device is
exceeded (see Figure 7). The TPS2044 and TPS2054 are capable of delivering current up to the current-limit
threshold without damaging the device. Once the threshold has been reached, the device switches into its
constant-current mode.

16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

APPLICATION INFORMATION

OC response
The OC open-drain output is asserted (active low) when an overcurrent or overtemperature condition is
encountered. The output will remain asserted until the overcurrent or overtemperature condition is removed.
Connecting a heavy capacitive load to an enabled device can cause momentary false overcurrent reporting from
the inrush current flowing through the device, charging the downstream capacitor. An RC filter of 500 µs (see
Figure 30) can be connected to the OC pin to reduce false overcurrent reporting. Using low-ESR electrolytic
capacitors on the output lowers the inrush current flow through the device during hot-plug events by providing
a low impedance energy source, thereby reducing erroneous overcurrent reporting.
V+
V+

Rpullup
Rpullup
TPS2044 TPS2044
Rfilter
GND1 To USB
OC1 GND1 OC1
Controller
IN1 OUT1 IN1 OUT1
EN1 OUT2 Cfilter
EN1 OUT2
EN2 OC2 EN2 OC2
GND2 OC3 GND2 OC3

IN2 OUT3 IN2 OUT3

EN3 OUT4 EN3 OUT4

EN4 OC4 EN4 OC4

Figure 30. Typical Circuit for OC Pin and RC Filter for Damping Inrush OC Responses

power dissipation and junction temperature

The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to those of power packages; it
is good design practice to check power dissipation and junction temperature. The first step is to find rDS(on) at
the input voltage and operating temperature. As an initial estimate, use the highest operating ambient
temperature of interest and read rDS(on) from Figure 21. Next, calculate the power dissipation using:

PD + rDS(on) I2

Finally, calculate the junction temperature:

TJ + PD R qJA ) TA
Where:
TA = Ambient Temperature °C
RθJA = Thermal resistance SOIC = 172°C/W
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation, using the calculated value as the new estimate. Two or three iterations are generally
sufficient to get a reasonable answer.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 17

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

APPLICATION INFORMATION

thermal protection
Thermal protection prevents damage to the IC when heavy-overload or short-circuit faults are present for
extended periods of time. The faults force the TPS2044 and TPS2054 into constant current mode, which causes
the voltage across the high-side switch to increase; under short-circuit conditions, the voltage across the switch
is equal to the input voltage. The increased dissipation causes the junction temperature to rise to high levels.
The protection circuit senses the junction temperature of the switch and shuts it off. Hysteresis is built into the
thermal sense circuit, and after the device has cooled approximately 20 degrees, the switch turns back on. The
switch continues to cycle in this manner until the load fault or input power is removed.
The TPS2044 and TPS2054 implement a dual thermal trip to allow fully independent operation of the power
distribution switches. In an overcurrent or short-circuit condition the junction temperature will rise. Once the die
temperature rises to approximately 140°C, the internal thermal sense circuitry checks which power switch is
in an overcurrent condition and turns that power switch off, thus isolating the fault without interrupting operation
of the adjacent power switch. Should the die temperature exceed the first thermal trip point of 140°C and reach
160°C, both switches turn off. The OC open-drain output is asserted (active low) when overtemperature or
overcurrent occurs.

undervoltage lockout (UVLO)

An undervoltage lockout ensures that the power switch is in the off state at power up. Whenever the input voltage
falls below approximately 2 V, the power switch will be quickly turned off. This facilitates the design of
hot-insertion systems where it is not possible to turn off the power switch before input power is removed. The
UVLO will also keep the switch from being turned on until the power supply has reached at least 2 V, even if
the switch is enabled. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.

universal serial bus (USB) applications

The universal serial bus (USB) interface is a 12-Mb/s, or 1.5-Mb/s, multiplexed serial bus designed for
low-to-medium bandwidth PC peripherals (e.g., keyboards, printers, scanners, and mice). The four-wire USB
interface is conceived for dynamic attach-detach (hot plug-unplug) of peripherals. Two lines are provided for
differential data, and two lines are provided for 5-V power distribution.
USB data is a 3.3-V level signal, but power is distributed at 5 V to allow for voltage drops in cases where power
is distributed through more than one hub across long cables. Each function must provide its own regulated 3.3 V
from the 5-V input or its own internal power supply.
The USB specification defines the following five classes of devices, each differentiated by power-consumption
requirements:
D Hosts/self-powered hubs (SPH)
D Bus-powered hubs (BPH)
D Low-power, bus-powered functions
D High-power, bus-powered functions
D Self-powered functions
Self-powered and bus-powered hubs distribute data and power to downstream functions. The TPS2044 and
TPS2054 can provide power-distribution solutions for many of these classes of devices.

18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

APPLICATION INFORMATION

host/self-powered and bus-powered hubs

Hosts and self-powered hubs have a local power supply that powers the embedded functions and the
downstream ports (see Figure 31). This power supply must provide from 5.25 V to 4.75 V to the board side of
the downstream connection under full-load and no-load conditions. Hosts and SPHs must have current-limit
protection and must report overcurrent conditions to the USB controller. Typical SPHs are desktop PCs,
monitors, printers, and stand-alone hubs.
Downstream
USB Ports

D+
Power Supply
D–
3.3 V 5V VBUS
TPS2044 +
33 µF GND
2
IN1
15
6 OUT1
IN2 D+
0.1 µF D–
14
OUT2 VBUS
+
† 33 µF GND
11 11
OC1
OUT3
3
EN1 D+
† 13
OC2
D–
4
USB EN2 VBUS
Controller † +
12 OC3 10 33 µF GND
OUT4
7
EN3
† 9
OC4 D+
8
EN4 D–
GND1 GND2 VBUS
+
1 5 33 µF GND

† An RC filter may be needed, see Figure 36

Figure 31. Typical Four-Port USB Host/Self-Powered Hub

Bus-powered hubs obtain all power from upstream ports and often contain an embedded function. The hubs
are required to power up with less than one unit load. The BPH usually has one embedded function, and power
is always available to the controller of the hub. If the embedded function and hub require more than 100 mA
on power up, the power to the embedded function may need to be kept off until enumeration is completed. This
can be accomplished by removing power or by shutting off the clock to the embedded function. Power switching
the embedded function is not necessary if the aggregate power draw for the function and controller is less than
one unit load. The total current drawn by the bus-powered device is the sum of the current to the controller, the
embedded function, and the downstream ports, and it is limited to 500 mA from an upstream port.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 19

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

APPLICATION INFORMATION

low-power bus-powered functions and high-power bus-powered functions

Both low-power and high-power bus-powered functions obtain all power from upstream ports; low-power
functions always draw less than 100 mA, and high-power functions must draw less than 100 mA at powerup
and can draw up to 500 mA after enumeration. If the load of the function is more than the parallel combination
of 44 Ω and 10 µF at power up, the device must implement inrush current limiting (see Figure 32).
Power Supply
D+ 3.3 V
TPS2044
D–
2
VBUS IN1
15 Internal
OUT1 Function
GND 10 µF 6
IN2 0.1 µF 10 µF
0.1 µF

14 Internal
3 OUT2
Function
EN1 0.1 µF 10 µF
4
EN2
7
EN3
8 11 Internal
EN4 OUT3
Function
0.1 µF 10 µF
USB
Control
16 10 Internal
OC1 OUT4 Function
13 0.1 µF 10 µF
OC2
12
OC3 1
GND1
9
OC4 5
GND2

Figure 32. High-Power Bus-Powered Function

20 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

APPLICATION INFORMATION

USB power-distribution requirements

USB can be implemented in several ways, and, regardless of the type of USB device being developed, several
power-distribution features must be implemented.
D Hosts/self-powered hubs must:
– Current-limit downstream ports
– Report overcurrent conditions on USB VBUS
D Bus-powered hubs must:
– Enable/disable power to downstream ports
– Power up at <100 mA
– Limit inrush current (<44 Ω and 10 µF)
D Functions must:
– Limit inrush currents
– Power up at <100 mA
The feature set of the TPS2044 and TPS2054 allows them to meet each of these requirements. The integrated
current-limiting and overcurrent reporting is required by hosts and self-powered hubs. The logic-level enable
and controlled rise times meet the need of both input and output ports on bus-power hubs, as well as the input
ports for bus-power functions (see Figure 33).

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 21

TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

APPLICATION INFORMATION
TUSB2040
Hub Controller

SN75240 BUSPWR Tie to TPS2041 EN Input

Upstream A C Downstream
Port GANGED Ports
B D
DP0 DP1 D+
D+
DM1 D–
D– DM0 Ferrite Beads
A C
GND
GND B D
SN75240
DP2 5V
TPS2041
DM2
OC EN 5 V Power 33 µF†
Supply DP3
5V IN OUT DM3
D+
A C
D–
1 µF B D
TPS76333 Ferrite Beads
SN75240 GND
IN DP4
0.1 µF DM4
3.3 V VCC 5V
4.7 µF 4.7 µF TPS2044
GND
GND PWRON1 EN1 OUT1 33 µF†
OVRCUR1 OC1 OUT2
PWRON2 EN2
D+
OVRCUR2 OC2 IN1
D–
48-MHz XTAL1 0.1 µF Ferrite Beads
Crystal
GND

Tuning PWRON3 EN3 OUT3 5V

XTAL2
Circuit OVRCUR3 OC3 OUT4
PWRON4 EN4 33 µF†
OCSOFF
OVRCUR4 OC4 IN2
D+
GND 0.1 µF
D–
Ferrite Beads
GND1 GND
GND2

5V

33 µF†
† USB rev 1.1 requires 120 µF per hub.

Figure 33. Hybrid Self/Bus-Powered Hub Implementation

22 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TPS2044, TPS2054
QUAD POWER-DISTRIBUTION SWITCHES
SLVS174B – JULY 1998 – REVISED FEBRUARY 1999

APPLICATION INFORMATION

generic hot-plug applications (see Figure 34)

In many applications it may be necessary to remove modules or pc boards while the main unit is still operating.
These are considered hot-plug applications. Such implementations require the control of current surges seen
by the main power supply and the card being inserted. The most effective way to control these surges is to limit
and slowly ramp the current and voltage being applied to the card, similar to the way in which a power supply
normally turns on. Due to the controlled rise times and fall times of the TPS2044 and TPS2054, these devices
can be used to provide a softer start-up to devices being hot-plugged into a powered system. The UVLO feature
of the TPS2044 and TPS2054 also ensures the switch will be off after the card has been removed, and the switch
will be off during the next insertion. The UVLO feature guarantees a soft start with a controlled rise time for every
insertion of the card or module.

PC Board
TPS2044
GND1 OC1 Block of
IN1 OUT1 Circuitry

EN1 OUT2 Block of

EN2 OC2 Circuitry
Power
Supply GND2 OC3 Block of
2.7 V to 5.5 V IN2 OUT3 Circuitry

1000 µF 0.1 µF
EN3 OUT4 Block of
Optimum Circuitry
EN4 OC4

Overcurrent Response

Figure 34. Typical Hot-Plug Implementation

By placing the TPS2044 and TPS2054 between the VCC input and the rest of the circuitry, the input power will
reach these devices first after insertion. The typical rise time of the switch is approximately 2.5 ms, providing
a slow voltage ramp at the output of the device. This implementation controls system surge currents and
provides a hot-plugging mechanism for any device.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 23

 PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS2044D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2044 Samples

TPS2044DR ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2044 Samples

TPS2054D ACTIVE SOIC D 16 40 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 TPS2054 Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Jul-2022

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS2044DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2044DR SOIC D 16 2500 340.5 336.1 32.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
TPS2044D D SOIC 16 40 507 8 3940 4.32
TPS2054D D SOIC 16 40 507 8 3940 4.32

Pack Materials-Page 3
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