Scribd Logo
Upload

Welcome to Scribd!

  • 28 views

    Compal Confidential: Schematics Document

    Uploaded by

    Daniel Lira
    This document is a confidential schematics document from Compal Electronics containing trade secret information about a mobile Penryn uFCPGA design with an Intel Cantiga core logic from 2007. It includes a cover sheet noting the document is proprietary property of Compal Electronics and contains confidential and trade secret information that cannot be shared without consent. The document is 51 pages and details the schematics of the mobile device design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Compal Confidential: Schematics Document

    Uploaded by

    Daniel Lira
    28 views51 pages
    This document is a confidential schematics document from Compal Electronics containing trade secret information about a mobile Penryn uFCPGA design with an Intel Cantiga core logic from 2007. It includes a cover sheet noting the document is proprietary property of Compal Electronics and contains confidential and trade secret information that cannot be shared without consent. The document is 51 pages and details the schematics of the mobile device design.

    Original Title

    Untitled

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document is a confidential schematics document from Compal Electronics containing trade secret information about a mobile Penryn uFCPGA design with an Intel Cantiga core logic from 2007. It includes a cover sheet noting the document is proprietary property of Compal Electronics and contains confidential and trade secret information that cannot be shared without consent. The document is 51 pages and details the schematics of the mobile device design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    28 views51 pages

    Compal Confidential: Schematics Document

    Uploaded by

    Daniel Lira
    This document is a confidential schematics document from Compal Electronics containing trade secret information about a mobile Penryn uFCPGA design with an Intel Cantiga core logic from 2007. It includes a cover sheet noting the document is proprietary property of Compal Electronics and contains confidential and trade secret information that cannot be shared without consent. The document is 51 pages and details the schematics of the mobile device design.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    You are on page 1of 51

    A B C D E

    1 1

    Compal confidential
    Schematics Document
    2
    Mobile Penryn uFCPGA with Intel 2

    Cantiga_PM+ICH9-M core logic

    2007-09-16

    3 3

    4 4

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    Cover Sheet

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 1 of 51

    x
    he
    A B C D E
    A B C D E

    Compal confidential Montevina Consumer Discrete

    CK505 72QFN

    Thermal Sensor Clock Generator


    1
    Mobile Penryn SLG8SP553V 1
    VRAM DDR2 EMC1402
    P17
    128/512MB uFCPGA-478 CPU
    P6
    page 23,24
    P6,7, 8

    64bits Fan conn P6 H_A#(3..35)


    TV out Discrete FSB
    H_D#(0..63) 667/800/1066 MHz 1.05V
    Nvidia DDR2 SO-DIMM X2
    NB9M-GE DDR2 667MHz 1.8V
    Dock connecter

    BANK 0, 1, 2, 3 P15, 16
    P20,21,22
    Intel Cantiga MCH
    Dual Channel
    LVDS Panel FCBGA 1329
    Interface P19
    USB conn x3
    P9, 10, 11, 12, 13, 14 P36
    CRT CRT
    2 2
    P18
    P40 USB2.0 X12
    DMI X4 C-Link BT Conn
    Support V1.3 P36

    HDMI P42
    USB Camera
    P19
    PCI-E BUS*5 Azalia

    Intel ICH9-M SATA Master-1

    SATA Slave
    Mavell Mini-Card*2 New Card Flash Memory Card mBGA-676 Audio CKT AMP & Audio Jack
    SATA Slave
    WLAN & Robson Controller Codec_IDT9271B7 TPA6017A2
    88E8072(Gbe) P25,26,27,28 P33 P35
    P30 P31 P31
    JMB385
    MDC P34
    P32
    RJ45/11 CONN LPC BUS
    P30
    3 SATA HDD Connector 3
    P29

    LED
    P39 5 in1 Slot
    P32 ENE
    KB926 SATA ODD Connector
    P29
    RTC CKT. P38
    P26
    e-SATA Connector Dock
    Touch Pad CONN. Int.KBD With 3'th USB P29 P40

    FPR Conn P39 P38


    SPI
    CIR Conn
    SPI ROM P35

    Power On/Off CKT. 25LF080A P37


    4 Capsense switch Conn 4

    P39

    DC/DC Interface CKT. Touch Screen Conn


    P41 Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Block Diagram
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 2 of 51
    A B C D E
    A

    X MEANS Symbol Note :


    Voltage Rails O MEANS ON OFF

    : means Digital Ground


    +5VS
    +3VS
    power +1.5VS
    : means Analog Ground
    plane
    +0.9V
    +5VALW +1.8V +VCCP
    @ : means just reserve , no build
    +B
    DEBUG@ : means just reserve for
    +CPU_CORE
    debug.
    +3VALW +2.5VS
    +1.8VS
    State +NVVDD
    +PCIE
    USB assignment:
    USB-0 Right side
    USB-1 Right side
    USB-2 Left side(with ESATA)
    S0 O O O O USB-3 Dock
    USB-4 Camera
    S1 O O O O USB-5 WLAN
    USB-6 Bluetooth
    S3 O O O X USB-7 Finger Printer
    USB-8 MiniCard(WWAN/TV)
    S5 S4/AC O O X X USB-9 Express card
    USB-10 X
    S5 S4/ Battery only O X X X USB-11 X
    S5 S4/AC & Battery
    don't exist X X X X PCIe assignment:
    1 1

    PCIe-1 TV tuner/WWAN/Robeson
    PCIe-2 X
    PCIe-3 WLAN
    SMBUS Control Table
    PCIe-4 New Card
    NB9M
    SERIAL Thermal PCIe-5 Card reader
    SOURCE INVERTER BATT EEPROM Sensor SODIMM CLK CHIP MINI CARD Sensor board Thermal NB9M
    Sensor PCIe-6 GLAN (Marvell)
    SMB_EC_CK1
    SMB_EC_DA1
    KB926 X V V X X X X X X X
    SMB_EC_CK2
    SMB_EC_DA2
    KB926 X X X V X X X V V V
    SMB_CK_CLK1
    SMB_CK_DAT1
    ICH9 X X X X V V V X X X
    NB9M SMBUS Control Table

    SOURCE LVDS CRT HDMI

    DDC2_DATA
    DDC2_CLK NB9M
    V X X
    3VDDCDA
    3VDDCCL
    NB9M X V X
    HDMIDAT_VGA
    HDMICLK_VGA
    NB9M X X V

    I2C / SMBUS ADDRESSING

    om
    l.c
    DEVICE HEX ADDRESS

    ai
    tm
    DDR SO-DIMM 0 A0 10100000 Security Classification Compal Secret Data Compal Electronics, Inc.

    ho
    Issued Date 2007/09/26 2007/09/26 Title
    Deciphered Date
    DDR SO-DIMM 1 A4 10100100
    Notes List

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

    nf
    CLOCK GENERATOR (EXT.) D2 11010010 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    Custom Montevina Consumer Discrete 0.1

    ai
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    x
    Date: Friday, October 05, 2007 Sheet 3 of 51

    he
    A
    5 4 3 2 1

    50mA
    Finger printer

    50mA
    PC Camera
    177mA
    ICH9 25mA +3VS_DVDD
    1A ALC268
    D
    +V_BATTERY Dock con D

    300mA 35mA
    LAN MDC 1.5

    60mA 1A
    +3VAUX_BT New card
    1A
    0.3A 20mA Mini card (WLAN)
    INVPWR_B+ LVDS CON +3VALW_EC

    10mA 278mA
    AC VIN SPI ROM ICH9
    1.7A 5.89A 5.39A
    +3VALW +3VS 1.5A
    2A 550mA +LCDVDD LVDS CON
    B++ JMB385
    250mA
    +3VS_CK505
    C
    657mA ICH_VCC1_5 C

    ICH9 390mA
    0.3A 2.2A NB9M (VGA)
    +1.5VS 1.56A
    ICH9
    1A
    Mini card (TV tu/WWAN/Robeson)

    35mA +VDDA
    0.58A 1.3A
    +5VALW +5VS IDT 9271B7
    B+
    7A

    10mA
    +5VAMP
    360mA
    NB9M (VGA) 1.8A
    ODD
    B B

    3.7 X 3=11.1V 3.7A 700mA


    MCH SATA
    DC BATT
    1.9A 12.11A 8 A 1.8A
    B+++ +1.8V DDR2 800Mhz 4G x2 Muti Bay
    50mA
    +0.9V
    1.17A
    ICH9

    4.7A 1.26A
    1.05V_B+ +VCCP MCH
    2.3A
    CPU

    2A 10mA 34A/1.025V
    CPU_B+ +VCC_CORE CPU
    A A

    2.725A
    0.27A
    +NVVDDP +NVVDD NB9M (VGA)

    2A/1.1V Security Classification Compal Secret Data Compal Electronics, Inc.


    0.19A 2007/09/26 2007/09/26 Title
    +1.1V_PCIE +PCIE NB9M (VGA) Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Power delivery
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    C Montevina Consumer UMA 0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 4 of 51
    5 4 3 2 1
    A

    1 1

    om
    l.c
    ai
    tm
    Security Classification Compal Secret Data Compal Electronics, Inc.

    ho
    Issued Date 2007/09/26 2007/09/26 Title
    Deciphered Date
    Notes List

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

    nf
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Custom Montevina Consumer UMA 0.1

    ai
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    x
    Date: Friday, October 05, 2007 Sheet 5 of 51

    he
    A
    5 4 3 2 1

    +3VS

    @ R1
    ITP-XDP Connector XDP_DBRESET#_R 1 2 1K_0402_5%
    +VCCP
    Change value in 5/02

    JP1 XDP_TDI R2 1 2 54.9_0402_1%


    1 2
    XDP_BPM#5 GND0 GND1 XDP_TMS R3 54.9_0402_1%
    3 4 1 2
    D XDP_BPM#4 OBSFN_A0 OBSFN_C0 D
    5 6
    OBSFN_A1 OBSFN_C1 XDP_TDO R4 54.9_0402_1%
    7 8 1 2
    XDP_BPM#3 GND2 GND3
    9 10
    XDP_BPM#2 OBSDATA_A0 OBSDATA_C0 XDP_BPM#5 R5 54.9_0402_1%
    11 12 1 2
    OBSDATA_A1 OBSDATA_C1
    13 14
    XDP_BPM#1 GND4 GND5 XDP_HOOK1 R6
    15 16 1 2 @ 54.9_0402_1%
    XDP_BPM#0 OBSDATA_A2 OBSDATA_C2
    17 18
    OBSDATA_A3 OBSDATA_C3 XDP_TRST# R7 54.9_0402_1%
    9 H_A#[3..16] 19 20 1 2
    JCPU1A GND6 GND7
    21 22
    H_A#3 H_ADS# OBSFN_B0 OBSFN_D0 XDP_TCK R8 54.9_0402_1%
    J4 H1 H_ADS# 9 23 24 1 2
    A[3]# ADS# OBSFN_B1 OBSFN_D1

    ADDR GROUP_0
    H_A#4 L5 E2 H_BNR# 25 26
    A[4]# BNR# H_BNR# 9 GND8 GND9
    H_A#5 L4 G5 H_BPRI# 27 28
    A[5]# BPRI# H_BPRI# 9 OBSDATA_B0 OBSDATA_D0
    H_A#6 K5 29 30 This shall place near CPU
    H_A#7 A[6]# H_DEFER# OBSDATA_B1 OBSDATA_D1
    M3 H5 H_DEFER# 9 31 32
    H_A#8 A[7]# DEFER# H_DRDY# GND10 GND11
    N2 F21 H_DRDY# 9 33 34
    H_A#9 A[8]# DRDY# H_DBSY# R9 OBSDATA_B2 OBSDATA_D2
    J1 E1 H_DBSY# 9 35 36
    H_A#10 A[9]# DBSY# 1K_0402_5% OBSDATA_B3 OBSDATA_D3
    N3 37 38
    H_A#11 A[10]# H_BR0# GND12 GND13
    P5 F1 H_BR0# 9 7,26 H_PWRGOOD 2 1H_PWRGOOD_R 39 40 CLK_CPU_XDP CLK_CPU_XDP 17
    H_A#12 A[11]# BR0# XDP_HOOK1 PWRGOOD/HOOK0 ITPCLK/HOOK4 CLK_CPU_XDP#
    P2 41 42 CLK_CPU_XDP# 17
    H_A#13 A[12]# H_IERR# T1 HOOK1 ITPCLK#/HOOK5

    CONTROL
    L2 D20 +VCCP 43 44 +VCCP
    H_A#14 A[13]# IERR# H_INIT# VCC_OBS_AB VCC_OBS_CD H_RESET#_R R10
    P4 B3 H_INIT# 26 2 1 45 46 1 2 1K_0402_1% H_RESET#
    H_A#15 A[14]# INIT# C1 0.1U_0402_16V4Z HOOK2 RESET#/HOOK6 XDP_DBRESET#_R R11
    P1 Place TP with a 47 48 2 1 200_0402_1% XDP_DBRESET#
    H_A#16 A[15]# H_LOCK# HOOK3 DBR#/HOOK7
    R1 H4 9GND 49 50
    H_ADSTB#0 M1
    A[16]# LOCK# H_LOCK# 0.1" away 51
    GND14 GND15
    52 XDP_TDO
    9 H_ADSTB#0 ADSTB[0]# SDA TD0
    C1 H_RESET# Removed at 5/30.(Follow 53 54 XDP_TRST#
    RESET# H_RESET# 9 SCL TRST#
    H_REQ#0 K3 F3 H_RS#0 55 56 XDP_TDI R12
    9 H_REQ#0 REQ[0]# RS[0]# H_RS#0 9 Chimay) TCK1 TDI
    H_REQ#1 H2 F4 H_RS#1 XDP_TCK 57 58 XDP_TMS 0_0402_5%
    9 H_REQ#1 REQ[1]# RS[1]# H_RS#1 9 TCK0 TMS
    H_REQ#2 K2 G3 H_RS#2 59 60 XDP_PRE 1 2
    9 H_REQ#2 REQ[2]# RS[2]# H_RS#2 9 GND16 GND17
    H_REQ#3 J3 G2 H_TRDY#
    9 H_REQ#3 REQ[3]# TRDY# H_TRDY# 9
    H_REQ#4 L1 CONN@SAMTE_BSH-030-01-L-D-A
    9 H_REQ#4 REQ[4]# H_HIT#
    Place R191 within 200ps (~1") to CPU
    9 H_A#[17..35] G6 H_HIT# 9
    H_A#17 HIT# H_HITM#
    Y2 E4 H_HITM# 9
    C H_A#18 A[17]# HITM# C
    U5
    H_A#19 A[18]# XDP_BPM#0
    R3 AD4
    A[19]# BPM[0]#
    ADDR GROUP_1

    H_A#20 W6 AD3 XDP_BPM#1


    H_A#21 A[20]# BPM[1]# XDP_BPM#2
    U4 AD1
    H_A#22 A[21]# BPM[2]# XDP_BPM#3
    Y5 AC4
    H_A#23 A[22]# BPM[3]# XDP_BPM#4
    XDP/ITP SIGNALS

    U1 AC2
    H_A#24 A[23]# PRDY# XDP_BPM#5
    R4 AC1
    H_A#25 A[24]# PREQ# XDP_TCK +3VS
    T5 AC5
    H_A#26 A[25]# TCK XDP_TDI
    T3 AA6
    H_A#27 A[26]# TDI XDP_TDO
    W2 AB3
    H_A#28 A[27]# TDO XDP_TMS
    W5 AB5
    H_A#29 A[28]# TMS XDP_TRST#
    Y4 AB6 1

    0.1U_0402_16V4Z
    H_A#30 A[29]# TRST# XDP_DBRESET#
    U2 C20 XDP_DBRESET# 27
    H_A#31 A[30]# DBR# C2
    V4
    H_A#32 A[31]# U1
    W3
    H_A#33 A[32]# 2
    AA4
    A[33]# THERMAL
    H_A#34 AB2 H_PROCHOT# R13 1 2 49.9_0402_1%
    H_A#35 A[34]# +VCCP SMB_EC_CK2
    AA3 D21 1 8 SMB_EC_CK2 21,38
    H_ADSTB#1 A[35]# PROCHOT# H_THERMDA_R R14 VDD SMCLK
    9 H_ADSTB#1 V1 A24 1 2 100_0402_5% H_THERMDA
    ADSTB[1]# THERMDA H_THERMDC_R R15
    B25 1 2 100_0402_5% H_THERMDC H_THERMDA 2 7 SMB_EC_DA2
    SMB_EC_DA2 21,38
    H_A20M# THERMDC C3 DP SMDATA
    26 H_A20M# A6
    A20M#
    ICH

    H_FERR# A5 C7 H_THERMTRIP# 1 2 H_THERMDC 3 6


    26 H_FERR# FERR# THERMTRIP# H_THERMTRIP# 9,26 DN ALERT#
    H_IGNNE# C4 2200P_0402_50V7K
    26 H_IGNNE# IGNNE# THERM# 4 5
    H_STPCLK# THERM# GND
    26 H_STPCLK# D5
    H_INTR STPCLK# R16
    26 H_INTR C6
    LINT0 H CLK
    H_NMI B4 A22 CLK_CPU_BCLK +3VS 1 2
    26 H_NMI LINT1 BCLK[0] CLK_CPU_BCLK 17
    H_SMI# A3 A21 CLK_CPU_BCLK# 10K_0402_5% EMC1402-1-ACZL-TR_MSOP8
    26 H_SMI# SMI# BCLK[1] CLK_CPU_BCLK# 17
    M4
    RSVD[01] Address:100_1100
    N5
    RSVD[02] H_THERMDA, H_THERMDC routing together,
    T2
    B
    V3
    RSVD[03] Trace width / Spacing = 10 / 10 mil B
    RSVD[04]
    B2
    RSVD[05]
    RESERVED

    D2
    RSVD[06]
    D22
    RSVD[07]
    D3
    RSVD[08] For Merom, R1798 and R1799 are 0ohm
    F6
    RSVD[09] For Penryn, R1798 and R1799 are 100ohm.
    PWM Fan Control circuit
    +5VS
    Penryn
    JP2
    1
    1
    2
    2

    1
    +VCCP 3
    1 1 G1
    D1 C4 C5 4
    4.7U_0805_10V4Z 0.1U_0402_16V4Z G2
    RB751V_SOD323 ACES_85204-02001
    1

    @ 2 2

    2
    R17
    56_0402_5%
    +FAN
    2 2

    1
    2
    5
    6

    1
    B

    D Q2 @ D2
    E

    H_PROCHOT# 3 1 OCP# G
    OCP# 27
    C

    @ Q1 3 RLZ5.1B_LL34
    38 FAN_PWM
    MMBT3904_NL_SOT23-3 S SI3456BDV-T1-E3_TSOP6

    2
    4
    +VCCP
    A ZZZ1 A
    2

    R18
    56_0402_5%

    PCB
    1

    H_IERR# Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Penryn(1/3)-AGTL+/ITP-XDP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 6 of 51
    5 4 3 2 1
    5 4 3 2 1

    +VCC_CORE +VCC_CORE
    9 H_D#[0..15] H_D#[32..47] 9
    JCPU1B JCPU1C
    H_D#0 E22 Y22 H_D#32 A7 AB20
    H_D#1 D[0]# D[32]# H_D#33 VCC[001] VCC[068]
    F24 AB24 A9 AB7
    H_D#2 D[1]# D[33]# H_D#34 VCC[002] VCC[069]
    E26 V24 A10 AC7
    D[2]# D[34]# VCC[003] VCC[070]

    DATA GRP 0
    H_D#3 G22 V26 H_D#35 A12 AC9
    D[3]# D[35]# VCC[004] VCC[071]

    DATA GRP 2
    D H_D#4 F23 V23 H_D#36 A13 AC12 D
    H_D#5 D[4]# D[36]# H_D#37 VCC[005] VCC[072]
    G25 T22 A15 AC13
    H_D#6 D[5]# D[37]# H_D#38 VCC[006] VCC[073]
    E25 U25 A17 AC15
    H_D#7 D[6]# D[38]# H_D#39 VCC[007] VCC[074]
    E23 U23 A18 AC17
    H_D#8 D[7]# D[39]# H_D#40 VCC[008] VCC[075]
    K24 Y25 A20 AC18
    H_D#9 D[8]# D[40]# H_D#41 VCC[009] VCC[076]
    G24 W22 B7 AD7
    H_D#10 D[9]# D[41]# H_D#42 VCC[010] VCC[077]
    J24 Y23 B9 AD9
    H_D#11 D[10]# D[42]# H_D#43 VCC[011] VCC[078]
    J23 W24 B10 AD10
    H_D#12 D[11]# D[43]# H_D#44 VCC[012] VCC[079]
    H22 W25 B12 AD12
    H_D#13 D[12]# D[44]# H_D#45 VCC[013] VCC[080]
    F26 AA23 B14 AD14
    H_D#14 D[13]# D[45]# H_D#46 VCC[014] VCC[081]
    K22 AA24 B15 AD15
    H_D#15 D[14]# D[46]# H_D#47 VCC[015] VCC[082]
    H23 AB25 B17 AD17
    H_DSTBN#0 D[15]# D[47]# H_DSTBN#2 VCC[016] VCC[083]
    9 H_DSTBN#0 J26 Y26 H_DSTBN#2 9 B18 AD18
    H_DSTBP#0 DSTBN[0]# DSTBN[2]# H_DSTBP#2 VCC[017] VCC[084]
    9 H_DSTBP#0 H26 AA26 H_DSTBP#2 9 B20 AE9
    H_DINV#0 DSTBP[0]# DSTBP[2]# H_DINV#2 VCC[018] VCC[085]
    9 H_DINV#0 H25 U22 H_DINV#2 9 C9 AE10
    DINV[0]# DINV[2]# VCC[019] VCC[086]
    9 H_D#[16..31] H_D#[48..63] 9 C10 AE12
    VCC[020] VCC[087]
    C12 AE13
    H_D#16 H_D#48 VCC[021] VCC[088]
    N22 AE24 C13 AE15
    H_D#17 D[16]# D[48]# H_D#49 VCC[022] VCC[089]
    K25 AD24 C15 AE17
    H_D#18 D[17]# D[49]# H_D#50 VCC[023] VCC[090]
    P26 AA21 C17 AE18
    H_D#19 D[18]# D[50]# H_D#51 VCC[024] VCC[091]
    R23 AB22 C18 AE20
    H_D#20 D[19]# D[51]# H_D#52 VCC[025] VCC[092]
    L23 AB21 D9 AF9
    D[20]# D[52]# VCC[026] VCC[093]

    DATA GRP 1
    H_D#21 M24 AC26 H_D#53 D10 AF10
    D[21]# D[53]# VCC[027] VCC[094]

    DATA GRP 3
    H_D#22 L22 AD20 H_D#54 D12 AF12
    H_D#23 D[22]# D[54]# H_D#55 VCC[028] VCC[095]
    M23 AE22 D14 AF14
    H_D#24 D[23]# D[55]# H_D#56 VCC[029] VCC[096]
    P25 AF23 D15 AF15
    H_D#25 D[24]# D[56]# H_D#57 VCC[030] VCC[097]
    P23 AC25 D17 AF17
    H_D#26 D[25]# D[57]# H_D#58 VCC[031] VCC[098]
    P22 AE21 D18 AF18
    H_D#27 D[26]# D[58]# H_D#59 VCC[032] VCC[099] +VCCP
    T24 AD21 E7 AF20
    H_D#28 D[27]# D[59]# H_D#60 VCC[033] VCC[100] R19
    R24 AC22 E9
    H_D#29 D[28]# D[60]# H_D#61 VCC[034]
    L25 AD23 E10 G21 +VCCPA 1 2 0_0402_5%
    H_D#30 D[29]# D[61]# H_D#62 VCC[035] VCCP[01] +VCCPB 0_0402_5%
    T25 AF22 E12 V6 1 2
    C H_D#31 D[30]# D[62]# H_D#63 VCC[036] VCCP[02] R20 C
    N25 AC23 E13 J6
    H_DSTBN#1 D[31]# D[63]# H_DSTBN#3 VCC[037] VCCP[03]
    9 H_DSTBN#1 L26 AE25 H_DSTBN#3 9 E15 K6 1
    H_DSTBP#1 DSTBN[1]# DSTBN[3]# H_DSTBP#3 VCC[038] VCCP[04]
    9 H_DSTBP#1 M26 AF24 H_DSTBP#3 9 E17 M6
    H_DINV#1 DSTBP[1]# DSTBP[3]# H_DINV#3 VCC[039] VCCP[05] + C6
    9 H_DINV#1 N24 AC20 H_DINV#3 9 E18 J21
    DINV[1]# DINV[3]# VCC[040] VCCP[06] 330U_D2E_2.5VM_R7
    E20 K21
    +V_CPU_GTLREF COMP0 VCC[041] VCCP[07]
    AD26 R26 F7 M21
    @ R21 GTLREF COMP[0] VCC[042] VCCP[08] 2
    1 2 1K_0402_5% TEST1 C23 MISC U26 COMP1 F9 N21
    @ R22 TEST2 TEST1 COMP[1] COMP2 VCC[043] VCCP[09]
    1 2 1K_0402_5% D25 AA1 F10 N6
    TEST3 TEST2 COMP[2] COMP3 VCC[044] VCCP[10]
    T2 C24 Y1 F12 R21
    TEST4 TEST3 COMP[3] VCC[045] VCCP[11]
    T3 AF26 F14 R6
    TEST5 TEST4 H_DPRSTP# R23 R24 R25 R26 VCC[046] VCCP[12]
    T4 AF1 E5 H_DPRSTP# 9,26,49 F15 T21
    TEST6 TEST5 DPRSTP# H_DPSLP# VCC[047] VCCP[13]
    A26 B5 F17 T6

    54.9_0402_1%

    27.4_0402_1%

    54.9_0402_1%

    27.4_0402_1%
    T5 TEST6 DPSLP# H_DPSLP# 26 VCC[048] VCCP[14]

    1
    TEST7 C3 D24 H_DPWR# F18 V21
    T6 TEST7 DPWR# H_DPWR# 9 VCC[049] VCCP[15]
    CPU_BSEL0 B22 D6 H_PWRGOOD F20 W21
    17 CPU_BSEL0 BSEL[0] PWRGOOD H_PWRGOOD 6,26 VCC[050] VCCP[16]
    CPU_BSEL1 B23 D7 H_CPUSLP# AA7
    17 CPU_BSEL1 BSEL[1] SLP# H_CPUSLP# 9 VCC[051]
    CPU_BSEL2 C21 AE6 H_PSI# AA9 B26
    17 CPU_BSEL2 BSEL[2] PSI# H_PSI# 49 VCC[052] VCCA[01] +1.5VS
    AA10 C26

    2
    Penryn VCC[053] VCCA[02]
    AA12

    10U_0805_6.3V6M

    0.01U_0402_16V7K
    VCC[054]
    AA13 AD6 CPU_VID0 49
    VCC[055] VID[0]
    AA15 AF5 CPU_VID1 49 1 1
    VCC[056] VID[1]
    * Route the TEST3 and TEST5 signals through AA17
    VCC[057] VID[2]
    AE5 CPU_VID2 49
    C7 C8
    AA18 AF4 CPU_VID3 49
    a ground referenced Zo = 55-ohm trace that VCC[058] VID[3]
    AA20 AE3 CPU_VID4 49
    VCC[059] VID[4] 2 2
    ends in a via that is near a GND via and is Resistor placed within 0.5" AB9
    VCC[060] VID[5]
    AF3 CPU_VID5 49
    AC10 AE2 CPU_VID6 49
    of CPU pin.Trace should be VCC[061] VID[6]
    accessible through an oscilloscope AB10
    VCC[062]
    at least 25 mils away from AB12
    connection. AB14
    VCC[063]
    AF7 VCCSENSE
    VCC[064] VCCSENSE VCCSENSE 49
    any other toggling signal. AB15
    VCC[065] Near pin B26
    AB17
    COMP[0,2] trace width is 18 AB18
    VCC[066]
    AE7 VSSSENSE
    VCC[067] VSSSENSE VSSSENSE 49
    B
    mils. COMP[1,3] trace width B
    CPU_BSEL CPU_BSEL2 CPU_BSEL1 CPU_BSEL0 Penryn
    is 4 mils. .

    166 0 1 1

    Length match within 25 mils.


    200 0 1 0
    The trace width/space/other is 20/7/25.
    +VCCP
    266 0 0 0
    1

    R27
    1K_0402_1%
    +VCC_CORE
    2

    +V_CPU_GTLREF

    R28 1 2 100_0402_1% VCCSENSE


    1

    R29
    2K_0402_1% R30 1 2 100_0402_1% VSSSENSE
    2

    Close to CPU pin within


    Close to CPU pin AD26 500mils.
    A A
    within 500mils.

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    Penryn(2/3)-AGTL+/ITP-XDP

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 7 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    +VCC_CORE

    5
    1 1 1 1 1 1 1 1
    Place these capacitors on C9 C10 C11 C12 C13 C14 C15 C16
    L8 (North side,Secondary 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    Layer) 2 2 2 2 2 2 2 2

    D D
    +VCC_CORE
    JCPU1D
    A4
    VSS[001] VSS[082]
    P6 5
    A8 P21 1 1 1 1 1 1 1 1
    VSS[002] VSS[083] C17 C18 C19 C20 C21 C22 C23 C24
    A11
    VSS[003] VSS[084]
    P24 Place these capacitors on
    A14 R2 L8 (North side,Secondary
    VSS[004] VSS[085] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    A16 R5
    VSS[005] VSS[086] Layer) 2 2 2 2 2 2 2 2
    A19 R22
    VSS[006] VSS[087]
    A23 R25
    VSS[007] VSS[088]
    AF2 T1
    VSS[008] VSS[089]
    B6 T4
    VSS[009] VSS[090] +VCC_CORE
    B8 T23
    VSS[010] VSS[091]
    B11 T26
    VSS[011] VSS[092]
    B13
    VSS[012] VSS[093]
    U3 5
    B16 U6 1 1 1 1 1 1 1 1
    VSS[013] VSS[094] C25 C26 C27 C28 C29 C30 C31 C32
    B19
    VSS[014] VSS[095]
    U21 Place these capacitors on
    B21 U24 L8 (North side,Secondary
    VSS[015] VSS[096] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    B24 V2
    VSS[016] VSS[097] Layer) 2 2 2 2 2 2 2 2
    C5 V5
    VSS[017] VSS[098]
    C8 V22
    VSS[018] VSS[099]
    C11 V25
    VSS[019] VSS[100]
    C14 W1
    VSS[020] VSS[101] +VCC_CORE
    C16 W4
    VSS[021] VSS[102]
    C19 W23
    VSS[022] VSS[103]
    C2
    VSS[023] VSS[104]
    W26 5
    C22 Y3 1 1 1 1 1 1 1 1
    VSS[024] VSS[105] C33 C34 C35 C36 C37 C38 C39 C40
    C25
    VSS[025] VSS[106]
    Y6 Place these capacitors on
    D1 Y21 L8 (North side,Secondary
    VSS[026] VSS[107] 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M 10U_0805_6.3V6M
    D4 Y24
    VSS[027] VSS[108] Layer) 2 2 2 2 2 2 2 2
    D8 AA2
    VSS[028] VSS[109]
    D11 AA5
    C VSS[029] VSS[110] C
    D13 AA8
    VSS[030] VSS[111]
    D16 AA11
    VSS[031] VSS[112]
    D19 AA14
    D23
    VSS[032] VSS[113]
    AA16
    Mid Frequence Decoupling
    VSS[033] VSS[114]
    D26 AA19
    VSS[034] VSS[115]
    E3 AA22
    VSS[035] VSS[116]
    E6 AA25
    VSS[036] VSS[117]
    E8 AB1
    VSS[037] VSS[118]
    E11 AB4
    VSS[038] VSS[119]
    E14 AB8
    VSS[039] VSS[120]
    E16 AB11
    VSS[040] VSS[121]
    E19 AB13
    E21
    VSS[041]
    VSS[042]
    VSS[122]
    VSS[123]
    AB16 ESR <= 1.5m ohm
    E24 AB19
    VSS[043] VSS[124] Near CPU CORE regulator
    F5
    F8
    VSS[044] VSS[125]
    AB23
    AB26
    Capacitor > 1980uF
    VSS[045] VSS[126]
    F11 AC3
    VSS[046] VSS[127]
    F13 AC6
    VSS[047] VSS[128] +VCC_CORE
    F16 AC8
    VSS[048] VSS[129]
    F19 AC11
    VSS[049] VSS[130] 330U_D2E_2.5VM_R7
    F2 AC14
    VSS[050] VSS[131]
    F22 AC16
    VSS[051] VSS[132]
    F25 AC19
    VSS[052] VSS[133]
    G4 AC21
    VSS[053] VSS[134]
    G1 AC24 1 1 1 1
    VSS[054] VSS[135]
    G23 AD2
    VSS[055] VSS[136] C41 + C42 + @ C43 + C44 +
    G26 AD5
    VSS[056] VSS[137] 330U_D2E_2.5VM_R7
    H3 AD8
    VSS[057] VSS[138]
    H6 AD11
    VSS[058] VSS[139] 2 2 2 2
    H21 AD13
    VSS[059] VSS[140]
    H24 AD16
    VSS[060] VSS[141]
    J2 AD19
    B VSS[061] VSS[142] 330U_D2E_2.5VM_R7 330U_D2E_2.5VM_R7 B
    J5 AD22
    VSS[062] VSS[143]
    J22 AD25
    VSS[063] VSS[144]
    J25 AE1
    VSS[064] VSS[145]
    K1 AE4
    VSS[065] VSS[146]
    K4 AE8
    VSS[066] VSS[147]
    K23 AE11
    VSS[067] VSS[148]
    K26 AE14
    VSS[068] VSS[149]
    L3 AE16
    VSS[069] VSS[150]
    L6 AE19
    VSS[070] VSS[151]
    L21 AE23
    VSS[071] VSS[152]
    L24 AE26
    VSS[072] VSS[153]
    M2 A2
    VSS[073] VSS[154]
    M5 AF6
    M22
    VSS[074] VSS[155]
    AF8 +VCCP Inside CPU center cavity in 2 rows
    VSS[075] VSS[156]
    M25
    VSS[076] VSS[157]
    AF11 5
    N1 AF13
    VSS[077] VSS[158]
    N4 AF16 1 1 1 1 1 1
    VSS[078] VSS[159] C45 C46 C47 C48 C49 C50
    N23 AF19
    VSS[079] VSS[160]
    N26 AF21
    VSS[080] VSS[161] 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K 0.1U_0402_10V6K
    P3 A25
    VSS[081] VSS[162] 2 2 2 2 2 2
    AF25
    VSS[163]
    Penryn
    .

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Penryn(3/3)-AGTL+/ITP-XDP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 8 of 51
    5 4 3 2 1
    5 4 3 2 1

    H_A#[3..35] 6 U2B
    7 H_D#[0..63] U2A
    A14 H_A#3 M36
    T7

    DDR CLK/ CONTROL/COMPENSATION


    H_D#0 H_A#_3 H_A#4 RESERVED M_CLK_DDR0
    F2 C15 T8 N36 AP24 M_CLK_DDR0 15
    H_D#1 H_D#_0 H_A#_4 H_A#5 RESERVED SA_CK_0 M_CLK_DDR1
    G8 F16 R33 AT21 M_CLK_DDR1 15

    0.01U_0402_25V7K
    T9

    2.2U_0603_6.3V4Z
    H_D#2 H_D#_1 H_A#_5 H_A#6 RESERVED SA_CK_1 M_CLK_DDR2
    F8 H13 T10 T33 AV24 M_CLK_DDR2 16
    H_D#3 H_D#_2 H_A#_6 H_A#7 +1.8V RESERVED SB_CK_0 M_CLK_DDR3
    E6 C18 T11 AH9 AU20 M_CLK_DDR3 16
    H_D#4 H_D#_3 H_A#_7 H_A#8 RESERVED SB_CK_1
    G2 M16 T12 AH10
    H_D#5 H_D#_4 H_A#_8 H_A#9 RESERVED M_CLK_DDR#0
    H6 J13 1 1 T13 AH12 AR24 M_CLK_DDR#0 15
    H_D#_5 H_A#_9 RESERVED SA_CK#_0

    1
    H_D#6 H_A#10 M_CLK_DDR#1

    C51

    C52
    H2 P16 T14 AH13 AR21 M_CLK_DDR#1 15
    H_D#7 H_D#_6 H_A#_10 H_A#11 R31 RESERVED SA_CK#_1 M_CLK_DDR#2
    F6 R16 T15 K12 AU24 M_CLK_DDR#2 16
    H_D#8 H_D#_7 H_A#_11 H_A#12 1K_0402_1% RESERVED SB_CK#_0 M_CLK_DDR#3
    D4 N17 T16 AL34 AV20 M_CLK_DDR#3 16
    H_D#9 H_D#_8 H_A#_12 H_A#13 2 2 RESERVED SB_CK#_1
    H3 M13 T17 AK34
    H_D#10 H_D#_9 H_A#_13 H_A#14 RESERVED DDR_CKE0_DIMMA
    M9 E17 T18 AN35 BC28 DDR_CKE0_DIMMA 15

    2
    H_D#11 H_D#_10 H_A#_14 H_A#15 SMRCOMP_VOH RESERVED SA_CKE_0 DDR_CKE1_DIMMA
    M11 P17 T19 AM35 AY28 DDR_CKE1_DIMMA 15
    D H_D#12 H_D#_11 H_A#_15 H_A#16 RESERVED SA_CKE_1 DDR_CKE2_DIMMB D
    J1
    H_D#_12 H_A#_16
    F17 80% of 1.8V VCC_SM T20 T24
    RESERVED SB_CKE_0
    AY36 DDR_CKE2_DIMMB 16

    1
    H_D#13 J2 G20 H_A#17 BB36 DDR_CKE3_DIMMB
    H_D#_13 H_A#_17 SB_CKE_1 DDR_CKE3_DIMMB 16

    RSVD
    H_D#14 N12 B19 H_A#18 R32 B31
    H_D#_14 H_A#_18 T21 RESERVED
    H_D#15 J6 J16 H_A#19 3.01K_0402_1% B2 BA17 DDR_CS0_DIMMA#
    H_D#_15 H_A#_19 T22 RESERVED SA_CS#_0 DDR_CS0_DIMMA# 15
    H_D#16 P2 E20 H_A#20 20% of 1.8V VCC_SM M1 AY16 DDR_CS1_DIMMA#
    H_D#_16 H_A#_20 T23 RESERVED SA_CS#_1 DDR_CS1_DIMMA# 15
    H_D#17 L2 H16 H_A#21 AV16 DDR_CS2_DIMMB#
    DDR_CS2_DIMMB# 16

    2
    H_D#18 H_D#_17 H_A#_21 H_A#22 SMRCOMP_VOL SB_CS#_0 DDR_CS3_DIMMB#
    R2 J20 AR13 DDR_CS3_DIMMB# 16
    H_D#19 H_D#_18 H_A#_22 H_A#23 SB_CS#_1
    N9 L17 T24 AY21
    H_D#_19 H_A#_23 RESERVED

    1
    H_D#20 L6 A17 H_A#24 BD17 M_ODT0 M_ODT0 15

    0.01U_0402_25V7K
    2.2U_0603_6.3V4Z
    H_D#21 H_D#_20 H_A#_24 H_A#25 R33 SA_ODT_0 M_ODT1
    M5 B17 1 1 AY17 M_ODT1 15
    H_D#22 H_D#_21 H_A#_25 H_A#26 1K_0402_1% SA_ODT_1 M_ODT2 +1.8V

    C53

    C54
    J3 L16 BF15 M_ODT2 16
    H_D#23 H_D#_22 H_A#_26 H_A#27 SB_ODT_0 M_ODT3
    N2 C21 T25 BG23 AY13 M_ODT3 16
    H_D#24 H_D#_23 H_A#_27 H_A#28 RESERVED SB_ODT_1
    R1 J17 T26 BF23

    2
    H_D#25 H_D#_24 H_A#_28 H_A#29 2 2 RESERVED SMRCOMP R34
    N5 H20 T27 BH18 BG22 1 2 80.6_0402_1%
    H_D#26 H_D#_25 H_A#_29 H_A#30 RESERVED SM_RCOMP SMRCOMP# R35
    N6 B18 T28 BF18 BH21 1 2 80.6_0402_1%
    H_D#27 H_D#_26 H_A#_30 H_A#31 RESERVED SM_RCOMP#
    P13
    H_D#_27 H_A#_31
    K17 Follow Design Guide
    H_D#28 N8 B20 H_A#32 BF28 SMRCOMP_VOH
    H_D#29 L7
    H_D#_28 H_A#_32
    F21 H_A#33 SM_RCOMP_VOH
    BH28 SMRCOMP_VOL For Cantiga: 80.6ohm
    H_D#30 H_D#_29 H_A#_33 H_A#34 SM_RCOMP_VOL
    N10 K21
    H_D#31 H_D#_30 H_A#_34 H_A#35 V_DDR_MCH_REF
    M3 L20 AV42
    H_D#32 H_D#_31 H_A#_35 SM_VREF SM_PWROK R36
    Y3 AR36 1 2 0_0402_5%
    H_D#33 H_D#_32 H_ADS# SM_PWROK SM_REXT R37
    AD14 H12 H_ADS# 6 BF17 1 2 499_0402_1%
    H_D#34 H_D#_33 H_ADS# H_ADSTB#0 SM_REXT TP_SM_DRAMRST#
    Y6 B16 H_ADSTB#0 6 BC36 T29 PAD
    H_D#35 H_D#_34 H_ADSTB#_0 H_ADSTB#1 +3VS SM_DRAMRST#
    Y10 G17 H_ADSTB#1 6
    H_D#36 H_D#_35 H_ADSTB#_1 H_BNR#
    Y12 A9 H_BNR# 6 B38
    H_D#37 H_D#_36 H_BNR# H_BPRI# PM_EXTTS#0 R38 DPLL_REF_CLK
    Y14 F11 H_BPRI# 6 1 2 10K_0402_5% A38
    H_D#38 H_D#_37 H_BPRI# H_BR0# DPLL_REF_CLK#
    Y7 G12 H_BR0# 6 E41
    H_D#39 H_D#_38 H_BREQ# H_DEFER# DPLL_REF_SSCLK
    W2 E9 F41
    HOST

    H_D#_39 H_DEFER# H_DEFER# 6 DPLL_REF_SSCLK#


    H_D#40 AA8 B10 H_DBSY# PM_EXTTS#1 R39 1 2 10K_0402_5%
    H_D#_40 H_DBSY# H_DBSY# 6

    CLK
    H_D#41 Y9 AH7 CLK_MCH_BCLK F43 CLK_MCH_3GPLL
    H_D#_41 HPLL_CLK CLK_MCH_BCLK 17 PEG_CLK CLK_MCH_3GPLL 17
    H_D#42 AA13 AH6 CLK_MCH_BCLK# E43 CLK_MCH_3GPLL#
    H_D#_42 HPLL_CLK# CLK_MCH_BCLK# 17 PEG_CLK# CLK_MCH_3GPLL# 17
    H_D#43 AA9 J11 H_DPWR# CLKREQ#_7 R40 1 2 10K_0402_5%
    C H_D#_43 H_DPWR# H_DPWR# 7 C
    H_D#44 AA11 F9 H_DRDY#
    H_D#_44 H_DRDY# H_DRDY# 6
    H_D#45 AD11 H9 H_HIT#
    H_D#_45 H_HIT# H_HIT# 6
    H_D#46 AD10 E12 H_HITM# AE41 DMI_TXN0
    H_D#_46 H_HITM# H_HITM# 6 DMI_RXN_0 DMI_TXN0 27
    H_D#47 AD13 H11 H_LOCK# AE37 DMI_TXN1
    H_D#_47 H_LOCK# H_LOCK# 6 DMI_RXN_1 DMI_TXN1 27
    H_D#48 AE12 C9 H_TRDY# AE47 DMI_TXN2
    H_D#_48 H_TRDY# H_TRDY# 6 DMI_RXN_2 DMI_TXN2 27
    H_D#49 AE9 AH39 DMI_TXN3
    H_D#_49 DMI_RXN_3 DMI_TXN3 27
    H_D#50 AA2
    H_D#51 H_D#_50 DMI_TXP0
    AD8 AE40 DMI_TXP0 27
    H_D#52 H_D#_51 MCH_CLKSEL0 DMI_RXP_0 DMI_TXP1
    AA3 17 MCH_CLKSEL0 T25 AE38 DMI_TXP1 27
    H_D#53 H_D#_52 H_DINV#0 MCH_CLKSEL1 CFG_0 DMI_RXP_1 DMI_TXP2
    AD3 J8 H_DINV#0 7 17 MCH_CLKSEL1 R25 AE48 DMI_TXP2 27
    H_D#54 H_D#_53 H_DINV#_0 H_DINV#1 MCH_CLKSEL2 CFG_1 DMI_RXP_2 DMI_TXP3
    AD7 L3 H_DINV#1 7 17 MCH_CLKSEL2 P25 AH40 DMI_TXP3 27
    H_D#55 H_D#_54 H_DINV#_1 H_DINV#2 CFG_2 DMI_RXP_3
    AE14 Y13 H_DINV#2 7 P20
    H_D#56 H_D#_55 H_DINV#_2 H_DINV#3 CFG_3 DMI_RXN0
    AF3 Y1 H_DINV#3 7 P24 AE35 DMI_RXN0 27
    H_D#57 H_D#_56 H_DINV#_3 CFG5 CFG_4 DMI_TXN_0 DMI_RXN1
    AC1 11 CFG5 C25 AE43 DMI_RXN1 27
    H_D#58 H_D#_57 H_DSTBN#0 CFG6 CFG_5 DMI_TXN_1 DMI_RXN2
    AE3 L10 H_DSTBN#0 7 11 CFG6 N24 AE46 DMI_RXN2 27
    H_D#59 H_D#_58 H_DSTBN#_0 H_DSTBN#1 CFG7 CFG_6 DMI_TXN_2 DMI_RXN3
    AC3 M7 H_DSTBN#1 7 11 CFG7 M24 AH42 DMI_RXN3 27
    H_D#60 H_D#_59 H_DSTBN#_1 H_DSTBN#2 CFG8 CFG_7 DMI_TXN_3
    AE11 AA5 H_DSTBN#2 7 11 CFG8 E21
    H_D#_60 H_DSTBN#_2 CFG_8

    CFG
    H_D#61 AE8 AE6 H_DSTBN#3 CFG9 C23 AD35 DMI_RXP0
    H_D#_61 H_DSTBN#_3 H_DSTBN#3 7 11 CFG9 CFG_9 DMI_TXP_0 DMI_RXP0 27

    DMI
    H_D#62 AG2 CFG10 C24 AE44 DMI_RXP1
    H_D#_62 11 CFG10 CFG_10 DMI_TXP_1 DMI_RXP1 27
    H_D#63 AD6 L9 H_DSTBP#0 CFG11 N21 AF46 DMI_RXP2
    H_D#_63 H_DSTBP#_0 H_DSTBP#0 7 11 CFG11 CFG_11 DMI_TXP_2 DMI_RXP2 27
    M8 H_DSTBP#1 CFG12 P21 AH43 DMI_RXP3
    H_DSTBP#_1 H_DSTBP#1 7 11 CFG12 CFG_12 DMI_TXP_3 DMI_RXP3 27
    AA6 H_DSTBP#2 CFG13 T21
    H_DSTBP#_2 H_DSTBP#2 7 11 CFG13 CFG_13
    +H_SWNG C5 AE5 H_DSTBP#3 CFG14 R20
    H_SWING H_DSTBP#_3 H_DSTBP#3 7 11 CFG14 CFG_14
    H_RCOMP E3 CFG15 M20
    H_RCOMP 11 CFG15 CFG_15
    B15 H_REQ#0 CFG16 L21
    H_REQ#_0 H_REQ#0 6 11 CFG16 CFG_16
    K13 H_REQ#1 CFG17 H21

    GRAPHICS VID
    H_REQ#_1 H_REQ#1 6 11 CFG17 CFG_17
    F13 H_REQ#2 CFG18 P29
    H_REQ#_2 H_REQ#2 6 11 CFG18 CFG_18
    B13 H_REQ#3 CFG19 R28
    H_REQ#_3 H_REQ#3 6 11 CFG19 CFG_19
    6 H_RESET# H_RESET# C12 B14 H_REQ#4 CFG20 T28 B33
    H_CPURST# H_REQ#_4 H_REQ#4 6 11 CFG20 CFG_20 GFX_VID_0 T30
    7 H_CPUSLP# H_CPUSLP# E11 B32
    H_CPUSLP# GFX_VID_1 T31
    B6 H_RS#0 H_RS#0 6 G33
    H_RS#_0 GFX_VID_2 T32
    F12 H_RS#1 H_RS#1 6 F33
    B H_RS#_1 GFX_VID_3 T33 B
    C8 H_RS#2 H_RS#2 6 27 PM_BMBUSY# PM_BMBUSY# R29 E33
    H_RS#_2 PM_SYNC# GFX_VID_4 T34
    +H_VREF A11 H_DPRSTP# B7
    H_AVREF 7,26,49 H_DPRSTP# PM_DPRSTP#
    B11 PM_EXTTS#0 N33
    H_DVREF 15 PM_EXTTS#0 PM_EXT_TS#_0
    PM_EXTTS#1 P32
    16 PM_EXTTS#1 PM_EXT_TS#_1

    PM
    CANTIGA ES_FCBGA1329 PM_PWROK AT40 C34
    27,38 PM_PWROK PWROK GFX_VR_EN T35 +VCCP
    PLT_RST# R41 1 2 AT11
    Layout note: 20,25,30,31,32
    6,26
    PLT_RST#
    H_THERMTRIP# R42 1 2 100_0402_5% THERMTRIP# T20
    RSTIN#
    0_0402_5% DPRSLPVR THERMTRIP#
    Route H_SCOMP and H_SCOMP# with trace 27,49 DPRSLPVR R32
    DPRSLPVR

    1
    width, spacing and impedance (55 ohm) same as CL_CLK
    AH37 CL_CLK0
    CL_CLK0 27
    R43
    AH36 CL_DATA0 1K_0402_1%
    FSB data traces

    0.1U_0402_16V4Z
    CL_DATA CL_DATA0 27
    1 @ BG48
    NC CL_PWROK
    AN36 M_PWROK
    M_PWROK 27,38
    C55 BF48 AJ35 CL_RST#
    CL_RST# 27

    2
    NC CL_RST# +CL_VREF
    Layout Note: Layout Note: V_DDR_MCH_REF BD48 AH34

    ME
    NC CL_VREF
    BC48

    1
    H_RCOMP / H_VREF / H_SWNG trace width and spacing is 20/20. 2 NC
    BH47
    NC
    0621 add CLK and DAT for DVI 1
    BG47 C56 R44
    trace width and spacing is 10/20 BE47
    NC
    N28 0.1U_0402_16V4Z 499_0402_1%
    +1.8V NC DDPC_CTRLCLK T36
    BH46 M28 T37
    NC DDPC_CTRLDATA 2
    BF46 G36

    2
    +VCCP NC SDVO_CTRLCLK

    NC
    BG45 E36
    NC SDVO_CTRLDATA
    1

    +VCCP BH44 K36 CLKREQ#_7


    NC CLKREQ# CLKREQ#_7 17

    MISC
    R45 BH43 H36 MCH_ICH_SYNC#
    NC ICH_SYNC# MCH_ICH_SYNC# 27
    1K_0402_1%
    1K_0402_1%

    221_0603_1%

    BH6
    NC
    1

    BH5
    NC *R37*Follow Intel
    R46 R47 BG4 B12 TSATN#
    TSATN# 38 feedback
    2

    V_DDR_MCH_REF NC TSATN#
    15,16 V_DDR_MCH_REF BH3
    NC
    BF3
    NC
    1

    BH2
    0.1U_0402_16V4Z
    2

    +H_VREF H_RCOMP +H_SWNG R48 NC


    1 BG2 B28
    C57 1K_0402_1% NC HDA_BCLK
    BE2 B30
    NC HDA_RST#
    BG1 B29
    24.9_0402_1%

    0.1U_0402_16V4Z

    NC HDA_SDI
    1

    A A
    100_0402_1%

    1 1 BF1 C29
    0.1U_0402_16V4Z

    R52 C58 R54 R55 C59 2 NC HDA_SDO


    2K_0402_1%

    BD1 A28
    NC HDA_SYNC

    HDA
    BC1

    om
    NC
    F1
    2 2 NC
    A47
    2

    NC

    l.c
    CANTIGA ES_FCBGA1329

    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    within 100 mils from NB Near B3 pin 2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    Cantiga(1/6)-AGTL/DMI/DDR

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 9 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    D D

    15 DDR_A_D[0..63] 16 DDR_B_D[0..63]
    U2D U2E
    DDR_A_D0 AJ38 BD21 DDR_A_BS0 DDR_B_D0 AK47 BC16 DDR_B_BS0
    SA_DQ_0 SA_BS_0 DDR_A_BS0 15 SB_DQ_0 SB_BS_0 DDR_B_BS0 16
    DDR_A_D1 AJ41 BG18 DDR_A_BS1 DDR_B_D1 AH46 BB17 DDR_B_BS1
    SA_DQ_1 SA_BS_1 DDR_A_BS1 15 SB_DQ_1 SB_BS_1 DDR_B_BS1 16
    DDR_A_D2 AN38 AT25 DDR_A_BS2 DDR_B_D2 AP47 BB33 DDR_B_BS2
    SA_DQ_2 SA_BS_2 DDR_A_BS2 15 SB_DQ_2 SB_BS_2 DDR_B_BS2 16
    DDR_A_D3 AM38 DDR_B_D3 AP46
    DDR_A_D4 SA_DQ_3 DDR_A_RAS# DDR_B_D4 SB_DQ_3
    AJ36 BB20 DDR_A_RAS# 15 AJ46
    DDR_A_D5 SA_DQ_4 SA_RAS# DDR_A_CAS# DDR_B_D5 SB_DQ_4 DDR_B_RAS#
    AJ40 BD20 DDR_A_CAS# 15 AJ48 AU17 DDR_B_RAS# 16
    DDR_A_D6 SA_DQ_5 SA_CAS# DDR_A_WE# DDR_B_D6 SB_DQ_5 SB_RAS# DDR_B_CAS#
    AM44 AY20 DDR_A_WE# 15 AM48 BG16 DDR_B_CAS# 16
    DDR_A_D7 SA_DQ_6 SA_WE# DDR_B_D7 SB_DQ_6 SB_CAS# DDR_B_WE#
    AM42 AP48 BF14 DDR_B_WE# 16
    DDR_A_D8 SA_DQ_7 DDR_B_D8 SB_DQ_7 SB_WE#
    AN43 AU47
    DDR_A_D9 SA_DQ_8 DDR_B_D9 SB_DQ_8
    AN44 DDR_A_DM[0..7] 15 AU46
    DDR_A_D10 SA_DQ_9 DDR_B_D10 SB_DQ_9
    AU40 BA48
    DDR_A_D11 SA_DQ_10 DDR_A_DM0 DDR_B_D11 SB_DQ_10
    AT38 AM37 AY48 DDR_B_DM[0..7] 16
    DDR_A_D12 SA_DQ_11 SA_DM_0 DDR_A_DM1 DDR_B_D12 SB_DQ_11 DDR_B_DM0
    AN41 AT41 AT47 AM47
    DDR_A_D13 SA_DQ_12 SA_DM_1 DDR_A_DM2 DDR_B_D13 SB_DQ_12 SB_DM_0 DDR_B_DM1
    AN39 AY41 AR47 AY47
    DDR_A_D14 SA_DQ_13 SA_DM_2 DDR_A_DM3 DDR_B_D14 SB_DQ_13 SB_DM_1 DDR_B_DM2
    AU44 AU39 BA47 BD40
    DDR_A_D15 SA_DQ_14 SA_DM_3 DDR_A_DM4 DDR_B_D15 SB_DQ_14 SB_DM_2 DDR_B_DM3
    AU42 BB12 BC47 BF35
    DDR_A_D16 SA_DQ_15 SA_DM_4 DDR_A_DM5 DDR_B_D16 SB_DQ_15 SB_DM_3 DDR_B_DM4
    AV39 AY6 BC46 BG11
    DDR_A_D17 SA_DQ_16 SA_DM_5 DDR_A_DM6 DDR_B_D17 SB_DQ_16 SB_DM_4 DDR_B_DM5
    AY44 AT7 BC44 BA3
    DDR_A_D18 SA_DQ_17 SA_DM_6 DDR_A_DM7 DDR_B_D18 SB_DQ_17 SB_DM_5 DDR_B_DM6
    BA40 AJ5 BG43 AP1
    SA_DQ_18 SA_DM_7 SB_DQ_18 SB_DM_6

    A
    DDR_A_D19 BD43 DDR_A_DQS[0..7] 15 DDR_B_D19 BF43 AK2 DDR_B_DM7
    SA_DQ_19 SB_DQ_19 SB_DM_7

    B
    DDR_A_D20 AV41 AJ44 DDR_A_DQS0 DDR_B_D20 BE45
    SA_DQ_20 SA_DQS_0 SB_DQ_20 DDR_B_DQS[0..7] 16
    DDR_A_D21 AY43 AT44 DDR_A_DQS1 DDR_B_D21 BC41 AL47 DDR_B_DQS0
    DDR_A_D22 SA_DQ_21 SA_DQS_1 DDR_A_DQS2 DDR_B_D22 SB_DQ_21 SB_DQS_0 DDR_B_DQS1
    BB41 BA43 BF40 AV48
    DDR_A_D23 SA_DQ_22 SA_DQS_2 DDR_A_DQS3 DDR_B_D23 SB_DQ_22 SB_DQS_1 DDR_B_DQS2
    BC40 MEMORY BC37 BF41 BG41
    DDR_A_D24 SA_DQ_23 SA_DQS_3 DDR_A_DQS4 DDR_B_D24 SB_DQ_23 SB_DQS_2 DDR_B_DQS3
    AY37 AW12 BG38 BG37

    MEMORY
    DDR_A_D25 SA_DQ_24 SA_DQS_4 DDR_A_DQS5 DDR_B_D25 SB_DQ_24 SB_DQS_3 DDR_B_DQS4
    BD38 BC8 BF38 BH9
    DDR_A_D26 SA_DQ_25 SA_DQS_5 DDR_A_DQS6 DDR_B_D26 SB_DQ_25 SB_DQS_4 DDR_B_DQS5
    AV37 AU8 BH35 BB2
    DDR_A_D27 SA_DQ_26 SA_DQS_6 DDR_A_DQS7 DDR_B_D27 SB_DQ_26 SB_DQS_5 DDR_B_DQS6
    AT36 AM7 DDR_A_DQS#[0..7] 15 BG35 AU1
    DDR_A_D28 SA_DQ_27 SA_DQS_7 DDR_A_DQS#0 DDR_B_D28 SB_DQ_27 SB_DQS_6 DDR_B_DQS7
    AY38 AJ43 BH40 AN6 DDR_B_DQS#[0..7] 16
    C DDR_A_D29 SA_DQ_28 SA_DQS#_0 DDR_A_DQS#1 DDR_B_D29 SB_DQ_28 SB_DQS_7 DDR_B_DQS#0 C
    BB38 AT43 BG39 AL46
    DDR_A_D30 SA_DQ_29 SA_DQS#_1 DDR_A_DQS#2 DDR_B_D30 SB_DQ_29 SB_DQS#_0 DDR_B_DQS#1
    AV36 BA44 BG34 AV47
    DDR_A_D31 SA_DQ_30 SA_DQS#_2 DDR_A_DQS#3 DDR_B_D31 SB_DQ_30 SB_DQS#_1 DDR_B_DQS#2
    AW36 BD37 BH34 BH41
    DDR_A_D32 SA_DQ_31 SA_DQS#_3 DDR_A_DQS#4 DDR_B_D32 SB_DQ_31 SB_DQS#_2 DDR_B_DQS#3
    BD13 AY12 BH14 BH37
    DDR_A_D33 SA_DQ_32 SA_DQS#_4 DDR_A_DQS#5 DDR_B_D33 SB_DQ_32 SB_DQS#_3 DDR_B_DQS#4
    AU11 BD8 BG12 BG9
    DDR_A_D34 SA_DQ_33 SA_DQS#_5 DDR_A_DQS#6 DDR_B_D34 SB_DQ_33 SB_DQS#_4 DDR_B_DQS#5
    BC11 AU9 BH11 BC2
    DDR_A_D35 SA_DQ_34 SA_DQS#_6 DDR_A_DQS#7 DDR_B_D35 SB_DQ_34 SB_DQS#_5 DDR_B_DQS#6
    BA12 AM8 DDR_A_MA[0..14] 15 BG8 AT2
    DDR_A_D36 SA_DQ_35 SA_DQS#_7 DDR_B_D36 SB_DQ_35 SB_DQS#_6 DDR_B_DQS#7
    AU13 BH12 AN5
    SYSTEM

    DDR_A_D37 SA_DQ_36 DDR_A_MA0 DDR_B_D37 SB_DQ_36 SB_DQS#_7


    AV13 BA21 BF11

    SYSTEM
    SA_DQ_37 SA_MA_0 SB_DQ_37 DDR_B_MA[0..14] 16
    DDR_A_D38 BD12 BC24 DDR_A_MA1 DDR_B_D38 BF8 AV17 DDR_B_MA0
    DDR_A_D39 SA_DQ_38 SA_MA_1 DDR_A_MA2 DDR_B_D39 SB_DQ_38 SB_MA_0 DDR_B_MA1
    BC12 BG24 BG7 BA25
    DDR_A_D40 SA_DQ_39 SA_MA_2 DDR_A_MA3 DDR_B_D40 SB_DQ_39 SB_MA_1 DDR_B_MA2
    BB9 BH24 BC5 BC25
    DDR_A_D41 SA_DQ_40 SA_MA_3 DDR_A_MA4 DDR_B_D41 SB_DQ_40 SB_MA_2 DDR_B_MA3
    BA9 BG25 BC6 AU25
    DDR_A_D42 SA_DQ_41 SA_MA_4 DDR_A_MA5 DDR_B_D42 SB_DQ_41 SB_MA_3 DDR_B_MA4
    AU10 BA24 AY3 AW25
    DDR_A_D43 SA_DQ_42 SA_MA_5 DDR_A_MA6 DDR_B_D43 SB_DQ_42 SB_MA_4 DDR_B_MA5
    AV9 BD24 AY1 BB28
    DDR_A_D44 SA_DQ_43 SA_MA_6 DDR_A_MA7 DDR_B_D44 SB_DQ_43 SB_MA_5 DDR_B_MA6
    BA11 BG27 BF6 AU28
    DDR_A_D45 SA_DQ_44 SA_MA_7 DDR_A_MA8 DDR_B_D45 SB_DQ_44 SB_MA_6 DDR_B_MA7
    BD9 BF25 BF5 AW28
    DDR_A_D46 SA_DQ_45 SA_MA_8 DDR_A_MA9 DDR_B_D46 SB_DQ_45 SB_MA_7 DDR_B_MA8
    AY8 AW24 BA1 AT33
    DDR_A_D47 SA_DQ_46 SA_MA_9 DDR_A_MA10 DDR_B_D47 SB_DQ_46 SB_MA_8 DDR_B_MA9
    BA6 BC21 BD3 BD33
    DDR_A_D48 SA_DQ_47 SA_MA_10 DDR_A_MA11 DDR_B_D48 SB_DQ_47 SB_MA_9 DDR_B_MA10
    AV5 BG26 AV2 BB16
    SA_DQ_48 SA_MA_11 SB_DQ_48 SB_MA_10
    DDR

    DDR_A_D49 AV7 BH26 DDR_A_MA12 DDR_B_D49 AU3 AW33 DDR_B_MA11


    SA_DQ_49 SA_MA_12 SB_DQ_49 SB_MA_11

    DDR
    DDR_A_D50 AT9 BH17 DDR_A_MA13 DDR_B_D50 AR3 AY33 DDR_B_MA12
    DDR_A_D51 SA_DQ_50 SA_MA_13 DDR_A_MA14 DDR_B_D51 SB_DQ_50 SB_MA_12 DDR_B_MA13
    AN8 AY25 AN2 BH15
    DDR_A_D52 SA_DQ_51 SA_MA_14 DDR_B_D52 SB_DQ_51 SB_MA_13 DDR_B_MA14
    AU5 AY2 AU33
    DDR_A_D53 SA_DQ_52 DDR_B_D53 SB_DQ_52 SB_MA_14
    AU6 AV1
    DDR_A_D54 SA_DQ_53 DDR_B_D54 SB_DQ_53
    AT5 AP3
    DDR_A_D55 SA_DQ_54 DDR_B_D55 SB_DQ_54
    AN10 AR1
    DDR_A_D56 SA_DQ_55 DDR_B_D56 SB_DQ_55
    AM11 AL1
    DDR_A_D57 SA_DQ_56 DDR_B_D57 SB_DQ_56
    AM5 AL2
    DDR_A_D58 SA_DQ_57 DDR_B_D58 SB_DQ_57
    AJ9 AJ1
    DDR_A_D59 SA_DQ_58 DDR_B_D59 SB_DQ_58
    AJ8 AH1
    DDR_A_D60 SA_DQ_59 DDR_B_D60 SB_DQ_59
    AN12 AM2
    B DDR_A_D61 SA_DQ_60 DDR_B_D61 SB_DQ_60 B
    AM13 AM3
    DDR_A_D62 SA_DQ_61 DDR_B_D62 SB_DQ_61
    AJ11 AH3
    DDR_A_D63 SA_DQ_62 DDR_B_D63 SB_DQ_62
    AJ12 AJ3
    SA_DQ_63 SB_DQ_63
    CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cantiga(2/6)-DDR2 A/B CH
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 10 of 51
    5 4 3 2 1
    5 4 3 2 1

    U2C
    Strap Pin Table
    R57 +VCC_PEG PEGCOMP trace width
    L32 000 = FSB 1066MHz
    L_BKLT_CTRL and spacing is 20/25 mils.
    G32 T37 1 2 CFG[2:0] FSB Freq
    L_BKLT_EN PEG_COMPI 49.9_0402_1% 010 = FSB 800MHz
    M32 T36
    L_CTRL_CLK PEG_COMPO select
    M33 011 = FSB 667MHz
    L_CTRL_DATA PEG_RXN0
    K33 H44 PEG_RXN0 20 Others = Reserved
    L_DDC_CLK PEG_RX#_0 PEG_RXN1
    J33 J46 PEG_RXN1 20
    L_DDC_DATA PEG_RX#_1 PEG_RXN2
    L44 PEG_RXN2 20
    PEG_RX#_2 PEG_RXN3
    PEG_RX#_3
    L40 PEG_RXN3 20 CFG[4:3] Reserved
    M29 N41 PEG_RXN4
    L_VDD_EN PEG_RX#_4 PEG_RXN4 20
    C44 P48 PEG_RXN5 0 = DMI x 2
    D LVDS_IBG PEG_RX#_5 PEG_RXN5 20 D
    B43 N44 PEG_RXN6 CFG5 (DMI select) 1 = DMI x 4
    E37
    E38
    LVDS_VBG
    LVDS_VREFH
    PEG_RX#_6
    PEG_RX#_7
    T43
    U43
    PEG_RXN7
    PEG_RXN8
    PEG_RXN6
    PEG_RXN7
    20
    20 *
    0 = The iTPM Host Interface is enable
    LVDS_VREFL PEG_RX#_8 PEG_RXN8 20

    LVDS
    C41 Y43 PEG_RXN9 CFG6
    LVDSA_CLK# PEG_RX#_9 PEG_RXN9 20
    C40 Y48 PEG_RXN10 1 = The iTPM Host Interface is disable
    B37
    A37
    LVDSA_CLK
    LVDSB_CLK#
    PEG_RX#_10
    PEG_RX#_11
    Y36
    AA43
    PEG_RXN11
    PEG_RXN12
    PEG_RXN10
    PEG_RXN11
    20
    20
    0 =(TLS)chiper suite with no confidentiality
    *
    LVDSB_CLK PEG_RX#_12 PEG_RXN12 20
    AD37 PEG_RXN13 CFG7 (Intel Management
    PEG_RX#_13 PEG_RXN13 20
    H47 AC47 PEG_RXN14 1 =(TLS)chiper suite with confidentiality
    E46
    G40
    LVDSA_DATA#_0
    LVDSA_DATA#_1
    PEG_RX#_14
    PEG_RX#_15
    AD39 PEG_RXN15
    PEG_RXN14
    PEG_RXN15
    20
    20
    Engine Crypto strap) *
    LVDSA_DATA#_2 PEG_RXP0
    A40 H43 PEG_RXP0 20
    LVDSA_DATA#_3 PEG_RX_0 PEG_RXP1
    PEG_RX_1
    J44 PEG_RXP1 20 CFG8 Reserved

    GRAPHICS
    H48 L43 PEG_RXP2
    LVDSA_DATA_0 PEG_RX_2 PEG_RXP2 20
    D45 L41 PEG_RXP3
    LVDSA_DATA_1 PEG_RX_3 PEG_RXP3 20
    F40 N40 PEG_RXP4 CFG9 (PCIE Graphics 0 = Reverse Lane,15->0, 14->1
    LVDSA_DATA_2 PEG_RX_4 PEG_RXP4 20
    B40 P47 PEG_RXP5
    LVDSA_DATA_3 PEG_RX_5 PEG_RXP5 20
    N43 PEG_RXP6 Lane Reversal) 1 = Normal Operation,Lane Number in
    A41
    H38
    LVDSB_DATA#_0
    PEG_RX_6
    PEG_RX_7
    T42
    U42
    PEG_RXP7
    PEG_RXP8
    PEG_RXP6
    PEG_RXP7
    20
    20 order *
    LVDSB_DATA#_1 PEG_RX_8 PEG_RXP8 20
    G37 Y42 PEG_RXP9
    LVDSB_DATA#_2 PEG_RX_9 PEG_RXP9 20
    J37 W47 PEG_RXP10 CFG10 (PCIE 0 = Enable
    LVDSB_DATA#_3 PEG_RX_10 PEG_RXP10 20
    Y37 PEG_RXP11
    PEG_RX_11 PEG_RXP11 20
    B42 AA42 PEG_RXP12 Lookback 1 = Disable
    G38
    F37
    LVDSB_DATA_0
    LVDSB_DATA_1
    PEG_RX_12
    PEG_RX_13
    AD36
    AC48
    PEG_RXP13
    PEG_RXP14
    PEG_RXP12
    PEG_RXP13
    20
    20
    CFG11
    enable)
    Reserved
    *
    LVDSB_DATA_2 PEG_RX_14 PEG_RXP14 20
    K37 AD40 PEG_RXP15
    LVDSB_DATA_3 PEG_RX_15 PEG_RXP15 20
    00 = Reserved

    PCI-EXPRESS
    J41 PEG_TXN0 C1289 1 2 0.1U_0402_16V4Z PEG_M_TXN0 20 CFG[13:12] (XOR/ALLZ) 01 = XOR Mode Enabled
    PEG_TX#_0 PEG_TXN1 C1290 0.1U_0402_16V4Z
    M46 1 2 PEG_M_TXN1 20 10 = All Z Mode Enabled
    PEG_TX#_1 PEG_TXN2 C1291 0.1U_0402_16V4Z
    F25 M47 1 2 11 = Normal Operation (Default)
    C
    H25
    K25
    TVA_DAC
    TVB_DAC
    PEG_TX#_2
    PEG_TX#_3
    M40
    M42
    PEG_TXN3
    PEG_TXN4
    C1292
    C1293
    1
    1
    2
    2
    0.1U_0402_16V4Z
    0.1U_0402_16V4Z
    PEG_M_TXN2
    PEG_M_TXN3
    PEG_M_TXN4
    20
    20
    20
    * C
    TVC_DAC PEG_TX#_4

    TV
    R48 PEG_TXN5 C1294 1 2 0.1U_0402_16V4Z PEG_M_TXN5 20 CFG[15:14] Reserved
    PEG_TX#_5 PEG_TXN6 C1295 0.1U_0402_16V4Z
    H24 N38 1 2 PEG_M_TXN6 20
    TV_RTN PEG_TX#_6 PEG_TXN7 C1296 0.1U_0402_16V4Z
    T40 1 2 PEG_M_TXN7 20
    PEG_TX#_7 PEG_TXN8 C1297 0.1U_0402_16V4Z
    PEG_TX#_8
    U37 1 2 PEG_M_TXN8 20 CFG16 (FSB Dynamic ODT) 0 = Disabled
    U40 PEG_TXN9 C1298 1 2 0.1U_0402_16V4Z 1 = Enabled
    C31
    E32
    TV_DCONSEL_0
    PEG_TX#_9
    PEG_TX#_10
    Y40
    AA46
    PEG_TXN10
    PEG_TXN11
    C1299
    C1300
    1
    1
    2
    2
    0.1U_0402_16V4Z
    0.1U_0402_16V4Z
    PEG_M_TXN9
    PEG_M_TXN10
    PEG_M_TXN11
    20
    20
    20
    *
    TV_DCONSEL_1 PEG_TX#_11 PEG_TXN12 C1301 0.1U_0402_16V4Z
    PEG_TX#_12
    AA37 1 2 PEG_M_TXN12 20 CFG[18:17] Reserved
    AA40 PEG_TXN13 C1302 1 2 0.1U_0402_16V4Z PEG_M_TXN13 20
    PEG_TX#_13 PEG_TXN14 C1303 0.1U_0402_16V4Z
    AD43 1 2 PEG_M_TXN14 20
    PEG_TX#_14 PEG_TXN15 C1304 0.1U_0402_16V4Z
    AC46 1 2 CFG19 (DMI Lane Reversal) 0 = Normal Operation
    E28
    PEG_TX#_15
    J42 PEG_TXP0 C1305 1 2 0.1U_0402_16V4Z
    PEG_M_TXN15

    PEG_M_TXP0
    20

    20
    (Lane number in Order) *
    CRT_BLUE PEG_TX_0 PEG_TXP1 C1306 0.1U_0402_16V4Z
    PEG_TX_1
    L46 1 2 PEG_M_TXP1 20 1 = Reverse Lane
    G28 M48 PEG_TXP2 C1307 1 2 0.1U_0402_16V4Z PEG_M_TXP2 20
    CRT_GREEN PEG_TX_2 PEG_TXP3 C1308 0.1U_0402_16V4Z
    M39 1 2 PEG_M_TXP3 20
    PEG_TX_3 PEG_TXP4 C1309 0.1U_0402_16V4Z
    J28 M43 1 2 PEG_M_TXP4 20
    CRT_RED PEG_TX_4
    VGA PEG_TXP5 C1310 0.1U_0402_16V4Z
    R47 1 2 CFG20 (PCIE/SDVO 0 = Only PCIE or SDVO is operational.
    G29
    CRT_IRTN
    PEG_TX_5
    PEG_TX_6
    N37
    T39
    PEG_TXP6
    PEG_TXP7
    C1311
    C1312
    1
    1
    2
    2
    0.1U_0402_16V4Z
    0.1U_0402_16V4Z
    PEG_M_TXP5
    PEG_M_TXP6
    PEG_M_TXP7
    20
    20
    20 concurrent) 1 = PCIE/SDVO are operating simu.
    *
    PEG_TX_7 PEG_TXP8 C1313 0.1U_0402_16V4Z
    H32 U36 1 2 PEG_M_TXP8 20
    CRT_DDC_CLK PEG_TX_8 PEG_TXP9 C1314 0.1U_0402_16V4Z
    J32 U39 1 2 PEG_M_TXP9 20
    CRT_DDC_DATA PEG_TX_9 PEG_TXP10 C1315 0.1U_0402_16V4Z
    J29 Y39 1 2 PEG_M_TXP10 20
    CRT_HSYNC PEG_TX_10 PEG_TXP11 C1316 0.1U_0402_16V4Z
    E29 Y46 1 2 PEG_M_TXP11 20
    CRT_TVO_IREF PEG_TX_11 PEG_TXP12 C1317 0.1U_0402_16V4Z +3VS
    L29 AA36 1 2 PEG_M_TXP12 20
    CRT_VSYNC PEG_TX_12 PEG_TXP13 C1318 0.1U_0402_16V4Z
    AA39 1 2 PEG_M_TXP13 20
    PEG_TX_13 PEG_TXP14 C1319 0.1U_0402_16V4Z
    AD42 1 2 PEG_M_TXP14 20
    PEG_TX_14 PEG_TXP15 C1320 0.1U_0402_16V4Z
    AD46 1 2 PEG_M_TXP15 20
    PEG_TX_15

    1
    R71 +3VS
    4.02K_0402_1%
    CANTIGA ES_FCBGA1329
    B B
    R72 1 2
    9 CFG16

    2
    CFG5 4.02K_0402_1%
    9 CFG5

    1
    @ @ R73 1 2
    9 CFG19
    R74 4.02K_0402_1%
    2.21K_0402_1%
    @R75
    @R75 1 2
    9 CFG20
    4.02K_0402_1%

    2
    @R76
    @R76 1 2
    9 CFG11
    2.21K_0402_1%

    R77 1 2
    9 CFG12
    2.21K_0402_1%

    R78 1 2
    9 CFG13
    2.21K_0402_1%
    @R79
    @R79 1 2
    9 CFG6
    2.21K_0402_1% @R80
    @R80 1 2
    9 CFG14
    2.21K_0402_1%
    R81 1 2
    9 CFG7
    2.21K_0402_1% @R82
    @R82 1 2
    9 CFG15
    2.21K_0402_1%
    @R83
    @R83 1 2
    9 CFG8
    2.21K_0402_1%

    @R84
    @R84 1 2 @R85
    @R85 1 2
    9 CFG9 9 CFG17
    2.21K_0402_1% 2.21K_0402_1%

    A @R86
    @R86 1 2 @R87
    @R87 1 2 A
    9 CFG10 9 CFG18
    2.21K_0402_1% 2.21K_0402_1%

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    Cantiga(3/6)-VGA/LVDS/TV

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 11 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    +VCCP
    +V1.05VS_AXF +VCCP
    U2H R93
    1 2

    10U_0805_10V4Z

    1U_0603_10V4Z
    852mA U13 0_0603_5%
    VTT

    220U_D2_4VM

    4.7U_0805_10V4Z
    73mA T13 1
    B27 VTT U12
    VCCA_CRT_DAC VTT 1 1 1

    C71

    C72

    C78

    C79
    A26 T12 +
    VCCA_CRT_DAC VTT
    U11
    VTT
    2.68mA T11
    VTT 2 2 2 2
    A25 U10

    CRT
    VCCA_DAC_BG VTT
    B25 T10
    VSSA_DAC_BG VTT
    D U9 D
    VTT
    T9
    VTT
    U8
    VTT
    F47 64.8mA T8
    VCCA_DPLLA VTT

    0.47U_0603_10V7K

    4.7U_0805_10V4Z

    2.2U_0805_16V4Z
    U7

    VTT
    VTT +1.8V_SM_CK +1.8V
    L48 64.8mA T7 1 1 1

    PLL
    VCCA_DPLLB VTT R95
    U6
    VTT

    0.1U_0402_16V4Z
    C80

    C81

    C82
    +1.05VS_HPLL AD1 24mA T6 1 2
    VCCA_HPLL VTT

    10U_0805_10V4Z

    10U_0805_10V4Z
    U5 0_0805_5%
    VTT 2 2 2 @
    +1.05VS_MPLL AE1 139.2mA T5 1 1 1
    VCCA_MPLL VTT

    C84

    C85
    V3
    VTT
    13.2mA U3

    A LVDS
    VTT

    C83
    J48 V2
    VCCA_LVDS VTT 2 2 2
    U2
    VTT
    J47 T2
    VSSA_LVDS VTT
    V1
    @ R96 VTT
    414uA U1
    VTT
    +3VS 1 2
    0_0603_5% AD48
    +1.5VS_PEG_BG VCCA_PEG_BG
    R97

    A PEG
    +1.5VS 1 2
    0_0603_5% +1.05VS_HPLL +VCCP +1.5VS_TVDAC +1.5VS
    50mA
    1 +1.05VS_PEGPLL AA48 R98 R99
    C89 VCCA_PEG_PLL
    1 2 1 2

    0.022U_0402_16V7K

    0.1U_0402_16V4Z
    MBK2012121YZF_0805 0_0805_5%
    0.1U_0402_16V4Z AR20
    2 VCCA_SM

    0.1U_0402_16V4Z

    10U_0805_10V4Z
    AP20 1 1 1 1
    VCCA_SM

    C90

    C91
    AN20 720mA
    VCCA_SM
    POWER

    C92

    C93
    AR17
    VCCA_SM
    AP17
    +VCCP VCCA_SM 2 2 2 2
    +1.05VS_A_SM
    AN17
    VCCA_SM
    AT16
    R100 VCCA_SM
    AR16
    VCCA_SM

    A SM
    1 2 AP16
    C VCCA_SM C
    10U_0805_10V4Z

    1 0_0805_5%
    1 1 1
    C94

    C95

    + C96 C97
    +VCC_PEG +VCCP
    220U_D2_4VM 4.7U_0805_10V4Z
    <BOM Structure>

    2 2 2 2 321.35mA +1.05VS_MPLL +VCCP R102


    1U_0603_10V4Z AP28 R101 1 2
    VCCA_SM_CK 0_0805_5%
    AN28 B22 +V1.05VS_AXF 1 2
    VCCA_SM_CK VCC_AXF

    10U_0805_10V4Z
    AP25 26mA B21 MBK2012121YZF_0805 1

    AXF
    +1.05VS_A_SM_CK VCCA_SM_CK VCC_AXF

    220U_D2_4VM
    R103 AN25 A21 1
    VCCA_SM_CK VCC_AXF

    C101
    1 2 AN24 26mA +
    VCCA_SM_CK 1 1
    1U_0603_10V4Z

    0.1U_0402_16V4Z

    C98
    0_0603_5% AM28 124mA C99 C100
    VCCA_SM_CK_NCTF
    10U_0805_10V4Z

    AM26
    VCCA_SM_CK_NCTF 2 2
    1 1 1 1 AM25
    VCCA_SM_CK_NCTF A CK 0.1U_0402_16V4Z
    2 2
    10U_0805_10V4Z
    C103

    C104

    C105

    C102 AL25 BF21 +1.8V_SM_CK

    SM CK
    VCCA_SM_CK_NCTF VCC_SM_CK
    AM24 BH20
    1U_0603_10V4Z AL24 VCCA_SM_CK_NCTF VCC_SM_CK BG20
    2 2 2 2 VCCA_SM_CK_NCTF VCC_SM_CK
    AM23 BF20
    VCCA_SM_CK_NCTF VCC_SM_CK
    AL23
    VCCA_SM_CK_NCTF
    118.8mA
    TVA 24.15mA +1.05VS_DMI
    K47 +1.05VS_PEGPLL +VCCP +VCCP
    TVB 39.48mA VCC_TX_LVDS
    B24 L1 R104
    TVX 24.15mA
    VCCA_TV_DAC +3VS_HV
    A24 C35 1 2 1 2
    TV

    VCCA_TV_DAC VCC_HV BLM18PG121SN1D_0603 0_0603_5%


    105.3mA B35
    VCC_HV

    0.1U_0402_16V4Z

    10U_0805_10V4Z

    0.1U_0402_16V4Z
    A35
    HV

    VCC_HV
    1 1

    0.1U_0402_16V4Z

    C106

    C108
    +1.5VS A32 50mA 1
    HDA

    VCC_HDA

    C109
    V48 +VCC_PEG 1
    VCC_PEG

    C107
    1732mA VCC_PEG
    U48
    V47 2 2
    PEG

    VCC_PEG 2
    U47
    VCC_PEG
    D TV/CRT

    M25 58.67mA U46 2


    +1.5VS_TVDAC VCCD_TVDAC VCC_PEG
    B L28 48.363mA B
    VCCD_QDAC
    AH48 +1.05VS_DMI
    VCC_DMI
    +1.05VS_HPLL AF1
    VCCD_HPLL
    157.2mA VCC_DMI
    AF48
    AH47
    DMI

    VCC_DMI
    +1.05VS_PEGPLL AA47 50mA AG47
    VCCD_PEG_PLL VCC_DMI +VCCP_D
    456mA
    M38
    LVDS

    VCCD_LVDS D3 R105 R106


    L37 A8
    VTTLF

    VCCD_LVDS VTTLF
    L1 +VCCP 2 1 1 2 1 2 +3VS_HV
    VTTLF 10_0402_5% 0_0402_5%
    60.31mA AB2
    VTTLF CH751H-40PT_SOD323-2
    0.47U_0603_10V7K

    0.47U_0603_10V7K

    0.47U_0603_10V7K

    +3VS
    1 1 1
    C110

    C111

    C112

    CANTIGA ES_FCBGA1329

    2 2 2

    A A

    Security Classification Compal Secret Data


    Title
    Compal Electronics, Inc.
    Issued Date 2007/09/26 Deciphered Date 2007/09/26

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cantiga(4/6)-PWR
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 12 of 51
    5 4 3 2 1
    5 4 3 2 1

    U2G
    3000mA
    Extnal Graphic: 1210.34mA AP33
    VCC_SM VCC_AXG_NCTF
    W28
    AN33 V28
    integrated Graphic: 1930.4mA VCC_SM VCC_AXG_NCTF
    +1.8V BH32 W26
    U2F VCC_SM VCC_AXG_NCTF
    BG32 V26
    +VCCP VCC_SM VCC_AXG_NCTF

    330U_D2E_2.5VM_R7

    0.01U_0402_16V7K
    BF32 W25
    VCC_SM VCC_AXG_NCTF

    10U_0805_10V4Z

    10U_0805_10V4Z
    1 BD32 V25
    VCC_SM VCC_AXG_NCTF
    1 1 2 BC32 W24
    VCC_SM VCC_AXG_NCTF

    C126

    C122

    C130

    C123
    D AG34 + BB32 V24 D
    VCC VCC_SM VCC_AXG_NCTF
    AC34 BA32 W23
    VCC VCC_SM VCC_AXG_NCTF
    AB34 AY32 V23
    VCC 2 2 2 1 VCC_SM VCC_AXG_NCTF
    AA34 AW32 AM21
    VCC VCC_SM VCC_AXG_NCTF
    Y34 AV32 AL21
    VCC VCC_SM VCC_AXG_NCTF
    V34 AU32 AK21
    VCC VCC_SM VCC_AXG_NCTF
    U34 AT32 W21
    VCC 0317 change value VCC_SM VCC_AXG_NCTF
    AM33 AR32 V21
    VCC VCC_SM VCC_AXG_NCTF
    AK33 AP32 U21
    VCC VCC_SM VCC_AXG_NCTF

    POWER
    AJ33 AN32 AM20
    VCC VCC_SM VCC_AXG_NCTF
    0.22U_0402_10V4Z

    0.22U_0402_10V4Z

    0.1U_0402_16V4Z
    AG33 BH31 AK20
    VCC VCC_SM VCC_AXG_NCTF
    220U_D2_4VM

    10U_0805_10V4Z

    1 AF33 BG31 W20


    VCC VCC_SM VCC_AXG_NCTF

    VCC CORE
    1 1 1 1 BF31 U20
    VCC_SM VCC_AXG_NCTF
    C131

    C124

    C132

    C133

    + C125
    AE33 BG30 AM19
    VCC VCC_SM VCC_AXG_NCTF
    AC33 BH29 AL19
    VCC VCC_SM VCC_AXG_NCTF
    AA33 BG29 AK19
    2 2 2 2 2 VCC VCC_SM VCC_AXG_NCTF
    Y33 BF29 AJ19
    VCC VCC_SM VCC_AXG_NCTF
    W33 BD29 AH19
    VCC VCC_SM VCC_AXG_NCTF
    V33 BC29 AG19

    VCC SM
    VCC VCC_SM VCC_AXG_NCTF
    U33 BB29 AF19
    VCC VCC_SM VCC_AXG_NCTF
    AH28 BA29 AE19
    VCC VCC_SM VCC_AXG_NCTF
    AF28 AY29 AB19
    VCC VCC_SM VCC_AXG_NCTF
    AC28 AW29 AA19
    VCC VCC_SM VCC_AXG_NCTF
    AA28 AV29 Y19
    VCC VCC_SM VCC_AXG_NCTF
    AJ26 AU29 W19
    VCC VCC_SM VCC_AXG_NCTF
    AG26 AT29 V19
    VCC VCC_SM VCC_AXG_NCTF
    AE26 AR29 U19
    VCC VCC_SM VCC_AXG_NCTF
    AC26 AP29 AM17
    VCC VCC_SM VCC_AXG_NCTF
    AH25 AK17
    VCC VCC_AXG_NCTF
    AG25 BA36 AH17
    VCC VCC_SM/NC VCC_AXG_NCTF
    AF25 BB24 AG17
    VCC VCC_SM/NC VCC_AXG_NCTF
    AG24 BD16 AF17
    C VCC +VCCP VCC_SM/NC VCC_AXG_NCTF C
    AJ23 BB21 AE17
    VCC VCC_SM/NC VCC_AXG_NCTF
    AH23 AW16 AC17
    VCC VCC_SM/NC VCC_AXG_NCTF
    AF23 AW13 AB17
    VCC VCC_SM/NC VCC_AXG_NCTF
    POWER
    AM32 AT13 Y17
    VCC_NCTF VCC_SM/NC VCC_AXG_NCTF
    T32 AL32 W17
    VCC VCC_NCTF VCC_AXG_NCTF
    VCC_NCTF
    AK32 6326.84mA VCC_AXG_NCTF
    V17
    AJ32 AM16

    VCC GFX NCTF


    VCC_NCTF VCC_AXG_NCTF
    AH32 Y26 AL16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AG32 AE25 AK16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AE32 AB25 AJ16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AC32 AA25 AH16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AA32 AE24 AG16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    Y32 AC24 AF16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    W32 AA24 AE16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    U32 Y24 AC16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AM30 AE23 AB16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AL30 AC23 AA16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AK30 AB23 Y16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AH30 AA23 W16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AG30 AJ21 V16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AF30 AG21 U16
    VCC_NCTF VCC_AXG VCC_AXG_NCTF
    AE30 AE21
    VCC_NCTF VCC_AXG
    AC30 AC21
    VCC_NCTF VCC_AXG
    AB30 AA21
    VCC_NCTF VCC_AXG
    AA30 Y21
    VCC_NCTF VCC_AXG
    Y30 AH20
    VCC_NCTF VCC_AXG
    VCC NCTF

    W30 AF20
    VCC_NCTF VCC_AXG
    V30 AE20
    VCC_NCTF VCC_AXG
    U30 AC20
    VCC_NCTF VCC_AXG
    AL29 AB20
    VCC_NCTF VCC_AXG
    AK29 AA20
    VCC_NCTF VCC_AXG
    AJ29 T17
    B VCC_NCTF VCC_AXG B
    AH29 T16
    VCC_NCTF VCC_AXG
    AG29 AM15
    VCC_NCTF VCC_AXG
    AE29 AL15
    VCC_NCTF VCC_AXG
    AC29 AE15
    VCC_NCTF VCC_AXG
    AA29 AJ15
    VCC_NCTF VCC_AXG
    Y29 AH15
    VCC_NCTF VCC_AXG
    W29 AG15
    VCC_NCTF VCC_AXG
    V29 AF15
    VCC_NCTF VCC_AXG
    AL28 AB15
    VCC_NCTF VCC_AXG
    AK28 AA15
    VCC_NCTF VCC_AXG
    AL26 Y15
    VCC_NCTF VCC_AXG

    VCC GFX
    AK26 V15
    VCC_NCTF VCC_AXG
    AK25 U15
    VCC_NCTF VCC_AXG
    AK24 AN14
    VCC_NCTF VCC_AXG
    AK23 AM14
    VCC_NCTF VCC_AXG
    U14 AV44 VCCSM_LF1
    VCC_AXG VCC_SM_LF
    T14 BA37 VCCSM_LF2
    VCC_AXG VCC_SM_LF

    VCC SM LF
    AM40 VCCSM_LF3
    VCC_SM_LF
    AV21 VCCSM_LF4
    VCC_SM_LF
    AY5 VCCSM_LF5
    VCC_SM_LF
    AM10 VCCSM_LF6
    CANTIGA ES_FCBGA1329 VCC_SM_LF
    BB13 VCCSM_LF7
    VCC_SM_LF

    C139

    C140

    C141

    C142

    C143

    C144

    C145
    1 1 1 1 1 1 1

    PAD T42 AJ14


    VCC_AXG_SENSE

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    PAD T43 AH14
    VSS_AXG_SENSE 2 2 2 2 2 2 2

    0.22U_0603_10V7K

    0.22U_0603_10V7K

    0.47U_0402_6.3V6K

    1U_0603_10V4Z

    1U_0603_10V4Z
    A A

    CANTIGA ES_FCBGA1329

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    Cantiga(5/6)-PWR/GND

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 13 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    U2J
    U2I BG21 AH8
    VSS VSS
    L12 Y8
    VSS VSS
    AU48 AM36 AW21 L8
    VSS VSS VSS VSS
    AR48 AE36 AU21 E8
    VSS VSS VSS VSS
    AL48 P36 AP21 B8
    VSS VSS VSS VSS
    BB47 L36 AN21 AY7
    VSS VSS VSS VSS
    AW47 J36 AH21 AU7
    VSS VSS VSS VSS
    AN47 F36 AF21 AN7
    VSS VSS VSS VSS
    AJ47 B36 AB21 AJ7
    VSS VSS VSS VSS
    AF47 AH35 R21 AE7
    D VSS VSS VSS VSS D
    AD47 AA35 M21 AA7
    VSS VSS VSS VSS
    AB47 Y35 J21 N7
    VSS VSS VSS VSS
    Y47 U35 G21 J7
    VSS VSS VSS VSS
    T47 T35 BC20 BG6
    VSS VSS VSS VSS
    N47 BF34 BA20 BD6
    VSS VSS VSS VSS
    L47 AM34 AW20 AV6
    VSS VSS VSS VSS
    G47 AJ34 AT20 AT6
    VSS VSS VSS VSS
    BD46 AF34 AJ20 AM6
    VSS VSS VSS VSS
    BA46 AE34 AG20 M6
    VSS VSS VSS VSS
    AY46 W34 Y20 C6
    VSS VSS VSS VSS
    AV46 B34 N20 BA5
    VSS VSS VSS VSS
    AR46 A34 K20 AH5
    VSS VSS VSS VSS
    AM46 BG33 F20 AD5
    VSS VSS VSS VSS
    V46 BC33 C20 Y5
    VSS VSS VSS VSS
    R46 BA33 A20 L5
    VSS VSS VSS VSS
    P46 AV33 BG19 J5
    VSS VSS VSS VSS
    H46 AR33 A18 H5
    VSS VSS VSS VSS
    F46 AL33 BG17 F5
    VSS VSS VSS VSS
    BF44 AH33 BC17 BE4
    VSS VSS VSS VSS
    AH44 AB33 AW17
    VSS VSS VSS
    AD44 P33 AT17 BC3
    AA44
    Y44
    VSS
    VSS
    VSS
    VSS
    VSS
    VSS
    L33
    H33
    R17
    M17
    VSS
    VSS
    VSS
    VSS VSS
    VSS
    VSS
    AV3
    AL3
    U44 N32 H17 R3
    VSS VSS VSS VSS
    T44 K32 C17 P3
    M44
    F44
    VSS
    VSS
    VSS
    VSS VSS
    VSS
    VSS
    F32
    C32 BA16
    VSS

    VSS
    VSS
    VSS
    VSS
    F3
    BA2
    BC43 A31 AW2
    VSS VSS VSS
    AV43 AN29 AU16 AU2
    VSS VSS VSS VSS
    AU43 T29 AN16 AR2
    VSS VSS VSS VSS
    AM43 N29 N16 AP2
    VSS VSS VSS VSS
    J43 K29 K16 AJ2
    C VSS VSS VSS VSS C
    C43 H29 G16 AH2
    VSS VSS VSS VSS
    BG42 F29 E16 AF2
    VSS VSS VSS VSS
    AY42 A29 BG15 AE2
    VSS VSS VSS VSS
    AT42 BG28 AC15 AD2
    VSS VSS VSS VSS
    AN42 BD28 W15 AC2
    VSS VSS VSS VSS
    AJ42 BA28 A15 Y2
    VSS VSS VSS VSS
    AE42 AV28 BG14 M2
    VSS VSS VSS VSS
    N42 AT28 AA14 K2
    VSS VSS VSS VSS
    L42 AR28 C14 AM1
    VSS VSS VSS VSS
    BD41 AJ28 BG13 AA1
    VSS VSS VSS VSS
    AU41 AG28 BC13 P1
    VSS VSS VSS VSS
    AM41 AE28 BA13 H1
    VSS VSS VSS VSS
    AH41 AB28
    VSS VSS
    AD41 Y28 U24
    VSS VSS VSS
    AA41 P28 AN13 U28
    VSS VSS VSS VSS
    Y41 K28 AJ13 U25
    VSS VSS VSS VSS
    U41 H28 AE13 U29
    VSS VSS VSS VSS
    T41 F28 N13
    VSS VSS VSS
    M41 C28 L13
    VSS VSS VSS
    G41 BF26 G13 AF32
    VSS VSS VSS VSS_NCTF
    B41 AH26 E13 AB32
    VSS VSS VSS VSS_NCTF
    BG40 AF26 BF12 V32
    VSS VSS VSS VSS_NCTF
    BB40 AB26 AV12 AJ30
    VSS VSS VSS VSS_NCTF
    AV40 AA26 AT12 AM29
    VSS VSS VSS VSS_NCTF
    AN40 C26 AM12 AF29
    VSS VSS VSS VSS_NCTF
    H40 B26 AA12 AB29
    VSS VSS VSS VSS_NCTF

    VSS NCTF
    E40 BH25 J12 U26
    VSS VSS VSS VSS_NCTF
    AT39 BD25 A12 U23
    VSS VSS VSS VSS_NCTF
    AM39 BB25 BD11 AL20
    VSS VSS VSS VSS_NCTF
    AJ39 AV25 BB11 V20
    VSS VSS VSS VSS_NCTF
    AE39 AR25 AY11 AC19
    VSS VSS VSS VSS_NCTF
    N39 AJ25 AN11 AL17
    B VSS VSS VSS VSS_NCTF B
    L39 AC25 AH11 AJ17
    VSS VSS VSS VSS_NCTF
    B39 Y25 AA17
    VSS VSS VSS_NCTF
    BH38 N25 Y11 U17
    VSS VSS VSS VSS_NCTF
    BC38 L25 N11
    VSS VSS VSS
    BA38 J25 G11
    VSS VSS VSS
    AU38 G25 C11 BH48
    VSS VSS VSS VSS_SCB

    VSS SCB
    AH38 E25 BG10 BH1
    VSS VSS VSS VSS_SCB
    AD38 BF24 AV10 A48
    VSS VSS VSS VSS_SCB
    AA38 AD12 AT10 C1
    VSS VSS VSS VSS_SCB
    Y38 AY24 AJ10 A3
    VSS VSS VSS VSS_SCB
    U38 AT24 AE10
    VSS VSS VSS
    T38 AJ24 AA10 E1
    VSS VSS VSS NC
    J38 AH24 M10 D2
    VSS VSS VSS NC
    F38 AF24 BF9 C3
    VSS VSS VSS NC
    C38 AB24 BC9 B4
    VSS VSS VSS NC
    BF37 R24 AN9 A5
    VSS VSS VSS NC
    BB37 L24 AM9 A6
    VSS VSS VSS NC
    AW37 K24 AD9 A43
    VSS VSS VSS NC
    AT37 J24 G9 A44
    VSS VSS VSS NC
    AN37 G24 B9 B45

    NC
    VSS VSS VSS NC
    AJ37 F24 BH8 C46
    VSS VSS VSS NC
    H37 E24 BB8 D47
    VSS VSS VSS NC
    C37 BH23 AV8 B47
    VSS VSS VSS NC
    BG36 AG23 AT8 A46
    VSS VSS VSS NC
    BD36 Y23 F48
    VSS VSS NC
    AK15 B23 E48
    VSS VSS NC
    AU36 A23 C48
    VSS VSS NC
    AJ6 B48
    VSS NC

    CANTIGA ES_FCBGA1329 CANTIGA ES_FCBGA1329


    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Cantiga(6/6)-PWR/GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 14 of 51
    5 4 3 2 1
    5 4 3 2 1

    +1.8V +1.8V

    10 DDR_A_DQS#[0..7] V_DDR_MCH_REF
    V_DDR_MCH_REF 9,16

    10 DDR_A_D[0..63] JDIMM1

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z
    1 2
    VREF VSS

    C146

    C151
    10 DDR_A_DM[0..7] 3 4 DDR_A_D5 1 1
    DDR_A_D4 VSS DQ4 DDR_A_D0
    5 6
    DDR_A_D1 DQ0 DQ5
    10 DDR_A_DQS[0..7] 7 8
    DQ1 VSS DDR_A_DM0
    9 10
    DDR_A_DQS#0 VSS DM0 2 2
    10 DDR_A_MA[0..14] 11 12
    DDR_A_DQS0 DQS0# VSS DDR_A_D6
    13 14
    DQS0 DQ6 DDR_A_D7
    15 16
    DDR_A_D2 VSS DQ7
    17 18
    D DDR_A_D3 DQ2 VSS DDR_A_D13 D
    19 20
    DQ3 DQ12 DDR_A_D12
    Layout Note: DDR_A_D8
    21
    VSS DQ13
    22
    23 24
    Place near DDR_A_D9 DQ8 VSS DDR_A_DM1
    25 26
    DQ9 DM1
    JP3 27 28
    DDR_A_DQS#1 VSS VSS M_CLK_DDR0
    29 30 M_CLK_DDR0 9
    DDR_A_DQS1 DQS1# CK0 M_CLK_DDR#0
    31 32 M_CLK_DDR#0 9
    DQS1 CK0#
    33 34
    DDR_A_D11 VSS VSS DDR_A_D15
    35 36
    DDR_A_D10 DQ10 DQ14 DDR_A_D14
    37 38
    +1.8V DQ11 DQ15
    39 40
    VSS VSS

    330U_D2E_2.5VM_R7
    41 42
    VSS VSS
    2.2U_0805_16V4Z

    2.2U_0805_16V4Z

    2.2U_0805_16V4Z

    2.2U_0805_16V4Z

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    1 DDR_A_D16 43 44 DDR_A_D20
    DDR_A_D17 DQ16 DQ20 DDR_A_D21
    1 1 1 1 1 1 1 1 1 45 46
    DQ17 DQ21
    C152

    C147

    C153

    C154

    C155

    C156

    C148

    C149

    C157

    C150
    + 47 48
    DDR_A_DQS#2 VSS VSS
    49 50 PM_EXTTS#0 9
    DDR_A_DQS2 DQS2# NC DDR_A_DM2
    51 52
    2 2 2 2 2 2 2 2 2 2 DQS2 DM2
    53 54
    DDR_A_D18 VSS VSS DDR_A_D23
    55 56
    DDR_A_D19 DQ18 DQ22 DDR_A_D22
    57 58
    DQ19 DQ23
    59 60
    DDR_A_D29 VSS VSS DDR_A_D28
    61 62
    DDR_A_D24 DQ24 DQ28 DDR_A_D25
    63 64
    DQ25 DQ29
    65 66
    DDR_A_DM3 VSS VSS DDR_A_DQS#3
    67 68
    DM3 DQS3# DDR_A_DQS3
    69 70
    NC DQS3
    71 72
    DDR_A_D26 VSS VSS DDR_A_D31
    73 74
    DDR_A_D27 DQ26 DQ30 DDR_A_D30
    75 76
    DQ27 DQ31
    77 78
    C DDR_CKE0_DIMMA VSS VSS DDR_CKE1_DIMMA C
    Layout Note: 9 DDR_CKE0_DIMMA 79
    CKE0 NC/CKE1
    80 DDR_CKE1_DIMMA 9
    81 82
    Place one cap close to every 2 VDD VDD
    83 84
    DDR_A_BS2 NC NC/A15 DDR_A_MA14
    pullup 10 DDR_A_BS2 85 86
    BA2 NC/A14
    87 88
    VDD VDD
    resistors terminated to +0.9VS DDR_A_MA12 89
    A12 A11
    90 DDR_A_MA11
    DDR_A_MA9 91 92 DDR_A_MA7
    DDR_A_MA8 A9 A7 DDR_A_MA6
    93 94
    A8 A6
    95 96
    DDR_A_MA5 VDD VDD DDR_A_MA4
    97 98
    DDR_A_MA3 A5 A4 DDR_A_MA2
    99 100
    DDR_A_MA1 A3 A2 DDR_A_MA0
    101 102
    +0.9V A1 A0
    103 104
    DDR_A_MA10 VDD VDD DDR_A_BS1
    105 106 DDR_A_BS1 10
    DDR_A_BS0 A10/AP BA1 DDR_A_RAS#
    5 10 10 DDR_A_BS0 107
    BA0 RAS#
    108 DDR_A_RAS# 10
    DDR_A_WE# 109 110 DDR_CS0_DIMMA#
    10 DDR_A_WE# WE# S0# DDR_CS0_DIMMA# 9
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    111 112
    DDR_A_CAS# VDD VDD M_ODT0
    10 DDR_A_CAS# 113 114 M_ODT0 9
    DDR_CS1_DIMMA# CAS# ODT0 DDR_A_MA13
    1 1 1 1 1 1 1 1 1 1 1 1 1 115 116
    9 DDR_CS1_DIMMA# NC/S1# NC/A13
    117 118
    M_ODT1 VDD VDD
    9 M_ODT1 119 120
    NC/ODT1 NC
    121 122
    2 2 2 2 2 2 2 2 2 2 2 2 2 DDR_A_D37 VSS VSS DDR_A_D32
    123 124
    DQ32 DQ36
    C158

    C159

    C160

    C161

    C162

    C163

    C164

    C165

    C166

    C167

    C168

    C169

    C170

    DDR_A_D36 125 126 DDR_A_D33


    DQ33 DQ37
    127 128
    DDR_A_DQS#4 VSS VSS DDR_A_DM4
    129 130
    DDR_A_DQS4 DQS4# DM4
    131 132
    DQS4 VSS DDR_A_D34
    133 134
    DDR_A_D39 VSS DQ38 DDR_A_D35
    135 136
    DDR_A_D38 DQ34 DQ39
    137 138
    DQ35 VSS DDR_A_D40
    139 140
    DDR_A_D45 VSS DQ44 DDR_A_D41
    141 142
    B DDR_A_D44 DQ40 DQ45 B
    143 144
    DQ41 VSS DDR_A_DQS#5
    145 146
    DDR_A_DM5 VSS DQS5# DDR_A_DQS5
    147 148
    +0.9V DM5 DQS5
    Layout Note: DDR_A_D47
    149
    VSS VSS
    150
    DDR_A_D43
    151 152
    56_0404_4P2R_5% RP1 RP2 56_0404_4P2R_5% Place these resistor DDR_A_D46 DQ42 DQ46 DDR_A_D42
    153 154
    DDR_A_MA8 DQ43 DQ47
    1 4 4 1 DDR_A_BS2 155 156
    DDR_A_MA5 2 3 3 2 DDR_CKE0_DIMMA
    closely JP3,all DDR_A_D49 157
    VSS VSS
    158 DDR_A_D52
    DQ48 DQ52
    trace length Max=1.5" DDR_A_D48 159
    DQ49 DQ53
    160 DDR_A_D53
    161 162
    56_0404_4P2R_5% RP3 RP4 56_0404_4P2R_5% VSS VSS M_CLK_DDR1
    163 164 M_CLK_DDR1 9
    DDR_A_MA1 NC,TEST CK1
    1 4 4 1 DDR_A_MA7 165 166 M_CLK_DDR#1
    M_CLK_DDR#1 9
    DDR_A_MA3 VSS CK1#
    2 3 3 2 DDR_A_MA6 DDR_A_DQS#6 167 168
    DDR_A_DQS6 DQS6# VSS DDR_A_DM6
    169 170
    DQS6 DM6
    171 172
    56_0404_4P2R_5% RP5 RP6 56_0404_4P2R_5% DDR_A_D54 VSS VSS DDR_A_D51
    173 174
    DDR_A_RAS# DQ50 DQ54
    1 4 4 1 DDR_A_MA12 DDR_A_D50 175 176 DDR_A_D55
    DDR_CS0_DIMMA# DQ51 DQ55
    2 3 3 2 DDR_A_MA9 177 178
    DDR_A_D61 VSS VSS DDR_A_D57
    179 180
    DDR_A_D60 DQ56 DQ60 DDR_A_D56
    181 182
    56_0404_4P2R_5% RP7 RP8 56_0404_4P2R_5% DQ57 DQ61
    183 184
    DDR_A_BS0 VSS VSS
    1 4 4 1 DDR_A_MA4 DDR_A_DM7 185 186 DDR_A_DQS#7
    DDR_A_MA10 DM7 DQS7#
    2 3 3 2 DDR_A_MA2 187 188 DDR_A_DQS7
    DDR_A_D59 VSS DQS7
    189 190
    DDR_A_D58 DQ58 VSS DDR_A_D62
    191 192
    56_0404_4P2R_5% RP9 RP10 56_0404_4P2R_5% DQ59 DQ62 DDR_A_D63
    193 194
    DDR_A_CAS# VSS DQ63
    1 4 4 1 DDR_A_MA0 16,17 CLK_SMBDATA
    CLK_SMBDATA 195 196
    DDR_A_WE# SDA VSS
    2 3 3 2 DDR_A_BS1 16,17 CLK_SMBCLK
    CLK_SMBCLK 197 198
    SCL SAO
    +3VS 199 200
    VDDSPD SA1

    1
    56_0404_4P2R_5% RP11 RP12 56_0404_4P2R_5%

    10K_0402_5%

    10K_0402_5%
    1 1
    2.2U_0603_6.3V4Z

    DDR_CS1_DIMMA# 2 3 4 1 M_ODT0 FOX_ASOA426-M4R-TR


    0.1U_0402_16V4Z

    A M_ODT1 2 DDR_A_MA13 C171 C172 A

    R115

    R116
    1 4 3
    2 2
    SO-DIMM A

    om
    RP13 56_0404_4P2R_5%
    4 1 DDR_CKE1_DIMMA

    l.c
    DDR_A_MA11 1 2 3 2 DDR_A_MA14

    ai
    R117 56_0402_5%
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    DDRII-SODIMM SLOT1

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 15 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    +1.8V +1.8V
    10 DDR_B_DQS#[0..7]

    10 DDR_B_D[0..63] V_DDR_MCH_REF
    V_DDR_MCH_REF 9,15

    10 DDR_B_DM[0..7] JDIMM2

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z
    1 2
    VREF VSS DDR_B_D5
    10 DDR_B_DQS[0..7] 3 4 1 1
    DDR_B_D0 VSS DQ4 DDR_B_D4
    5 6
    DQ0 DQ5

    C173

    C182
    10 DDR_B_MA[0..14] DDR_B_D1 7 8
    DQ1 VSS DDR_B_DM0
    9 10
    DDR_B_DQS#0 VSS DM0 2 2
    11 12
    DDR_B_DQS0 DQS0# VSS DDR_B_D6
    13 14
    DQS0 DQ6 DDR_B_D7
    15 16
    D DDR_B_D2 VSS DQ7 D
    17 18
    DDR_B_D3 DQ2 VSS DDR_B_D12
    Layout Note: 19
    DQ3 DQ12
    20
    DDR_B_D13
    21 22
    Place near DDR_B_D8 VSS DQ13
    23 24
    DDR_B_D9 DQ8 VSS DDR_B_DM1
    JP10 25 26
    DQ9 DM1
    27 28
    DDR_B_DQS#1 VSS VSS M_CLK_DDR2
    29 30 M_CLK_DDR2 9
    DDR_B_DQS1 DQS1# CK0 M_CLK_DDR#2
    31 32 M_CLK_DDR#2 9
    DQS1 CK0#
    33 34
    DDR_B_D10 VSS VSS DDR_B_D14
    35 36
    DDR_B_D11 DQ10 DQ14 DDR_B_D15
    37 38
    +1.8V DQ11 DQ15
    39 40
    VSS VSS
    5
    41 42
    VSS VSS
    2.2U_0805_16V4Z

    2.2U_0805_16V4Z

    2.2U_0805_16V4Z

    2.2U_0805_16V4Z

    2.2U_0805_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    DDR_B_D21 43 44 DDR_B_D16
    DDR_B_D20 DQ16 DQ20 DDR_B_D17
    1 1 1 1 1 1 1 1 1 45 46
    DQ17 DQ21
    C174

    C175

    C176

    C183

    C177

    C178

    C179

    C180

    C181
    47 48
    DDR_B_DQS#2 VSS VSS
    49 50 PM_EXTTS#1 9
    DDR_B_DQS2 DQS2# NC DDR_B_DM2
    51 52
    2 2 2 2 2 2 2 2 2 DQS2 DM2
    53 54
    DDR_B_D19 VSS VSS DDR_B_D22
    55 56
    DDR_B_D18 DQ18 DQ22 DDR_B_D23
    57 58
    DQ19 DQ23
    59 60
    DDR_B_D28 VSS VSS DDR_B_D29
    61 62
    DDR_B_D25 DQ24 DQ28 DDR_B_D24
    63 64
    DQ25 DQ29
    65 66
    DDR_B_DM3 VSS VSS DDR_B_DQS#3
    67 68
    DM3 DQS3# DDR_B_DQS3
    69 70
    NC DQS3
    71 72
    DDR_B_D30 VSS VSS DDR_B_D26
    73 74
    DDR_B_D31 DQ26 DQ30 DDR_B_D27
    C
    Layout Note: 75
    DQ27 DQ31
    76
    C
    77 78
    Place one cap close to every 2 DDR_CKE2_DIMMB VSS VSS DDR_CKE3_DIMMB
    9 DDR_CKE2_DIMMB 79 80 DDR_CKE3_DIMMB 9
    CKE0 NC/CKE1
    pullup 81 82
    VDD VDD
    83 84
    NC NC/A15
    resistors terminated to +0.9VS 10 DDR_B_BS2
    DDR_B_BS2 85
    BA2 NC/A14
    86 DDR_B_MA14
    87
    VDD VDD
    88 0612 add
    DDR_B_MA12 89 90 DDR_B_MA11
    DDR_B_MA9 A12 A11 DDR_B_MA7
    91 92
    DDR_B_MA8 A9 A7 DDR_B_MA6
    93 94
    A8 A6
    95 96
    DDR_B_MA5 VDD VDD DDR_B_MA4
    97 98
    +0.9V DDR_B_MA3 A5 A4 DDR_B_MA2
    99 100
    DDR_B_MA1 A3 A2 DDR_B_MA0
    101 102
    A1 A0
    5 10 103
    VDD VDD
    104
    DDR_B_MA10 105 106 DDR_B_BS1
    A10/AP BA1 DDR_B_BS1 10
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    DDR_B_BS0 107 108 DDR_B_RAS#


    10 DDR_B_BS0 BA0 RAS# DDR_B_RAS# 10
    DDR_B_WE# 109 110 DDR_CS2_DIMMB#
    10 DDR_B_WE# WE# S0# DDR_CS2_DIMMB# 9
    1 1 1 1 1 1 1 1 1 1 1 1 1 111 112
    DDR_B_CAS# VDD VDD M_ODT2
    10 DDR_B_CAS# 113 114 M_ODT2 9
    DDR_CS3_DIMMB# CAS# ODT0 DDR_B_MA13
    9 DDR_CS3_DIMMB# 115 116
    NC/S1# NC/A13
    117 118
    2 2 2 2 2 2 2 2 2 2 2 2 2 M_ODT3 VDD VDD
    9 M_ODT3 119 120
    NC/ODT1 NC
    C184

    C185

    C186

    C187

    C188

    C189

    C190

    C191

    C192

    C193

    C194

    C195

    C196

    121 122
    DDR_B_D32 VSS VSS DDR_B_D36
    123 124
    DDR_B_D37 DQ32 DQ36 DDR_B_D33
    125 126
    DQ33 DQ37
    127 128
    DDR_B_DQS#4 VSS VSS DDR_B_DM4
    129 130
    DDR_B_DQS4 DQS4# DM4
    131 132
    DQS4 VSS DDR_B_D39
    133 134
    DDR_B_D34 VSS DQ38 DDR_B_D38
    135 136
    DDR_B_D35 DQ34 DQ39
    137 138
    DQ35 VSS DDR_B_D44
    139 140
    B DDR_B_D40 VSS DQ44 DDR_B_D45 B
    Layout Note: DDR_B_D41
    141
    DQ40 DQ45
    142
    143 144
    Place these resistor DQ41 VSS DDR_B_DQS#5
    145 146
    +0.9V DDR_B_DM5 VSS DQS5# DDR_B_DQS5
    closely JP3,all 147 148
    DM5 DQS5
    149 150
    VSS VSS
    trace length Max=1.5" DDR_B_D42 151
    DQ42 DQ46
    152 DDR_B_D46
    56_0404_4P2R_5% RP14 RP15 56_0404_4P2R_5% DDR_B_D43 153 154 DDR_B_D47
    DDR_B_MA3 DDR_B_MA12 DQ43 DQ47
    1 4 4 1 155 156
    DDR_B_MA1 DDR_B_MA9 DDR_B_D55 VSS VSS DDR_B_D51
    2 3 3 2 157 158
    DDR_B_D50 DQ48 DQ52 DDR_B_D54
    159 160
    DQ49 DQ53
    161 162
    56_0404_4P2R_5% RP16 RP17 56_0404_4P2R_5% VSS VSS M_CLK_DDR3
    163 164 M_CLK_DDR3 9
    DDR_B_BS0 DDR_B_MA11 NC,TEST CK1 M_CLK_DDR#3
    1 4 4 1 165 166 M_CLK_DDR#3 9
    DDR_B_MA10 DDR_B_MA14 DDR_B_DQS#6 VSS CK1#
    2 3 3 2 167 168
    DDR_B_DQS6 DQS6# VSS DDR_B_DM6
    169 170
    DQS6 DM6
    171 172
    56_0404_4P2R_5% RP18 RP19 56_0404_4P2R_5% DDR_B_D52 VSS VSS DDR_B_D49
    173 174
    DDR_B_MA0 DDR_B_MA5 DDR_B_D53 DQ50 DQ54 DDR_B_D48
    1 4 4 1 175 176
    DDR_B_BS1 DDR_B_MA8 DQ51 DQ55
    2 3 3 2 177 178
    DDR_B_D60 VSS VSS DDR_B_D56
    179 180
    DDR_B_D61 DQ56 DQ60 DDR_B_D57
    181 182
    56_0404_4P2R_5% RP20 RP21 56_0404_4P2R_5% DQ57 DQ61
    183 184
    DDR_CS2_DIMMB# DDR_B_MA6 DDR_B_DM7 VSS VSS DDR_B_DQS#7
    1 4 4 1 185 186
    DDR_B_RAS# DDR_B_MA7 DM7 DQS7# DDR_B_DQS7
    2 3 3 2 187 188
    DDR_B_D63 VSS DQS7
    189 190
    DDR_B_D58 DQ58 VSS DDR_B_D59
    191 192
    56_0404_4P2R_5% RP22 RP23 56_0404_4P2R_5% DQ59 DQ62 DDR_B_D62
    193 194
    DDR_B_CAS# DDR_B_MA2 CLK_SMBDATA VSS DQ63
    1 4 4 1 15,17 CLK_SMBDATA 195 196
    DDR_B_WE# DDR_B_MA4 CLK_SMBCLK SDA VSS R118
    2 3 3 2 15,17 CLK_SMBCLK 197 198
    SCL SA0
    +3VS 199 200 1 2 +3VS
    VDDSPD SA1

    1
    10K_0402_5%
    56_0404_4P2R_5% RP24 RP25 56_0404_4P2R_5% 1 1 10K_0402_5%
    0.1U_0402_16V4Z
    2.2U_0603_6.3V4Z

    R119
    A DDR_CS3_DIMMB# 2 3 4 1 DDR_B_MA13 FOX_AS0A426-N8RN-7F A
    M_ODT3 1 4 3 2 M_ODT2 C197 C198
    2 2 SO-DIMM B

    2
    RP26 56_0404_4P2R_5%
    4 1 DDR_CKE2_DIMMB
    DDR_CKE3_DIMMB 1 2 3 2 DDR_B_BS2
    R120 56_0402_5%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DDRII-SODIMM SLOT2
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 16 of 51
    5 4 3 2 1
    5 4 3 2 1

    +3VS +3VS_CK505
    FSC FSB FSA CPU SRC PCI REF DOT_96 USB R121
    CLKSEL2 CLKSEL1 CLKSEL0 MHz MHz MHz MHz MHz MHz 1 2
    1 1 1 1 1 1 1
    0_0805_5% C199 C200 C201 C202 C203 C204 C205
    0 0 0 266 100 33.3 14.318 96.0 48.0
    10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2 2 2 2 2 2
    0 0 1 133 100 33.3 14.318 96.0 48.0
    Routing the trace at least 10mil +VCCP +1.05VS_CK505
    0 1 0 200 100 33.3 14.318 96.0 48.0
    CLK_XTAL_OUT

    D CLK_XTAL_IN R122
    Place close to U51 D
    0 1 1 166 100 33.3 14.318 96.0 48.0
    1 2 0.1U_0402_16V4Z 10U_0805_10V4Z 0.1U_0402_16V4Z
    Y1
    0_0805_5% 1 1 1 1 1 1 1
    1 0 0 333 100 33.3 14.318 96.0 48.0 2 1 14.31818MHZ_16P C206 C207 C208 C209 C210 C211 C212

    2 2 2 2 2 2 2
    1 0 1 100 100 33.3 14.318 96.0 48.0
    10U_0805_10V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    2 2
    1 1 0 400 100 33.3 14.318 96.0 48.0 C213 C214
    18P_0402_50V8J 18P_0402_50V8J
    1 1
    1 1 1 Reserved
    Vendor suggests 22pF
    R123 +3VS_CK505 +1.05VS_CK505
    1 2 +VCCP
    1

    56_0402_5% R_CPU_XDP R124 1 2 0_0402_5% XDP/ITP


    CLK_CPU_XDP 6
    CLRP1 R_CPU_XDP# R125 1 2 0_0402_5%
    CLK_CPU_XDP# 6
    NO SHORT PADS R126 1 2 475_0402_1% R_CLKREQ#_7 R_MCH_3GPLL R127 1 2 0_0402_5%
    9 CLKREQ#_7 CLK_MCH_3GPLL 9
    2

    R128 R130 0_0402_5% R_MCH_BCLK# R_MCH_3GPLL# R131 0_0402_5%


    9 CLK_MCH_BCLK# 1 2 1 2 CLK_MCH_3GPLL# 9 3G_PLL
    FSA 1 2 1 2 NB R132 1 2 0_0402_5% R_MCH_BCLK R_CLKREQ#_6 R133 1 2 475_0402_1%
    MCH_CLKSEL0 9 9 CLK_MCH_BCLK CLKREQ#_6 31
    2.2K_0402_5% R129 R134 1 2 0_0402_5% R_CPU_BCLK# R_CLK_PCIE_MCARD2 R135 1 2 0_0402_5%
    6 CLK_CPU_BCLK# CLK_PCIE_MCARD2 31
    R138 1K_0402_5% CPU R136 1 2 0_0402_5% R_CPU_BCLK R_CLK_PCIE_MCARD2# R137 1 2 0_0402_5% MiniCard_WLAN
    6 CLK_CPU_BCLK CLK_PCIE_MCARD2# 31
    7 CPU_BSEL0 1 2 +3VS_CK505
    0_0402_5%
    1

    72
    71
    70
    69
    68
    67
    66
    65
    64
    63
    62
    61
    60
    59
    58
    57
    56
    55
    R139 U3
    1K_0402_5% +3VS_CK505 +1.05VS_CK505

    VDD_CPU
    CPU_0
    CPU_0#
    VSS_CPU
    CPU_1
    CPU_1#
    VDD_CPU_IO
    CLKREQ_7#
    SRC_8/CPU_ITP
    SRC_8#/CPU_ITP#
    VDD_SRC_IO
    SRC_7
    SRC_7#
    VSS_SRC
    CLKREQ_6#
    SRC_6
    SRC_6#
    VDD_SRC
    C C
    2

    @ R141 1 2 0_0402_5%
    27,49 VGATE @ R142 1 2 0_0402_5%
    +VCCP 49 CLK_ENABLE# R140 1 2 0_0402_5% R_CKPWRGD 1 54 H_STP_PCI#
    27 CK_PWRGD CKPWRGD/PD# PCI_STOP# H_STP_PCI# 27
    FSB 2 53 H_STP_CPU#
    FS_B/TEST_MODE CPU_STOP# H_STP_CPU# 27
    3 52
    2

    @ CLK_XTAL_OUT VSS_REF VDD_SRC_IO R_CLK_PCIE_MCARD0# R144 0_0402_5%


    No Debug port anymore 4
    XTAL_OUT SRC_10#
    51 1 2 CLK_PCIE_MCARD0# 31
    R143 CLK_XTAL_IN 5 50 R_CLK_PCIE_MCARD0 R145 1 2 0_0402_5% MiniCard_WWAN
    XTAL_IN SRC_10 CLK_PCIE_MCARD0 31
    1K_0402_5% 6 49 R_CLKREQ#_10 R146 1 2 475_0402_1%
    VDD_REF CLKREQ_10# CLKREQ#_10 31
    R147 1 2 33_0402_1% FSC 7 48 R_CLK_SRC11 R725 1 2 0_0402_5%
    27 CLK_14M_ICH REF_0/FS_C/TEST_ SRC_11 CLK_SRC11 32
    REF1 8 47 R_CLK_SRC11# R726 1 2 0_0402_5% Card reader
    CLK_SRC11# 32
    1

    FSB T44 CLK_SMBDATA REF_1 SRC_11#


    1 2 MCH_CLKSEL1 15,16 9 CLK_SMBDATA 9 46
    R150 CLK_SMBCLK SDA CLKREQ_11# R_CLK_PCIE_LAN# R152
    15,16 CLK_SMBCLK 10 45 1 2 0_0402_5% CLK_PCIE_LAN# 30
    R154 1K_0402_5% DEBUG@ SCL SRC_9# R_CLK_PCIE_LAN R153
    11 44 1 2 0_0402_5% CLK_PCIE_LAN 30 GLAN
    DEBUG@ NC SRC_9 R_CLKREQ#_9 R738
    7 CPU_BSEL1 1 2 12 43 1 2 475_0402_1% CLKREQ#_9 30
    0_0402_5% R169 VDD_PCI CLKREQ_9#
    1 2 33_0402_1% PCI2_1 13 42
    1

    Mini card debug port31 CLK_DEBUG_PORT_1 R155 1 2 33_0402_1% PCI2_2 14


    PCI_1 VSS_SRC
    41 R_CLKREQ#_4 R156 1 2 475_0402_1%
    24pin debug port 37 CLK_DEBUG_PORT_0 PCI_2 CLKREQ_4# CLKREQ#_4 31
    @ R158 1 2 33_0402_1% 27_SEL 15 40 R_CLK_PCIE_NCARD# R159 1 2 0_0402_5%
    38 CLK_PCI_EC PCI_3 SRC_4# CLK_PCIE_NCARD# 31
    R157 PCI_CLK3 R_CLK_PCIE_NCARD R160 2 0_0402_5%
    16 39 1 31 New Card

    USB_1/CLKREQ_A#
    PCI_4/SEL_LCDCL SRC_4 CLK_PCIE_NCARD
    0_0402_5% R161 1 2 33_0402_1% ITP_EN 17 38

    LCDCLK#/27M_SS
    SRC_0#/DOT_96#
    25 CLK_PCI_ICH PCIF_5/ITP_EN VDD_SRC_IO R_CLKREQ#_C R162
    18 37 1 2 475_0402_1%

    SRC_0/DOT_96
    CLKREQ#_C 27
    2

    VSS_PCI CLKREQ_3#

    VDD_PLL3_IO
    LCDCLK/27M
    USB_0/FS_A

    VDD_PLL3

    VSS_PLL3

    VSS_SRC
    VDD_48

    SRC_2#

    SRC_3#
    +VCCP

    VDD_IO
    VSS_48

    VSS_IO

    SRC_2

    SRC_3
    1

    @
    R163 SLG8SP553VTR_QFN72_10x10

    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    1K_0402_5% +3VS_CK505

    B R164 R_PCIE_SATA# R166 0_0402_5% B


    1 2 CLK_PCIE_SATA# 26
    2

    FSC R167 2 33_0402_1% FSA R_PCIE_SATA R168 0_0402_5%


    1 2 1 2 MCH_CLKSEL2 9 27 CLK_48M_ICH
    1 1 2 CLK_PCIE_SATA 26 SATA
    10K_0402_5% R165
    R171 1K_0402_5% R_PCIE_ICH# R170 1 2 0_0402_5%
    CLK_PCIE_ICH# 27
    1 2 +1.05VS_CK505 R_PCIE_ICH R172 1 2 0_0402_5% ICH
    7 CPU_BSEL2 CLK_PCIE_ICH 27
    0_0402_5% +1.05VS_CK505
    1

    R173 1 2 0_0402_5% R_CLK_PCIE_VGA


    20 CLK_PCIE_VGA
    @ VGA R175 1 2 0_0402_5% R_CLK_PCIE_VGA# SSCDREFCLK# R176 1 2 0_0402_5%
    20 CLK_PCIE_VGA# 27M_SSC 21
    R174 SSCDREFCLK R177 1 2 0_0402_5% VGA
    27M_CLK 21
    0_0402_5%
    2

    +3VS
    +3VS

    0 = SRC8/SRC8#
    ITP_EN +3VS
    1 = ITP/ITP# V R178 R179
    0 = Enable DOT96 & SRC1(UMA) 2.2K_0402_5% 2.2K_0402_5%
    PCI_CLK3 @ C215 2 1 CLK_48M_ICH
    1 = Enable SRC0 & 27MHz(DIS) V
    2

    5P_0402_50V8C
    G

    @ C216 2 1 CLK_14M_ICH
    21,27,31,37 ICH_SMBDATA 1 3 CLK_SMBDATA 4.7P_0402_50V8C
    +3VS +3VS @ C217 2 1 CLK_PCI_ICH
    D

    S
    2

    4.7P_0402_50V8C
    G

    SB, MINI PCI


    2N7002_SOT23-3 @ C218 2 1 CLK_PCI_EC
    1

    21,27,31,37 ICH_SMBCLK 1 3 Q3 CLK_SMBCLK 4.7P_0402_50V8C


    R180 R181
    D

    10K_0402_5% 10K_0402_5%
    A 2N7002_SOT23-3 A
    Q4
    2

    om
    ITP_EN PCI_CLK3

    l.c
    1

    @ @

    ai
    R182 R183
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    10K_0402_5% 10K_0402_5%
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    Clock Generator CK505
    2

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 17 of 51

    x
    he
    5 4 3 2 1
    A B C D E

    +5VS +RCRT_VCC +CRTVDD

    CRT D4 F1 BLUE
    GREEN
    2 1 1 2 W=40mils
    Connector RB491D_SC59-3 1.1A_6VDC_FUSE
    1 RED
    Place close to
    0.1U_0402_16V4Z JCRT

    1
    C220 2 @ D5 @ D6 @ D7
    JCRT1

    DAN217T146_SC59-3

    DAN217T146_SC59-3

    DAN217T146_SC59-3
    6
    11
    1 RED 1 1
    40 RED +5VS
    7

    3
    12
    GREEN 2
    40 GREEN
    8
    40 D_HSYNC 13
    BLUE 3 CONN@
    40 BLUE
    9 SUYIN_070546FR015S263ZR
    40 D_VSYNC 14 16
    4 17
    +5VS +5VS 10
    15
    C221 C222 5
    0.1U_0402_16V4Z 0.1U_0402_16V4Z
    1 2 1 2
    +3VS
    +CRTVDD +CRTVDD +3VS

    5
    1
    U4
    SN74AHCT1G125GW_SOT353-5 R184

    P
    OE#

    1
    1
    CRT_HSYNC 2 4 HSYNC_G_A 1 2 0_0603_5% D_HSYNC
    20 CRT_HSYNC A Y R185 R186 R187 R188

    5
    1
    2.2K_0402_5% 2.2K_0402_5%

    2
    R189 2.2K_0402_5% 2.2K_0402_5%

    G
    P
    OE#
    3
    CRT_VSYNC 2 4 VSYNC_G_A 1 2 0_0603_5% D_VSYNC
    20 CRT_VSYNC

    2
    2
    A Y D_DDCDATA 3VDDCDA
    1 3 3VDDCDA 21

    G
    U5 1 @ 1 @

    S
    SN74AHCT1G125GW_SOT353-5 C223 C224

    3
    1

    2
    2N7002_SOT23-3

    G
    R190 R191 5P_0402_50V8C 5P_0402_50V8C Q5
    51K_0402_5% 51K_0402_5% 2 2 D_DDCCLK 1 3 3VDDCCL
    3VDDCCL 21

    S
    2 2
    2

    2N7002_SOT23-3
    Q6

    D_DDCDATA 40
    D_DDCCLK 40

    CRT Termination/EMI Filter Note: CRT / TV-out should route to JP30


    first then to the JP1 & JP2 on system side.

    3 3
    C_RED L2 1 2 RED
    20 M_RED
    HLC0603CSCCR11JT_0603

    C_GRN L3 1 2 GREEN
    20 M_GREEN
    HLC0603CSCCR11JT_0603

    C_BLU L4 1 2 BLUE
    20 M_BLUE
    HLC0603CSCCR11JT_0603
    1

    1
    150_0402_1%

    150_0402_1%

    150_0402_1%

    150_0402_1%

    150_0402_1%

    150_0402_1%

    1 1 1
    C228 C229 C230

    10P_0402_50V8J 10P_0402_50V8J
    2

    2 2 2

    R195 R196 R197


    R239 R238 R237
    10P_0402_50V8J

    4 4

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    CRT Connector
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 18 of 51
    A B C D E
    5 4 3 2 1

    +LCDVDD +3VS
    +LCDVDD +LCDVDD +5VALW Q7
    SI2301BDS-T1-E3_SOT23-3

    2
    1 3

    S
    D
    R198 R199 1

    4.7U_0805_10V4Z
    1 1 100_0402_5% 47K_0402_5%
    C231 C232 C233 1

    G
    2
    4.7U_0805_10V4Z

    1
    +3VS +LCDVDD INVPWR_B+ 0.1U_0402_16V4Z 0.1U_0402_16V4Z 2 C234
    2 2
    2

    1
    D D R200 D
    Q8 2 2 1
    C235 C236 C237 2N7002_SOT23-3 G
    S 100K_0402_5%

    3
    680P_0402_50V7K C238

    680P_0402_50V7K

    680P_0402_50V7K
    1
    LVDS CONN WITH Camera and Digi MIC
    1

    1
    0.047U_0402_16V7K

    Limited Current < 1A


    2

    1
    2 D
    JLVDS 2 Q9
    21 ENAVDD
    1 2 LVDS_A2- G 2N7002_SOT23-3
    1 2 LVDS_A2- 20

    0.22U_0603_10V7K
    3 4 LVDS_A2+ C239 1 S
    LVDS_A2+ 20

    3
    3 4 LVDS_A1- R201
    5 6 LVDS_A1- 20
    5 6 LVDS_A1+ 100K_0402_5%
    7 8 LVDS_A1+ 20
    7 8 LVDS_A0-
    9 10 LVDS_A0- 20
    9 10 LVDS_A0+ 2
    11 12 LVDS_A0+ 20

    2
    USB20_P4 11 12 LVDS_ACLK-
    27 USB20_P4 13 14 LVDS_ACLK- 20
    USB20_N4 13 14 LVDS_ACLK+
    27 USB20_N4 15 16 LVDS_ACLK+ 20
    15 16
    17 18
    +3VS 17 18
    19 20
    19 20
    21 22 Avoid Panel display garbage after power
    LVDS_BCLK+ 21 22 DMIC_DAT
    20 LVDS_BCLK+ 23 24 DMIC_DAT 33
    LVDS_BCLK- 23 24 DMIC_CLK on.
    20 LVDS_BCLK- 25 26 DMIC_CLK 33
    25 26 +3V_LOGO R727
    27 28 1 2 +5VS
    LVDS_B0+ 27 28 INV_PWM 470_0402_5% +3VS
    20 LVDS_B0+ 29 30 INV_PWM 38
    LVDS_B0- 29 30 BKOFF#
    20 LVDS_B0- 31 32 BKOFF# 38
    LVDS_B1+ 31 32 DAC_BRIG B+ INVPWR_B+
    20 LVDS_B1+ 33 34 DAC_BRIG 38
    LVDS_B1- 33 34 @
    20 LVDS_B1- 35 36 USB_CAM
    LVDS_B2+ 35 36 DDC2_CLK L5 0_0805_5%
    20 LVDS_B2+ 37 38 DDC2_CLK 21 1 2
    37 38

    2
    LVDS_B2- 39 40 DDC2_DATA
    20 LVDS_B2- 39 40 DDC2_DATA 21
    41 42 R202 R203
    C GND GND 2.2K_0402_5% 2.2K_0402_5% L6 C
    1 2
    ACES_88242-4001 FBMA-L11-201209-221LMA30T_0805

    1
    DDC2_CLK 0308_Reserve L10 and install
    1 1 DDC2_DATA
    L11.
    C435 C434
    680P_0402_50V7K 680P_0402_50V7K
    2 2

    0308_Install all cap for EMI


    request.

    B B

    +5VALW USB_CAM

    3.9K_0402_1%
    1

    PJP604 U42
    PAD-OPEN 2x2m 1
    SHDN# R1091
    4
    OUTPUT
    2
    GND
    2

    3 5
    VIN SET C1391
    1

    G913E-SOT23-5
    2

    C1392 10U_1206_6.3V6M
    10U_1206_6.3V6M R1093
    2

    1K_0402_1%
    2

    USB_VCCA is +3.6VS, R892:1K; R891:3.9Kohm


    USB_VCCA is +4VS, R892:1K; R891:4.22Kohm

    A A

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    LCD CONN.

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 19 of 51

    x
    he
    5 4 3 2 1
    A B C D E

    LVDS & DAC Interface


    U17F
    PEG Interface
    NB9M-GS_BGA_533P
    COMMON

    6/13 IFPAB
    IFPA_TXD0 V4 LVDS_A0- 19
    IFPA_TXD0 V5 +PCIE
    LVDS_A0+ 19 U17A
    600 mA
    NB9M-GS_BGA_533P 0.1U_0402_16V4Z 10U_0805_6.3V6M
    +1.8VS COMMON
    100mA IFPA_TXD1 AA4 LVDS_A1- 19
    IFPA_TXD1 AA5 LVDS_A1+ 19 1/13 PCI_EXPRESS 1 1 2 1 1
    2 1 4.7U_0603_6.3V6K 4700P_0402_25V7K IFPAB_PLLVDD AD5 IFPAB_PLLVDD PEX_IOVDD AC9
    1 1
    L7 IFPAB_RSET AB6 IFPAB_RSET A PEX_IOVDD AD7
    BLM18PG181SN1D_0603 IFPA_TXD2 Y4 LVDS_A2- 19 PEX_IOVDD AD8 C244 C252 C253 C254 C255
    W4 AE7 2 2 1 2 2
    1 IFPA_TXD2 LVDS_A2+ 19 PEX_IOVDD

    1
    1 1 2 PEX_IOVDD AF7
    PEX_IOVDD AG7 0.1U_0402_16V4Z 1U_0603_10V4Z 4.7U_0603_6.3V6K
    4.7U_0603_6.3V6K R205 IFPA_TXD3 AB5
    2 C257 C246 C247 C248 1K_0402_1% IFPA_TXD3 AB4
    2 2 1 @ AB13 470P_0402_50V7K
    PEX_IOVDDQ +PCIE

    2
    DATA PEX_IOVDDQ AB16
    IFPB_TXD4 V1 LVDS_B0- 19 PEX_IOVDDQ AB17 1 1 2 1.920 Amps
    470P_0402_50V7K IFPB_TXD4 W1 LVDS_B0+ 19 PEX_IOVDDQ AB7
    AE9 RFU PEX_IOVDDQ AB8 C258 C249 C259
    PEX_IOVDDQ AB9
    W2 AC13 2 2 1
    IFPB_TXD5 LVDS_B1- 19 PEX_IOVDDQ
    IFPB_TXD5 W3 LVDS_B1+ 19 R204 PEX_IOVDDQ AC7
    +1.8VS 0_0402_5% PEX_IOVDDQ AD6 0.1U_0402_16V4Z 1U_0603_10V4Z
    100 mA B 9,25,30,31,32 PLT_RST# 1 2 PEX_RST# AD9 PEX_RST PEX_IOVDDQ AE6
    2 1 4700P_0402_25V7K 470P_0402_50V7K IFPA_IOVDD V3 IFPA_IOVDD IFPB_TXD6 AA3 PEX_IOVDDQ AF6 4.7U_0603_6.3V6K
    LVDS_B2- 19
    L8 IFPB_TXD6 AA2 LVDS_B2+ 19 PEX_IOVDDQ AG6
    BLM18PG181SN1D_0603 1 1 2 IFPB_IOVDD V2 IFPB_IOVDD 2 1 1
    PEX_REFCLKP AB10 PEX_REFCLK
    17 CLK_PCIE_VGA PEX_REFCLKN
    C251 IFPB_TXD7 AA1 AC10 PEX_REFCLK C262 C263 C264
    17 CLK_PCIE_VGA#
    IFPB_TXD7 AB1
    2 2 C266 1 C267 C265 1 2 0.1U_0402_16V4Z PEX_TXP0 AD10 1 2 2 10U_0805_6.3V6M
    11 PEG_RXP0 PEX_TX0
    4.7U_0603_6.3V6K
    11 PEG_RXN0
    C268 1 2 0.1U_0402_16V4Z PEX_TXN0 AD11 PEX_TX0
    IFPA_TXC AD4 LVDS_ACLK- 19 1U_0603_10V4Z
    IFPA_TXC AC4 LVDS_ACLK+ 19 AE12 PEX_RX0
    A 11 PEG_M_TXP0
    AF12
    11 PEG_M_TXN0 PEX_RX0
    CLOCK
    4700P_0402_25V7K 470P_0402_50V7K IFPB_TXC AB2 C270 1 2 0.1U_0402_16V4Z PEX_TXP1 AD12 PEX_TX1 VDD J10 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z +NVVDD
    LVDS_BCLK- 19 11 PEG_RXP1
    B IFPB_TXC AB3
    LVDS_BCLK+ 19 11 PEG_RXN1
    C271 1 2 0.1U_0402_16V4Z PEX_TXN1 AC12 PEX_TX1 VDD J12
    1 2 VDD J13 1 1 1 1 1 1
    11 PEG_M_TXP1 AG12 PEX_RX1 VDD J9
    11 PEG_M_TXN1 AG13 PEX_RX1 VDD L9 C273 C274 C275 C276 C277 C278
    VDD M11
    2 C279 1 C280 C281 1 2 0.1U_0402_16V4Z PEX_TXP2 AB11 M17 2 2 2 2 2 2
    11 PEG_RXP2 PEX_TX2 VDD
    C282 1 2 0.1U_0402_16V4Z PEX_TXN2 AB12 PEX_TX2 VDD M9
    11 PEG_RXN2
    VDD N11 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    11 PEG_M_TXP2 AF13 PEX_RX2 VDD N12
    2 AE13 PEX_RX2 VDD N13 2
    11 PEG_M_TXN2
    VDD N14
    11 PEG_RXP3 C283 1 2 0.1U_0402_16V4Z PEX_TXP3 AD13 PEX_TX3 VDD N15 0.1U_0402_16V4Z 4.7U_0603_6.3V6K 4.7U_0603_6.3V6K 4.7u X 3
    11 PEG_RXN3
    C284 1 2 0.1U_0402_16V4Z PEX_TXN3 AD14 PEX_TX3 VDD N16
    VDD N17 1 1 1 1 1 0.47u X 7
    11 PEG_M_TXP3 AE15 PEX_RX3 VDD N19
    11 PEG_M_TXN3 AF15 PEX_RX3 VDD N9 C285 C286 C287 C288 C289 0.1u X 7
    VDD P11
    C291 1 2 0.1U_0402_16V4Z PEX_TXP4 AD15 P12 2 2 2 2 2
    11 PEG_RXP4 PEX_TX4 VDD
    C292 1 2 0.1U_0402_16V4Z PEX_TXN4 AC15 PEX_TX4 VDD P13
    11 PEG_RXN4
    VDD P14 470P_0402_50V7K 4.7U_0603_6.3V6K
    11 PEG_M_TXP4 AG15 PEX_RX4 VDD P15
    11 PEG_M_TXN4 AG16 PEX_RX4 VDD P16
    VDD P17
    C293 1 2 0.1U_0402_16V4Z PEX_TXP5 AB14 PEX_TX5 VDD R11 470P_0402_50V7K 470P_0402_50V7K 470P_0402_50V7K
    11 PEG_RXP5
    C294 1 2 0.1U_0402_16V4Z PEX_TXN5 AB15 PEX_TX5 VDD R12
    11 PEG_RXN5
    VDD R13 1 1 1 1 1 1
    U17D 11 PEG_M_TXP5 AF16 PEX_RX5 VDD R14
    11 PEG_M_TXN5 AE16 PEX_RX5 VDD R15 C295 C296 C297 C298 C299 C300
    NB9M-GS_BGA_533P VDD R16
    COMMON
    C301 1 2 0.1U_0402_16V4Z PEX_TXP6 AC16 R17 2 2 2 2 2 2
    R206 11 PEG_RXP6 PEX_TX6 VDD
    5/13 DACC
    11 PEG_RXN6
    C302 1 2 0.1U_0402_16V4Z PEX_TXN6 AD16 PEX_TX6 VDD R9
    1 2 W5 DACC_VDD VDD T11 470P_0402_50V7K 470P_0402_50V7K 470P_0402_50V7K
    11 PEG_M_TXP6 AE18 PEX_RX6 VDD T17
    R6 DACC_VREF 11 PEG_M_TXN6 AF18 PEX_RX6 VDD T9
    10K_0402_5% U19
    VDD
    V6 U6 C303 1 2 0.1U_0402_16V4Z PEX_TXP7 AD17 U9
    DACC_RSET
    DAC C DACC_HSYNC
    DACC_VSYNC U4
    11
    11
    PEG_RXP7
    PEG_RXN7
    C304 1 2 0.1U_0402_16V4Z PEX_TXN7 AD18
    PEX_TX7
    PEX_TX7
    VDD
    VDD
    VDD
    W10
    W12
    11 PEG_M_TXP7 AG18 PEX_RX7 VDD W13
    DACC_RED T5 11 PEG_M_TXN7 AG19 PEX_RX7 VDD W18
    VDD W19
    DACC_GREEN T4 C305 1 2 0.1U_0402_16V4Z PEX_TXP8 AC18 PEX_TX8 VDD W9 +NVVDD_SENSE
    11 PEG_RXP8
    11 PEG_RXN8
    C306 1 2 0.1U_0402_16V4Z PEX_TXN8 AB18 PEX_TX8
    DACC_BLUE R4 R392 0_0402_5%
    11 PEG_M_TXP8 AF19 PEX_RX8 VDD_SENSE W15 1 2
    11 PEG_M_TXN8 AE19 PEX_RX8 GND_SENSE W16

    11 PEG_RXP9 C307 1 2 0.1U_0402_16V4Z PEX_TX9 AB19 PEX_TX9


    3
    C308 1 2 0.1U_0402_16V4Z PEX_TX9* AB20 PEX_TX9 3
    11 PEG_RXN9 +3VS
    11 PEG_M_TXP9 AE21 PEX_RX9 110 mA
    AF21 PEX_RX9 VDD33 A12 VDD33
    11 PEG_M_TXN9
    VDD33 B12

    1U_0603_10V4Z
    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    C309 1 2 0.1U_0402_16V4Z PEX_TX10 AD19 C12
    U17C 11 PEG_RXP10 PEX_TX10 VDD33 1 1 1

    BLM18PG181SN1D_0603
    150 mA
    NB9M-GS_BGA_533P
    COMMON

    3/13 DACA
    CRT 11
    11 PEG_RXN10

    PEG_M_TXP10
    C310 1 2 0.1U_0402_16V4Z PEX_TX10* AD20

    AG21
    AG22
    PEX_TX10

    PEX_RX10
    PEX_RX10
    VDD33
    VDD33
    VDD33
    D12
    E12
    F12
    2
    C1476
    2
    C314
    2
    C311

    11 PEG_M_TXN10
    2 1 470P_0402_50V7K DACA_VDD AG2 DACA_VDD
    +3VS
    L9 11 PEG_RXP11 C315 1 2 0.1U_0402_16V4Z PEX_TX11 AD21 PEX_TX11
    DACA_VREF AF1 DACA_VREF C316 1 2 0.1U_0402_16V4Z PEX_TX11* AC21 PEX_TX11
    11 PEG_RXN11
    AE1 DACA_RSET DACA_HSYNC AD2 CRT_HSYNC 18 11 PEG_M_TXP11 AF22 PEX_RX11
    1

    AD1 AE22

    C317
    1 1 1 1
    R207
    DAC A DACA_VSYNC CRT_VSYNC 18 11

    11
    PEG_M_TXN11

    PEG_RXP12 C322 1 2 0.1U_0402_16V4Z PEX_TX12 AB21


    PEX_RX11

    PEX_TX12 120mA
    1U_0402_6.3V4Z C319 C320 C321 DACA_RED AE2 C323 1 2 0.1U_0402_16V4Z PEX_TX12* AB22 PEX_TX12 4.7U_0603_6.3V6M
    2 2 2 2 M_RED 18 11 PEG_RXN12 PEX_PLLDVDD
    PEX_PLLVDD AF9 2 1 +PCIE
    2

    DACA_GREEN AE3 11 PEG_M_TXP12 AE24 PEX_RX12 L10


    M_GREEN 18
    11 PEG_M_TXN12 AF24 PEX_RX12 1 1 1 1 BLM18PG181SN1D_0603
    4700P_0402_25V7K 0.1U_0402_16V4Z 124_0402_1% DACA_BLUE AD3 M_BLUE 18
    C324 1 2 0.1U_0402_16V4Z PEX_TX13 AC22 PEX_TX13 C327 C325 C446 C447
    11 PEG_RXP13
    C326 1 2 0.1U_0402_16V4Z PEX_TX13* AD22 PEX_TX13
    11 PEG_RXN13 2 2 2 2
    11 PEG_M_TXP13 AG24 PEX_RX13
    11 PEG_M_TXN13 AF25 PEX_RX13
    0.1U_0402_16V4Z 0.01U_0402_25V7K 1U_0402_6.3V4Z
    11 PEG_RXP14 C328 1 2 0.1U_0402_16V4Z PEX_TX14 AD23 PEX_TX14
    C329 1 2 0.1U_0402_16V4Z PEX_TX14* AD24 PEX_TX14
    11 PEG_RXN14
    R208 200_0402_1%

    BLM18PG181SN1D_0603
    U17E

    NB9M-GS_BGA_533P
    COMMON
    TV-OUT 11
    11
    PEG_M_TXP14
    PEG_M_TXN14
    C330 1 2 0.1U_0402_16V4Z PEX_TXP15 AE25
    AG25
    AG26
    PEX_RX14
    PEX_RX14

    PEX_TX15
    PEX_TSTCLK_OUT
    PEX_TSTCLK_OUT
    AF10
    AE10
    1 2

    11 PEG_RXP15
    4/13 DACB C331 1 2 0.1U_0402_16V4Z PEX_TXN15AE26 PEX_TX15 RFU AG9
    DACB_VDD 11 PEG_RXN15
    +3VS 2 1 1U_0402_6.3V4Z 470P_0402_50V7K D7 DACB_VDD
    L11 11 PEG_M_TXP15 AF27 PEX_RX15 PEX_TERMP AG10 1 2
    DACB_VREF G6 DACB_VREF AE27 PEX_RX15
    11 PEG_M_TXN15
    4 R209 4
    DACB_RSET F8 2.49K_0402_1%
    DACB_RSET
    1 1 1 1
    1

    DACB_CSYNC D6
    C333 C334 C335
    2 2 2
    C336
    2
    R210 DAC B DACB_RED F7 TV_CRMA
    TV_CRMA 40
    DACB_GREEN E7 TV_LUMA
    2

    TV_LUMA 40
    4700P_0402_25V7K 0.1U_0402_16V4Z 124_0402_1% DACB_BLUE E6 TV_COMPS
    TV_COMPS 40

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title

    T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL
    PEG & LVDS & DAC
    AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIVISION OF R&D
    Size Docum ent Num ber Rev
    DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS
    Cus tom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 20 of 51
    A B C D E
    5 4 3 2 1

    U17H

    +3VS 9/21 change C341 form 220p to 470p for nvidia NB9M-GS_BGA_533P
    COMMON

    7/13 IFPC

    1
    +1.8VS BLM18PG181SN1D_0603
    U17L
    160 mA MXM DVI DP

    R211 2 1 470P_0402_50V7K IFPC_PLLVDD P6 IFPC_PLLVDD


    NB9M-GS_BGA_533P 10K_0402_5% L12 IFPC_RSET R5 IFPC_RSET
    COMMON

    1
    11/13 MISC 1 1 1 1
    4.7U_0603_6.3V6K C338 IFPC_AUX G5
    ROM_CS B10 ROM_CS# C337 R212 IFPC_AUX G4
    STRAP0 C7 STRAP0 1K_0402_1%
    STRAP1 B9 A10 ROM_SI 2 2 2 C340 2 C341
    STRAP1 ROM_SI

    2
    STRAP2 A9 STRAP2 ROM_SO C10 ROM_SO TXD0 TXD0 IFPC_L3 J4 HDMI_C_CLK- C1474 1 2 0.1U_0402_16V4Z
    ROM_SCLK HDMI_C_CLK+ C1475 HDMI_CLK- 42
    ROM_SCLK C9 IFPC_L3 H4 1 2 0.1U_0402_16V4Z
    10K_0402_5%@ R213 4.7U_0603_6.3V6K 4700P_0402_25V7K C TXD0 TXD0 HDMI_CLK+ 42
    R214 1 2 IFPC_L2 K4 HDMI_C_TX0- C1468 1 2 0.1U_0402_16V4Z
    D +3VS TXD1 TXD2 HDMI_TX0- 42 D
    40.2K_0402_1% HDCP_SCL HDMI_C_TX0+ C1469 2 0.1U_0402_16V4Z
    1 2 F11 STRAP_REF_3V3
    I2CH_SCL
    I2CH_SDA
    A3
    A4 HDCP_SDA +PCIE BLM18PG181SN1D_0603
    385 mA TXD1 TXD2 IFPC_L2 L4 1 HDMI_TX0+ 42
    2 1 IFPC_L1 M4 HDMI_C_TX1- C1470 1 2 0.1U_0402_16V4Z
    +3VS TXD2 TXD1 HDMI_TX1- 42
    1 2 F10 STRAP_REF_MIOB 10K_0402_5% R215 2 1 4700P_0402_25V7K IFPC_IOVDD J6 IFPC_IOVDD TXD2 TXD1 IFPC_L1 M5 HDMI_C_TX1+ C1471 1 2 0.1U_0402_16V4Z HDMI_TX1+ 42
    L13
    40.2K_0402_1% 1 1 1 1 IFPC_L0 N4 HDMI_C_TX2- C1472 1 2 0.1U_0402_16V4Z
    TXC TXC HDMI_TX2- 42
    R216 BUFRST N5 TXC TXC IFPC_L0 P4 HDMI_C_TX2+ C1473 1 2 0.1U_0402_16V4Z HDMI_TX2+ 42
    C342 C343
    F9 SPDIF RFU J5 4.7U_0603_6.3V6K
    +3VS 2 2 2 C346 2 C347
    RFU F6
    4.7U_0603_6.3V6K 470P_0402_50V7K
    1

    SPDIF 10K_0402_5% TESTMODE AD25


    R217 @ C15 RFU U17G
    C349 D15 RFU

    1
    RFU_GND AC6 NB9M-GS_BGA_533P
    2

    COMMON
    1 2 SPDIF_IN 10K_0402_5%
    33,40 SPDIF_OUT
    R218 8/13 IFPE
    1

    MXM DVI DP
    10K_0402_5%
    VGA Thermal Sensor

    2
    0.01U_0402_25V7K R220 N6 IFPE_PLLVDD
    @ M6 IFPE_RSET

    1
    ADM1032ARMZ
    2

    R234 IFPE_AUX D4
    +3VS 10K_0402_5%
    Closed to VGA IFPE_AUX D3

    2
    2 TXD0 TXD0 IFPE_L3 B4
    @ C348 IFPE_L3 B3
    E TXD0 TXD0

    2
    +3VS +3VS @
    0.1U_0402_16V4Z R219 TXD1 TXD2 IFPE_L2 C4
    1 C3
    HDCP 2 1
    U6
    10K_0402_5% TXD1 TXD2 IFPE_L2

    0.1U_0402_16V4Z VGA_SM_CLK
    ROM 1 8 IFPE_L1 D5

    1
    VDD SCLK TXD2 TXD1
    C351 10K_0402_5% H6 IFPE_IOVDD IFPE_L1 E4
    1 TXD2 TXD1
    R221 @ VGA_THERMDA 2 7 VGA_SM_DA
    D+ SDATA

    1
    @ C350 TXC TXC IFPE_L0 F4
    C U7 1 2 VGA_THERMDC 3 6 THERM_SCI# IFPE_L0 F5 C
    2

    D- ALERT# THERM_SCI# 27,38 TXC TXC


    1 8 HDCP_WP HDCP_SCL R236
    2 A0 VCC 7 HDCP_WP 2200P_0402_50V7K THERM#_VGA 4 5 10K_0402_5%
    A1 WP THERM# GND
    1

    1
    3 6 HDCP_SCL

    2
    A2 SCL HDCP_SDA
    4 5 10K_0402_5% 10K_0402_5% R222
    GND SDA R223 R224 @ ADM1032ARMZ REEL_MSOP8 R1129 0_0402_5%
    +3VS 1 2
    AT88SC0808 VGA_SM_CLK 2 1 SMB_EC_CK2 6,38
    <BOM Structure> @ 10K_0402_5% VGA_SM_DA 2 1
    2

    SMB_EC_DA2 6,38
    R1130 0_0402_5%
    +3VS
    9/21 follow 17"
    U17K
    I2CE_SCL 2K_0402_5% 1 2 R227
    NB9M-GS_BGA_533P I2CE_SDA 2K_0402_5% 1 2 R230
    COMMON
    36 mA
    12/13 XTAL_PLL I2CB_SCL 2K_0402_5% 1 2 R231
    BLM18PG181SN1D_0603 I2CB_SDA 2K_0402_5% 1 2 R232
    +PCIE 2 1 0.1U_0402_16V4Z GPU_PLLVDD K5 PLLVDD GPIO I/O ACTIVE USAGE
    L14
    1U_0402_6.3V4Z

    1 1 1 1 1 K6 VID_PLLVDD
    1U_0402_6.3V4Z

    GPIO0 IN N/A Primary DVI Hot-plug


    C497 C352 C353 C354 C355 L6 SP_PLLVDD
    U17M
    2 2 2 2 2
    GPIO1 IN N/A 2nd DVI Hot-plug
    NB9M-GS_BGA_533P
    COMMON
    1U_0402_6.3V4Z 0.1U_0402_16V4Z
    17 27M_SSC
    D11 XTAL_SSIN XTAL_OUTBUFF E9 GPIO2 OUT H Panel Back-Light PWM 9/13 I2C_GPIO_THERM_JTAG
    1

    R1
    R228 XTALIN D10 XTAL_IN XTAL_OUT E10XTALOUT R229 GPIO3 OUT H Panel Power Enable
    I2CA_SCL
    I2CA_SDA T3
    3VDDCCL 18 CRT
    3VDDCDA 18
    10K_0402_5% 1 1 10K_0402_5%
    VGA_THERMDC D8 THERMDN I2CB_SCL R2 I2CB_SCL
    @ @ C357 @ GPIO4 OUT H Panel Back-Light Enable I2CB_SDA R3 I2CB_SDA
    2

    @ C356 18P_0402_50V8J VGA_THERMDA D9 THERMDP


    2 18P_0402_50V8J 2 A2 DDC2_CLK
    GPIO5 OUT N/A NVVDD VID0
    I2CC_SCL
    I2CC_SDA B1 DDC2_DATA
    DDC2_CLK 19 LVDS
    DDC2_DATA 19
    JTAG_TCK AF3 JTAG_TCK
    T47 JTAG_TMS
    B
    R233 0_0402_5% GPIO6 OUT N/A NVVDD VID1
    T48 JTAG_TDI
    AF4
    AG4
    JTAG_TMS
    JTAG_TDI
    I2CD_SCL
    I2CD_SDA
    N2
    N3
    HDMICLK_VGA 42 HDMI B
    T49 HDMIDAT_VGA 42
    1 2 XTALIN JTAG_TDO AE4 JTAG_TDO
    17 27M_CLK T50 JTAG_TRST I2CE_SCL
    T51 AG3 JTAG_TRST I2CE_SCL Y6
    1

    GPIO7 OUT N/A FBVDD VID0 I2CE_SDA W6 I2CE_SDA


    @ R235
    10K_0402_5%
    GPIO8 IN L Thermal Alert GPIO0 N1
    GPIO1 G1
    2

    HDMI_DETECT 42
    0_0402_5% @ R225 GPIO2 C1
    GPIO9 OUT L FAN PWM 2 1 VGA_SM_CLK T1 I2CS_SCL GPIO3 M2 ENVDD
    17,27,31,37 ICH_SMBCLK ENAVDD 19
    17,27,31,37 ICH_SMBDATA 2 1 VGA_SM_DA T2 I2CS_SDA GPIO4 M3 ENBKL 38
    0_0402_5% R226 GPIO5 K3 GPU_VID 47
    GPIO10 OUT N/A FBVref Select @ GPIO6 K2
    GPIO7 J2
    GPIO8 C2 THERMAL ALERT 1 2 THERM#_VGA
    GPIO11 OUT N/A SLI SYNCO GPIO9 M1 SINN_GPIO9 0_0402_5%
    1 2R396 THERM_SCI#
    GPIO10 D2 0_0402_5% R395
    GPIO11 D1

    Straps GPIO12

    GPIO13
    IN

    OUT
    N/A

    L
    AC Detect

    PS Control or HDMI_CEC
    GPIO12
    GPIO13
    GPIO14
    GPIO15
    J3
    J1
    K1
    F3
    GPIO16 G3
    MULTI LEVEL STRAPS GPIO14 OUT H PS Control
    GPIO17
    GPIO18
    G2
    F1
    9/21 GPU_VID
    F2
    GPIO19
    High: +NVVDDP 1.0V
    DDR2 Resistor Value
    STRAP0 Low: +NVVDDP 0.9V
    STRAP1 Locating R248
    STRAP2 16MX16 Hynix 20 Kohms
    ROM_SI 16MX16 Samsung 10 Kohms
    ROM_SO 32MX16 Hynix 45 Kohms U17I
    ROM_SCLK 32MX16 Samsung 30 Kohms
    +3VS HDMI_CLK- NB9M-GS_BGA_533P
    HD AUDIO
    COMMON
    HDMI_CLK+
    HDMI_TX0-
    10/13 HDAUDIO
    @ 1 R242 2 1 R243 2 HDMI_TX0+
    5.1K_0402_5% 45.3K_0402_1% HDMI_TX1- HDA_BCLK A7
    A HDMI_TX1+ HDA_BITCLK_VGA 26,33 A
    1 R244 2 1 R245 2 @ HDMI_TX2- HDA_SYNC B7
    HDMI_TX2+ HDA_SDIN2_R HDA_SYNC_VGA 26,33
    10K_0402_1% 5.1K_0402_5% HDA_SDI A6 R399 33_0402_5% 1 2 HDA_SDIN2 26
    HDA_SDO B6 HDA_SDOUT_VGA 26
    @ 1 R246 2 1 R247 2 HDA_RST C6 HDA_RST#_VGA 26,33
    5.1K_0402_5% 5.1K_0402_5%
    1

    9/21 R329 near GPU


    1 R248 @ 1 R249 2
    20K_0402_1% 5.1K_0402_5% R960 R961 R962 R963 R964 R965 R966 R967 9/21 R237, R238, R240, R241 near ICH
    499_0402_1%
    @ 1 R250 2 1 R251 2 <BOM Structure>
    2

    5.1K_0402_5% 5.1K_0402_5%
    499_0402_1% 499_0402_1% 499_0402_1% 499_0402_1%
    Security Classification Compal Secret Data Compal Electronics, Inc.
    1 R252 2 @ 1 R253 2 499_0402_1% 499_0402_1% 499_0402_1% Issued Date 2006/02/13 Deciphered Date 2006/03/10 Title
    15K_0402_5% 5.1K_0402_5%
    T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL
    Straps & HDMI
    Size Docum ent Num ber Rev
    AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIVISION OF R&D
    DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS Cus tom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 21 of 51
    5 4 3 2 1

    om
    l.c
    ai
    tm
    ho
    @
    nf
    x ai
    he
    A

    VRAM Interface +VDD_MEM18


    R1124
    1

    1
    0_1206_5%
    2

    2
    +1.8VS

    R1125 0_1206_5%

    MDA[15..0]
    23 MDA[15..0]
    U17B U17J
    MDA[31..16]
    23 MDA[31..16] NB9M-GS_BGA_533P NB9M-GS_BGA_533P
    MDA[47..32] COMMON COMMON
    24 MDA[47..32]
    2/13 FRAME_BUFFER +VDD_MEM18 13/13 GND_NC
    MDA[63..48] MDA0 D21 FBA_D0
    24 MDA[63..48] MDA1 C22 FBA_D1 0.022U_0402_16V7K 0.1U_0402_16V4Z 4.7U_0603_6.3V6K AC11 GND NC AA6
    MDA2 B22 FBA_D2 AC14 GND NC AC19
    MDA3 A22 FBA_D3 1 1 1 1 1 1 AC17 GND NC E15
    MDA4 C24 FBA_D4 FBVDDQ A13 AC2 GND NC T6
    MDA5 B25 FBA_D5 FBVDDQ B13 C358 C366 C359 C360 C367 C368 AC20 GND
    MDA6 A25 FBA_D6 FBVDDQ C13 AC23 GND
    MDA7 A26 D13 2 2 2 2 2 2 AC26
    FBA_D7 FBVDDQ GND
    MDA8 D22 FBA_D8 FBVDDQ D14 AC5 GND
    MDA9 E22 FBA_D9 FBVDDQ E13 0.022U_0402_16V7K 0.022U_0402_16V7K 4.7U_0603_6.3V6K AC8 GND
    MDA10 E24 FBA_D10 FBVDDQ F13 AF11 GND
    MDA11 D24 FBA_D11 FBVDDQ F14 AF14 GND
    MDA12 D26 FBA_D12 FBVDDQ F15 AF17 GND
    MDA13 D27 FBA_D13 FBVDDQ F16 4700P_0402_25V7K 0.022U_0402_16V7K 0.1U_0402_16V4Z AF2 GND
    MDA14 C27 FBA_D14 FBVDDQ F17 AF20 GND
    MDA15 B27 FBA_D15 FBVDDQ F19 1 1 1 1 1 1 AF23 GND
    MDA16 D16 FBA_D16 FBVDDQ F22 AF26 GND
    MDA17 E16 FBA_D17 FBVDDQ H23 C361 C369 C362 C363 C364 C365 AF5 GND
    MDA18 D17 FBA_D18 FBVDDQ H26 AF8 GND
    MDA19 F18 J15 2 2 2 2 2 2 B11
    FBA_D19 FBVDDQ GND
    MDA20 D20 FBA_D20 FBVDDQ J16 B14 GND
    MDA21 F20 FBA_D21 FBVDDQ J18 4700P_0402_25V7K 4700P_0402_25V7K 0.1U_0402_16V4Z
    MDA22 E21 FBA_D22 FBVDDQ J19 B17 GND
    MDA23 F21 FBA_D23 FBVDDQ L19 B2 GND
    MDA24 C16 FBA_D24 FBVDDQ L23 4700P_0402_25V7K 1U_0402_6.3V4Z 0.022U_0402_16V7K B20 GND
    MDA25 B18 FBA_D25 FBVDDQ L26 C373 1 B23 GND
    MDA26 C18 FBA_D26 FBVDDQ M19 1 1 1 1 1 B26 GND
    MDA27 D18 FBA_D27 FBVDDQ N22 C375 B5 GND
    MDA28 C19 FBA_D28 FBVDDQ U22 C370 C371 B8 GND
    MDA29 C21 Y22 2 E11
    FBA_D29 FBVDDQ GND
    MDA30 B21 2 2 2 C372 2
    <BOM Structure> 2 C374 E14
    FBA_D30 GND
    MDA31 A21 FBA_D31 E17 GND
    MDA32 P22 FBA_D32 4700P_0402_25V7K 0.1U_0402_16V4Z 1U_0402_6.3V4Z E2 GND
    MDA33 P24 FBA_D33 E20 GND
    MDA34 R23 FBA_D34 E23 GND
    MDA35 R24 FBA_D35 E26 GND
    MDA36 T23 FBA_D36 E5 GND
    MDA37 U24 FBA_D37 E8 GND
    CMDA[30..0] 23,24
    MDA38 V23 FBA_D38 H2 GND
    MDA39 V24 FBA_D39 FBA_CMD0 F26 CMDA0 H5 GND
    MDA40 N25 FBA_D40 FBA_CMD1 J24 CMDA1 J11 GND
    MDA41 N26 FBA_D41 FBA_CMD2 F25 CMDA2 J14 GND
    MDA42 R25 FBA_D42 FBA_CMD3 M23 CMDA3
    MDA43 R26 FBA_D43 FBA_CMD4 N27 CMDA4 J17 GND
    MDA44 T25 FBA_D44 FBA_CMD5 M27 CMDA5 K19 GND
    MDA45 V26 FBA_D45 FBA_CMD6 K26 CMDA6 K9 GND
    MDA46 V25 FBA_D46 FBA_CMD7 J25 CMDA7 L11 GND
    MDA47 V27 FBA_D47 FBA_CMD8 J27 CMDA8 L12 GND
    MDA48 V22 FBA_D48 FBA_CMD9 G23 CMDA9 L13 GND
    MDA49 W22 FBA_D49 FBA_CMD10 G26 CMDA10 L14 GND
    MDA50 W23 FBA_D50 FBA_CMD11 J23 CMDA11 L15 GND
    MDA51 W24 FBA_D51 FBA_CMD12 M25 CMDA12 L16 GND
    MDA52 AA22 FBA_D52 FBA_CMD13 K27 CMDA13 L17 GND
    MDA53 AB23 FBA_D53 FBA_CMD14 G25 CMDA14 L2 GND
    MDA54 AB24 FBA_D54 FBA_CMD15 L24 CMDA15 L5 GND
    MDA55 AC24 FBA_D55 FBA_CMD16 K23 CMDA16 9/18 add R for nvidia M12 GND
    MDA56 W25 FBA_D56 FBA_CMD17 K24 CMDA17 M13 GND
    MDA57 W26 FBA_D57 FBA_CMD18 G22 CMDA18 M14 GND
    MDA58 W27 FBA_D58 FBA_CMD19 K25 CMDA19 R1131 10K_0402_5% M15 GND
    1 MDA59 AA25 FBA_D59 FBA_CMD20 H22 CMDA20 CMDA12 1 2 M16 GND 1

    MDA60 AB25 FBA_D60 FBA_CMD21 M26 CMDA21 P19 GND


    MDA61 AB26 FBA_D61 FBA_CMD22 H24 CMDA22 P2 GND
    MDA62 AD26 FBA_D62 FBA_CMD23 F27 CMDA23 R394 10K_0402_5% P23 GND
    MDA63 AD27 FBA_D63 FBA_CMD24 J26 CMDA24 CMDA11 1 2
    FBA_CMD25 G24 CMDA25 P26 GND
    23 DQMA[3..0] FBA_CMD26 G27 CMDA26 P5 GND
    DQMA0 D23 FBA_DQM0 FBA_CMD27 M24 CMDA27 P9 GND
    DQMA1 C26 FBA_DQM1 FBA_CMD28 K22 CMDA28 T12 GND
    DQMA2 D19 FBA_DQM2 RFU J22 CMDA29 T13 GND
    DQMA3 B19 FBA_DQM3 RFU L22 CMDA30 T14 GND
    24 DQMA[7..4] DQMA4 T24 FBA_DQM4 T15 GND
    DQMA5 T26 FBA_DQM5 T16 GND
    DQMA6 AA23 FBA_DQM6 U11 GND
    DQMA7 AB27 FBA_DQM7 FBA_CLK0 F24 U12 GND
    CLKA0 23
    FBA_CLK0 F23 CLKA0# 23 U13 GND
    23 QSA[3..0] FBA_CLK1 N24 CLKA1 24 U14 GND
    QSA0 A24 FBA_DQS_WP0 FBA_CLK1 N23 CLKA1# 24 U15 GND
    QSA1 C25 FBA_DQS_WP1 U16 GND
    QSA2 E19 FBA_DQS_WP2 U17 GND
    QSA3 A19 FBA_DQS_WP3 U2 GND
    24 QSA[7..4]
    QSA4 T22 FBA_DQS_WP4 U23 GND
    QSA5 T27 FBA_DQS_WP5 U26 GND
    QSA6 AA24 FBA_DQS_WP6 U5 GND
    QSA7 AA26 FBA_DQS_WP7 V19 GND

    V9 GND
    23 QSA#[3..0] QSA#0 B24 FBA_DQS_RN0 R254 30_0402_1% W11 GND
    QSA#1 D25 FBA_DQS_RN1 FB_CAL_PD_VDDQ B15 1 2 W14 GND
    +VDD_MEM18
    QSA#2 E18 FBA_DQS_RN2 W17 GND
    QSA#3 A18 FBA_DQS_RN3 FB_CAL_PU_GND A15 1 2 R255 30_0402_1% Y2 GND
    24 QSA#[7..4] QSA#4 R22 FBA_DQS_RN4 Y23 GND
    QSA#5 R27 FBA_DQS_RN5 FB_CAL_TERM_GND B16 @1
    @ 2 R256 40.2_0402_1% Y26 GND
    QSA#6 Y24 FBA_DQS_RN6 Y5 GND
    QSA#7 AA27 FBA_DQS_RN7

    R257
    FBA_DEBUG M22 1 2 +VDD_MEM18
    10K_0402_5% @

    +VDD_MEM18
    FB_PLLAVDD R19 0.1U_0402_16V4Z 2 1 +PCIE
    L15
    1

    FB_DLLAVDD T19 1 1 BLM18PG181SN1D_0603

    @ R258 Rt C376 C377


    1K_0402_1% 1U_0402_6.3V4Z
    2 2
    2

    A16 FB_VREF
    1

    1
    BLM18PG181SN1D_0603
    @ R259 Rb C378 2 1 +PCIE
    1K_0402_1% 1 L16
    2 @
    1
    2

    C380
    0.1U_0402_16V4Z C379 1U_0402_6.3V4Z
    2
    2
    0.01U_0402_25V7K

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/03/10 Deciphered Date 2006/03/10 Title

    T HIS SHEET OF ENGINEERING DRAWING IS T HE PROPRIET ARY PROPERT Y OF COM PAL ELECT RONICS, INC. AND CONT AINS CONFIDENT IAL
    VRAM / GND
    AND T RADE SECRET INFORM AT ION. T HIS SHEET M AY NOT BE T RANSFERED FROM T HE CUST ODY OF T HE COM PET ENT DIVISION OF R&D Size Docum ent Num ber Rev
    DEPART M ENT EXCEPT AS AUT HORIZED BY COM PAL ELECT RONICS, INC. NEIT HER T HIS SHEET NOR T HE INFORM AT ION IT CONT AINS
    Cus tom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 22 of 51
    A
    5 4 3 2 1

    DATA Bus
    Address 0..31 32..63
    VRAM DDR2 chips (256MB & 128MB) CMD0 A3
    CMD1 A0 A0
    32Mx16 DDR2 400MHz *4==>256MB
    CMD2 A2
    16Mx16 DDR2 400MHz*4==>128MB CMD3 A1 A1
    CMD4 A3
    QSA[7..0] CMD5 A4
    D 22,24 QSA[7..0] D
    QSA#[7..0] CMD6 A5
    22,24 QSA#[7..0]
    DQMA[7..0] CMD7
    22,24 DQMA[7..0]
    MDA[63..0] CMD8 CS# CS#
    22,24 MDA[63..0]
    CMDA[30..0] CMD9 WE# WE#
    22,24 CMDA[30..0]

    CMD10 BA0 BA0


    CMD11 CKE CKE
    CMD12 ODT ODT
    CMD13
    CMD14 A12 A12
    CMD15 RAS# RAS#
    U8 U9 CMD16 A11 A11
    CMDA10 L2 B9 MDA7 CMDA10 L2 B9 MDA27
    CMDA18 BA0 DQ15 MDA0 CMDA18 BA0 DQ15 MDA28
    L3
    BA1 DQ14
    B1 L3
    BA1 DQ14
    B1 CMD17 A10 A10
    D9 MDA5 D9 MDA24
    CMDA14 DQ13 MDA2 CMDA14 DQ13 MDA31
    R2
    A12 DQ12
    D1 R2
    A12 DQ12
    D1 CMD18 BA1 BA1
    CMDA16 P7 D3 MDA3 CMDA16 P7 D3 MDA30
    CMDA17 A11 DQ11 MDA4 CMDA17 A11 DQ11 MDA25
    M2
    A10/AP DQ10
    D7 M2
    A10/AP DQ10
    D7 CMD19 A8 A8
    CMDA20 P3 C2 MDA1 CMDA20 P3 C2 MDA29
    CMDA19 A9 DQ9 MDA6 CMDA19 A9 DQ9 MDA26
    P8 C8 P8 C8 CMD20 A9 A9
    CMDA23 A8 DQ8 MDA23 CMDA23 A8 DQ8 MDA15
    P2 F9 P2 F9
    CMDA21 A7 DQ7 MDA18 CMDA21 A7 DQ7 MDA9
    C
    N7
    A6 DQ6
    F1 N7
    A6 DQ6
    F1 CMD21 A6 A6 C
    CMDA22 N3 H9 MDA20 CMDA22 N3 H9 MDA12
    CMDA24 A5 DQ5 MDA16 CMDA24 A5 DQ5 MDA8
    N8
    A4 DQ4
    H1 N8
    A4 DQ4
    H1 CMD22 A5
    CMDA0 N2 H3 MDA17 CMDA0 N2 H3 MDA11
    CMDA2 A3 DQ3 MDA21 CMDA2 A3 DQ3 MDA13
    M7
    A2 DQ2
    H7 M7
    A2 DQ2
    H7 CMD23 A7 A7
    CMDA3 M3 G2 MDA19 CMDA3 M3 G2 MDA10
    CMDA1 A1 DQ1 MDA22 CMDA1 A1 DQ1 MDA14
    M8
    A0 DQ0
    G8 M8
    A0 DQ0
    G8 CMD24 A4
    CMD25 CAS# CAS#
    CLKA0# K8 A9 +VDD_MEM18 CLKA0# K8 A9 +VDD_MEM18
    CLKA0 CK VDDQ1 CLKA0 CK VDDQ1
    J8
    CK VDDQ2
    C1 J8
    CK VDDQ2
    C1 CMD26 A13 A13
    C3 C3
    CMDA11 VDDQ3 CMDA11 VDDQ3
    K2
    CKE VDDQ4
    C7 K2
    CKE VDDQ4
    C7 CMD27 BA2 BA2
    C9 C9
    VDDQ5 VDDQ5
    VDDQ6
    E9
    VDDQ6
    E9 CMD28
    G1 G1
    CMDA8 VDDQ7 CMDA8 VDDQ7
    L8
    CS VDDQ8
    G3 L8
    CS VDDQ8
    G3 CMD29
    G7 G7
    CMDA9 VDDQ9 CMDA9 VDDQ9
    K3 G9 K3 G9 CMD30
    WE VDDQ10 WE VDDQ10
    CMDA15 K7 A1 CMDA15 K7 A1
    RAS VDD1 RAS VDD1
    E1 E1
    CMDA25 VDD2 CMDA25 VDD2
    L7 J9 L7 J9
    CAS VDD3 CAS VDD3
    M9 M9
    DQMA2 VDD4 DQMA1 VDD4
    F3 R1 F3 R1
    DQMA0 LDM VDD5 DQMA3 LDM VDD5
    B3 B3
    UDM 0.1U_0402_16V4Z UDM 0.1U_0402_16V4Z
    J1 J1
    VDDL VDDL
    J7 1 1 J7 1 1
    CMDA12 VSSDL CMDA12 VSSDL
    K9 K9
    ODT C383 C384 ODT C381 C382
    4.7U_0805_6.3V6K 4.7U_0805_6.3V6K
    +VDD_MEM18 QSA2 2 2 QSA1 2 2
    F7 F7
    QSA#2 LDQS QSA#1 LDQS
    E8 A7 E8 A7
    B LDQS VSSQ1 LDQS VSSQ1 B
    B2 B2
    VSSQ2 VSSQ2
    B8 B8
    VSSQ3 VSSQ3
    1

    D2 D2
    R260 QSA0 VSSQ4 QSA3 VSSQ4
    B7 D8 B7 D8
    1K_0402_1% QSA#0 UDQS VSSQ5 QSA#3 UDQS VSSQ5 CLKA0
    A8 E7 A8 E7 22 CLKA0
    UDQS VSSQ6 UDQS VSSQ6
    F2 F2
    VSSQ7 VSSQ7

    1
    F8 F8
    2

    MEM_VREF0 VSSQ8 MEM_VREF0 VSSQ8 R261


    J2 H2 J2 H2
    VREF VSSQ9 VREF VSSQ9 475_0402_1%
    H8 H8
    VSSQ10 VSSQ10
    1

    1 A2 A2
    R262 NC#A2 NC#A2
    E2 A3 E2 A3

    2
    1K_0402_1% C385 NC#E2 VSS1 NC#E2 VSS1 CLKA0#
    L1 E3 L1 E3 22 CLKA0#
    0.1U_0402_16V4Z NC#L1 VSS2 NC#L1 VSS2
    R3 J3 R3 J3
    2 NC#R3 VSS3 NC#R3 VSS3
    R7 N1 R7 N1
    2

    NC#R7 VSS4 NC#R7 VSS4


    R8 P9 R8 P9
    NC#R8 VSS5 NC#R8 VSS5
    (SSTL-1.8) VREF = .5*VDDQ
    HY5PS561621F-25 HY5PS561621F-25

    DDR BGA MEMORY


    DDR2 BGA MEMORY
    +VDD_MEM18 +VDD_MEM18

    0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.01U_0402_16V7K

    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    C395 C396 C397 C398 C399 C400 C401 C402 C386 C387 C388 C389 C390 C391 C392 C393
    A 1000P_0402_50V7K 1000P_0402_50V7K A
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

    om
    0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K 0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2005/05/05 2006/05/05 Title

    ho
    Issued Date Deciphered Date
    LS-2821 ATI_M56-P VGA Board

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    CHANNEL A EXT. 256M_1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 7 of 16

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    DATA Bus

    VRAM DDR2 chips (256MB & 128MB) Address

    CMD0
    0..31
    A3
    32..63

    32Mx16 DDR2 400MHz *4==>256MB CMD1 A0 A0


    CMD2 A2
    16Mx16 DDR2 400MHz*4==>128MB
    CMD3 A1 A1
    CMD4 A3
    D DQMA[7..0] CMD5 A4 D
    22,23 DQMA[7..0]
    CMDA[30..0] CMD6 A5
    22,23 CMDA[30..0]
    QSA#[7..0] CMD7
    22,23 QSA#[7..0]
    QSA[7..0] CMD8 CS# CS#
    22,23 QSA[7..0]
    MDA[63..0] CMD9 WE# WE#
    22,23 MDA[63..0]
    CMD10 BA0 BA0
    CMD11 CKE CKE
    CMD12 ODT ODT
    CMD13
    CMD14 A12 A12
    CMD15 RAS# RAS#
    CMD16 A11 A11
    CMD17 A10 A10
    U10 U11 CMD18 BA1 BA1
    CMDA10 L2 B9 MDA39 CMDA10 L2 B9 MDA59
    CMDA18 BA0 DQ15 MDA32 CMDA18 BA0 DQ15 MDA60
    L3
    BA1 DQ14
    B1 L3
    BA1 DQ14
    B1 CMD19 A8 A8
    D9 MDA38 D9 MDA58
    CMDA14 DQ13 MDA34 CMDA14 DQ13 MDA62
    R2
    A12 DQ12
    D1 R2
    A12 DQ12
    D1 CMD20 A9 A9
    CMDA16 P7 D3 MDA33 CMDA16 P7 D3 MDA63
    C CMDA17 A11 DQ11 MDA37 CMDA17 A11 DQ11 MDA56 C
    M2
    A10/AP DQ10
    D7 M2
    A10/AP DQ10
    D7 CMD21 A6 A6
    CMDA20 P3 C2 MDA35 CMDA20 P3 C2 MDA61
    CMDA19 A9 DQ9 MDA36 CMDA19 A9 DQ9 MDA57
    P8
    A8 DQ8
    C8 P8
    A8 DQ8
    C8 CMD22 A5
    CMDA23 P2 F9 MDA44 CMDA23 P2 F9 MDA51
    CMDA21 A7 DQ7 MDA43 CMDA21 A7 DQ7 MDA53
    N7
    A6 DQ6
    F1 N7
    A6 DQ6
    F1 CMD23 A7 A7
    CMDA6 N3 H9 MDA47 CMDA6 N3 H9 MDA48
    CMDA5 A5 DQ5 MDA40 CMDA5 A5 DQ5 MDA55
    N8
    A4 DQ4
    H1 N8
    A4 DQ4
    H1 CMD24 A4
    CMDA4 N2 H3 MDA41 CMDA4 N2 H3 MDA52
    CMDA13 A3 DQ3 MDA46 CMDA13 A3 DQ3 MDA49
    M7
    A2 DQ2
    H7 M7
    A2 DQ2
    H7 CMD25 CAS# CAS#
    CMDA3 M3 G2 MDA42 CMDA3 M3 G2 MDA54
    CMDA1 A1 DQ1 MDA45 CMDA1 A1 DQ1 MDA50
    M8
    A0 DQ0
    G8 M8
    A0 DQ0
    G8 CMD26 A13 A13
    CMD27 BA2 BA2
    CLKA1# K8 A9 +VDD_MEM18 CLKA1# K8 A9 +VDD_MEM18
    CLKA1 CK VDDQ1 CLKA1 CK VDDQ1
    J8
    CK VDDQ2
    C1 J8
    CK VDDQ2
    C1 CMD28
    C3 C3
    CMDA11 VDDQ3 CMDA11 VDDQ3
    K2
    CKE VDDQ4
    C7 K2
    CKE VDDQ4
    C7 CMD29
    C9 C9
    VDDQ5 VDDQ5
    VDDQ6
    E9
    VDDQ6
    E9 CMD30
    G1 G1
    CMDA8 VDDQ7 CMDA8 VDDQ7
    L8 G3 L8 G3
    CS VDDQ8 CS VDDQ8
    G7 G7
    CMDA9 VDDQ9 CMDA9 VDDQ9
    K3 G9 K3 G9
    WE VDDQ10 WE VDDQ10
    CMDA15 K7 A1 CMDA15 K7 A1
    RAS VDD1 RAS VDD1
    E1 E1
    CMDA25 VDD2 CMDA25 VDD2
    L7 J9 L7 J9
    CAS VDD3 CAS VDD3
    M9 M9
    DQMA5 VDD4 DQMA6 VDD4
    F3 R1 F3 R1
    DQMA4 LDM VDD5 DQMA7 LDM VDD5
    B3 B3
    UDM 0.1U_0402_16V4Z UDM 0.1U_0402_16V4Z
    J1 J1
    VDDL VDDL
    J7 1 1 J7 1 1
    B CMDA12 VSSDL CMDA12 VSSDL B
    K9 K9
    ODT C405 C406 ODT C403 C404
    +VDD_MEM18 4.7U_0805_6.3V6K
    QSA5 2 2 QSA6 2 2
    F7 F7
    QSA#5 LDQS 4.7U_0805_6.3V6K QSA#6 LDQS
    E8 A7 E8 A7
    LDQS VSSQ1 LDQS VSSQ1
    B2 B2
    VSSQ2 VSSQ2
    1

    B8 B8
    R266 VSSQ3 VSSQ3
    D2 D2
    1K_0402_1% QSA4 VSSQ4 QSA7 VSSQ4 CLKA1
    B7 D8 B7 D8 22 CLKA1
    QSA#4 UDQS VSSQ5 QSA#7 UDQS VSSQ5
    A8 E7 A8 E7
    UDQS VSSQ6 UDQS VSSQ6
    F2 F2
    2

    VSSQ7 VSSQ7

    1
    F8 F8
    MEM_VREF1 VSSQ8 MEM_VREF1 VSSQ8 R267
    J2 H2 J2 H2
    VREF VSSQ9 VREF VSSQ9 475_0402_1%
    H8 H8
    VSSQ10 VSSQ10
    1

    1 A2 A2
    R268 NC#A2 NC#A2
    E2 A3 E2 A3

    2
    1K_0402_1% C407 NC#E2 VSS1 (SSTL-1.8) VREF = .5*VDDQ NC#E2 VSS1 CLKA1#
    L1 E3 L1 E3 22 CLKA1#
    0.1U_0402_16V4Z NC#L1 VSS2 NC#L1 VSS2
    R3 J3 R3 J3
    2 NC#R3 VSS3 NC#R3 VSS3
    R7 N1 R7 N1
    2

    NC#R7 VSS4 NC#R7 VSS4


    R8 P9 R8 P9
    NC#R8 VSS5 NC#R8 VSS5

    HY5PS561621F-25 HY5PS561621F-25

    +VDD_MEM18 DDR2 BGA MEMORY +VDD_MEM18 DDR BGA MEMORY

    0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.1U_0402_16V4Z 0.01U_0402_16V7K 4.7U_0805_6.3V6K 0.01U_0402_16V7K

    1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
    A C417 C418 C419 C420 C421 C422 C423 C424 C408 C409 C410 C411 C412 C413 C414 C415 A
    1000P_0402_50V7K 1000P_0402_50V7K
    2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
    0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K
    0.01U_0402_16V7K 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.01U_0402_16V7K

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2005/05/05 Deciphered Date 2006/05/05 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LS-2821 ATI_M56-P VGA Board
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    0.1
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    CHANNEL A EXT. 256M_2
    Date: Monday, October 08, 2007 Sheet 8 of 16
    5 4 3 2 1
    5 4 3 2 1

    +3VS

    R272 1 2 8.2K_0402_5% PCI_DEVSEL#

    R273 1 2 8.2K_0402_5% PCI_STOP#

    R274 1 2 8.2K_0402_5% PCI_TRDY#

    R275 1 2 8.2K_0402_5% PCI_FRAME# U12B


    D11 F1 PCI_REQ0#
    R276 1 PCI_PLOCK# AD0 REQ0# PCI_GNT0#
    2 8.2K_0402_5% C8 G4
    D AD1 GNT0# PCI_REQ1# D
    D9 PCI B6
    R277 1 AD2 REQ1#/GPIO50
    2 8.2K_0402_5% PCI_IRDY# E12 A7
    AD3 GNT1#/GPIO51 PCI_REQ2#
    E9 F13
    R278 1 AD4 REQ2#/GPIO52
    2 8.2K_0402_5% PCI_SERR# C9 F12
    AD5 GNT2#/GPIO53 PCI_REQ3#
    E10 E6
    R279 1 AD6 REQ3#/GPIO54
    2 8.2K_0402_5% PCI_PERR# B7 F6 PCI_GNT3#
    AD7 GNT3#/GPIO55
    C7
    AD8
    C5 D8
    AD9 C/BE0#
    G11 B4 Place closely pin
    AD10 C/BE1#
    F8 D6
    AD11 C/BE2# D4
    F11 A5
    AD12 C/BE3# CLK_PCI_ICH
    E7
    AD13 PCI_IRDY#
    A3 D3
    AD14 IRDY#

    1
    +3VS D2 E3 @
    AD15 PAR PCI_RST# R280
    F10 R1 PCI_RST# 37,38
    AD16 PCIRST# PCI_DEVSEL# 10_0402_5%
    D5 C6
    R281 1 AD17 DEVSEL#
    2 8.2K_0402_5% PCI_PIRQA# D10 E4 PCI_PERR#
    PCI_SERR# 38
    AD18 PERR# PCI_PLOCK#
    B3 C2

    2
    R282 1 AD19 PLOCK#
    2 8.2K_0402_5% PCI_PIRQB# F7 J4 PCI_SERR#
    AD20 SERR# PCI_STOP#
    C3 A4 1
    R283 1 AD21 STOP#
    2 8.2K_0402_5% PCI_PIRQC# F3 F5 PCI_TRDY# @
    AD22 TRDY# PCI_FRAME# C425
    F4 D7
    R284 1 AD23 FRAME#
    2 8.2K_0402_5% PCI_PIRQD# C1 8.2P_0402_50V
    AD24 PLT_RST# 2
    G7 C14 PLT_RST# 9,20,30,31,32
    R285 1 AD25 PLTRST#
    2 8.2K_0402_5% PCI_PIRQE# H7 D4 CLK_PCI_ICH
    CLK_PCI_ICH 17
    AD26 PCICLK PCI_PME#
    D1 R2 PCI_PME# 38
    R286 1 AD27 PME#
    2 8.2K_0402_5% PCI_PIRQF# G5
    AD28
    H6
    AD29 3/28 PCI_PME# Remvoe 8.2k pull high +3VALW resistance.
    R287 1 2 8.2K_0402_5% PCI_PIRQG# G1
    AD30
    H3
    R288 2 AD31
    1 8.2K_0402_5% PCI_PIRQH#

    C C
    PCI_PIRQA# J5
    Interrupt I/F H4 PCI_PIRQE#
    R289 1 PIRQA# PIRQE#/GPIO2
    2 8.2K_0402_5% PCI_REQ0# PCI_PIRQB# E1 K6 PCI_PIRQF#
    PCI_PIRQC# PIRQB# PIRQF#/GPIO3 PCI_PIRQG#
    J6 F2
    R290 1 PIRQC# PIRQG#/GPIO4
    2 8.2K_0402_5% PCI_REQ1# PCI_PIRQD# C4 G2 PCI_PIRQH# 1 2 ACCEL_INT 37
    PIRQD# PIRQH#/GPIO5 R291 0_0402_5%
    R292 1 2 8.2K_0402_5% PCI_REQ2# ICH9-M ES_FCBGA676
    08/25 Follow Abita
    R293 1 2 8.2K_0402_5% PCI_REQ3#

    A16 swap override Strap


    B
    Boot BIOS Strap B
    Low= A16 swap override Enble
    PCI_GNT3# Boot BIOS
    High= Default * PCI_GNT0# SPI_CS#1
    Location

    @R294
    @R294 0 1 SPI
    PCI_GNT3# 1 2
    1K_0402_5%
    1 0 PCI

    1 1 LPC *

    +3VALW

    @ R295
    SPI_CS1#_R 1 2
    27 SPI_CS1#_R
    1K_0402_5%
    @ R296
    PCI_GNT0# 1 2
    1K_0402_5%

    A A

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    ICH9(1/4)-PCI/INT

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 25 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    ICH8M Internal VR Enable Strap


    +RTCVCC (Internal VR for VccSus1.05, VccSus1.5,
    +3VS
    VccCL1.5)
    1 2 SM_INTRUDER# ICH_INTVRMEN Low = Internal VR Disabled R298
    R297 1M_0402_5% GATEA20 1 2
    1 2 LAN100_SLP High = Internal VR Enabled(Default) 10K_0402_5%
    R299 330K_0402_5%
    1 2 ICH_INTVRMEN R301
    R300 330K_0402_5% ICH8M LAN100 SLP Strap KB_RST# 1 2
    1 2 ICH_SRTCRST# 10K_0402_5%
    R302 180K_0402_5% (Internal VR for VccLAN1.05 and VccCL1.05)

    1
    D D

    0_0402_5%

    0_0402_5%
    1
    C426 @ @ +VCCP
    R303 R304 ICH_LAN100_SLP Low = Internal VR Disabled
    0.1U_0402_16V4Z @ R305
    2 High = Internal VR Enabled(Default) H_DPRSTP# 1 2

    2
    56_0402_5%
    LPC_AD[0..3] 31,37,38
    U12A @ R306
    ICH_RTCX1 C23 K5 LPC_AD0 H_DPSLP# 1 2
    ICH_RTCX2 RTCX1 FWH0/LAD0 LPC_AD1 56_0402_5%
    C24 K4
    R307 RTCX2 FWH1/LAD1 LPC_AD2
    L6
    ICH_RTCRST# FWH2/LAD2 LPC_AD3
    +RTCVCC 1 2 A25 K2
    20K_0402_5% ICH_SRTCRST# RTCRST# FWH3/LAD3
    F20
    SM_INTRUDER# SRTCRST# LPC_FRAME#
    C22 K3 LPC_FRAME# 31,37,38
    INTRUDER# FWH4/LFRAME# +VCCP

    RTC
    1

    LPC
    1
    C427 CLRP2 ICH_INTVRMEN B22 J3
    SHORT PADS LAN100_SLP INTVRMEN LDRQ0#
    A22 J1
    1U_0603_10V4Z LAN100_SLP LDRQ1#/GPIO23 T54 PAD

    2
    2 GATEA20
    E25 N7 GATEA20 38
    GLAN_CLK A20GATE H_A20M# R308
    AJ27 H_A20M# 6
    A20M# 56_0402_5%
    C13
    LAN_RSTSYNC H_DPRSTP_R# R309 H_DPRSTP#
    AJ25 1 2 H_DPRSTP# 7,9,49
    DPRSTP# H_DPSLP# 0_0402_5%
    F14 AE23 H_DPSLP# 7

    1
    R312 33_0402_5% HDA_BITCLK LAN_RXD0 DPSLP#
    21,33 HDA_BITCLK_CODEC 1 2 G13
    R313 33_0402_5% LAN_RXD1 R_H_FERR# R310 H_FERR#
    34 HDA_BITCLK_MDC 1 2 D14 AJ26 1 2 H_FERR# 6
    LAN_RXD2 FERR#

    LAN / GLAN
    R324 33_0402_5% 1 2 56_0402_5%
    34 HDA_BITCLK_VGA
    D13 AD22 H_PWRGOOD 3/28 add 56ohm
    LAN_TXD_0 CPUPWRGD H_PWRGOOD 6,7
    R314 33_0402_5% 1 2 HDA_SYNC D12
    34 HDA_SYNC_MDC LAN_TXD_1
    R316 33_0402_5% 1 2 E13 AF25 H_IGNNE#
    21,33 HDA_SYNC_CODEC +1.5VS LAN_TXD_2 IGNNE# H_IGNNE# 6
    R397 33_0402_5% 1 2 within 2" from R379
    21,33 HDA_SYNC_VGA
    B10 AE22 H_INIT#
    GPIO56 INIT# H_INIT# 6 +VCCP
    R317 33_0402_5% 1 2 HDARST# AG25 H_INTR

    CPU
    C 21,33 HDA_RST#_CODEC INTR H_INTR 6 C
    R318 33_0402_5% 1 2 R311 B28 L3 KB_RST#
    34 HDA_RST#_MDC GLAN_COMPI RCIN# KB_RST# 38
    R398 33_0402_5% 1 2 1 2 GLAN_COMP B27
    34 HDA_RST#_VGA GLAN_COMPO

    1
    24.9_0402_1% AF23 H_NMI
    NMI H_NMI 6
    HDA_BITCLK AF6 AF24 H_SMI# R315
    HDA_BIT_CLK SMI# H_SMI# 6
    HDA_SYNC AH4 56_0402_5%
    HDA_SYNC H_STPCLK#
    AH27 H_STPCLK# 6
    HDARST# STPCLK#
    AE7

    2
    HDA_RST# THRMTRIP_ICH# R319
    AG26 1 2 54.9_0402_1% H_THERMTRIP# 6,9
    HDA_SDIN0 THRMTRIP#
    33 HDA_SDIN0 AF4
    HDA_SDIN1 HDA_SDIN0
    34 HDA_SDIN1 AG4
    HDA_SDIN1 TP12
    AG27 placed within 2"
    HDA_SDIN2 AH3
    21 HDA_SDIN2 HDA_SDIN2 from ICH9M
    AE5

    IHDA
    R320 33_0402_5% HDA_SDIN3
    34 HDA_SDOUT_MDC 1 2 AH11 SATA_RXN4_C 29
    R321 33_0402_5% HDA_SDOUT SATA4RXN 0.01U_0402_50V7K
    33 HDA_SDOUT_CODEC 1 2 AG5 AJ11 SATA_RXP4_C 29
    R323 33_0402_5% HDA_SDOUT SATA4RXP SATA_TXN4_C
    21 HDA_SDOUT_VGA 1 2 AG12 2 1 C428 SATA_TXN4
    SATA_TXN4 29 ODD
    SATA4TXN SATA_TXP4_C
    PAD T55 AG7 AF12 2 1 C429 SATA_TXP4
    SATA_TXP4 29
    HDA_DOCK_EN#/GPIO33 SATA4TXP
    PAD T56 AE8
    HDA_DOCK_RST#/GPIO34 0.01U_0402_50V7K
    SATA_LED# AG8
    39 SATA_LED# SATALED#
    AH9 SATA_RXN5_C 36
    SATA5RXN 0.01U_0402_50V7K
    HDD 29 SATA_RXN0_C AJ16 AJ9 SATA_RXP5_C 36e-SATA
    0.01U_0402_50V7K SATA0RXN SATA5RXP SATA_TXN5_C
    29 SATA_RXP0_C AH16 AE10 2 1 C430 SATA_TXN5
    SATA_TXN5 36
    SATA_TXN0 C431 SATA_TXN0_C SATA0RXP SATA5TXN SATA_TXP5_C
    29 SATA_TXN0 1 2 AF17 AF10 2 1 C432 SATA_TXP5
    SATA_TXP5 36 De-feature disable
    SATA_TXP0 C433 SATA_TXP0_C SATA0TXN SATA5TXP 0.01U_0402_50V7K
    29 SATA_TXP0 1 2 AG17
    SATA0TXP CLK_PCIE_SATA#
    AH18 CLK_PCIE_SATA# 17
    0.01U_0402_50V7K SATA_CLKN CLK_PCIE_SATA

    SATA
    29 SATA_RXN1_C AH13 AJ18 CLK_PCIE_SATA 17
    0.01U_0402_50V7K SATA1RXN SATA_CLKP
    29 SATA_RXP1_C AJ13 AJ7
    SATA_TXN1 C820 SATA_TXN1_C SATA1RXP SATARBIAS# R322
    Multi bay 29 SATA_TXN1 1 2 AG14 AH7 1 2
    SATA_TXP1 C821 SATA_TXP1_C SATA1TXN SATARBIAS 24.9_0402_1%
    29 SATA_TXP1 1 2 AF14
    SATA1TXP
    0.01U_0402_50V7K Within 500 mils
    ICH9-M ES_FCBGA676
    B B

    XOR CHAIN ENTRANCE STRAP:RSVD


    +3VS

    @ R325
    1 2 HDA_SDOUT_CODEC
    1K_0402_5%

    @ R326
    1 2 ICH_RSVD +RTCVCC +3VL
    1K_0402_5%
    ICH_RSVD 27 0821 Change C528 and C516 to 15PF HDA_BITCLK
    BATT1.1
    1

    ICH_RTCX1 @ D8
    R327 R329 W=20mils 2
    R328 10_0402_5% 1 2 1 R330 JBATT1
    1 2 ICH_RTCX2 W=20mils 3 1 2 1
    0_0402_5% W=20mils 1
    W=20mils 2
    2

    10M_0402_5% DAN202U_SC70 1K_0402_5% 2


    1 3
    C438 GND
    ICH_RSVD HDA_SDOUT_CODEC C436
    1 1
    C437
    4
    GND
    1
    @ 2.2U_0603_6.3V4Z ACES_85205-02001
    15P_0402_50V8J 15P_0402_50V8J C439 2 CONN@
    2 2 10P_0402_25V8K Place near ICH9
    A 0 0 2 A

    0 1 Y2
    1 4
    1 0 2 3

    1 1 32.768KHZ_12.5P_MC-146 Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ICH9(2/4)_LAN,HD,IDE,LPC
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 26 of 51
    5 4 3 2 1
    5 4 3 2 1

    +3VALW R331 1 2 2.2K_0402_5% Place closely pin Place closely pin


    +3VS R332 1 2 2.2K_0402_5%
    U12C AF3 H1
    ICH_SMBCLK G16 AH23 GPIO21 CLK_48M_ICH CLK_14M_ICH
    17,21,31,37 ICH_SMBCLK SMBCLK SATA0GP/GPIO21
    1 2 SIRQ ICH_SMBDATA A13 AF19 GPIO19
    R333 10K_0402_5%
    17,21,31,37 ICH_SMBDATA
    LINKALERT# E17
    SMBDATA SMB SATA1GP/GPIO19
    AE21 GPIO36

    SATA
    GPIO
    LINKALERT#/GPIO60/CLGPIO4 SATA4GP/GPIO36

    1
    1 2 PM_CLKRUN# ME_EC_CLK1 C17 AD20 GPIO37 @ @
    R334 8.2K_0402_5% ME_EC_DATA1 SMLINK0 SATA5GP/GPIO37 R342 R343
    B18
    OCP# SMLINK1 CLK_14M_ICH
    1 2 H1 CLK_14M_ICH 17
    R335 10K_0402_5% +3VS ICH_RI# CLK14 CLK_48M_ICH 10_0402_5% 10_0402_5%
    F19 clocks AF3 CLK_48M_ICH 17
    THERM_SCI# RI# CLK48
    1 2

    2
    @ R336 8.2K_0402_5% PAD T57 SUS_STAT# R4 P1 ICH_SUSCLK T58 PAD
    CLKREQ#_C XDP_DBRESET# SUS_STAT#/LPCPD# SUSCLK
    1 2 6 XDP_DBRESET# G19 1 @ 1 @

    1
    @ R337 10K_0402_5% @ @ SYS_RESET# SLP_S3# C440 C441
    C16 SLP_S3# 38
    D PM_BMBUSY# R339 R340 PM_BMBUSY# SLP_S3# SLP_S4# D
    1 2 9 PM_BMBUSY# M6 E16 T60 PAD
    @ R338 8.2K_0402_5% 10K_0402_5% 10K_0402_5% PMSYNC#/GPIO0 SLP_S4# SLP_S5# 4.7P_0402_50V8C 4.7P_0402_50V8C
    G17 SLP_S5# 38
    SLP_S5# 2 2

    SYS / GPIO
    1 2 EC_SCI# 38 EC_LID_OUT# EC_LID_OUT# A17
    R341 8.2K_0402_5% SMBALERT#/GPIO11 S4_STATE#
    C10

    2
    H_STP_PCI# S4_STATE#/GPIO26
    17 H_STP_PCI# A14
    GPIO6 R345 STP_PCI#
    1 2 17 H_STP_CPU# 1 2 0_0402_5% R_STP_CPU# E19 G20 PM_PWROK
    PM_PWROK 9,38
    R346 10K_0402_5%
    R344 8.2K_0402_5% STP_CPU# PWROK
    1 2
    PM_CLKRUN# L4 M2 R348 1 2 0_0402_5%
    CLKRUN# DPRSLPVR/GPIO16 DPRSLPVR 9,49

    Power MGT
    1 2 GPIO18 ICH_PCIE_WAKE# E20 B13 ICH_LOW_BAT#
    30,31 ICH_PCIE_WAKE# WAKE# BATLOW#
    R349 8.2K_0402_5% SIRQ M5
    38 SIRQ SERIRQ
    1 2 GPIO19 THERM_SCI# AJ23 R3 PWRBTN_OUT#
    21,38 THERM_SCI# THRM# PWRBTN# PWRBTN_OUT# 38
    R350 8.2K_0402_5%
    1 2 GPIO20 VGATE D21 D20
    17,49 VGATE VRMPWRGD LAN_RST#
    R351 8.2K_0402_5%
    1 2 GPIO21 R353 1 2 PAD T59 A20 D22 R_EC_RSMRST# R354 1 2 100_0402_5%
    TP11 RSMRST# EC_RSMRST# 38
    R352 8.2K_0402_5% 100K_0402_5% R355 1 2 10K_0402_5%
    1 2 GPIO22 6 OCP# OCP# AG19 R5 CK_PWRGD
    GPIO1 CK_PWRGD CK_PWRGD 17
    R356 8.2K_0402_5% GPIO6 AH21
    GPIO36 EC_SCI# GPIO6 M_PWROK
    1 2 38 EC_SCI# AG21 R6 M_PWROK 9,38
    R357 8.2K_0402_5% EC_SMI# GPIO7 CLPWROK
    38 EC_SMI# A21
    GPIO37 GPIO8 +3VS
    1 2 C12 B16
    R358 8.2K_0402_5% GPIO12 SLP_M#
    C21
    GPIO39 17/14 GPIO13 CL_CLK0 R360
    1 2 AE18 F24 CL_CLK0 9
    R359 10K_0402_5% GPIO18 GPIO17 CL_CLK0 0.1U_0402_16V4Z
    K1 B19 1 2

    GPIO
    GPIO48 GPIO20 GPIO18 CL_CLK1 3.24K_0402_1%

    Controller Link
    1 2 AF8
    GPIO20

    1
    R361 8.2K_0402_5% GPIO22 AJ22 F22 CL_DATA0 1
    SCLOCK/GPIO22 CL_DATA0 CL_DATA0 9
    1 2 GPIO57 DIS/UMA A9 C19 C442 R363
    R362 8.2K_0402_5% GPIO27 CL_DATA1 453_0402_1%
    D19
    8.2K_0402_5% CLKREQ#_C GPIO28 CL_VREF0_ICH
    17 CLKREQ#_C L1 C25
    R364 GPIO38 SATACLKREQ#/GPIO35 CL_VREF0 CL_VREF1_ICH 2 NA lead free
    +3VS 1 2 AE19 A19

    2
    GPIO49 R393 1 SLOAD/GPIO38 CL_VREF1
    1 2 31 EXP_CPPE# 2 0_0402_5% GPIO39 AG22
    C R365 10K_0402_5% GPIO48 SDATAOUT0/GPIO39 CL_RST# +3VALW C
    AF21 F21 CL_RST# 9
    GPIO49 SDATAOUT1/GPIO48 CL_RST0#
    @ AH24 D18
    @ GPIO57 GPIO49 CL_RST1# R367
    A8
    R366 1K_0402_5% GPIO57/CLGPIO5 XMIT_OFF 0.1U_0402_16V4Z
    +3VS 1 2 A16 XMIT_OFF 31 1 2
    SB_SPKR MEM_LED/GPIO24 GPIO10 3.24K_0402_1%
    33 SB_SPKR M7 C18
    SPKR GPIO10/SUS_PWR_ACK

    1
    MCH_ICH_SYNC# AJ24 C11 GPIO14 R370 1
    9 MCH_ICH_SYNC#

    MISC
    +3VALW ICH_RSVD MCH_SYNC# GPIO14/AC_PRESENT LAN_WOL_EN C443 R368
    26 ICH_RSVD B21 C20 2 1 +3VALW
    TP3 WOL_EN/GPIO9 453_0402_1%
    AH20
    TP8 100K_0402_5%
    AJ20
    LINKALERT# TP9 2
    1 2 R424 AJ21

    2
    R369 10K_0402_5% TP10
    Low -->default
    1 2 ICH_LOW_BAT# High -->No boot ICH9-M ES_FCBGA676
    R371 8.2K_0402_5%
    1 2 ICH_PCIE_WAKE# U12D
    R372 1K_0402_5% PCIE_RXN1 N29 V27 DMI_RXN0 DMI_RXN0 9
    31 PCIE_RXN1 PERN1 DMI0RXN
    1 2 ICH_RI# PCIE_RXP1 N28 V26 DMI_RXP0 DMI_RXP0 9
    31 PCIE_RXP1 PERP1 DMI0RXP
    R374 10K_0402_5% TV Tuner/WWAN/Robeson
    31 PCIE_TXN1 C445 1 2 0.1U_0402_16V4Z PCIE_C_TXN1 P27 U29 DMI_TXN0 DMI_TXN0 9
    XDP_DBRESET# C444 1 PCIE_C_TXP1 PETN1 DMI0TXN DMI_TXP0
    1 2 31 PCIE_TXP1 2 0.1U_0402_16V4Z P26 U28 DMI_TXP0 9

    Direct Media Interface


    R375 10K_0402_5% PETP1 DMI0TXP
    1 2 S4_STATE# L29 Y27 DMI_RXN1 DMI_RXN1 9
    R376 10K_0402_5% PERN2 DMI1RXN DMI_RXP1
    L28 Y26 DMI_RXP1 9
    ME_EC_CLK1 PERP2 DMI1RXP DMI_TXN1
    1 2 M27 W29 DMI_TXN1 9
    R377 10K_0402_5% PETN2 DMI1TXN DMI_TXP1
    M26 W28 DMI_TXP1 9
    ME_EC_DATA1 PETP2 DMI1TXP
    1 2

    PCI - Express
    R378 10K_0402_5% PCIE_RXN3 J29 AB27 DMI_RXN2 DMI_RXN2 9
    31 PCIE_RXN3 PERN3 DMI2RXN
    1 2 GPIO10 PCIE_RXP3 J28 AB26 DMI_RXP2 DMI_RXP2 9
    31 PCIE_RXP3 PERP3 DMI2RXP
    R379 10K_0402_5% WLAN 31 PCIE_TXN3 C448 1 2 0.1U_0402_16V4Z PCIE_C_TXN3 K27 AA29 DMI_TXN2 DMI_TXN2 9
    EC_LID_OUT# C449 1 PCIE_C_TXP3 PETN3 DMI2TXN DMI_TXP2
    1 2 31 PCIE_TXP3 2 0.1U_0402_16V4Z K26 AA28 DMI_TXP2 9
    R373 10K_0402_5% PETP3 DMI2TXP
    1 2 EC_SMI# PCIE_RXN4 G29 AD27 DMI_RXN3 DMI_RXN3 9
    31 PCIE_RXN4 PERN4 DMI3RXN
    R380 8.2K_0402_5% PCIE_RXP4 G28 AD26 DMI_RXP3 DMI_RXP3 9
    31 PCIE_RXP4 PERP4 DMI3RXP
    1 2 GPIO14 New Card 31 PCIE_TXN4 C450 1 2 0.1U_0402_16V4Z PCIE_C_TXN4 H27 AC29 DMI_TXN3 DMI_TXN3 9
    B R381 8.2K_0402_5% C451 1 PETN4 DMI3TXN B
    31 PCIE_TXP4 2 0.1U_0402_16V4Z PCIE_C_TXP4 H26 AC28 DMI_TXP3 DMI_TXP3 9
    PETP4 DMI3TXP
    PCIE_RXN5 E29 T26 CLK_PCIE_ICH#
    +3VS +3VS 32 PCIE_RXN5 PERN5 DMI_CLKN CLK_PCIE_ICH# 17
    PCIE_RXP5 E28 T25 CLK_PCIE_ICH
    32 PCIE_RXP5 PERP5 DMI_CLKP CLK_PCIE_ICH 17
    Card reader 32 PCIE_TXN5 C501 1 2 0.1U_0402_16V4Z PCIE_C_TXN5 F27
    C500 1 PCIE_C_TXP5 PETN5
    Board ID 32 PCIE_TXP5 2 0.1U_0402_16V4Z F26 AF29 R382 24.9_0402_1% Within 500 mils
    PETP5 DMI_ZCOMP
    2

    AF28 DMI_IRCOMP 1 2 +1.5VS


    GLAN_RXN DMI_IRCOMP
    30 GLAN_RXN C29
    R745 R747 @ GLAN_RXP PERN6/GLAN_RXN USB20_N0
    30 GLAN_RXP C28 AC5 USB20_N0 36
    10K_0402_5% 10K_0402_5% C452 1 0.1U_0402_16V4Z GLAN_TXN_C PERP6/GLAN_RXP USBP0N USB20_P0
    GLAN 30 GLAN_TXN
    C453 1
    2
    0.1U_0402_16V4Z GLAN_TXP_C
    D27
    PETN6/GLAN_TXN USBP0P
    AC4
    USB20_N1
    USB20_P0 USB-0
    36 Right side
    30 GLAN_TXP 2 D26 AD3 USB20_N1 36
    1

    DIS/UMA 17/14 PETP6/GLAN_TXP USBP1N USB20_P1


    AD2 USB20_P1 USB-1
    36 Right side
    USBP1P USB20_N2
    PAD T61 D23 AC1 USB20_N2 36
    SPI_CLK USBP2N
    2

    PAD T62 D24 AC2 USB20_P2 USB-2 Left side(with ESATA)


    SPI_CS0# USBP2P USB20_P2 36
    17" High 25 SPI_CS1#_R SPI_CS1#_R F23 AA5 USB20_N3
    SPI_CS1#GPIO58/CLGPIO6 USBP3N USB20_N3 40
    R746 @ R748 AA4 USB20_P3
    10K_0402_5% 10K_0402_5% USBP3P USB20_N4
    USB20_P3 USB-3
    40 Dock
    14" Low PAD T63 D25
    SPI_MOSI SPI USBP4N
    AB2
    USB20_P4
    USB20_N4 19
    PAD T64 E23 AB3 USB20_P4 USB-4
    19 Camera
    1

    SPI_MISO USBP4P USB20_N5


    Dis" High USB_OC#0 USBP5N
    AA1
    USB20_P5
    USB20_N5 31
    N4 AA2 USB20_P5 USB-5
    31 WLAN
    R383 1 OC0#/GPIO59 USBP5P
    UMA" Low 36 BT_OFF 2 0_0402_5% USB_OC#1 N5 W5 USB20_N6
    USB20_N6 36
    USB_OC#2 OC1#/GPIO40 USBP6N USB20_P6
    N6 USB W4 USB20_P6 USB-6
    36 Bluetooth
    RP27 WXMIT_OFF# OC2#/GPIO41 USBP6P USB20_N7
    31 WXMIT_OFF# P6 Y3 USB20_N7 36
    USB_OC#6 USB_OC#4 OC3#/GPIO42 USBP7N USB20_P7
    4 5 +3VALW M1 Y2 USB20_P7 USB-7
    36 Finger Printer
    USB_OC#1 USB_OC#5 OC4#/GPIO43 USBP7P USB20_N8
    3 6 N2 W1 USB20_N8 31
    USB_OC#2 USB_OC#6 OC5#/GPIO29 USBP8N USB20_P8
    2 7 M4 W2 USB20_P8 USB-8
    31 MiniCard(WWAN/TV)
    USB_OC#4 USB_OC#7 OC6#/GPIO30 USBP8P USB20_N9
    1 8 M3 V2 USB20_N9 31
    USB_OC#8 OC7#/GPIO31 USBP9N USB20_P9
    N3 V3 USB20_P9 USB-9
    31 Express card
    10K_1206_8P4R_5% USB_OC#9 OC8#/GPIO44 USBP9P
    N1 U5
    USB_OC#10 OC9#/GPIO45 USBP10N
    P5 U4
    RP28 USB_OC#11 OC10#/GPIO46 USBP10P
    P3 U1
    USB_OC#7 OC11#/GPIO47 USBP11N
    4 5 U2
    A USB_OC#8 USBRBIAS USBP11P A
    3 6 AG2
    USB_OC#9 USBRBIAS
    2 7 AG1
    USBRBIAS#
    1

    USB_OC#0 1 8 Within 500 mils

    om
    ICH9-M ES_FCBGA676
    10K_1206_8P4R_5% R384

    l.c
    22.6_0402_1%
    RP29

    ai
    2

    WXMIT_OFF# 4 5
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    USB_OC#5 3 6
    USB_OC#10 2 7 2007/09/26 2007/09/26 Title

    ho
    USB_OC#11
    Issued Date Deciphered Date
    1 8
    ICH9(3/4)_DMI,USB,GPIO,PCIE

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    10K_1206_8P4R_5% AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 27 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    +RTCVCC +VCCP U12E


    U12F AA26 H5
    VSS[001] VSS[107]
    20 mils A23 G3: 6uA A15 AA27 J23
    VCCRTC VCC1_05[01] VSS[002] VSS[108]
    1634mA B15 AA3 J26

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    ICH_V5REF_RUN VCC1_05[02] 0.1U_0402_16V4Z 0.1U_0402_16V4Z VSS[003] VSS[109]
    1 1 A6
    V5REF
    2mA VCC1_05[03]
    C15 AA6
    VSS[004] VSS[110]
    J27

    C462

    C454
    D15 1 1 AB1 AC22
    VCC1_05[04] C457 C455 VSS[005] VSS[111]
    E15 AA23 K28
    ICH_V5REF_SUS VCC1_05[05] VSS[006] VSS[112]
    AE1 2mA F15 AB28 K29
    2 2 V5REF_SUS VCC1_05[06] VSS[007] VSS[113]
    L11 AB29 L13
    VCC1_05[07] 2 2 VSS[008] VSS[114]
    AA24 646mA L12 AB4 L15
    VCC1_5_B[01] VCC1_05[08] VSS[009] VSS[115]
    AA25 L14 AB5 L2
    VCC1_5_B[02] VCC1_05[09] VSS[010] VSS[116]
    AB24 L16 AC17 L26
    VCC1_5_B[03] VCC1_05[10] VSS[011] VSS[117]
    AB25 L17 AC26 L27
    R387 VCC1_5_B[04] VCC1_05[11] VSS[012] VSS[118]
    AC24 L18 AC27 L5
    10U_0805_10V4Z VCC1_5_B[05] VCC1_05[12] R385 VSS[013] VSS[119]
    +1.5VS 1 2 40 mils AC25
    VCC1_5_B[06] VCC1_05[13]
    M11 AC3
    VSS[014] VSS[120]
    L7
    D CHB1608U301_0603 AD24 M18 0.01U_0402_16V7K 1 2 AD1 M12 D
    1 VCC1_5_B[07] VCC1_05[14] +1.5VS VSS[015] VSS[121]
    AD25 P11 CHB1608U301_0603 AD10 M13

    CORE
    1 1 1 VCC1_5_B[08] VCC1_05[15] VSS[016] VSS[122]
    + C459 C460 C456 AE25 P18 AD12 M14

    220U_D2_4VM
    VCC1_5_B[09] VCC1_05[16] 1 1 VSS[017] VSS[123]
    C461 C463

    C458
    AE26 T11 AD13 M15
    VCC1_5_B[10] VCC1_05[17] VSS[018] VSS[124]
    AE27 T18 AD14 M16
    2 2 2 2 VCC1_5_B[11] VCC1_05[18] 10U_0805_10V4Z VSS[019] VSS[125]
    AE28 U11 AD17 M17
    VCC1_5_B[12] VCC1_05[19] 2 2 VSS[020] VSS[126]
    AE29 U18 AD18 M23
    +5VS +3VS 10U_0805_10V4Z 2.2U_0603_6.3V4Z VCC1_5_B[13] VCC1_05[20] VSS[021] VSS[127]
    F25 V11 AD21 M28
    VCC1_5_B[14] VCC1_05[21] VSS[022] VSS[128]
    G25 V12 AD28 M29
    VCC1_5_B[15] VCC1_05[22] VSS[023] VSS[129]
    H24 V14 AD29 N11
    VCC1_5_B[16] VCC1_05[23] VSS[024] VSS[130]
    1

    H25 V16 AD4 N12


    R386 D9 VCC1_5_B[17] VCC1_05[24] VSS[025] VSS[131]
    J24 V17 +VCCP AD5 N13
    VCC1_5_B[18] VCC1_05[25] VSS[026] VSS[132]

    VCCA3GP

    22U_0805_6.3VAM
    J25 V18 AD6 N14
    100_0402_5% CH751H-40_SC76 VCC1_5_B[19] VCC1_05[26] VSS[027] VSS[133]
    K24 1 AD7 N15
    VCC1_5_B[20] C464 VSS[028] VSS[134]
    K25 AD9 N16
    2

    VCC1_5_B[21] VSS[029] VSS[135]


    L23 AE12 N17
    ICH_V5REF_RUN VCC1_5_B[22] VSS[030] VSS[136]
    L24 R29 AE13 N18
    VCC1_5_B[23] VCCDMIPLL 2 VSS[031] VSS[137]
    1 20 mils L25
    VCC1_5_B[24]
    AE14
    VSS[032] VSS[138]
    N26
    C465 M24 W23 AE16 N27
    VCC1_5_B[25]
    M25
    VCC1_5_B[26]
    23mA VCC_DMI[1]
    VCC_DMI[2]
    Y23 +VCCP AE17
    VSS[033]
    VSS[034]
    VSS[139]
    VSS[140]
    P12
    0.1U_0402_10V6K N23 AE2 P13
    2 VCC1_5_B[27] VSS[035] VSS[141]
    N24 AB23 AE20 P14
    VCC1_5_B[28]
    N25 48mA V_CPU_IO[1] AC23 AE24
    VSS[036] VSS[142]
    P15
    VCC1_5_B[29] V_CPU_IO[2] VSS[037] VSS[143]

    4.7U_0603_6.3V6M

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    P24 AE3 P16
    VCC1_5_B[30] +3VS VSS[038] VSS[144]
    P25 AG29 1 1 1 AE4 P17
    +5VALW +3VALW VCC1_5_B[31] VCC3_3[01] VSS[039] VSS[145]

    C466

    C467

    C468
    R24 2mA AJ6 AE6 P2
    VCC1_5_B[32] VCC3_3[02] VSS[040] VSS[146]
    R25 AC10 AE9 P23
    VCC1_5_B[33] VCC3_3[07] VSS[041] VSS[147]

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    R26 AF13 P28
    VCC1_5_B[34] VSS[042] VSS[148]
    1

    2 2 2
    R27 AD19 1 1 1 AF16 P29
    R388 D10 VCC1_5_B[35] VCC3_3[03] VSS[043] VSS[149]
    T24 AF20 AF18 P4

    VCCP_CORE
    VCC1_5_B[36] VCC3_3[04] VSS[044] VSS[150]

    C469

    C470

    C471
    T27 AG24 AF22 P7
    10_0402_5% CH751H-40_SC76 VCC1_5_B[37] VCC3_3[05] VSS[045] VSS[151]
    T28 AC20 AH26 R11
    C VCC1_5_B[38] VCC3_3[06] +3VS 2 2 2 VSS[046] VSS[152] C
    T29 (DMI) AF26 R12
    2

    ICH_V5REF_SUS VCC1_5_B[39] VSS[047] VSS[153]


    U24
    VCC1_5_B[40]
    308mA AF27
    VSS[048] VSS[154]
    R13
    20 mils U25 B9 0.1U_0402_16V4Z AF5 R14
    VCC1_5_B[41] VCC3_3[08] VSS[049] VSS[155]
    1 V24 F9 1 AF7 R15
    C472 VCC1_5_B[42] VCC3_3[09] C473 VSS[050] VSS[156]
    V25 G3 AF9 R16
    VCC1_5_B[43] VCC3_3[10] VSS[051] VSS[157]
    U23 G6 AG13 R17
    VCC1_5_B[44] VCC3_3[11] VSS[052] VSS[158]

    PCI
    0.1U_0402_10V6K W24 J2 AG16 R18
    2 VCC1_5_B[45] VCC3_3[12] 2 VSS[053] VSS[159]
    W25 J7 AG18 R28
    VCC1_5_B[46] VCC3_3[13] VSS[054] VSS[160]
    K23 K7 AG20 T12
    VCC1_5_B[47] VCC3_3[14] VSS[055] VSS[161]
    Y24 AG23 T13
    VCC1_5_B[48] R741 VSS[056] VSS[162]
    Y25 AG3 T14
    VCC1_5_B[49] VSS[057] VSS[163]
    47mA 11mA AJ4 1 2 0_0402_5% 0.1U_0402_16V4Z +3VS AG6 T15
    VCCHDA R740 VSS[058] VSS[164]
    1 AG9 T16
    R389 0.1U_0402_16V4Z VSS[059] VSS[165]
    11mA AJ3 1 2 0_0402_5% +3VALW C474 AH12 T17
    VCCSUSHDA VSS[060] VSS[166]
    +1.5VS 1 2 AJ19 1 AH14 T23
    CHB1608U301_0603 VCCSATAPLL C475 VSS[061] VSS[167]
    AH17 B26
    1U_0603_10V4Z

    2 VSS[062] VSS[168]
    AC8 AH19 U12
    10U_0805_10V4Z

    VCCSUS1_05[1] T65 VSS[063] VSS[169]


    1 1 +1.5VS AC16 F17 AH2 U13
    VCC1_5_A[01] VCCSUS1_05[2] T66 2 VSS[064] VSS[170]
    C476

    C477

    AD15 AH22 U14


    0316 change design VCC1_5_A[02] VSS[065] VSS[171]
    1 AD16 AH25 U15
    C478 VCC1_5_A[03] VSS[066] VSS[172]
    AE15 AD8 VCCSUS1_5_ICH_1 AH28 U16
    2 2 VCC1_5_A[04] VCCSUS1_5[1] T67 VSS[067] VSS[173]
    ARX

    AF15 AH5 U17


    1U_0603_10V4Z VCC1_5_A[05] VCCSUS1_5_ICH_2 VSS[068] VSS[174]
    AG15 F18 AH8 AD23
    2 VCC1_5_A[06] VCCSUS1_5[2] T68 +3VALW VSS[069] VSS[175]
    AH15 AJ12 U26
    VCC1_5_A[07] VSS[070] VSS[176]
    AJ15 AJ14 U27
    VCC1_5_A[08] 0.1U_0402_16V4Z VSS[071] VSS[177]
    A18 AJ17 U3
    VCCSUS3_3[01] VSS[072] VSS[178]

    0.1U_0402_16V4Z
    AC11
    VCC1_5_A[09]
    212mA VCCSUS3_3[02]
    D16 1 1 AJ8
    VSS[073] VSS[179]
    V1
    VCCPSUS

    AD11 D17 B11 V13


    VCC1_5_A[10] VCCSUS3_3[03] VSS[074] VSS[180]

    C479

    C480
    AE11 E22 B14 V15
    +1.5VS VCC1_5_A[11] VCCSUS3_3[04] VSS[075] VSS[181]
    AF11 B17 V23
    VCC1_5_A[12] 2 2 VSS[076] VSS[182]
    ATX

    1 AG10 B2 V28
    C481 VCC1_5_A[13] VSS[077] VSS[183]
    AG11 B20 V29
    B VCC1_5_A[14] VSS[078] VSS[184] B
    AH10 B23 V4
    1U_0603_10V4Z VCC1_5_A[15] VSS[079] VSS[185]
    AJ10 AF1 B5 V5
    2 VCC1_5_A[16] VCCSUS3_3[05] VSS[080] VSS[186]
    B8 W26
    VSS[081] VSS[187]
    AC9 1342mA
    VCC1_5_A[17]
    C26
    VSS[082] VSS[188]
    W27
    C27 W3
    VSS[083] VSS[189]
    AC18 E11 Y1
    VCC1_5_A[18] VSS[084] VSS[190]
    AC19 E14 Y28
    VCC1_5_A[19] VSS[085] VSS[191]
    T1 E18 Y29
    VCCSUS3_3[06] VSS[086] VSS[192]
    AC21 T2 E2 Y4
    VCC1_5_A[20] VCCSUS3_3[07] VSS[087] VSS[193]
    T3 E21 Y5
    VCCSUS3_3[08] +3VALW VSS[088] VSS[194]
    +1.5VS G10 T4 E24 AG28
    VCC1_5_A[21] VCCSUS3_3[09] VSS[089] VSS[195]
    G9 T5 E5 AH6
    VCC1_5_A[22] VCCSUS3_3[10] VSS[090] VSS[196]
    1 11mA 11mA T6 E8 AF2
    C483 VCCSUS3_3[11] VSS[091] VSS[197]
    +1.5VS AC12 U6 1 F16 B25
    VCCPUSB

    VCC1_5_A[23] VCCSUS3_3[12] C482 VSS[092] VSS[198]


    1 AC13 U7 F28
    0.1U_0402_16V4Z C484 VCC1_5_A[24] VCCSUS3_3[13] VSS[093]
    AC14 V6 F29
    2 VCC1_5_A[25] VCCSUS3_3[14] 4.7U_0603_6.3V6M VSS[094]
    V7 G12
    0.1U_0402_16V4Z VCCSUS3_3[15] 2 VSS[095]
    AJ5 W6 G14 A1
    2 VCCUSBPLL VCCSUS3_3[16] VSS[096] VSS_NCTF[01]
    W7 G18 A2
    VCCSUS3_3[17] VSS[097] VSS_NCTF[02]
    USB CORE

    AA7 Y6 G21 A28


    VCC1_5_A[26] VCCSUS3_3[18] VSS[098] VSS_NCTF[03]
    AB6 Y7 G24 A29
    VCC1_5_A[27] VCCSUS3_3[19] VSS[099] VSS_NCTF[04]
    AB7 T7 G26 AH1
    VCC1_5_A[28] VCCSUS3_3[20] VSS[100] VSS_NCTF[05]
    AC6 G27 AH29
    VCC1_5_A[29] VSS[101] VSS_NCTF[06]
    AC7 G8 AJ1
    VCC1_5_A[30] VSS[102] VSS_NCTF[07]
    H2 AJ2
    T69 VCC_LAN1_05_INT_ICH_1 VSS[103] VSS_NCTF[08]
    A10 H23 AJ28
    T70 VCC_LAN1_05_INT_ICH_2 VCCLAN1_05[1] VCCCL1_05_ICH VSS[104] VSS_NCTF[09]
    A11 G22 H28 AJ29
    +3VS VCCLAN1_05[2] VCCCL1_05 T71 VSS[105] VSS_NCTF[10]
    G23 H29 B1
    VCCCL1_5 VSS[106] VSS_NCTF[11]
    A12 B29
    VCCLAN3_3[1] VSS_NCTF[12]
    B12 19/78/78mA 19/73/73mA
    VCCLAN3_3[2]
    1 23mA A24 +3VS 1 @
    0.1U_0402_16V4Z

    C485 R390 CHB1608U301_0603 VCCCL3_3[1] C486 ICH9-M ES_FCBGA676


    B24
    VCCCL3_3[2]
    GLAN POWER

    A 1 2 A27 1U_0603_10V4Z A
    R391 4.7U_0805_10V4Z VCCGLANPLL
    +1.5VS 80mA
    2 2
    1 2 D28
    10U_0805_10V4Z

    +1.5VS
    2.2U_0603_6.3V4Z

    VCCGLAN1_5[1]
    D29
    CHB1608U301_0603 VCCGLAN1_5[2]
    1 1 E26
    C487 C488 VCCGLAN1_5[3]
    1 E27
    VCCGLAN1_5[4]
    1mA
    A26
    2 2
    0316 change design
    C489
    2
    +3VS VCCGLAN3_3
    ICH9-M ES_FCBGA676
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    ICH9(4/4)_POWER&GND
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 28 of 51
    5 4 3 2 1
    5 4 3 2 1

    HDD Connector JP3


    +5VS Pleace near HD CONN
    1
    GND SATA_TXP0
    2 SATA_TXP0 26
    A+ SATA_TXN0
    3

    10U_0805_10V4Z

    0.1U_0402_16V4Z
    A- SATA_TXN0 26
    1 1 1 1 4 0.01U_0402_16V7K
    GND SATA_RXN0 1 C494 SATA_RXN0_C

    C490

    C493
    5 2 SATA_RXN0_C 26
    C491 C492 B- SATA_RXP0
    6 2 1 C495 SATA_RXP0_C SATA_RXP0_C 26
    B+ 0.01U_0402_16V7K
    7
    D 2 2 2 2 GND D
    0.1U_0402_16V4Z 0.1U_0402_16V4Z Near CONN side.
    8
    V33 +3VS
    9
    V33
    10
    V33
    11
    GND
    12
    GND
    13
    GND
    14
    V5 +5VS
    15
    V5
    16
    V5
    17
    GND
    18
    Reserved
    19
    GND
    20
    V12
    21
    V12
    22
    V12

    SUYIN_127072FR022G523_RV
    CONN@

    CD-ROM Connector
    +5VS JP5
    Placea caps. near ODD
    CONN. GND
    13
    C 12 SATA_TXP4 C
    A+ SATA_TXP4 26
    11 SATA_TXN4
    A- SATA_TXN4 26
    10 0.01U_0402_16V7K
    GND SATA_RXN4
    9 2 1 C510 SATA_RXN4_C SATA_RXN4_C 26
    0.1U_0402_16V4Z B-

    1U_0603_10V4Z

    10U_0805_10V4Z
    8 SATA_RXP4 2 1 C511 SATA_RXP4_C
    B+ SATA_RXP4_C 26
    1 1 1 1 7 0.01U_0402_16V7K
    GND
    C512

    Near CONN side.


    C513

    C514
    C515
    10U_0805_10V4Z 6
    2 2 2 2 DP
    5
    V5
    4 +5VS
    V5
    3
    MD
    2
    GND
    1
    GND

    SUYIN_127382FR013GX09ZR
    CONN@

    Multi Bay Connector


    JP12
    +5VS
    B B
    Placea caps. near ODD GND
    1
    SATA_TXP1
    2 SATA_TXP1 26
    CONN. TX+ SATA_TXN1
    3 SATA_TXN1 26
    TX-
    4
    GND SATA_RXN1 C822 2
    5 1 0.01U_0402_16V7K SATA_RXN1_C
    SATA_RXN1_C 26
    RX- SATA_RXP1 C823 2 SATA_RXP1_C
    6 1 0.01U_0402_16V7K SATA_RXP1_C 26
    RX+
    0.1U_0402_16V4Z

    1U_0603_10V4Z

    10U_0805_10V4Z

    7 MultiBay@
    GND
    1 1 1 1 8 MultiBay@
    GND
    C517

    9
    GND Near CONN side.
    C518

    C519

    C516 10
    10U_0805_10V4Z GND
    11
    2 2 2 2 VCC3 +5VS
    12
    VCC3
    13
    VCC3
    14
    VCC5
    15
    VCC5
    16
    MultiBay@ MultiBay@ MultiBay@ MultiBay@ VCC5

    JAE_WM2M016JPA

    CONN@

    A A

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    HDD & CDROM

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 29 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    +3V_LAN
    C1403 +3V_LAN +3VALW
    2 1
    R1106
    +3V_LAN 0.1U_0402_16V4Z @ 0_1206_5% Turn off power when S3. 06/14

    1
    1K_0402_5%

    1K_0402_5%
    1 2
    R1107 10K_0402_5%
    CLKREQ#_9

    R1108

    R1109
    2 1
    R1110 10K_0402_5%
    2 1 ICH_PCIE_WAKE# U43 AP2305GN Q106

    2
    R1111 10K_0402_5% 1 8
    LAN_LOM_DIS A0 VCC
    2 1 2 7 1 3

    S
    D
    A1 WP LAN_EE_CLK
    3 6
    NC SCL LAN_EE_DATA
    4 5
    D GND SDA D

    G
    2
    CAT24C08WI-GT3 SO 8P <BOM Structure> 38 LAN_POWER_OFF

    +3V_LAN
    U44
    1 1 1 1 1
    CLKREQ#_9 42 LED 59 LAN_ACT#
    17 CLKREQ#_9 CLKREQn LED_ACTn
    27 GLAN_RXP 0.1U_0402_16V4Z 2 1 C1404PCIE_RXP2_LAN 49 60 C1406 C1407 C1408 C1409 C1410
    TX_P LED_LINK10/100n
    27 GLAN_RXN 0.1U_0402_16V4Z 2 1 C1405PCIE_RXN2_LAN 50 62 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    TX_N LED_LINK1000n LANLINK_STATUS# 2 2 2 2 2
    27 GLAN_TXP 54 PCI-E 63
    RX_P LED_DUPLEXn
    27 GLAN_TXN 53
    ICH_PCIE_WAKE# RX_N
    27,31 ICH_PCIE_WAKE# 6 46
    WAKEn TEST TESTMODE +3V_LAN
    17 CLK_PCIE_LAN 55
    R1112 0_0402_5% REFCLKP
    17 CLK_PCIE_LAN# 56 8
    REFCLKN AVDDH V1.8_LAN
    9,20,25,31,32 PLT_RST# 1 2 5
    PERSTn
    19
    LAN_MDI0+ AVDD 0.1U_0402_16V4Z V1.8_LAN
    17
    MDIP0 POWER AVDD
    22
    LAN_MDI0- 18 23
    LAN_MDI1+ MDIN0 AVDD
    20 & 28 1 1 1 1 1 1 1 1
    LAN_MDI1- MDIP1 AVDD +3V_LAN
    21
    LAN_MDI2+ MDIN1 C1411 C1412 C1413 C1414 C1415 C1416 C1417 C1418
    26
    MDIP2 Media GROUND VDDO_TTL
    1
    LAN_MDI2- 27 40 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    LAN_MDI3+ MDIN2 VDDO_TTL 2 2 2 2 2 2 2 2
    30 45
    LAN_MDI3- MDIP3 VDDO_TTL
    31 61
    MDIN3 VDDO_TTL V1.2_LAN
    LAN_EE_CLK 38 2
    LAN_EE_DATA VPD_CLK VDD
    41 EEPROM 7
    VPD_DATA VDD
    13
    VDD V1.2_LAN
    34 33
    SPI_DO VDD
    35 39
    SPI_DI FLASH VDD
    37 44 1 1 1 1 1 1
    C SPI_CLK MEMORY VDD C
    36 48
    SPI_CS VDD C1419 C1420 C1421 C1422 C1423 C1424
    58
    LAN_X1 VDD 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    15 65
    LAN_X2 XTALI CLOCK VSS V1.8_LAN 2 2 2 2 2 2
    14
    +3VS +3V_LAN XTALO
    32
    LAN_LOM_DIS NC
    10 51
    LOM_DISABLEn NC
    12 52
    VAUX_AVLBL NC
    11 57
    SWITCH_VCC NC
    47 64
    +3V_LAN R1113 4.99K_0402_1% VMAIN_AVLBL No Connect NC V1.2_LAN
    9
    16
    SWITCH_VAUX
    RSET Reserved
    24 for power saving
    CTRL18 4 Analog 25 1 1 1
    4.7U_0805_10V4Z C1425 R1114 4.7K_0402_5% CTRL12 CTRL18 Reserved
    3 29
    CTRL12 Reserved C1426 C1427 C1428
    2 1 2 1 43
    Reserved 0.1U_0402_16V4Z 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    3

    Q107 2 2 2
    88E8072_QFN64
    1 CTRL12

    V1.2_LAN 2SB1188T100R_SC62-3 CONN@


    2

    C1431 27P_0402_50V8J JRJ45


    22U_0805_6.3VAM C1430 1 2 +3V_LAN R1115 2 1 300_0402_5% 13
    Yellow LED+
    2 1
    2

    LAN_ACT# 14
    Yellow LED-
    16
    +3V_LAN Y6 RJ45_MIDI3- SHLD1
    40 RJ45_MIDI3- 8
    25MHZ_20P_1BG25000CK1A PR4-
    9
    RJ45_MIDI3+ DETECT PIN1
    40 RJ45_MIDI3+ 7
    4.7U_0805_10V4Z C1432 R1116 4.7K_0402_5% LAN_X1 C1433 27P_0402_50V8J PR4+
    1

    2 1 2 1 LAN_X2 1 2 40 RJ45_MIDI1- RJ45_MIDI1- 6


    PR2-
    3

    B Q108 RJ45_MIDI2- B
    5
    7/31 40 RJ45_MIDI2- PR3-
    1 CTRL18 40 RJ45_MIDI2+ RJ45_MIDI2+ 4
    PR3+
    40 RJ45_MIDI1+ RJ45_MIDI1+ 3
    2SB1188T100R_SC62-3 PR2+
    V1.8_LAN
    2

    40 RJ45_MIDI0- RJ45_MIDI0- 2
    4.7U_0805_6.3V6K C1434 PR1-
    10
    RJ45_MIDI0+ DETCET PIN2
    2 1 40 RJ45_MIDI0+ 1
    PR1+
    15
    R1117 2 SHLD1
    +3V_LAN 1 300_0402_5% 11
    Green LED+
    LANLINK_STATUS# 12
    Green LED-
    V1.8_LAN FOX_JM36113-P1122-7F

    T72

    2 1 TRM_CT 1 24 2 R1118 1
    C1435 LAN_MDI3+ TCT1 MCT1 RJ45_MIDI3+ 75_0402_1% LAN_ACT# LANLINK_STATUS#
    2 23
    0.1U_0402_16V4Z LAN_MDI3- TD1+ MX1+ RJ45_MIDI3-
    3 22
    TD1- MX1-
    2 2
    2 1 TRM_CT 4 21 2 R1119 1
    C1436 LAN_MDI2+ TCT2 MCT2 RJ45_MIDI2+ 75_0402_1% @ C1437 @ C1438
    5 20
    0.1U_0402_16V4Z LAN_MDI2- TD2+ MX2+ RJ45_MIDI2-
    6 19 300p_0402_25V 300p_0402_25V
    TD2- MX2- 1 1
    2 1 TRM_CT 7 18 2 R1120 1
    C1439 LAN_MDI1+ TCT3 MCT3 RJ45_MIDI1+ 75_0402_1%
    8 17
    0.1U_0402_16V4Z LAN_MDI1- TD3+ MX3+ RJ45_MIDI1-
    9 16
    TD3- MX3- C1441
    2 1 TRM_CT 10 15 2 R1121 1 1 2
    A C1440 LAN_MDI0+ TCT4 MCT4 RJ45_MIDI0+ 75_0402_1% A
    11 14
    0.1U_0402_16V4Z LAN_MDI0- TD4+ MX4+ RJ45_MIDI0- 1000P_1808_3KV7K
    12
    TD4- MX4-
    13 1115 EMI REQUEST

    0.5u_GST5009
    <BOM Structure>
    Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    LAN-88E8072
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-3821P 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 30 of 51
    5 4 3 2 1
    A B C D E

    Mini Card 0--TV tuner/WWAN/Robson Mini Card 2---WLAN +1.5VS_WLAN


    +3VS_WLAN +3VALW
    0.01U_0402_16V7K 4.7U_0805_10V4Z

    +3VALW SIM card Connector +3VS_WWAN 0.1U_0402_16V4Z


    1 1 1 1

    0.1U_0402_16V4Z
    0.01U_0402_16V7K 4.7U_0805_10V4Z 1 1 C568 C569 C570 C571
    +3VS_WWAN C566 C567

    JP4 2 2 2 2
    1 1 1 2 2
    1 C573 C574 C575 1
    0.1U_0402_16V4Z

    C572 UIM_PWR 1 4.7U_0805_10V4Z 0.1U_0402_16V4Z


    2
    1 UIM_DATA 2 1
    3
    2 2 2 UIM_CLK 3
    4
    2 UIM_RST 4
    5
    0.1U_0402_16V4Z UIM_VPP 5
    6 8
    +3VS_WWAN 6 G1
    7 9
    CONN@ 7 G2
    JP6 +1.5VS_WLAN ACES_88266-07001 CONN@
    ICH_PCIE_WAKE# 1 2 JP7
    CH_DATA 1 2 ICH_PCIE_WAKE#
    3 4 1 2 +3VS_WLAN
    CH_CLK 3 4 CH_DATA 1 2
    5 6 36 CH_DATA 3 4
    CLKREQ#_10 5 6 UIM_PWR CH_CLK 3 4
    17 CLKREQ#_10 7 8 36 CH_CLK 5 6 +1.5VS_WLAN
    7 8 UIM_DATA CLKREQ#_6 5 6 R699 0_0402_5% DEBUG@
    9 10 17 CLKREQ#_6 7 8 1 2 LPC_FRAME# 26,37,38
    9 10 UIM_CLK 7 8 R700 0_0402_5% DEBUG@
    17 CLK_PCIE_MCARD0# 11 12 9 10 1 2 LPC_AD3 26,37,38
    11 12 UIM_RST CLK_PCIE_MCARD2# 9 10 R701 0_0402_5% DEBUG@
    17 CLK_PCIE_MCARD0 13 14 17 CLK_PCIE_MCARD2# 11 12 1 2 LPC_AD2 26,37,38
    13 14 UIM_VPP CLK_PCIE_MCARD2 11 12 R702 0_0402_5% DEBUG@
    15 16 17 CLK_PCIE_MCARD2 13 14 1 2 LPC_AD1 26,37,38
    15 16 13 14 R703 0_0402_5% DEBUG@
    17 18 15 16 1 2 LPC_AD0 26,37,38
    17 18 M_WXMIT_OFF# PLT_RST# 15 16
    19 20 17 18
    0_0402_5% 19 20 PLT_RST# R704 17 18
    21 22 17 CLK_DEBUG_PORT_1 1 2 0_0402_5% DEBUG@ 19 20 XMIT_OFF#
    21 22 19 20
    27 PCIE_RXN1 1 R419 2 PCIE_C_RXN1 23 24 @R420
    @R420 1 2 0_0402_5% +3VALW 0_0402_5% 21 22 PLT_RST#
    23 24 21 22
    27 PCIE_RXP1 1 R421 2 PCIE_C_RXP1 25 26 R422 1 2 0_0402_5% +3VS_WWAN 27 PCIE_RXN3 R423 1 2 PCIE_C_RXN3 23 24 R424 1 2 0_0402_5% +3VALW
    0_0402_5% 25 26 R425 1 PCIE_C_RXP3 23 24 @ R426 1
    27 28 +1.5VS_WLAN 27 PCIE_RXP3 2 25 26 2 0_0402_5% +3VS
    27 28 ICH_SMBCLK 0_0402_5% 25 26
    29 30 27 28 +1.5VS_WLAN
    PCIE_TXN1 29 30 ICH_SMBDATA 27 28 ICH_SMBCLK
    27 PCIE_TXN1 31 32 29 30
    PCIE_TXP1 31 32 PCIE_TXN3 29 30 ICH_SMBDATA
    27 PCIE_TXP1 33 34 27 PCIE_TXN3 31 32
    33 34 PCIE_TXP3 31 32
    35 36 USB20_N8 27 27 PCIE_TXP3 33 34
    R427 0_0603_5% 35 36 33 34
    37 38 USB20_P8 27 35 36 USB20_N5 27
    37 38 35 36
    +3VS_WWAN 1 2 39 40 37 38 USB20_P5 27
    39 40 37 38
    1 2 41 42 39 40
    R428 0_0603_5% 41 42 39 40
    43 44 +3VS_WLAN 41 42
    43 44 +3VS_WWAN 41 42
    45 46 43 44 WL_LED# 39
    45 46 43 44
    47 48 +1.5VS_WLAN 45 46
    47 48 45 46
    49 50 47 48 +1.5VS_WLAN
    2 49 50 47K_0402_5% 47 48 2
    51 52 +3VS_WWAN 49 50
    51 52 @ R440 49 50
    147K_0402_5%
    2 UIM_PWR 51 52 +3VS_WLAN
    @ R441 UIM_DATA 51 52
    53 54 1 2
    GND1 GND2
    53 54
    GND1 GND2 +3VALW
    0821 Change +3VS to +3VS_WWAN FOX_AS0B226-S40N-7F +1.5VS R431 1 2 0_1206_5% +1.5VS_WLAN
    FOX_AS0B226-S40N-7F
    +3VS_WWAN +3VALW
    0811 Pins 37 and 43 connect to GND and remove +1.5VS

    1
    D11 +3VS R432 1 2 0_1206_5% +3VS_WLAN @
    1 2 M_WXMIT_OFF# R418 @ R433 R434
    27 WXMIT_OFF#
    1 2 18P_0402_50V8J 10K_0402_5% 100K_0402_5%
    CH751H-40_SC76 0_1206_5%

    2
    UIM_CLK XMIT_OFF#
    1

    1
    AP2305GN Q115 C585 D @
    @ 2 Q10
    27 XMIT_OFF
    1 3 G 2N7002_SOT23-3
    S
    D

    2
    S

    3
    G
    2

    38 WWAN_POWER_OFF R435
    1 2
    0_0402_5%
    @

    Near to Express Card slot.


    3
    New Card +3VS_PEC 3
    CONN@
    Express Card Power Switch JEXP1 4.7U_0805_10V4Z
    +1.5VS Close to
    C576
    1 2 0.1U_0402_16V4Z U16 R436 JEXP 2 0_0402_5%
    1 USB10-
    1
    2
    GND 1 1
    27 USB20_N9 USB_D-
    12 11 +1.5VS_PEC R437 1 2 0_0402_5% USB10+ 3 C577 C578
    +3VS 1.5Vin 1.5Vout 27 USB20_P9 USB_D+
    14 13 CPUSB# 4
    1.5Vin 1.5Vout CPUSB# 2 2
    5
    RSV 0.1U_0402_16V4Z
    6
    C579 1 RSV
    2 0.1U_0402_16V4Z 2 3 +3VS_PEC 17,21,27,37 ICH_SMBCLK
    ICH_SMBCLK 7
    3.3Vin 3.3Vout ICH_SMBDATA SMB_CLK
    4 5 17,21,27,37 ICH_SMBDATA 8
    C580 1 3.3Vin 3.3Vout SMB_DATA +1.5VS_PEC
    2 0.1U_0402_16V4Z +1.5VS_PEC 9
    R438 +1.5V
    +3VALW 17 15 +3V_PEC +1.5VS_PEC 10
    AUX_IN AUX_OUT PCIE_PME#_R +1.5V 4.7U_0805_10V4Z
    27,30 ICH_PCIE_WAKE# 1 2 11
    PLT_RST# 0_0402_5% WAKE#
    9,20,25,30,32 PLT_RST# 6 19 12 1 1
    SYSRST# OC# +3V_PEC PERST# +3.3VAUX
    13
    SYSON PERST# PERST# C581 C582
    38,39,41,47,50 SYSON 20 8 +3VS_PEC 14
    SHDN# PERST# +3.3V
    15
    SUSP# CLKREQ#_4 +3.3V 2 2
    33,38,41,44,46,47,48 SUSP# 1 16 17 CLKREQ#_4 16
    STBY# NC CPUSB# CLKREQ#
    17
    R439 1 CPPE#
    +3VALW 2 100K_0402_5% 10 7 17 CLK_PCIE_NCARD# 18 0.1U_0402_16V4Z
    CPPE# GND REFCLK-
    17 CLK_PCIE_NCARD 19
    EXP_CPPE# REFCLK+
    27 EXP_CPPE# 9 20
    CPUSB# GND
    27 PCIE_RXN4 21
    PERn0
    18 27 PCIE_RXP4 22
    RCLKEN PERp0 +3V_PEC
    23
    GND
    R5538D001-TR-F_QFN20_4X4~D 27 PCIE_TXN4 24
    PETn0 4.7U_0805_10V4Z
    27 PCIE_TXP4 25
    PETp0
    26
    internal pull high to 3.3Vaux-in GND
    1 1
    27
    4 EC need setting at Hi-Z & output Low 28
    GND
    GND
    C583 C584 4

    SANTA_131851-A_LT 2 2

    om
    0.1U_0402_16V4Z

    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    WLAN, WWAN, New Card

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 31 of 51

    x
    he
    A B C D E
    5 4 3 2 1

    +1.8VS_CR
    +3VS
    1 1 1 1
    R1042 1 2 4.7K_0402_5% XDCD0#_SDCD# C1326 C1329 +VCC_OUT +VCC_4IN1
    R1041 1 2 4.7K_0402_5% XDCD1#_MSCD# 10U_0805_10V4Z 0.1U_0402_16V4Z @ R1128
    2 2 C1327 2 C1328 2 0_0603_5%
    0.1U_0402_16V4Z 1000P_0402_50V7K 1 2
    D +VCC_4IN1 +3VS D

    1
    +3VS C1325
    R1044 2 1 10K_0402_5% XDWP#_SDWP# C1324 0.1U_0805_50V7M
    R1043 2 1 10K_0402_5% XD_RB# U36 1 10U_0805_10V4Z

    2
    2
    1 1
    3 5 C1336
    17 CLK_SRC11# APCLKN APVDD
    4 10 0.1U_0402_16V4Z C1334 C1335
    17 CLK_SRC11 APCLKP APV18 2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    9 30 2 2
    27 PCIE_TXN5 APRXN TAV33
    27 PCIE_TXP5 8 Use 0603 type and over 20
    +3VS APRXP
    R709 20
    DV33 +1.8VS_CR
    27 PCIE_RXN5
    C1321 2 1 0.1U_0402_16V4Z PCIE_C_RXN5 11
    APTXN DV33
    44 mils trace width on both side
    1 2 200K_0603_5% XD_CLE
    27 PCIE_RXP5
    C1322 2 1 0.1U_0402_16V4Z PCIE_C_RXP5 12 18
    APTXP DV18
    37
    R1047 DV18
    2 1 10K_0402_5% PREXT 7 1 1
    XD_RE# R1046 APREXT
    1 2 200K_0402_5% 48 XD_SD_MS_D0
    R1048 MDIO0
    XD_ALE 1 2 200K_0402_5% 47 XD_SD_MS_D1 C1332 C1333
    R972 MDIO1
    +3VS 1 2 10K_0402_5% XIN 38 46 XD_SD_MS_D2 0.1U_0402_16V4Z 0.1U_0402_16V4Z
    PCIES_EN MDIO2 XD_SD_MS_D3 2 2
    39 45
    +3VS PCIES JMB385 MDIO3
    MDIO4
    43 SDCMD_MSBS_XDWE#
    42 SDCLK_MSCLK_XDCE#
    MDIO5 XDWP#_SDWP#
    19 41
    REG_CTRL MDIO6 XD_CLE
    40
    MDIO7 XD_D4
    29
    XDCE# MDIO8 XD_D5
    2 1 2 1 1 28
    @ R706 @ C788 9,20,25,30,31 PLT_RST# XRSTN MDIO9 XD_D6 +VCC_4IN1
    2 27
    100_0402_5% 100P_0402_25V8K XTEST MDIO10 XD_D7
    26
    MDIO11 25 XD_RE# +VCC_OUT
    SDCLK 1 2 1 2 13
    MDIO12
    23 XD_RB# 40mil
    @ R707 @ C789 SEEDAT MDIO13 XD_ALE
    14 22
    100_0402_5% 100P_0402_25V8K SEECLK MDIO14
    C +3VS U37 C
    34
    MSCLK XDCD1#_MSCD# NC
    1 2 1 2 15 35
    @ R708 @ C790 XDCD0#_SDCD# CR1_CD1N NC
    16 36 3 1
    100_0402_5% 100P_0402_25V8K CR1_CD0N NC VIN VOUT
    4 5
    6 VIN/CE VOUT
    use for PWR_EN# APGND 1

    1
    +VCC_OUT 17 2 1
    CR1_PCTLN C1330 GND
    24
    GND 0.1U_0402_16V4Z RT9701CB_SOT25
    31
    R710 GND 2
    SDCLK_MSCLK_XDCE# 1 2 22_0402_5% SDCLK CR_LED# 21 32 @ R1050
    R711 CR1_LEDN GND C1331 2
    1 2 22_0402_5% MSCLK 8mA sink current 33 150K_0402_5%

    2
    R712 GND
    1 2 22_0402_5% XDCE# 1U_0603_10V4Z

    JMB385-LGEZ0A_LQFP48_7X7
    reserved power circuit
    D42
    Layout must add a thermal pad pin49
    XDCD1#_MSCD# 2
    1 1 XD_CD#
    XDCD0#_SDCD# 3
    C1047
    DAN202U_SC70 270P_0402_50V7K
    2

    +1.8VS_CR +1.8VS

    Card Reader Connector


    U35
    +VCC_4IN1 33 23 +VCC_4IN1 R705 1 2
    XD-VCC SD-VCC 0_0805_5%
    14
    B XD_SD_MS_D0 8 MS-VCC B
    White LED: VF=3V, IF = 5mA, Res = 56ohm XD_SD_MS_D1 9
    XD-D0
    4 IN 1 CONN 24 SDCLK
    XD_SD_MS_D2 26 XD-D1 SD_CLK 25 XD_SD_MS_D0
    +5VALW_LED XD_SD_MS_D3 XD-D2 SD-DAT0 XD_SD_MS_D1
    27 29
    XD_D4 28 XD-D3 SD-DAT1 10 XD_SD_MS_D2
    XD_D5 XD-D4 SD-DAT2 XD_SD_MS_D3
    30 11
    XD-D5 SD-DAT3
    1

    XD_D6 31 12 SDCMD_MSBS_XDWE#
    XD_D7 32 XD-D6 SD-CMD 36 XDCD0#_SDCD#
    R719 XD-D7 SD-CD-SW
    56_0402_5% SDCMD_MSBS_XDWE# 6 35 XDWP#_SDWP#
    XDWP#_SDWP# XD-WE SD-WP-SW
    7
    2

    XD_ALE XD-WP
    5
    XD_CD# XD-ALE MSCLK
    34 15
    XD-CD MS-SCLK
    2

    XD_RB# 1 19 XD_SD_MS_D0
    D15 XD_RE# XD-R/B MS-DATA0 XD_SD_MS_D1
    2 20
    XDCE# XD-RE MS-DATA1 XD_SD_MS_D2
    S1-023459_AQUA-WHITE_0603 3 18
    XD_CLE XD-CE MS-DATA2 XD_SD_MS_D3
    4 16
    XD-CLE MS-DATA3 17 XDCD1#_MSCD#
    MS-INS SDCMD_MSBS_XDWE#
    13 21
    3 1

    22 4IN1 GND MS-BS


    47K 4IN1 GND
    Q103

    10K 2 CR_LED# 37
    38 4IN1 GND
    DTA114YKAT146_SOT23-3 4IN1 GND
    TAITW_R015-312-LM
    CONN@
    1

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    USB CardReader&CONN
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
    Custom Montevina Consumer Discrtet 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 32 of 51
    5 4 3 2 1
    A B C D E

    0212_Change to +5VALW.
    CODEC POWER
    +3VS_HDA +3VS +VDDA_CODEC
    +3VDD_CODEC +VDDA_CODEC_R
    W=40Mil +5VALW (4.75V)
    R1051 R1052 R1053 U39
    300mA

    2.2U_0805_16V4Z
    1 2 +3VS 1 2 1 2 +VDDA_CODEC C1341 1 2 1 5
    BLM18BD601SN1D_0603 BLM18BD601SN1D_0603 0_0603_5% 0.1U_0402_16V4Z VIN OUT

    1U_0603_10V4Z
    1

    0.1U_0402_16V4Z

    0.1U_0402_16V4Z
    0.1U_0402_16V4Z
    1 1 1 1 2

    1U_0603_10V4Z
    GND

    C1342

    C1343
    1
    1 3 4 1
    31,38,41,44,46,47,48 SUSP# SHDN# BP 2
    2 2 2 2 GMT_G9191-475T1U_SOT23-5

    C1337

    C1338

    C1339

    C1340
    2 1
    C1344
    0208_Change SLP_S3# to SUSP#.
    0.1U_0402_16V4Z
    2

    U38

    +3VDD_CODEC 9 47 EAPD_CODEC
    DVDD_CORE* EAPD/ SPDIF OUT 0 or 1 / GPIO 0 EAPD_CODEC 38
    1 2 DMIC_DAT 19
    DVDD_CORE VOL_UP/DMIC_0/GPIO 1
    4
    VOL_DN/DMIC_1/GPIO 2
    +VDDA_CODEC_R 25
    AVDD1*
    30
    GPIO 3
    38
    AVDD2**
    31
    VREFOUT-E / GPIO 4
    +3VS_HDA 3 43
    DVDD_IO GPIO 5
    32 44
    MONO_OUT GPIO 6
    45
    2 HDA_BITCLK_CODEC SPDIF OUT1 / GPIO 7 2
    21,26 HDA_BITCLK_CODEC 6
    HDA_BITCLK_CODEC BITCLK SPDIF_OUT
    48 SPDIF_OUT 21,40
    HDA_SDOUT_CODEC SPDIF OUT0
    26 HDA_SDOUT_CODEC 5
    SDO
    1

    @
    R1054 R1055 1 2 33_0402_5% 8
    26 HDA_SDIN0 SDI_CODEC
    47_0402_5% 28 VREFOUT_B
    VREFOUT-B VREFOUT_B 35
    HDA_SYNC_CODEC 10
    21,26 HDA_SYNC_CODEC SYNC +VDDA_CODEC_R
    29
    2

    HDA_RST#_CODEC VREFOUT-C
    1 21,26 HDA_RST#_CODEC 11
    @ RESET# R1056 1 2 5.1K_0402_1%
    C1345 R1057 1 2 20K_0402_1% EXTMIC_DET# 35
    33P_0402_50V8K R1058 22_0402_5% 13 SENSE R1059 1 2 39.2K_0402_1% JACK_DET# 35,40
    2 SENSE_A R683
    19 DMIC_CLK 1 2 46 1 2 10K_0402_1% INTMIC_DET# 35
    DMIC_CLK C1346 0.1U_0402_16V4Z
    1 2
    R1060 1 2 47K_0402_5% C1347 2 1 33 41 HP_OUTR
    27 SB_SPKR CAP2 PORTA_R HP_OUTR 35
    1U_0603_10V4Z HP Jack & Dock
    R1061 1 2 10K_0402_5% 1 2 MONO_INR 12 39 HP_OUTL
    PCBEEP PORTA_L HP_OUTL 35
    C1348 0.1U_0402_16V4Z
    C1349 1 2 0.1U_0402_16V4Z
    22 MIC_EXTR 1 2
    PORTB_R MIC_EXT_R 35
    @ C1358 40 C1350 1U_0603_10V6K Jack MIC
    R1062 1 NC / OTP
    1 2 +VDDA_CODEC_R 2 5.1K_0402_1% 21 MIC_EXTL 1 2 MIC_EXT_L 35
    0.1U_0402_16V4Z R1063 1 PORTB_L
    40 SENSE_B# 2 39.2K_0402_1% SENSEB# 34 C1351 1U_0603_10V6K 1 2 MIC_IN_R 35
    SENSE_B / NC C1352 1U_0603_10V6K
    1

    1
    @ C1359 37 24 MIC_INR
    C1353 NC PORTC_R @ R1064
    1 2
    0.1U_0402_16V4Z 0.1U_0402_16V4Z 18 23 MIC_INL 0_0603_5% Internal MIC
    2 NC PORTC_L
    @ C1360 19 C1354 1U_0603_10V6K

    2
    NC LINE_OUT_R
    1 2 36 LINE_OUT_R 35 1 2 MIC_IN_L 35
    0.1U_0402_16V4Z PORTD_R
    20
    NC LINE_OUT_L
    35 LINE_OUT_L Internal
    35 SPKR.
    3 @ C1361 C1355 PORTD_L 3
    1 2 10U_0805_10V4Z
    0.1U_0402_16V4Z 1 2 VC_REFA 27 15 DOCK_MICR 1 2
    VREFFILT PORTE_R DOCK_MIC_R 40
    C1356 1U_0603_10V6K DOCK MIC
    R1067 26 14 DOCK_MICL 1 2
    AVSS1* PORTE_L DOCK_MIC_L 40
    1 2 C1357 1U_0603_10V6K
    0_1206_5% 42
    AVSS2**
    17
    R1065 PORTF_R
    7
    DVSS**
    1 2 16
    0_1206_5% PORTF_L

    R1066
    1 2 92HD71B7X5NLGXA1X8_QFN48_7X7
    GNDA 35,40
    0_1206_5%

    GND GNDA

    SENSE A SENSE B

    Port Resistor Port Resistor

    4
    A 39.2K E 39.2K 4

    om
    B 20K F 20K

    l.c
    ai
    C 10K G 10K Security Classification Compal Secret Data

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    Codec_IDT9271B7

    @
    D 5.11K H 5.11K THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer UMA 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 33 of 51

    x
    he
    A B C D E
    5 4 3 2 1

    D
    MDC 1.5 Conn. D

    JP8 1 2 +1.5VS
    R475 0_0603_5%
    1 2 @1 2 +3VS
    HDA_SDOUT_MDC GND1 RES0 R476 0_0603_5%
    26 HDA_SDOUT_MDC 3 4
    IAC_SDATA_OUT RES1
    5 6 +3VS
    HDA_SYNC_MDC GND2 3.3V +3VS
    26 HDA_SYNC_MDC 7 8
    IAC_SYNC GND3
    26 HDA_SDIN1 1 2 HDA_SDIN1_MDC 9 10
    R477 33_0402_5% IAC_SDATA_IN GND4
    26 HDA_RST#_MDC 11 12 HDA_BITCLK_MDC 26
    IAC_RESET# IAC_BITCLK

    C619

    C620

    @C621
    C621
    2 1 1 2

    1000P_0402_50V7K

    0.1U_0402_16V4Z

    4.7U_0805_10V4Z
    @ R478 @ C618

    GND
    GND
    GND
    GND
    GND
    GND
    1 1 1

    @
    10_0402_5% 10P_0402_25V8K

    ACES_88018-124G

    13
    14
    15
    16
    17
    18
    2 2 2

    Connector for MDC Rev1.5

    C C

    B B

    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    MDC 1.5 & Robson
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 34 of 51
    5 4 3 2 1
    A B C D E

    +5VAMP +5VS
    R1133
    9/21 follow 14" AMD 0.1U_0402_16V4Z 1 2 SPEAKER
    0_1206_5%
    1 1 1 SP02000D000 S W-CONN ACES 85204-04001 4P P1.25
    C1477 C1478 C1479 JP60
    SPKL+ R1102 1 2 0_0603_5% 1
    10U_0805_10V4Z SPKL- R1103 0_0603_5% 1
    1 2 2
    2 2 2 SPKR+ R1104 0_0603_5% 2
    1 2 3
    +5VS SPKR- R1105 0_0603_5% 3
    1 2 4
    0.1U_0402_16V4Z 4
    5

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J

    100P_0402_50V8J
    1 G1 1
    10 dB 1 1 1 1 6
    G2
    C1375 C1376 C1377 C1378 ACES_85204-04001
    CONN@

    16
    15
    6

    2
    U40 2 2 2 2

    VDD
    PVDD1
    PVDD2
    R1134 @ R1135
    100K_0402_5% 100K_0402_5% @ D55 D56 @
    PSOT24C_SOT23-3 PSOT24C_SOT23-3

    2
    C1480 1 2 0.47U_0603_16V7K 7 2

    1
    RIN+ GAIN0
    1 2
    C1481 47P_0402_50V8J 3
    R1136 GAIN1

    1
    2 1 C1482 1 2 0.47U_0603_16V7K 17
    33 LINE_OUT_R RIN- SPKR+
    1 2 18
    20K_0402_5% C1483 47P_0402_50V8J ROUT+ @ R1137 R1138 8/31EMI request
    100K_0402_5%
    14 SPKR-

    2
    C1484 ROUT-
    1 2 0.47U_0603_16V7K 9
    LIN+ 100K_0402_5%
    1 2
    C1485 47P_0402_50V8J 4 SPKL+
    R1139 LOUT+
    2 1 C1486 1 2 0.47U_0603_16V7K 5
    33 LINE_OUT_L LIN- SPKL-
    1 2 8
    20K_0402_5% C1487 47P_0402_50V8J LOUT-

    12
    NC

    THERMAL PAD
    10 Keep 10 mil width
    EC_MUTE# BYPASS
    19
    2 38 EC_MUTE# SHUTDOWN
    1
    Audio/B & CIR 2

    GND1
    GND2
    GND3
    GND4
    C1488 10U_0805_10V4Z JP49
    2 MIC_EXT_R 1
    MIC_EXT_L 1
    2

    20
    13
    11
    1

    21
    2
    3
    TPA6017A2_TSSOP20 HP_OUT_R 3
    4
    HP_OUT_L 4
    5
    5
    6
    EXTMIC_DET# 6
    33 EXTMIC_DET# 7
    HP_DET# 7
    8
    8
    9
    9
    10
    CIR_IN 10
    38,40 CIR_IN 11
    11
    +5VL 12
    12
    13
    13
    14
    14
    ACES_87213-1400G
    CONN@
    33,40 JACK_DET#
    B+
    +3VALW
    Q49
    1

    D 2N7002_SOT23-3
    2

    2 R678
    R676 G 330K_0402_5%
    10K_0402_5% S
    3

    2
    1

    3 3
    +VDDA_CODEC
    R1077 C1379
    +VDDA_CODEC 0_0402_5% 1U_0603_10V4Z INTMIC IN
    1

    D Q50 2 1 1 2
    1

    2
    HP_DET# 2 D 2N7002_SOT23-3

    1
    G 2 R951
    2N7002_SOT23-3 S G R1078 R1079 10K_0402_5%
    3

    Q114 4.7K_0402_5% 4.7K_0402_5%


    S
    HP OUT
    3

    Q47

    1
    2N7002_SOT23-3 JP51

    2
    2
    G

    1
    1
    33 MIC_IN_L 2
    DOCK_LOUT_R 2
    33 HP_OUTR 1 3 DOCK_LOUT_R 40 33 MIC_IN_R 3
    3
    4
    D

    S
    2

    4
    G

    2 1
    HP OUT For Docking +3VS
    R681 10K_0402_5% 5
    GND1
    1 3 DOCK_LOUT_L 38 ANA_MIC_DET 6
    33 HP_OUTL DOCK_LOUT_L 40 GND2
    R684
    D

    Q48 33 VREFOUT_B 2 1 C787 1 2 ACES_88231-04001


    2N7002_SOT23-3 0_0402_5% 33 INTMIC_DET# CONN@

    1
    1U_0603_10V4Z D
    1

    1
    D Q109 2
    R685 R686 Q110 2 2N7002_SOT23-3 G
    C785 HP_OUT_R
    +

    1 2 G S

    3
    4.7K_0402_5% 4.7K_0402_5% 2N7002_SOT23-3 S

    3
    100U_D2_6.3VM
    2

    C786 HP_OUT_L HP OUT For M/B


    +

    1 2
    33 MIC_EXT_R MIC_EXT_R
    100U_D2_6.3VM
    33 MIC_EXT_L MIC_EXT_L EXTMIC IN
    4 4

    om
    l.c
    ai
    Security Classification Compal Secret Data

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    AMP & Audio Jack

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 35 of 51

    x
    he
    A B C D E
    5 4 3 2 1

    Left side ESATA/USB combination Connector


    +5VALW

    USB_VCCC
    U41
    USB_VCCC
    1
    GND OUT
    8 W=60mils
    2 7 JP53
    D IN OUT USB D
    3 6 1

    1000P_0402_50V7K
    1

    150U_D_6.3VM

    0.1U_0402_16V4Z
    IN OUT B_VCC
    1 4 5 1 1 2
    C1381 EN# OC# + 27 USB20_N2 B_D-

    C1380

    C1382

    C1383
    3
    TPS2061IDGNR_MSOP8 27 USB20_P2 B_D+
    4
    B_GND
    2 2 2 2
    5
    USB_EN# SATA_TXP5 GND
    26 SATA_TXP5 6
    SATA_TXN5 A+ ESATA
    26 SATA_TXN5 7
    4.7U_0805_10V4Z A-
    8
    GND
    26 SATA_RXN5_C
    C1385 2 1 0.01U_0402_16V7K SATA_RXN5 9
    C1384 2 B-
    26 SATA_RXP5_C 1 0.01U_0402_16V7K SATA_RXP5 10
    R1083 B+
    1 2 10K_0402_5% +5VALW 11
    GND
    TYCO_1759576-1
    CONN@

    D46
    4 2 SATA_TXP5
    20070921 remove invter +5VALW VIN IO1
    SATA_TXN5 3 1
    IO2 GND
    @ PRTR5V0U2X_SOT143-4

    C
    USB cable connector for Right side C

    JP55
    +5VALW 1
    1
    2
    2
    3
    USB_EN# 3
    4
    4
    27 USB20_N0 5
    5
    27 USB20_P0 6
    6
    7
    7
    27 USB20_N1 8
    8
    27 USB20_P1 9
    9
    10
    10

    11
    GND1
    12
    GND2
    ACES_87213-1000G
    BT Connector Need change to New version
    JP57
    1 +3VAUX_BT
    1
    2
    B 2 USB20_P6_R R1084 B
    3 2 1 0_0402_5% USB20_P6 27
    3 USB20_N6_R R1085
    4 2 1 0_0402_5% USB20_N6 27
    4
    5 BT_LED 39
    5 @ R1086 1 1K_0402_5%
    6 2 CH_DATA 31
    6 @ R1087 1 1K_0402_5%
    7 2 CH_CLK 31
    Finger printer 7
    8
    GND1
    8
    9 0612 no install
    10 D47
    GND2
    ACES_88231-08001 +5VALW 4 2 USB20_P6_R
    VIN IO1
    USB20_N6_R 3 1
    IO2 GND
    @ PRTR5V0U2X_SOT143-4
    R627 1 2 0_0603_5%
    @ Q31 SI2301BDS_SOT23
    20070209 Add for FPR +3VS
    @ R628 +3VALW +3VAUX_BT
    S

    3 1 1 2 Q105 SI2301BDS_SOT23
    D

    +3VALW
    1 0_0603_5%
    0.1U_0402_16V4Z

    S
    C756 3 1

    D
    0.1U_0402_16V4Z
    G
    2

    38 USB_EN#

    1
    2 JP24

    G
    1 1 1 1

    2
    1 C1386 R1090 C1387 C1388 C1389
    R634 1 USB20_N7_R 1
    27 USB20_N7 2 0_0402_5% 2
    R635 1 2
    27 USB20_P7 2 0_0402_5% USB20_P7_R 3 1U_0603_10V4Z 100K_0402_5%
    3 2 2 2 2
    4

    2
    4
    2

    5 0.01U_0402_16V7K 4.7U_0805_10V4Z
    GND1
    6
    D30 @ GND2 R1092 C1390
    A PACDN042_SOT23-3~D ACES_88231-04001 1 2 1 2 A
    27 BT_OFF
    47K_0402_5% 0.1U_0402_16V4Z
    1

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    USB, BT, eSATA
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 36 of 51
    5 4 3 2 1
    5 4 3 2 1

    LPC Debug
    +3VL +3VL SPI ROM
    +3VL CONN@
    Port Change from +3VL to +3VS. 6/9

    1
    1 U27
    C711 20mils 8 4 Removed +3VS. 6/13
    R552 VCC VSS
    1
    0.1U_0402_16V4Z 100K_0402_5% C712 3
    2 U28 0.1U_0402_16V4Z W

    2
    8 1 7 B+
    VCC A0 2 HOLD
    7 2
    WP A1 SPI_FSEL# CONN@
    38,43 SMB_EC_CK1 6 3 38 FSEL# 1 2 1
    D SCL A2 R553 0_0402_5% S JP18 D
    38,43 SMB_EC_DA1 5 4
    SDA GND SPI_CLK_R
    38 SPI_CLK 1 2 6 1
    AT24C16AN-10SI-2.7_SO8 R554 0_0402_5% C Ground
    17 CLK_DEBUG_PORT_0 2
    SPI_FWR# SPI_SO FRD# LPC_PCI_CLK
    38 FWR# 1 2 5 2 1 2 FRD# 38 3
    R556 0_0402_5% D Q R555 0_0402_5% Ground
    26,31,38 LPC_FRAME# 4
    WIESON G6179 8P SPI LPC_FRAME#
    5
    +V3S

    1
    SP07000F500 S SOCKET WIESON G6179-100000 8P SPIFLASH 25,38 PCI_RST# 6
    LPC_RESET#
    R557 7
    100K_0402_5%
    WIESO_G6179-100000_8P +V3S
    26,31,38 LPC_AD0 8
    LPC_AD0
    26,31,38 LPC_AD1 9
    LPC_AD1
    26,31,38 LPC_AD2 10

    2
    &U1 LPC_AD2
    26,31,38 LPC_AD3 11
    LPC_AD3
    12
    ON/OFFBTNLED# VCC_3VA
    13
    PWR_LED#
    14
    CAPS_LED#
    45level 15
    NUM_LED#
    VCC1PWRGD 16
    45@ SPI_CLK_JP52 VCC1_PWRGD
    SST25LF080B_SO8-200mil Connect pin3 & 23 17
    SPI_CLK
    SPI_CS#_JP52 18
    together and pin 24 SPI_SI_JP52 SPI_CS#
    19
    SPI_SO_JP52 SPI_SI
    20
    to GND in 6/29. SPI_HOLD#_0 21
    SPI_SO
    SPI_HOLD#
    22
    Reserved
    23
    Reserved
    24
    Reserved

    ACES_87216-2404_24P

    C C

    SPI_CLK 1 2 SPI_CLK_JP52
    DEBUG@ R558 0_0402_5%

    FSEL# 1 2 SPI_CS#_JP52
    DEBUG@ R559 0_0402_5%

    +3VALW FWR# 1 2 SPI_SI_JP52


    Acceleromter R561 1 HOLD#
    DEBUG@ R560 0_0402_5%

    SPI_HOLD#_0
    2 1 2
    3.3K_0402_5% DEBUG@ R562 0_0402_5%
    +3VS +3VS_ACL +3VS_ACL_IO FRD# 1 2 SPI_SO_JP52
    DEBUG@ R563 0_0402_5%
    D23 R564
    0_0603_5% ON/OFFBTN_LED# 1 2 ON/OFFBTNLED#
    38,39 ON/OFFBTN_LED# DEBUG@ R565 0_0402_5%
    2 1 1 2

    CH751H-40PT_SOD323-2 VCC1_PWRGD 1 2 VCC1PWRGD


    38 VCC1_PWRGD DEBUG@ R566 0_0402_5%

    U29 +3VS_ACL

    25 ACCEL_INT 1 16
    INT/RDY GND R567
    0_0402_5%
    2 15 1 2
    SDD RES
    B B

    17,21,27,31 ICH_SMBDATA 3 14
    SDA/SDI/SPC GND

    4 13 +3VS_ACL
    +3VS_ACL_IO VDD_IO VDD R568
    0_0402_5%
    17,21,27,31 ICH_SMBCLK 5 12 1 2
    SCL/SPC RES

    2 1 6 11
    10U_0805_6.3V6M

    +3VS_ACL
    0.1U_0402_16V4Z

    R569 10K_0402_5% CS VDD R570


    C713

    C714

    0_0402_5% 1 1
    7 10 1 2 +3VS_ACL_IO
    NC RES

    8 9 2 2
    CK GND
    1

    R571
    0_0402_5% LIS3LV02DL-TR _LGA16

    L Must be placed in the center of the system.


    2

    A A

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    BIOS ROM

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 37 of 51

    x
    he
    5 4 3 2 1
    +3VL_EC

    0.1U_0402_16V4Z 0.1U_0402_16V4Z 1000P_0402_50V7K


    1 1 1 1 1
    C715 C716 C717 C718 C719 +3VL +3VL_EC +EC_AVCC

    2 2 2 2 2 R572
    0.1U_0402_16V4Z 1000P_0402_50V7K 1 2
    0_0805_5%
    For EMI

    111
    125
    +5VL +3VS 100P_0402_50V8J @ C1442

    22
    33
    96

    67
    9
    U30 KSI7 1 2
    SMB_EC_DA1 R573 1 2 4.7K_0402_5% 100P_0402_50V8J @ C1443

    VCC
    VCC
    VCC
    VCC
    VCC
    VCC

    AVCC
    SMB_EC_CK1 R577 1 2 4.7K_0402_5% KSI0 1 2
    SMB_EC_DA2 R574 1 2 4.7K_0402_5%
    SMB_EC_CK2 R575 1 2 4.7K_0402_5% 100P_0402_50V8J @ C1444
    CLKRUN# R724 1 2 8.2K_0402_5% GATEA20 1 21 INV_PWM KSO13 1 2
    26 GATEA20 GA20/GPIO00 INVT_PWM/PWM1/GPIO0F INV_PWM 19
    KB_RST# 2 23 FAN_PWM 100P_0402_50V8J @ C1445
    26 KB_RST# KBRST#/GPIO01 BEEP#/PWM2/GPIO10 FAN_PWM 6
    SIRQ 3 26 LAN_POWER_OFF KSO14 1 2
    27 SIRQ SERIRQ# FANPWM1/GPIO12 LAN_POWER_OFF 30
    @ @ LPC_FRAME# 4 27 ACOFF 100P_0402_50V8J @ C1446
    26,31,37 LPC_FRAME# LFRAME# ACOFF/FANPWM2/GPIO13 ACOFF 44
    C722 R576 26,31,37 LPC_AD3 LPC_AD3 5 0.01U_0402_16V7K KSO15 1 2
    LPC_AD2 LAD3 C720 ECAGND
    1 2 1 2 26,31,37 LPC_AD2 7
    LAD2 PWM Output 1 2
    33_0402_5%26,31,37 LPC_AD1 LPC_AD1 8 63 BATT_TEMP
    LAD1 BATT_TEMP/AD0/GPIO38 BATT_TEMP 43
    15P_0402_50V8J LPC_AD0 BATT_OVP
    LAD0 LPC & MISC
    26,31,37 LPC_AD0 10 64 BATT_OVP 43
    BATT_OVP/AD1/GPIO39 ADP_I 100P_0402_50V8J @ C1448
    65 ADP_I 44
    CLK_PCI_EC ADP_I/AD2/GPIO3A ADP_ID KSO9
    17 CLK_PCI_EC 12
    PCICLK AD Input AD3/GPIO3B
    66 ADP_ID 43 1 2
    PCI_RST# 13 75 TP_BTN# 100P_0402_50V8J @ C1449
    25,37 PCI_RST# PCIRST#/GPIO05 AD4/GPIO42 TP_BTN# 39
    +3VL R578 1 2 ECRST# 37 76 ANA_MIC_DET KSO10 1 2
    ECRST# SELIO2#/AD5/GPIO43 ANA_MIC_DET 35
    47K_0402_5% 20 100P_0402_50V8J @ C1450
    27 EC_SCI# CLKRUN# SCI#/GPIO0E KSO11
    38 1 2
    CLKRUN#/GPIO1D DAC_BRIG 100P_0402_50V8J @ C1451
    68 DAC_BRIG 19
    C721 DAC_BRIG/DA0/GPIO3C VCTRL KSO12
    2 1 70 VCTRL 44 1 2
    EN_DFAN1/DA1/GPIO3D

    1
    0.1U_0402_16V4Z J1 DA Output 71 IREF
    KSI0 IREF/DA2/GPIO3E AC_SET IREF 44 100P_0402_50V8J @ C1452
    55 72
    JOPEN KSI1 KSI0/GPIO30 DA3/GPIO3F AC_SET 44 KSO6
    56 1 2

    2
    KSI2 KSI1/GPIO31 +5V 100P_0402_50V8J @ C1453
    57
    KSI3 KSI2/GPIO32 EC_MUTE# KSO3
    58 83 EC_MUTE# 35 1 2
    KSI4 KSI3/GPIO33 PSCLK1/GPIO4A USB_EN# R579 1
    59 84 USB_EN# 36 2 10K_0402_5% 100P_0402_50V8J @ C1454
    KSI5 KSI4/GPIO34 PSDAT1/GPIO4B I2C_INT R580 1
    60 85 I2C_INT 39 2 10K_0402_5% KSO7 1 2
    KSI6 KSI5/GPIO35 PSCLK2/GPIO4C MUTE_LED 100P_0402_50V8J @ C1455
    +3VL
    61
    KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D
    86 MUTE_LED 40
    SUSP# PCI_RST# +3VL KSI7 62 87 TP_CLK KSO8 1 2
    KSO0 KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E TP_DATA TP_CLK 39
    39 88
    KSO1 KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 39 100P_0402_50V8J @ C1456
    40
    KSO1/GPIO21
    1

    KSO2 41 Select SPI ROM or LPC ROM KSO4 1 2


    KSO2/GPIO22
    2

    R581 R713 KSO3 42 97 R582 1 2 4.7K_0402_5% 100P_0402_50V8J @ C1459


    KSO3/GPIO23 SDICS#/GPXOA00
    1

    100K_0402_5% 100K_0402_5% R721 KSO4 43 98 DOCK_VOL_UP# KSO0 1 2


    R583 @ KSO5 KSO4/GPIO24 SDICLK/GPXOA01 DOCK_VOL_DWN# DOCK_VOL_UP# 40
    KSO5/GPIO25 Int. K/B
    4.7K_0402_5% 44 99 DOCK_VOL_DWN# 40
    10K_0402_5% KSO6 SDIDO/GPXOA02
    45 109
    KSO6/GPIO26 Matrix
    2

    KSO7 SDIDI/GPXID0 100P_0402_50V8J @ C1458


    46 SPI Device Interface
    1

    KSO8 KSO7/GPIO27 KSO5


    47 1 2
    2

    KSO9 KSO8/GPIO28 FRD#


    48 119 FRD# 37
    KSO10 KSO9/GPIO29 SPIDI/RD# FWR# 100P_0402_50V8J @ C1460
    49 120 FWR# 37
    LID_SW# TP_BTN# KSO11 KSO10/GPIO2A SPIDO/WR# SPI_CLK KSI3
    50
    KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58
    126 SPI_CLK 37 1 2
    KSO12 51 128 FSEL# 100P_0402_50V8J @ C1461
    KSO12/GPIO2C SPICS# FSEL# 37 +3VL
    KSO13 52 @ KSI2 1 2
    KSO14 KSO13/GPIO2D R720
    53 1 2 10K_0402_5% 100P_0402_50V8J @ C1462
    KSO15 KSO14/GPIO2E CIR_IN KSO1
    54 73 CIR_IN 35,40 1 2
    KSO15/GPIO2F CIR_RX/GPIO40 VCC1_PWRGD 100P_0402_50V8J @ C1463
    81 74 VCC1_PWRGD 37
    KSO16/GPIO48 CIR_RLC_TX/GPIO41 FSTCHG KSO2
    82 89 FSTCHG 44 1 2
    KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 STD_ADP
    90 STD_ADP 44
    BATT_CHGI_LED#/GPIO52 CAPS_LED# 100P_0402_50V8J @ C1464
    91 CAPS_LED# 39
    +3VL SMB_EC_CK1 CAPS_LED#/GPIO53 BAT_LED# KSI5
    37,43 SMB_EC_CK1 77
    SCL1/GPIO44 GPIO BATT_LOW_LED#/GPIO54
    92 BAT_LED# 39 1 2
    SMB_EC_DA1 78 93 ON/OFFBTN_LED# 100P_0402_50V8J @ C1465
    37,43 SMB_EC_DA1 SDA1/GPIO45 SUSP_LED#/GPIO55 ON/OFFBTN_LED# 37,39
    SMB_EC_CK2 79 SM Bus 95 SYSON 9/21 add R for nvidia KSI1 1 2
    6,21 SMB_EC_CK2 SCL2/GPIO46 SYSON/GPIO56 SYSON 31,39,41,47,50
    SMB_EC_DA2 80 121 VR_ON 100P_0402_50V8J @ C1466
    6,21 SMB_EC_DA2 SDA2/GPIO47 VR_ON/XCLK32K/GPIO57 VR_ON 49
    2

    127 AC_IN KSI4 1 2


    R585 AC_IN/GPIO59 ENBKL 100P_0402_50V8J @ C1467
    2 1 2 1
    10K_0402_5% R586 10K_0402_5% R1132 10K_0402_5% KSI6 1 2
    SLP_S3# 6 100 EC_RSMRST#
    27 SLP_S3# PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXO03 EC_RSMRST# 27
    SLP_S5# 14 101 R588 1 2
    27 SLP_S5# EC_LID_OUT# 27
    1

    R589 EC_SMI# PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXO04 EC_ON 0_0402_5%


    27 EC_SMI# 15 102 EC_ON 45
    EC_PME# LID_SW# EC_SMI#/GPIO08 EC_ON/GPXO05 WL_BLUE_LED#
    1 2 39 LID_SW# 16 103 WL_BLUE_LED# 39
    25 PCI_PME# 0_0402_5% ESB_CLK_R LID_SW#/GPIO0A EC_SWI#/GPXO06 PM_PWROK
    17 104
    ESB_DAT_R SUSP#/GPIO0B ICH_PWROK/GPXO06 BKOFF# PM_PWROK 9,27
    18 GPO 105
    EC_PME# 19
    PBTN_OUT#/GPIO0C
    EC_PME#/GPIO0D GPIO
    BKOFF#/GPXO08
    WL_OFF#/GPXO09
    106 M_PWROK BKOFF#
    M_PWROK
    19
    9,27
    14" INT_KBD
    1 @ R591 2 0_0603_5% 25 107 TP_LED#
    9 TSATN#
    40 CONA#
    CONA# 28
    EC_THERM#/GPIO11
    FAN_SPEED1/FANFB1/GPIO14
    GPXO10
    GPXO11
    108 HDDHALT_LED# TP_LED#
    HDDHALT_LED#
    39
    39
    CONN.( TYPE "D"
    31 WWAN_POWER_OFF 29
    FANFB2/GPIO15
    R593
    1
    4.7K_0402_5%
    2
    UTX
    URX
    30
    31
    EC_TX/GPIO16
    110 DOCK_PWRON
    KB)
    +3VL EC_RX/GPIO17 PM_SLP_S4#/GPXID1 DOCK_PWRON 40 +3VL
    ON/OFFBTN 32 112 ENBKL
    39 ON/OFFBTN ON_OFF/GPIO18 ENBKL/GPXID2 ENBKL 21
    R592 DIM_LED 34 114 EAPD_CODEC JP19
    41 DIM_LED PWR_LED#/GPIO19 GPXID3 EAPD_CODEC 33
    1 2 PWRBTN_OUT# NUM_LED# 36 GPI 115 THERM_SCI# KSO15
    DOCK_SLP_BTN# 39 NUM_LED# NUMLED#/GPIO1A GPXID4 THERM_SCI# 21,27 1
    0_0402_5% 116 SUSP# KSO10
    C723 GPXID5 PWRBTN_OUT# SUSP# 31,33,41,44,46,47,48 D16 KSO11 2
    117 PWRBTN_OUT# 27
    15P_0402_50V8J GPXID6 NMI_DBG# ADP_ID KSO14 3
    118 1 2
    CRY2 GPXID7 KSO13 4
    1 2 122
    XCLK1 +3VL CH751H-40PT_SOD323-2 KSO12 5
    123 124
    XCLK0 V18R KSO3 6
    1
    AGND

    7
    1

    Y5 KSO6
    GND
    GND
    GND
    GND
    GND

    1
    @ C724 R714 KSO8 8
    3 4
    NC OUT R595 4.7U_0603_6.3V6K 10K_0402_5% KSO7 9
    20M_0402_5% KB926QFB0_LQFP128_14X14 2 KSO4 10
    2 1
    EC DEBUG port
    11
    24
    35
    94
    113

    69

    NC IN KSO2 11
    <BOM Structure>
    2

    32.768KHZ_12.5P_1TJS125DJ2A073 D14 KSI0 12


    For C

    2
    JP20 NMI_DBG# 13
    2 1 PCI_SERR# PCI_SERR# 25
    KSO1
    CRY1 Revision KSO5 14
    1 +5VL 1 2
    1 URX +3VL_EC +3VL CH751H-40PT_SOD323-2 KSI3 15
    2
    2 UTX C725 KSI2 16
    3
    3 17
    ECAGND

    4 15P_0402_50V8J KSO0
    1

    1
    4 R715 KSI5 18
    ACES_85205-0400 +EC_AVCC L30 10K_0402_5% KSI4 19
    CONN@ 0_0603_5% KSO9 20
    KSI6 21
    L31 D13 KSI7 22
    2

    2
    AC_IN ACIN KSI1 23
    1 2 1 2 2 1 ACIN 44,45
    C726 0.1U_0402_16V4Z 0_0603_5% 24
    CH751H-40PT_SOD323-2 ACES_85201-2405
    1 2 CONN@
    C791 100P_0402_50V8J
    @ R729 1 2 0_0402_5% SMB_EC_CK2
    @ R730
    Cypress Vendor
    1 2 0_0402_5% SMB_EC_DA2
    Recommend
    R731 1 2 0_0402_5% ESB_CLK_R ENE
    39
    39
    ESB_CLK
    ESB_DAT
    R732 1 2 0_0402_5% ESB_DAT_R Security Classification Compal Secret Data Compal Electronics, Inc.
    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    EC KB926/KB Conn.
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 38 of 51
    A B C D E

    System LED White Keyboard backlight Conn


    S1-023459_AQUA-WHITE_0603
    R1095
    Mini card LED
    D50 1 2 1 2
    38 CAPS_LED#
    470_0402_5%
    +5VALW_LED
    Cap lock +3VS
    WL_BLUE_LED# 38
    White Q112

    1
    S1-023459_AQUA-WHITE_0603 JP9 47K 2N7002_SOT23-3 D
    R1097 1 +5VALW_LED 2
    38 BAT_LED#
    D52 1 2 1 2 +5VALW Battery 1
    2
    2
    36 BT_LED
    G

    1
    1 5 3 2 10K S 1
    31 WL_LED#

    3
    470_0402_5% G1 3 R1126
    6 4
    Charge LED G2 4
    ACES_85201-04051
    +5VALW_LED
    100K_0402_5%

    S1-023462_AQUA-WHITE/AMBER R1098 Q111

    2
    White 470_0402_5% DTA114YKAT146_SOT23-3

    1
    D
    26 SATA_LED# 1 2 1 2 +5VALW_LED
    WL_LED 2 Q113
    G 2N7002_SOT23-3
    3 4 1 2 +5VALW_LED HDD LED S

    3
    38 HDDHALT_LED#

    1
    AMBER R728
    470_0402_5% R1127
    D53 100K_0402_5%

    White

    2
    S1-023459_AQUA-WHITE_0603
    R980
    ON/OFFBTN_LED# D17 1 2 1 2 +5VALW_LED System
    470_0402_5%
    Power LED TouchPAD ON/OFF LED
    +5VALW_LED
    TP ON/OFF
    Capacitor Sensor Conn

    1
    +5VALW_LED +3VL R609 R610
    200_0402_5% 820_0402_5%
    +5V

    2
    2 4.7K_0402_5% 2

    1
    +5VS
    White AMBER

    4
    R611
    1

    D54 @ 10K_0402_5%

    1
    R1099 R1100 S1-023462_AQUA-WHITE/AMBER
    4.7K_0402_5% R613 SW1

    2
    JP59 10K_0402_5% SMT1-05-A_4P
    On (TP_LED#=L)-> White
    1 3 1 TP_BTN# TP_BTN# 38
    Off (TP_LED#=H)-> Amber
    2

    3
    1
    2

    2
    2
    38 NUM_LED# 3 4 2
    3 TP_LED#_LIGHT
    38 ESB_CLK 4
    4
    38 ESB_DAT 5

    5
    6
    5
    38 I2C_INT 6
    6
    7
    7 Q25 Q26
    37,38 ON/OFFBTN_LED# 8
    8

    1
    D D
    38 ON/OFFBTN 9
    9 TP_LED#
    10 2 2 TP_LED# 38
    1

    10
    11 G G
    10K_0402_5% GND 2N7002_SOT23-3 2N7002_SOT23-3
    12 S S

    3
    R1101 GND
    ACES_85201-1005N
    CONN@
    2

    T/P Board T/P Power


    +5V +5VALW +5V
    Q23
    SI2301BDS-T1-E3_SOT23-3

    3 3

    S
    3 1

    D
    ON/OFF Button Connector 1 @

    1
    C729

    G
    2
    R612
    0.1U_0402_16V4Z 10K_0402_5%
    JP23 2
    1

    2
    +3VALW 1
    2 TP_CLK 38
    2
    5 3 TP_DATA 38
    JP10 G1 3
    6 4
    G2 4
    1
    1

    1
    ON/OFFBTN ACES_85201-04051 D
    2
    ON/OFFBTN_LED# 2 SYSON Q24
    3 5 CONN@ 1 1 31,38,41,47,50 SYSON 2
    3 G1 @ @ G 2N7002_SOT23-3
    4 6
    4 G2 C730 C731 S

    3
    ACES_85201-04051 100P_0402_50V8J 100P_0402_50V8J
    CONN@ 2 2

    TP_DATA
    TP_CLK
    3

    D28
    Reed Switch Connector PSOT24C_SOT23-3
    @
    1

    +3VALW
    4 JP11 4
    1
    1
    38 LID_SW# 2 4

    om
    2 G1
    3 5
    3 G2

    l.c
    ACES_85204-03001
    CONN@

    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    LED, TP,KBL,Cab sensor boar

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Monday, October 08, 2007 Sheet 39 of 51

    x
    he
    A B C D E
    Atlas/ Saturn Dock 2
    R1069

    0_0402_5%
    1
    +DOCKVIN JDOCK1
    R1068
    43 2 1
    43 0_0402_5%
    44
    44

    RED 40 39 NB_GND
    18 RED 40 39
    GREEN 38 37 TV_LUMA DOC_GNDA
    18 GREEN 38 37
    BLUE 36 35 TV_CRMA
    18 BLUE 36 35
    D_DDCDATA 34 33 TV_COMPS
    18 D_DDCDATA 34 33
    D_DDCCLK 32 31 VGA_GND DOC_GNDA
    18 D_DDCCLK 32 31
    D_HSYNC 30 29 CIR_IN
    18 D_HSYNC 30 29 CIR_IN 35,38
    D_VSYNC 28 27 DOCK_PWRON DOCK_PWRON 38
    18 D_VSYNC 28 27
    USB20_N3 26 25 MUTE_LED MUTE_LED 38
    27 USB20_N3 26 25
    USB20_P3 24 23 DOCK_SLP_BTN#
    27 USB20_P3 24 23 DOCK_SLP_BTN# 38
    NB_GND 22 21 JACK_DET#
    22 21 JACK_DET# 33,35
    RJ45_MIDI3- 20 19 R_VOL_UP# R617 1 2 200_0402_5% DOCK_VOL_UP# 38
    30 RJ45_MIDI3- 20 19
    RJ45_MIDI3+ 18 17 R_VOL_DWN# R618 1 2 200_0402_5% DOCK_VOL_DWN# 38
    30 RJ45_MIDI3+ 18 17
    RJ45_MIDI2- 16 15 SPDIFO_L
    30 RJ45_MIDI2- 16 15
    RJ45_MIDI2+ 14 13 AUDIO_OGND DOC_GNDA
    30 RJ45_MIDI2+ 14 13
    RJ45_MIDI1- 12 11 DOCK_LOUT_R DOCK_LOUT_R 35
    30 RJ45_MIDI1- 12 11
    RJ45_MIDI1+ 10 9 DOCK_LOUT_L DOCK_LOUT_L 35
    30 RJ45_MIDI1+ 10 9
    RJ45_MIDI0- 8 7 DOCK_MIC_R_C
    30 RJ45_MIDI0- 8 7
    RJ45_MIDI0+ 6 5 DOCK_MIC_L_C
    30 RJ45_MIDI0+ 6 5
    4 3 AUDIO_IGND DOC_GNDA
    +V_BATTERY 4 3 DOCK_PRESENT
    2 1
    2 1
    PJP3

    1
    B+ 1 2 41 R620
    41 2K_0402_5%
    42
    +3VALW 42
    PAD-OPEN 2x2m

    2
    +3VS_HDA
    2

    FOX_QL1122L-H212AR-7F
    R621
    10K_0402_5%
    need change to reverse type connector

    2
    R1140
    1

    33_0402_5%
    38 CONA#

    1 1
    1

    C
    DOCK_PRESENT Q27 D R1141
    2
    B MMBT3904_NL_SOT23-3 Q116 2 1 2 SPDIF_OUT 21,33
    E 2N7002_SOT23-3 G 220_0402_5%
    3
    1

    1 S

    3
    C739 R623 NB_GND

    1
    100N_0402_50V7M 2K_0402_5% DOCK_LOUT_R 1
    0720 Add dock_present_gnd DOCK_LOUT_L SPDIFO_L 1 2 C1489
    2 R1142 R1143
    1 1
    2

    0815 change 0_0603_5% 220P_0402_25V8J 110_0402_5%

    220P_0402_50V7K

    220P_0402_50V7K
    2

    2
    dock_present_gnd to NB_GND

    C740

    C741
    2 2

    DOC_GNDA DOC_GNDA
    TV-out
    20 TV_LUMA
    TV_LUMA
    R_VOL_UP# R_VOL_DWN#
    MIC_Dock
    1 1
    TV_CRMA
    20 TV_CRMA
    C744 C745
    TV_COMPS 1000P_0402_50V7K 1000P_0402_50V7K
    20 TV_COMPS 2 2 Need 600 Ohm 500 mA

    L36
    1

    R629 R630 R631 C746 1U_0603_10V6K FBM-11-160808-601-T_0603


    150_0402_1%

    150_0402_1%

    150_0402_1%

    33 DOCK_MIC_R 1 2 1 2 DOCK_MIC_R_C

    33 DOCK_MIC_L 1 2 1 2 DOCK_MIC_L_C
    L37
    2

    +DOCKVIN C753 1U_0603_10V6K FBM-11-160808-601-T_0603 1 1


    C755
    C754
    220P_0402_50V7K 2 2 220P_0402_50V7K
    +3VS
    1
    C734 DOC_GNDA DOC_GNDA
    1000P_0402_50V7K
    2 10K_0402_5%
    SENSE_B# 33

    2
    R625

    1
    R626 D

    1
    10K_0402_5% 2 Q29
    G 2N7002_SOT23-3

    1
    C S

    3
    2
    MMBT3904_NL_SOT23-3 B

    1
    R632 C E Q30

    3
    DOCK_MIC_L_C 1 2 2 Q32
    10K_0402_5% B MMBT3904_NL_SOT23-3

    2
    2 E

    3
    C757
    R633
    47K_0402_5% 1

    1
    1U_0603_10V6K

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    DOCK CONN.
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 40 of 51
    5 4 3 2 1

    +5VALW to +5VS Transfer +3VALW to +3VS Transfer DIM LED


    +5VALW +5VALW_LED
    +5VALW +5VS B+ +3VALW +3VS Q33
    SI2301BDS-T1-E3_SOT23-3
    B+ U32 U33

    S
    10U_0805_10V4Z 10U_0805_10V4Z

    D
    8 1 8 1 3 1
    D S D S

    1
    1 7 2 1 7 2
    C760 D S R649 C759 D S
    6 3 6 3 1
    1

    1
    D S D S C758
    5 4 5 4

    G
    1 1 1 1

    2
    D R636 10U_0805_10V4Z D G C761 C762 330K_0402_5% 10U_0805_10V4Z D G C763 C764 R637 0.1U_0402_16V4Z D
    2 AO4466_SO8 2 AO4466_SO8 10K_0402_5%

    2
    330K_0402_5% 2
    2 2 2 2
    2

    2
    RUNON_3VS

    1
    RUNON 0.1U_0402_16V4Z
    R648
    1 0.1U_0402_16V4Z 470_0402_5%

    1
    R638 D

    1
    @ SUSP 2 Q45 D
    470_0402_5%

    2
    1

    D G 2N7002_SOT23-3 DIM_LED 2 Q35


    38 DIM_LED
    SUSP 2 Q34 S 1 G 2N7002_SOT23-3
    2

    3
    G 2N7002_SOT23-3 C769 S

    3
    S 1
    3

    C765 0.01U_0402_16V7K
    2
    <BOM Structure>
    @ 0.01U_0402_16V7K
    2

    +1.8V to +1.8VS Transfer


    +1.8V +1.8VS

    B+ U34 +3VL +3VL


    8 1 10U_0805_10V4Z
    D S
    1 7 2
    D S

    1
    C C766 6 3 C
    D S
    1

    5 4 1 1 R639 R640
    R651 10U_0805_10V4Z D G C767 C768
    2 AO4466_SO8 100K_0402_5% 100K_0402_5%
    330K_0402_5%

    2
    2 2 SYSON# SUSP
    48 SYSON# SUSP 48
    2

    RUNON_1.8VS

    1
    D D
    1

    0.1U_0402_16V4Z SYSON 2 2 SUSP#


    31,38,39,47,50 SYSON SUSP# 31,33,38,44,46,47,48
    R650 G G
    10K_0402_5% Q36 S S Q37

    3
    1

    D 2N7002_SOT23-3 2N7002_SOT23-3
    SUSP 2 Q46
    2

    G 2N7002_SOT23-3
    S 1
    3

    C770

    1U_0402_6.3V6K
    2

    Discharge circuit H1
    HOLEA
    H2
    HOLEA
    H3
    HOLEA
    H4
    HOLEA
    H5
    HOLEA
    H6
    HOLEA
    H7
    HOLEA
    H8
    HOLEA
    H9
    HOLEA
    H10
    HOLEA

    +5VS +3VS +1.8V +1.5VS +VCCP +0.9V +1.8VS

    1
    B B
    1

    1
    R641 R642 R643 R644 R645 R646 R647 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20
    HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEC HOLEC
    470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5% 470_0402_5%
    2

    1
    1

    1
    D Q38 D Q39 D Q40 D Q41 D Q42 D Q43 D Q44
    SUSP 2 SUSP 2 SYSON# 2 SUSP 2 SUSP 2 SUSP 2 SUSP 2
    G G G G G G G
    S S S S S S S
    3

    3
    2N7002_SOT23-3 2N7002_SOT23-3 2N7002_SOT23-3 2N7002_SOT23-3 2N7002_SOT23-3 2N7002_SOT23-3 2N7002_SOT23-3
    FM1 FM2 FM3 FM4
    1 1 1 1

    A A

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    DC/DC Interface

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 41 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    +3VS +5VS_HDMI

    @
    @ @ @

    2
    R1039 R1033 +3VS R1034
    D 2.2K_0402_5% R1040 D
    2.2K_0402_5%
    Q101 6.8K_0402_5% 6.8K_0402_5%

    2
    G
    2

    1
    2N7002_SOT23-3
    3 1 HDMIDAT
    21 HDMIDAT_VGA

    D
    1 2
    0_0402_5% R1023
    @
    +3VS

    2
    G
    2N7002_SOT23-3
    Q102
    3 1 HDMICLK
    21 HDMICLK_VGA

    D
    1 2
    0_0402_5% R1024
    @

    C C

    L70
    HDMI_CLK- 1 2 HDMI_R_CLK-
    21 HDMI_CLK- 1 2

    HDMI_CLK+ 4 3 HDMI_R_CLK+
    21 HDMI_CLK+ 4 3
    WCM-2012-900T_0805
    D41 +5VS

    RB411D T146 _SOT23-3


    HDMI Connector

    2
    +5VS_HDMI
    9/21 change R1036 and
    R1035 from 10K to 2.2K
    for nvidia

    1
    L71 +5VS_HDMI
    HDMI_TX0- 1 2 HDMI_R_TX0-
    21 HDMI_TX0- 1 2
    1
    B R1036 R1035 B
    HDMI_TX0+ 4 3 HDMI_R_TX0+ 0.1U_0402_16V4Z

    2.2K_0402_5%

    2.2K_0402_5%
    21 HDMI_TX0+ 4 3 Need to check A51 team circuit

    2
    C1247
    WCM-2012-900T_0805 2

    @
    R1037 L74 JP48

    1
    HDMI_DETECT 1 2 1 2 19
    21 HDMI_DETECT 1K_0402_1% HP_DET
    18
    +5V
    1

    1 FBML10160808121LMT_0603 1 17
    HDMIDAT DDC/CEC_GND
    16
    D40 R1038 HDMICLK SDA
    15
    L72 SKS10-04AT_TSMA 10K_0402_1% C1248 SCL
    14
    HDMI_TX1- HDMI_R_TX1- 330P_0402_50V7K 2 Reserved
    21 HDMI_TX1- 1 2 13
    2

    1 2 HDMI_R_CLK- CEC
    12 20
    CK- GND
    11 21
    HDMI_TX1+ HDMI_R_TX1+ HDMI_R_CLK+ CK_shield GND
    21 HDMI_TX1+ 4 3 10 22
    4 3 HDMI_R_TX0- CK+ GND
    9 23
    WCM-2012-900T_0805 D0- GND
    8
    HDMI_R_TX0+ D0_shield
    7
    HDMI_R_TX1- D0+
    6
    D1-
    5
    HDMI_R_TX1+ D1_shield
    9/21 remove ESD Cap. 4
    D1+
    HDMI_R_TX2- 3
    D2-
    2
    HDMI_R_TX2+ D2_shield
    1
    D2+
    L73 CONN@SUYIN_100042MR019SX53ZL
    HDMI_TX2- 1 2 HDMI_R_TX2-
    21 HDMI_TX2- 1 2

    A 21 HDMI_TX2+
    HDMI_TX2+ 4
    4 3
    3 HDMI_R_TX2+ HDMI ESD A
    WCM-2012-900T_0805

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2007/09/26 Deciphered Date 2007/09/26 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    HDMI LS & Conn.
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 42 of 51
    5 4 3 2 1
    A B C D

    +3VALW

    PQ3

    3
    TP0610K-T1-E3_SOT23-3

    BATT
    1
    2 AC_LED 47 1

    340K_0402_1%
    PR1 1
    +5VALW
    ADP_ID 41

    0.01U_0402_25V7K
    2 1

    2
    1

    1
    PC1
    PR8

    499K_0402_1%
    PR4 1
    100_0402_5% PR2
    10K_0402_5%
    VIN +DOCKVIN

    2
    1

    2
    ACES_88334-057N
    ADP_SIGNAL 1 2

    8
    5 PR3 PR5
    5 @10K_0402_5% 10K_0402_5%
    4 3

    P
    4 PL1 PL2 +
    3
    3
    0
    1 2 1 BATT_OVP <40>
    2 SMB3025500YA_2P SMB3025500YA_2P 2
    2 -

    G
    ADPIN

    105K_0402_1%
    1 1 2 2 1
    1

    PR6 1
    0.01U_0402_25V7K

    4
    1
    PJP1 PU1A

    PC6
    LM358ADT_SO8
    100P_0402_50V8J

    1000P_0402_50V7K

    2
    2

    PD1

    100P_0402_50V8J

    2
    1

    1
    PC5
    PC4
    PC3
    2

    2
    PC2

    1000P_0402_50V7K
    PJSOT24C_SOT23-3
    1

    2 2

    VMB
    PL3 BATT
    PJP2 HCB2012KF-121T50_0805
    1 1 2
    1 PL4
    2
    2
    3 EC_SMD PD2 HCB2012KF-121T50_0805
    PH1 under CPU botten side :
    3 EC_SMC @SM05_SOT23
    4
    4
    5 3
    1 2 CPU thermal protection at 90 +-3 degree C
    5
    1

    6
    6
    7 2
    1 Recovery at 47 +-3 degree C
    7 PC9
    8 PC8
    2

    8 1000P_0402_50V7K 0.01U_0402_50V4Z PR7


    9
    GND +5VS
    10 47K_0402_1%
    GND
    3

    1 2
    3 SUYIN_200275MR008GXOLZR CPU 3
    1
    1

    1
    PD3
    1

    PR14 @SM24.TC_SOT23-3 PH1


    PR13 100_0402_5% 10K_TH11-3H103FT_0603_1%
    100_0402_5%
    2

    ENTRIP1 <47>
    2

    2
    +3VL SMB_EC_DA1 PR10
    SMB_EC_DA1 <39,40>

    8
    15K_0402_1%

    1
    D
    1 2 1 2 5

    P
    SMB_EC_CK1 + PQ1
    PR9 SMB_EC_CK1 <39,40> 7 2
    0 G SSM3K7002FU_SC70-3
    10K_0402_5% +5VALW 1 2 6
    -

    G
    BAT_ID <46> PR11 PU1B S

    3
    1 150K_0402_1%

    4
    1

    1
    LM358ADT_SO8

    1
    PC10 PR12
    PR16
    +3VL 2.55K_0402_1% PR15
    6.49K_0402_1% 0.22U_0603_10V7K
    2

    1 2 150K_0402_1% PC11
    2

    2
    1000P_0402_50V7K ENTRIP2 <47>

    2
    1

    1
    PR17 D
    1K_0402_5% 2 PQ2
    G SSM3K7002FU_SC70-3
    2

    BATT_TEMP
    S

    3
    4 4

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

    ho
    DC Connector/CPU_OTP

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Size Document Number Rev

    nf
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

    x
    Date: Friday, October 05, 2007 Sheet 43 of 51

    he
    A B C D
    A B C D

    P4 B+

    BATT
    VIN P2
    PQ102
    AM4835EP-T1-PF_SO8

    PQ101 PQ103
    1 8
    1
    PR102 PL101 2 7 1
    AM4835EP-T1-PF_SO8 AM4835EP-T1-PF_SO8 0.012_2512_1% HCB2012KF-121T50_0805 3 6
    8 1 1 8 1 2 1 2 CHG_B+ 5
    7 2 2 7 PR103
    6 3 3 6 47K_0402_5%

    4
    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    5 5 1 2 1 2 VIN
    PR101

    1
    47P_0402_50V8J

    47K_0402_5% PR104 ACDET PC102

    1
    0_0402_5%

    0.1U_0603_25V7K

    PC103

    PC104

    PC105
    1 2 1U_0603_6.3V6M
    <40> AC_SET 1 2 ACSET

    2
    1

    3
    PR105
    PC101

    1
    10K_0402_5%

    0.22U_0603_16V7K

    PC108
    1

    1
    2

    2
    1
    PC109

    200K_0402_5%
    2 PC107 ACOFF#

    2
    1

    @0.01U_0402_16V7K @0.1U_0603_25V7K

    PC106

    PR106

    1
    CHG_B+

    2
    PR107 CHGEN# AC_LED PR139

    2
    47K_0402_1% PQ104 PR108 +3VLP 100K_0402_5%
    1 2 2 DTA144EUA_SC70-3 10_1206_5% 1 2
    1

    1
    1 2 2 ACOFF <40>

    1
    D

    LPREF

    ACSET

    ACDET

    ACP
    LPMD

    ACN

    CHGEN
    PQ105 29 PACIN 2
    TP

    5
    6
    7
    8
    DTC115EUA_SC70-3 PR110 PC110 G
    3

    PQ107 0_0402_5% 1U_0805_25V6K S PQ114

    3
    1

    SSM3K7002FU_SC70-3 D PR109<32,34,40,43,48,49,50> SSM3K7002FU_SC70-3 PQ106


    SUSP# 1 2 8 28 1 2
    150K_0402_5% IADSLP PVCC PC111 DTC115EUA_SC70-3
    2
    G 0.1U_0402_10V7K PQ108

    2
    S 9 27 BST_CHG 1 2 4 AO4466_SO8
    3

    AGND BTST
    PC112 BQ24740VREF PU101
    1 2 10
    VREF
    BQ24740RHDR_QFN28_5X5
    HIDRV
    26 DH_CHG
    PL102 PR112
    BATT

    3
    2
    1
    PR111 PQ109 1U_0603_6.3V6M +3VL 10U_LF919AS-100M-P3_4.5A_20% 0.015_1206_1%
    1

    3K_0402_1% D LX_CHG
    11 25 1 2 1 2
    PACIN SSM3K7002FU_SC70-3 VDAC PH
    1 2 2

    1
    G PD102

    5
    6
    7
    8
    S PR113 VADJ 12 24 REGN 2 1
    3

    143K_0402_1% VADJ REGN


    ACOFF# 1 2 PR114 RLS4148_LL34-2

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    2 2

    @0_0402_5% 13 23 DL_CHG
    2
    EXTPWR LODRV

    1
    PD101 VCTRL 1 2 PQ110

    PC113

    PC114

    PC115

    PC116
    RLS4148_LL34-2 4 AO4466_SO8
    1

    14 22

    2
    ISYNSET PGND
    1

    DPMDET
    PC117 PR115 1 2

    IADAPT

    SRSET

    CELLS

    1
    1U_0603_10V6K 100K_0402_1% PC119

    SRN
    2

    3
    2
    1
    SRP
    BAT
    PR116
    2

    39K_0402_5% 1U_0603_10V6K PC118

    2
    0.1U_0402_10V7K

    15

    16

    17

    18

    19

    20

    21
    PR117
    100K_0402_5% BQ24740VREF

    IADAPT
    PR118 1 2
    Charge Detector

    1
    10K_0402_5%
    1 2 @47K_0402_5%
    <40> ADP_I

    1
    D PR119

    100P_0402_50V8J
    0.22U_0603_10V7K
    1

    1
    PQ111 2 BAT_ID <45>

    2
    SSM3K7002FU_SC70-3
    PC120

    PC121
    G
    S
    2

    3
    BATT

    0.1U_0603_25V7K

    @0.1U_0603_25V7K
    PR120
    2 1 IREF <40>

    PC122
    PC124
    133K_0402_1%

    1
    PC123
    1

    0.1U_0402_10V7K PR122

    2
    PR121 681K_0402_1%
    200K_0402_1% 1 2
    2

    PR123
    2

    1M_0402_5%
    3
    1 2 3

    P2 PR124
    BQ24740VREF VIN 1K_0402_5%
    VIN
    1 2
    1

    +3VL ACIN <40,47>

    1
    PR125
    47_1206_5% PR126
    1
    10K_0402_5%

    100K_0402_1% PR127
    VIN PR130 10K_0402_1%
    2

    8
    +3VL
    10K_0402_1%

    2.15K_0402_1% PU102B
    PR128

    2
    1 2 5

    P
    +
    1

    PR129

    7 PACIN
    2

    O
    1

    1
    100K_0402_5%

    PR131 6
    -

    G
    133K_0402_1% PC125 CHGEN#
    2

    1
    0.1U_0603_25V7K PC126 LM393DG_SO8
    PR132

    PR133
    2

    1
    0.047U_0402_16V7K
    10K_0603_0.1%
    2

    PR134
    2

    2
    1

    D PD103 10K_0402_5%
    3
    P

    2
    + PQ112 RLZ4.3B_LL34
    1 2
    O
    1

    2 G SSM3K7002FU_SC70-3

    2
    -
    G

    PU102A S
    3

    PR135
    LM393DG_SO8 FSTCHG#
    4

    10K_0603_0.1% PR136
    49.9K_0402_1%
    2

    D
    1 2 P2
    <40> FSTCHG 2 PQ113
    1.24VREF
    G SSM3K7002FU_SC70-3
    S
    3

    STD_ADP <40>
    PU104

    4 3 1.24VREF
    ACDET REF CATHODE
    1 2

    1
    PC127 2
    PR137 NC
    22P_0402_50V8J
    1

    4 4
    20K_0402_1%
    100K_0402_1%

    5 1

    2
    ANODE NC
    PR138

    LMV431ACM5X_SOT23-5
    2

    Security Classification
    2007/05/29
    Compal Secret Data
    2008/05/29 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    Charger
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 44 of 51
    A B C D
    A B C D E

    2VREF_51125

    0.22U_0603_10V7K

    1
    1 1

    PC302

    2
    PR301 PR302
    13.7K_0402_1% 37.4K_0402_1%
    1 2 1 2

    PR303 PR304
    B+ B++
    20K_0402_1% 24K_0402_1%
    B++
    PL301 1 2 1 2
    HCB2012KF-121T50_0805

    1 2 +3VLP

    ENTRIP2

    ENTRIP1
    PR305 PR306
    2200P_0402_50V7K

    4.7U_0805_25V6-K
    @0.1U_0402_25V4K

    @0.1U_0402_25V4K
    137K_0402_1% 133K_0402_1%
    1

    1
    PC316

    PC301

    PC303

    PC317
    1 2 1 2

    2200P_0402_50V7K

    10U_1206_25V6M
    10U_0805_6.3V6M

    1
    PC304

    PC305
    2

    2
    2

    2
    6

    5
    6
    7
    8
    PC306
    PU301

    8
    7
    6
    5

    ENTRIP2

    VFB2

    TONSEL

    VREF

    VFB1

    ENTRIP1
    25 PQ302
    2 P PAD AO4466_SO8 2

    2
    PQ301
    AO4466_SO8 7 24 4
    VO2 VO1
    4

    UG1_5V
    UG1_3V
    8 23 PR308 PC308
    PR307 VREG3 PGOOD 0_0402_5% 0.1U_0402_10V7K
    PR309 1 2 1 2 BST_3V 9 22 BST_5V 1 2 1 2 PR310

    3
    2
    1
    0_0402_5% 0_0402_5% VBST2 VBST1 0_0402_5%
    1
    2
    3

    PL302 1 2 PC307 UG_3V 10 21 UG_5V 1 2 PL303


    4.7UH_SIQB74B-4R7PF_4A_20% 0.1U_0402_10V7K DRVH2 DRVH1 4.7UH_SIL1045R-4R7PF_6.3A_30%
    2 1 LX_3V 11 20 LX_5V 1 2
    +3VALWP LL2 LL1
    8
    7
    6
    5

    5
    6
    7
    8
    LG_3V 12 19 LG_5V +5VALWP
    DRVL2 DRVL1

    SKIPSEL
    @4.7_1206_5%

    @4.7_1206_5%
    1

    220U_6.3VM_R15
    VREG5
    1

    1
    VCLK
    1

    GND
    EN0

    VIN
    +
    PC309

    PQ303 TPS51125RGER_QFN24_4X4
    220U_6.3VM_R15

    +
    PR315

    PR316

    PC310
    AO4466_SO8 4 4

    13

    14

    15

    16

    17

    18
    2
    2

    2
    2

    620K_0402_5%

    1
    @680P_0603_50V7K

    @680P_0603_50V7K
    1
    2
    3

    3
    2
    1
    VL PQ304
    1

    1
    PC314

    PR311

    PC315
    FDS6690AS_NL_SO8
    1 2
    2

    2
    1

    PC311
    PR312 PR318

    10U_0805_10V6K
    @0_0402_5% 1 2
    0_1206_5%

    2
    3 3

    <45> ENTRIP1 <45> ENTRIP2

    1
    B++

    0.1U_0603_25V7K
    2
    PC312
    2VREF_51125
    1

    D D
    PQ305 2 2 PQ306
    SSM3K7002FU_SC70-3 G G SSM3K7002FU_SC70-3
    S S
    +5VL
    3

    VL
    PJP304
    2 1
    PJP302 PAD-OPEN 2x2m
    1 2
    VL +5VALWP 1 2 +5VALW (4.5A,180mils ,Via NO.= 9)
    PR313 +3VLP +3VL
    PAD-OPEN 4x4m
    PQ308 100K_0402_5% PJP301
    1

    SSM3K7002FU_SC70-3 D D PQ307 PJP303


    2 1
    <40,46> ACIN 1 2 2 2
    EC_ON <40>
    +3VALWP
    1 2 +3VALW (3A,120mils ,Via NO.= 6)
    G G PAD-OPEN 2x2m
    PR317 S S SSM3K7002FU_SC70-3
    0.022U_0603_25V7K

    PAD-OPEN 4x4m
    604K_0402_1%
    1

    1
    PC318

    4 4
    100K_0402_5%
    2

    PR314

    om
    2

    l.c
    Compal Electronics, Inc.

    ai
    Security Classification Compal Secret Data

    tm
    Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

    ho
    3.3VALWP/5VALWP

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 45 of 51

    x
    he
    A B C D E
    A B C D

    1 1

    PR401
    0_0402_5%
    1 2 PL401
    SUSP#
    HCB1608KF-121T30_0603
    1

    PR410 1.05V_B+ 1 2 B+
    1

    @10K_0402_5% PC401

    2200P_0402_50V7K
    4.7U_0805_25V6-K
    @0.1U_0402_25V4K

    @4.7U_0805_25V6-K
    @1000P_0402_50V7K
    2

    5
    6
    7
    8

    1
    +5VALW
    2

    PC414

    PC403

    PC404

    PC405
    PC406
    BST_1.05V
    1 2 BST1_1.05V1 2 @680P_0402_50V7K

    2
    PC415 PR402 PC402
    1

    4.7U_0805_10V6K 0_0402_5% 0.1U_0402_10V7K 4


    PR403

    15

    14
    1
    316_0402_1% PU401
    2

    PR404

    EN_PSV

    TP

    VBST
    2 255K_0402_1% PQ401 2
    2

    3
    2
    1
    PR411
    1 2 2 13 DH_1.05V 1 2 AO4466_SO8 PL402
    TON DRVH 2.2UH_PCMC063T-2R2MN_8A_20%
    PR405 0_0402_5%
    +1.05V_VCCP 2 1 3 12 LX_1.05V 1 2 +1.05V_VCCP
    VOUT LL

    220U_6.3VM_R15
    0_0402_5%

    1
    4 11 1 2
    V5FILT TRIP

    5
    6
    7
    8
    PR406 PR407
    1

    @0.1U_0402_10V7K

    @0.1U_0402_10V7K
    5 10 +5VALW 15K_0402_1% @4.7_1206_5%
    VFB V5DRV

    1
    +

    PC408

    PC410

    PC411
    1

    PC409 6 9

    2 2
    PGOOD DRVL

    PGND
    1U_0603_10V6K

    GND

    2
    DL_1.05V 4 2
    2

    PC412
    +1.05V_VCCP TPS51117RGYR_QFN14_3.5x3.5 @680P_0603_50V7K
    7

    1
    PR408
    1 2
    10.5K_0402_1% PQ402

    3
    2
    1
    AO4466_SO8
    1 2
    PC413
    @10P_0402_50V8J
    1

    PR409
    25.5K_0402_1%
    2

    3 3

    PJP401
    +1.05V_VCCP 1 2 +VCCP (6A,240mils ,Via NO.=12)
    PAD-OPEN 4x4m

    4 4

    Security Classification
    2007/05/29
    Compal Secret Data
    2008/05/29 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    1.05V_VCCP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 46 of 51
    A B C D
    5 4 3 2 1

    PR521
    200K_0402_1%
    1 2
    GPU_VID <32,40,41,43,52>

    1
    G
    PQ504 PR520 PC522
    SSM3K7002FU_SC70-3 105K_0402_1% 0.01U_0402_16V7K
    3 1 1 2 High: +NVVDDP 1.0V

    2
    S

    D
    D D
    B+++ PR501 PR502 Low: +NVVDDP 0.9V
    73.2K_0402_1% 75K_0402_1% PR503 PR504
    75K_0402_1% 15K_0402_1%
    +1.5VSP 1 2 1 2 1 2 1 2 +NVVDDP1
    2200P_0402_50V7K

    PC516
    @0.1U_0402_25V4K

    1
    4.7U_0805_25V6-K

    @0.1U_0402_10V7K PR519
    PR518

    2
    PR505 1 2 10_0402_5% B+++ B+
    1

    0_0402_5% 0_0402_5% PL502


    PC501

    PC502

    PC520

    HCB2012KF-121T50_0805

    2
    2 1
    2

    +NVVDDP
    +NVVDD_SENSE

    @0.1U_0402_25V4K
    2200P_0402_50V7K
    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    +NVVDD_SENSE

    5
    6
    7
    8

    PC521
    PQ502 PU501

    PC504

    PC505
    PC511
    1 8

    VO2

    VFB2

    TONSEL

    GND

    VFB1

    VO1
    D1 1G PQ501
    2 7 25

    2
    D1 1S/2D P PAD AO4466_SO8
    3 6
    G2 1S/2D
    4 5
    S2 1S/2D
    7 24 4
    C SP8K10S-FD5_SO8 PGOOD2 PGOOD1 C
    PC507
    PC506 PR506 8 23 PR507
    EN2 EN1 0.1U_0402_10V7K
    0.1U_0402_10V7K 0_0402_5% 0_0402_5%
    +1.5VSP 2 1 2 1 BST_1.5V 9 22 BST_VGA 2 1 1 2

    3
    2
    1
    VBST2 VBST1
    +NVVDDP
    PL503 UG1_1.5V 2 1 UG_1.5V 10 21 UG_VGA 2 1 UG1_VGA PL501
    3.3UH_PCMC063T-3R3MN_6A_20% 0_0402_5% PR508 DR VH2 DR VH1 PR509 1UH_PCMC063T-1R0MN_11A_20%
    2 1 LX_1.5V 11 20 LX_VGA 0_0402_5% 1 2
    LL2 LL1
    LG_1.5V 12 19 LG_VGA
    DR VL2 DR VL1

    @0.1U_0402_10V7K

    @0.1U_0402_10V7K
    1

    5
    6
    7
    8
    1

    PGND2

    PGND1
    V5FILT

    1
    PR515

    TRIP2

    TRIP1

    PC525
    1

    V5IN
    1

    + PR516
    PC517

    PC524
    @4.7_1206_5%
    220U_B2_2.5VM

    330U_D2_2.5VY_R9M
    2
    +

    PC508
    PC509 @4.7_1206_5%

    2
    4.7U_0805_6.3V6K TPS51124RGER_QFN24_4x4 PC510
    2

    1 2

    13

    14

    15

    16

    17

    18
    2 4 4.7U_0805_6.3V6K

    1 2

    1
    2

    2
    PC518 PQ503
    2

    @680P_0603_50V7K PR510 PR511 PC519 FDS6670AS_NL_SO8

    3
    2
    1
    16.5K_0402_1% 12.4K_0402_1% @680P_0603_50V7K
    1 2

    1
    PR513
    0_0402_5% PR512
    2 1 0_0402_5%
    <32,34,40,43,46,48,50> SUSP# 1 2
    B
    1 2 SYSON <32,40,41,43,52> B
    +5VALW
    PR514
    3.3_0402_5%

    1
    PR517
    1

    1
    PC514 PC515 PC512 @100K_0402_5%
    1U_0603_10V6K 4.7U_0805_10V6K @0.1U_0402_16V7K
    PC513
    2

    2
    @0.1U_0402_10V7K

    2
    PJP501

    +1.5VSP 1 2 +1.5VS (4A,160mils ,Via NO.=8)


    PAD-OPEN 4x4m

    PJP502
    +NVVDDP 1 2 +NVVDD (12A,480mils ,Via NO.= 24)
    PAD-OPEN 4x4m

    PJP503
    1 2

    PAD-OPEN 4x4m

    A A

    om
    l.c
    Compal Electronics, Inc.

    ai
    Security Classification Compal Secret Data

    tm
    Issued Date 2007/05/29 Deciphered Date 2008/05/29 Title

    ho
    1.5VSP/VGA_CORE

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 47 of 51

    x
    he
    5 4 3 2 1
    5 4 3 2 1

    D D

    +1.8V

    PU601
    1 6
    VIN VCNTL +5VALW

    @10U_0805_10V4Z
    2 5
    GND NC

    PC602

    1
    PC601 3 7

    1
    VREF NC
    10U_0805_10V4Z

    2
    PR601 PC603
    4 8
    1K_0402_1% VOUT NC 1U_0603_16V6K

    2
    9

    2
    TP
    G2992F1U_SO8

    1 2
    <42,43> SYSON#
    PR602 +0.9VP

    0.1U_0402_16V7K
    1
    @0_0402_5%
    PQ601
    SSM3K7002FU_SC70-3 PR603

    1
    D
    1K_0402_1%
    1 2 2 PC605
    <43> SUSP

    2
    G 10U_0805_6.3V6M

    PC604
    PR604

    2
    0_0402_5% S

    3
    1
    C PC606 C

    2
    @0.1U_0402_16V7K

    +5VALWP

    1
    PC609 +1.5VS
    1U_0603_6.3V6M

    2
    PJP601

    +0.9VP 1 2 +0.9V (2A,80mils ,Via NO.= 4)

    6
    PU603

    1
    5

    VCNTL
    PAD-OPEN 3x3m VIN
    7 PC610
    POK 10U_0805_10V6K
    9

    2
    VIN
    3
    VOUT

    <32,34,40,43,46,48,49> SUSP# 1 2 8
    EN VOUT
    4 +1.1V_PCIE
    PR606

    GND
    1

    1
    0_0402_5% 2
    FB PC612
    B PJP603 PC611 22U_0805_6.3V6M B

    2
    1
    1 2 +PCIE (2A,80mils ,Via NO.= 4) @0.01U_0402_16V7K
    +1.1V_PCIE

    1
    PR607
    PAD-OPEN 3x3m
    40.2K_0402_1% PC613

    2
    APL5913-KAC-TRL_SO8 47P_0402_50V8J

    2
    1
    PR608
    105K_0402_1%

    2
    A A

    Security Classification Compal Secret Data Compal Electronics, Inc.


    Issued Date 2006/11/23 Deciphered Date 2007/11/23 Title

    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    0.9VP/1.1V_PCIE
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 48 of 51
    5 4 3 2 1
    5 4 3 2 1

    +5VS

    B+

    32
    CPU_B+

    2
    PR202 PL201

    CPU_VID6

    CPU_VID5

    CPU_VID4

    CPU_VID3

    CPU_VID2

    CPU_VID1

    CPU_VID0
    1_0603_5% SMB3025500YA_2P

    VR_ON
    2 1

    2200P_0402_50V7K

    1000P_0402_50V7K
    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    68U_25V_M_R0.44
    1

    1
    @0.1U_0402_25V4K
    PR201 499_0402_1%

    PC233

    PC234

    PC205

    PC206
    D D

    1
    1 2 PC203 +

    PC204

    PC207

    PC208
    7,20 DPRSLPVR
    PC202 2.2U_0603_6.3V6K

    PC237
    2

    2
    PR203 0_0402_5% 0.022U_0402_16V7K

    2
    2

    PR208

    PR209

    PR210

    PR211

    PR212

    PR205

    PR213
    1 2

    PR207
    5,7,19 H_DPRSTP#

    5
    6
    7
    8
    PR204 0_0402_5% PQ201

    D
    D
    D
    D
    CLK_ENABLE# 1 2 SI4684DY-T1-E3_SO8

    1
    1

    0_0402_5%

    0_0402_5%

    0_0402_5%

    0_0402_5%
    0_0402_5%

    0_0402_5%

    0_0402_5%

    0_0402_5%
    PR206 0_0402_5%

    G
    S
    S
    S
    +3VS 1 2

    4
    3
    2
    1
    +3VS

    1U_0603_6.3V6M

    2
    2
    0_0603_5% 0.22U_0603_10V7K UGATE_CPU1-2 PL202

    1.91K_0402_1%

    1
    PR214 PC209 0.36UH_PCMC104T-R36MN1R17_30A_20%

    PC201
    1
    BOOT_CPU1 1 2 1 2 2 1 +VCC_CORE
    2

    5
    6
    7
    8

    5
    6
    7
    8
    PR215
    PR216

    1
    10K_0402_1%
    @4.7_1206_5%

    3.65K_0805_1%

    1
    @499_0402_1%

    49

    48

    47

    46

    45

    44

    43

    42

    41

    40

    39

    38

    37
    1 2

    PR218

    PR219

    PR220
    0_0603_5% PR223
    2
    PR217 1_0402_5%

    GND

    3V3

    CLK_EN#

    DPRSTP#

    DPRSLPVR

    VR_ON

    VID6

    VID5

    VID4

    VID3

    VID2

    VID1

    VID0
    1

    4 4 PR224

    1 2

    2
    1 36 @0_0603_5%

    @680P_0603_50V7K

    2
    15,20 VGATE PGOOD BOOT1 PQ202 1 2
    2 35 UGATE_CPU1-1 AO4456_SO8 VSUM PC211

    PC210
    5 H_PSI# PSI# UGATE1
    1 2

    3
    2
    1

    3
    2
    1

    2
    1 PR221 2 3 34 PHASE_CPU1 PQ203 VCC_PRM
    @0_0402_5% PR222 147K_0402_1% PMON PHASE1 AO4456_SO8 ISEN1
    1 2 4 33 0.22U_0603_10V7K
    RBIAS PGND1
    VR_TT# 5 32 LGATE_CPU1 CPU_B+
    VR_TT# LGATE1

    2200P_0402_50V7K
    5
    6
    7
    8
    C C
    6 31

    1
    NTC PVCC

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    4.7U_0805_25V6-K

    @0.1U_0402_25V4K
    PQ204

    D
    D
    D
    D

    1
    7 30 LGATE_CPU2

    PC212

    PC213

    PC235

    PC236
    SI4684DY-T1-E3_SO8

    1
    SOFT ISL6262ACRZ-T_QFN48_7X7 LGATE2

    PC214
    2

    2
    8 29

    PC238
    2

    2
    G
    OCSET PGND2

    S
    S
    S
    0.022U_0603_25V7K PC215

    2
    1 2 9 28 PHASE_CPU2

    4
    3
    2
    1
    VW PHASE2 PR225
    PR226 13K_0402_1% 10 27 UGATE_CPU2-1 1 2 UGATE_CPU2-2
    COMP UGATE2 0_0603_5% 0.36UH_PCMC104T-R36MN1R17_30A_20%
    1 2
    11 26 BOOT_CPU2
    1 2 1 2 2 1
    FB BOOT2 PR227 PL203
    1 2

    5
    6
    7
    8

    5
    6
    7
    8

    1
    DROOP

    1000P_0402_50V7K PC216 12 25 0_0603_5% PC217

    @4.7_1206_5%

    1
    FB2 NC
    VDIFF

    VSUM

    ISEN2

    ISEN1
    VSEN

    PR228 6.81K_0402_1% 0.22U_0603_10V7K

    PR229
    GND

    10K_0402_1%
    VDD
    RTN

    3.65K_0805_1%
    DFB

    1
    VIN

    PR232
    VO

    1 2

    PR231
    PR230
    1 2 PU201
    13

    14

    15

    16

    17

    18

    19

    20

    21

    22

    23

    24

    1 2
    4 4 1_0402_5%

    2
    PC218 1000P_0402_50V7K

    2
    ISEN1 PQ205 PR233 @0_0603_5%

    PC219
    @680P_0603_50V7K
    ISEN2 AO4456_SO8 1 2

    2
    1 PR236 2

    PR235 97.6K_0402_1% PC220 1 2 PQ206


    @0_0402_5%

    +5VS

    3
    2
    1

    3
    2
    1
    2 PR237 1

    1 2 2 1 AO4456_SO8 VSUM PC223


    1K_0402_1%

    PR234 1_0603_5% 1 2
    470P_0402_50V7K PC221
    1 2 1U_0402_6.3V6K
    2

    0.22U_0603_10V7K
    PC222 220P_0402_50V7K VCC_PRM
    PR239 ISEN2
    255_0402_1% PC224 1000P_0402_50V7K 10_0603_5%
    1 2 1 2 1 2 CPU_B+
    B B
    1

    PR238 1 2 PC225
    0.1U_0603_25V7K
    PR240 1K_0402_1%
    2

    PC226 820P_0603_50V7K
    5 VCCSENSE 1 2
    VSUM
    1

    PC227 PC228
    2.61K_0402_1%

    @0.022U_0603_50V7K 0.01U_0603_50V7K
    PR241
    2

    5 VSSSENSE
    2
    1

    PC229 180P_0402_50V8J
    11K_0402_1%

    1 2
    PR242

    10KB_0603_5%_ERTJ1VR103J
    1 2 1 2 PH201
    2

    PR243 1K_0402_1% PR244 3.57K_0402_1%


    PC230 0.1U_0402_16V7K
    1

    VCC_PRM 1 2
    PC232 0.22U_0402_6.3V6K
    PC231 2 1 2 1
    0.22U_0603_10V7K

    A A

    om
    l.c
    ai
    tm
    Compal Electronics, Inc.

    ho
    Title
    +CPU_CORE

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

    nf
    Size Document Number Rev
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Custom 0.1

    ai
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

    x
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. Date: Friday, October 05, 2007 Sheet 49 of 51

    he
    5 4 3 2 1
    A B C D

    1 1

    PR701
    0_0402_5%
    1 2 PL701
    SYSON
    1

    HCB1608KF-121T30_0603
    PC702 1.8V_B+ 1 2 B+
    @1000P_0402_50V7K

    2200P_0402_50V7K
    4.7U_0805_25V6-K

    4.7U_0805_25V6-K
    @0.1U_0402_25V4K
    2

    5
    6
    7
    8

    1
    +5VALW

    PC701

    PC704

    PC705

    PC706
    PC707
    BST_1.8V1 2 BST1_1.8V 1 2 @680P_0402_50V7K

    2
    1

    PC716 PR702 PC703


    1

    4.7U_0805_10V6K 0_0402_5% 0.1U_0402_10V7K 4


    PR703

    15

    14
    2

    1
    316_0402_1% PU701
    2 PR704 2

    EN_PSV

    TP

    VBST
    255K_0402_1% PQ701
    2

    3
    2
    1
    PR711
    1 2 2 13 DH_1.8V 1 2 AO4466_SO8 PL702
    TON DRVH 2.2UH_PCMC063T-2R2MN_8A_20%
    PR705 0_0402_5%
    +1.8VP 2 1 3 12 LX_1.8V 1 2 +1.8VP
    VOUT LL
    0_0402_5%

    1
    4 11 1 2
    V5FILT TRIP

    5
    6
    7
    8
    PR706 PR707
    1

    @0.1U_0402_10V7K

    @0.1U_0402_10V7K
    330U_D2_2VY_R15M
    5 10 +5VALW 17.8K_0402_1% @4.7_1206_5%
    VFB V5DRV

    1
    +

    PC709

    PC711

    PC712
    1

    PC710 6 9 DL_1.8V PC717

    2 2
    PGOOD DRVL

    PGND
    1U_0603_10V6K 4.7U_0805_6.3V6K

    GND

    2
    4 2
    2

    PC713
    +1.8VP TPS51117RGYR_QFN14_3.5x3.5 @680P_0603_50V7K
    7

    1
    PR708
    1 2
    28K_0603_0.1% PQ702

    3
    2
    1
    FDS6690AS_NL_SO8
    1

    PR709
    19.6K_0603_0.1%
    2

    3 3

    PJP701

    +1.8VP 1 2 +1.8V (7A,280mils ,Via NO.= 14)


    PAD-OPEN 4x4m
    PJP702
    1 2

    PAD-OPEN 4x4m

    4 4

    Security Classification
    2007/05/29
    Compal Secret Data
    2008/05/29 Title
    Compal Electronics, Inc.
    Issued Date Deciphered Date
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    1.8VP
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 50 of 51
    A B C D
    5 4 3 2 1

    Item Fixed Issue Reason for change PAGE Modify List Note

    D D

    C C

    B B

    A A

    om
    l.c
    ai
    Security Classification Compal Secret Data Compal Electronics, Inc.

    tm
    2007/09/26 2007/09/26 Title

    ho
    Issued Date Deciphered Date
    PIR

    @
    THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
    AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
    Size Document Number Rev

    nf
    DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Montevina Consumer Discrete 0.1

    ai
    MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
    Date: Friday, October 05, 2007 Sheet 51 of 51

    x
    he
    5 4 3 2 1

    You might also like

    pFad - Phonifier reborn

    Pfad - The Proxy pFad of © 2024 Garber Painting. All rights reserved.

    Note: This service is not intended for secure transactions such as banking, social media, email, or purchasing. Use at your own risk. We assume no liability whatsoever for broken pages.


    Alternative Proxies:

    Alternative Proxy

    pFad Proxy

    pFad v3 Proxy

    pFad v4 Proxy