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    6.02 Nbits +1.76 25,84 DB: SNR V V

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    Helder Cruz
    The document discusses a 4-bit analog-to-digital converter (ADC) with the following key details: 1) The ADC has a resolution of 4 bits, providing 16 distinct digital output levels. 2) It consists of 3 stages, resulting in a latency of 3 clock cycles to convert an analog input voltage to a digital output. 3) Diagrams and equations show the analog signal processing and quantization in each stage to progressively refine the digital output code representing the input voltage.

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    6.02 Nbits +1.76 25,84 DB: SNR V V

    Uploaded by

    Helder Cruz
    28 views2 pages
    The document discusses a 4-bit analog-to-digital converter (ADC) with the following key details: 1) The ADC has a resolution of 4 bits, providing 16 distinct digital output levels. 2) It consists of 3 stages, resulting in a latency of 3 clock cycles to convert an analog input voltage to a digital output. 3) Diagrams and equations show the analog signal processing and quantization in each stage to progressively refine the digital output code representing the input voltage.

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    The document discusses a 4-bit analog-to-digital converter (ADC) with the following key details: 1) The ADC has a resolution of 4 bits, providing 16 distinct digital output levels. 2) It consists of 3 stages, resulting in a latency of 3 clock cycles to convert an analog input voltage to a digital output. 3) Diagrams and equations show the analog signal processing and quantization in each stage to progressively refine the digital output code representing the input voltage.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    28 views2 pages

    6.02 Nbits +1.76 25,84 DB: SNR V V

    Uploaded by

    Helder Cruz
    The document discusses a 4-bit analog-to-digital converter (ADC) with the following key details: 1) The ADC has a resolution of 4 bits, providing 16 distinct digital output levels. 2) It consists of 3 stages, resulting in a latency of 3 clock cycles to convert an analog input voltage to a digital output. 3) Diagrams and equations show the analog signal processing and quantization in each stage to progressively refine the digital output code representing the input voltage.

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    © All Rights Reserved
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    1

    a) Resolution=2+(2-1)+(2-1)=4 bits

    b) (
    SNR max v i n =
    V ref
    2 )=6.02⋅nbits +1.76=25,84 dB

    c) 3 stages → latency =3

    Vout

    1 1 1 2 2 2
    Q 2 C +Q C +Q 2 C =Q 2 C +Q C +Q 2 C ⇔( 0v i n)⋅2 C +(00)⋅C +( 0v i n)⋅2 C=(0v R 1 )⋅2C +( 0v R 0)⋅C +( 0v out )⋅2 C
    1
    ⇔ v out =2⋅v i nv R 1 ⋅v R 0
    2

    Vref V ref

    { }
    bi
    2 vRi if bi =1 V ref
    v Ri = 2 = + bi⋅V ref
    -Vref bi V ref 2
    2 if bi =0 V ref V ref
    2 v out =2⋅v i n + b1⋅V ref + b 0⋅V ref
    2 4
    g) Stage 0
    Stage 2 0.075 V
    0.15 V Stage 1 0.0 VV
    0.025
    0.05 V
    vres0
    vres2
    Sample

    Sample

    Sample
    & Hold

    & Hold

    & Hold
    0.2 V 0.15 V
    vin + 2 + 2
    0.2 V - 0.125 V - 0.125
    v
    V
    vDAC2 DAC1

    DAC

    DAC
    ADC

    ADC

    ADC
    clk 2 2 clk 2 2 clk 2

    dout2 dout1 dout0


    10 10 10

    0.125 V
    0.125 V 10 10
    10

    10
    10 0.15 V 0.05
    0.0 VV
    0.2 V

    d out =1000 +10+1=1011

    h) Stage 0
    Stage 2 -0.175 V -0.35 V
    vres2
    Stage 1 0.025 V
    0.05 V
    vres0
    Sample

    Sample

    Sample
    & Hold

    & Hold

    & Hold
    0.2 V -0.35 V
    vin + 2 + 2
    0.2 V - 0.375 V - -0,375
    v
    V
    vDAC2 DAC1
    DAC

    DAC
    ADC

    ADC

    ADC
    clk 2 2 clk 2 2 clk 2

    dout2 dout1 dout0


    11 00 10

    0.375 V
    11 10

    00 -0,375 V
    00
    11 0.05 V
    -0.35 V
    0.2 V

    d out =1100 +0010+1=1011

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