Non Linear Applications

of OP-AMP
 Contents :
Comparators, Limitations of op-amp as comparator,
Schmitt Trigger,
Precision half wave and full wave rectifiers,
Peak Detectors,
Sample and Hold circuits,
Waveform generators,
Wein bridge Oscillator
Quadrature oscillator.
An operational amplifier, in open loop configuration, operates
in a non-linear manner.
It finds use in many applications in which the output needs to
be switched between positive and negative saturation levels.
Positive feedback can also be employed in these circuits to
obtain hysteresis characteristics, i.e., to provide the upper and
lower input voltage levels that trigger the output voltage to
change from one saturation level to the other.
 Comparators
An op-amp comparator compares an input voltage signal with a known voltage, called the
reference voltage.
 In its simplest form, the comparator consists of an op-amp operated in open-loop, and
when fed with two analog inputs, it produces one of the two saturation voltages ±Vsat ( +Vcc
or – VEE ) at the output of the op-amp.
The input-output transfer characteristics of an ideal comparator and a practical comparator
using op-amp are shown in Fig.
 It can be seen from Fig. (b) that the output state of a practical comparator can change with
an input increment of only 2 mV.
This width of 2 mV is the region of uncertainty of a practical comparator.
Two types of comparators, viz.
(i) Non-inverting comparator, and (ii) Inverting comparator can be constructed using op-
amps.
Transfer characteristics of an ideal comparator and a
practical comparator
Non-inverting comparator
• A fixed reference voltage Vref is applied to (–) input and
a time-varying signal vi is applied to (+) input.
• When the noninverting input vi is less than the reference
voltage Vref, i.e. vi < Vref, the output voltage vo is at -V @ -
V sat EE .
• On the other hand, when vi is greater than Vref , i.e. vi >
Vref , the output voltage vo is at +V @ +V sat CC
• .
• Thus, the output vo changes from one saturation level to
another depending on the voltage difference between vi
and Vref.
• Figures show the input and output waveforms of the
comparator when Vref is positive and negative
respectively.
• The diodes D1 and D2 are connected to protect the op-amp
from excessive input voltages of Vref as shown in Fig
In practical circuits, Vref can be
obtained by the use of a 10 k
potentiometer forming a voltage
divider with the use of supply voltages
+VCC and –VEE , and the wiper
connected to (–) input terminal of op-
amp as shown in Fig. (d).
Output voltage level other than ±Vsat at the output can be
obtained by using a resistor R and back-to-back Zener diodes
connected at the output of op-amp as shown in Fig. (e).
Then, the limiting values of voltage vo becomes (VZ1 + VD)
and –(VZ2 + VD), where VD ª 0.7V, and VZ1 and VZ2 are the
Zener voltages.
 Practical inverting comparator
Figure (a) shows a practical
inverting comparator with the
reference voltage Vref applied to (+)
input and the voltage signal vi
applied to the (–) input.
 For a sinusoidal input signal vi and
for positive and negative Vref, the
input and output waveforms are as
shown in Fig. (b) and (c) respectively.
Applications of comparator
The important applications of comparator are:
(i) Zero crossing detector (sine wave to square wave converter)
(ii) Amplitude distribution analyser
(iii) Pulse-time modulator
(iv) Window detector
(v) Timing marker signal generator
(vi) Phase detector
Exa. 1 . Draw the transfer characteristics of the comparator circuit
shown in Fig. , when (a) op-amp is ideal and (b) open-loop gain of op-
amp is 100000. Assume VZ1 = VZ2 = 5.5 V.
(a) Since the op-amp is ideal, the open-loop gain AOL
= ∞. Therefore, a very small positive or negative
voltage at the input results in ±Vsat at the output.
This causes VZ1 or VZ2 to breakdown, driving the
output vo to ±(VZ + VD) = ±(5.5 V + 0.7 V) = ±6.2 V.
The curve shown in Fig. shows the transfer
characteristics of the ideal op-amp.
That is, the Zener diodes break down at ±0.062 mV. The transfer characteristic of such an
arrangement is shown in Fig.
 Limitations of op-amp as comparator

Transition from one state to another state.

These transitions are more noticeable at high frequencies or
even greater than the input signal period itself.
Thus there is upper limit of the operating frequency for the
comparator.
This maximum operating frequency is dependent on the slew
rate of the op-amp.
The Compatibility issues. For e.g. With TTL logic, two levels
are defined: +5V(logic1) and 0V(logic0). Thus to get the output
level within specified limit, additional components are
required like Zener diodes.
Schmitt Trigger
The basic comparator is used in open-loop mode. Since the open loop gain of the
op-amp is very large, false triggering at the output can occur even due to a few
tenths of millivolts peak of the input or less.
When the input changes slowly as compared to the output, noise is coupled from
the output of the comparator back to the input.
The comparator circuit designed with a positive feedback to avoid such an
unwanted triggering is called the Schmitt Trigger or the Regenerative Comparator.
The positive feedback makes the gain very large and the transfer curve of the comparator
becomes closer to the ideal curve as shown in Fig..
Theoretically, if the loop gain βAOL is adjusted to be unity, the gain with feedback Avf
becomes infinite.
This results in an abrupt transition (zero rise and fall timings) between the two saturation
voltages.
But, in practical circuits, the loop gain may not be maintained exactly equal to unity for a
long time.
This may be due to supply voltage or temperature variations.
 Hence, a value greater than one is chosen normally.
This gives an output waveform exhibiting the characteristics of hysteresis or backlash.
•Figure (a) shows the regenerative comparator or the inverting Schmitt Trigger.
•It consists of an inverting comparator provided with positive feedback.
• The input voltage to be wave-shaped is applied to the (–) input terminal and the feedback voltage is applied
to the (+) input terminal.
•The input voltage vi triggers the output vo every time it crosses certain voltage levels.
•These voltage levels are called Upper Threshold Voltage VUT and Lower Threshold Voltage VLT.
•The difference between the two threshold voltages VUT and VLT is called the hysteresis voltage,
•VH = VUT – VLT.
•The voltage span of hysteresis is set to be greater than the peak-to-peak noise voltage.
•Therefore, there will not be any incorrect output variations due to noise signals.
The threshold voltage values can be obtained as follows. Suppose the output is at positive saturation with vo = +Vsat,
then the voltage at (+) input terminal is given by
where VUT is the upper threshold voltage.
The output voltage vo remains constant at +Vsat as long as vi is less than VUT.
When vi is just slightly more positive than VUT, the output vo switches from +Vsat to –Vsat and remains at the same
level, as long as vi is greater than VUT as shown in Fig. 5.9(b). When Vo = – Vsat, the voltage at the (+) input terminal
is given by
This voltage is identified as Lower Threshold
Voltage VLT
The input voltage vi must be slightly more negative than VLT to switch vo from –Vsat to +Vsat as shown in Fig. (c). The
complete transfer characteristics of the regenerative action are shown in Fig. (d).
The hysteresis width VH is the difference between the two threshold voltages. That is,

It can be observed from the above equation that VH is independent of Vref.

Resistor R3 of Fig. (a) is selected such that R3=R1‖ R2. This compensates for the variations in input bias current of the
op-amp.
A non-inverting Schmitt trigger is constructed in the same manner with a modification. The signal vi and Vref
are interchanged between (–) and (+) input terminals of op-amp.
If Vref in Fig. (a) is made equal to 0 V, the upper and lower threshold voltage levels are

When an input sinusoidal signal of frequency f is applied to such a comparator, a symmetrical square wave is
produced at the output as shown in Fig.
Hence, the most important application of the Schmitt trigger circuit is to convert a slowly varying input voltage
into a square wave output. Hence, the circuit is also called a squarer.
Refer to the circuit of Fig.(a), R1 = 56 k, R2 = 150 k, vi = 1Vpp sine wave of frequency 50
Hz, Vref = 0V and op-amp 741 is used with supply voltages of = ±15 V and the saturation
voltages are ±13.5 V. Determine the threshold voltages VUT and VLT and draw the input
and output waveforms of Schmitt trigger. Also, plot the hysteresis voltage curve.
 Precision rectifiers
The signal processing applications with very low voltage, current and power
levels require rectifier circuits.
 The ordinary diodes cannot rectify voltages below the cut-in voltage of the
diode.
A circuit which can act as an ideal diode or precision signal-processing
rectifier circuit for rectifying voltages which are below the level of cut-in
voltage of the diode can be designed by placing the diode in the feedback loop
of an op-amp.
The above figure shows a practical rectifier circuit with its transfer characteristics.
In a practical rectifier circuit, the output waveform will be 0.7 volts less than the applied input
voltage, and the transfer characteristic will look like the figure shown in the diagram.
At this point, the diode will only conduct if the applied input signal is slightly greater than the
forward voltage of the diode.
Noninverting Half Wave Rectifier:
Vi >0 V

Vi<0 V
INVERTING HALF WAVE RECTIFIER
 Precision half wave rectifier
A non-saturating half-wave precision rectifier circuit is shown in Fig. 5.12(a).
When vi > 0, the voltage at the inverting input becomes positive, forcing the output VOA to go
negative. This results in forward biasing the diode D1 and the op-amp output drops only by ª
0.7 V below the inverting input voltage.
Diode D2 becomes reverse-biased. The output voltage vo is zero since no current flows in the
feedback circuit through Rf.
 Hence, the output vo is zero when the input is positive.
When vi < 0, the op-amp output VOA becomes positive, forward biasing the diode D2 and
reverse biasing the diode D1.
The circuit then acts like an inverting amplifier circuit with a non-linear diode in the forward
path.
The gain of the circuit is unity when Rf = Ri.
The input and output waveforms are shown in Fig. (b).
The op-amp shown in the circuit must be a high-speed op-amp. This accommodates the
abrupt changes in the value of VOA when vi changes sign and improves the frequency
response characteristics of the circuit.
The advantages of half-wave rectifier are
(i) it is a precision half-wave rectifier, and
(ii) it is a nonsaturating one.
The inverting characteristics of the output vo can be circumvented by the use of an
additional inversion for achieving a positive output.
Precision full wave rectifier (Absolute value circuit)

The first part of the total circuit is a half-wave rectifier circuit

The second part of the circuit is an inverting summing circuit.
Vo will be inverted and will thus be positive. This corresponds to the second quadrant operation of the
circuit.
It can be observed
that this circuit is of
non-saturating form.
 Peak Detectors
A peak detector is a circuit that produces an output voltage equal to the positive or negative
peak value of the input voltage.
 A positive peak detector detects the positive peak magnitude of the input and a negative peak
detector identifies the negative peak magnitude of the input
The basic blocks required for the peak detector circuit are:
(i) an analog memory such as a capacitor to store the charge proportional to the peak value
(ii) a unidirectional switch such as a diode to charge the capacitor when a new peak arrives at the
input
(iii) a device such as a voltage follower circuit for making the capacitor charge to the input voltage
and
(iv) a switch to periodically reinitialize the output to zero.
Figure (a) shows the circuit of a positive peak detector.
The capacitor CH, diode D2, op-amp A1 and switch SW perform the four
functions listed above in order.
The op-amp A2 acts as a buffer. This prevents discharging of the capacitor
CH.
The diode D2 is preferred to be of very low leakage current.
The diode D1 and resistance R avoids saturation of op-amp when a peak is
detected.
When the input signal vi > 0, the output of op-amp A1 is positive. The diode
D2 is hence forward-biased and diode D1 is reverse-biased. The capacitance
CH then gets charged. The feedback path provided by diode D2, op-amp A2
and resistor R maintain the virtual short between the input terminals of A1.
 In other words, the voltages at the inverting and non-inverting terminals of
A1 are equal. Then, the voltage vi during this phase is vi = vo + VD2(ON)
The output vo tracks vi and this phase is called the track mode. The op-amp A1
sources current to charge CH through diode D2. When vi begins to decrease, D2
becomes reverse-biased and D1 becomes forward-biased and conducts.
The output of A1 is now.
The feedback path from vo to vi through diode D2 and R is now open. During
this phase, the capacitor voltage remains constant. Hence it is called the hold
mode and the output of op-amp A2 retains the peak voltage.
Figure (b) shows the voltage waveforms for the positive peak detector for a
certain input signal vi. The circuit can be reset at any time by closing the switch
SW. The switch SW can be a low leakage MOSFET.
Negative peak detectors can be obtained by reversing the diode connections.
Figure (a) and (b) show the equivalent circuits of the peak detector when
the circuit operates in the track mode and hold mode.
It can be observed that, placing the diode D2 and op-amp A2 within the
feedback path of A1 eliminates the possible errors due to the diode drop
across D2 and the input offset voltage of A2.
The requirements for op-amp A1 are low dc input error and high output
current capability to charge CH during fast occurring peaks.
The op-amp A2 with low input bias current is preferred to minimise the
capacitance discharge between peaks.
 A peak-to-peak detector

The op-amp A is a subtractor connected the op-amp circuit, which enables the
signal vp–p to identify the peak-to-peak value of the input signal vi.
 Sample & Hold Circuit
Sample & Hold Circuit is used to sample the given input signal and to hold the sampled
value.
Sample and hold circuit is used to sample an analog signal for a short interval of time in
the range of 1 to 10µS and to hold on its last sampled value until the input signal is
sampled again.
The holding period may be from a few milliseconds to several seconds.
The following figure shows the block diagram of a typical sample and hold amplifier.
The Command terminal is in the form of a logic pulse. It controls whether to
sample the input signal or hold the last sampled value of the input signal.
When the pulse is high signal is sampled and when the pulse is low signal value
is holded. Thus the circuit has two modes of operation depending upon the
logic level of S/H command signal.
Upon receiving the input command pulse, the circuit samples the input and
output follows input i.e. output tracks the input so called TRACK mode of
operation.
 After command pulse is removed the circuit holds the output at a value
which input signal had at an instant of pulse deactivation; which is called HOLD
mode.
Sample and hold circuits are used in
following applications.
1. Analog to Digital conversion (ADCs)
Out of different ADCs, successive approximation type ADC uses S/H
circuit, where the signal is to be held constant while A to D conversion is
taking place.
2. In DACs
3. In analog demultiplexing in data distribution and in analog delay lines.
In general S/H circuits are used in all applications where it is necessary to
freeze the analog signal for further processing.
Sample and Hold circuit
Amplifier A1 and A2 are both voltage follower circuits.
FET is operated as ON/OFF switch.
The S/H pulses controls the switching ON/OFF of FET.
Signal to be sampled is applied at Vin.
Input impedance of A1 is very high so input voltage source is not loaded.
 While sampling output of A1 is same as Vin.
When S/H pulse is applied FET switches ON and starts conducting. Resistance between drain
and source (rdsON) is very small.
For voltage follower, A1 and A2 have 100% feedback (β=1). Therefore output impedance of A1
and A2 is very small.
Now capacitor C starts charging through rdsON and output impedance of A1.
Charging Time Constant = rdsON × rout × C
As rdsON and rout are very small, capacitor C charges through very quickly to Vin (i.e. capacitor
tracks the input signal).
At the end FET is off, so almost acts as open circuit. So capacitor isolates
from previous circuits and it holds the charge of last sampled value.
As input impedance of A2 is very large, capacitor discharging time is very
high, so it almost holds the charge. Also Gain of A2 is unity.
Therefore Vout = Charge on capacitor
As rout of A2 is very small, we can take Vout across any value of RL
The Capacitor C used has a perfect dielectric having no leakage.
Materials used for di-electric are polycarbonate, polythene, polystyrene,
myler or Teflon.
Performance parameters of S/H circuit:
The performance of an ordinary S/H circuit can be characterized by Vio,
Gain error, nonlinearity etc. Consider the following figure to define some
of the important parameters of S/H amplifier.
1. Acquisition Time (tAC):
It is the time required for the holding capacitor CH to charge upto a level
close to the input voltage during sampling. It depends on three factors
namely RC time constant, Maximum output current of op-amp and slew
rate of op-amp.
2. Aperture Time (tAP):
Ideally as soon as the hold command is given to S/H circuit, the circuit
should stop following any changes taking place in the input and hold the
latest sampled value. But practically, the S/H circuit will follow the
changes in input voltage for a short period of time, even after receiving
the hold command. This period is called as aperture time. It is due to the
propagation delays of the driver and the switch.
3. Aperture Uncertainty (∆tAP):
It is the variation in the aperture time from sample to sample.
4. Hold mode settling time (ts):
After the application of hold command, it takes a certain amount of time for Vo to settle within a
specified error band such as 1%, 0.1%, 0.01%.
5. Hold Step:
At the time of switching from sample to hold or hold to sample mode, there is an unwanted
transfer of charge between the switch driver and holding capacitor CH. This changes the
capacitor voltage and hence output voltage. These changes in output voltage are referred as
hold step, pedestal error or sample and hold offset.
6. Feed through:
In the hold mode, because of stray capacitances across switch there is a small amount of ac
coupling between Vo and Vin. This ac coupling causes output voltage to vary with variation in
the input voltage. This is referred as feed through.
7. Voltage Droop:
The leakage current causes voltage of the capacitor to drop down. This is referred as droop.
This sample and hold circuit is readily built in IC form is available (monolithic) and are
comparatively inexpensive. For this IC user has to connect only a single capacitor externally.
National Semiconductor ICs LM 198/298/398.
 Waveform generators

The op-amps are widely used in circuits for generating various waveforms.
Most of the analog and digital equipments require one or more periodic
waveforms for timing, control and other functions.
The commonly used sinusoidal, square and triangular waveform generations
are other forms of evolution in the design of operational amplifiers.
Their applications have made the design of oscillators possible, which are
capable of generating repetitive waveforms of fixed frequency and amplitude
without the need of any other signal.
The terms oscillator and function generator or waveform generator represent
the circuits employed for generating such waveforms.
 Multivibrators

Multivibrators are regenerative circuits, which are mainly used in timing applications. Based
on their operational characteristics, they can be classified into three categories, namely,
(i) Astable multivibrator
(ii) Monostable multivibrator
(iii) Bistable multivibrator
The astable multivibrator toggles between one state and the other without the influence of
any other external control signal. It is also called a free-running multivibrator.
The monostable multivibrator or one-shot requires an external signal called a trigger to force
the circuit into a quasi-stable state for a particular time duration or delay. A suitable timing
network determines the time delay and it returns to the stable state at the end of the delay
time.
Square-wave generator / Astable multivibrator
 Square-wave generator / Astable
multivibrator
An astable multivibrator is a square-wave generator. Figure (a) shows the circuit of an astable
multivibrator with the output of op-amp fedback to the (+) input terminal.
 The resistors R1 and R2 forma voltage divider network, and a fraction β = R2/R1+R2 of the
output is fed back to the input.
 The output can take values of +βVsat or –βVsat. The voltage ± β Vsat acts as Vref at the (+)
input terminal. The output is also connected to the (–) input terminal through an integrating
low-pass RC network.
When the voltage Vc across capacitor C just exceeds Vref , switching takes place resulting in a
square-wave output.
To understand the operation of the circuit, let us consider that initially the output is at +Vsat
as shown in Fig. (b).
The capacitor C with its voltage shown as Vc starts charging through resistor R towards +Vsat.
The voltage at (+) input terminal is held at +βVsat as indicated by the use of R1 – R2 potential
divider network.
The charging of C continues until the voltage Vc at the (–) input terminal is just greater than
the voltage at the (+) input terminal, +βVsat .
When this happens as shown at point b of Fig. (b), the output is switched down to –Vsat.
The voltage + +βVo across the capacitor now starts discharging through resistance R and
charging towards –Vsat. The capacitor voltage v
Vc now becomes increasingly more and more negative and at point c just exceeds –βVsat. The
output now switches back to +Vsat, and the cycle repeats.
Summarising,
(i) when vo = + Vsat, C charges from –βVsat to +βVsat and switches vo to – Vsat and
(ii) when vo = – Vsat, C charges from +βVsat to –βVsat and switches vo to +Vsat.
The frequency of the free running multivibrator is determined by the charging and
discharging time of the capacitor between the voltage levels –b Vsat and +bVsat
and vice versa. The voltage across the capacitor as a function of time can be
represented as

Considering the charging of the capacitor from point a towards +Vsat,

At t = T1, the voltage across the capacitor reaches +b Vsat and
switches at point b. Therefore, capacitor voltage vc at time T1 is

The output is a symmetrical waveform

Considering R1 = R2
Equation shows that the period is directly proportional to the time constant, RC.
Thus, varying either R or C changes the period correspondingly.
Therefore, providing a tunable resistance R paves the way for a continuously tunable square-
wave generator.
The output peak amplitudes can be varied by the use of Zener diodes connected back to
back as shown in Fig. (c).
The output voltage is then regulated to ±(Vz + VD) where Vz is the Zener voltage. Then the
peak-to-peak output voltage is given by vo (peak-to-peak) = 2(Vz + VD).
To generate an asymmetric square wave, a variable voltage source V can be introduced as
shown in Fig. (d).
For the circuit shown in Fig. (a), assuming that R1 = 116 k, R2 = 100 k, and ± Vsat = ± 14 V, find
(i) the time constant to produce 1 kHz output
(ii) the resistance R and
(iii) the maximum value of differential input voltage
Design a square wave oscillator for fo = 1 kHz using 741 op-amp
and DC supply voltage of ± 12 V.

Let R1 = R2 = 10 kΩ
Design a square-wave oscillator for fo = 2 kHz using 741 OP-
AMP and a dc supply voltage of +12 V.
 Triangular wave generator

Figure (a) shows the circuit of a triangular wave generator.

It consists of two op-amps and several passive components.
The op-amp A1 forms a non-inverting comparator with hysteresis, which is a Schmitt
Trigger.
The op-amp A2 forms an integrator which integrates the output obtained from the
Schmitt trigger.
The op-amp A1 is a two level comparator whose outputs are determined by ±Vsat.
The square-wave output from A1 is applied to the (–) input terminal of the op-amp
A2.
The output of A2 is a triangular wave and it is fed back as an input to the comparator
A1 through a voltage divider network formed by R2 and R3.
Let us consider that the output v ¢o of comparator A1 is +Vsat initially. The integrator
integrates +Vsat and produces a negative going ramp at its output as shown in Fig. (b).
Hence, the voltages at the two ends of the voltage divider formed by R2 – R3 are + Vsat at
the output of A1and –Vramp at the output of A2.
 At t = T1 , when the negative going ramp reaches a value of –Vramp represented as point a
in Fig. (b), the effective value at the point P becomes slightly less than 0 V.
This switches the op-amp A1 to its negative saturation level – Vsat.
With the output of A1 at –Vsat, the op-amp A2 starts integrating and increases its output in
the positive direction.
 At t = T2, shown as point b in Fig. (b), the voltage at P becomes just more than 0 V. This
switches the output of op-amp A1 from – Vsat to +Vsat.
This cycle repeats itself, and generates a triangular waveform. The frequency of the
waveform is determined by the RC value of the integrator formed by op-amp A2 and the
saturation voltage levels ±Vsat of comparator op-amp A1.
When the comparator output is at + Vsat, the effective voltage at the point P is
The time taken for the output of A2 to switch from –Vramp to +Vramp is half of the time period,
i.e. T/2.

Substituting the value of vo(pp) from Eq. (7.27) in the above equation, we get

Therefore, the frequency of oscillation is

Assume that for the circuit shown in Fig. (a), R1 = 100 k, R2 = 10 k, R3 = 20 k, C1 = 0.01
µF and ± Vsat = ± 14 V for the op-amps. Determine the (a) period, (b) frequency,
(c) peak value of square wave and (d) peak value of triangular wave.

(c) The peak value of the op-amp is simply the saturation voltage levels, i.e. +14V and –14V
(d) Peak value of the triangular wave is

Therefore, the triangular wave oscillates between +7 V and –7 V

Assume that for the circuit shown in Fig. (a), R1 = 10 k, R2 = 1 k, R3 = 2.2 k, C1 = 0.01µF and ±Vsat = ±14
V for the op-amps. Determine the (a) period, (b) frequency, (c) peak value of square-wave, and (d)
peak value of triangular wave.
A triangular waveform generator can also be constructed by a simple
alternate arrangement of a square-wave generator connected to an
integrator as shown in Fig. (a).
Let us assume that the voltage Vo´ is high at +Vsat.
This forces a current of +Vsat/R3 through capacitor Cf of the integrator, producing a negative
ramp at the output of the integrator.
 When Vo´ is low at voltage – Vsat, the output of integrator ramps up linearly.
This cycle repeats itself and hence the frequency of the triangular wave is the same as that of
the square-wave.
 Hence, the value of resistor R connected in the square-wave generator part of the circuit
determines the frequency of the triangular wave.
The amplitude of the triangular wave decreases with an increase in frequency value. This is due
to the fact that the capacitive reactance decreases at high frequencies and increases at low
frequencies.
The square waveform and triangular waveform of the circuit are shown in Fig. (b).
A stable triangular wave can be obtained by maintaining 5R3C2 > T /2, where T is the period of
the square-wave input. A resistance R4 is normally connected across Cf to avoid saturation
problems occurring at low frequencies.
 Sine-wave oscillators
The sine-wave is one of the most fundamental waveforms.
The generation of sine-wave is a challenging task if ideal waveform characteristics are expected.
In the sine-wave oscillators using op-amps, the required phase-shift of 180o in the feedback
loop from output to input is obtained by using either L and C or R and C components.
An oscillator is basically a feedback amplifier, in which a fraction of the output is fed back to the
input with the use of a feedback circuit. The block diagram of an oscillator is shown in Fig.
Therefore, the two basic requirements for
sustained oscillations are:
(i) the magnitude of the loop gain, Av b, must
be unity and
(ii) the total phase-shift of the loop gain, Av b ,
must be equal to 0o or 360o
 RC oscillators

All the oscillators using tuned LC circuits operate well at high frequencies.
At low frequencies, as the inductors and capacitors required for the timing
circuit would be very bulky, RC oscillators are found to be more suitable.
Two important RC oscillators are
(i) RC phase shift oscillator and
(ii) Wien Bridge oscillator.
 Wein bridge Oscillator

Wien Bridge oscillator is the most commonly used audio frequency oscillator due to its
inherent simplicity and stability.
Figure (a) shows the Wien Bridge oscillator using op amp. Since the op-amp is connected to
operate in non-inverting mode, it produces no phase-shift at the output. The Wien Bridge
circuit is connected between the input and output terminals of the amplifier.
The bridge consists of a series RC network (shown as Zs (s)) forming one arm of the bridge
circuit, a parallel RC network (shown as Zp (s)) forming the second arm, input resistance R1
and feedback resistance Rf forming the third and fourth arms of the bridge circuit
respectively as shown in Fig.(b).
The feedback circuit of the Wien Bridge oscillator is shown in Fig. (c).
The above RC network consists of a series RC circuit connected to a parallel RC forming basically a High Pass Filter
connected to a Low Pass Filter producing a very selective second-order frequency dependant Band Pass Filter with
a high Q factor at the selected frequency, ƒr.
At low frequencies the reactance of the series capacitor (C1) is very high so acts a bit like an open circuit, blocking
any input signal at Vin resulting in virtually no output signal, Vout. Likewise, at high frequencies, the reactance of
the parallel capacitor, (C2) becomes very low, so this parallel connected capacitor acts a bit like a short circuit
across the output, so again there is no output signal.
So there must be a frequency point between these two extremes of C1 being open-circuited and C2 being short-
circuited where the output voltage, VOUT reaches its maximum value. The frequency value of the input waveform
at which this happens is called the oscillators Resonant Frequency, (ƒr).
At this resonant frequency, the circuits reactance equals its resistance, that is: Xc = R, and the phase difference
between the input and output equals zero degrees. The magnitude of the output voltage is therefore at its
maximum and is equal to one third (1/3) of the input voltage as shown.
It can be seen that at very low frequencies the
phase angle between the input and output
signals is “Positive” (Phase Advanced), while at
very high frequencies the phase angle becomes
“Negative” (Phase Delay). In the middle of these
two points the circuit is at its resonant frequency,
(ƒr) with the two signals being “in-phase” or 0o.
We can therefore define this resonant frequency
point with the following expression.

Where:
ƒr is the Resonant Frequency in Hertz
R is the Resistance in Ohms
C is the Capacitance in Farads
As ZS and ZP are effectively connected together in series across the
input, VIN, they form a voltage divider network with the output taken from
across ZP as shown.
Lets assume then that the component values of R1 and R2 are the same
at: 12kΩ, capacitors C1 and C2 are the same at: 3.9nF and the supply
frequency, ƒ is 3.4kHz.
 At the supply frequency of 3400Hz, or 3.4kHz, the combined DC impedance of the RC parallel
circuit becomes 6kΩ (R||Xc) with the vector sum of this parallel impedance being calculated as:

So we now have the value for the vector sum of the series impedance: 17kΩ, ( ZS = 17kΩ ) and for the parallel
impedance: 8.5kΩ, ( ZP = 8.5kΩ ). Therefore the total output impedance, Zout of the voltage divider network at
the given frequency is:

Then at the oscillation frequency, the magnitude of the output voltage, Vout will be equal to Zout x Vin which as
shown is equal to one third (1/3) of the input voltage, Vin and it is this frequency selective RC network which
forms the basis of the Wien Bridge Oscillator circuit.
If we now place this RC network across a non-inverting amplifier which has a gain of 1+R1/R2 the following
basic Wien bridge oscillator circuit is produced.
 The output of the operational amplifier is fed back to both the inputs of the
amplifier. One part of the feedback signal is connected to the inverting input
terminal (negative or degenerative feedback) via the resistor divider network
of R1 and R2 which allows the amplifiers voltage gain to be adjusted within
narrow limits.
The other part, which forms the series and parallel combinations of R and C
forms the feedback network and are fed back to the non-inverting input
terminal (positive or regenerative feedback) via the RC Wien Bridge network
and it is this positive feedback combination that gives rise to the oscillation.
The RC network is connected in the positive feedback path of the amplifier
and has zero phase shift a just one frequency. Then at the selected resonant
frequency, ( ƒr ) the voltages applied to the inverting and non-inverting inputs
will be equal and “in-phase” so the positive feedback will cancel out the
negative feedback signal causing the circuit to oscillate.

The voltage gain of the amplifier circuit MUST be equal too or greater than three “Gain = 3” for oscillations to start because
as we have seen above, the input is 1/3 of the output. This value, ( Av ≥ 3 ) is set by the feedback resistor network, R1 and R2
and for a non-inverting amplifier this is given as the ratio 1+(R1/R2).
Also, due to the open-loop gain limitations of operational amplifiers, frequencies above 1MHz are unachievable without the
use of special high frequency op-amps.
It is known that the total phase-shift around the circuit must be 0o or 360° for oscillations to occur.
It is achieved when the bridge is balanced, i.e. at resonance. Thus the frequency of oscillation is the
resonant frequency of the balanced Wien Bridge.
Wien-Bridge networks are low frequency oscillators which are used to generate audio and
sub-audio frequencies ranging between 20 Hz to 20 KHz.
Further, they provide stabilized, low distorted sinusoidal output over a wide range of
frequency which can be selected using decade resistance boxes.
In addition, the oscillation frequency in this kind of circuit can be varied quite easily as it just
needs variation of the capacitorsC1and C2.
 Advantages

1. The overall gain of the oscillator is high as it uses a two-stage amplifier.

2. As no inductors are used in the circuit, there is no issue of interference
from external magnetic fields.
3. This oscillator produces a stable sine wave without any distortions.
4. Here, the frequency of the oscillations can be changed by changing the
values of capacitors or by the use of a variable resistor in the circuit.
5. The Wein-bridge oscillator has good frequency stability
Disadvantages
1. The two-stage amplifier type of oscillator requires more devices
for construction.
2. This oscillator cannot generate very high frequencies, because of
the limitations placed on the amplitude and phase-shift values of the
amplifier.
Applications
1. These are highly used for audio testing.
2. Clock signals for testing filter circuits can be generated by this
oscillator.
3. Used in distortion testing of power amplifiers.
4. These are also used as excitation for the AC bridges.
Design a Wien Bridge oscillator for fo = 2 kHz
Determine the maximum and minimum frequency of
oscillations of a Wien Bridge Oscillator circuit having a resistor
of 10kΩ and a variable capacitor of 1nF to 1000nF.
A Wien Bridge Oscillator circuit is required to generate a sinusoidal
waveform of 5,200 Hertz (5.2kHz). Calculate the values of the frequency
determining resistors R1 and R2 and the two capacitors C1 and C2 to
produce the required frequency.
 Quadrature oscillator
Quadrature signals are those two signals of same frequency but separated by a phase shift
of 90° from each other.
The quadrature oscillator circuit shown in Fig. generates two sinusoidal signals that are in
quadrature with each other or with 90° phase difference.
The quadrature oscillator circuit requires dual op-amp formed by A1 and A2 and three RC
combinations.
The two amplifiers are connected in cascade to form a feedback loop.
The op-amp A1 operates as a noninverting integrator.
The op-amp A2 acts as an inverting integrator.
The output of A2 is connected to voltage divider network consisting of R1 – C1 combination
and the voltage across C1 is fed back to the non-inverting input of A1
A total phase shift of 360° is
needed around the loop.
The op-amp A2 acts as an
inverting integrator,
contributing for 270° of phase
shift i.e. 180° due to inverter
arrangement and 90° due to
integrator.
The remaining 90° phase shift is
realized in the voltage divider
R1C1 and op-amp A1.