Ema 5

Analysis, Modeling and Design of Energy
Management and Multisource Power Systems

by
John Jacob Cooley
B.S., E.E., Massachusetts Institute of Technology (2005)
B.S., Physics, Massachusetts Institute of Technology (2005)
M.Eng, Massachusetts Institute of Technology (2007)
Electrical Engineer, Massachusetts Institute of Technology (2009)
Submitted to the Department of Electrical Engineering and Computer
Science
in partial fulfillment of the requirements for the degree of
Doctor of Philosophy in Electrical Engineering
at the
MASSACHUSETTS INSTITUTE OF TECHNOLOGY
June 2011
c John Jacob Cooley, MMXI. All rights reserved.

The author hereby grants to MIT permission to reproduce and
distribute publicly paper and electronic copies of this thesis document
in whole or in part.
Author . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Department of Electrical Engineering and Computer Science
May 20, 2011
Certified by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Steven B. Leeb
Professor, EECS & ME, MacVicar Faculty Fellow
Thesis Supervisor
Accepted by . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Leslie A. Kolodziejski
Chair, Committee on Graduate Students
2
Analysis, Modeling and Design of Energy Management and
Multisource Power Systems
by
John Jacob Cooley
Submitted to the Department of Electrical Engineering and Computer Science

on May 20, 2011, in partial fulfillment of the
requirements for the degree of
Doctor of Philosophy in Electrical Engineering
Abstract
Transformative impacts on our energy security rely on creative approaches for con-
sumption and generation of electricity. Technological contributions can impact both
areas if they focus on problems of scale. For example, occupancy-based electrical loads
(HVAC and lighting) accounted for roughly 50% of the total consumed electricity in
the U.S. in 2008. Meanwhile, roughly 50% of consumed oil in the U.S. is imported.
The U.S. Department of Energy has appropriately identified “sensing and measure-
ment” as one of the “five fundamental technologies” essential for achieving energy
security. Complementing reductions in consumption with increases in deployment of
fossil-fuel-independent generation (solar and wind) and energy storage (batteries, ca-
pacitors and fuel cells) will yield a two-fold impact. Lofty energy security goals can be
made realizable by aggressive application of inexpensive technologies for minimizing
waste and by maximizing energy availability from desirable sources.
Long-standing problems in energy consumption and generation can be addressed
by adding degrees of freedom to sensing and power conversion systems using multiple
electrical sources. This principal drove the invention of the hybrid electric vehicle,
which achieves efficiency increases by combining the energy capacity of gasoline with
the flexible storage capability of batteries. Similarly, fresh strategies for electrical
circuit design, control, and estimation in systems with multiple electrical sources can
minimize consumption, extend the useful life of storage, and improve the efficiency
of generation.
A solar array constitutes a grid or network of panels or cells that may best be
modeled and treated as independent sources needing careful control to maximize
overall power generation. A fuel cell stack, an array of sources in its own right, is
best used in a hybrid arrangement with batteries or capacitors to mitigate the impact
of electrical transients. Meanwhile, room lighting constitutes a network of multiple
electrostatic field sources that can be particularly useful for occupancy detection.
Exploiting performance benefits of multi-source electrical networks requires an
increased flexibility in the analysis required to make informed design choices. This
thesis addresses the added complexity with linear analytical and modeling approaches
3
that reveal the salient features of complicated multisource systems. Examples and
prototypes are presented in capacitive sensing occupancy detectors, hybrid power
systems and multi-panel solar arrays.
Thesis Supervisor: Steven B. Leeb

Title: Professor, EECS & ME, MacVicar Faculty Fellow
4
Acknowledgments
I thank my fiance, Clarissa, for her patience, love and support. I have relied on her
countless times and I am elated to share the rest of my life with her.
I thank my advisor, Steve. I have been constantly amazed by his innate ability to
guide me toward both exciting technical contributions and critical life lessons. I am
certain that I will never adequately express my gratitude toward him.
I thank my committee, Prof. Perreault and Prof. Shaw. Their guidance, insight
and encouragement over the years has been precious on many levels.
I would like to thank my colleagues who contributed to my personal and technical
development and also, in some cases, directly to this thesis: Al Avestruz, Rob Cox,
Chris Laughman, Jim Paris, Warit Wichakool, Uzoma Orji, Chris Schantz, Riccardo
Signorelli, Robert Pilawa, Brandon Pierquet, Dan Vickery, Sabrina Neuman, Zach
Clifford, Zack Remscrim, Alex Crumlin, BJ Thompson, and Shahriar Khushrushahi.
I would like to thank the faculty members from whom I have received valuable insight
and support over the years: Prof. Dawson, Prof. Roberge, Prof. Ram, Prof. Braida,
and Prof. Lee.
I would also like to thank my friends and family, my mom, my brother, and my
sister. Finally, this thesis is dedicated to the memory of my dad.
5
6
Contents
1 Introduction 35
1.1 Thesis Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1.2 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.2.1 Capacitive Sensing Occupancy Detectors . . . . . . . . . . . . 37
1.2.2 Multi-converter Systems . . . . . . . . . . . . . . . . . . . . . 38
1.2.3 Per-panel Photovoltaic Power Processing . . . . . . . . . . . . 38
1.3 Thesis Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
2 Analysis and Modeling of Fully-differential Closed-loop Op-amp Cir-

cuits 41
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
2.1.1 Current Paths in FD Amplifiers . . . . . . . . . . . . . . . . . 43
2.1.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1.3 Scope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
2.1.4 Dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.1.5 Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . 46
2.2 Analysis Step One: Transimpedance Amplifier . . . . . . . . . . . . . 46
2.2.1 Transimpedance Amplifier Output Behavior . . . . . . . . . . 47
2.2.2 Transimpedance Amplifier Input Behavior . . . . . . . . . . . 49
2.2.3 Circuit Models of the Transimpedance Amplifier . . . . . . . . 50
2.2.4 Transimpedance Amplifier Model Validation . . . . . . . . . . 54
2.2.5 The Virtual Short-Circuit Approximation . . . . . . . . . . . . 56
2.3 Analysis Step Two: Voltage Amplifier . . . . . . . . . . . . . . . . . . 56
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2.3.1 Model Correction . . . . . . . . . . . . . . . . . . . . . . . . . 62

2.3.2 Voltage Amplifier Input Impedance . . . . . . . . . . . . . . . 66
2.3.3 Discussion and Model Validation . . . . . . . . . . . . . . . . 68
2.3.4 Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
2.3.5 Finite Op-amp Input Impedance . . . . . . . . . . . . . . . . 74
2.4 Experimental Validation . . . . . . . . . . . . . . . . . . . . . . . . . 75
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
3 Capacitive Sensing Fluorescent Lamps 79

3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
3.2 Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
3.2.1 Modeling the Floor . . . . . . . . . . . . . . . . . . . . . . . . 85
3.2.2 Modeling the Source . . . . . . . . . . . . . . . . . . . . . . . 85
3.2.3 Signal Source Reference . . . . . . . . . . . . . . . . . . . . . 88
3.2.4 Capacitive Models and Limitations . . . . . . . . . . . . . . . 88
3.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
3.3.1 Carrier Suppression . . . . . . . . . . . . . . . . . . . . . . . . 90
3.3.2 Synchronous Detection . . . . . . . . . . . . . . . . . . . . . . 92
3.3.3 Front-end Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.4 Phase-Reference Amplifier . . . . . . . . . . . . . . . . . . . . 97
3.3.5 Electrode Cable Shields . . . . . . . . . . . . . . . . . . . . . 99
3.3.6 Stray Input Capacitances . . . . . . . . . . . . . . . . . . . . 100
3.3.7 Transimpedance Amplifier Stability . . . . . . . . . . . . . . . 101
3.3.8 Fully-differential Synchronous Detector . . . . . . . . . . . . . 106
3.3.9 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.3.10 Op-amp Input-referred Noise . . . . . . . . . . . . . . . . . . . 108
3.3.11 Feedback Resistor Noise . . . . . . . . . . . . . . . . . . . . . 110
3.3.12 Total Narrowband Front-end Output Noise . . . . . . . . . . . 112
3.3.13 Noise in the Synchronous Detector . . . . . . . . . . . . . . . 113
3.3.14 Total Noise at the ADC Input . . . . . . . . . . . . . . . . . . 115
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3.3.15 The Effect of Stray Input Capacitance on Noise . . . . . . . . 116

3.3.16 Time-domain Noise Data . . . . . . . . . . . . . . . . . . . . . 121
3.4 Range Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3.5 Full System Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.5.1 SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
3.5.2 Capacitive Model . . . . . . . . . . . . . . . . . . . . . . . . . 127
3.5.3 Connecting “Earth,” “GND,” and “Common” . . . . . . . . . 131
3.5.4 Simulation Procedure . . . . . . . . . . . . . . . . . . . . . . . 132
3.5.5 Experimental Procedure . . . . . . . . . . . . . . . . . . . . . 133
3.5.6 Model Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . 134
3.5.7 Effective Capacitive Sensitivity . . . . . . . . . . . . . . . . . 135
3.6 Auto-dimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
3.6.1 Dimming Ballast and Lamp Sensor Interface . . . . . . . . . . 139
3.6.2 Auto-dimming Considerations . . . . . . . . . . . . . . . . . . 141
3.6.3 Lamp Sensor SNR across Dimming Levels . . . . . . . . . . . 142
3.6.4 Characterization of Non-idealities . . . . . . . . . . . . . . . . 144
3.6.5 Auto-calibration, Detection and Demonstration . . . . . . . . 148
3.6.6 Quasistatic FM Wireless Link . . . . . . . . . . . . . . . . . . 150
3.6.7 PLL Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
3.6.8 Wireless Link Demonstration and Range . . . . . . . . . . . . 157
4 Dimmable Solid-state Lamp with Integral Occupancy Detection 161

4.1 Introduction: Energy efficient lighting technology . . . . . . . . . . . 161
4.2 Power Electronic LED Drive and Dimming . . . . . . . . . . . . . . . 163
4.2.1 High Brightness LED Modules . . . . . . . . . . . . . . . . . . 163
4.2.2 Switching Current Source LED Driver . . . . . . . . . . . . . 165
4.2.3 Dimming and Inductor Pre-Charging . . . . . . . . . . . . . . 166
4.2.4 Control Circuit Implementation . . . . . . . . . . . . . . . . . 167
4.2.5 Symmetric Tri-State Pulse-Width Modulation . . . . . . . . . 169
4.2.6 Logic Generation . . . . . . . . . . . . . . . . . . . . . . . . . 173
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4.2.7 Analysis of Power Electronic Losses . . . . . . . . . . . . . . . 174

4.3 Experimental Setup and Results . . . . . . . . . . . . . . . . . . . . . 176
4.3.1 Dark Occupancy Sensing . . . . . . . . . . . . . . . . . . . . . 181
4.4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
5 Standalone Capacitive Sensing Occupancy Detectors 187

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
5.2 System Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 188
5.3 System Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
5.4 Active Carrier Suppression . . . . . . . . . . . . . . . . . . . . . . . . 192
5.5 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.6 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
5.7 Detection Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
6 Analysis and Modeling of Feedback-regulated Multi-converter, Multi-

source Power Systems 205
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
6.1.1 Context - Fuel Cell Power Processing . . . . . . . . . . . . . . 210
6.2 Single Converter Systems Review . . . . . . . . . . . . . . . . . . . . 211
6.2.1 Middlebrook’s Linearized Canonical Converter Model . . . . . 212
6.2.2 Converter Transfer Functions . . . . . . . . . . . . . . . . . . 214
6.3 Regulator Example: Voltage Regulated Power System . . . . . . . . . 217
6.4 Canonical Model Generalizations . . . . . . . . . . . . . . . . . . . . 219
6.5 Multi-converter Systems . . . . . . . . . . . . . . . . . . . . . . . . . 220
6.5.1 Linearized Multi-converter Model . . . . . . . . . . . . . . . . 220
6.5.2 Converter Transfer Functions . . . . . . . . . . . . . . . . . . 221
6.6 Regulator Example 1: Dual Voltage-mode Regulated Power System . 227
6.6.1 Closed-Loop Transfer Functions . . . . . . . . . . . . . . . . . 229
6.6.2 Open-Loop Transfer Functions . . . . . . . . . . . . . . . . . . 235
6.7 Regulator Example 2: Master-Slave Current-Voltage Regulated Power
System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238
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6.7.1 Closed-loop Transfer Functions . . . . . . . . . . . . . . . . . 240

6.7.2 Open-Loop Transfer Functions . . . . . . . . . . . . . . . . . . 248
7 The Effect of Multiple Input Filters in Multi-converter, Multi-source

Power Systems 253
7.1 Single Converter Systems Review: The Extra Element Theorem for
Input Filter Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . 254
7.1.1 Review of the EET . . . . . . . . . . . . . . . . . . . . . . . . 254
7.1.2 Modified Converter Transfer Functions in Single-Converter Sys-
tems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255
7.1.3 Modified Feedback Control in Single-Converter Systems . . . . 257
7.1.4 Practical Interpretations and Impedance Inequalities . . . . . 258
7.1.5 Example: Generalized Corrections for Single Converter Systems 260
7.2 Multi-converter Systems: The 2EET for Multiple Input Filter Evaluation267
7.2.1 The 2EET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267
7.2.2 Modified Converter Transfer Functions in Multi-Converter Sys-
tems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268
7.2.3 Modified Feedback Control in Multi-Converter Systems . . . . 268
7.2.4 Practical Interpretations and Impedance Inequalities . . . . . 269
7.2.5 Example: Correction Factors for v̂/dˆ1 , v̂/dˆ2 , îo1 /dˆ1 , and îo1 /dˆ2
in a Hybrid Power System . . . . . . . . . . . . . . . . . . . . 269
7.3 Numerical Computation of High Order Rational Polynomials . . . . . 277
8 Design Example 1: Run-time Integral Diagnostics of a Grid-Tied

Fuel Cell 279
8.1 Fuel Cell Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280
8.1.1 Fuel Cell Impedance Spectroscopy . . . . . . . . . . . . . . . . 281
8.1.2 Parametric Modeling and Identification . . . . . . . . . . . . . 283
8.2 Dual Voltage Regulated Power System Architecture . . . . . . . . . . 285
8.3 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
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8.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297
9 Design Example 2: Run-time Integral Diagnostics of a Fuel Cell

under Unmanned Aerial Vehicle Load Profiles 301
9.1 Current-Voltage Regulated Power System Architecture . . . . . . . . 302
9.2 Feedback Compensation . . . . . . . . . . . . . . . . . . . . . . . . . 303
9.3 Closed-Loop Responses . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9.3.1 Low Frequency Fuel Cell Current Buffering . . . . . . . . . . . 307
9.4 Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 308
9.5 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
9.5.1 Gain-Lead Compensator-Subtractor . . . . . . . . . . . . . . . 314
9.6 Measured Step Responses . . . . . . . . . . . . . . . . . . . . . . . . 314
9.7.1 Reference Simulator . . . . . . . . . . . . . . . . . . . . . . . 326
9.8 UAV Flight Plans . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
9.9 Empirically-based Frequency Precompensator . . . . . . . . . . . . . 331
9.10 Fuel Cell Impedance Results . . . . . . . . . . . . . . . . . . . . . . . 335
9.10.1 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340
10 Per-Panel Photovoltaic Energy Extraction with Switched-capacitor

Multilevel Output DC/DC Converters 343
10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343
10.1.1 System Overview . . . . . . . . . . . . . . . . . . . . . . . . . 346
10.1.2 Switched-capacitor Benefits . . . . . . . . . . . . . . . . . . . 347
10.1.3 Total Efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . 348
10.2 Maximum Power Point Tracking . . . . . . . . . . . . . . . . . . . . . 349
10.2.1 PV Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349
10.2.2 Local Maximum Power Point Tracking . . . . . . . . . . . . . 351
10.2.3 Global Maximum Power Point Tracking . . . . . . . . . . . . 353
10.2.4 Statistical Performance Evaluation . . . . . . . . . . . . . . . 355
10.2.5 Effect of spatial panel separation . . . . . . . . . . . . . . . . 357
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10.3 Switched-capacitor Implementation . . . . . . . . . . . . . . . . . . . 359

10.3.1 Efficient Switching Patterns . . . . . . . . . . . . . . . . . . . 359
10.3.2 Linear Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 362
10.3.3 Switching Loss . . . . . . . . . . . . . . . . . . . . . . . . . . 364
10.3.4 Inherent Features . . . . . . . . . . . . . . . . . . . . . . . . . 365
10.3.5 Gate Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366
10.3.6 Non-integral Level Selections . . . . . . . . . . . . . . . . . . . 367
10.4 Simulated Prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . 367
10.4.1 Number of Levels . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.4.2 MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.4.3 Power Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368
10.4.4 Simulated Performance . . . . . . . . . . . . . . . . . . . . . . 370
10.4.5 Model Validation . . . . . . . . . . . . . . . . . . . . . . . . . 370
10.5 Experimental Prototype . . . . . . . . . . . . . . . . . . . . . . . . . 373
10.5.1 Photovoltaic Circuit Model Implementation . . . . . . . . . . 374
10.5.2 Experimental Prototype Performance . . . . . . . . . . . . . . 378
10.6 Efficiency Optimizations . . . . . . . . . . . . . . . . . . . . . . . . . 382
10.6.1 Standby Power . . . . . . . . . . . . . . . . . . . . . . . . . . 382
10.6.2 Run-Time Zener Biasing Optimization . . . . . . . . . . . . . 384
10.6.3 Run-Time Frequency Scaling . . . . . . . . . . . . . . . . . . . 386
10.7 Input Current-controlled Inverter Dynamics . . . . . . . . . . . . . . 386
10.8 Conclusions and Further Work . . . . . . . . . . . . . . . . . . . . . . 387
11 Conclusion 389
A Capacitive Sensing Occupancy Detection 391

A.1 Lamp Sensor Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . 392
A.1.1 Photographs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
A.1.2 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394
A.1.3 Schematic Drawings . . . . . . . . . . . . . . . . . . . . . . . 400
A.1.4 Build Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403
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A.1.5 BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

A.2 Dimming Ballast Hardware . . . . . . . . . . . . . . . . . . . . . . . 405
A.2.1 Photographs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406
A.2.2 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407
A.2.3 Schematic Drawings . . . . . . . . . . . . . . . . . . . . . . . 413
A.2.4 Build Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
A.2.5 BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414
A.2.6 Inductor Specifications . . . . . . . . . . . . . . . . . . . . . . 416
A.3 Lamp Sensor Software . . . . . . . . . . . . . . . . . . . . . . . . . . 419
A.3.1 PIC Microcontroller Operating System . . . . . . . . . . . . . 420
A.3.2 Matlabr Sensing and Real-time Measurements . . . . . . . . 426
A.3.3 Matlabr Time-domain Windowed Noise Measurements . . . 430
A.4 Lamp Sensor Full System Simulation . . . . . . . . . . . . . . . . . . 433
A.4.1 SPICE Model Output Voltage Extraction . . . . . . . . . . . . 433
A.4.2 Fully Differential Amplifier Circuit Model Netlist . . . . . . . 440
A.4.3 Full System Simulation SPICE Parameters . . . . . . . . . . . 441
A.4.4 Example Capacitances . . . . . . . . . . . . . . . . . . . . . . 442
A.5 Lamp Sensor Practice . . . . . . . . . . . . . . . . . . . . . . . . . . . 444
A.5.1 Matlabr Interface and Demonstration . . . . . . . . . . . . 444
A.5.2 Nulling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446
A.5.3 Grounding, Stray Current Return Paths, and Safety Isolation 447
A.5.4 Modifying Off-the-shelf Fluorescent Lamps . . . . . . . . . . . 448
A.5.5 Programming the PIC Microcontroller . . . . . . . . . . . . . 449
A.5.6 Required PCB Cleaning . . . . . . . . . . . . . . . . . . . . . 451
A.6 Standalone Sensor Software . . . . . . . . . . . . . . . . . . . . . . . 453
A.6.1 Matlabr Detection Pattern Data Collection . . . . . . . . . 453
A.7 Fully-Differential Amplifier Detailed Derivations . . . . . . . . . . . . 461
A.7.1 Derivation of Transconductances using the Virtual Short-ckt.
Approximation . . . . . . . . . . . . . . . . . . . . . . . . . . 461
A.7.2 Derivation of Ycd′ using the corrected circuit model . . . . . . . 474
14
Contents
B Multi-converter Systems 479

B.1 Master-Slave Current-Voltage Regulator Hardware . . . . . . . . . . . 480
B.1.1 Photograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480
B.1.2 Schematic Drawings . . . . . . . . . . . . . . . . . . . . . . . 481
B.2 Matlabr Scripts for Multi-converter System Modeling . . . . . . . . 484
B.2.1 Master-slave Current-voltage Regulated Power System Evaluation484
B.3 Derivation of Special-case Impedances for îo1 /dˆ1 . . . . . . . . . . . . 503
B.4 Derivation of Special-case Impedances for îo1 /dˆ2 . . . . . . . . . . . . 505
C Switched-capacitor Multilevel Output DC/DC Converters 509

C.1 Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
C.1.1 Photograph . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
C.1.2 PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511
C.1.3 Schematic Drawings . . . . . . . . . . . . . . . . . . . . . . . 515
C.1.4 Build Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522
C.1.5 BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523
C.2 Matlabr Scripts for Switched-capacitor System Modeling . . . . . . 524
C.2.1 Monte Carlo Performance Prediction . . . . . . . . . . . . . . 524
D Switched-capacitor DC/DC Marx Converter Loss Models 541

D.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541
D.1.1 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . 542
D.1.2 Analytical and Model Validation Approaches in this Work . . 543
D.2 Switching Speed Limit Definitions . . . . . . . . . . . . . . . . . . . . 544
D.2.1 Generalization of SSL to Finite R-C Loads . . . . . . . . . . . 547
D.3 Switching Pattern Classification of Marx Converters . . . . . . . . . . 548
D.4 3-Level Marx Switch States . . . . . . . . . . . . . . . . . . . . . . . 549
D.5 Class-I Marx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551
D.6 Class-II Marx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
D.6.1 Extension to 4-Level Example . . . . . . . . . . . . . . . . . . 566
D.7 Class-III Marx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573
15
Contents
D.8 Discussion, Conclusion, and Further Work . . . . . . . . . . . . . . . 578
16
List of Figures
2-1 A FD closed-loop op-amp circuit . . . . . . . . . . . . . . . . . . . . 42

2-2 Small-signal current paths in closed-loop op-amp amplifiers. . . . . . 44
2-3 A FD transimpedance amplifier small-signal model. . . . . . . . . . . 48
2-4 A FD transimpedance amplifier and two approximate small-signal mod-
els. The T-model and the Π-model differ in the structure of their input
network. Each contain an internal node labeled ecc . . . . . . . . . . . 51
2-5 Validating the transimpedance amplifier model. . . . . . . . . . . . . 55
2-6 Adding the input elements onto the transimpedance amplifier model
yields a voltage-mode amplifier model. . . . . . . . . . . . . . . . . . 59
2-7 Accuracy improvement for small-mismatch Avc . . . . . . . . . . . . . 63
2-8 Validating the voltage amplifier model: Avd . Impedances are purely
real (resistive). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2-9 Validating the voltage amplifier model: Avc . Impedances are purely
real (resistive). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2-10 Finite op-amp CM gains, ad and ac , lead to a null in the CMRR at
nonzero mismatch values. . . . . . . . . . . . . . . . . . . . . . . . . . 72
2-11 Plots of CMRR for various multiplicative errors in op-amp gain ad
compared to the actual CMRR for the Linear Technology part LT6404-1. 74
2-12 Plot of simulated and measured occupancy sensor output data from
reference [1]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
2-13 A simplified schematic of the fully-differential signal conditioning elec-
tronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
17
List of Figures
3-1 Examples of systems with human conductor models taken from refer-
ences [2–9]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
3-2 Capacitive loading impedances on the signal source are very large com-
pared to the Thevenin resistance of the source. . . . . . . . . . . . . . 86
3-3 Alternating linear voltage profile of a resistive bulb. . . . . . . . . . . 87
3-4 Two bulb halves comprise the lumped element model of a single bulb. 87
3-5 A diagram of the two-bulb fluorescent lamp and electrodes. The elec-
trodes are spaced symmetrically about the center of the lamp. . . . . 90
3-6 Reversing the connections to one bulb in a two-bulb lamp yields the
desired symmetry in the electric field source. . . . . . . . . . . . . . . 91
3-7 A fully-differential transimpedance amplifier and its approximate small-
signal model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
3-8 A block diagram of the signal conditioning system. Transimpedance
amplifiers are marked with a ‘Z’. . . . . . . . . . . . . . . . . . . . . 92
tronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
3-10 A circuit for calculating the loop transfer function in a FD amplifier. 101
3-11 Open-loop frequency responses showing suitable phase margin. . . . . 104
3-12 Bode plot of the loop transfer function for the uncompensated system
(Cf = 0) showing poor phase margin. . . . . . . . . . . . . . . . . . . 106
3-13 Noise in the front-end amplifier. . . . . . . . . . . . . . . . . . . . . . 111
3-14 Power spectral density of noise voltage due to feedback resistors. . . . 112
3-15 Phasor diagram for additive noise [10]. . . . . . . . . . . . . . . . . . 114
3-16 Noise in the front-end amplifier with stray input capacitances. . . . . 120
3-17 Time-domain noise data taken from an experimental prototype lamp
sensor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
3-18 A photograph of the cart-mounted lamp experimental setup . . . . . 122
3-19 Examples of plots of sample detections from the range test. (Configu-
ration 44x5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
3-20 A screenshot of the FastCapr 3D model . . . . . . . . . . . . . . . . 127
18
List of Figures
3-21 An example FastCapr output matrix . . . . . . . . . . . . . . . . . . 128
3-22 Fluorescent bulb voltage (top) and current (bottom). . . . . . . . . . 131
3-23 Photographs of the hanging lamp experimental setup. . . . . . . . . . 134
3-24 Comparison between simulated and measured occupancy sensor output

data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
3-25 A SPICE simulation of the capacitive model, F-D Transimpedance

Amplifier Front end and the signal conditioning electronics. . . . . . . 137
3-26 The block diagram of the auto-dimming lamp sensor. Transimpedance

amplifiers are marked with a ’Z’. . . . . . . . . . . . . . . . . . . . . 139
3-27 A simplified schematic of the frequency-controlled dimming ballast.

The ballast is designed around the International Rectifier part IR21592
[11]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
3-28 The optical isolator separates the lamp sensor common potential from
the ballast common potential. The soft-start protects the bulb by
clamping the dim signal to the range 0.5-5 V and brings the dim signal
down slowly on startup. . . . . . . . . . . . . . . . . . . . . . . . . . 141
3-29 A curve fit of the rms bulb voltage plotted against lamp power (which
increases with rms current) shows the familiar negative incremental
resistance of the bulb. . . . . . . . . . . . . . . . . . . . . . . . . . . 143
3-30 A curve fit of the detection signal bulb voltage plotted against lamp
power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
3-31 A curve fit of the SNR plotted against lamp power shows a maximum
SNR around 40% power. . . . . . . . . . . . . . . . . . . . . . . . . . 145
3-32 The lamp sensor output voltage for repeated switching between dim-
ming levels. The two lamp power levels in this example are 8.1%(dim)
and 59.4% (bright). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
3-33 Example Drift Plots for the Lamp Sensor output voltage. Both plots
show data taken for a lamp power level of 8.1% (dim). . . . . . . . . 147
19
List of Figures
3-34 This plot is a screenshot of the display for the autodimmer. It shows the
output voltage varying with the target and the two different baselines
taken from the auto-calibration. Jumps in the output voltage can be
used to determine when the lamp dimmed or brightened. . . . . . . . 149
3-35 A notional picture of the quasistatic wireless link system. . . . . . . . 150
3-36 The wireless link receiver and the PLL dynamical block diagram. . . 151
3-37 Bode plot of the loop transfer function of the PLL. . . . . . . . . . . 155
3-38 Bode plot of the closed-loop transfer function of the PLL. . . . . . . . 156
3-39 Simulated step response from the input signal to the VCO input in the
PLL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
3-40 Measured step response using an FM-capable Agilent signal generator. 158
3-41 The PLL step response with the lamp in the system shows a slower
rise time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
3-42 Wireless link demonstration . . . . . . . . . . . . . . . . . . . . . . . 159
3-43 The measured wireless link range between the closest edge of the trans-
mitting lamp and the receiving lamp’s electrode. . . . . . . . . . . . . 160
4-1 Bidirectional LED modules. . . . . . . . . . . . . . . . . . . . . . . . 164

4-2 Schematic of the bipolar LED driver. Transformer T1 isolates the in-
verter output. Transformer T2 matches the currents between the two
LED bulbs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
4-3 Hysteretic Current Controller. . . . . . . . . . . . . . . . . . . . . . . 167
4-4 Example Hysteretic Controller Waveforms. Top: Current-sense voltage
Vsense. Bottom: Comparator non-inverting input V+ . . . . . . . . . . 168
4-5 Timing Diagram Using Continuous Inductor Current. . . . . . . . . . 170
4-6 Waveforms at 96% Duty-Cycle with Continuous Inductor Current. . . 171
4-7 Timing Diagram Using Inductor Pre-Charging [and Energy Recovery.]172
4-8 Waveforms at 10% Duty-Cycle with Inductor Current Pre-Charge. . . 173
4-9 A photograph of the LED lamp. Top: bright, Bottom: dim. . . . . . 175
4-10 The experimental setup. . . . . . . . . . . . . . . . . . . . . . . . . . 178
20
List of Figures
4-11 Training runs (source calibration) x = 0 cm . . . . . . . . . . . . . . 179

4-12 LED lamp sensor measured and predicted responses. . . . . . . . . . 180
4-13 I-V curve of LED lamp module. (a) is the classic diode characteristic,
but closer inspection of the log plot in (b) reveals the non-idealities in
real devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
4-14 Comparison of capacitive sensor output at dark (100 µA) and lighted
(10 mA) LED current levels for an average height subject walking back
and forth along the axis of the lamps. . . . . . . . . . . . . . . . . . . 183
5-1 The capacitive sensor would resemble the PIR motion sensor in both
form and function, but would provide true presence detection. . . . . 188
5-2 Closely spaced electrode configurations . . . . . . . . . . . . . . . . . 190
5-3 Distantly spaced electrode configurations . . . . . . . . . . . . . . . . 190
5-4 A simplified model of the two-electrode stand alone sensor using a FD
measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
5-5 A simplified model of the single-electrode stand alone sensor with active
carrier suppression using a FD measurement . . . . . . . . . . . . . . 192
5-6 The stand alone sensor experimental setup with customizable electrode
configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
5-7 A typical Matlabr plot window and detection field experimental
setup. In this single measurement electrode configuration, footsteps
are apparent in the detection (bottom plot of (b)). Approximately 10
datapoints correspond to 1 sec. . . . . . . . . . . . . . . . . . . . . . 196
5-8 1 meas., 1 source, distantly spaced. . . . . . . . . . . . . . . . . . . . 199
5-9 1 meas., 1 source, closely spaced for various vertical spacings between
source and measurement. . . . . . . . . . . . . . . . . . . . . . . . . . 200
5-10 2 meas., 1 source (high), closely spaced for various vertical spacings
between source and measurement. . . . . . . . . . . . . . . . . . . . . 201
5-11 1 meas., 2 source (high and earth ground), closely spaced for various
vertical spacings between source and measurement. LO: earth ground. 202
21
List of Figures
5-12 2 meas., 2 source, closely spaced for various vertical spacings between
source and measurement. LO: earth ground. . . . . . . . . . . . . . . 203
tronics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
6-1 The analysis in this chapter focuses on steps 1-4. The approach is
reviewed for single converter systems, then extended to multi-converter
systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
6-2 Canonical circuit modeling developed in references [12, 13] and [14]. . 213
6-3 The converter switching section can be represented by an input output
dynamical block diagram consisting of the relevant converter transfer
functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215
6-4 A linearized converter model inserted into a voltage-mode feedback
control loop [14]. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218
6-5 The linearized multi-converter model. The battery and fuel cell source
are examples of sources in a multi-source power system. . . . . . . . . 221
6-6 The multi-converter switching section can be represented by an input
output dynamical block diagram consisting of the relevant converter
transfer functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
6-7 Dual voltage regulator system linearized model . . . . . . . . . . . . . 228
6-8 Dual voltage regulator system block diagram . . . . . . . . . . . . . . 229
6-9 Master-slave regulator system linearized model . . . . . . . . . . . . . 238
6-10 Master-slave regulator system block diagram . . . . . . . . . . . . . . 239
7-1 The EET can be applied by considering the special-case impedances

at the extra element port. . . . . . . . . . . . . . . . . . . . . . . . . 256
7-2 A typical frequency plot of the special case impedances, Zn−c (s), Zo−l (s),
and the input filter output impedance, Zo (s), for a single converter sys-
tem. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
7-3 Calculating special-case impedances from the canonical circuit model 261
7-4 Multiple input filters added to a dual voltage-regulated power system. 270
22
List of Figures
7-5 The circuit used for calculating the special-case impedances for the
2EET correction factors. . . . . . . . . . . . . . . . . . . . . . . . . . 271
8-1 Conceptual diagram of SOFC energy conversion. . . . . . . . . . . . . 280
8-2 A 5 kW Siemens / Fuel Cell Technology stack used for testing. . . . . 282
8-3 A hybrid power system with EIS functionality built from off-the-shelf
components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286
8-4 An oscilloscope screen shot showing the battery and fuel cell currents
during run-time EIS (≈100 Hz). Top to bottom: load voltage (ch2),
fuel cell current (ch3),battery current (ch4), control signal (ch1). . . . 287
8-5 io2 /io1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289
8-6 |iin1 /vref 1 |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
8-7 |v/iref 1|. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290
8-8 The input filter for the fuel cell converter. . . . . . . . . . . . . . . . 291
8-9 The current transfer function for the fuel-cell leg input filter . . . . . 292
8-10 The special case impedances for correcting v̂/dˆ1 and the input filter
output impedances with system parameters: VF C = 28V, Vbatt = 48V,
Vout =12V, R = 2Ω, Le = 1µH, Ce = 1µF . . . . . . . . . . . . . . . . 293
8-11 Correction factors CF (1) and CF (2) with system parameters: VF C =

28V, Vbatt = 48V, Vout =12V, R = 2Ω, Le = 1µH, Ce = 1µF . . . . . . 295
8-12 Schematic illustration of stack, power electronics, and measurements.

Components within the dashed line are within the physical envelope
of the Siemens Alpha 8 unit. . . . . . . . . . . . . . . . . . . . . . . . 296
8-13 Measured and predicted stack current as a function of time. . . . . . 297
8-14 Stack current and voltage, measured as indicated in fig:hybridex1 8-

12. The triangle current waveform in 8-14(a) is due to the operation
of the DC/DC converter in the system. The corresponding voltage of
the stack appears in 8-14(b). . . . . . . . . . . . . . . . . . . . . . . 298
23
List of Figures
8-15 Whole stack impedance spectroscopy results. (a) Stack response to rip-
ple current and power electronic test signal. (b) Low-frequency portion
of stack response showing response to power electronic test signal. . . 299
9-1 A hybrid power system with EIS functionality built upon a Master-
Slave current-voltage regulated architecture. . . . . . . . . . . . . . . 304
9-2 Open-loop bode plots indicate tradeoffs among loop bandwidth, switch-
ing frequency attenuation and stability. . . . . . . . . . . . . . . . . . 305
9-3 Simulated closed-loop bode plots indicate suitable fuel cell excitation
current bandwidth, good load voltage regulation and good fuel cell
current buffering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
9-4 Closed loop response from load current to fuel cell current with 500
mΩ of extra inductor ESR. . . . . . . . . . . . . . . . . . . . . . . . . 307
9-5 The basic input filter topology . . . . . . . . . . . . . . . . . . . . . . 308
9-6 The tradeoff between input filter negative phase contribution and band-
width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
9-7 Input filter transfer functions . . . . . . . . . . . . . . . . . . . . . . 311
9-8 Extra element correction factors for the voltage feedback loop . . . . 312
9-9 Extra element correction factors for the current feedback loop . . . . 313
9-10 The lead compensator subtractor and gain circuit . . . . . . . . . . . 315
9-11 First converter’s control voltage to first converter’s output current.

Ch1: v̂ref 1 , ch4: îo1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
9-12 Second converter’s control voltage to load voltage. Ch1: v̂ref 2 , ch2: v̂ 318
9-13 Load current to first converter’s input current. Ch1: îload , ch4: îiin1 . 319
9-14 The experimental setup block diagram with the Montana State Uni-
versity fuel cell reference simulator. . . . . . . . . . . . . . . . . . . . 320
9-15 A photograph of the full experimental setup including the data acqui-
sition system, power converters, measurement and power supplies, and
the fuel cell setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
24
List of Figures
9-16 A photograph of the two solid-oxide fuel cell ovens, temperature con-
trol units and mass flow controllers used in the integral diagnostics
experiments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
9-17 A closeup photograph of the two solid-oxide fuel cell ovens, tempera-
ture control units and mass flow controllers used in the integral diag-
nostics experiments. . . . . . . . . . . . . . . . . . . . . . . . . . . . 323
9-18 A closeup photograph of the mass flow controllers used to control the
flow of Oxygen and Hydrogen into the solid-oxide fuel cell ovens. . . . 323
9-19 A photograph of the two-converter current-voltage regulated power
system connected to the data acquisition system in the fuel cell exper-
imental setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
9-20 A closeup photograph of the data acquisition system buffers and low
pass filters in the fuel cell experimental setup. . . . . . . . . . . . . . 325
9-21 A closeup photograph of the reference simulator electronics in the fuel
cell experimental setup. . . . . . . . . . . . . . . . . . . . . . . . . . . 326
9-22 Data for three different flight plans made available through a collabo-
ration with the USAF. . . . . . . . . . . . . . . . . . . . . . . . . . . 328
9-23 Oscilloscope traces showing EIS operation during flight plans: ch1:
Battery Voltage ch2: Battery Current ch3: Fuel Cell Voltage ch4: Fuel
Cell Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330
9-24 FC currents during EIS sweeps 0.1 Hz to 1 kHz showing the need for
the frequency precompensator. . . . . . . . . . . . . . . . . . . . . . . 331
9-25 The EIS control signal frequency precompensator constructed based
on observations of the inductive fuel cell source impedance effect on
the transmission of excitation currents to the fuel cell terminals. . . . 333
9-26 With Precompensator: 50 mVp−p from EIS37 (Flight Plan 3) . . . . . 334
9-27 Control experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . 336
9-28 EIS with a fixed load (no flight plan), If c = 4 A . . . . . . . . . . . . 337
9-29 Single Cell EIS during Flight Plan 3 for two different time segments,
If c = 4 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338
25
List of Figures
9-30 Nyquist plots showing measured impedances during flight plans. . . . 339
9-31 Pre-degrade, If c = 4.1 A, degraded If c = 4 A, post-recovery, If c = 4 A 340
9-32 A circuit model of a solid-oxide fuel cell taken from reference [15]. . . 342
10-1 Simple series connections of PV panels, unshaded and partially shaded 344
10-2 3 panel system tracking efficiencies showing the effect of partial shad-
ing on a series string with an oversimplified global maximum power
tracking approach. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
10-3 A series connection of PV panels becomes a series connection of con-
verters processing power from their respective panels. . . . . . . . . . 346
10-4 A DC linearized model with an N-panel PV string illustrates the
system-level approach. The ideal transformers model the function of
the DC/DC MICs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347
10-5 Specific cost and volume: Discrete inductors (10 µH- 1 mH/100 mA-1
A) and capacitors (Ceramic and Film 1-10 µF/10-100 V) sampled from
Digikey. Energy was calculated as 12 CV 2 or 12 LI 2 for maximum rated
voltages and currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . 348
10-6 A literature survey of total energy extraction efficiency, DC/DC MICs:
[16–23] and MPPT algorithms: [23–28] . . . . . . . . . . . . . . . . . 349
10-7 PV circuit model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350
10-8 A single Io sweep: 3 panels, Qavail = [0,1,2,3,4], Imp,vec = [6.898, 4.503,
4.878] A, ∆Io = 1 mA . . . . . . . . . . . . . . . . . . . . . . . . . . 353
10-9 A hypothetical MPPT timing diagram for one inverter input current
step. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354
10-10Monte Carlo performance prediction: Qavail = [0 : 1 : Qmax ], Monte
Carlo Length = 200, Io,sweep = [0.01 : 0.02 : 6.93] A . . . . . . . . . . 356
10-11Monte Carlo simulation: Qavail = [0 : 1 : Qmax ], Monte Carlo Length
= 200, Io,sweep = [0.01 : 0.02 : 6.93] A, Compressed Distributions . . . 358
10-12A 5-Level Marx converter . . . . . . . . . . . . . . . . . . . . . . . . 359
10-13Switching configurations . . . . . . . . . . . . . . . . . . . . . . . . . 361
26
List of Figures
10-14The canonical circuit for studying the fundamental loss associated with
charging a capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
10-15Switching loss evaluation in the Marx converter for active MOSFETs 364
10-16The recommended gate drive adapted from IR AN-978 [29]. . . . . . 366
10-17A 5-Level Marx converter having the added output diode and capacitor.368
10-18Unoptimized system performance prediction: Qavail = [0 : 1 : Qmax ],
Monte Carlo Length = 400, Io,sweep = [0.01 : 0.02 : 6.93] A, C = 12.5
µF, fsw = 250 kHz, Rdson = 10 mΩ, Qg = 10 nC, Qoss = 5 nC, Qrr =
25 nC,Vg = 15 V, Voc = 29 V, Vmp = 24.6 V, Isc = 7.38 A, Imp = 6.93
A, Distribution Compression = 50% . . . . . . . . . . . . . . . . . . . 369
10-19Model Validation: Single Io sweep, 3 sources, Q = [0, 2, 4], Imp,vec =
[0.007 3.465 6.93] A, C = 12.5 µF, fsw = 360 kHz, MOSFET: IRF8721,
Vg = 10 V, deadtime = 100 ns, Rg = 4 Ω . . . . . . . . . . . . . . . . 371
10-20Time-domain waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 372
10-21A connection diagram depicting the experimental setup for the series
connection of Marx modules and PV circuit models. . . . . . . . . . . 374
10-22A photograph of the switched-capacitor (Marx) converter photovoltaic
experimental validation system. . . . . . . . . . . . . . . . . . . . . . 375
10-23The experimental PV circuit model construction. . . . . . . . . . . . 375
10-24Experimental validation of the artificial PV circuit models. . . . . . . 377
10-25Model Validation: Single Io sweep, 3 sources, Q = [0, 2, 4], Imp,vec =
[0.007 3.465 6.93] A, C = 12.5 µF . . . . . . . . . . . . . . . . . . . . 379
10-26Switching frequency choice for the experimental system . . . . . . . . 380
10-27Charge pump operation for M6 in the Q = 2 module. Ch1: VOU T , ch2:
VS , ch3: VB , math: VBS . . . . . . . . . . . . . . . . . . . . . . . . . 381
10-28A possible run time zener bias resistor selection circuit . . . . . . . . 385
10-29A linearized model of an input current-controlled inverter front-end. . 387
10-30Inverter closed-loop step responses . . . . . . . . . . . . . . . . . . . 388
A-1 Photographs of the lamp sensor electronics and electrodes. . . . . . . 393
27
List of Figures
A-2 The Eagle Cadr PCB layout of the lamp sensor, Rev 2. . . . . . . . . 394
A-3 The Eagle Cadr PCB layout of the lamp sensor, Rev 2 without ground
and power planes drawn. . . . . . . . . . . . . . . . . . . . . . . . . . 395
A-4 Top copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396
A-5 Bottom copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 397
A-6 Inner copper layer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 398
A-8 The analog section of the Eagle Cadr schematic of the lamp sensor,
Rev 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400
A-9 The digital section of the Eagle Cadr schematic of the lamp sensor,
Rev 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
A-10 The ancillary sections of the Eagle Cadr schematic of the lamp sensor,
Rev 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
A-11 Photographs of the dimming ballast, Rev. 2 PCB. . . . . . . . . . . . 406
A-12 The Eagle Cadr PCB layout of the dimming ballast, Rev 2. . . . . . 407
A-13 The Eagle Cadr PCB layout of the dimming ballast, Rev 2 without
ground and power planes drawn. . . . . . . . . . . . . . . . . . . . . . 408
A-14 Top copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409
A-15 Bottom copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 410
A-18 Dimming ballast, Rev. 2 schematic . . . . . . . . . . . . . . . . . . . 413
A-19 Dimming ballast, Rev.2 bill of materials. . . . . . . . . . . . . . . . . 415
A-20 Dimming ballast, Rev.2 resonant inductor specification. . . . . . . . . 416
A-21 Dimming ballast, Rev.2 current share (balance) transformer specification.417
A-22 Dimming ballast, Rev.2 power factor correction (pfc) transformer spec-
ification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418
A-23 Flow chart of PIC microcontroller “operating system” listed in A.3.1. 419
28
List of Figures
A-24 A screenshot of a Matlabr demonstration output window showing

the lampsensor output voltage. Top: auto-zooming window, Middle:
fixed-scale window, Bottom: Event history window . . . . . . . . . . 445
A-25 A photograph of an adjustable electrode . . . . . . . . . . . . . . . . 446
A-26 A photograph of the MPLab ICD 2 programmer puck connected to the
lamp sensor board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450
A-27 A photograph of the MPLab ICD 2 connector used for the lamp sensor
revisions 1 and 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452
B-1 A closeup photograph of the two-converter current-voltage regulated

power system deployed in the fuel cell experimental setup. . . . . . . 480
B-2 Switching sections and feedback control circuits. ‘A’, ‘B’, ‘C’, ‘Vdd’,
‘Vss’, labels above switching section nodes correspond to edge connec-
tors on the Totem Cards for the respective converters (fuel cell and
battery). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481
B-3 Gate drives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482
B-4 Linear regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
C-1 A closeup photograph of the two marx converters in the experimental

setup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510
C-2 The Eagle Cadr PCB layout of the marx converter. . . . . . . . . . . 511
C-3 The Eagle Cadr PCB layout of the marx converter without ground
and power planes drawn. . . . . . . . . . . . . . . . . . . . . . . . . . 512
C-4 Top copper layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513
C-5 Bottom copper layer . . . . . . . . . . . . . . . . . . . . . . . . . . . 514
C-6 Switching section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515
C-7 Gate drives, sheet 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516
C-10 Switching pattern selection switches . . . . . . . . . . . . . . . . . . . 519
C-11 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520
29
List of Figures
C-12 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521
D-1 The simple two-port model of switched-capacitor DC/DC converters

proposed by Seeman. The model captures open-circuit voltage, load
regulation and loss with one ideal transformer and one resistor [30]. . 542
D-2 In the SSL, capacitor voltages equilibrate each half-cycle and currents
are impulsive. In the FSL, capacitor voltages are constant and capac-
itor currents are fixed during each half cycle in the big capacitance
limit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545
D-3 The canonical circuit for studying the fundamental loss associated with
charging a capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . 546
D-4 In the SSL, the capacitors have time to fully equilibrate. With a finite
R-C load, the output voltage ripple allows for a time-varying equili-
bration point during some phases. . . . . . . . . . . . . . . . . . . . . 547
D-5 3-level marx converter example FET implementation and the ideal
switch implementation used for the analysis here. . . . . . . . . . . . 550
D-6 0-output switch states. . . . . . . . . . . . . . . . . . . . . . . . . . . 551
D-7 1-states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
D-8 The only 2-state (2). . . . . . . . . . . . . . . . . . . . . . . . . . . . 553
D-9 The two simplified switching states of the class-1 converter. . . . . . . 553
D-10 Load regulation in the SSL class-I three-level marx for D=0.5. . . . . 555
D-11 SSL Class-I simulated load regulation and η: the fundamental behavior
of the marx converter changes between DC/DC mode (big Cload ) and
DC/AC mode (small Cload ). . . . . . . . . . . . . . . . . . . . . . . . 557
D-12 Model and simulation of load regulation and efficiency plots at FSL for
the Class-I marx converter. . . . . . . . . . . . . . . . . . . . . . . . . 560
D-13 The recharging state. . . . . . . . . . . . . . . . . . . . . . . . . . . . 561
D-14 The two simplified switching states of the class-1 converter. . . . . . . 562
D-15 Simulated and modeled output resistance across switching speed limits. 564
30
List of Figures
D-16 Model and simulation of load regulation and efficiency plots at SSL
and FSL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565
D-17 Simulated and modeled efficiency, η, vs. Rload across duty ratio, D. . 566
D-18 4-level marx converter example FET implementation and the ideal
switch implementation used for the analysis here. . . . . . . . . . . . 567
D-19 The simplified switching states of the four-level class-2 converter for
boosting to twice the input voltage. . . . . . . . . . . . . . . . . . . . 568
D-20 The simplified switching states of the four-level class-2 converter for
boosting to three times the input voltage. . . . . . . . . . . . . . . . 570
D-21 Model and simulation agreement of load regulation and efficiency for
the four-level marx boosting to three times the input voltage. . . . . 572
D-22 The four simplified switching states of the class-III converter. Phases
1 and 3 are the same recharging switch state. . . . . . . . . . . . . . . 573
D-23 The loss and load regulation model for the class-III marx. . . . . . . . 574
D-24 Model and simulation agreement of load regulation and efficiency for
the three-level class-III marx. . . . . . . . . . . . . . . . . . . . . . . 577
D-25 A “fully-capable” switch implementation. . . . . . . . . . . . . . . . . 579
31
List of Figures
32
List of Tables
3.1 Typical system parameters and passive components. . . . . . . . . . . 90

3.2 Dominant Pole Models . . . . . . . . . . . . . . . . . . . . . . . . . . 105
3.3 Range Test Experimental Setup Parameters. . . . . . . . . . . . . . . 123
3.4 Detection Data p − values for Various Electrode Configurations at the
Limit of the Detection Range. . . . . . . . . . . . . . . . . . . . . . . 124
3.5 Typical Simulated Capacitances (shown for a target positioned under
the left end of the lamp sensor depicted in Figures 3-20 and 3-23(b)). 129
3.6 Simulation Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . 133
3.7 Experimental Setup Parameters. . . . . . . . . . . . . . . . . . . . . . 133
3.8 Simulated Capacitance Change: x = −100 cm to x = −80 cm. . . . . 136
4.1 Truth table of all possible logic states. . . . . . . . . . . . . . . . . . 174

4.2 Power Electronic Loss Comparisons . . . . . . . . . . . . . . . . . . . 177
5.1 Typical system parameters and passive components. . . . . . . . . . . 194
6.1 Canonical Model Parameters for CCM-operated Buck, Boost and Buck-
Boost converters with a fixed load R [14] . . . . . . . . . . . . . . . . 214
6.2 Canonical Model Parameters for the Buck, Boost and Buck-Boost with
a generalized load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
7.1 Special-case impedances for correcting Gvd (s) in CCM-operated con-

verters with a fixed load, R [14]. . . . . . . . . . . . . . . . . . . . . . 257
7.2 Generalized Input Filter Design Constraints for Single-Converter Systems266
33
List of Tables
9.1 Nominal fuel cell master-slave system parameters . . . . . . . . . . . 302
10.1 RSSL Multipliers: (×1/Cfsw ) . . . . . . . . . . . . . . . . . . . . . . 364

10.2 RF SL Multipliers: (×Rds,on ) . . . . . . . . . . . . . . . . . . . . . . . 364
10.3 Simulated statistical performance: 5-level, 3 Panel optimized system:
Monte Carlo Length = 100, Distribution Compression = 50%, ∆Io = 1
mA, Diode Loss = [on], fsw = 360 kHz . . . . . . . . . . . . . . . . . 370
10.4 Circuit component summary . . . . . . . . . . . . . . . . . . . . . . . 370
10.5 Experimental prototype parameter summary . . . . . . . . . . . . . . 373
10.6 The implemented PV circuit model elements . . . . . . . . . . . . . . 376
10.7 Detailed experimental prototype circuit component values . . . . . . 376
10.8 MOSFET source voltages normalized to the input voltage . . . . . . 382
10.9 Standby power optimization results: Q = 2 module. . . . . . . . . . . 385
A.1 Lamp sensor, Rev.2 bill of materials. . . . . . . . . . . . . . . . . . . 404

A.2 MPLab connector pin-out color code. . . . . . . . . . . . . . . . . . . 451
C.1 Marx converter bill of materials. . . . . . . . . . . . . . . . . . . . . . 523
D.1 Classification of Switching Patterns Analyzed . . . . . . . . . . . . . 549
34
Chapter 1
Introduction
Multisource electrical networks pervade systems that consume and generate electrical
power. Understanding, modeling, and designing multisource networks is increasingly
a key step in implementing technological solutions for energy management, conserva-
tion and generation. A lighting array, for example, constitutes a network of multiple
electrostatic field sources particularly useful for occupancy detection. A solar array
constitutes a grid or network of panels serving as sources, and a fuel cell stack is typi-
cally used in a hybrid arrangement with other electrical storage devices like batteries
or capacitors to control the impact of electrical transients. The benefits of multisource
electrical networks come with increased complexity in the analysis required to make
informed design choices.
This thesis addresses the added complexity with linear analytical and model-
ing approaches that reveal the salient features of complicated multisource systems.
Examples from capacitive sensing occupancy detectors, hybrid power systems and
multipanel solar arrays demonstrate the utility of the analytical approaches.
1.1 Thesis Overview
The advantages of multisource networks are explored first in the context of capaci-
tive sensing occupancy detectors. Multiple signal sources can be configured to yield
a natural carrier suppression enabling surprising resolution of fine perturbations in
35
1.1. Thesis Overview
the lumped capacitive network comprising the occupancy detection field. The car-
rier suppression is exploited with a fully-differential measurement technique which
necessitated analytical modeling not previously found in the literature. The resulting
circuit and mathematical model of the fully-differential amplifier is employed to val-
idate our understanding of the operating principles in a first capacitive sensor that
uses multiple sources of stray electric fields from fluorescent lamps to detect occu-
pants. Extensions of this application are demonstrated for solid-state lighting and for
a capacitive sensor based on multiple artificially generated electric field sources.
In a second example, multisource networks are explored in the context of fuel cell
power processing. The need to maintain a fuel cell output current at a fixed and
safe operating point to contend with the well-known inherent reliability issues therein
is addressed by deploying a multisource multi-converter system. The multisource
system fundamentally provides the needed degrees of freedom to support both safe
fuel cell operation and the practical variability in the load. As an added benefit, that
system is designed to achieve integral diagnostics of the fuel cell based on impedance
spectroscopy using a control approach that could only be developed with a firm
understanding of the linearized behavioral aspects of that power converter system.
The analyses and examination of the behavior and design of multi-converter systems
presented in this thesis has far-reaching implications in the area of control paradigms
for paralleled converter systems, hybrid power systems, and distributed source power
systems.
A distinct example of multisource power conversion addressed in this thesis fo-

cuses on distributed solar power processing. With the growing need for per panel
maximum power point tracking of solar arrays to contend with varying light levels,
panel ages, etc. across a physically widespread array there are interesting challenges
defined by simultaneous constraints in cost, performance and longevity. The devel-
opment of a linearized circuit model for such a system has revealed a solar power
harvesting approach exhibiting a combination of benefits regarding all of the funda-
mental constraints.
The common analytical style in this thesis blends linear superposition and decom-
36
1. Introduction
position techniques to establish linearized circuit models and design-oriented math-

ematical results. The analysis prioritizes intermediate circuit models often useful in
their own right, but that also serve as abstractions useful in completing the analysis
of the full system. Similarities are evident in the design-oriented analytical process
discussed by Middlebrook in [31].
1.2 Thesis Contributions
The principle contributions of this thesis are summarized here.
1.2.1 Capacitive Sensing Occupancy Detectors
An approach based on carrier suppression techniques in amplitude-modulated sensing

systems is presented in the context of capacitive sensing occupancy detectors. The
carrier suppression techniques largely rely on balanced systems derived from mul-
tisource excitation networks. A differential measurement technique is employed to
sense small imbalances in the resulting capacitive bridge-like networks. An analytical
model of the fully-differential closed-loop op-amp circuit and a detailed analytical ap-
proach is presented. The analytical model captures the distinct common-mode and
differential-mode current paths through the fully-differential transimpedance ampli-
fier. The circuit model of the transimpedance amplifier, useful in its own right, is used
to continue the analysis for fully-differential voltage amplifiers leading to mathemat-
ical results that hold for arbitrary external impedance values - a characteristic that
is superior to the mathematical results from classical analyses of the same circuit.
Lumped element models for capacitive sensors are developed and validated. System
design and modeling considerations are presented for example capacitive sensing oc-
cupancy sensors based on the circuit model of the fully-differential amplifier. A signal
processing approach and circuit is presented with frequency-domain and noise analy-
sis. The performance of several implemented capacitive sensor systems is presented.
37
1.2. Thesis Contributions
1.2.2 Multi-converter Systems
An analytical and modeling framework is presented that addresses three key areas in
the implementation of practical multisource, multi-converter power systems: open-
loop transfer function analysis, closed-loop transfer function analysis, and the effect
of multiple input filters on both. The analysis is applied to two design examples con-
stituting two different feedback control techniques in the context of fuel cell power
processing. Design considerations enabling integral diagnostics based on impedance
spectroscopy using small-signal power converter control techniques are presented in
the context of the example systems. The performance of two implemented systems
and fuel cell impedance results indicative of run-time integral diagnostics are pre-
sented. The health of an electrically-simulated fuel cell stack is determined based on
run-time impedance measurements showing distinct differences between healthy and
damaged states.
1.2.3 Per-panel Photovoltaic Power Processing
A linearized circuit model of an N-converter-N-panel solar power array is developed

leading to a maximum power point tracking approach enabling the use of circuit
topologies with benefits in efficiency, cost, and complexity. The maximum power point
tracking approach overcomes the limitations of multilevel output switched-capacitor
converters and obviates the need for interpanel communication. The underlying moti-
vation is to deploy switched-capacitor converters because they achieve power conver-
sion without magnetic energy storage – a key cost element in inductor-based power
converters. A statistical performance evaluation method is presented revealing the
predicted average performance of the proposed system. Competitive tracking effi-
ciencies are supported by the statistical performance predictions despite a relatively
small number of discrete conversion ratios accessible to each of the panel convert-
ers. A switched-capacitor experimental prototype is presented to demonstrate power
processing and design concepts. Predicted and measured conversion efficiencies agree
well and indicate good performance.
38
1. Introduction
1.3 Thesis Organization

Chapter 2 presents a detailed analysis of the first multisource electrical network con-
sidered in this thesis. The analysis develops circuit models and mathematical expres-
sions to describe the behavior of fully-differential closed-loop op-amp circuits. The
results of that analysis are used in the design and configuation of the multisource
capacitive sensing occupancy detectors detailed in Chapters 3 - 5.
Chapters 6 - 9 present work on multiconverter power systems with examples for
fuel cell power processing. Chapter 6 investigates a linearized model of the multi-
converter system and the analysis of its behavior in the context of feedback con-
trol. Chapter 7 addresses the effect of multiple input filters in multisource, multi-
converter systems using an application of the two extra element theorem (2EET).
Chapter 8 presents a design example using dual voltage regulated power converters
for impedance spectroscopy in a grid-tied fuel cell application. Chapter 9 presents a
design example using a master-slave control technique for impedance spectroscopy in
a fuel cell application intended for unmanned aerial vehicles (UAV’s).
Chapter 10 describes a method for deploying magneticless per panel solar power
converters.
39
1.3. Thesis Organization
40
Chapter 2
Analysis and Modeling of

Fully-differential Closed-loop
Op-amp Circuits
2.1 Introduction
Fully-differential (FD) amplifiers afford notable benefits in dynamic range and rejec-
tion of unwanted signals. The dynamic range benefit is significant when contend-
ing with low supply voltages in fully-integrated and system on-chip design [32–38],
general purpose and audio frequency instrumentation [35, 39–41], and in discrete
op-amp applications particularly for accommodating differential-mode (DM) input
ADC’s [40–44]. Integrated switched-capacitor amplifiers have exploited this benefit as
well [45–48]. Power supply disturbances and common-mode (CM) pickup are typical
unwanted signals that are better rejected by FD electronics when compared to their
single-ended (SE) counterparts [39, 45, 49–52]. Both voltage-mode and current-mode
(transimpedance) FD amplifiers are useful as front-end amplifiers for suppressing un-
wanted carrier content in balanced or “bridge-like” systems [1, 53–55]. Additionally,
DM signal processing rejects the effects of even-order nonlinearities [42, 51]. Both
balanced and intentionally asymmetric FD amplifiers play important roles [41, 44].
41
2.1. Introduction
The benefits of FD signal processing come at the expense of added complexity in

analysis. Powerful simplifications are possible upon assuming perfect or almost per-
fect symmetry, e.g. equality between homologous elements, Zf 1 and Zf 2 , in Figure
2-1. References [51,56–58] exploit those simplifications to develop half-circuit decom-
position methods. In reference [41] the author analyzes FD amplifiers directly, but
relies on perfect symmetry assumptions late in the analysis to arrive at expressions
in terms of DM or CM input signals.
Zf 2
Z1 Vsup+
Vin+ + −
A(s) +
Vod
Vin− +
−
Z2 Vsup−
Zf 1
Figure 2-1: A FD closed-loop op-amp circuit
This work takes an alternative approach to the analysis of FD amplifiers. The

analysis is separated into two steps corresponding to the inner transimpedance am-
plifier and the outer voltage-mode amplifier. Linear superposition of CM and DM
signals assures the results are written directly in terms of those quantities. Separation
of the analysis and the use of linear superposition leads to concise or “low-entropy”
mathematical expressions [31]. An added benefit of the approach is that the usual
symmetry assumptions are not needed and so the results hold for arbitrary element
values.
The development of the FD transimpedance amplifier circuit model in Section 2.2
is perhaps the core contribution of this work. The versatility of that circuit model
is demonstrated in three key contexts. First, the transimpedance amplifier model
42
2. Analysis and Modeling of Fully-differential Closed-loop Op-amp Circuits
is used to derive the performance of a voltage amplifier with arbitrary impedance

elements, Z1 and Z2 in Figure 2-1. The results hold for arbitrary impedance values
and agree well with the simulated behavior of a commercial FD op-amp. Second, the
extension of that analysis to include finite op-amp input impedance, using the same
transimpedance amplifier circuit model is described. Finally, the transimpedance
amplifier model is used to predict the behavior of a capacitive bridge sensor system.
In the capacitive bridge sensor system, the external impedance elements Z1 and Z2
are further generalized to an arbitrary impedance network. Finite op-amp input
impedance is captured by including shunt impedances at the transimpedance amplifier
circuit model inputs. In the capacitive bridge sensor system, the front-end amplifier
is loaded by the subsequent synchronous demodulation circuitry. Model validation
comparing experimental data to data simulated using the transimpedance amplifier
circuit model shows excellent agreement.
2.1.1 Current Paths in FD Amplifiers
The ensuing analysis will be better appreciated having an understanding of the CM

and DM current paths through a FD amplifier. The current paths in the FD amplifier
(Figure 2-2(b)), are in some sense a generalization of those in the SE amplifier (Figure
2-2(a)); current return paths are supported by the output structure of the op-amp
itself, but in the FD amplifier purely DM and purely CM currents take two distinct
paths. The circuit models developed through the analysis in Sections 2.2 and 2.3 will
mirror the current paths shown in Figure 2-2(b). Note that the incremental grounds
in Figure 2-2 are physically supported by the op-amp power supply connections.
43
2.1. Introduction
Zf
Zi
−
v− vo
+
vs +
− vout
+ −
(a) SE
Zf 2
Z1
+
v+ 1
2 vod
vsc +
1
2 vsd
−
voc −
− + − + +
vod
+ − −
1
2 vsd 1
2 vod
+
+
−
v−
−
Z2
Zf 1
DM Currents
CM Currents
(b) FD
Figure 2-2: Small-signal current paths in closed-loop op-amp amplifiers.
44
2.1.2 Definitions
Definitions of CM and DM signal decompositions vary among the literature. We

define them in this work as follows. Differential-mode (DM) voltage is defined as the
difference between two voltages,
vdm ≡ v+ − v− , (2.1)
and common-mode (CM) voltage is defined as the geometric mean of the two,
v+ + v−
vcm ≡ . (2.2)
2
Differential-mode current is defined as half the difference between two currents,
i+ − i−
idm ≡ , (2.3)
2
while common-mode (CM) current is defined as the sum of the two,
icm ≡ i+ + i− . (2.4)
2.1.3 Scope
The analysis in Sections 2.2 and 2.3 focuses on the DM output voltage while the
CM output voltage is assumed to be held fixed by the CM feedback circuit included
in all commercial FD op-amps. The scope of this chapter is intended to address
op-amp circuits that process signals having frequency content well below the op-
amp cross-over frequency, e.g. 1 kHz in the simulations of the LTC6404. These
cases are ubiquitous as they correspond to good design practices guaranteeing that
the op-amp will exhibit large DM-DM gain, ad , and relatively small CM-DM gain, ac .
Loading effects on the closed-loop op-amp circuit are negligible under these conditions
because the feedback control significantly reduces the effect of finite op-amp (open-
loop) output impedance. The assumptions described above will be validated in both
45
2.2. Analysis Step One: Transimpedance Amplifier
simulation and in a practical setting in Section 2.4.
2.1.4 Dynamics
The results in this chapter are derived in terms of op-amp gain parameters, ad and ac ,
and generalized external impedance elements. The behavior of an arbitrary system
having dynamic effects may be described by inserting the frequency dependencies of
those parameters into the mathematical results or circuit models.
2.1.5 Model Validation
Comparison of the mathematical results with simulated and experimental data vali-
dates the assumptions taken in the analysis, the practical relevance of this work and
the correctness of the mathematical manipulations.
Simulated model validation was carried out by comparing numerical results from
the mathematical results to SPICE simulations of ideal circuit models and of a com-
mercial FD op-amp, the LTC6404. The model validations plot the quantities of
interest against percentage mismatch between homologous elements, e.g. ∆Z is the
mismatch between Z1 and Z2 in Figure 2-1. A 0% mismatch corresponds to perfect
symmetry while a 200% mismatch means that one element is zero-valued while the
other is twice the average value.
Experimental model validation was carried out by comparing simulated data to
experimental data in a practical setting involving macroscopic capacitive occupancy
sensing and a synchronous detection signal processing system.
2.2 Analysis Step One: Transimpedance Amplifier

In this section, we analyze a FD transimpedance amplifier using the small-signal
model shown in Figure 2-3. According to the CM and DM signal definitions from
Section 2.1, in the small-signal model, the DM input voltage is
vid = v+ − v− , (2.5)
46
and the CM input voltage is

1
vic = (v+ + v− ), (2.6)
2
while the DM output voltage is
vod = vo+ − vo− . (2.7)
Similarly, the DM input current is
1
iid = (i+ − i− ), (2.8)
2
while the CM input current is

iic = i+ + i− . (2.9)
Finally, the amplifier has the effect according to its DM-DM voltage gain, ad , and its
CM-DM voltage gain, ac :
vod = ad vid + ac vic . (2.10)
The output terminal voltages are symmetrical about the incremental CM output
voltage, a CM voltage that is assumed fixed for the analyses in this chapter, i.e.
vo+ = −vo− . (2.11)
Normally, ad , the DM-DM op-amp gain, is large by design while ac , the CM-DM
op-amp gain, is relatively small, also by design. The small-signal CM output voltage
is an incremental ground having assumed a purely DC CM output voltage.
2.2.1 Transimpedance Amplifier Output Behavior
A CM-DM superposition approach for determining the transimpedance amplifier’s

DM output voltage is summarized by the equation:

vod vod
vod = iid + iic , (2.12)
iid iic =0 iic iid =0
47
Zf 2
1
i
2 sc
i+ vo−
−
v+
1
2 (ad vid + ac vic)
−
isd vid
+
vod
−
1
2 (ad vid + ac vic)
−
v− +
1
i i− vo+ +
2 sc
Zf 1
Figure 2-3: A FD transimpedance amplifier small-signal model.
in which the terms in parentheses are the transimpedance and cross-transimpedance.

To find (vod /iid )iic=0 , the CM input current sources are deactivated. Note that in this
case,
iid = isd = i+ = −i− . (2.13)
From Figure 2-3, the resulting input terminal voltages are
v+ = vo− + iid Zf 2 (2.14)
and
v− = vo+ − iid Zf 1 , (2.15)
so that, from (2.5) and (2.6), the CM and DM input voltages become
1 iid
vic = (v+ + v− ) = (Zf 2 − Zf 1 ) (2.16)
2 2
and
vid = v+ − v− = −vod + iid Zf 2 + iid Zf 1 , (2.17)
48
respectively. Substituting the CM and DM input voltages into the output voltage
from (2.10) yields
iid
vod = ad (iid (Zf 1 + Zf 2 ) − vod ) + ac (Zf 2 − Zf 1 ), (2.18)
2
so that,
vod ad ac
=2 Zf − ∆Zf , (2.19)
iid iic=0 1 + ad 2(1 + ad )
where the following terms are defined:
(Zf 1 + Zf 2 )
Zf ≡ (2.20)
2
and
∆Zf ≡ Zf 1 − Zf 2 . (2.21)
To calculate (vod /iic )iid =0 , the DM input current source is deactivated. A similar
analysis yields
vod 1 (−ad ∆Zf + ac Zf )
= . (2.22)
iic iid =0 2 (1 + ad )
Superposing the two responses in (2.19) and (2.22) yields the complete expression for
the DM output voltage in response to generalized input currents:
!
2Zf ad − 12 ac ∆Zf ac Zf − ad ∆Zf
vod = iid + iic . (2.23)
(1 + ad ) 2(1 + ad )
2.2.2 Transimpedance Amplifier Input Behavior
Having derived the DM output voltage, a similar analysis leads to the DM and CM in-
put voltages. These results will be grouped according to the superposition expressions
below. The DM input voltage will be grouped as follows:

vid vid
vid = iid + iic (2.24)
49
and the CM input voltage will be grouped as follows:

vic vic
vic = iid + iic . (2.25)
Analyzing the small-signal model in Figure 2-3, leads to
∆Zf Zf
vic = −iid + iic (2.26)
2 2
and !
2Zf + 12 ∆Zf ac ∆Zf + Zf ac
vid = iid − iic . (2.27)
(1 + ad ) 2(1 + ad )
Comparing these results to (2.24) and (2.25) reveals the distinct terms resulting from
the superposition of the CM and DM input sources. An interesting pattern arises in
the results above. Terms with one of ac or ∆Zf influence cross-coupling from CM
to DM signals. On the other hand, terms with a product of ac and ∆Zf appear as
non-ideal terms in the relation between two DM signals. This pattern is intuitive and
ubiquitous in this chapter.
2.2.3 Circuit Models of the Transimpedance Amplifier
For the second step of the analysis, it will be useful to form circuit models of the
transimpedance amplifier. Figures 2-4(b) and 2-4(c) show ‘T’ and ‘Π’ topologies that
are helpful for representing the CM and DM input voltages in (2.26) and (2.27). Both
models include a dependent voltage source at the output, which captures the function
of the transimpedance and the cross-transimpedance from equation (2.23). The two
models differ in their input structures. The T-network and the Π-network are each
intended to approximate the behavior of the CM and DM input voltages in equations
(2.26) and (2.27).
50
Zf 2
Vsup+
1
i
2 sc
i+
+
− vo−
isd A(s)
1 +
i
2 sc i− vo+
−
Vsup−
Zf 1
(a) A FD Transimpedance Amplifier
1
i
2 sc
i+ 1
Z
+ 2 α
vo+
+ 1
eα
− 2 Zβ
isd ecc
+ vod
−
+ 1
1
i eα
2 sc i− − 2
+
eβ vo−
−
−
1
Z
2 α
(b) A Small-signal T-model
1
i
2 sc
i+ 2Zδ
+
vo+
+
eγ
−
isd ecc + vod
−
1 Zγ
i
2 sc i−
vo−
−
+
2Zδ eδ
−
(c) A Small-signal Π-model
Figure 2-4: A FD transimpedance amplifier and two approximate small-signal models.

The T-model and the Π-model differ in the structure of their input network. Each
contain an internal node labeled ecc .
51
To simplify the following discussion, it is convenient to rename the terms in equa-

tions (2.26) and (2.27) as follows. The impedance elements in the CM current path
will be assigned values according to,

vic Zf
Zc ≡ = (2.28)
iic iid =0 2
while the impedance elements appearing in the DM current path will be assigned
values according to,
!
vid 2Zf + 12 ∆Zf ac
Zd ≡ = . (2.29)
iid iic =0 (1 + ad )
The dependent voltage source in the CM current path will be assigned a value ac-
cording to,
vic ∆Zf
ec (iid ) ≡ iid = −iid (2.30)
iid iic =0 2
while the dependent voltage sources in the DM current path will be assigned values
according to,
vid ∆Zf + Zf ac
ed (iic ) ≡ iic = −iic . (2.31)
iic iid =0 2(1 + ad )
The terms Zc and Zd are the diagonal-terms from equations (2.26)-(2.27) and they
are the CM and DM input impedances of the transimpedance amplifier. The terms
ec (iid ) and ed (iic ) represent dependent voltage sources that capture the effects of the
“cross-terms” in equations (2.26) and (2.27).
Using the definitions in (2.28)-(2.31), the following model parameters achieve an

exact match between the terminal behaviors of the circuits in Figures 2-4(b) and
2-4(c) and the input voltages represented by (2.26) and (2.27). For the T-model, the
impedance elements are
Zα = Zd (2.32)
Zβ = Zc (2.33)
52
and the dependent sources are
eα = ed (iic ) (2.34)
iic Zd
eβ = ec (iid ) − . (2.35)
4
For the Π-model, the impedance elements are
Zd
Zγ = Zd (2.36)
Zd ||4Zc
Zδ = Zc , (2.37)
Zd
eγ = ed (iic ) (2.38)
Zd ||4Zc
eδ = ec (iid ). (2.39)
The model parameters in (2.32)-(2.39) can be simplified under practical approxima-

tions to make the circuit models more intuitive. For sufficiently small Zd , the additive
term, (iic Zd /4), will approach zero and the multiplicative term, (Zd /Zd ||4Zc), will ap-
proach unity. From (2.28)-(2.31), Zd is guaranteed to be small if both ad and the ratio
ad /ac are large. Under these assumptions, the model parameters in (2.32)-(2.39) re-
duce to the following. For the T-model, the impedance elements are
Zα = Zd (2.40)
Zβ = Zc (2.41)
eα = ed (iic ) (2.42)
eβ = ec (iid ). (2.43)
53
For the Π-model, the impedance elements are
Zγ = Zd (2.44)
Zδ = Zc , (2.45)
eγ = ed (iic ) (2.46)
eδ = ec (iid ). (2.47)
For simplicity, the rest of this analysis assumes that the gain criteria above have been
met, and proceeds with the approximate model parameters in (2.40)-(2.47).
2.2.4 Transimpedance Amplifier Model Validation
Figure 2-5 shows model validation plots for the transimpedance amplifier. In the
model validations, the amplifier was driven with a 1 kHz sinusoidal current source with
equal CM and DM components each having an amplitude of 1 mA. The calculated
results for vid , vic , and vod were overlayed on the simulated results for the T and
Π circuit models, a small-signal (“s-s”) op-amp model, and a simulated commercial
op-amp. The left column in Figure 2-5 shows results for positive-valued mismatches,
∆Zf . The right column shows results for negative-valued mismatches. The results in
Figure 2-5 show good agreement among the calculated and simulated results.
54
DM Input Voltage vs. Zf Mismatch DM Input Voltage vs. Z Mismatch

f
−4 |Isd|=|Isc|=1mA, f=1kHz, ad=2.79M, ac=8,771 −3 |Isd|=|Isc|=1mA, f=1kHz, ad=2.79M, ac=8,771
x 10 x 10
4 0
Calculated
3
Simulated s−s Op−amp −0.1 Zf = 100Ω
Simulated T−model
Simulated Π−model −0.2
2 Simulated LTC6404−1 Zf = 200Ω
DM Input Voltage |V | (V)
DM Input Voltage |V | (V)

−0.3
ind
ind
1
−0.4
0 −0.5
−0.6
−1 Zf = 100Ω
−0.7
−2 Calculated
−0.8 Simulated s−s Op−amp
Zf = 200Ω Simulated T−model
−3
−0.9 Simulated Π−model
Simulated LTC6404−1
−4 −1
−1 0 1 2 −1 0 1 2
10 10 10 10 10 10 10 10
∆ Z (%) −∆ Zf (%)
f
(a) vid for ∆Zf > 0 (b) vid for ∆Zf < 0
CM Input Voltage vs. Zf Mismatch CM Input Voltage vs. Z Mismatch
f
|Isd|=|Isc|=1mA, f=1kHz, ad=2.79M, ac=8,771 |Isd|=|Isc|=1mA, f=1kHz, ad=2.79M, ac=8,771
0.1
Calculated
0.08 Zf = 200Ω Simulated s−s Op−amp
Simulated T−model
0.25
0.06 Simulated Π−model
CM Input Voltage |V | (V)
CM Input Voltage |Vinc| (V)
0.04
Zf = 100Ω
inc
0.02 0.2
−0.02 0.15 Zf = 200Ω
−0.04
Calculated
−0.06 Simulated s−s Op−amp 0.1
Simulated T−model
−0.08 Simulated Π−model Zf = 100Ω
−0.1 0.05
−1 0 1 2 0 1 2
10 10 10 10 10 10 10
∆ Z (%) −∆ Zf (%)
f
(c) vic for ∆Zf > 0 (d) vic for ∆Zf < 0
DM Output Voltage vs. Zf Mismatch DM Output Voltage vs. Z Mismatch
f
|Isd|=|Isc|=1mA, f=1kHz, ad=2.79M, ac=8,771 |Isd|=|Isc|=1mA, f=1kHz, ad=2.79M, ac=8,771
0.45
0.6 Calculated
0.4 Zf = 200Ω Simulated s−s Op−amp
Simulated T−model
0.55
Simulated Π−model
0.35 Simulated LTC6404−1
DM Output Voltage |Vod| (V)
DM Output Voltage |Vod| (V)
0.5
0.3
0.45
0.25 0.4 Zf = 200Ω

Zf = 100Ω
0.2 0.35
0.15 Calculated 0.3

Simulated s−s Op−amp
Simulated T−model 0.25
0.1
Simulated Π−model Zf = 100Ω
Simulated LTC6404−1 0.2
0.05
−1 0 1 2 0 1 2
10 10 10 10 10 10 10
∆ Z (%) −∆ Zf (%)
f
(e) vod for ∆Zf > 0 (f) vod for ∆Zf < 0
Figure 2-5: Validating the transimpedance amplifier model.
55
2.3. Analysis Step Two: Voltage Amplifier
2.2.5 The Virtual Short-Circuit Approximation
From (2.29), the impedance of the DM virtual short-circuit is predominantly 2Zf /(1+
ad ). The DM gain, ad , is large by design, so this impedance is small and hence the
virtual short circuit approximation. On the other hand, the CM input impedance in
(2.28) is half the average feedback impedance – approximately equal to Zf 1 ||Zf 2 for
small mismatch values. These results become intuitive when following the respective
current paths (Figure 2-2(b)) through the amplifier.
The circuit model intuition, and in particular, the virtual short-circuit approxima-
tion will be useful in the chapters that follow. System configurations, modeling and
design of the capacitive occupancy sensor systems in Chapters 3-5 will rely heavily
on the analytical model of the FD transimpedance amplifier developed here and on
these intuitive approximations.
2.3 Analysis Step Two: Voltage Amplifier
In Figure 2-6, input elements Z1 and Z2 are added onto the Π-model of the tran-
simpedance amplifier circuit model to form a voltage amplifier model. The goal of
this section is to find the DM output voltage, vod , that results from the CM and
DM input voltages, vsc and vsd . The transimpedances derived in Section 2.2 reveal
the relationships between the input currents, iic and iid , and the DM output voltage,
vod , from (2.23). The voltage amplifier analysis reduces to finding the relationships
between the input voltage sources, vsc and vsd , and the input currents, iic and iid .
This analysis results in four transconductances. Detailed algebraic manipulations for
these derivations can be found in Appendix A.7.
A superposition approach to find the overall DM output voltage yields the follow-
ing expression:
vod vod
vod = iid + iic , (2.48)
where the terms in parentheses are the two transimpedances from Section 2.2. The
currents, iid and iic in (2.48), may be found using linear superposition of the DM and
56
CM input voltage sources as follows
vod =
!
iid iid vod
vsd + vsc
vsd vsc =0 vsc vsd =0 iid iic =0
| {z } | {z }
iid transimpedance
!
iic iic vod
+ vsd + vsc , (2.49)
vsd vsc =0 vsc vsd =0 iic iid =0
| {z } | {z }
iic cross-transimpedance
where the added terms in parentheses are the four transconductances. The two tran-
simpedances and four transconductances can be renamed for brevity as follows. The
transimpedance from DM input current to DM output voltage is

vod
Zdd ≡ , (2.50)
iid iic =0
and the transimpedance from CM input current to DM output voltage is

vod
Zcd ≡ . (2.51)
iic iid =0
The transconductance from DM input voltage to DM input current is

iid
Ydd ≡ , (2.52)
vsd vsc =0
and the transconductance from CM input voltage to DM input current is

iid
Ycd ≡ . (2.53)
vsc vsd =0
The transconductance from DM input voltage to CM input current is

iic
Ydc ≡ , (2.54)
vsd vsc=0
57
and the transconductance from CM input voltage to CM input current is

iic
Ycc ≡ . (2.55)
vsc vsd =0
With the definitions above, the expression in (2.49) can be re-written
vod = (vsd Ydd + vsc Ycd )Zdd + (vsd Ydc + vsc Ycc )Zcd (2.56)
and then regrouped with the source terms:
vod = vsd (Ydd Zdd + Ydc Zcd ) + vsc (Ycd Zdd + Ycc Zcd ). (2.57)
58
Zf 2
Vsup+
Z1 i+
+
+
vsc 1
v − vo−
2 sd
− + −
A(s)
+
1
v
2 sd i− + vo+
−
−
Z2
Vsup−
Zf 1
(a) A FD voltage-mode amplifier
Z1 i+ 2Zc
+
vo+
+
1 +
vsc v
2 sd − ed (iic )
− + −
ecc + vod
−
+
1
v Zd
2 sd i−
−
−
vo−
+
Z2 2Zc −
ec (iid )
(b) A voltage-mode amplifier model built from the Π-model of the

transimpedance amplifier
Z1 i+
+
vo+
+
1
vsc v
2 sd
− −
Zc
+ ecc + vod
−
+
1
v
2 sd
−
i− +
ec (iid ) − vo−
−
Z2
(c) A voltage-mode amplifier model using the “virtual short-circuit

approximation”
Z1 i+ 2Zc
+
vo+
+ 1
i′+
vsc v
2 sd
− + −
ied +
ed (iic ) + vod
− −
+ 1
v
2 sd
−
i− i′−
−
vo−
+
Z2 2Zc −
ec (iid )
(d) The model used for deriving the correction in Section 2.3.1
Figure 2-6: Adding the input elements onto the transimpedance amplifier model
yields a voltage-mode amplifier model.
59
The analysis may be simplified using the virtual short-circuit approximation quan-
tified in Section 2.2.5. Analysis of the resulting circuit in Figure 2-6(c) may be divided
into four distinct pieces for the four unknown transconductances needed in the ex-
pression for vod (2.57). Shorting the DM input source results in the set of constraints
on the input currents,
(vsc − ecc )
i+ = (2.58)
Z1
(vsc − ecc )
i− = , (2.59)
Z2
while shorting the CM input source results in the set of constraints on the input
currents,
( 12 vsd − ecc )
i+ = (2.60)
Z1
1
(− 2 vsd − ecc )
i− = . (2.61)
Z2
In either case, the node voltage ecc in Figure 2-6(c) is constrained to be
ecc = ec + (i+ + i− )Zc . (2.62)
Solving for iid = (i+ − i− )/2 and iic = (i+ + i− ) leads to four permutations of
constraints corresponding to the four transconductances. For instance, to find Ydd ,
the CM input voltage is deactivated according to the definition in (2.52), and the DM
input current is found from
i+ − i−
iid = , (2.63)
2
with the three constraints from KVL above, (2.60), (2.61), and (2.62). Solving for
iid /vsd and simplifying leads to:
2Zf + Z1 + Z2
Ydd = . (2.64)
4(Z1 ||Z2 + 12 Zf )(Z1 + Z2 ) + ∆Z∆Zf
The denominator in Ydd above appears in all four transconductances. The quantities
60
in that denominator can be identified with respect to physical current paths in the
voltage amplifier as follows:
Zdm = Z1 + Z2 (2.65)
Zf
Zcm = Z1 ||Z2 + . (2.66)
2
For the simplified model of Figure 2-6(c), Zdm is the impedance seen by a purely DM
input voltage source driving a purely DM input current and Zcm is the impedance
seen by a purely CM input voltage source driving a purely CM input current. That
is,

vsd
Zdm = (2.67)
iid vsc =0
iic =0

vsc
Zcm = . (2.68)
iic vsd =0
iid =0
Applying the constraints in the four permutations, simplifying and identifying the
impedance terms Zdm and Zcm leads to the DM-DM transconductance,
Zf + Z
Ydd = 2 , (2.69)
4ZcmZdm + ∆Z∆Zf
the CM-DM transconductance,
−∆Z
Ycd = 2 , (2.70)
4ZcmZdm + ∆Z∆Zf
the DM-CM transconductance,
∆Zf − ∆Z
Ydc = 2 , (2.71)
4ZcmZdm + ∆Z∆Zf
and the CM-CM transconductance,
Z
Ycc = 8 . (2.72)
4Zcm Zdm + ∆Z∆Zf
61
The common denominator in these transconductances aids further analysis when we

form linear combinations of these terms (see Section 2.3.3).
2.3.1 Model Correction
The virtual short-circuit approximation led to some inaccuracy in the results for CM-
DM gain, Avc , in the small-mismatch region, Figure 2-7(a). The modularity of the
results allows for rapid correction of this inaccuracy. Adding the effect of ed (iic ) is
most critical for correcting Avc because it accounts for a DM input voltage in response
to a CM input current. Among the two transconductaces that affect CM-DM gain,
Ycd quantifies the DM input current, which is most directly affected by the addition
of ed (iic ) to the model. This correction rederives Ycd from the circuit in Figure 2-6(d),
while Ycc is assumed sufficiently accurate.
62
Uncorrected Small−mismatch CM to DM Gain vs. Feedback Elt. Symmetric Mismatch

−3 Z = Zf = 100Ω Resistive, f=1kHz, ad=2.79M, ac=8,771
x 10
3
1
CM−DM Voltage Gain
−1
−2 Calculated
Simulated S−S Op−amp
Simulated T−model
−3 Simulated T−model shorted input
−4
−1 0
10 10
∆Zf (%)
(a) Small-mismatch “zoom-in” of Avc for ∆Zf > 0 (uncorrected). Plotting Avc
for ∆Z > 0 results in a very similar plot. The calculated line falls on the shorted-
input model data instead of the more accurate simulated data.
Corrected Small−mismatch CM to DM Gain vs. Feedback Elt. Symmetric Mismatch
−3 Z = Zf = 100Ω Resistive, f=1kHz, ad=2.79M, ac=8,771
x 10
3
1
−1
−2 Calculated
Simulated S−S Op−amp
Simulated T−model
−3 Simulated T−model shorted input
−4
−1 0
10 10
∆Zf (%)
(b) Small-mismatch “zoom-in” of Avc for ∆Zf > 0 (corrected). A plot of Avc for
∆Z > 0 is very similar. Small-mismatch CM-DM gain agrees well with simulated
circuits after the correction is added.
Figure 2-7: Accuracy improvement for small-mismatch Avc .
63
The circuit in Figure 2-6(d) leads to the following constraints. The DM input
current is,
ed
iid = ied +
4Zc
= ied + i′id , (2.73)
while the CM input current is,
iic = i+ + i− = i′ic , (2.74)
where we have made the following definitions:
1 ′
i′id ≡ (i − i′− ) (2.75)
2 +
i′ic ≡ i′+ + i′− = iic (2.76)
and the current through the added DM voltage element is
ied = i+ − i′+
= i′− − i− . (2.77)
Finally, applying KVL results in two equations:
vsc − i+ Z1 − ed − i′− 2Zc − ec = 0 (2.78)
vsc − i− Z2 + ed − i′+ 2Zc − ec = 0. (2.79)
Solving these constraints for the “corrected transconductance,” Ycd′ = (iid /vsc )vsd =0 ,
leads to
∆Zf +ac Zf
Ycc (Zf ∆Z + Z 1+ad
)− ∆Z
Ycd′ = , (2.80)
4Z1 Z2 + 12 ∆Zf ∆Z
which is more complicated than the expressions in (2.69)-(2.72). Because the small-
64
mismatch region is of interest here, Ycd′ can be simplified with the small-mismatch
approximations,
∆Zf << Zf 1 , Zf 2 , Zf (2.81)
∆Z << Z1 , Z2 , Z, (2.82)
which imply that Zf 1 ≈ Zf 2 ≈ Zf and Z1 ≈ Z2 ≈ Z. The “small-mismatch corrected

transconductance” becomes
Zf ac
′ 1+ad
− ∆Z
Ycds ≈ . (2.83)
2Zdm Zcm
The denominator in (2.83) can be forced to match the common denominator from the
other three transconductances by multiplying the numerator and denominator by 2
and adding the small quantity, ∆Z∆Zf , back in:
correction term
z }| {
ac
Zf −∆Z
′ 1 + ad
Ycds ≈2 . (2.84)
4Zdm Zcm + ∆Zf ∆Z
′
Comparing Ycds from (2.84) to Ycd from (2.70), reveals that they differ only in the

ac
“correction term” Zf 1+a d
.
′
Model validation (Figure 2-7(b)) with this corrected Ycds shows good agreement
′
for small mismatch values. Although Ycds was calculated while assuming small mis-
matches, model valdiatons will show that the full model, including the corrected
′
Ycds , agrees for the range 0% − 200% of resistive element mismatch values. There-
′
fore, the following results, including Ycds , are proposed as the full transconductance-
transimpedance descriptive abstraction of the FD voltage amplifier. The DM-DM
and CM-DM transconductances are
Zf + Z
Ydd = 2 (2.85)

ac
Zf 1+ad − ∆Z
′
Ycds =2 , (2.86)
65
while the DM-CM and CM-CM transconductances are
∆Zf − ∆Z
Ydc = 2 (2.87)
4ZcmZdm + ∆Z∆Zf
Z
Ycc = 8 (2.88)
4ZcmZdm + ∆Z∆Zf
and the transimpedance amplifier results are repeated here for convenience:
ad Zf − ac ∆Zf /2
Zdd = 2 (2.89)
(1 + ad )
1 ac Zf − ad ∆Zf
Zcd = . (2.90)
2 (1 + ad )
The results in (2.85)-(2.90) yield the full expression for the DM output voltage when
substituted into the following expression:
′
vod = vsd (Ydd Zdd + Ydc Zcd ) + vsc (Ycds Zdd + Ycc Zcd) . (2.91)
2.3.2 Voltage Amplifier Input Impedance
Input impedances for the voltage-mode amplifier may be taken directly from the
transconductances as follows. The DM input impedance is

vsd −1
Zind ≡ = Ydd (2.92)
iid vsc =0
and the CM input impedance is

vsc
Zinc ≡ = Ycc−1 , . (2.93)
iic vsd =0
The results above can be written as follows. The DM input impedance is
1 4Zcm Zdm + ∆Z∆Zf

Zind = (2.94)
2 Zf + Z
66
and the CM input impedance is
1 4Zcm Zdm + ∆Z∆Zf

Zinc = . (2.95)
8 Z
Simplifying the expressions for DM and CM input impedance with the small-mismatch
approximations in (2.81)-(2.82) leads to the “small-mismatch DM input impedance,”
Zinds = Zdm = Z1 + Z2 , (2.96)
and the “small-mismatch CM input impedance,”
Zf
Zincs = Zcm = Z1 ||Z2 + , (2.97)
2
which can be approximated for intuition as
Zincs ≈ Z1 ||Z2 + Zf 1 ||Zf 2. (2.98)
The DM and CM input impedance expressions, especially (2.96) and (2.98), are
intuitive when following the respective current paths (Figure 2-2(b)) through the
amplifier. As one might expect, the special-case impedances, Zdm and Zcm from
(2.65) and (2.66), are related to the input impedances, Zind and Zinc in (2.94)-(2.97).
In fact, Zdm and Zcm are, by definition, special cases of Zind and Zinc . Mathematically,
the special-case impedance, Zdm is related to the DM input impedance:
Zdm = Zind |iic =0 (2.99)
and the special-case impedance, Zcm is related to the CM input impedance:
Zcm = Zinc |iid =0 . (2.100)
Moreover, the results in equations (2.96) and (2.97) suggest that those special cases
are coincident with small mismatches in the external homologous elements.
67
2.3.3 Discussion and Model Validation
Familiar quantities such as DM-DM gain, Avd , and common-mode rejection ratio,
CMRR, are readily extracted and simplified from the modularized result. For in-
stance, DM-DM gain in the result from (2.91) is

vod
Avd ≡ = Ydd Zdd + Ydc Zcd , (2.101)
vsd vsc =0
and expanding this leads to the full DM voltage gain expression,
Avd =
a ∆Z
4(Zf + Z)(ad Zf − c 2 f ) + (∆Zf − ∆Z)(ac Zf − ad ∆Zf )
. (2.102)
(4ZcmZdm + ∆Z∆Zf )(1 + ad )
This full gain expression can be simplified to suit the particular non-idealities of
interest. For instance, if mismatches are small, the difference between them is smaller
(∆Zf −∆Z ≈ 0), and the second term in the numerator of (2.102) can be disregarded
leaving only Avd ≈ Ydd Zdd . In the small-mismatch approximation this becomes
4(Zf + Z)(ad Zf − 12 ac ∆Zf )

Avd ≈ , (2.103)
(4ZcmZdm )(1 + ad )
where the small second-order mismatch term in the denominator has been left out.
Expanding the impedances, Zdm and Zcm , the DM voltage gain above reduces to
(ad Zf − 12 ac ∆Zf )
Avds = , (2.104)
Z(1 + ad )
where we define Avds as the “small-mismatch DM voltage gain.” In the fully-ideal

limit, ad → ∞ and ac → 0
Zf
Avdo = , (2.105)
Z
where we define Avdo as the “fully-ideal voltage gain.” The form of Avdo is consistent
with intuition that we bring from SE amplifier cases.
68
Also from (2.91), the CM-DM cross-coupling gain is

vod ′
Avc ≡ = Ycds Zdd + Ycc Zcd . (2.106)
vsc vsd =0
Model validation plots for the voltage amplifier results are shown in Figures 2-8 and
2-9. The calculated results for Avd and Avc were overlayed on the simulated results for
the circuit models, a small-signal (“s-s”) op-amp model, and a simulated commercial
op-amp. The top rows in Figures 2-8 and 2-9 show Avd and Avc across mismatches in
the feedback elements, ∆Zf , while the bottom rows show the same for mismatches in
the input elements, ∆Z. The model validation results show good agreement among
the calculated and simulated results.
The plots in Figures 2-8 and 2-9 include comparisons to the results from a half-
circuit analytical example found in reference [58] demonstrating the break down of
the half-circuit analytical approach for large mismatches and, in some cases, for rela-
tively small mismatches. Reference [58] did not consider mismatches in the feedback
elements so the plots showing the quantities across feedback element mismatch are
somewhat trivial. However, reference [58] did include the effect of the CM-CM gain
of the op-amp. That value was measured for the LTC6404-1 part as acm = −0.043
and was used for plotting the results.
Dividing the CM-DM voltage gain by the DM-DM voltage gain yields the common-
mode rejection, ′
Avc Ycds Zdd + Ycc Zcd
CMR ≡ = , (2.107)
Avd Ydd Zdd + Ydc Zcd
which can be simplified by neglecting small terms to get the approximate CMR:

ac
4(Zf 1+ad
− ∆Z)ad Zf + 4Z(ac Zf − ad ∆Zf )
CMR ≈ (2.108)
4(Zf + Z)ad Zf + (∆Zf − ∆Z)(ac Zf − ad ∆Zf )
The common denominator in the transconductances (2.85)-(2.88) divides out, sim-

plifying the calculation above. Collecting terms, approximating (1 + ad ) ≈ ad , and
69
DM Voltage gain vs. Feedback Elt. Symmetric Mismatch DM Voltage gain vs. Feedback Elt. Symmetric Mismatch
Z = 100Ω Resistive, f=1kHz, ad=2.79M, ac=8,771 Z = 100Ω Resistive, f=1kHz, ad=2.79M, ac=8,771
2 2
Zf = 200Ω Zf = 200Ω
1.8 1.8
1.6 Calculated 1.6

DM Voltage Gain
DM Voltage Gain
1.4 Simulated T−model 1.4
1.2 Simulated LTC6404−1 1.2
Gray and Meyer Zf = 100Ω Zf = 100Ω
1 1
Calculated
0.8 0.8 Simulated s−s Op−amp
Simulated T−model
0.6 0.6
Gray and Meyer
0.4 0.4
−1 0 1 2 −1 0 1 2
10 10 10 10 10 10 10 10
∆Zf (%) ∆Zf (%)
(a) Avd for ∆Zf > 0 (b) Avd for ∆Zf < 0
DM Voltage gain vs. Input Elt. Symmetric Mismatch DM Voltage gain vs. Input Elt. Symmetric Mismatch
3 3.5
Calculated Calculated
Simulated s−s Op−amp Simulated s−s Op−amp
Simulated T−model 3 Simulated T−model
2.5 Simulated Π−model Simulated Π−model
Simulated LTC6404−1 Simulated LTC6404−1
Gray and Meyer Gray and Meyer
Zf = 200Ω 2.5
DM Voltage Gain
DM Voltage Gain
2
Zf = 200Ω
2
1.5
1.5
Zf = 100Ω
1 Zf = 100Ω
1
0.5 0.5
−1 0 1 2 −1 0 1 2
10 10 10 10 10 10 10 10
∆Z (%) ∆Z (%)
(c) Avd for ∆Z > 0 (d) Avd for ∆Z < 0
Figure 2-8: Validating the voltage amplifier model: Avd . Impedances are purely real
(resistive).
rewriting (2.108):
Z
∆Zf +∆Z
ac Zf
ad
− Zf +Z
CMR ≈ ∆Zf . (2.109)
(∆Zf −∆Z)( aac − )
d Zf
1+ 4(Z+Zf )
Reducing (2.109) further with the small-mismatch approximations in (2.81) and

(2.82), the denominator approaches 1, leaving the numerator and we arrive at the
“small-mismatch common-mode rejection:”
Z
ac Zf
∆Zf + ∆Z
CMRs = − , (2.110)
ad Zf + Z
|{z} | {z }
“op-amp gains” “external elements”
70
CM to DM Gain vs. Feedback Elt. Symmetric Mismatch CM to DM Gain vs. Feedback Elt. Symmetric Mismatch
0.2
0 1.2
Zf = 100Ω
−0.2
1

−0.4 Calculated Zf = 200Ω Calculated
Simulated s−s Op−amp 0.8 Simulated s−s Op−amp
Simulated T−model Simulated T−model
−0.6
Simulated Π−model Simulated Π−model
0.6
−0.8 Gray and Meyer Gray and Meyer
0.4
−1
0.2 Zf = 200Ω
−1.2
Zf = 100Ω
0
−1.4
−1 0 1 2 −1 0 1 2
10 10 10 10 10 10 10 10
∆Zf (%) ∆Zf (%)
(a) Avc for ∆Zf > 0 (b) Avc for ∆Zf < 0
CM to DM Gain vs. Input Elt. Symmetric Mismatch CM to DM Gain vs. Input Elt. Symmetric Mismatch
0.5 2.5
0 Zf = 100Ω 2
Calculated Calculated
−0.5
Zf = 200Ω 1.5
Simulated T−model Simulated T−model
Simulated Π−model Simulated Π−model
−1 1
Gray and Meyer Gray and Meyer
−1.5 0.5
Zf = 200Ω
Zf = 100Ω
−2 0
−1 0 1 2 −1 0 1 2
10 10 10 10 10 10 10 10
∆Z (%) ∆Z (%)
(c) Avc for ∆Z > 0 (d) Avc for ∆Z < 0
Figure 2-9: Validating the voltage amplifier model: Avc . Impedances are purely real
(resistive).
which is neatly separable into an “op-amp gain term” and an “external element term.”
Model validation plots for CMRs in Figure 2-10 show good agreement for symmet-
ric mismatches up to about 100% in the feedback and input elements.1 For calculating
CMR with larger mismatches, the expression in (2.109) can be used for better accu-
racy as it is shows good agreement for large percentage mismatch (200%). Numerical
results from the half-circuit decomposition analysis in reference [58] are overlaid on
the lower plots. In Figures 2-10(a) and 2-10(b), the results from reference [58] are
trivial because that analysis does not consider mismatches in feedback elements. In
Figures 2-10(c) and 2-10(d), the results from reference [58] fail to predict the key
1
CMRR is defined here as the logarithmic version of CMR measured in decibels, CMRR ≡
20log10 |CMR|.
71
feature, the null in the CMRR for nonzero-valued mismatches because that analysis
does not consider the finite op-amp gain, ac .
CM Rejection Ratio (Avc/Avd) vs. Feedback Elt. Symmetric Mismatch CM Rejection Ratio (Avc/Avd) vs. Feedback Elt. Symmetric Mismatch
20 10
0
0
−20
−10 Calculated CMRR
Calculated CMRR
CMRR (db)
CMRR (db)
s
−40
−20 Simulated T−model
−60 Zf = 200Ω Simulated Π−model
Calculated CMRR
Calculated CMRR −30 Gray and Meyer
−80 s
Simulated T−model
−100 Zf = 100Ω Simulated Π−model −40 Zf = 100Ω Zf = 200Ω
Gray and Meyer
−120 −50
−1 0 1 2 −1 0 1 2
10 10 10 10 10 10 10 10
∆Zf (%) ∆Zf (%)
(a) CMRR for ∆Zf > 0 (b) CMRR for ∆Zf < 0
CM Rejection Ratio (Avc/Avd) vs. Input Elt. Symmetric Mismatch
CM Rejection Ratio (Avc/Avd) vs. Input Elt. Symmetric Mismatch Z = 100Ω Resistive, f=1kHz, ad=2.79M, ac=8,771
Z = 100Ω Resistive, f=1kHz, ad=2.79M, ac=8,771
10
20
Calculated CMRR
Calculated CMRRs
0
0 Simulated s−s Op−amp
Simulated T−model
−10 Simulated Π−model
−20 Simulated LTC6404−1
−20 Gray and Meyer
CMRR (db)
CMRR (db)
−40
−30 Zf = 100Ω
−60 Zf = 200Ω
Calculated CMRR −40 Zf = 200Ω
Calculated CMRR
−80 s
Simulated s−s Op−amp −50
Simulated T−model
−100 Zf = 100Ω Simulated Π−model
−60
Gray and Meyer
−120 −70
−1 0 1 2 −1 0 1 2
10 10 10 10 10 10 10 10
∆Z (%) ∆Z (%)
(c) CMRR for ∆Z > 0 (d) CMRR for ∆Z < 0
Figure 2-10: Finite op-amp CM gains, ad and ac , lead to a null in the CMRR at
nonzero mismatch values.
The cancelation effect at nonzero-valued mismatch results from the finite DM and
CM gains of the op-amp, ad and ac , as is clear from the CMR expression in (2.110).
For example, with Zf = 100Ω, the optimal mismatch for the LTC6404-1 for either the
feedback or input element mismatch alone is about 0.61% as shown in Figure 2-10. In
theory, arbitrarily small CMR values could be obtained by adjusting the mismatches
to achieve zero-valued CM-DM gain. In practice, such control over the mismatch is
perhaps difficult. The zero-crossing of the CM-DM gain, which leads to the null in
the CMRR, is also evident in the plot of Figure 2-7(b) from Section 2.3.1. Note that
the plots for CMRR in Figure 2-10 approach the CMRR of the op-amp, -50 db, for
72
zero-valued mismatches also in agreement with (2.110).
2.3.4 Sensitivity
The results in Sections 2.2 and 2.3 indicate good model accuracy having considered op-
amp gain parameters, ad and ac . Examining the sensitivity of the mathematical model
to those parameters may reveal the amount of modeling error caused by uncertainties
in our knowledge of the op-amp gain parameters. It may also reveal the amount that
particular performance metrics change as op-amp gain parameters vary in time due
temperature effects, etc. In either case, the simple derivative may be employed to
examine the effect of changes in the op-amp gain parameters.
For example, starting from (2.110), the value of feedback impedance mismatch,
∆Zf , corresponding to the null in the CMRR varies with op-amp gain parameters as
follows. The sensitivity to changes in DM-DM op-amp gain of the feedback impedance
mismatch value corresponding to the null is

∂∆Zf ac Zf
ad = − Z f + Z , (2.111)
∂ad CMRR→−∞ ad Z
∆Z=0
while the sensitivity to changes in CM-DM op-amp gain is

∂∆Zf ac Zf
ac = Zf + Z . (2.112)
∂ac CMRR→−∞ ad Z

∆Z=0
Analysis regarding the value of input element mismatch leads to similar results. Note
that the error due to changes in ad is simply the negative of the error due to changes
in ac .
As a numerical example, consider the nominal impedances Zf = Z = 100 Ω
and op-amp gain parameters from the simulations above. Using (2.111), a fractional
change in DM op-amp gain, ∂ad /ad = −0.15, corresponding to a multiplicative error
of 0.85, leads to an error in the location of the null of approximately +0.09% in
agreement with the results plotted in Figure 2-11. Figure 2-11 also illustrates the
effect of larger changes in ad . Naturally, the zero-mismatch CMRR should increase
73
as ad decreases, also in agreement with Figure 2-11.

CM Rejection Ratio A /A vs. Feedback Elt. Symmetric Mismatch
vc vd
Z1,2 = <Zf> = 100 Ω Resistive, f = 1 kHz, ad = 2.79 M, ac = 8,771
10
0 Calculated CMRR, a × 0.85
d
Calculated CMRR, a × 0.5
d
−10
Calculated CMRR, a × 0.1
d
−20
CMRR (db)
−30
−40
−50
−60
−70
−80
−1 0 1 2
10 10 10 10
∆ Zf (%)
Figure 2-11: Plots of CMRR for various multiplicative errors in op-amp gain ad
compared to the actual CMRR for the Linear Technology part LT6404-1.
2.3.5 Finite Op-amp Input Impedance
The results above were calculated based on the op-amp model in Figure 2-3 and the
assumptions described in Section 2.1.3. Model validation showed excellent agreement
among the calculated results and the behavior of a commercial FD op-amp. In general,
there may be a need to include other aspects in the op-amp model. The versatility of
the transimpedance amplifier abstraction developed in Section 2.2 was demonstrated
in a first example, by adding to it the input elements, Z1 and Z2 , yielding a voltage
amplifier. Here, we consider the addition of finite op-amp input impedance to the
idealized op-amp model of Figure 2-3.
The op-amp input impedance elements can be modeled as shunt impedances at
the op-amp input nodes to incremental ground. The addition of those impedances can
be viewed as a modification of the voltage amplifier analysis in Section 2.3 leading to
74
the four transconductances, Ydd − Ycc. Because the transimpedance amplifier model
responses were derived in terms of the input currents i+ and i− , only the voltage
amplifier analysis needs to be iterated.
Using the Thevenin equivalent circuits comprised of the input voltage sources and
impedances Z1 , Z2 and the additional op-amp input impedance elements, equations
(2.58)-(2.61) become
Zin1
(vsc Zin1 +Z1
− ecc )
i+ |vsd =0 = (2.113)
Z1 ||Zin1
Zin2
(vsc Zin2 +Z2
− ecc )
i− |vsd =0 = (2.114)
Z2 ||Zin2
Zin1
( 21 vsd Zin1 +Z1
− ecc )
i+ |vsc =0 = (2.115)
Z1 ||Zin1
Zin2
(− 12 vsd Zin2 +Z2
− ecc )
i− |vsc =0 = . (2.116)
Z2 ||Zin2
Starting from these modified constraints, one can re-derive the four tranconductances
in terms of op-amp input impedances, Zin1 and Zin2 , while keeping the same results
for the two transimpedances found in Section 2.2.
2.4 Experimental Validation
This treatment of FD amplifiers was motivated by an investigation of a particu-

lar capacitive sensing occupancy detector. The sensor, presented in [1], employs a
FD amplifier connected between two electrodes, to measure changes in a physically
balanced bridge network comprised of the lumped capacitances between conducting
bodies in the detection field. A half-circuit representation of the FD amplifier was
not suitable for capturing the effect of the arbitrarily varying capacitive impedances
in the bridge network nor was it sufficient to account for the effects of the amplifier’s
separate DM and CM current paths. Only a generalized model with an unbroken
structure could accurately represent these effects.
Figure 2-13 shows a schematic of the signal conditioning electronics for this ca-
75
2.4. Experimental Validation
pacitive sensor including the FD front-end amplifier. Also shown in the Figure is a
simplified depiction of the lumped element capacitive bridge network. The capacitive
impedances in the bridge network correspond to the input impedance elements Z1
and Z2 in Figure 2-1. The FD front-end amplifier is loaded by a FD multiplier circuit
used to synchronously detect modulations of the high frequency carrier signal caused
by the presence of the occupant. More details can be found in [1].
Sensor Reponse to a Passing Occupant for 3 Different Detection Ranges

150
Simulated 0.6 m
100 Measured 0.6 m
Simulated 0.45 m
Measured 0.45 m
50 Simulated 0.75 m
Sensor Output (mV)
Measured 0.75 m
−50
−100
−150
−3 −2 −1 0 1 2 3
Occupant Distance from Center of Detection Field (m)
Figure 2-12: Plot of simulated and measured occupancy sensor output data from
reference [1].
A comparison of experimental and simulated data further validated the analytical

modeling in this work. Experimental data was taken from an implemented capacitive
sensor using the electronics shown in Figure 2-13. Simulated data was taken from a
SPICE simulation of the experimental setup having replaced the front-end amplifier
with the circuit model of the FD amplifier in Figure 2-4(b). Finite op-amp input
impedances as well as coaxial shield stray capacitances were included in the simulated
model as shunt impedances at the input terminals to the transimpedance amplifier
circuit model. Model parameters, ad and ac , for the FD front-end circuit model were
76
taken from the datasheet for the THS4140 FD op-amp at the signal frequency, 50
kHz in this example.
Finite element modeling software, FastCapr , was used to determine the values
of the lumped element capacitances needed for the SPICE simulation. To simulate
a passing occupant, the FastCapr simulation was re-run for several different config-
urations of the system corresponding to different time steps as the occupant passed
through the detection field. Details can be found in reference [1].
Model validation results showing excellent agreement are plotted in Figure 2-12
for three different detection ranges as the occupant passes through the detection field.
2.5 Conclusion
A new approach for small-signal analysis of fully-differential (FD) closed-loop op-amp
circuits is presented. The approach is built upon the development a circuit model
for a FD transimpedance amplifier. The circuit model of the FD transimpedance
amplifier enables analysis and simulation of practical FD circuits and captures the
distinct CM and DM paths through the amplifier. Simulated model validation showed
excellent agreement between the calculated results and the performance of a commer-
cial FD op-amp. Experimental model validation showed excellent agreement between
the behavior of the simulated FD transimpedance amplifier circuit model and an
implemented capacitive sensor employing a FD front-end amplifier.
77
tronics
Measurement Electrodes Front End Amplifier Multiplier Low-pass Filter Buffer A/D
Cf 2 +12 V
Rlim
5 V
LT1236
+
Rf 2 +5 V
+12 V φ1 φ2
−
− Rlpf
LTC2051
Vref
RG-174 +12 V +5 V
Electrode 2 AD8620
− +
+
2.5 V + +
THS4140 vod
−12 V Vocm vo LTC2440
+ +5 V − −
+12 V To PIC
−12 V
Clpf −
−
φ2 φ1 LTC2051
Electrode 1 RG-174 AD8620
+
+ Rf 1
− Rlpf
−12 V
Analog Sw/s: ADG411 sensor output
Rlim
Cf 1
Lumped Element Capacitive Model
Cf 3
+5 V
Electrode 1 C11 Electrode 2
+12 V
Rpu φ2
−
Rf 3
AD790 C1 C2 C5 C6
Electrode 3 RG-174 + +
+12 V +
Phase Reference C9 C10
− −12 V +5 V Vs Vs
AD8620 C3 C4 C7 C8
− −
+12 V
+ Rpu φ1
−
−12 V
AD790
Occupant
+
Phase Reference Electrode −12 V
2.5. Conclusion
Figure 2-13: A simplified schematic of the fully-differential signal conditioning elec-
78
Chapter 3
Capacitive Sensing Fluorescent

Lamps
3.1 Introduction
The U.S. Department of Energy has identified “sensing and measurement” as one
of the “five fundamental technologies” essential for driving the creation of a “Smart
Grid” [59]. In 2008, occupant-oriented loads such as lighting, and heating, ventilation
and air conditioning (HVAC) accounted for 50% and 47% of the total consumed
electricity in the U.S. for the residential and commercial sectors, respectively [60]. The
integration of smart grid-enabled control into industrial power electronic systems and
occupant-based control of lighting have been shown to provide substantial benefits in
this regard [61–63].
This chapter presents an occupancy detector that exploits a fluorescent lamp’s own
stray electric fields as an excitation source for capacitive sensing (the lamp sensor).
Reuse of in-place fluorescent lamp infrastructure should support low-cost, widespread
deployment. Additionally, the sensor measures electric fields rather than IR, so the
usual limitations associated with PIR sensors are eliminated and true presence detec-
tion is feasible. Finally, by incorporating the sensor electronics in fluorescent lamps,
control of lighting based on occupancy detection can be particularly straightforward.
Reference [64] details an application example in which the lamp sensor directly con-
79
3.1. Introduction
trols the lamp’s power consumption using a custom dimming fluorescent lamp bal-
last [65–67]. Significantly, [64] demonstrates good detection sensitivity even at very
low bulb power (1%). The “autodimming” lamp obviates the need for frequent lamp
ignition which has been shown to impact bulb life [67, 68].
Pyroelectric Infrared (PIR) sensors have been used extensively for low-cost occu-
pancy detection [69–71]. Typically, the ability of a PIR sensor to function as a pres-
ence detector is limited by low-frequency noise or drift from changes in background
infrared radiation (IR). The measured signals can be bandlimited (high-pass filtered),
but the sensor effectively becomes a motion sensor, not a presence sensor [69, 70]. As
an alternative to PIR sensors, reference [4] presents a retrofit capacitive sensor for
detecting occupants using in-place utility wiring and demonstrates detection ranges
of about 1 m from the wire to the occupant. The sensor presented here demonstrates
detection ranges approximately three times as long as those in [4].
Reference [4] is one of many references that set a precedent for modeling a hu-
man as a conducting body. Other such precedents can be found in references [3, 5–9].
Figure 3-1 shows some human conductor models from those references. Reference [6]
demonstrates capacitive sensors for occupancy sensing in automobiles and [7] demon-
strates a human capacitive sensor for robotics applications. Other applications of
capacitive sensors include fingerprint sensing [72–75], MEMS accelerometers and po-
sition sensors [76–80], pressure [81], humidity [82], and angular speed sensors [83], an
underground power cable sensor [84], and a sensor for micro-fluids [85]. Capacitive
sensors are also found in Medical applications [9, 86, 87]. Reference [88] uses daylight
MEMS sensors to inform a lighting energy management system.
Section 3.2 reviews and develops the basic operating principles and modeling of
the lamp sensor system. Section 3.3 presents the implementation of a lamp sensor
including a discussion of key design principles and experimental data from a cart-
mounted lamp sensor. Section 3.4 presents the results of a range test for the cart-
mounted lamp sensor. Section 3.5 presents a new full system model and validates it
against experimental data from a hanging lamp sensor.
80
3. Capacitive Sensing Fluorescent Lamps
(a) 3D touchless computer (b) Modeling utility linesman (c) Utility wiring occupancy
mouse: [2] potentials: [3] sensing: [4]
(d) Human body capacitance (e) Passenger vehicle seat oc- (f) Human occupancy sensor
modeling for ESD studies: [5] cupancy sensing: [6] for robotics: [7]
(g) Conductor model of the (h) Capacitive sensing of the

human thorax for medical ap- heart for medical applications:
plications: [8] [9]
Figure 3-1: Examples of systems with human conductor models taken from references
[2–9].
81
3.2. Modeling
3.2 Modeling
The operation of the lampsensor system can be understood with a capacitive abstrac-
tion which models the behavior of the electrostatic fields coupling the conducting ob-
jects below the lamp. Implicit in this abstraction is the assumption that the electric
fields vary slowly enough that the system is quasistatic – an assumption that holds
for any reasonable lamp ballast operating frequency (10-100 kHz). In this section,
the link between electrostatic field modeling and the capacitive abstraction is briefly
reviewed starting from Maxwell’s equations. Then, the development of a capacitive
model is discussed by considering models of the key system elements.
The boundary conditions that arise from Maxwell’s equations are useful for study-
ing these interactions. For instance, from one of Maxwell’s equations, the electric
~ is equal
Gauss’ Law, the gradient (spatial derivative) of the electric flux density, D,
to the volumetric charge density, ρv , with units C/m3 , i.e.
~ = ∇ · ǫE
∇·D ~ = ρv . (3.1)
Taking a fixed volume of charge with charge density ρv , and shrinking its thickness to
zero yields a charged planar boundary with “surface charge density” ρs having units
C/m2 . For instance, for ρs = 1 C/m2 , a plane with area 1 m2 contains 1 C of charge.
Gauss’ electric law (3.1) then leads directly to a constraint on the electric flux density
on sides “1” and “2” of an arbitrary planar boundary (boundary condition):

n̂ · D~1 − D
~ 2 = ρs , (3.2)
where n̂, is a unit vector normal to the boundary surface, i.e. the discontinuity in the
electric flux normal to a boundary aries from the surface charge on that boundary.
~
~ = − ∂ B , the curl
From another of Maxwell’s equations, Faraday’s law: ∇ × E ∂t
of the electric field strength is proportional to the time derivative of the proximal
82
magnetic flux density. In integral form, Faraday’s law is

I
~ · dl = − ∂ΦB (t) ,
E (3.3)
S ∂t
where ΦB (t) is the magnetic flux impinging the surface, S, enclosed by the line integral
H
S
. Holding one dimension of the surface, S, fixed and pinching the other dimension
until it shrinks to zero, the magnetic flux and its time derivative through that surface
~ (the left
(the right side of (3.3)) also shrinks to zero. To make the closed integral of E
side of (3.3)) equal to zero, adjacent components of the electric field strength must
~ is:
be equal in magnitude and direction. Therefore, the boundary condition on E

~ ~
n̂ × E1 − E2 = 0 , (3.4)
i.e. tangential components of electric field strength are continuous. Combining the
boundary condition in (3.4) with the fact that the electric field strength inside a
~ at the surface
conductor is forced to zero reveals that the tangential component of E
of the conductor is zero. Therefore, the electric field must terminate normal to the
surface. Adding to this, the boundary condition on the electric flux density (3.2),
reveals that the electric field at the surface is both normal to the (conducting) surface
and equal to the surface charge density divided by the permittivity of the medium
~ = E~n =
around the conductor, i.e. E ρs
. The total charge in an area, A, on the
ǫ
surface of a conductor is therefore,

ZZ
Q(t) = ρs (t)dA
ZA
Z
=ǫ E~n (t) · dA,
~ (3.5)
A
so the charge is equal to the permittivity times the electric flux,
Q(t) = ǫΦe (t), (3.6)
where Φe (t) is the total electric flux impinging normal to the surface with area A. If
83
3.2. Modeling
the electric field impinging on the surface of the conductor is the result of the potential
on a second conductor, then the potential difference between any two points on those
two conductors is Z
vc (t) = ~ · d~s,
E(t) (3.7)
s
where (little) s is an arbitrary path between the two conductors. The voltage, vc (t),
must be the potential difference between any points on those two conductors since
they are both equipotential surfaces. Dividing the total charge on either conductor
by this potential difference, by definition, yields the capacitance, i.e.
RR
ǫ E~n (t) · dA
~ Φe (t)
C≡ RA =ǫ . (3.8)
~ · d~s
E(t) vc (t)
s
The current drawn onto a surface of area A, by an impinging electric field, E~n , must
be the time derivative of the total charge in that area. From (3.6), the current is then
∂Q(t) ∂Φe (t)

I(t) = =ǫ . (3.9)
∂t ∂t
Examining the expression in (3.9) reveals two key insights. First, the time-derivative
of the electric flux must be nonzero to support a current on the conductor (electrode).
Therefore, the electrical signal source must be time-varying and in most practical
situations will be ac. Second, the time-derivative between the electric field and the
current indicates a 90◦ phase shift for each sinusoidal component of excitation. A
measurement electrode can therefore be thought of as a transducer between electric
field and current. The transducer has a gain term proportional to the electrode area,
A, the permittivity of the space containing the electric field, ǫ, and the frequency
of the sinusoidal component of interest, ω. It also has a phase term equal to 90◦ .
Since the electric potential is always related to the electric field through a spatial
not a time-derivative, that 90◦ phase shift occurs between the capacitor voltage and
current as expected. Equation (3.8) implies that
ǫΦe (t) = Cvc (t) (3.10)
84
so that taking the time-derivative of both sides yields
∂Φe (t) ∂vc (t)

ǫ =C (3.11)
∂t ∂t
and comparing (3.11) to (3.9) reveals that
∂vc (t)
I(t) = C (3.12)
∂t
as expected.
The capacitive abstraction approach in this work generally attempts to lump con-
ducting objects in the lamp sensor system as nodes in a circuit model. For instance,
the backplane of the lamp, the measurement electrodes, and other large unmovable
conducting objects in the detection field are taken as conducting nodes in the system.
References [2–9] set precedents for treating a human as a conducting shell. Therefore,
the human “target” is also taken as a conducting (and moving) node in the system.
3.2.1 Modeling the Floor
It is difficult to generalize the floor below the lamp as a conducting or a nonconducting

plane. The correct treatment is perhaps dependent on the particular construction of
any given floor. Moreover, if the floor is taken as a conducting plane, it must then be
determined if it is sufficiently well-connected to any reference potentials in the system,
e.g. earth ground. Section 3.5 describes a method for controlling these ambiguities
by iteratively comparing simulated results to experimental data. For now, the floor
may simply be taken as another conducting node in the system.
3.2.2 Modeling the Source
Identifying a reasonable and useful model of the signal source is a key challenge in
forming the lumped-element abstraction of the lamp sensor system. The signal source
is derived from stray electric fields that couple from the ends and surfaces of the bulbs
to the other conducting objects in the system.
85
3.2. Modeling
First, the signal source should be qualified as either a voltage source (low impedance)
or as a current source (high impedance). Consider the circuit model of a driven flu-
orescent bulb in Figure 3-2(a). Typically, a fluorescent bulb will be driven by a
high-impedance (current) source as shown in Figure 3-2(a). Reference [89] argues a
resistor model of a fluorescent lamp bulb excited at high frequency. Data taken from
the fluorescent bulbs used in the experimental setup of Section 3.5 will confirm a bulb
model with a resistance of approximately 1 kΩ (see Figure 3-22).
Low-impedance Signal Source

1
R
3 bulb
+ Rth = 13 Rbulb
+
1
R
3 bulb
vmeas
iballast vmeas Cload
− −
1
R
3 bulb
(a) A high-impedance source drives the bulb (b) Loading impedances are small compared to
the effective source impedance.
Figure 3-2: Capacitive loading impedances on the signal source are very large com-
pared to the Thevenin resistance of the source.
With the resistor model of the bulb, the current source supports a potential dif-
ference between any two points along its length. In Figure 3-2(a), we take those
points to divide the bulb equally into three pieces. The circuit in Figure 3-2(a) is
re-drawn as its Thevenin equivalent in Figure 3-2(b). Typical operating bulb resis-
tances vary between 100 and 10 kΩ [89] and the Thevenin resistance in Figure 3-2(b)
is upper-bound by that value. Capacitances coupling directly to the source will be
shown in simulation (Section 3.5) to have values ranging between 20 fF and 30 pF.
At the ballast operating frequency, fc = 50 kHz, those capacitances correspond to
impedances ranging between 160 MΩ and 106 kΩ. The simplified picture depicted in
Figure 3-2(b) therefore indicates loading impedances that are large compared to the
effective source impedance. Therefore, the signal source is taken here as a voltage
(low-impedance) source.
To develop a voltage-source element representation of the signal source, each bulb
86
vbulb “weak” “strong”
iballast
Figure 3-3: Alternating linear voltage profile of a resistive bulb.
must be lumped into at least two pieces and those pieces must be assigned correspond-
ing (alternating) potentials. Figure 3-3 depicts the alternating linear voltage profile
along the length of a driven resistive bulb. If the bulb is lumped into two halves, the
half closer to the driven end may be called the “strong” half because the potentials in
that piece vary a lot with respect to the undriven end (the ballast common). Then,
the half closer to the undriven end may be called the “weak” half for obvious rea-
sons. A corresponding lumped element model of a single driven fluorescent bulb is
depicted in Figure 3-4. In Section 3.5, a capacitive model is evaluated in which the
vwk vs vend
− + − + − +
weak strong
− +
vbulb
Figure 3-4: Two bulb halves comprise the lumped element model of a single bulb.
signal source derived from a two-bulb lamp is represented using two lumped-element
models like the one shown in Figure 3-4.
87
3.2. Modeling
3.2.3 Signal Source Reference
In this electrostatic system, it is important to establish conceptions of the reference

potentials and surfaces that support current return paths as we develop lumped-
element models of the system. Because the signal source itself is a conceived elec-
trostatic model of driven fluorescent bulbs, the signal source reference potential and
its physical location in the system is perhaps ambiguous. In the signal source model
in Figure 3-4, the high potential end of the bulb (the strong node), may be taken as
the conducting surface from which currents leave the source and the low potential
end of the bulb (the weak node) may be taken as the surface which sinks those cur-
rents. Following this reasoning, we might choose to call the weak end of the bulb the
“signal source reference.” However, in practical configurations of the lamp, there may
be more than one bulb so the location and potential of the signal source reference
becomes muddied. Moreover there is no convenient way to electrically (ohmically)
connect to the conceived model of the weak end of the bulb.
A more convenient choice for the signal source reference is the ballast common
shown as a ground symbol in Figure 3-4 because a) it is separated from the weak
node in the bulb model by a relatively small (alternating) potential difference and b)
it is a physical node in a the ballast circuit that allows for explicit ohmic connections.
Therefore, in this work, the ballast common is called the “signal source reference”
and those two node names are used interchangeably. For example, when the signal
source reference is said to be explicitly connected to the lamp sensor power supply
ground, this means that the ballast common is connected (with a wire) to the ground
on the power supply for the lamp sensor electronics.
3.2.4 Capacitive Models and Limitations
Having lumped all of the key elements in the system as conducting nodes that may
or may not be driven to a particular potential, the electric field behavior may be
captured by considering the capacitive coupling between those nodes. Proceeding
along these lines, a circuit model of the relatively complicated system can be drawn.
88
The signal conditioning electronics can be taken to connect to that circuit at the
electrode nodes and the system response can be determined by various means. An
example of such a full system model is presented and evaluated in Section 3.5 using
capacitance extraction software and a SPICE simulation.
Perhaps the primary limitation of the lumped element capacitive model originates
in the modeling of the signal source. The electric field is related to the spatial deriva-
~ = −∇ϕ. When
tive (gradient) of the corresponding scalar potential field, i.e. E
the bulb is lumped into two distinct halves and each half assigned a single potential,
the variation of the actual potential along the length of those sections is neglected.
Furthermore, abrupt changes are implicitly introduced in the potential at the ends
of the bulb halves. The electric field corresponding to the lumped element model is
inevitably an approximation of the actual electric field. Section 3.5 will show that the
approximations inherent to the lumped-element model allow for acceptable prediction
of the system behavior.
3.3 Implementation
Section 3.2 conceived a circuit model of the lamp sensor system. This section con-
siders the design (and analysis) of a lamp sensor and appropriate signal conditioning
circuitry informed by the conceptual developments in Section 3.2.
The lamp sensor design combines two key operating principles, carrier suppression
and synchronous detection. Carrier suppression is achieved with a balanced or sym-
metrical excitation source and a differential measurement technique. Synchronous
detection is achieved through multiplication of the measured signal with an in-phase
reference signal. Figure 3-9 shows a simplified schematic of the implemented electron-
ics. For a detailed schematic see Appendix A.1. Typical passive component values
are shown in Table 3.1.
89
3.3. Implementation
Table 3.1: Typical system parameters and passive components.
Parameter Value
Rf 1,2 10 MΩ
Cf 1,2 7.5 pF
Rf 3 200 kΩ
Cf 3 660 pF
Rlim 20 Ω
Rpu 500 Ω
Rlpf 10 kΩ
Clpf 150 pF
fc 50 kHz
3.3.1 Carrier Suppression
The physical configuration of the lamp shown in Figure 3-5 includes two measure-
ment electrodes spaced symmetrically about the center of the lamp. The electrical
configuration shown in Figure 3-6 reverses the ballast connections to one of the two
bulbs. The result is a symmetrical electric field source. Coupling this lamp and elec-
trode configuration with a differential measurement yields a natural suppression of
unneeded carrier content. This carrier suppression is important for detecting very
small perturbations of the capacitive system caused by the occupant below the lamp.
Lamp Midpoint
L/2
Electrode 2
L/2
Spacing = L
Depth
Electrode 1
Figure 3-5: A diagram of the two-bulb fluorescent lamp and electrodes. The electrodes
are spaced symmetrically about the center of the lamp.
90
Ballast
Bulb 1
Bulb 2
Figure 3-6: Reversing the connections to one bulb in a two-bulb lamp yields the
desired symmetry in the electric field source.
A fully-differential transimpedance amplifier was used to achieve the needed car-

rier suppression. The analytical modeling effort in Chapter 2 supports the circuit
model in Figure 3-7(b). Based on the analytical results in Chapter 2, the approxi-
mate circuit model parameters are as follows. The impedance elements are

Zf
Zc = (3.13)
2
!
2Zf + 12 ∆Zf ac
Zd = (3.14)
(1 + ad )
and the dependent voltage sources as

∆Zf
ec (iid ) = −iid (3.15)
2

∆Zf Zf ac
ed (iic ) = iic − − . (3.16)
2(1 + ad ) 2(1 + ad )
Notably, the model indicates a low impedance path for purely differential-mode input
currents, i.e. a differential-mode virtual short-circuit between the input nodes of
the amplifier. Accordingly, the fully-differential transimpedance amplifier may be
91
3.3. Implementation
Zf 2
I+
Vsup+
+
+ − i+ 1
− +
Z
2 d
Vid A(s) Vod vo+
+ 1
e (i ) +
− 2 d ic − Zc
− + + vod (iid , iic )
ecc −
Vsup− 1
e (i )
+
−
i− 2 d ic
+
ec (iid )
I− − 1 − vo−
Z
2 d
Zf 1
(a) A fully-differential transimpedance amplifier. (b) A small-signal T-model approximation.
Figure 3-7: A fully-differential transimpedance amplifier and its approximate small-

signal model.
approximated as a short circuit between the measurement electrodes. Its output

voltage is proportional to the current that flows through that short circuit according
to (2.23). The circuit model in Figure 3-7(b) is validated as part of the full system
model in Section 3.5.
3.3.2 Synchronous Detection
front-end amplifier
Cmeas
q(t) r(t)
Carrier Z LPF +1 A/D To PIC
Cbig
Z
phase-reference amplifier
Figure 3-8: A block diagram of the signal conditioning system. Transimpedance

amplifiers are marked with a ‘Z’.
The block diagram in Figure 3-26 illustrates the synchronous detection scheme.
The carrier signal is the high-frequency alternating signal source originating in the
fluorescent lamp. Presence of the occupant in the detection field changes the amount
92
of capacitive coupling from the lamp to the electrodes and thus the amount of current
input to the front-end. This modulation effect is represented in Figure 3-26 with a
variable capacitor, Cmeas . A copy of the (unmodulated) carrier signal is fed forward
and multiplied with the output of the front-end amplifier. Multiplication by this phase
reference achieves specificity in phase and frequency leading to a significant rejection
of unwanted signals. A low-pass filter (LPF) attenuates the high-frequency residue
after demodulation to yield the low-frequency modulations caused by the occupant
below the lamp.
The synchronous detector primarily functions by multiplying the modulated signal

with a phase reference signal as described above. In the implemented synchronous
detector, a FD multiplier is controlled by the phase reference signal so that it in-
verts the incoming DM signal every half-cycle. A reasonable model for this effect
is a multiplication of the modulated signal by a square wave with zero offset and
unity amplitude. The demodulated signal can thus be written as a multiplication
between the Fourier series decomposition of a square wave, and the incoming signal.
The incoming signal may be comprised of a wanted portion with time-varying am-
plitude A(t) at the carrier frequency, ωc , and an unwanted portion with time-varying
amplitude E(t) at a different frequency, ωe . The result is
∞
4 X 1
q(t) = sin(ωc,n t + φc,n ) × (An (t) sin (ωc,n t) + En (t) sin (ωe,n t)) , (3.17)
π n, odd n
for the nth harmonic of the carrier frequency, ωc,n , where φc,n is the phase error
between the front-end output and the reference signal at the carrier frequency. Using a
trigonometric identity leads to a demodulated signal with a zero-frequency component
whose magnitude decreases with φc,n :
q(t) =
∞
4 X 11
An (t) (cos φc,n − cos (2ωc,nt + φc,n )) (3.18)
π n, odd n 2
11
+ En (t) (cos (ωc,n t + φc,n − ωe,n t) − cos (ωc,n t + φc,n + ωe,n t)) .
n2
93
3.3. Implementation
After low-pass filtering, the high-frequency content is stripped leaving,
∞
2 X 1 1
r(t) = An (t) cos φc,n + En (t) cos (ωc,nt + φc,n − ωe,n t) . (3.19)
π n=1,3,5...
n n
Further, if the LPF bandwidth is narrower than the difference between the carrier
frequency and the frequency of the unwanted signal, (ωc,n − ωe,n ), then the unwanted
signal (E(t)) is also stripped and the output becomes
∞
2 X 1
r(t) = An (t) cos φn . (3.20)
π n=1,3,5...
n
In our system, A(t) is the amplitude of the DM output voltage from the front-end
amplifier, vod (t). From Chapter 2, the DM output voltage might be approximated as
vod (t) ≈ 2Z f iid (t), which has an amplitude, A(t) = 2Z f Iid (t). Equation (3.20) can
then be re-written in terms of the DM input current to the front-end amplifier:
∞
2 X 1
r(t) = 2Z f Iid,n (t) cos φn . (3.21)
π n=1,3,5...
n
Further, assuming a single frequency component, the output reduces to
4
r(t) = Zf Iid (t) cos φ . (3.22)
π
The phase specificity of the synchronous detector is evident in equation (3.22) and
the frequency specificity was explicit in the analysis above.
94
95
tronics
Measurement Electrodes Front-end Amplifier Multiplier Low-pass Filter Buffer A/D
Cf 2 +9 V
Rlim
5 V
LT1236
Rf 2 +5 V
+9 V φ1 φ2
−
− Rlpf
LTC2051
Vref
RG-174 +9 V +5 V
Electrode 2 AD8620
− +
+
2.5 V +
THS4140
−9 V Vocm LTC2440
+ +5 V −
+9 V To PIC
−9 V
Clpf −
−
φ2 φ1 LTC2051
+
+ Rf 1
Rlpf
−9 V
Analog Sw/s: ADG411
Rlim
Cf 1
Cf 3
+5 V
+9 V
Rf 3 Rpu φ2
−

+9 V
− +
−9 V +5 V
Phase Reference
AD8620
+
+9 V
Rpu φ1
−9 V −
AD790
+

3.3. Implementation
3.3.3 Front-end Amplifier
The front-end amplifier was implemented with a fully-differential op-amp in a closed-

loop transimpedance configuration. The feedback components for the front-end were
chosen to satisfy constraints in noise performance and closed-loop stability. The
AD8620 op-amps shown in Figure 3-9 were chosen for their JFET input devices,
which draw very little input bias current and input-referred current noise.
The developments regarding circuit models and analysis of the fully-differential
transimpedance front-end amplifier from Chapter 2 are useful for modeling the system
response to capacitive coupling changes in the detection field below the lamp and for
understanding and assigning values to the distinct current paths supported by the
amplifier. The virtual short-circuit approximation quantified in Chapter 2 has already
been utilized as a basic operating principle concept in the current chapter (see Section
3.2). The circuit model of the front-end amplifier will be even more critical in the
full system simulation later in this chapter (see Section 3.5) and also in the chapters
that follow as it will inform the configuration of those systems. However, for the
present task of gaining an understanding around the nominal amplifier stability and
noise performance, a simplified analytical approach is used instead. Specifically, noise
performance and stability are evaluated having assumed perfect symmetry among
external homologous elements. Those assumptions will be apparent in the design-
oriented analyses throughout this section.
Three main considerations led to the choice of feedback impedance components
for the front-end amplifier including,
• Noise performance
• Closed-loop stability
• Phase-matching.
The transimpedance value should be large enough that the noise produced by
the amplifier itself does not overwhelm amplified signals of interest. The value of
the total impedance in the feedback network is equal to (half) of the nominal tran-
96
simpedance for the FD front-end based on equation (2.23). Therefore, either increas-
ing Rf 1,2 or decreasing Cf 1,2 increases the transimpedance value. The values of the
feedback impedance components themselves also influence the total amount of noise
contributed by the front-end. Section 3.3.9 will show that noise embedded in the
incoming signal currents dominates the total noise at the output of the sensor elec-
tronics implying that the implemented front-end is suitable in this regard. Because
the JFET-input buffers (AD8620) require very little input bias current, a very large
feedback resistor can be used. The transimpedance value at ballast operating fre-
quencies is then typically upper-bound by practical values for Cf 1,2 and in that case,
the transimpedance becomes capacitive.
The components that make up the transimpedance, Rf 1,2 and Cf 1,2 , should also
result in a stable closed-loop configuration. Section 3.3.7 derives the loop transfer
function and evaluates the stability of an implemented sensor front-end. Finally,
the transimpedance should be chosen so that the phase of the front-end output, with
respect to the ac signal source, is well-matched to that of the phase reference amplifier.
Section 3.3.4 shows that the implemented front-end amplifier achieves a calculated
phase error of about 1◦ and a corresponding multiplicative error factor of about 0.99.
Refer to Table 3.1 for typical front-end feedback component values.
3.3.4 Phase-Reference Amplifier
The phase reference is measured with a SE transimpedance amplifier that is capacitively-

coupled to the bulbs similar to the front-end amplifier. The phase reference electrode
can be taped to the bulb or to the ballast wire. It can also be built into the ballast as
a trace adjacent to the drive signal for the bulb or as an explicit capacitor coupling to
the ballast drive signal. The output of the phase reference amplifier drives opposite
inputs of two comparitors in order to generate two (barred and unbarred) control
signals for the FD multiplier.
It is important to realize the implications of using a SE amplifier to measure the
phase reference. Because the lamp sensor is a quasistatic system, every measured
current must have a return path. If the power supply ground of the lamp sensor is
97
3.3. Implementation
not explicitly connected to the signal source reference, the SE capacitively coupled
measurement will rely on stray return paths. In practice, we have observed little
or no measurable change in the behavior of the lamp sensor with or without an
explicit connection (short-circuit) between the power supply ground and the signal
source reference. This suggests that the stray coupling, although uncontrolled, is
both significant and unavoidable.
Three main considerations led to the choice of feedback impedance components
for the phase-reference amplifier including,
• Output Signal level
• Closed-loop stability
• Phase-matching.
The transimpedance value for the phase reference amplifier should be chosen so
that, given the configuration of the phase reference electrode, the amplifier’s output
signal is well-behaved. That is, the output signal should be large enough to support
good transitions in the comparators, but it should not saturate the output of the
phase reference amplifier. Depending on the particular implementation of the phase
reference electrode, the transimpedance value that satisfies this criterion is most easily
found by experimentation. Stability considerations for choosing the transimpedance
for the phase reference amplifier are addressed in Section 3.3.7.
The phase-reference amplifier’s output should be well-matched in phase to the
output of the front-end amplifier. From equation (2.23), the closed-loop frequency
response of the FD transimpedance amplifier can be approximated with the tran-
simpedance, 2Zf . Similarly, the closed-loop response of the SE amplifier can be
approximated by its feedback impedance value. Given the typical passive component
values from Table 3.1 the magnitude and phase of the closed-loop response for the
phase-reference amplifier is
|Zf 3 | = 4.82 kΩ (3.23)
∠Zf 3 = −88.6◦ (3.24)
98
and for the front-end amplifier,
|2Zf | = 424 kΩ (3.25)
∠2Zf = −87.6◦ . (3.26)
Equations (3.24) and (3.26) show a phase error of φ = 1◦ between the front-end
and phase-reference amplifiers’ closed-loop response at fc . From equation (3.22), the
multiplicative error factor corresponding to this phase error is
η = cos φ = cos 1◦ ≈ 0.99985. (3.27)
Because both the front-end and the phase-reference amplifiers are capacitively coupled
to the signal source and because η is close to unity, the outputs of the two amplifiers
should be well-matched in phase. Equations (3.24) and (3.26) also reveal that both
transimpedances are largely capacitive at the signal frequency, fc . Therefore, the
phase between the signal source voltage originating in the lamp and the outputs of
the two amplifiers should be nearly 0◦ .1 Refer to Table 3.1 for typical phase-reference
feedback component values.
3.3.5 Electrode Cable Shields
In this implementation of the lamp sensor, the electrodes are connected to the input
nodes of the amplifiers with shielded coaxial cables connected to the lamp sensor
power supply ground as shown in Figure 3-9. Those shields reduce coupling to the
wires between the electrodes and the electronics. However, they also present a sig-
nificant capacitance between the input nodes and power supply ground. That shield
capacitance has different implications depending on the configuration of the lamp
sensor system. For instance, if the power supply ground is well-connected or even
coupled to the signal source reference, those shields may actually shunt some of the
desired signal currents away from the amplifier. On the other hand, if the power
1
or 180◦ depending on the implementation, e.g. inverting or non-inverting amplification.
99
3.3. Implementation
supply ground and signal source reference are not well-connected, the shield capac-
itances should have a lesser impact on desired signal currents. In either case, the
shield capacitances should be taken into account when enumerating the stray input
capacitances at the input nodes of the amplifiers.
3.3.6 Stray Input Capacitances
There are some significant capacitances between the amplifier input nodes and power
supply or incremental ground in the implementation of the lamp sensor presented here.
These “stray input capacitances” largely consist of the coaxial shield capacitance
from the electrode cables, the stray capacitance between PCB traces and the input
capacitance of the AD8620 op-amps in the front-end amplifier. The total stray input
capacitance was measured, using an LCR meter operating at 50 kHz, between the
input node on the lamp sensor PCB connected to electrode 1 in Figure 3-9 and the
lamp sensor’s power supply ground.2 For this measurement, the lamp sensor was
powered off and the feedback passive components, Rf 1 and Cf 1 , were removed from
the PCB. An electrode with a 48-inch RG-174 electrode cable was attached to the
input node of interest. Typical measured stray input capacitances depended on the
particular PCB tested and they fell in the range:
120 pF < Cstray < 165 pF. (3.28)
For the analysis and modeling in the rest of this work, the total stray capacitance is
taken to be that measured for one particular PCB:
Cstray = 159 pF . (3.29)
For convenience, the stray input capacitances were assumed to be the same for both
input nodes of the front-end amplifier and for the input node of the phase-reference
amplifier.
2
Either input node yielded about the same capacitance.
100
3.3.7 Transimpedance Amplifier Stability
The feedback impedances for the front-end and the phase-reference amplifiers are
chosen with several considerations in mind. One key consideration is the closed-loop
stability of those amplifiers. Therefore, the choice of feedback impedances comprises
feedback compensation for both amplifiers.
Zf 1
Z1 Vsup+
+
+ −
−
Vid A(s) Vod

+
−
+
−
Vsup−
Z2
Zf 2
Figure 3-10: A circuit for calculating the loop transfer function in a FD amplifier.
Closed-loop stability is readily evaluated by analyzing the open-loop transfer func-

tions (“loop transfer functions”). The loop transfer function for the front-end can be
examined by analyzing the circuit of Figure 3-10. The analysis is simplified by assum-
ing symmetry between homologous elements (e.g. Zf 1 = Zf 2 = Zf and Z1 = Z2 = Z).
Assuming, that the CM feedback loop within the amplifier is stable, the output CM
voltage is fixed. In that case, only the DM output voltage, vod , varies. The DM
output voltage is
vod = ad (s)vid + ac (s)vic , (3.30)
for DM-DM op-amp gain, ad (s) and CM-DM op-amp gain, ac (s). If the amplifier in
Figure 3-10 is symmetrical and the CM output voltage is fixed, the CM input voltage
variation, vic , is zero volts. The DM output voltage reduces to
vod = ad (s)vid . (3.31)
101
3.3. Implementation
Using a voltage divider relation, the amplifier’s input voltages are
Z1
v+ = vo− (3.32)
Z1 + Zf 2
Z2
v− = vo+ . (3.33)
Z2 + Zf 1
Symmetry yields,
Z1 Z2 Z
= = , (3.34)
Z1 + Zf 2 Z2 + Zf 1 Z + Zf
Combining equations (3.32),(3.33) and (3.34) leads to
Z
vid = v+ − v− = −vod . (3.35)
Z + Zf
Equations (3.31) and (3.35) describe the negative feedback between vod and vid in
which the loop transfer function is
Z
L(s) = ad (s) . (3.36)
Z + Zf
The same result could be obtained using half-circuit analysis [56]. In fact, a half-
circuit analytical approach highlights the manner in which the JFET-input buffers
(AD8620) can be accounted for in the front-end implementation of Figure 3-9. Since
there is one JFET-input buffer for each side of the circuit, the overall DM-DM op-
amp gain for the front-end amplifier can be taken to be ad (s) × Hj (s), where Hj (s) is
the closed-loop transfer function of one JFET-input buffer. This again assumes that
the circuit is symmetrical, so that the two buffers are identical. More explicitly, if the
DM-DM gain, of the op-amp is defined so that
vod = vo+ − vo− = ad (s)(v+ − v− ), (3.37)
and Hj (s) multiplies each of v+ and v− in the front-end of Figure 3-9, the argument
102
above follows directly from the commutative property in (3.37), i.e.
vod = ad (s)(HJ (s)v+ − HJ (s)v− ) = ad (s)HJ (s)(v+ − v− ) (3.38)
so that the effective DM-DM gain of open-loop front-end amplifier is simply
ad,ef f (s) = ad (s)HJ (s). (3.39)
The loop transfer function for the implemented front-end amplifier is therefore
Z
L(s) = ad (s)HJ (s) . (3.40)
Z + Zf
A similar analysis leads to the loop transfer function for the (single-ended) phase-
reference amplifier:
Z
Lp (s) = aJ (s) , (3.41)
Z + Zf 3
in which aJ (s) is the DM voltage gain of the AD8620 op-amp, Z is the impedance
between the op-amp inverting input and incremental ground and Zf 3 is the value
of the amplifier’s feedback impedance, e.g. the parallel combination of Rf 3 and Cf 3
shown in Table 3.1.
Stray capacitances from the input nodes to ground enter into (3.40) and (3.41)
because they appear in parallel with the input elements, e.g. Z1 and Z2 in Figure
3-10. Therefore, Z in (3.40) was taken to consist of the stray capacitance shown in
equation (3.29). Increasing the stray capacitance at the input nodes decreases |Z|
and attenuates the loop-transfer function magnitude. In many cases, this effect will
actually increase the stability of the closed-loop system.
103
3.3. Implementation
Bode Diagram
Gm = Inf dB (at Inf rad/sec) , Pm = 75.9 deg (at 4.11e+007 rad/sec)
100
50
Magnitude (dB)
−50
−100
0
−45
Phase (deg)
−90
−135
−180
2 4 6 8 10
10 10 10 10 10
Frequency (rad/sec)
(a) Front-end, P.M. = 75.9◦
Bode Diagram
Gm = Inf , Pm = 90 deg (at 1.26e+008 rad/sec)
110
100
Magnitude (dB)
90
80
70
60
0
Phase (deg)
−45
−90
−135
1 2 3 4 5
10 10 10 10 10
Frequency (rad/sec)
(b) Phase-reference, P.M. = 90◦
Figure 3-11: Open-loop frequency responses showing suitable phase margin.
104
To evaluate the stability of both amplifiers, dominant pole models of the op-amp
dynamics were extracted from the datasheets [90, 91]. Those model parameters are
shown in Table 3.2. Finally, feedback impedances in this implementation were those
Table 3.2: Dominant Pole Models
Part Parameter Value

THS4140 GBW 2,238.7 Hz
[91] Dominant Pole 67 kHz
AD8620 GBW 150 kHz
[90] Dominant Pole 166 Hz
shown in Table 3.1. Bode plots of the corresponding loop transfer functions are shown
in Figure 3-11. Both plots show good phase margin indicating suitable stability.
Closer examination of the loop-transfer functions reveals the manner in which the
feedback compensation achieves closed-loop stability. The loop-transfer, L(s), for the
front-end can be re-written as

1 + Rf sCf
L(s) = ad (s)HJ (s) , (3.42)
1 + Rf s(Cin + Cf )
where Cin is the total capacitance from the either input node to ground. With the
dominant pole models, the gain terms ad (s) and HJ (s) each contribute one pole but
no zeros. The addition of Rf contributes one additional pole and the addition of
Cf contributes one additional zero (consider equation (3.42) for Cf = 0). Therefore,
L(s) contains three poles and one zero. The uncompensated loop transfer function
(Cf = 0 pF) would have been

′ 1
L (s) = ad (s)HJ (s) . (3.43)
1 + Rf sCin
The uncompensated loop transfer function, L′ (s), contains three poles and no zeros.
The bode plot corresponding to L′ (s) is shown in Figure 3-12. The uncompensated
system shows a significantly reduced phase margin compared to Figure 3-11(a) and
a non-infinite gain margin. The non-infinite gain margin reflects the fact that the
number of poles exceeds the number of zeros by three or more, so the phase exceeds
105
3.3. Implementation
-180◦ for some frequencies. Increasing the loop gain by the gain margin would result
in instability. The instability in the uncompensated front-end amplifier arises from
Bode Diagram
Gm = 41 dB (at 8.12e+006 rad/sec) , Pm = 30.3 deg (at 7.15e+005 rad/sec)
100
50
Magnitude (dB)
−50
−100
−150
−200
0
−45
Phase (deg)
−90
−135
−180
−225
−270
2 4 6 8 10
10 10 10 10 10
Frequency (rad/sec)
Figure 3-12: Bode plot of the loop transfer function for the uncompensated system
(Cf = 0) showing poor phase margin.
the two-pole roll-off near the cross-over (|L′ (s)| = 0 db) frequency. With the lack of a
zero in the vicinity, the phase is allowed to approach -180◦ at cross-over, hence a poor
phase margin. From (3.42) the feedback capacitance, Cf , adds a zero in the loop-
transfer function in the vicinity of at least one of the poles. This significantly reduces
the phase of the loop transfer function near cross-over thereby increasing the phase
margin of the system. The addition of the parallel capacitance, Cf , in the feedback
network is a form of lead compensation because it adds leading phase shift or positive
phase to the output signal relative to the input signal at all frequencies [92].
3.3.8 Fully-differential Synchronous Detector
The electronics between the front-end and the ADC are fully-differential (FD) pri-
marily because this eliminates the need for a differential-to-single-ended converter.
106
The FD signal chain also rejects CM pickup and power-supply disturbances.

The FD multiplier is implemented with a full-bridge of analog switches controlled
according to the measured phase reference signal. The FD low-pass filter is imple-
mented as an RC ladder and serves to attenuate the high-frequency residue left after
demodulation. Because band-limiting effects in the final ADC are significant, the
LPF may be viewed as an anti-aliasing filter while the majority of interpolation oc-
curs in the ADC itself. A typical sampling rate for the ADC is 14 sps. Taking the
corresponding Nyquist rate (7 Hz) as the low-pass bandwidth, the synchronous de-
tector will largely reject unwanted signals whose frequency differs from that of the
desired signal by more than 7 Hz. Given typical carrier frequencies near 50 kHz, the
synchronous detector effectively achieves extremely aggressive bandlimiting of the
incoming modulated signal.
Two chopper-stabilized op-amps buffer the output of the LPF. Those buffers
present a high input impedance to the preceding LPF and a low-output impedance
to the ensuing ADC. Therefore, inserting those buffers de-couples the frequency re-
sponse design constraints of the LPF from the maximum source impedance constraints
specified for the ADC [93].
3.3.9 Noise
The signal conditioning circuitry was designed to contribute less noise than the noise
inherent in the measured signal. To evaluate the implemented design in this regard,
the effects of individual noise sources originating in the electronics may be enumerated
as follows.
A noise model of the front-end amplifier is shown in Figure 3-13(a) [41]. A small-
signal noise model is shown in Figure 3-13(b).3 The following analyses are simplified
by assuming symmetry between homologous elements (e.g. Zf 1 = Zf 2 = Zf and
Z1 = Z2 = Z).
3
√
The notation here uses e to represent a noise voltage density with units V/ Hz and v to represent
voltages in the conventional sense.
107
3.3. Implementation
3.3.10 Op-amp Input-referred Noise
The effect of each noise source on the DM output, eod , can be evaluated separately
with a superposition approach. For instance, to determine the effect of the THS4140
part’s input-referred voltage noise, enT , the other voltage noise sources may be shorted
and the current noise sources open-circuited. Defining eid as the DM input noise
voltage, eic as the CM input noise voltage, and eod as the DM output noise voltage,
a KVL loop around the amplifier dictates that
0 = eid + enT + eod , (3.44)
which can be re-written based on the op-amp DM gain, ad , and CM gain, ac ,
0 = eid + enT + ad eid + ac eic , (3.45)
according to the equation eod = ad eid + ac eic . Collecting terms,
eid (1 + ad ) + eic ac + en = −eod , (3.46)
where eid and eic can be found from their definitions as follows. Identifying terminal
voltages, e+ and e− , the DM input noise voltage is
eid ≡ e+ − e− , (3.47)
which, under the assumption of perfect symmetry reduces as follows
1 1
eid = − eod + enT − eod = enT − eod . (3.48)
2 2
Similarly, the CM input noise voltage is
e+ + e−
eic ≡ , (3.49)
2
108
which, reduces as follows
− 12 eod + enT + 12 eod enT

eic = = . (3.50)
2 2
Substituting the results for eid and eic into (3.46) yields
enT
(enT − eod )(1 + ad ) + ac + enT = −eod , (3.51)
2
and simplifying leads to
1 + ad 1 + a2c
eod = enT + enT . (3.52)
ad ad
For most practical cases, ad /ac is large and eod can be approximated as follows
1 + ad
eod ≈ enT , (3.53)
ad
which can be further approximated under the practical assumption that ad >> 1 as
follows
V2
e2od,T ≈ e2nT . (3.54)
Hz
The analysis of the enJ sources on eod is equivalent except that there are two noise
sources corresponding to the two AD8620 parts, so
V2
e2od,eJ ≈ 2e2nJ . (3.55)
Hz
The input-referred current noise sources are drawn only for the AD8620 parts. The
input current noise from the THS4140 part multiplies the low output impedance of
the JFET-input buffers and should contribute no significant noise voltage. A KVL
loop can be written to account for each current noise from the AD8620 parts as
follows:
0 = eid − inJ Zf 1 + eod . (3.56)
109
3.3. Implementation
Equation (3.56) is similar to the expression in (3.45) except that the noise voltage, enT ,
has been replaced with the term −inJ Zf 1 . Therefore, the same practical assumptions
made in the analysis for enT apply here and the effect on eod can be approximated as
follows:
V2
e2od,iJ ≈ 2i2nJ Zf2 , (3.57)
Hz
where the factor of two accounts for the two separate current noise sources from the
two AD8620 parts.
3.3.11 Feedback Resistor Noise
The feedback resistors can be modeled as noiseless resistors in parallel with current
noise sources having a flat spectral density:
4kT A2
i2nRf = . (3.58)
Rf Hz
Multiplying the current noise from (3.58) with the feedback impedance, Zf , yields a
noise voltage across those feedback impedances
4kT 2 V2
e2nRf = Z . (3.59)
Rf f Hz
An analysis similar to those for the op-amp input-referred noise sources above reveals
that the contribution of the feedback resistor noise to the output of the front-end is
e2od,Rf ≈ 2e2nRf , (3.60)
which can be re-written

4kT 2 V2
e2od,Rf ≈ 2 Z . (3.61)
Rf f Hz
110
inRf 2
Rf 2
Cf 2
+12 V
−
enJ enT
AD8620 +12 V
+ − +
inJ −12 V THS4140 vod

+ −
+12 V
− −12 V
inJ AD8620
+
enJ −12 V
Cf 1
Rf 1
inRf 1
(a) Noise model of the front-end amplifier [41].
inRf 1
Zf 1
enJ enT
+ − + − e−
+ +
− 1
inJ 2 (ad eid + ac eic )
−
eid eod
+
1
inJ + 2 (ad eid + ac eic )
−
−
+ − e+
enJ
Zf 2
inRf 2
(b) Small-signal noise model of the front-end amplifier.
Figure 3-13: Noise in the front-end amplifier.
111
3.3. Implementation
3.3.12 Total Narrowband Front-end Output Noise
The noise density at the output of the front-end amplifier is generally frequency-
dependent. In particular equations (3.57), and (3.61) show that the noise density is
a function of the complex feedback impedance value. For instance the power spectral
density described by equation (3.61) is depicted in Figure 3-14. The synchronous
e2nRf
BWn

e2nRf
ωc
1
ωc log ω
Rf C f
Figure 3-14: Power spectral density of noise voltage due to feedback resistors.
detector will isolate a narrow band of frequencies around the carrier frequency as
suggested by Figure 3-14. In other words, the spectral density of the output noise
voltage will be approximately flat over the frequency range ωc ± 12 BWn . This nar-
rowband feature means that the value of the frequency-dependent noise contributions
can be well-approximated by evaluating those quantities at a single frequency, ωc .
Therefore, in (3.57), and (3.61), Zf may be approximated as Zf |ωc so that those noise
contributions become
V2
e2od,iJ ≈ 2i2nJ Zf |2ωc (3.62)
Hz
4kT V2
e2od,Rf ≈2 Zf |2ωc . (3.63)
Rf Hz
Finally, summing the power spectral densities for the various noise source contri-
butions at the output of the front-end yields the front-end output noise density:
V2
e2n,amp = e2od,T + e2od,eJ + e2od,iJ + e2od,Rf . (3.64)
Hz
112
Taking the square root in (3.64) and using equations (3.54), (3.55) and (3.63), the
front-end output voltage noise density becomes
s
4kT V
en,amp = e2nT + 2e2nJ + 2i2nJ Zf |2ωc + 2 Zf |2ωc √ . (3.65)
Rf Hz
3.3.13 Noise in the Synchronous Detector
To see how the synchronous detector processes the noise from the front-end, it is
necessary to consider the effect of the multiplier and the filtering that follows (Fig-
ure 3-26). To that end, we consider an in-phase and quadrature decomposition of
a hypothetical noisy signal. According to [10], a noisy voltage signal, n, with spec-
tral density No V2 /Hz in a frequency band centered on ωi can be divided into two
orthogonal components as follows:
n = nx + ny , (3.66)
where the in-phase component is
nx = x sin ωi t (3.67)
and the quadrature component is
ny = y cos ωi t. (3.68)
The amplitudes, x and y, are random time functions each with flat spectral density
No V2 /Hz. In analyzing the synchronous detector it is helpful to consider the noiseless
signal of interest as well [10]. For instance, taking
∞
X
vi (t) = Vij sin (ωij t) (3.69)
j=1
113
3.3. Implementation
as the input signal of interest to the multiplier and adding it to the noise signal yields
a phasor diagram like that in Figure 3-15 for j th frequency component. The phasor
diagram shows that nx contributes amplitude noise while ny contributes phase noise
to the input signal [10]. The situation depicted in Figure 3-15 is described by the
following equation:
vij + nj = Vij sin (ωij t) + xj sin (ωij t) + yj cos (ωij t). (3.70)
The synchronous detector isolates the in-phase part of this noisy signal, Vij sin (ωij t)+
xj sin (ωij t), leaving out the phase-noise contribution in yj cos (ωij t). After low-pass
filtering, the output of the synchronous detector including both noise and the signal
of interest is v
∞ uX∞
2 X 1 2u 1 p
r(t) = Vij + t ( xj )2 BWn . (3.71)
π j π j
j,odd j,odd
For simplicity, it is assumed that only the noise surrounding the fundamental fre-
quency is significant after demodulation. The contributions from the higher harmonic
terms are attenuated as 1/j for j = 1, 3, 5... in addition to the natural band-limiting
in the system. In an rms-sum, the noise contributions from the higher harmonic
terms quickly become insignificant. From (3.71), the total rms noise voltage from the
front-end amplifier at the output of the synchronous detector is approximately,
2 p
vn,amp ≈ en,amp BWn . (3.72)
π
vi + n
n y
ny
φi vi nx
Vi x
Figure 3-15: Phasor diagram for additive noise [10].
114
3.3.14 Total Noise at the ADC Input
Combining (3.72) with (3.65) yields the total noise voltage contribution of the front-
end amplifier at the ADC input (the output of the synchronous detector):
s
2 4kT
vn,amp ≈ e2nT + 2e2nJ + 2i2nJ Zf |2ωc +2 2
Zf |ωc BWn Vrms . (3.73)
π Rf
The noise bandwidth, BWn , is ultimately determined by the ADC, assuming the LPF
is a suitable anti-aliasing filter. For a typical sampling rate of 13.75 Hz, BWn , for the
LTC2440 part is 12.4 Hz [93]. Using the datasheets for the THS4140 and AD8620,
the individual noise densities are as follows [90,91]. The THS4140 part input-referred
voltage noise density is
nV
enT = 6.5 √ (3.74)
Hz
The AD8620 input-referred voltage and current noise densities are, respectively,
nV
enJ = 6 √ (3.75)
Hz
fA
inJ = 5 √ . (3.76)
Hz
Using these values along with the passive component values from Table 3.1 and a
nominal room temperature of T = 300 K in equation (3.73) yields the total noise
voltage from the front-end at the output of the synchronous detector:
vn,amp = 60 nVrms . (3.77)
in a frequency band from 0.1 to 12.4 Hz. Note that if the inputs to the THS4140 part
√
were left unbuffered, its much more significant input current noise of 1.25 pA/ Hz
would develop a noise voltage contribution of 2.8 × 10−13 V2 /Hz, several orders of
magnitude larger than the current noise term contributed by the JFET-input buffers.
In addition to the front-end, significant noise sources originate in the buffers that
follow the LPF and in the ADC. The noise sources at the ADC input for the entire
115
3.3. Implementation
signal conditioning chain are enumerated as follows [93, 94]. The noise contribution
from the front-end amplifier is
vn,amp = 60 nVrms (3.78)
in a frequency band from 0.1 to 12.4 Hz. The noise contribution from the buffer
op-amps is
vn,buf f = 1.5 µVp−p , typical in 0.1 − 10 Hz (3.79)
and the noise contribution from the ADC is
vn,AD = 250 nVrms , (3.80)
also in a frequency band from 0.1 to 12.4 Hz. From (3.78)-(3.80), the dominant noise
source originates in the buffers that precede the ADC inputs. Therefore, the front-end
is suitably low-noise in the sense that it is not the dominant noise source.
3.3.15 The Effect of Stray Input Capacitance on Noise
Section 3.3.6 discussed significant stray capacitances at the input nodes to the front-
end amplifier in a practical implementation. This section considers the effect of the
those stray capacitances on the noise contribution of the front-end amplifier. Figure
3-16 shows a noise model of the front-end amplifier having added the stray input
capacitances to power supply or incremental ground. In analyzing the circuit of
Figure 3-16(b), it is convenient to use the following approximations
Z1 = Z2 = Z (3.81)
Zf 1 = Zf 2 = Zf , (3.82)
116
as in the analyses above. It is helpful to take the following additional approximations
vod ≈ ad vid (3.83)
vod ≈ 2Zf iid (3.84)
where (3.83) approximates the CM-DM gain, ac , of the fully-differential amplifier to

be zero and (3.84) is the fully-ideal DM output voltage from the analysis of the FD
transimpedance amplifier in Chapter 2. Analyzing the circuit in Figure 3-16(b) leads
to the following front-end output noise densities. The noise density contribution from
the THS4140 part itself is 2
Zf
e2od,T ≈ e2nT . (3.85)
Z
The noise density contribution from the AD8620 input-referred voltage noise is
2
Zf
e2od,eJ ≈ 2e2nJ (3.86)
Z
and the noise density contribution from the AD8620 input-referred current noise is
e2od,iJ ≈ 2i2nJ Zf2 . (3.87)
Finally, the noise contribution from the feedback resistors is
4kT 2
e2od,Rf ≈ 2 Z , (3.88)
Rf f
so that the total noise voltage contribution of the front-end amplifier at the ADC
input (the output of the synchronous detector) becomes:
v !
u 2 2
2u Z f Z f 4kT
vn,amp ≈ t e2nT + 2e2nJ + 2i2nJ Zf |2ωc + 2 Zf |2ωc BWn Vrms .
π Z ωc Z ωc Rf
(3.89)
where we have taken the values of Zf and Z at the carrier frequency, ωc , e.g. Zf ≈
Zf |ωc because the synchronous detector output is narrowband. Equations (3.85)-
117
3.3. Implementation
(3.88) reveal that the contributions of the current noise sources to the output of
the front-end are approximately unchanged. On the other hand, the input-referred
Zf
voltage noise sources from the op-amps are gained by a factor Z
. For the typical
stray capacitance from Section 3.3.6 and the passive component values in Table 3.1,
Zf
the magnitude of the factor Z
at ωc is approximately
s

Zf2
≈ 21. (3.90)
Z2

ωc
With this gain factor, the total noise voltage from the front-end at the output of the
synchronous detector (compare to equation (3.77)) becomes
vn,amp ≈ 500 nVrms . (3.91)
The addition of stray capacitances at the input nodes caused the noise voltage sources
to be gained to the output while the effect of the current noise sources remained
approximately the same. The result was a significant degradation of the front-end
amplifier noise performance. The significant noise contributions at the ADC input
upon addition of the stray input capacitances are enumerated as follows. The noise
contribution from the front-end amplifier is
vn,amp = 500 nVrms (3.92)
in a frequency band from 0.1 to 12.4 Hz. The noise contribution from the buffer
op-amps is
vn,buf f = 1.5 µVp−p , typical in 0.1 − 10 Hz (3.93)
and the noise contribution from the ADC is
vn,AD = 250 nVrms . (3.94)
118
also in a frequency band from 0.1 to 12.4 Hz. From (3.92)-(3.94), the front-end is
suitably low-noise in the sense that it is still not the dominant noise source.
119
3.3. Implementation
inRf 2
Rf 2
Cf 2
+12 V
Cstray1 −
enT
enJ AD8620 +12 V
+ − +
inJ −12 V THS4140 vod

+ −
+12 V
− −12 V
inJ AD8620
+
enJ −12 V
Cstray2 Cf 1
Rf 1
inRf 1
(a) Noise model of the front-end amplifier [41].
inRf 1
Zf 1
Z1 enJ enT
+ − + − e−
+ +
− 1
inJ 2 (ad eid + ac eic )
−
eid eod
+
1
inJ + 2 (ad eid + ac eic )
−
−
+ − e+
Z2 enJ
Zf 2
inRf 2
(b) Small-signal noise model of the front-end amplifier.
Figure 3-16: Noise in the front-end amplifier with stray input capacitances.
120
3.3.16 Time-domain Noise Data
Whether or not the electronics as a whole are suitably low-noise depends on the noise
content inherent in the measured signals. Time-domain plots of typical noise at the
lamp sensor output are shown in Figure 3-17. Figure 3-17(a) shows data taken with
electrode cables attached and with the lamp turned off but with an artificial phase
reference signal driving the demodulator at 50 kHz. The typical (windowed) noise
level depicted in Figure 3-17(a) is 2.5 µVrms and is reasonably consistent with the
noise contributions listed in (3.92)-(3.88). Figure 3-17(b) shows time-domain noise
data from the lamp sensor once the lamp has been turned on. Typical (windowed)
noise levels for this case are 186 µVrms . Comparing the noise in Figure 3-17(a) to that
in Figure 3-17(b) reveals that the signal conditioning electronics contribute negligibly
to the overall noise content. Therefore, the signal conditioning electronics are suitably
low-noise. Matlabr scripts for computing the time-domain windowed noise values
can be found in Appendix A.3.
x 10
−6 Lamp sensor Output Lamp sensor Output
10 −0.017
8 −0.0175
6 −0.018
Vout (V)
Vout (V)
4 −0.0185
2 −0.019
0 −0.0195
−2 −0.02
−4 −0.0205
−6 −0.021
−8 −0.0215
0 20 40 60 80 100 0 20 40 60 80 100
Time (s) Time (s)
(a) Without Lamp: Avg. noise voltage in 10-sec (b) With Lamp: Avg. noise voltage in 10-sec
window = 2.51 µVrms window = 186 µVrms
Figure 3-17: Time-domain noise data taken from an experimental prototype lamp
sensor.
3.4 Range Test

A cart-mounted system, shown in Figure 3-18, was constructed to collect data and
to perform a range test using the lamp sensor. Examples of the output voltage
121
3.4. Range Test
data collected from the cart-mounted lamp sensor during the range test are shown in
Figure 3-19. Experimental setup parameters including passive component values for
the sensor are shown in Table 3.3.
Figure 3-18: A photograph of the cart-mounted lamp experimental setup
Data was taken for 20 different electrode configurations. Each configuration con-
sisted of an electrode spacing and depth as defined in Figure 3-5. Each sample
consisted of one pass of a human target walking in front of the horizontally mounted
lamp. The metric for each sample was the ac rms output voltage, Vac,rms . For each
configuration, 10 control samples (noise floor measurements) were taken with no tar-
get. Then, for each range in each electrode configuration, 5 samples were taken with
a target person passing in front of the lamp. A Z-test in Matlabr was performed
on the data comparing each 5-sample data set for each range to the control data set
for the corresponding electrode configuration. In our detection rule, the sample data
sets had to demonstrate a mean Vac,rms larger than that of the control data sets with
a confidence level of 99% or better. The resulting statistical data are shown in Table
3.4 at the boundary of the detection range. The range between the lamp and the
122
target varies along the columns. The electrode configuration varies along the rows.
Table 3.3: Range Test Experimental Setup Parameters.
Parameter Note / Value

Rf 1,2 1 MΩ
Cf 1,2 1 pF
Rf 3 80 kΩ
Cf 3 30 pF
fc 42 kHz
Phase Ref Elect. Taped to bulb center
Earth, gnd, Common Not explicitly connected
The Z-test measures the statistical likelihood that the means of two gaussian-
distributed random variables are different based on the mean and variance calculated
from sample sets of the two variables. The p-value quantifies the confidence level
of detection where, p is the probability that the means of the two sample sets are
equal. Thus a higher p-value indicates a higher probability that there is no detection.
Therefore, the confidence level, α, that there has been a detection is defined as:
α = 1 − p. (3.95)
For example the percent confidence for the 10 foot range in the configuration with
the electrodes two inches from the lamp and 28 inches apart (2x28) is
P C = 100(1 − p) = 100%(1 − 0.027) = 97.3% (3.96)
and it is rejected as a detection based on the 99% confidence level rule.

For each configuration in Table 3.4, the p-values for the data straddling the de-
tection range are highlighted. The highlighted data therefore indicate the detection
range for each configuration. From Table 3.4, it appears that the detection range
varies with the electrode configuration. Considering the differential measurement
between the two electrodes, it is intuitive that the sensitivity to the target should
increase as the spacing between the electrodes increases. It is also intuitive that the
sensitivity to the target should increase as the depth of the electrodes increases (as the
123
3.4. Range Test
Table 3.4: Detection Data p − values for Various Electrode Configurations at the
Limit of the Detection Range.
p-values
Spacing(in.) Depth(in.) 7ft. 8ft. 9ft. 10ft. 11ft. Noise Floor (µVac,rms )
44 5 0 0 0 2.53×10−4 0.328 54.5
4 0 0 4.63×10−7 0.0165 N/A 65.1
3 0 0 0 4.85×10−6 0.661 98.9
2 0 < 10−7 0.0426 N/A N/A 168.5
38 5 0 0 3.05×10−5 0.0240 N/A 61.8
4 0 0 4.93×10−5 0.865 N/A 67.3
3 0 0 < 10−7 0.133 N/A 62.7
2 0 0 0.00200 0.0160 N/A 74.0
28 5 0 0 0 < 10−7 0.306 45.2
4 0 0 1.19×10−4 0.676 N/A 70.7
3 0 0 < 10−7 0.884 N/A 52.3
2 0 2.62×10−5 0.00100 0.0270 N/A 65.3
19 5 0 < 10−7 0.382 N/A N/A 55.4
4 0 0 < 10−7 0.126 N/A 41.6
3 0 < 10−7 0.0120 N/A N/A 45.4
2 0 0 1.01×10−5 0.0340 N/A 42.2
15 5 0 < 10−7 0.0360 N/A N/A 40.9
4 < 10−7 0.0210 N/A N/A N/A 51.5
3 0 < 10−7 0.0640 N/A N/A 49.9
2 < 10−7 0.0120 N/A N/A N/A 57.2
electrodes are moved closer to the target). The trend of the detection range evident
in Table 3.4, matches our intuition about how the detection range should be affected
by the electrode configuration.
124
Lamp sensor output Lamp sensor output

−0.035 −0.052
−0.04 −0.054
−0.045
−0.056
Output voltage (V)
Output voltage (V)

−0.05
−0.058
−0.055
−0.06
−0.06
−0.062
−0.065
−0.07 −0.064
−0.075 −0.066
0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5
Time (s) Time (s)
4ft. 5ft.
−0.0595 −0.062
−0.06 −0.0622
−0.0605 −0.0624
−0.061 −0.0626
Output voltage (V)
Output voltage (V)

−0.0615 −0.0628
−0.062 −0.063
−0.0625 −0.0632
−0.063 −0.0634
−0.0635 −0.0636
−0.064 −0.0638
−0.0645 −0.064
0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5
Time (s) Time (s)
6ft. 7ft.
−0.0634 −0.0378
−0.0635
−0.0379
−0.0636
−0.0637 −0.038
Output voltage (V)
Output voltage (V)
−0.0638
−0.0381
−0.0639
−0.0382
−0.064
−0.0641 −0.0383
−0.0642
−0.0384
−0.0643
−0.0644 −0.0385
0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5 3
Time (s) Time (s)
8ft. 9ft.
−0.0442 −0.0482
−0.0442 −0.0482
−0.0443
−0.0483
Output voltage (V)
Output voltage (V)
−0.0443
−0.0483
−0.0444
−0.0484
−0.0444
−0.0484
−0.0445
−0.0445 −0.0485
−0.0446 −0.0485
0.5 1 1.5 2 2.5 3 0.5 1 1.5 2 2.5
Time (s) Time (s)
10ft. 11ft.
Figure 3-19: Examples of plots of sample detections from the range test. (Configura-
tion 44x5)
125
3.5. Full System Model
3.5 Full System Model
This section presents and evaluates a SPICE model of the lamp sensor system in-
cluding a lumped element capacitive model. A depiction of the model implemented
in LTSPICEr is shown in Figure 3-25.
3.5.1 SPICE Model
The SPICE simulation (Figure 3-25) includes a lumped element capacitive model like
the one described in Section 3.2, a circuit model of the front-end amplifier taken from
Chapter 2, and a model of the entire signal processing chain described in Section 3.3.
The netlist for the front-end amplifier can be found in Appendix A.4.2. The remaining
SPICE parameters can be found in Appendix A.4.3 and example capacitance values
can be found in Appendix A.4.4. With these components, the output voltage of the
synchronous detector, corresponding to equation (3.22), can be read directly from the
simulated results. The SPICE model can be used to validate the capacitive model
and the model of the electronics including the front-end amplifier model developed in
Chapter 2.
Phase Accounting
By accounting for the phase contributions in SPICE, the simulation is expected to

yield the correct polarity of the output voltage. The phase reference in the SPICE
simulation includes an additional 270◦ phase lag to account for the inversion in the
phase reference amplifier and the 90◦ phase contribution from the front-end ampli-
fier, not accounted for by the front-end SPICE circuit model.4 The ADG411 analog
switches shown in Figure 3-9 are active-low. This was accounted for in the SPICE
simulation by controlling the simulated switches with logically-inverted (“barred”)
versions of the control signals from the comparators.
4
The 90◦ phase contribution is due to the capacitive feedback elements in the real sensor front-
end. For simplicity, in the SPICE model, we take the entire feedback network to be purely real with
a resistance equal to the magnitude of the impedance of the actual feedback network.
126
3.5.2 Capacitive Model
The intent of the capacitive modeling approach in this section is to build the model
by considering all of the capacitances between all of the conducting nodes in the
system. Each conducting node is initially taken to be floating. Depending on the
configuration of the system or on measurements taken from the experimental setup,
some of those nodes may then be modeled as driven to a particular potential.
FastCapr - Capacitance Extraction
A capacitance extraction software, FastCapr , was used to determine the lumped

element capacitance values to insert into the SPICE simulation [95]. A screenshot
of the 3D model built for this purpose is shown in Figure 3-20. In the 3D model,
one can see the floor at the bottom, the human target on the left and the fluorsecent
lamp and electrodes (lamp sensor) above the center of the floor. Also included in the
model are other unmovable conducting objects such as a large cabinet on the left, as
well as overhead pipes, other lamps, a large duct and a power strip case that appears
at waist level. The 3D model in Figure 3-20 corresponds to the photograph of the
experimental setup in Figure 3-23(b).
Duct
Pipe Hanging Lamps
Cabinet
Target Lamp Sensor

Power Strip
Floor
Figure 3-20: A screenshot of the FastCapr 3D model
127
For each simulation, FastCapr generated an output matrix like the one shown in
Figure 3-21. The output matrices contained the values of the capacitances between
each conductor in the system. For instance, the matrix element at row 5, column
8, corresponded to the net capacitance between conductor 5 (the left electrode) and
conductor 8 (the target).5
Figure 3-21: An example FastCapr output matrix
Typical simulated capacitances are shown in Table 3.5. Those capacitances repre-
sent the simulation of the target under the left edge of the lamp in Figure 3-20 with
the lamp at a height of 2.43 m. Several capacitances in simulation are taken to be
fixed as the target moves under the lamp (“Assumed Fixed”) while only a few are
taken to vary while the target moves (“Vary with Target”). When the target passes
directly below the center of the lamp, many capacitances can also be assumed from
symmetry.
Simulating the Floor
Section 3.2, discussed the ambiguity concerning the correct model of the floor below
the lamp. The floor in the experimental setup was a tile floor on top of a concrete slab
of unknown construction. Two key questions arise: 1) is the floor is well-represented
by a conducting plane? and 2) if it is well-represented by a conducting plane, is it
well-connected to reference potentials in the system, e.g. earth ground? To control
these ambiguities, data from simulation was compared to data from the experimental
system with and without an artificial conducting floor made of aluminum foil. The
5
According to the Maxwell capacitance matrix format, mutual capacitances (off-diagonal ele-
ments) are reported as the negative of their actual value while diagonal elements are reported as
positive values. If the capacitance matrix has non-negative off diagonals, we expect that there has
been a problem with the extraction of the capacitance values [95].
128
Table 3.5: Typical Simulated Capacitances (shown for a target positioned under the
left end of the lamp sensor depicted in Figures 3-20 and 3-23(b)).
Capacitance Value Notes
Vary with Target
L. strong-Target 300 fF
R. strong-Target 167 fF
L. Electrode-Target 534 fF
R. Electrode-Target 187 fF
Backplane-Target 14.3 pF
Cabinet-Target 2.5 pF
Assumed Fixed
L. strong-L. Electrode 477 fF
L. strong-L. weak 126 fF
L. strong-R. strong 41 fF
L. strong-Cabinet 56 fF
R. strong-Cabinet 62 fF
L. weak-Cabinet 81 fF
R. weak-Cabinet 53 fF
L. Electrode-Cabinet 102 fF
R. Electrode-Cabinet 52 fF
Backplane-Cabinet 19 pF
L. strong-R. Electrode 27 fF
L. strong-Backplane 3 pF
L. Electrode-Backplane 3.1 pF
L. strong-R. weak 1.6 pF
Floor-Backplane 79.7 pF
Floor-Cabinet 121 pF
Floor-L. strong 321 fF
Floor-L. Electrode 401 fF
Floor-Target 42.4 pF “Shoe Capacitance”
artificial conducting floor was also connected and disconnected to or from the earth
ground reference. Because little change was observed in the measured output from
the experimental system among the three cases, it was speculated that the actual floor
below the lamp was well-represented by an earthed conducting plane. In the SPICE
model of Figure 3-25, this was implemented as a short circuit between the “earth”
and “floor” nodes. In the FastCapr 3D model of Figure 3-20, this is manifested as a
conducting plane below the lamp and the target.6
Having a conducting plane model of the floor, the effective depth of that con-
6
Segmenting the floor plane into smaller panels, as shown in Figure 3-20, aided the FastCap
simulator. In general, this method of breaking the conductors into pieces aided the simulation and
was a practical necessity for getting the simulator to work properly. Common results yielded by a
model without enough of this kind of granularity included “non-negative off-diagonals” and “failure
to converge” errors as well as prohibitively long computation times.
129
ducting floor (“effective conducting floor depth”) was also adjusted by comparing
simulated and experimental data. To that end, a conducting plane was positioned in
the FastCapr simulation some distance below the surface of the actual floor. That
distance was determined empirically, by closely matching the peak deviation of sim-
ulated data taken from the SPICE simulation to the peak deviation of corresponding
experimental data. The effective conducting floor depth was set using data with the
lamp set at a height of 2.43 m and then held fixed for the other experiments. The
final value of the effective conducting floor depth is shown in Table 3.6.
Simulating the Source
The capacitive model in Figure 3-25 includes a model of the signal source consistent
with the developments in Section 3.2. That is, in the signal source model, each bulb
consists of two nodes - “strong” and “weak”. Because the model in Section 3.2 divides
the bulb into two distinct pieces, it is necessary to assign each piece an alternating
potential with respect to the signal source reference. Based on the alternating linear
voltage profile of a single (resistive) bulb shown in Figure 3-3, it is convenient to
assign the model parameters for the signal source model in Figure 3-4 as follows:
1 1 1
vwk = vbulb , vs = vbulb , vend = vbulb , (3.97)
4 2 4
where the total bulb voltage is comprised of the three voltages, i.e.
vbulb = vwk + vs + vend . (3.98)
Figure 3-22 shows an oscilloscope shot of the bulb voltage and current under
the experimental conditions. It shows a bulb voltage amplitude of 200 V and an
operating frequency of about 50 kHz. With vbulb = 200 V, the pieces of the signal
source model become, vwk = 50 V, vs = 100 V, and vend = 50 V. The signal source
model parameters are summarized in Table 3.6.
130
Figure 3-22: Fluorescent bulb voltage (top) and current (bottom).
Note that the polarity and lack of phase shift between the measured bulb voltage
and current validates the assumption that the bulb is well-modeled at high-frequency
as a resistor. The bulb voltage and current in Figure 3-22 indicate a bulb resistance
of approximately 1 kΩ.
3.5.3 Connecting “Earth,” “GND,” and “Common”
In the lamp sensor system, there are several “reference potentials” including the lamp
sensor power supply ground (“gnd”), the ballast common (“common”), and earth
ground (“earth”).7 To simplify the simulation, all of those reference potentials were
explicitly shorted together in both the experimental setup and in simulation (see the
bottom left of Figure 3-25).8
Certain conductors were found to be connected to the reference potentials. It was
verified with an ohm meter (and a piece of sandpaper) that the pipes, fluorescent lamp
backplanes, duct and power strip case were earthed. Those corresponding nodes in
7
In the LTSPICE simulation, the triangular ground symbol is equivalent to any node labeled
“gnd.”
8
Shorting the ballast common to earth required that the L/N utility feed to the ballast be isolated.
131
Figure 3-25 were shorted to earth. On the other hand, the cabinet was not connected
to earth and was therefore modeled in Figure 3-25 as a floating node.
Some of the capacitances in Table 3.5 do not effect the simulated results depend-
ing on the connections between reference potentials. For instance, the capacitance
between the backplane and the floor is irrelevant when both the backplane and the
floor are taken to be connected to earth.
3.5.4 Simulation Procedure
The simulation was conducted using the FastCapr model in Figure 3-20. The simu-
lated capacitances were inserted into the SPICE model shown in Figure 3-25 and the
simulated lamp sensor output voltage was read directly from SPICE.
First, the fixed capacitances listed as “assumed fixed” in Table 3.5 were taken
from a FastCapr simulation with the target below the left end of the lamp. Then,
the simulated offset was measured by inserting all of the capacitances from that
FastCapr simulation into the SPICE model of Figure 3-25 and reducing the “vary
with target” capacitances by 10 orders of magnitude. The resulting output voltage
was saved so that it could be subtracted from the rest of the simulated output values.
Finally, thirty-seven separate simulations like the one depicted in Figure 3-20 were
used to model a passing occupant. For each simulation, the target was moved, in 20
cm increments, along the path that the real target in the experimental setup would
take. In the simulation, the left end of the lamp was positioned at the x-origin (x
= 0 m). The target started 3 m to the left of the origin in simulation (x = -3.0 m)
and was stopped 3 m beyond the right end of the lamp (x = 4.2 m). Simulation
parameters are summarized in Table 3.6. An example list (.lst) file for creating the
model in Figure 3-20 and the dimensions of the individual conductors can be found
in Appendix A.4.
132
Table 3.6: Simulation Parameters.

Simulation Parameter Note / Value Source
vbulb1,2 200 V Oscilloscope (Figure 3-22)
vs1,2 100 V Model (Section 3.2)
vwk1,2 50 V Model (Section 3.2)
fc 50 kHz Oscilloscope (Figure 3-22)
Zf 1,2 423 kΩ Calculated as |Zf | @ ω = 2πfc
Earth, gnd, Common Explicitly connected N/A
Electrode Depth 14.5 cm Meas’d electrodes to bulb surface
Electrode Spacing 98 cm Measured between electrodes
Lamp Height 2.28, 2.43, 2.58 m Measured from bulb surface to floor
Target Height 1.83 m Measured height of human occupant
Effective Conducting Empirical
Floor Depth -2.5 cm (Section 3.5.2)
3.5.5 Experimental Procedure
Experimental data was taken from the experimental setup shown in Figure 3-23(b).
The photograph in Figure 3-23(b) is labeled so that it is obvious how the experimental
setup corresponds to the 3D model shown in Figure 3-20. Figure 3-23(a), shows a
close-up of the hanging lamp sensor and its adjustable electrodes.
Data was taken for the target passing through a detection field 7.2 m long posi-
tioned symmetrically about the center of the lamp (along the black line on the floor in
Figure 3-23(b)). This path was chosen to correspond to the simulated path described
in Section 3.5.4.
Table 3.7: Experimental Setup Parameters.
Experimental Parameter Note / Value
Rf 1,2 10 MΩ
Cf 1,2 7.5 pF
Rf 3 200 kΩ
Cf 3 660 pF
fc 50 kHz
Phase Ref Elect. Integrated as Trace in Ballast
Earth, gnd, Common Explicitly connected
Electrode Depth 14.5 cm
Electrode Spacing 98 cm
Lamp Height 2.28, 2.43, 2.58 m
Target Height 1.83 m
Exactly 37 data points were taken from each pass in the experimental setup in
order to ease the comparison to the simulated data. At the sampling rate of 13.75 sps,
37 data samples took approximately 2 seconds. Some trial and error was necessary
133
Duct
Pipe
Other Hanging Lamps
Lamp Sensor
Cabinet
Power Strip
Floor
(a) A close-up photograph of the hanging lamp (b) A photograph of the experimental setup.
sensor.
Figure 3-23: Photographs of the hanging lamp experimental setup.
to acquire data that was situated symmetrically about the time axis in the resulting
output plot. The experimental offset was measured as the value of the first data point
taken from the sensor (corresponding to the case when the target is not well within
the detection field). That offset was subtracted from all of the experimental data.
Experimental setup parameters including passive component values for the sensor are
summarized in Table 3.7.
3.5.6 Model Evaluation
Figure 3-24 shows three comparisons between measured data taken from the lamp
sensor and simulated data taken from the circuit in Figure 3-25. The three plots in
Figure 3-24 correspond to three different lamp heights, 2.28 m, 2.43 m and 2.58 m
measured between the floor and the bottom of the bulb surfaces in the experimental
134
setup. They show good agreement among the simulated and experimental data.
Scripts for extracting data from the SPICE .log files and generating the plots in
Figure 3-24 can be found in Appendix A.4.1.
Sensor Reponse to a Passing Occupant for 3 Different Detection Ranges

150
Simulated 0.6 m
100 Measured 0.6 m
Simulated 0.45 m
Measured 0.45 m
50 Simulated 0.75 m
Sensor Output (mV)
Measured 0.75 m
−50
−100
−150
−3 −2 −1 0 1 2 3
Occupant Distance from Center of Detection Field (m)
Figure 3-24: Comparison between simulated and measured occupancy sensor output
data.
The system model in this section was presented “as-is” with little or no simplifi-
cation. That is, the intent was to include all of the capacitances between all of the
conducting nodes in the system as a starting point for a working model. Undoubtedly,
accurate prediction is possible without considering all of those capacitances. More-
over, the simulation likely discounts some capacitances that may influence the sensor
response. Finally, the limitations of the lumped-element capacitive model described
in Section 3.2.4 should be considered when evaluating the model presented here.
3.5.7 Effective Capacitive Sensitivity
From the lamp sensor response in Figure 3-24, and the simulated capacitances taken
from FastCapr , the sensitivity of the lamp sensor to changes in capacitances (effective
135
capacitive sensitivity) can be inferred. Table 3.8, shows the capacitances that vary
with the target for two different simulations. The first column shows capacitances
for the target positioned 40 cm to the left of the left end of the lamp (x = −100
cm). The second column shows capacitances for the target positioned 20 cm to the
left of the left end of the lamp (x = −80 cm). The third column shows the change
in those capacitances. In the lampsensor output plot of Figure 3-24, this corresponds
to a change of at least 10 mV. Compared to typical noise levels of about 200 µV, like
those in Figure 3-17, a deviation of 10 mV is quite significant. Therefore, based on
simulation and experiment, the lamp sensor appears to easily measure changes in the
capacitances below the lamp on the order of 10’s and 100’s of fF.
Table 3.8: Simulated Capacitance Change: x = −100 cm to x = −80 cm.

Capacitance x = −100 cm x = −80 cm Change
L. Source-Target 214 fF 266 fF 52 fF
R. Source-Target 100 fF 133 fF 33 fF
L. Electrode-Target 394 fF 475 fF 81 fF
R. Electrode-Target 116 fF 144 fF 28 fF
Backplane-Target 13.2 pF 13.8 pF 600 fF
Cabinet-Target 3.6 pF 3.0 pF 600 fF
136
Capacitive Modeling Signal Conditioning
137
drive1 drive2
vend1 C13 vend2

vinpfda vopfda
strong1 strong2 e1 vinpfda
C1 C3 C5 C7
Cstray
C11 C9 C10 C12 Front-end Model
vs1 e1 target e2 vs2
Netlist
C2 C4 C6 C8
See Section A.4.2
e2 vinmfda
weak1 weak2
C32 vinmfda vomfda
vwk1 vwk2 Cstray
common
strong1 e1 target e2 strong2
C14 C15 C16 C17 C18
weak1 weak2
floor
vopfda
C19 C20
C43 Rlp
strong1 e1 target e2 strong2 voutp
C25 C26 C27 C28 C29 − Clp

φ1 φ2
ltc2051
vmultp
vmultp vmultm +
weak1 weak2 Clp
backplane
Rlp
C30 C31 voutm
plifier Front end and the signal conditioning electronics.

C42 C44 φ2 φ1
strong1 e1 target e2 strong2 −
vmultm ltc2051
C35 C36 C37 C38 C39 +
weak1 weak2 vomfda

cabinet
phaseref
C41 C40
SINE(0 0.5 fcarr 0 0 270 1000)
vsupp
Reference Potential Connections
phaseref
− Rpu φ2
earth backplane C
+ vsupp vsupm
earth floor vsupp
+ +
− −
earth − Rpu φ1
Figure 3-25: A SPICE simulation of the capacitive model, F-D Transimpedance Am-
C
+
common
phaseref
3.6. Auto-dimming
3.6 Auto-dimming
This section presents the building blocks of a new autonomous and self-expanding
demand-side energy management system for lighting control. It is a demand-side
energy management system because the control of energy consumption is confined
to the demand or end-user portion of the power system. References [96–99] detail
the design of the “lamp sensor” which measures the lamp’s own electric fields to
detect human targets. Interfacing the lamp sensor with a dimming ballast creates
a smart auto-dimming lamp which uses the lamp sensor’s occupancy detections to
appropriately dim or brighten. These fine-grain occupancy detections may also be
used to adjust power consumption of other systems such as Heating, Ventilation
and Air Conditioning (HVAC). All of the electronics are made to fit inside a ballast
box with the intent to create a drop-in replacement for standard ballasts. We have
also demonstrated a quasistatic frequency-modulated (FM) wireless link to enable
communication between adjacent lamps. By communicating with adjacent lamps,
one lamp can command a cluster or an entire room of lamps to turn on above an
occupant according to desired lighting schemes. The wireless link reuses the lamp
sensor electric field measurement and the action of the frequency-controlled dimming
ballast.
Because the performance of the lamp sensor system depends on many factors such
as ceiling height, electrode configuration, separation of lamps, the physical geometry
of the particular lamp case, etc., the auto-dimming lamp in this work is presented
as an example. From this example, we detail critical system characterizations that
must be understood by the system designer to implement a network of auto-dimming
lamps.
Section 3.6.2 presents system characterizations necessary to implement the auto-

dimming lamps including the lamp as a signal source and the lamp sensor signal-to-
noise ratio (SNR) across dimming levels. It also presents example characterizations of
three critical non-idealities in the lamp sensor system: drift, offsets and offset settling
after switching between dimming levels. It then presents a strategy for using this
138
Main Front-end Amplifier

Electrodes
Z LPF +1 ADC
Clock
Electrode
Z
To PC
PIC
Clock Amplifier
Dimming Ballast DAC
Isolator and Soft-start

Figure 3-26: The block diagram of the auto-dimming lamp sensor. Transimpedance
amplifiers are marked with a ’Z’.
information to design an auto-dimming lamp including auto-calibration and detection

strategies as well as a demonstration of a real auto-dimming lamp. Section 3.6.6
presents a novel wireless link between adjacent lamps including the design, simulation
and measurement of a phase-locked loop (PLL).
3.6.1 Dimming Ballast and Lamp Sensor Interface
A simplified schematic of the dimming ballast is shown in Figure 3-27. It is designed

to operate the lamp between 1.3% and 90% of the full specified power for two T8
32W bulbs. The ballast adjusts the lamp power or brightness by changing its output
(excitation) frequency relative to the natural frequency of the LC tank created by
Lres and Cres . The ballast adjusts its excitation frequency from 64.4kHz to 41.7kHz
for minimum to maximum lamp power respectively.
The frequency-controlled dimming ballast is designed around the International
Rectifier part IR21592 [11]. The ballast consists of a utility-line rectifier and boost-
mode power factor corrector (PFC). The STMicroelectronics part L6561 handles the
power factor correction and dc-dc up-conversion for the high-voltage dc input to the
139
3.6. Auto-dimming
inverter stage of the ballast. The IR part controls the half-bridge inverter that drives
the lamp output stage. The lamp output stage consists of two fluorescent bulbs in
series with a “balance transformer”, a shunt resonant capacitor and a series resonant
inductor. The balance transformer matches the currents in the two bulbs to prevent
“winner-take-all” situations in which one bulb strikes before the other, loading down
the resonant tank output and preventing the other bulb from striking.
The IR part controls the lamp power as described in the IR21592 datasheet.
During dimming, the output stage is effectively an inductance in series with a parallel
bulb resistance and resonant capacitance. The current into the output stage is shifted
from the half-bridge output voltage somewhere between 0 and -90 degrees during
dimming. Zero phase-shift corresponds to maximum lamp power [11].
The IR21592 takes a dim level input voltage (0.5-5Vdc) command and generates
a reference signal. The phase between this signal and the gate drive signal is the
desired phase between the output current and voltage in order to achieve the proper
lamp power. The phase reference signal is compared to the inverter output current
and the resulting phase error forces the circuits voltage-controlled oscillator (VCO)
to steer the inverter frequency in the right direction. The VCO steers the frequency
until the phase error between the output stage current and the reference signal is
forced to zero yielding the desired lamp power [11].
Lbalance
L
Vdd LresB LresC
N
Vdd 4 13
G 16
8 + LresA
Bulb1
Bulb2
Dim+ L6561 5 IR21592

PFC
Dim- 7
6 12 11
Cres
LresD LresE
Figure 3-27: A simplified schematic of the frequency-controlled dimming ballast. The

ballast is designed around the International Rectifier part IR21592 [11].
The lamp sensor-ballast interface consists of a buffered digital-to-analog converter

(DAC) and an optical isolation barrier as indicated in Figure 3-26. The optical isolator
and soft-start circuitry is shown in Figure 3-28. The optical isolator separates the
lamp sensor’s ground from the ballast’s ground. It also provides a high-voltage safety
140
barrier so that the lamp sensor is not easily damaged by dramatic failures in the
ballast. The soft-start is intended to protect the bulbs. It clamps the dimming signal
to the range 0.5-5V. It also brings the lower limit down slowly on startup so that the
bulbs are struck at a high dimming level and then brought down slowly if the lamp
sensor is either off or commanding a low dimming level.
10k
150k
−
150k +5V +12V
+ L
DAC out
LT2051 7805 Isolated N
10k AC/DC
Lampsensor
+5V +5V 20k
+12V
+5V
68 +12V +12V
10k
− − +
+ + 910k 33uF
- 10k
- + LT2051 LT2051 +
0.01uF 100k
20k Dim
Avago +5V
Optocoupler
Lampsensor gnd Ballast Common
"Isolation Barrier" "Clamping and Soft-start Circuit"
Figure 3-28: The optical isolator separates the lamp sensor common potential from
the ballast common potential. The soft-start protects the bulb by clamping the dim
signal to the range 0.5-5 V and brings the dim signal down slowly on startup.
3.6.2 Auto-dimming Considerations
This section presents examples of critical system characterizations, a strategy for

using those characterizations to design auto-calibration and detection algorithms and
a demonstration of the auto-dimming lamp.
Certain performance metrics depend strongly on the height of the lamp and the
electrode configuration. For the following discussion of the auto-dimming lamp, the
lamp height was 7ft. 4in. above the floor, the electrode depth was 5 in. and the
electrode spacing was 38 in.
141
3.6. Auto-dimming
3.6.3 Lamp Sensor SNR across Dimming Levels
The signal-to-noise ratio (SNR) of the lamp sensor system across dimming levels must
be determined as this constrains the detection range. To characterize the source, we
measured the bulb rms voltage across power levels. It is well known that the bulb
current-voltage (I-V) characteristics exhibit positive nominal resistance, but negative
incremental resistance for some operating regions [100]. That is,
V dV
> 0, but < 0. (3.99)
I dI
This means that decreasing the current in the bulb increases the voltage across it.
In Figure 3-29, the rms bulb voltage is plotted against lamp power. Lamp power is
calculated as the average power, i.e.
Pavg = (Irms Vrms ) cos φ (3.100)
where φ is the phase between the voltage and current. Percent lamp power is defined
as the power relative to the maximum bulb power, e.g. 32W. For instance, the lowest
lamp power shown, 1.3%, is 0.013×32W = 420mW.
Because lamp current increases monotonically with lamp power, the plot in Figure
3-29 can also be taken as the bulb’s I-V characteristic. The plot shows the familiar
negative incremental resistance to the right of the peak in the voltage near 25% lamp
power.
To characterize the lamp sensor sensitivity across power levels, we performed an

experiment with a hanging lamp sensor to measure the SNR with a 6ft.-tall person
under the lamp. Each detection consisted of the target passing through the entire
detection field of the lamp sensor yielding a peak-to-peak differential output voltage.
Each detection was repeated 5 times for each dimming level. Also, at each dimming
level, the windowed noise floor was measured in the time-domain by taking the average
ac rms voltage from 15 5-second windows with no target. The noise window length
was chosen to match the time it took to fully walk in and out of the detection field.
142
Bulb Vrms vs. Percent Full Bulb Power

170
Measured data
Fitted curve
165
160
155
Vrms (V)
150
145
140
135
130
0 10 20 30 40 50 60 70 80 90
Percent Power (%)
Figure 3-29: A curve fit of the rms bulb voltage plotted against lamp power (which
increases with rms current) shows the familiar negative incremental resistance of the
bulb.
The noise experiments were repeated after the entire first trial and these data were
averaged into the first data set in order to minimize the effect of long-term changes in
noise levels. The results are presented in Figures 3-30 and 3-31. SNR here is defined
as the peak-to-peak detection voltage of the human target divided by the ac rms
windowed noise voltage in the absence of a detection.
The signal from the lamp sensor increases to follow the bulb I-V characteristic
curve so that it shows a maximum around 25% lamp power as shown in Figure 3-30.
However, the sensitivity of the lamp sensor is quantified by the SNR. Because the
dominant noise originates in the bulbs and ballast, we might expect it to also vary
with the lamp power [96–99]. The SNR plot across lamp power levels in Figure 3-31,
shows that the sensitivity actually shows a maximum around 40% lamp power. Such
SNR characterizations will be necessary for the designer to determine at which power
levels detection is possible. In this experiment, we have shown a situation in which
detection is easily possible even at 1.3% (minimum) lamp power.
143
3.6. Auto-dimming
Detection Level vs. Bulb Power

400
Measured data
Fitted curve
380
360
Sensor Output (mV )
pp
340
320
300
280
260
0 10 20 30 40 50 60 70 80 90
Percent Power (%)
Figure 3-30: A curve fit of the detection signal bulb voltage plotted against lamp
power.
3.6.4 Characterization of Non-idealities
Characterization of output voltage offsets and transients when switching between

the dim and bright power levels are necessary for the design of auto-calibration and
detection algorithms. Despite correcting for phase errors, there are still measurable
offsets in the lamp sensor output voltage when switching between dimming levels.
These offsets may be due to differences in the voltage profiles of the two bulbs as they
are dimmed or due to un-corrected phase errors across dimming frequencies. Figure
3-32 shows a plot of the output voltage when repeatedly switching between dimming
levels. For these particular bulbs and dimming levels (8.1% and 59.4%), the difference
between output voltage offsets is about 40mV. The plot shows two important features.
First, the offsets are repeatable. That is, when switching back to a dimming level, the
output offset will be the same as it was the last time (ignoring drift). Second, there is
a consistent transient after each switch, after which the output voltage flattens. The
output voltage offsets and transients will determine the baselines for detection in the
144
Sensitivity vs. Bulb Power

5000
Measured data
4500 Fitted curve
4000
3500
3000
SNR
2500
2000
1500
1000
500
0
0 10 20 30 40 50 60 70 80 90
Percent Power (%)
Figure 3-31: A curve fit of the SNR plotted against lamp power shows a maximum
SNR around 40% power.
auto-dimming system. Deviations from the baselines will correspond to detections.

Characterization of output voltage drift ensures repeatable detection and trigger-
ing over time. Figures 3-33(a) and 3-33(b) show typical output voltage drift over a
period of 60 minutes (long-term) and 3.5 minutes (short-term) respectively for the low
lamp power level (8.1%). This data can be used to determine detection bands around
the baselines to account for drift. We know from previous experiments, that several
mechanisms contribute to drift including sources in the ballast and lamp [96–99].
Therefore, we may speculate that warming and cooling of the bulbs yields slowly
varying asymmetries between the two signal sources that appear as differential mod-
ulations of the measured signal.
145
3.6. Auto-dimming
Switching Dim Levels

0.01
0
Output Voltage (V)
−0.01
−0.02
−0.03
−0.04
−0.05
0 0.5 1 1.5
Time (min.)
Figure 3-32: The lamp sensor output voltage for repeated switching between dimming
levels. The two lamp power levels in this example are 8.1%(dim) and 59.4% (bright).
146
Long−term Drift Vout vs. Time
0.05
17mV Detections
0
Output Voltage (V)
−0.05
−0.1
−0.15
0 10 20 30 40 50 60
Time (min.)
(a) An example long-term drift output voltage plot; 17 mV in 60 min.
Short−term Drift: Vout vs. Time
0.04
0.039
0.038
Output Voltage (V)
0.037
6mV
0.036
0.035
0.034
0.033
0.032
1 1.5 2 2.5 3 3.5
Time (min.)
(b) An example short-term drift output voltage plot; 6 mV in 3.5 min.
Figure 3-33: Example Drift Plots for the Lamp Sensor output voltage. Both plots
show data taken for a lamp power level of 8.1% (dim).
147
3.6. Auto-dimming
3.6.5 Auto-calibration, Detection and Demonstration
This section shows how to use the characterization of non-idealities to implement an

auto-dimming lamp. A screenshot of the output display from the prototype auto-
dimming lamp is shown in Figure 3-34. The screen shot shows two different base-
lines for when the lamp is bright (59.4% lamp power) and dim (8.1% lamp power)
respectively. The baselines are the approximate output voltage in the absence of
detection and they are different because of the offsets described above. The two
baselines are generated during the auto-calibration which takes place on start-up.
The auto-calibration procedure uses the information gained from characterizing the
output voltage offsets and transients when switching between dimming levels. The
first auto-calibration procedure used was as follows. In the absence of a detection,
the lamp is first brightened and the output voltage is measured. The first 80 points
(about 6 seconds) are discarded as part of the switching transient depicted in Figure
3-32 and the remaining 20 points (about 1.5 seconds) are averaged. This average be-
comes the “bright baseline”. The lamp is then dimmed and the procedure is repeated
to generate the “dimmed baseline.”
The detection algorithm uses the information gained from characterizing the out-
put voltage offsets and drift. The detection algorithm used here was as follows.
When the lamp is dimmed, if the output voltage deviates from the dimmed baseline
by more than +/-17mV and the deviation persists for more than 200ms, then the
lamp is undimmed. When the lamp is brightened, if the output voltage returns to
within 10mV of the bright baseline and this persists for more than 200ms, the lamp
is dimmed again. The turn-on deviation level (17mV) is greater than the turn-off
level (10mV) to discourage multiple transitions. The timing delays serve at least 2
purposes. First, when the target passes under the lamp, it is possible for the output
to reach the baseline if the target is symmetrically positioned below the center of
the lamp. The delay in this case means that the target must not only be carefully
positioned under the lamp but it must stay that way for a little while. Second, the
delay adds further protection against multiple transitions when the output voltage is
148
Autodimmer Output Voltage
0.06
turn−on
turn−off
0.04
turn−off
0.02
dim baseline
Volts
bright baseline
−0.02
−0.04
−0.06 turn−on
20 40 60 80 100 120 140

Datapoints
Figure 3-34: This plot is a screenshot of the display for the autodimmer. It shows
the output voltage varying with the target and the two different baselines taken from
the auto-calibration. Jumps in the output voltage can be used to determine when the
lamp dimmed or brightened.
slowly varying.
More advanced auto-calibration procedures will make the auto-dimmer more ro-
bust and more sensitive. One obvious improvement would be to store the transient of
the output voltage after switching between dimming levels and use this to adjust the
baselines in real-time after switches. More advanced detection algorithms will also
improve robustness and sensitivity. For instance, it may be possible to not only con-
strain the deviation from the baseline, but also the time derivative of the deviation.
If the deviation is small, but the combination of the time derivative and the deviation
is unlike any drift or noise expected from the lamp sensor, then it may be possible
to rule that as a detection. Ultimately, we have the advantage that a “false-positive”
detection is not tragic. Therefore, in our detection algorithms we may lean toward
avoiding missed detections at the expense of a higher rate of false-positives.
149
3.6. Auto-dimming
3.6.6 Quasistatic FM Wireless Link
Zf
Freq. controlled Phase-Locked
FM in
Dim Dimming Ballast − Loop
(Same as electrode
Dim pin) fin fout
+
VCOin
Quasistatic Wireless Link FM out
Transmitting Lamp On Neighboring Lamp
Figure 3-35: A notional picture of the quasistatic wireless link system.
This section details the design and performance of the quasistatic wireless link for
communication between adjacent lamps. By communicating with neighboring lamps,
a detection by a single lamp could, for instance, command its neighboring lamps to
turn on as well, and command those lamps to tell their neighboring lamps to turn
on. Thus a particular lighting scheme may cause a single lamp, a cluster of lamps, or
an entire room of lamps to turn on upon an occupancy detection. Such a network of
auto-dimming lamps would self-expand as more lamps were added because the lamps
would each passively and wirelessly command their neighboring lamps to turn on.
150
1pF (bread board interrail)
5M
+5V +5V
Link Electrode +12V
− 10k +12V
− Data out
AD8620
+ C
1uF 10k + AD790
-12V FM out
+5V
+5V +12V
Signal In −
16 Rf
10k OP27
14 Phase 13
+
3 Comparator2 Cf
10k -12V
4
11 VCO VCO in
in
12 14
CD4046 8
R1 R2
7 6
C
(a) The schematic of the receiver including the PLL.
Phase
detector Loop Filter
fin Φin Φerr
1
+ Vout
s
Kd F (s)
−
Φo
Ko
s
VCO
(b) The dynamical block diagram of the PLL from input frequency to output baseband voltage.
Figure 3-36: The wireless link receiver and the PLL dynamical block diagram.
151
3.6. Auto-dimming
The wireless link is quasistatic because it does not use propagating electromag-
netic waves for transmission. It uses the same electric fields from the lamp that
the lamp sensor uses to detect occupants. The electric fields vary slowly enough
(∼50kHz) that the associated wavelengths for propagating waves at these frequencies
are extremely long compared to the length-scales of the lamp sensor system. It is
a frequency-modulated (FM) link because it transmits information by adding small
frequency deviations or modulations (∼+/-500Hz) to the high-frequency (∼50kHz)
ballast signal.
The notional drawing of the wireless link is shown in Figure 3-35. The baseband
or frequency modulating signal is input as small voltage deviations on the dim pin
of the dimming ballast. A single-ended transimpedance amplifier, similar to those
used in the lamp sensor, measures the frequency-modulated electric fields at the
receiving lamp’s electrode. The signal that is detected is input to a phase-locked loop
(PLL). When the PLL locks onto the input signal, the VCO input is a dc voltage
which corresponds to the input signal frequency. When the input signal frequency
changes, the PLL tracks those changes and the VCO input varies correspondingly.
The baseband or modulating signal is then available at the VCO input, which we call
the output of the PLL here.
3.6.7 PLL Design
The full schematic of the receiver including the PLL is shown in Figure 3-36(a). The
dynamical block diagram is shown in Figure 3-36(b). This PLL uses a phase detector
and VCO from the Fairchild Semiconductor part CD4046 [10]. The gain term, Kd , is
determined by the phase detector output voltage function for the connection shown
in Figure 3-36(a) [10]:
Θerr
Vpd = 2.5 V + × 2.5V (3.101)
2π
dVpd 2.5 V
Kd = = . (3.102)
dΘerr 2π rad
The gain term Ko is the VCO gain from input voltage to output frequency. The
152
external components R1 , R2 , and C determine Ko and the VCO center frequency, fo .

Using the CD4046 datasheet, these values were chosen to yield
fo = 57.4 kHz (3.103)
and
krps
Ko = 14.4 . (3.104)
V
Smaller modulations of the ballast frequency yield less visible flicker in the light.
The gain Ko could be as low as necessary for those modulations to fill the input
dynamic range of the VCO (0.5-4.5V). However, such a small Ko will lead to a small
gain-bandwidth product (GBW), Ko Kd , of the integrator in the loop. The transfer
function from fin to VCOin = Vout with a passive RC low-pass loop filter is
Vout (s) Kd /Rf Cf

= 2 . (3.105)
fin (s) s + s/Rf Cf + Kd Ko /Rf Cf
Recognizing Kd Ko as the GBW and the entire denominator of eqn. (3.105) as the
characteristic polynomial of a second-order system,
p(s) = s2 + 2ζωns + ωn2 (3.106)

s
GBW
ωn = (3.107)
Rf Cf
s
1 1
ζ = (3.108)
2 Rf Cf × GBW
where ωn is the natural frequency and ζ is the closed-loop damping ratio. From [92],
the bandwidth of this second-order system is
q p
ωh = ωn 1 − 1ζ 2 + 2 − 4ζ 2 + 4ζ 4 , (3.109)
which is always greater than ωn so that the closed-loop bandwidth, ωh , increases with
the GBW, Ko Kd , of the loop.
153
3.6. Auto-dimming
A small Ko will also limit the frequency range which the PLL can lock onto
(lock range). Instead, choosing a larger value of Ko increases the GBW of the loop
and the lock range. As a consequence, small frequency modulations only produce
small deviations of the VCO input voltage, so the threshold of the comparator at the
output of the system must be trimmed to be centered on those small deviations. A
tradeoff between noticeable flicker, PLL noise and PLL bandwidth falls out of this
discussion. If, for instance, we wanted to reduce the change in dimming levels to
reduce the noticeable light flicker, we could reduce the change in ballast frequencies
or modulation depth but this would also reduce the VCO input deviations. At some
point the VCO input deviations will fall below the VCO input-referred noise. To
increase the deviations we only have two choices: increase the flicker in the lamp, or
decrease the gain Ko of the VCO so that the reduced changes in frequency fill more of
the VCO input range. However, from above, we know that decreasing Ko decreases
the closed-loop bandwidth of the PLL. We can write a fundamental expression relating
these trade-offs in the PLL described here.
GBW = Ko Kd (3.110)
Ko ∆VCOin = ∆f (3.111)
GBW ∆f
= (3.112)
Kd ∆VCOin
To attenuate the high-frequency components of the phase-detector output while

maintaining reasonable loop stability, the LPF 3db frequency was chosen to match the
cross-over frequency of the integrator in the feedback loop shown in Figure 3-36(b).
That is,
1
ω3db = = Ko Kd = GBW (3.113)
Rf Cf
This strategy leads to about 45◦ of phase margin. The values for Rf and Cf in Figure
154
3-36(a) are
Rf = 2kΩ (3.114)
Cf = 0.1µF. (3.115)
Bode Diagram
40
20
Magnitude (dB)
−20
−40
−60
−90
Phase (deg)
−135
−180
2 3 4 5
10 10 10 10
Frequency (rad/sec)
Figure 3-37: Bode plot of the loop transfer function of the PLL.
The Bode plots of the loop transfer function and the closed-loop transfer function
are shown in Figures 3-37 and 3-38. They show 49◦ of phase margin and a closed-loop
bandwidth of 6.9krps or 1.1kHz. In this PLL, because the loop filter is a first-order RC
LPF, the average value of the phase detector output is the VCO input. Therefore, the
steady-state phase error, Θe (t) and the corresponding phase detector output voltage
varies with the steady-state VCO output frequency. Because the VCO input range is
0.5-4.5V, the extremes of the output frequency lock range in eqn. (3.101) correspond
to a phase error range of about +/-5 rad. Therefore, for all frequencies within the lock
range, the phase error is never more than +/-2π rad. and this PLL is not vulnerable
to skipping cycles during step transients or “cycle slipping” [101].
155
3.6. Auto-dimming
Bode Diagram
10
−10
Magnitude (dB)
−20
−30
−40
−50
−60
0
−45
Phase (deg)
−90
−135
−180
2 3 4 5
10 10 10 10
Frequency (rad/sec)
Figure 3-38: Bode plot of the closed-loop transfer function of the PLL.
The simulated and measured step response from the input signal to the VCO
input voltage are shown in Figures 3-39, 3-40 and 3-41. The measured step response
was generated with an FM-capable Agilent signal generator driving the input signal
to the PLL. The measured peak overshoot in the step response is about 1.2 which for
a second-order system corresponds to 45◦ of phase margin as predicted above [92].
The rise time of the measured step response is about 320µs which for a second order
system corresponds to a bandwidth of
2.2
BW ≈ = 6.9 krps = 1.1 kHz, (3.116)
tr
also as predicted above [92].
Finally, Figure 3-41 shows the step response using a transmitting lamp in place of
the FM signal generator. The lamp frequency in this example is modulated between
56.6 kHz and 55.6 kHz by modulating the lamp power between 36.3% and 45.3%.
156
Step Response
1.4
1.2
1
Amplitude
0.8
0.6
0.4
0.2
0
0 0.5 1 1.5 2 2.5
Time (sec) −3
x 10
Figure 3-39: Simulated step response from the input signal to the VCO input in the
PLL.
The rise time in Figure 3-41 is about 8.24 ms. This corresponds to a bandwidth of
BW = 43 Hz (3.117)
The PLL design is sufficient because the lamp is clearly the limiting factor in the
signal bandwidth.
3.6.8 Wireless Link Demonstration and Range
Figures 3-42(a) and 3-42(b) depict bitstreams transmitted with the wireless link.
For the system demonstrated here, the lamp power is modulated between 36.3%
corresponding to f = 56.6kHz and 45.3% corresponding to f = 55.6kHz. These
frequency deviations result in peak-to-peak VCO input voltage deviations of 700mV
centered on 1.9V near the center of the VCO input voltage range. The output data
is available at the comparator output in Figure 3-36(a).
157
3.6. Auto-dimming
Figure 3-40: Measured step response using an FM-capable Agilent signal generator.
Figure 3-41: The PLL step response with the lamp in the system shows a slower rise
time.
158
(a) A 3-byte long (24-bit) packet transmitted over the wireless link and demodulated
by the PLL (top) and frequency modulations are evident in the output of the receiver
front-end before demodulation (bottom).
(b) A sequence of 7 3-byte long packets.
Figure 3-42: Wireless link demonstration

159
3.6. Auto-dimming
The maximum distance between adjacent lamps for proper wireless link operation
affects lighting network design. To determine the link range, one lamp was used to
transmit data while a receiving electrode was moved away until there were visible bit
errors in the received packets. A dummy lamp under the receiving electrode modeled
the capacitive structure in a realistic system. As depicted in Figure 3-43, the adjacent
lamp end-to-end maximum distance was 3ft. 8in. The range between two parallel
lamps (broad-side range) was 2ft. 11in. The 45◦ range between the nearest corner of
the transmitting lamp and the nearest corner of the receiving electrode was 2ft. 3in.
Receiving Lamp
Receiving Lamp
2ft. 11in.
2ft. 3in.
Receiving Lamp Transmitting Lamp

o
45
3ft. 8in.
Figure 3-43: The measured wireless link range between the closest edge of the trans-
mitting lamp and the receiving lamp’s electrode.
160
Chapter 4
Dimmable Solid-state Lamp with

Integral Occupancy Detection
4.1 Introduction: Energy efficient lighting tech-

nology
New illumination sources and new power electronic controls for lighting have the
potential to produce energy efficiency gains of 240 percent in the residential sector
and 150 percent in the commercial sector [102]. In 2007, lighting accounted for 15.6
percent and 23.3 percent of all electricity consumed in the residential and commercial
sectors, respectively, in the USA, [102]. Efficiency gains from lighting sources and
active control can substantially reduce overall energy consumption. In particular,
solid-state lighting promises improved energy efficiency and long lifetime [103].
A fluorescent lamp with an integral occupancy sensor was demonstrated in [1].
By exploiting the lamp’s own stray electric field, the sensor system is able to detect
changes in the electric field below the lamp, [which includes people, or perhaps
autonomous mobile robotics that rely on machine vision]. Unlike standard
proximity sensors which require building planners to design for a proximity detection
system separate from the lighting system, this proximity sensor is essentially a drop-in
replacement for a standard commercial fluorescent lamp ballast.
161
4.1. Introduction: Energy efficient lighting technology
This chapter describes
• the application of the lamp sensor to a solid-state (LED, i.e. light emitting
diode) lighting array that detects occupancy both lighted and in the dark;
• the design and implementation of a wide dimming range LED driver (“ballast”)
using an inductor pre-charging method that is broadly applicable.
Design considerations for the ballast include those relevant to lighting, such as
power efficiency and consistent color cast, or chromaticity, across dimming levels.
Although, a hard-switching design using freewheeling diodes is demonstrated in this
work, it is possible to use synchronous rectifiers and soft-switching such as in [104–
106], to improve efficiency, with a tradeoff of additional active devices and related
components. The effects of DC and PWM (pulse-width modulation) dimming has
been studied for both RGB (red-green-blue) and phosphor-based LED light sources
[107–109]. A PWM technique, which shorts the inductor during off-periods for the
LED current is investigated in [110]. Multiple current-level driving techniques are dis-
cussed in [111] and [112]; and [113] proposes a hybrid PWM/AM dimming strategy.
Not only is the effect of dimming modulation on chromaticity a concern in lighting,
but also in LCD backlighting applications [114]. Although this work only discusses
operation of the LED driver in the PWM mode, the topology easily allows for opera-
tion in similar multi-level schemes where both the peak drive current and duty-cycle
can be independently controlled.
A PWM technique for multiple parallel LED strings that operates with power
factor correction (PFC) off the AC line is described in [115], and a flyback topology
also with PFC is detailed in [116]. If desired, PFC can similarly be applied to the
ballast described in this work.
In addition, both the ballast and the LED array topology must be designed to
support the lamp sensor electronics by driving the lamp with an alternating current
to produce an alternating electric field. The design and implementation of the ballast
for the LED lamp is discussed in Section 4.2. Finally, experimental data from the
lamp sensor built around the LED lamp are presented and compared to quasistatic
162
4. Dimmable Solid-state Lamp with Integral Occupancy Detection
models in Section 4.3.
4.2 Power Electronic LED Drive and Dimming

Power electronic drives represent a significant efficiency improvement over linear
power sources. In LEDs, light output is best controlled by regulating current. Some
difficulties in using the terminal voltage as the control include a negative temperature
coefficient that leads to thermal runaway and a poorly behaved exponential relation
to power output.
The salient characteristic of a linear regulator is that a voltage is dropped across
an element that continuously carries current, resulting in an inescapable power dis-
sipation. Linear current regulators can use active devices in either open-loop (e.g.
current mirror) or closed-loop (e.g. op-amp with a pass transistor). A voltage source
with a series resistor is also used in driving LEDs—the underlying approximation
is that the voltage drop across the resistor is large, hence approximating a current
source, which means that it is guaranteed that power is dissipated as heat by the
resistor. This approximation weakens at low current levels when dimming, resulting
in a drifting current level and hence light output.
Pulse width modulation of the current is an effective approach to driving an LED.
Not only is there an advantage in efficiency, but a number of studies have suggested
that there may be an advantage to the quality of lighting [107–109]. There are a
number of choices for the design of a switching current source. Our design was based
on several requirements, which include a bipolar source for proximity sensing, square
current pulses for color quality, and a wide dimming range.
4.2.1 High Brightness LED Modules
Currently, we use commercially available modules with 14 LEDs within a diode bridge.
Because these modules were originally intended to replace halogen lighting in low-
voltage 60 Hz sockets, slow recovery rectifier diodes were used in the bridge, resulting
in voltage waveform distortion and power loss when driven by a high frequency in-
163
4.2. Power Electronic LED Drive and Dimming
verter. The solution is to use diodes with better recovery characteristics. As we see
in the driver design below, the inverter operates at frequencies just above the au-
dio upper limit of about 20 kHz, yet below frequencies where more expensive high
performance diodes are needed.
The partitioning of these LEDs into bridged segments is an important considera-
tion for capacitive sensing because it determines the shape of the electric field source.
Ultimately, the design may consist of groups of LEDs consisting of fewer diode bridges
with a voltage distribution that is optimal for sensing and would result in lower cost.
The use of many uniform groups of bridged LEDs provides a proof-of-principle pro-
totype and allows a comparison with previous results using a fluorescent lamp (linear
voltage profile) field source [1].
Figure 4-1: Bidirectional LED modules.
164
4.2.2 Switching Current Source LED Driver
We selected a topology that consists of a buck converter with a hysteretic current

controller with a switching frequency in the range of a few hundreds of kilohertz and a
post-inverter in the 20–30 kHz range. A hysteretic-controlled, hard-switched converter
operating in the hundreds of kilohertz range provides a fast response without having
a power efficiency that is overcome by switching losses. By operating the inverter in
the 20–30 kHz range, capacitive sensing is effective, without driving too much reactive
current into the metal fixture.
A schematic of the power system is shown in Figure 4-2. The circuit is designed
to operate from a 170 V DC bus (nominal rectified line voltage) driving two parallel
strings of 40 mA AC LED modules anti-symmetrically, which are illustrated in Figure
4-1. The DC bus can of course be derived from an AC front-end, and can tolerate
variable levels of ripple to provide a complete ac-ac ballast solution. By operating
the buck converter in the continuous inductor current mode, nearly square pulses of
current are provided by the inverter to the LEDs, which has been suggested to help
maintain consistent chromaticity, or “color-cast” [107–109]. An advantage to this
topology is that it is possible to independently control both peak and average LED
current, which is useful in multi-level driving schemes, while maintaining a constant
brightness. The peak current is controlled by the buck converter and the duty cycle
by the full bridge.
Because the full-bridge inverter is driven by a current source with free-wheel diode,
D2 , no dead-time circuitry for the switches is necessary, which simplifies the de-
sign. Placing the current sense resistor at the bottom of the bridge enables ground-
referenced measurement of the inductor current, which is easier than high-side differ-
ential measurements, or switch current measurements which tend to be corrupted by
transients from gate drive charge injection or switch capacitance. Transformer T1 is a
1 : 1 provides galvanic isolation from the mains for safety and additionally allows one
to choose a potential reference (e.g. fixture ground), which may result in an improved
sensitivity in the lamp sensor.
165
D2
170 +
− G D1 A C
Vdc T1
B D
T2
Rsense
Figure 4-2: Schematic of the bipolar LED driver. Transformer T1 isolates the inverter
output. Transformer T2 matches the currents between the two LED bulbs.
An advantage to using AC to drive the LEDs is the ability to use low-cost trans-
formers to enforce current sharing among parallel lamps at good power efficiency.
Transformer T2 is a small current balancing transformer, similar to those that are
used in fluorescent lamp ballasts. The volt-second demands on this transformer are
small because they corresponds to the ensemble average of diode voltage mismatches
among LEDs in each string.
4.2.3 Dimming and Inductor Pre-Charging
Dimming is performed by symmetric tri-state PWM at the inverter. There is a

challenge in maintaining efficiency at high dimming (low-light) levels, where the duty
cycle is small. Conduction losses dominate if the converter is run continuously, but
alternatively, there are higher switching losses for on-off operation of the converter
because square current pulses cannot be achieved without a high switching frequency.
Square current pulses means a high current slew, which for on-off operation means
that for a fixed input voltage, a small inductor value along with continuous inductor
166
current is necessary, hence a high switching frequency.
dIL
Vinput = L ∝ L∆IL fsw , (4.1)
dt
where ∆IL is the inductor current ripple and fsw is the switching frequency.
We developed a driving method to help overcome the challenge of efficient dimming
at reasonable frequencies for hard switching, using a relatively simple converter and
control scheme, which is typically a factor in lowering cost.
4.2.4 Control Circuit Implementation
R2
GEN
R1
From +
Rsense IR2125
C GATE
−
DRIVE
LT1016 G
+5V
Figure 4-3: Hysteretic Current Controller.
The schematic for our hysteretic current-mode buck converter controller is shown
in Figure 4-3. A reference voltage to match the desired current (expressed as a voltage
across the current-sense resistor, Rsense ) is set with a potentiometer at the inverting
input of a high-speed comparator. A positive feedback loop splits this reference
into two hysteresis bands, which can be determined through superposition of the
comparator output and the voltage across the current-sense resistor, Vsense : when the
comparator’s non-inverting output is LOW (0V),
R2
V+ = Vsense (4.2)
R1 + R2
167
and, when the comparator’s non-inverting output is HIGH (5V),
R2 R1
V+ = Vsense + Vout (4.3)
R1 + R2 R1 + R2
The spread of these hysteresis bands is therefore equal to the difference between these
two terms:
R1
Hysteresis Spread = H+ − H− = Vout (4.4)
R1 + R2
Since typically R2 ≫ R1 , V− will approximately set the top hysteresis band, with the
bottom hysteresis band Vout R1 /(R1 + R2 ) below.
We set the potentiometer to obtain current regulation at 80mA (for two LED
strings at 40mA each). We set the hysteresis spread to correspond to a 10% current
ripple, with an Rsense of 10 Ω:
H+ − H− = Rsense∆i = 10 Ω · 8 mA = 80 mV (4.5)
Example control waveforms are shown in Figure 4-4.
Vsense
H+
H−
V+
V−
Figure 4-4: Example Hysteretic Controller Waveforms. Top: Current-sense voltage

Vsense . Bottom: Comparator non-inverting input V+ .
A first-order low-pass filter is placed on the current-sense input to attenuate
168
switching transients and prevent erroneous transitioning.

The gate enable (GEN ) signal is controlled by a DSPIC33FJ2560GP710 micro-
controller. This signal can be used to break open the control loop and shut down
the buck converter during the off-duty periods in between PWM pulses to recover
inductor current.
4.2.5 Symmetric Tri-State Pulse-Width Modulation
The switching pattern of the inverter generates a bipolar pulse-width modulated

current through the LED strings in which the individual pulses alternate in polarity
with each pulse, so there is zero DC current offset. Light output is controlled by
modulating the duty of these bipolar pulses. This is known as “symmetric tri-state
pulse-width modulation”. Typical symmetric tri-state PWM waveforms can be seen
in Figures 4-7 and 4-5, labeled “LED Current”.
We execute symmetric tri-state PWM using two modes, depending on duty ratio.
These two modes are continuous current mode (performed at high duty cycles greater
than 60%) and pre-charge mode (performed at low duty cycles below 60%). Each
mode is implemented in such a way as to preserve square current pulses through the
LEDs in order to [improve] color quality.
Continuous Current Mode
In continuous current mode the control circuit shown in Figure 4-3 is run constantly
(GEN = 1 always). This means that during the off-duty period between pulses, the
buck converter continues to regulate its current, which is shunted through a short
consisting of two inverter switches in series: either A and B or C and D, with the
corresponding complementary switches off. Keeping the buck in a continuous current-
regulating state allows square LED current pulses without the need for a very large
inductor di/dt. This way, we can still maintain tight current regulation using a large
inductance at the buck output.
Figure 4-5 shows the switching pattern at high duty cycle when continuous induc-
169
tor current is used. Figure 4-6 illustrates the median-filtered results at 96% inverter
duty-cycle, where the ballast is operating in continuous current mode. End-to-End
Lamp Voltage is the differential voltage across a single LED string. LED Current cor-
responds to the primary current of T1 and closely represents the sum of the currents
into the two parallel LED strings. A filtered version of Clock, with the spikes from
switching transient pickup eliminated, is used for synchronization by the lamp sensor.
CLOCK
PWM
G_EN
Buck
Inductor
Current
LED
Current
Figure 4-5: Timing Diagram Using Continuous Inductor Current.
170
Clock
5
Volts
−5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−4
x 10
End−to−End Lamp Voltage
200
100
Volts
−100
−200
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−4
x 10
Current Sense Resistor
0.2
Amperes
0.15
0.1
0.05
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−4
x 10
LED Current
0.2
0.1
Amperes
−0.1
−0.2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−4
x 10
Figure 4-6: Waveforms at 96% Duty-Cycle with Continuous Inductor Current.
Pre-Charge Mode
At low duty ratios, there is enough time during the off-duty periods between pulses to
turn off the current controller and recover inductor current. This is done by setting
the gate enable (GEN ) signal OF F , which opens up the current control feedback
loop. All switches in the inverter are likewise turned OF F . This turns diode D2
ON, hence recovering inductor current. In order to maintain a square LED current,
we pre-charge the inductor prior to inverter turn-on by letting the buck converter
regulate into the short created by turning ON either A and B or C and D, with the
complementary inverter switches OF F . Shorting the output of the buck converter in
this way results in the fastest pre-charge for any given input voltage:
Trise = LIpk /Vin (4.6)
Where Trise is the rise time of the buck converter output current and L is a
conservative estimate of the inductor value for all operating points and Vin is the
input DC voltage to the buck converter, which could either be measured by the
microcontroller, or set for worst-case low-line voltage. Note that the inductor fall
171
time during energy recovery is also equal to Trise .

Figure 4-7 shows the pre-charge mode switching pattern. Figure 4-8 shows the
median-filtered, low duty cycle waveforms where the ballast is operating in pre-charge
mode. The Current Sense Resistor waveform is the current through the resistor at
the bottom of the full-bridge, which represents the inductor current when the bridge
switches are conducting.
CLOCK
PWM
G_EN
Buck Pre-Charge
Inductor
Current
Energy Recovery
LED
Current
Figure 4-7: Timing Diagram Using Inductor Pre-Charging [and Energy Recovery.]
By turning off the buck converter and recovering the inductor current, conduction
172
Clock
5
Volts
−5
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−4
x 10
End−to−End Lamp Voltage
200
100
Volts
−100
−200
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−4
x 10
Current Sense Resistor
0.2
0.1
Amperes
−0.1
−0.2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−4
x 10
LED Current
0.2
0.1
Amperes
−0.1
−0.2
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−4
x 10
Figure 4-8: Waveforms at 10% Duty-Cycle with Inductor Current Pre-Charge.
losses are reduced for low duty ratios (D < 60%). Pre-charging has the same ad-
vantage of allowing for a square LED current without needing a very large inductor
di/dt, allowing us to utilize a large buck output inductance for tight current reg-
ulation, obviating the need for a very high switching frequency and the associated
switching losses.
4.2.6 Logic Generation
The inverter switching patterns and the gate enable signal are generated by a DSPIC33-
FJ2560GP710 microcontroller in combination with a fast programmable logic device
(PLD). The microcontroller produces three signals: CLK, P W M and gate enable
(GEN ). CLK controls the ballast operating frequency and corresponds to an internal
clock that determines the polarity of the inverter, while P W M controls the duty
ratio. GEN turns on and off the hysteretic current controller for the buck converter,
thereby setting the operating mode: continuous current (GEN = 1 always) or induc-
tor pre-charge. When operating in pre-charge mode, the duration of the GEN pulse
before the P W M pulse sets the pre-charge time.
The signals CLK, P W M, and GEN are fed into the PLD, which generates the
173
MCU Signals PLD Signals

Status
CLK PWM GEN A B C D
1 0 0 0 0 0 0 LED OFF
1 0 1 1 1 0 0 Pre-Charge
1 1 1 1 0 0 1 LED POS Current
1 0 0 0 0 0 0 LED OFF/Discharge
0 0 0 0 0 0 0 LED OFF
0 0 1 0 0 1 1 Pre-Charge
0 1 1 0 1 1 0 LED NEG Current
0 0 0 0 0 0 0 LED OFF/Discharge
Table 4.1: Truth table of all possible logic states.
drive signals for the four inverter switches (A, B, C, D) according to a truth table,
shown above as Table 4.1. The logic states shown in Table 4.1 are listed in the
sequence in which they would occur when operating in inductor pre-charge mode.
Although, the switching patterns are creating using a microcontroller and PLD for
research purposes, the logic table can easily be implemented as a simple state machine
in a range of low-cost, high-volume technologies.
4.2.7 Analysis of Power Electronic Losses
Table 4.2 illustrates power loss calculations of the hard-switched/pre-charging method

used in this work in comparison to maintaining the inductor current through a short
through the inverter bridge similar to [110]. In addition, the decrease in power loss by
using either synchronous rectifiers, or soft-switching alone along with pre-charging is
investigated. The calculations are based on IRF740 MOSFETs and MUR120 diodes.
The buck inductance (L) is 10.2 mH with a DC resistance (RdcL ) of 10 Ω. The flat-top
current (Ipeak ) to the LEDs is 80 mA with 8 mA of ripple, which results in a buck
switching frequency (fs ) of 216 kHz with an inverter frequency (fsi ) of 25 kHz. The
input (Vin ) is 170 Vdc and the output LED voltage is 150 Vdc.
The main advantage of the pre-charge/energy recovery technique in comparison
to only shorting the inductor is in the reduction of losses from the buck inductor at
174
Figure 4-9: A photograph of the LED lamp. Top: bright, Bottom: dim.
low light dimming levels. The additional losses from each pre-charging, or energy
recovery are mainly by the diode conduction during current ramp up, or down,
1
Ppc = Vdiode Ipeak Trise fsi .
2
These additional losses when instead, using a synchronous rectifier are dominated by
the inductor during the current ramping period,
1 2
Ppc = Ipeak RdcL Trise fsi ,
3
175
4.3. Experimental Setup and Results
which might be slightly underestimated because the DC resistance is used, but is

still useful in highlighting the improvement over only shorting the inductor. In the
calculation of the inductor loss during the operation of the buck converter, the DC
resistance is a good approximation in the continuous current mode with small inductor
ripple.
The transition switching losses for the MOSFETs were calculated using linear
ramp approximations of voltage and current [117], and the gating loss using a 12 V
gate drive. The main switching loss mechanism, which can be eliminated by soft-
switching, is the charge stored in the output capacitance in the buck MOSFET, that
is dissipated every cycle the MOSFET turns on,
1
Pcout = Cout Vin2 fs ,
2
Different conversion efficiencies are given only as an index for comparison because
only relevant, or dominating loss mechanisms are considered. Several tradeoffs can
be made to improve efficiency. For example, lower current MOSFETs with higher on-
resistance, but lower output capacitance and gate drive charge might be used instead
of the IRF740. Also, a physically larger inductor with lower losses might be used,
but this would impact power density. The purpose of the power electronic design is
to provide a ballast, which supports proximity sensing, that can be modified to take
into consideration the many requirements for a particular lighting use case.
4.3 Experimental Setup and Results
The experimental setup of the LED lamp and lamp sensor electronics is shown in
Figure 4-10. The lamp sensor output was measured as a conducting sphere (the
target) was passed under the lamp. Data was taken with the target fixed at 20 cm
intervals in the y-dimension as depicted in Figure 4-10. For each interval, the lamp
sensor output data was averaged for 20 seconds. The experiment was iterated for three
lamp power settings “bright” (Duty ratio of 96%), “medium” (Duty ratio of 60%)”,
176
Shorting Proposed Synchronous Soft Units

Inductor Pre-Charging Rectifier Switching
Dimming Duty Cycle 95% 10% 95% 10% 95% 10% 95% 10%
Buck Converter
Low-side Diode/MOSFET 5.4 0.6 5.4 0.6 0.4 0.04 5.4 0.6 mW
Inductor 64 64 64 6.4 64 6.4 64 6.4 mW
High-side MOSFET
Switching Losses
Transition 59 5.9 59 5.9 59 5.9 0 0 mW
Output Capacitance 375 38 375 38 375 38 0 0 mW
Gating 125 13 125 13 125 13 125 13 mW
On Resistance 3 0.4 3 0.4 3 0.4 3 0.4 mW
Current Sense Resistor 64 6.4 64 6.4 64 6.4 64 6.4 mW
Inverter
Switching Losses
Transition 6.8 0.7 6.8 0.7 6.8 0.7 0 0 mW
Output Capacitance 43 4.3 43 4.3 45 4.3 0 0 mW
Gating 14.4 14.4 14.4 14.4 14.4 14.4 14.4 14.4 mW
On Resistance 7 7 7 0.7 7 0.7 7 0.7 mW
Precharge/
Energy Recovery
Diode/MOSFET
Conduction Loss 0 11.5 0 0.6 11.5 mW
Inductor 0 2.6 0 2.6 2.6 mW
Total Loss 767 160 767 104 761 92 282 55 mW
Power Delivered 11.4 1.2 11.4 1.2 11.4 1.2 11.4 1.2 W
Dc-to-Output Efficiency 93.7% 88% 93.7% 92% 93.7% 92.9% 97.6% 95.6%
Table 4.2: Power Electronic Loss Comparisons
and “dim” (Duty ratio of 20%). A photograph of the lamp under the “bright” and
“dim” settings is shown in Figure 4-9. The experiment was also repeated for three
x-displacements: 0 cm, 22 cm, and 45 cm.
The analytical approach described in reference [118] was also used to model the
lamp sensor system. The electrostatic model of the lamp sensor consisted of conduct-
ing spheres representing the source nodes, electrodes and the target. The calculated
difference between the electrode potentials was taken to be proportional to the output
of the lamp sensor. Also, the floor was taken to be a conductor, so the model also
consisted of image spheres below the plane of the floor. Finally, the potential of the
“Lo” source nodes and of the plane of the floor was assumed to be earth ground.
To compare the analytical approach to measured data, the signal source parame-
ters used in the electrostatic model were first calibrated. A “training run” consisted of
taking measured data from the lamp sensor for known x and y displacements. Then,
an iterative least-squares optimization method was used to infer the effective signal
source parameters based on the measured data.
In the least-squares optimization method, the signal source parameters were first
177
Voltage Source
+ −
LED Driver
Earth
Voltage Source
Hi Lo
Backplane
+ − Lo LED Bulb Hi
PC RS-232 Lamp sensor Hi LED Bulb Lo
Conducting Sphere
0.97 m
Electrode 1 Electrode 2 Electrode 1 Electrode 2 25 cm
z 2.24 m
−y 1.02 m
Non-conducting Support
x
x=0
y = 140 cm y = 0 cm y = −140 cm
Figure 4-10: The experimental setup.
guessed. Then, the results of predicting the lamp sensor output using the electrostatic
modeling approach from reference [118] and the guessed signal source parameters
were compared to the measured data. Depending on the squared error between the
predicted and measured data, the signal source parameters were perturbed and the
process was repeated. This iterative process continued until the squared error between
the predicted and measured lamp sensor output were less than a certain threshold.
The signal source parameters from the last iteration were then taken as the actual
effective signal source parameters in the lamp sensor system.
The measured and fitted data in Figure 4-11 correspond to training runs for each
of the three lamp power settings. For each lamp power setting, we have different
effective signal source parameters. Those effective signal source parameters were
used to predict the lamp sensor response for different x-displacements. Figures 4-
12(a), 4-12(b), and 4-12(c) compare those predictions to measured lamp sensor data
at x-displacements of 22 cm and 45 cm for each of the three lamp power settings (dim,
medium, and bright). The results in Figure 4-12 show that the modeling approach
described in reference [118] yields predictive power for design-oriented estimation of
the lamp sensor output voltage in response to a target.
178
Lamp sensor output for Passing Spherical Conductor

z−Displacement = 1.02 m, x−displacement = 0 m
0.01
0.005
Lamp Sensor Output (V)
−0.005 Measured Dim

Fitted Dim
Measured Med
Fitted Med
−0.01
Measured Bright
Fitted Bright
−0.015
−1.5 −1 −0.5 0 0.5 1 1.5
Sphere Distance from center of lamp (m)
Figure 4-11: Training runs (source calibration) x = 0 cm
179
Predicted and Measured Lamp sensor Output

−3 z−Displacement = 1.02 m, Lamp Power = Dim
x 10
3

0
−1
−2
Predicted x = 22 cm
Measured x = 22 cm
−3 Predicted x = 45 cm
Measured x = 45 cm
−4
−1.5 −1 −0.5 0 0.5 1 1.5
(a) Dim
−3 z−Displacement = 1.02 m, Lamp Power = Med
x 10
8
4
−2
−4
−6
Predicted x = 22 cm
−8 Measured x = 22 cm
Predicted x = 45 cm
−10 Measured x = 45 cm
−12
−1.5 −1 −0.5 0 0.5 1 1.5
(b) Medium
z−Displacement = 1.02 m, Lamp Power = Bright
0.01
0.005
−0.005
Predicted x = 22 cm
−0.01 Measured x = 22 cm
Predicted x = 45 cm
Measured x = 45 cm
−0.015
−1.5 −1 −0.5 0 0.5 1 1.5
(c) Bright
Figure 4-12: LED lamp sensor measured and predicted responses.

180
4.3.1 Dark Occupancy Sensing
In this section, we address the ability to sense occupancy in the dark, which is relevant
to the use cases such as entry into a dark room. In this section, we demonstrate
excellent occupancy sensing at very low LED current levels. In fact, from the brightest
to essentially dark there is about a three order of magnitude difference in power level,
yet the electric field source for sensing drops by only a factor that is less than a half.
In Figure 4-8, a duty-cycled LED current also results in the lamp voltage also
pulsating. This voltage is proportional to the electric field that drives the lamp
sensor. From Chapter 3, the signal that is detected is an averaged magnitude that
is proportional to the duty cycle. This means that as the lamp is dimmed, the
sensor voltage output decreases proportionally, which can be observed in Figure 4-11.
Despite the decreased voltage levels, the output voltage is above the noise floor for a
wide range of dimming levels.
A special case arises in dark occupancy sensing, when one is no longer concerned
about maintaining a constant peak LED current, hence relaxing the consideration for
chromaticity. In this case, the LEDs are run at very low current levels at 50% duty
cycle. This is advantageous, because as we observe in Figure 4-13(b), the voltage drop
across one LED module changes roughly logarithmically with current. This means
that most of the voltage that drives the sensing is maintained at very small current
levels using the maximum available duty cycle, which results in the largest output
voltage signal when using the demodulation scheme discussed in Chapter 3.
181
0.07
0.06
0.05
Current (Amperes)
0.04
0.03
0.02
0.01
0
4 5 6 7 8 9 10 11 12
Voltage Drop (Volts)
(a)
12
11
10
Voltage Drop (Volts)
4
−7 −6 −5 −4 −3 −2 −1
10 10 10 10 10 10 10
Current (Amperes)
(b)
Figure 4-13: I-V curve of LED lamp module. (a) is the classic diode characteristic,
but closer inspection of the log plot in (b) reveals the non-idealities in real devices.
182
The result for sensing in the dark is compared to sensing at moderate lighting
levels in Figure 4-14. A careful comparison shows that there is actually an increase in
the output signal at low LED current levels. This may be attributed to a shift in the
electric field distribution from the LED lamps as we vary from low to high currents. At
low current levels, the shape of the electric field is dominated by parasitic capacitances
from the modules to the housing, as well as the capacitances associated with LEDs
at small bias. At higher current levels, the effective resistance of the LEDs decreases,
which results in a different type of distribution. The dynamics and geometry of this
process is complicated and is currently under investigation.
0.02
100 µA
10 mA
0.015
0.01
0.005
−0.005
−0.01
−0.015
−0.02
0 5 10 15 20
Time (s)
Figure 4-14: Comparison of capacitive sensor output at dark (100 µA) and lighted
(10 mA) LED current levels for an average height subject walking back and forth
along the axis of the lamps.
4.4 Conclusion
Reference [119] is one of many references that discusses curtailed demand and its
value in the energy market. In curtailed demand, the supply company reduces the
183
4.4. Conclusion
effective energy demand by reclaiming unused or wasted energy. Reference [119] cites
the sophisticated planning and knowledge of building characteristics necessary to im-
plement curtailed demand and suggests that it can only be effective if ”sensing and
switching can be done cheaply” and with ”a high level of automation.” In particular,
there is a great interest in controlling lighting to optimize energy consumption. Light-
ing in commercial and residential spaces consumes a significant portion of the end use
demand for delivered energy in the United States. In 2005, lighting consumed 0.73
Quadrillion Btu (QBtu) in the residential sector and 1.18 QBtu in the commercial
sector [120].
This work has presented a ballast or solid-state lamp driver that is suitable for
dimmable operation of solid-state or LED lighting. The ballast design permits the
possiblity for chromaticity control even at lower switching frequencies for the power
electronic current drive, which results in the ability to use hard switching as opposed
to resonant topologies, hence resulting in a relatively simple converter and control
scheme. The ballast described in this work also creates the correct lamp current
waveforms to permit a solid-state lamp to function effectively as a proximity sensor for
occupants, not just for motion as is typically deployed today. This opens the door to
distributed, autonomous control for lighting. That is, light fixtures can automatically
alter their illumination based on the presence or absence of occupants, and any other
important environmental variables such as time of day, through the actions of an
embedded controller. The proximity sensor does not require motion or other intrusive
occupant behavior to function. It is sensitive directly to the dielectric presence of an
occupant. Interfacing the lamp sensor with a dimming ballast creates a smart auto-
dimming lamp that can use the lamp sensor’s occupancy detections to appropriately
dim or brighten.
This work has also demonstrated an electro-quasistatic model that accurately

predicts the behavior of the proximity sensor for both fluorescent and solid state
lamps. The model can be used by building designers to predict detection range given
a particular configuration of luminaire. It can also be used to select a luminaire design
to achieve needed detection range.
184
The incorporation of automatic proximity detection in solid state lighting could be

a “game changing” addition to solid-state lamps that accelerates their acceptance.
185
4.4. Conclusion
186
Chapter 5
Standalone Capacitive Sensing

Occupancy Detectors
5.1 Introduction
This chapter explores capacitive sensing occupancy detectors that rely on their own
source of electric fields. The principal advantages of these “standalone occupancy de-
tectors” are that the signal source may be well controlled and optimized for sensing
and that the electrode and source configuration may be customized. The principle
drawbacks of the standalone occupancy detectors relative to retrofit systems like the
one in Chapter 3 are that the signal source and source coupling surfaces must be pro-
vided. The underlying motivation of this work is to provide a superior replacement to
PIR motion sensors like the one in Figure 5-1. The capacitive sensor would resemble
the PIR motion sensor in both form and function, but would provide true presence
detection. Recall from Chapter 3 that the ability of a PIR sensor to function as a pres-
ence detector is limited by low-frequency noise or drift from changes in background
infrared radiation (IR). The measured signals can be bandlimited (high-pass filtered),
but the sensor effectively becomes a motion sensor, not a presence sensor [69, 70].
The signal conditioning electronics from the fluorescent lamp sensor in Chapter 3
are reused in the standalone system. The analytical modeling of the fully-differential
front-end amplifier from Chapter 2 is directly relevant to the operation and modeling
187
5.2. System Configurations
Figure 5-1: The capacitive sensor would resemble the PIR motion sensor in both form
and function, but would provide true presence detection.
of the system in this Chapter.
5.2 System Configurations

Several permutations of electrode configurations are considered here. The electrodes
in the standalone sensor system include the measurement electrode(s) and the source
electrode(s). The measurement and source electrodes may be closely spaced or dis-
tantly spaced. Closely spaced electrodes are separated by lengths that are small
compared to the detection field length scales while distantly spaced electrodes are
separated by lengths that are comparable to the detection field length scales. Both
cases are explored in this chapter.
The signal source must have at least two coupling surfaces. These surfaces may
generally be explicit electrodes or they may be manifested as stray coupling to con-
ducting surfaces in the detection field. In this chapter, we consider systems having
at least one explicit source electrode while the other coupling surface may be another
explicit electrode or it may rely on stray coupling. The measurement must consist of
188
5. Standalone Capacitive Sensing Occupancy Detectors
at least one coupling surface that provides a return path to the signal source refer-
ence. Here we consider systems having at least one explicit measurement electrode.
Systems having two explicit measurement electrodes can achieve the natural carrier
suppression inherent to the fluorescent lamp sensor system. Systems having only
one measurement electrode generally require active carrier suppression to achieve the
same effect. This is discussed in Section 5.4.
The signal source can be generated by any periodic electric field source, for ex-
ample a signal generator with a sinusoidal output. Useful signal amplitudes range
from tens to hundreds of volts. Useful signal frequencies range from tens to hundreds
of kilohertz. The signal source may be earth referenced or not. If the signal source
is earth referenced, then stray coupling to earth serves as a return path for coupled
signals. In systems having only one explicit source electrode, stray coupling to earth
is the only return path. A notable feature of those systems is that footsteps may be
significantly detected in the sensor measurement as they may represent a substantial
change in the coupling from the occupant to the stray earth coupling in the floor.
189
5.2. System Configurations
(a) 2 meas., 2 source (b) 2 meas., 1 source
(c) 1 meas., 2 source (d) 1 meas., 1 source
Figure 5-2: Closely spaced electrode configurations
(a) 2 meas., 2 source (b) 1 meas., 2 source
(c) 2 meas., 1 source (d) 1 meas., 1 source
Figure 5-3: Distantly spaced electrode configurations
190
5.3 System Modeling

The capacitive modeling of the standalone system may be guided by the modeling
described for the fluorescent lamp sensor system in Chapter 3. In contrast to the
lamp sensor system, modeling the signal source in the standalone system is relatively
straightforward. The system may be modeled using the circuit model of the fully-
differential front-end amplifier developed in Chapter 2.
An example system model corresponding to a system having two measurement
electrodes is shown in Figure 5-4. The system model in Figure 5-4 represents systems
having one or two explicit source electrodes. If the triangular ground symbol in
Figure 5-4 is taken to be earth, then the model represents systems with an earth-
referenced signal source. In systems having two explicit measurement electrodes, it is
not necessary that the sensor electronics share the ground reference with the signal
source.
Capacitance model FD amplifier model
C1 C3 C5 Cshield +
1
2 Zd
+
HI +
e1 C7 C8 e2 Zc vo
vs1 1 −
2 Zd
LO C2 C4 C6 −
−
Cshield
Occupant
Figure 5-4: A simplified model of the two-electrode stand alone sensor using a FD
measurement
An example system model corresponding to a system having one measurement

electrode is shown in Figure 5-4. In systems having only one explicit measurement
electrode, it is particularly useful if the sensor electronics share the ground reference
with the signal source.
191
5.4. Active Carrier Suppression
5.4 Active Carrier Suppression

Some practical system configurations relevant to the standalone sensor comprise only
one measurement electrode. Here we describe a method for achieving active carrier
suppression in otherwise unbalanced capacitive systems using an artificial secondary
signal source and the multi-input structure of the fully-differential amplifier from
Chapters 2 and 3.
In Chapter 3 carrier suppression was a key operating principle that allowed for
detection of minute changes in the lumped capacitive network comprising the detec-
tion field. Without suitable suppression of the unneeded carrier content, there would
be an awkward design tradeoff between front-end gain (transimpedance) and output
dynamic range. Balanced multisource capacitive systems can achieve this carrier sup-
pression naturally. Systems having one measurement electrode may require an added
signal to actively suppress unwanted carrier content.
Capacitance model FD amplifier model
C1 C3 +
1
2 Zd
+
HI Cshield
Occupant C5 e1 Zc
+
vs1 1 −
vo
2 Zd
LO C2 C4 Cac −
−
vs2 Cshield
Carrier suppression
Figure 5-5: A simplified model of the single-electrode stand alone sensor with active
carrier suppression using a FD measurement
In single measurement electrode configurations, the unused input on the fully-

differential front-end amplifier provides a means for injecting an active carrier sup-
pression signal. Active carrier suppression may be achieved with the configuration
indicated for the system model in Figure 5-5. A discrete capacitor, Cac , is placed in
series with the unused input on the fully-differential front-end amplifier and a copy
of the signal source, vs2 . The amplitude of vs2 or the value of the capacitance, Cac ,
may be adjusted to null the output of the front-end amplifier in the absence of a de-
192
tection. The required adjustment depends on the physical configuration of the source
and measurement electrodes and may be implemented with a variable gain op-amp
connection.
5.5 Implementation
The implemented electronics for the stand alone sensor experimental setup are shown
in Figure 5-13. The electronics are based on the signal conditioning electronics used
in the fluorescent lamp sensor from Chapter 3.
In the stand alone sensor setup, the signal source, Vs , is assumed to be directly
available to the signal conditioning electronics. For practical embodiments in which
the source and measurement are distantly spaced, a signal source recovery circuit
may be needed. An example of a signal source recover circuit is a phase-locked-loop
(PLL).
Because the signal source is directly available in the experimental setup considered
here, the phase reference is coupled to the signal source with a discrete capacitor,
Cphase . Also, the active carrier suppression circuit shown in Figure 5-13 directly
accesses the signal source to generate the carrier suppression signal. The active carrier
suppression circuit takes a divided down copy of the signal source and applies a non-
inverting variable gain. The intent of the two-stage inverting op-amp connection
is to achieve a non-inverting gain that may be less than unity. The output of the
carrier suppression circuit is coupled to the unused input on the front-end amplifier,
when only one measurement electrode is used. The capacitive coupling simulates
the capacitive coupling effect of the first measurement electrode. Typical passive
component values are shown in Table 5.1.
5.6 Experimental Setup
An experimental setup was constructed to allow for investigation of all of the electrode
and source configurations described in Section 5.2. A photograph of the experimental
193
5.6. Experimental Setup
Table 5.1: Typical system parameters and passive components.
Parameter Value
Rf 1,2 10 MΩ
Cf 1,2 7.5 pF
Rf 3 200 kΩ
Cf 3 660 pF
Rlim 20 Ω
Rpu 500 Ω
Rlpf 10 kΩ
Clpf 150 pF
Cphase 20 pF
Cac 68 pF
Rac1 3 MΩ
Rac2 18 kΩ
Rac3 100 kΩ
Rac4 100 kΩ
Rac5 102 pot
fc 30 kHz
Vs 100 Vp−p
setup is shown in Figure 5-6. The experimental setup includes the signal conditioning
electronics from Figure 5-13, and movable electrodes like the ones in Figure A-1. The
signal source was generated with an HP 6827A bipolar amplifier and a Tektronix
CFG250 signal generator. Data was taken using the same Matlabr interface and
PIC operating system employed for the fluorescent lamp sensor. The relevant software
can be found in Appendix A.
Figure 5-7 shows a typical Matlabr plot window. The upper two windows show
the same detection signal in real time, but scaled differently in the vertical axis. The
interesting portion of this particular plot window is shown in the bottom plot, which
indicates a time history of what the software identified as a detection. This detection
corresponds to an occupant walking approximately 10 m through the detection field
for a system having one measurement electrode. From the discussion in Section 5.2,
this system relies on an earth return through ambient coupling, e.g. through the
floor. Therefore, footsteps should be captured in the detection as they constitute a
significant time-varying change in the capacitive coupling from the occupant to the
194
Figure 5-6: The stand alone sensor experimental setup with customizable electrode
configurations.
earth return.
An overhead view of the detection field and occupant path in this example is
shown in Figure 5-7(b). The drawing is not to scale, but approximate dimensions are
shown in meters. The measurement electrode was centered in the detection field. The
occupant passed by the measurement electrode. In the bottom plot in Figure 5-7(a),
the small perturbations superposed on the detection correspond to the footsteps of
the passing occupant. The amplitude of the footstep signal increases as the occupant
passes by the measurement electrode. In the upper plot, the real-time data detects
the occupant as he passes in front of the source to capture the data on the PC after
a three second pause. The dip in the real-time detection window also appears at the
end of the detection history in the bottom plot.
195
x
PC
(1.375 m, 2.75m)
Source Measurement
2.75 m
Path
Pause 3 sec.
Occupant
(0,0) 5m y
(a) Overhead view of detection field and occupant path
(b) Matlabr plot window showing footsteps
Figure 5-7: A typical Matlabr plot window and detection field experimental setup.
In this single measurement electrode configuration, footsteps are apparent in the
detection (bottom plot of (b)). Approximately 10 datapoints correspond to 1 sec.
196
5.7 Detection Patterns
Detection patterns can be found by plotting the sensor response to an occupant in

a grid of positions about the detection field. These plots can be used to evaluate
the characteristics of particular electrode and system configurations, e.g. sensitivity,
range, directionality. In all of the detection patterns, the absolute offset voltage may
be disregarded. Only the shape of the response about the offset is interesting for
this discussion because the degree to which the carrier suppression achieves zero volts
absolute offset is a practical matter and has no effect on the relative detection as long
as the sensor output does not saturate.
Figure 5-8 shows an overhead view of the experimental setup and detection pat-
tern for a distantly spaced electrode configuration. The detection pattern shows a
“tunnel” between the source and the measurement. When the occupant is behind
the measurement electrode, the detection pattern flattens. This detection pattern
demonstrates an interesting example of a directional electrode configuration.
Figure 5-9 shows the experimental setup and detection pattern for a closely spaced
electrode configuration. In this example there is one explicit source electrode and
one measurement electrode. Active carrier suppression was needed in this example
to achieve a nulling of the sensor output in the absence of a detection. The four
detection pattern plots in Figure 5-9 correspond to four different vertical spacings
between the source and measurement electrodes. From the data, the peak relative
detection decreases as the vertical spacing increases. However, the detection level at
increasingly further x and y positions increases as the vertical spacing increases. The
detection pattern effectively “squashes” outward as the vertical spacing increases.
This is a useful observation because it indicates that the detection range increases
for larger spacing between the measurement and source electrodes, an effect that we
intuitively expect.
Also evident in the detection patterns are two peaks about the source electrode
that appear in all four cases. Asymmetries between those two peaks are likely due to
measurement error. Those peaks indicate that the peak detection occurs when the
197
5.7. Detection Patterns
occupant is slightly to either side of the source electrode.

Figure 5-10 shows the experimental setup and detection pattern for a closely
spaced electrode configuration with two measurement electrodes and two source elec-
trodes (one high and one earth ground). The four detection pattern plots in Figure
5-9 correspond to four different vertical spacings between the source and measure-
ment electrodes. From the data, the peak relative detection generally decreases as the
vertical spacing increases. The ∆z = 5 cm case shows a slight increase in the peak
detection. Again, the detection pattern effectively “squashes” outward as the vertical
spacing increases. This is a useful observation because it indicates that the detection
range increases for larger spacing between the measurement and source electrodes, an
effect that we intuitively expect.
Also evident in the detection patterns are two oppositely facing peaks about the
two measurement electrodes that appear in all four cases. The differences between
the two peaks are likely due to differences in earth coupling on the two sides of the
electrode group. The sign reversal between the two peaks indicates directionality that
may be useful in practical applications.
198
PC x
earth
(1.375 m, 2.75m)
Source
LO HI Measurement
2.75 m
HP
6827A
Occupant
Tek
CFG250
(0,0) 5m y
(a) Overhead view of detection field
−3
x 10
−1
Sensor Ouput (V)
−2
−3
−4
−5
15
10 15
10
5
5
x−Position (ft.) 0 0
y−position (ft.)
(b) Detection pattern
Figure 5-8: 1 meas., 1 source, distantly spaced.
199
x
PC
(1.375 m, 2.75m)
earth 2.75 m
HI
LO HI
HP
6827A
Occupant
Tek
CFG250
(0,0) 5m y
0
0.2
0 −0.2
Sensor Ouput (V)
Sensor Ouput (V)
−0.2
−0.4
−0.4
−0.6
−0.6
−0.8
−1 −0.8
15
15
−1.2 10
12 −1 10
10 12
8 5 10 5
6 8 6
4 4
2 0 2 0
0 y−position (ft.) 0
x−Position (ft.) y−position (ft.)
x−Position (ft.)
(b) ∆z = 1 cm (c) ∆z = 5 cm
0
0
−0.1
−0.1
−0.2
Sensor Ouput (V)
−0.2
Sensor Ouput (V)
−0.3
−0.3
−0.4
−0.4
−0.5
−0.5
−0.6
−0.6
−0.7 15
15 −0.7 10
−0.8 12
12 10 10
10 8 8 5
6 5 6
4 4
2 0 0 2 0
0 y−position (ft.)
x−Position (ft.) y−position (ft.) x−Position (ft.)
(d) ∆z = 20 cm (e) ∆z = 27 cm
Figure 5-9: 1 meas., 1 source, closely spaced for various vertical spacings between
source and measurement.
200
x
PC 15 cm
(1.375 m, 2.75m)
earth 2.75 m
HI
LO HI
HP
6827A
Occupant
Tek
CFG250
(0,0) 5m y
0
0
−0.1 −0.1
−0.2 −0.2
Sensor Ouput (V)
Sensor Ouput (V)
−0.3 −0.3
−0.4
−0.4
−0.5
−0.5
−0.6
15 −0.6
−0.7 15
12 10 10
10 −0.7
8 12
6 5 10 5
4 8 6
2 0 4 2 0
0 0
x−Position (ft.) y−position (ft.) y−position (ft.)
x−Position (ft.)
(b) ∆z = 1 cm (c) ∆z = 5 cm
0 0
−0.05
−0.1
−0.1
Sensor Ouput (V)
Sensor Ouput (V)
−0.2 −0.15
−0.2
−0.3
−0.25
−0.3
−0.4
−0.35
15 15
−0.5 −0.4
12 10 10
10 12
8 10
6 5 8 5
4 6
2 4
0 2 0
0 0 y−position (ft.)
x−Position (ft.) y−position (ft.) x−Position (ft.)
(d) ∆z = 20 cm (e) ∆z = 27 cm
Figure 5-10: 2 meas., 1 source (high), closely spaced for various vertical spacings
between source and measurement.
201
x
PC
LO (1.375 m, 2.75m)
earth 2.75 m
15 cm
LO HI
HI
HP
6827A
Occupant
Tek
CFG250
(0,0) 5m y
0
0
−0.02
−0.05 −0.04
Sensor Ouput (V)
Sensor Ouput (V)
−0.06
−0.1
−0.08
−0.15 −0.1
−0.12
−0.2
15 −0.14
−0.25 15
10 −0.16
12 12 10
10 10
8 5 8
6 6 5
4 4
2 0 2 0
0 y−position (ft.) 0
x−Position (ft.) x−Position (ft.) y−position (ft.)
(b) ∆z = 1 cm (c) ∆z = 5 cm
0
0
−0.02
−0.05 −0.04
Sensor Ouput (V)
Sensor Ouput (V)
−0.06
−0.1
−0.08
−0.1
−0.15
15 −0.12
−0.2 10 15
12 −0.14 10
10 8 5 12
6 10 8 5
4 6 4
2 0 0 2 0 0
y−position (ft.) y−position (ft.)
x−Position (ft.) x−Position (ft.)
(d) ∆z = 20 cm (e) ∆z = 27 cm
Figure 5-11: 1 meas., 2 source (high and earth ground), closely spaced for various
vertical spacings between source and measurement. LO: earth ground.
202
x
PC 15 cm
LO (1.375 m, 2.75m)
earth 2.75 m
15 cm
LO HI
HI
HP
6827A
Occupant
Tek
CFG250
(0,0) 5m y
0
−0.1
−0.02
−0.2
−0.04
Sensor Ouput (V)
Sensor Ouput (V)
−0.06 −0.3
−0.08
−0.4
−0.1
−0.5
−0.12
−0.14 −0.6
15
−0.16 10
12 10 −0.7 15
8 5 12 10 10
6 4 8 6 5
2 4 2 0
0 0 0
y−position (ft.)
x−Position (ft.) x−Position (ft.) y−position (ft.)
(b) ∆z = 1 cm (c) ∆z = 5 cm
0.05
0
−0.05 0
−0.1
−0.05
Sensor Ouput (V)
Sensor Ouput (V)
−0.15
−0.2 −0.1
−0.25 −0.15
−0.3
−0.2
−0.35
−0.4 −0.25
−0.45 15
−0.3 15
12 10 10
10 8 12 10
6 4 5 8 6 5
2 0 4 2 0
0 0
x−Position (ft.) y−position (ft.) x−Position (ft.) y−position (ft.)
(d) ∆z = 20 cm (e) ∆z = 27 cm
Figure 5-12: 2 meas., 2 source, closely spaced for various vertical spacings between
source and measurement. LO: earth ground.
203
Measurement Electrodes Front-end Amplifier Multiplier Low-pass Filter Buffer A/D
Cf 2 +12 V
tronics
Rlim
5 V
LT1236
Rf 2 +5 V
+12 V φ1 φ2
−
− Rlpf
LTC2051
Vref
RG-174 +12 V +5 V
Electrode 2 AD8620
− +
+
2.5 V +
THS4140
−12 V Vocm LTC2440
+ +5 V −
+12 V To PIC
Electrode 1 −12 V
Clpf −
−
φ2 φ1 LTC2051
RG-174 AD8620
+
Config. Select + Rf 1
Rlpf
−12 V
Analog Sw/s: ADG411
Rlim
Cf 1
Rac4
Rac1
Vs Rac3 +12 V Rac5
−
Rac2 LM358
Active Carrier Suppression
+ +12 V
−
−12 V
LM358
+ Cac
−12 V
Cf 3
+5 V
+12 V
Rf 3 Rpu φ2
−
RG-174 AD790
+12 V
− +
−12 V +5 V
Phase Reference
AD8620
Cphase
+
+12 V
Rpu φ1
−12 V −
AD790
+
204
Chapter 6
Analysis and Modeling of

Feedback-regulated
Multi-converter, Multi-source
Power Systems
6.1 Introduction
This chapter presents linearized modeling and analysis of multi-converter, multi-

source power systems for fuel cell power processing applications. Specifically, the
multi-converter system is intended to achieve current buffering of the fuel cell from
variations in the load. Additionally, the multi-converter system is designed for in-
tegral diagnostics using impedance spectroscopy. The excitation for the impedance
spectroscopy signal is generated with a small-signal control signal superposed on the
control input of one of the converters in the multi-converter system. The small-signal
response of the entire multi-converter system is designed to minimize the effect of the
impedance spectroscopy on the load voltage and current. That is, the excitation cur-
rent for impedance spectroscopy effectively flows from the secondary source, typically
a battery in the design examples, and not from the load.
205
6.1. Introduction
The analysis of multi-converter systems has been the subject of many previous
investigations. Much of the previous work on multi-converter or “hybrid” power
systems focuses on system level analyses [121–127]. These analyses treat the convert-
ers as simplified elements having ideal voltage or current outputs and perhaps some
characteristic, usually the negative incremental input impedance effect of a feedback
regulated converter [122, 125]. Conclusions are often drawn from simulation rather
than analysis [126, 128].
Previous work on paralleled converter systems has investigated actual converter

dynamics and interactions leading to design-oriented conclusions. The analyses of
paralleled converter systems has been focused on systems having a single input source
[129–133]. Many of those analyses are focused on a particular control scheme [131–
133]. The treatment of multiple input filters in a multi-converter system presented in
this thesis was not found in the literature.
The work in [129] is closest to the developments in this thesis - the main difference
being that [129] focuses on multi-converter systems having a single input source.
References [130] and [131] focus on stability analysis through the examination of loop
gains in a master-slave current sharing system. Reference [132] focuses on paralleled
buck converters operating under average current share control and reference [133]
focuses on paralleled voltage regulator modules for microprocessor power. Reference
[134] derives a modeling approach that is distinct because it reduces the paralleled
converter system to two subsystems - one differential mode and the other common
mode. Much of the single converter systems review in this thesis is based on reference
[14].
A key feature of any of these analyses is the version of the linearized converter
model used in the analysis. Naturally, all of these linearized models can be shown to
be equivalent in as much as they are similarly complete. Reference [129] employs the
converter model developed by Vorperian in [135]. References [130, 133, 134] employ a
Thevenin equivalent converter model and reference [136] employs the model developed
by Middlebrook. Reference [137] does not directly reference any linearized circuit
model and instead derives the linearized converter transfer functions directly from
206
6. Analysis and Modeling of Feedback-regulated Multi-converter, Multi-source
Power Systems
the nonlinear converter topology of interest. Notably, reference [137] analyzes multi-
converter systems with a single input source but discusses a method for extending the
analysis to systems having different input voltages. Other references [131, 132, 138]
employ linearized circuit models developed somewhat independently and always, in
some sense, based on linear superposition principles.
A key stylistic feature of the analyses is the use of matrix formulations, block
diagram representations, linear superposition arguments, or a mix. Again, all of
these approaches can be argued as equivalent. References [129,131,138] employ linear
superposition in the context of block diagram representations only. Reference [130]
mixes linear superposition, block diagram representations and matrix formulations
while [137] employs matrix formulations and block diagram representations only.
207
6.1. Introduction
Vg +
−
C R
Step 0: Linearization, Derivation of Model Parameters

ed̂ Le
+
−
v̂g +
− jd̂ Ce R
1 : M (D)
Step 1: Derivation of Converter Transfer Functions
in1 out1
G11 (s)
Gmn (s)
inm outn
switching stage
Step 2: Construction of Feedback Control System
Gzz
Gyy
+ -
Σ Gc Fm Gxx Σ
+ +
-
switching stage
Step 3: Evaluation of C-L and O-L Transfer Functions

||
Step 4: Add Input Filter(s), Compute (N)EET Correction Factors
in1 out1
G11 CF11
Gmn CFmn
inm outn
switching stage
Figure 6-1: The analysis in this chapter focuses on steps 1-4. The approach is reviewed
for single converter systems, then extended to multi-converter systems.
208
Power Systems
The analyses presented in this thesis were developed for a particular set of appli-
cations requiring specific large and small signal functionality with multiple distinct
sources. More than one application and set of requirements is considered so some ef-
fort was made to generalize the modeling effort so that it can be applied to arbitrary
feedback control approaches.
The linearized circuit model employed here is that developed by Middlebrook

in [12, 139, 140]. The model is written in terms of three model parameters that may
be related to any converter topology. A benefit of the model is that it includes input
current perturbations. This has particular implications for the small-signal input
current functionality needed in the design of the systems presented here. It also
makes the multi-converter model directly useful for studying the effects of multiple
input filters in Chapter 7.
The stylistic features of the analyses here are defined by a separation of the an-
alytical process into distinct steps and the use of linear superposition in the context
of block diagram representations. A schematic illustration of the analytical method
followed in this thesis is shown in Figure 6-1. Step 0 is not directly addressed in
this thesis, the results of which are essentially a tabulation of model parameters that
may be inserted into the the linearized model. While the computation of the model
parameters (Step 0) is not directly addressed here, the nature of those model pa-
rameters is discussed on a fundamental level. This understanding leads to a method
presented in Section 6.4 for generalizing previously derived model parameters. The
benefit of this generalization method is that those model parameters may be used to
relate the linearized models of multi-converter systems developed in this thesis to ac-
tual converter topologies, e.g. buck, boost, or buck-boost. Steps 1-3 in Figure 6-1 are
the topic of the current chapter. Step 4 represents a sufficiently distinct development
that it is treated separately in Chapter 7.
In this chapter (steps 1-3 from Figure 6-1), converter transfer functions are derived
from the linearized model. The converter transfer functions may be used to represent
the behavior of the converter when it is inserted into a feedback regulation system.
Closed-loop transfer functions (regulator transfer functions) and open-loop transfer
209
6.1. Introduction
functions are considered separately. The analyses of two example feedback regulation
systems are presented. Before applying this method to multi-converter power systems,
we first review the analogous method for single converter systems.
6.1.1 Context - Fuel Cell Power Processing
This investigation was motivated by the application of multi-converter power systems

to multi-source systems comprising a fuel cell and a second source. There is an
increasing realization that the commercial viability of fuel cells depends on work to
enhance reliability and durability [141, 142]. These limitations can be mitigated by
furnishing the fuel cell with a fixed power operating point within the rated power
of the device. However, many practical applications demand widely varying power.
Incorporating the fuel cell into a multi-source power system adds enough degrees
of freedom for fixed operating point fuel cell operation while the secondary source
accommodates the variability in the load.
In practice, operating the fuel cell at a fixed and safe operating point may not
completely mitigate degradation effects. Therefore, there is some interest in monitor-
ing degradation phenomena during runtime, when fuel cells are integrated into real
systems. As an example, in [143], Ramschak et. al. provide a method to detect the
failure of a single cell within a stack by analyzing the harmonic distortion on the stack
voltage. Similarly, in [144] Gemmen et. al. study the impact of inverter load dynam-
ics on a fuel cell, with the conclusion that stack / inverter interaction is significant in
the operating conditions and long term behavior of the stack. In references [145,146],
Ren et. al. examine the interactions between solid-oxide fuel cells and grid interface.
Fuel cell diagnostics may be achieved through impedance spectroscopy, commonly
known as electrochemical impedance spectroscopy (EIS) when applied to an electro-
chemical device [142, 147–150]. Integral diagnostics may be achieved by integrating
EIS functionality into the controls of the power system. In a single converter system,
integral diagnostics functionality can lead to unwanted effects, for instance the EIS
measurement may yield prohibitive or at least unwanted disturbance of the load volt-
age and / or current. The added degrees of freedom needed to reduce or eliminate
210
Power Systems
these unwanted effects can also be exploited with a multi-converter power system.
In Chapters 8 and 9, we present two design examples. In the first example the inte-
gral diagnostics functionality for a fuel cell is demonstrated in a stationary application.
Buffering of the fuel cell current from load current variability is not demonstrated in
this first example because the power system feeds directly to the grid and the load
power is relatively fixed. The needed functionality in this first example is achieved
with a dual voltage regulated power system using off-the-shelf power converters.
In the second example, the power system is intended to power an electric un-
manned aerial vehicle (UAV). The load in this second example is by its nature highly
variable. Both integral diagnostics and buffering of the fuel cell current from the
load current variability are demonstrated. The needed functionality in this second
example is achieved with a master-slave current-voltage regulated power system.
6.2 Single Converter Systems Review
This chapter analyzes the small-signal behavior of multi-converter, multi-source power

systems starting from Middlebrook’s linearized canonical models of CCM-operated
power converters [12]. A parallel development could be carried out if the converters
operate in DCM by using the corresponding models for DCM-operated converters
[140].
The analytical methods are first reviewed in the context of single converter sys-
tems. The single converter review begins with a review of Middlebrook’s linearized
converter model in Section 6.2.1. Some notable converter transfer functions are de-
rived in Section 6.2.2. Finally, an example single-converter closed-loop power system
is analyzed in Section 6.3.
The multi-converter developments mirror the single converter review. The gen-
eralizations necessary to build a linearized model of a multi-converter power system
from Middlebrook’s canonical circuit models are discussed in Section 6.4. A general
linearized model of a multi-converter, multi-source power system based on Middle-
brook’s linearized converter model is presented in Section 6.5. Some particularly
211
6.2. Single Converter Systems Review
useful converter transfer functions are derived from that model. Finally, example
closed-loop power systems are analyzed in Sections 6.6 and 6.7.
6.2.1 Middlebrook’s Linearized Canonical Converter Model
In reference [12], Middlebrook develops linearized circuit models that can be used to
represent the input, output and control properties of many switching power convert-
ers. The goal of that circuit modeling is well-understood in analogy to the small-signal
modeling of the bipolar transistor [12]. While the nonlinear relations describing the
terminal voltages and currents of the transistor are inconvenient to use when the
device is embedded in an otherwise linear system, one approach is to establish a
linear small-signal model that represents the AC properties of the transistor about
a specified DC (large-signal) operating point [12]. Then, the linearized model is in-
corporated into the overall linear system. The objective of Middlebrook’s canonical
circuit models for power converters is the same. Those models represent the linearized
small-signal properties of the converter about a given DC operating point [12].
212
Power Systems
+
L
+ C
Vg − V R
-
Switching-mode Converter
D
Duty Ratio
(a) Basic Elements of a switching-mode regulator. The LC input filter and buck converter
are shown as typical realizations [13].
Control Basic DC Low-pass
function conversion filter
ˆ
e(s)d(s) 1 : M (D)
+
−
+
Le
+ îload (s)
− Ce v̂(s)
v̂g (s) ˆ
j(s)d(s) R
-
Canonical Converter Model
λ
ˆ
d(s)
(b) A small-signal regulator model using Middlebrook’s linearized canonical circuit model of the
power converter [13]. Hats (ˆ) denote small-signal quantities.
Figure 6-2: Canonical circuit modeling developed in references [12, 13] and [14].
213
Middlebrook demonstrates how CCM-operated converters can be manipulated

into one fixed topology and DCM-operated converters into another fixed topology in
references [12, 139, 140]. For example, the basic elements of a typical power converter
are shown in Figure 6-2(a). In Figure 6-2(b), the buck converter has been replaced
1
with the linearized canonical circuit model developed by Middlebrook in [12].
The canonical circuit model consists of three pieces (in boxes): an ideal trans-
former that represents the converter’s ideal voltage and current transformation2 , an
effective low-pass filter at the output that includes the effects of the energy storage
elements involved in the switching action of the converter, and dependent current and
ˆ Reducing every con-
voltage sources that capture the effect of the control signal, d.
verter to this “canonical topology” means that a linearized input-output and control
description of any converter reduces to looking up the, perhaps frequency-dependent
values for each of the model parameters as in Table 6.1 [12, 14].
Table 6.1: Canonical Model Parameters for CCM-operated Buck, Boost and Buck-
Boost converters with a fixed load R [14]
Converter M(D) Le e(s) j(s)
V V
Buck D L D2 R
1 L sL
V
Boost D′ D ′2
V 1− D ′2 R D ′2 R

Buck-Boost − DD′ L
D ′2
− DV2 1 − sDL
D ′2 R
− DV′2 R
6.2.2 Converter Transfer Functions
The converter transfer functions describe the linearized dynamical behavior of the
converter about a fixed operating point. Their derivation is a necessary starting
point for any analysis of a closed-loop regulator.
The mathematical results of the converter transfer function derivations can be
1
The hats (ˆ) denote small-signal quantities.
2
the straight line and the wavy line drawn on the transformer element in Figure 6-2(b) are
intended to indicate DC and AC respectively.
214
Power Systems
summarized in a block diagram representation. For example, Figure 6-3 describes

how three converter transfer function superpose in a summing element to capture
the effects of three respective input signals on the converter output voltage. The
converter output voltage is only an example and any signal can be represented as an
output.
îload (s)
v̂g (s) Ze (s)

Gvg (s)
ˆ
d(s)
+ - v̂(s)
Gvd (s) Σ
+
Converter switching stage
Figure 6-3: The converter switching section can be represented by an input output
dynamical block diagram consisting of the relevant converter transfer functions.
In Figure 6-3, the superposition of the converter transfer function outputs on the
final output signal reflects the manner in which the converter transfer functions are
derived. Each converter transfer function in the example of Figure 6-3 can be derived
from a circuit model of the converter in a linear superposition sense. Specifically,
having defined the input signal pertaining to each converter transfer function, the
other independent input signals are deactivated. Mathematically, the three notable
converter transfer functions in Figure 6-3 may be defined as follows:

v̂(s)
Gvd (s) ≡ (6.1)
ˆ v̂g =0
d(s)
îload =0

v̂(s)
Gvg (s) ≡ (6.2)
v̂g (s) d=0ˆ
îload =0

v̂(s)
Ze (s) ≡ . (6.3)
îload (s) d=0 ˆ
v̂g =0
Deriving the converter transfer functions from Middlebrook’s canonical linearized

converter model leads to generalized results. The behavior of any particular topology
215
can be represented by inserting canonical model parameters like the ones in Table
6.1 into the results. These generalized derivations are relatively straightforward. For
instance, from Figure 6-2(b), the following converter transfer functions can be written
down by inspection:
Gvd (s) = eMλ (6.4)
Gvg (s) = Mλ (6.5)
Ze (s) = ZL ||Zle , (6.6)
where we have defined
ZL
λ≡ (6.7)
ZL + Zle
ZL ≡ R||Zce (6.8)
1
Zce ≡ . (6.9)
sCe
The choice of converter transfer functions to derive depends partly on the intended
feedback system. For instance, in a PWM-controlled converter, the feedback system
will control the converter via the duty cycle input. In a voltage-regulated converter,
the feedback system will regulate the converter’s output voltage. The converter trans-
fer function from duty ratio to output voltage, e.g. Gvd , would ultimately be needed
to form the final representation of the closed-loop regulator. On the other hand, if
the feedback system regulates the converter output current by way of the duty cycle,
the converter transfer function from duty cycle to output current would be critical.
For a feedback system that controls the converter based on both output voltage and
current, both transfer functions would be needed.
The converter transfer functions described above are critical because they are ulti-
mately “in the loop.” There is also generally a need to capture the effect of converter
input signals that will not be in the loop. For instance, we are often interested in
the “audio susceptibility” (the effect of the input voltage, v̂g , on the regulator) or
the closed-loop output impedance (the effect of load current perturbations, îload , on
216
Power Systems
the regulator). The converter transfer functions needed to ultimately capture these
effects on the closed-loop system are Gvg and Ze in this example.
6.3 Regulator Example: Voltage Regulated Power

System
Figure 6-4(a) shows a linearized model of a voltage regulated converter and Figure
6-4(b) shows a block diagram represenation of the same system. The dashed box
depicts in Figure 6-4(b) the converter transfer functions defined in equations (6.1)-
(6.3). From Figure 6-4(b), it is explicitly clear that the duty ratio input is “in the
loop” and the other two converter inputs are not.
Regulator transfer functions, both closed-loop and open-loop may be taken di-
rectly from the block diagram. For instance, the closed-loop transfer function from
the reference voltage, v̂ref , to the output voltage, v̂, in Figure 6-4(b) is

v̂(s) 1 T (s)
= (6.10)
v̂ref (s) v̂g =0 H(s) 1 + T (s)
îload =0
in which the loop transfer function is
T (s) = Gc (s)Fm Gvd (s)H(s). (6.11)
This classic result shows that the closed response of the regulator output voltage to
1
changes in the control voltage approaches H(s)
when the loop gain, T (s), is large
compared to unity. While the other two converter transfer functions do not directly
affect the loop-transfer function, they do impact the closed-loop transfer functions.
For instance, the closed-loop transfer function from input voltage and load current to
output voltage can be written as follows:

v̂(s) 1
= Gvg (s) (6.12)
v̂g (s) v̂ref =0
1 + T (s)
îload =0
217
6.3. Regulator Example: Voltage Regulated Power System
îin
Fuel Cell Zf c (s) e(s)dˆ1 1 : M (D) îo
+
−
+
Le î
v̂f c
+
− j(s)dˆ1 Ce v̂(s) R
-
d̂(s) H(s)
+
v̂ref (s)
FM Gc (s) Σ
-
(a) A linear model of a voltage regulated single converter system

îload (s)
v̂g (s) Ze (s)

Gvg (s)
v̂e (s) v̂c (s) ˆ

d(s)
v̂ref (s) + − v̂(s)
Σ Gc (s) Fm Gvd (s) Σ
+
+
−
Compensator Pulse-width
modulator Converter switching stage
H(s)
Sensor gain
(b) A block diagram representation of a voltage regulated single converter system
Figure 6-4: A linearized converter model inserted into a voltage-mode feedback control
loop [14].
and
v̂(s) 1
= Ze (s) . (6.13)

îload (s) v̂ref =0 1 + T (s)
v̂g =0
These results describe the closed-loop rejection of disturbances. Both of these con-
verter transfer functions from extra input signals appear attenuated by the factor
(1 + T (s)). When the loop gain, T (s), is large, the regulator response to variations
in input voltage and output current will be reduced accordingly.
218
Power Systems
6.4 Canonical Model Generalizations
A linearized multi-converter, multi-source model will be developed based on the lin-

earized canonical circuit models detailed above. This development will rely on suf-
ficient generalization of the canonical circuit model so that it may be extended to
multi-converter power systems.
To draw attention to the particular type of generalization needed for the hybrid
power system analysis, the model parameters in Table 6.1, e(s) and j(s), contain
instances of the load resistance, R. Some information is lost when deriving the model
parameters for the single converter-resistive load case because the quantity R may
appear in the results to represent two very different things: the impedance shunting
the load – a small-signal quantity, or the ratio of the DC load current and voltage –
a large signal quantity. In generalizing the model parameters, it is initially unclear
whether to replace any instance of R, with the quantity V /I. However, it is possible
to determine an appropriate generalization based on a fundamental understanding of
the linearized models.
Because the model parameters, e(s) and j(s), are factors in the linearized canonical
ˆ they, by definition, cannot also include
model that multiply the control signal, d,
ˆ would be nonlinear and so would the
other small-signal factors (for instance, e(s)d(s)
resulting circuit model). In other words, e(s) and j(s) are terms that represent and
depend on the DC (large-signal) operating point of the converter. They only depend
on the load in that they may depend on the DC output current I and/or voltage
V . This realization of the canonical circuit model is particularly useful for modeling
multi-converter power systems, because the model parameters depend only internal
converter characteristics and on the DC operating points of the output current and
voltage.
To demonstrate this point, the previously derived canonical model parameters

from Table 6.1 can be generalized from the single converter-resistive load case to the
general case by replacing all factors of R in e(s) and j(s) with the ratio of DC output
voltage and current, V /I. The results, shown in Table 6.2, are valid for CCM-operated
219
6.5. Multi-converter Systems
Table 6.2: Canonical Model Parameters for the Buck, Boost and Buck-Boost with a
generalized load
Converter M(D) Le e(s) j(s)
V
Buck D L D2
I
1 L sLI
I
Boost D′ D ′2
V 1− D ′2 V D ′2

Buck-Boost − DD′ L
D ′2
− DV2 1 − sDLI
D ′2 V
− DI′2
converters driving a generalized load. Having developed this “intellectual shortcut”

the results of hybrid power system analysis based on the canonical circuit model are
more useful because previously-derived model parameters can be easily extended.
6.5 Multi-converter Systems

The methods for analyzing closed-loop feedback converters are now extended to multi-
converter systems. The analysis starts with a presentation of the linearized circuit
model and then follows with derivations of converter transfer functions. Two regula-
tor examples are presented to demonstrate the manner in which the converter transfer
functions may be used to arrive at closed-loop and open-loop regulator transfer func-
tions.
6.5.1 Linearized Multi-converter Model
The linearized multi-converter model used for the analysis of converter transfer func-
tions is shown in Figure 6-5. It is conceptually important that the analyses treat this
model as a single circuit without any explicit division between the two converters.
When converter transfer functions are derived directly from the circuit in Figure 6-5,
the second converter loads the first and vice versa. The independent inputs shown
include the two duty ratios, dˆ1 and dˆ2 , the two input voltage perturbations, v̂f c and
v̂batt , and the load current perturbation, îload . The output signals labeled are the
input currents, îin1 and îin2 , the converter output currents, îo1 and îo2 , and the load
220
Power Systems
îin1
Fuel Cell Zf c (s) e1 (s)d̂1 1 : M1 (D1 ) îo1
+
−
Le1
v̂f c
+
− j1 (s)d̂1 Ce1
d̂1 (s)
îin2
Battery Zbatt (s) e2 (s)d̂2 1 : M2 (D2 ) îo2

+
−
+
Le2
v̂batt îload
+ î
− j2 (s)d̂2 Ce2 v̂(s)
-
d̂2 (s)
Figure 6-5: The linearized multi-converter model. The battery and fuel cell source
are examples of sources in a multi-source power system.
current and voltage, v̂, î.
The source output impedances will be assumed zero-valued for now. The effect of
finite source impedance can be examined in an identical fashion to the effect of input
filters. Those developments will be detailed in Chapter 7.
6.5.2 Converter Transfer Functions
The converter transfer functions can be derived from the circuit in Figure 6-5. In
our examples of closed-loop regulators, the feedback control will always control the
converter using pulse-width modulation. The converter transfer functions having one
of the duty ratios as an input will therefore be in the loop. Each of the key output
variables can be written as a linear superposition of the output signals from the
221
îload
îo1
îload
dˆ1 îo1
dˆ1 + + îo1
Σ
+
îo1
dˆ2
v̂
îload
v̂
ˆ
d1 +
+ v̂
Σ
dˆ2 +
v̂
ˆ
d2
Figure 6-6: The multi-converter switching section can be represented by an input out-
put dynamical block diagram consisting of the relevant converter transfer functions.
converter transfer functions for each of the two duty ratios as follows:

ˆ ˆ v̂ ˆ v̂
v̂(d1 , d2 ) = d1 + dˆ2 (6.14)
ˆ
d1 dˆ2 =0 ˆ
d2 dˆ1 =0

î î
ˆ ˆ
î(d1 , d2 ) =
ˆ
d1 +

dˆ2 (6.15)
dˆ1 dˆ =0 dˆ2 dˆ =0
2 1
îo1 îo1
îo1 (dˆ1 , dˆ2 ) = dˆ1 + dˆ2 (6.16)
ˆ
d1 dˆ =0
ˆ
d2 dˆ =0

2 1
îo2 îo2
ˆ ˆ
îo2 (d1 , d2 ) = ˆ
d1 + dˆ2 . (6.17)
dˆ1 ˆ
d2 =0
dˆ2 ˆ
d1 =0
222
Power Systems
In addition to the converter transfer functions having duty ratios as inputs, it is

possible to derive the converter transfer functions having any other independent signal
as an input. For instance, we may deactivate both duty ratios and activate îload in
Figure 6-5. In that case, we can find some interesting converter transfer functions,
e.g. from the load current to the load voltage or from the load current to the first
converter’s output current. The corresponding superposition expressions above are
expanded as follows:

ˆ ˆ v̂ ˆ v̂ ˆ v̂
v̂(d1 , d2 , îload ) = d1 + d2 + îload (6.18)
dˆ1 dˆ2 =0 dˆ2 dˆ1 =0 îload dˆ1 =dˆ2 =0

îo1
îo1 îo1
ˆ ˆ
îo1 (d1 , d2 , îload ) = ˆ
d1 + ˆ
d2 + îload . (6.19)
dˆ1 ˆ
d2 =0
dˆ2 ˆd1 =0
îload ˆ ˆ
d1 =d2 =0
The two additional converter transfer functions having îload as the input will also
be derived here. A block diagram representation of the superposition expressions
above is shown in Figure 6-6. This block diagram represents the dynamical behavior
of the multi-converter system. It is analogous to the block diagram in Figure 6-3
for single converter systems. This section is focused deriving the converter transfer
functions in the blocks of Figure 6-6. The blocks each correspond to a rational term in
the superposition expressions above. Note that this representation only captures the
effects of select inputs on select outputs that will be important later in our examples.
Neither this representation, nor any representation captures all transfer functions
from all inputs to all outputs.
Here we define the following quantities. The impedance ZL is all of the impedance
that shunts the output node, ZL ≡ R||Zce1||Zce2 and the effective converter output
impedances are Ze1 ≡ Zle1 ||Zce1 and Ze2 ≡ Zle2 ||Zce2, where Zce1,2 ≡ 1/sCe1,2 and
Zle1,2 ≡ sLe1,2 .
From Figure 6-5, the two terms comprising the load voltage can be written down
223
by inspection:

v̂ ZL ||Zle2
= e1 M1 (6.20)
ˆ
d1 dˆ2 =0 Zle1 + ZL ||Zle2

v̂ ZL ||Zle1
= e2 M2 . (6.21)
dˆ2 dˆ =0 Zle2 + ZL ||Zle1

1
These two terms are the converter transfer functions from the duty ratios to load
voltage. The expression for the load current follows directly from that for the load
voltage, i.e. î = v̂/R.
Having found the converter transfer functions from duty ratio to load voltage, we
can used them to expedite the analyses of the converter output currents as follows.
From Figure 6-5, the two terms comprising the first converter’s output current are
!
îo1 v̂ 1 v̂ 1
= e1 M1 − −
dˆ1 dˆ2 =0
dˆ1 dˆ2 =0 Zle1 dˆ1 dˆ2 =0 Zce1

e1 M1 v̂ 1
= − (6.22)
Zle1 dˆ1 dˆ2 =0 Ze1
!
îo1 v̂ 1
= − (6.23)
dˆ2 dˆ1 =0
dˆ2 dˆ1 =0 Ze1
Substituting the expressions for output voltage,

îo1 1 1 ZL ||Zle2
= − e1 M1 (6.24)
dˆ1 dˆ =0 Zle1 Ze1 Zle1 + ZL ||Zle2
2
îo1 ZL ||Zle1 e2 M2
=− (6.25)
dˆ2 dˆ =0 Zle2 + ZL ||Zle1 Ze1
1
The result for the second converter’s output current can be found, using symmetry
arguments, from the first without too much trouble:

îo2 ZL ||Zle1 e1 M1
=− (6.26)
dˆ1 dˆ =0 Zle2 + ZL ||Zle1 Ze2
2
îo2 1 1 ZL ||Zle2
= − e2 M2 . (6.27)
dˆ2 ˆd1 =0
Zle2 Ze2 Zle1 + ZL ||Zle2
224
Power Systems
Having derived the converter transfer functions with duty ratios as inputs, we
now derive the converter transfer functions having the load current perturbation as
an input. From Figure 6-5, we have the two constraints:

v̂ Ze2
îo1 = îload + (6.28)
R Ze1 + Ze2
v̂ = −îo1 Ze1. (6.29)
Combining these two constraints,

!
îo1 Ze1 Ze2
îo1 = îload − (6.30)
R Ze1 + Ze2
simplifying and collecting terms,
e2 Z
îo1 Ze1 +Ze2
= (6.31)
îload 1 + ZRe1 Ze1Z+Z
e2
e2
Ze2
= . (6.32)
Ze1 + Ze2 + Ze1RZe2
îo1
Combining the result for îload
above with the second constraint leads to
v̂ îo1
=− Ze1 (6.33)
îload îload
Ze1 Ze2
=− . (6.34)
Ze1 + Ze2 + Ze1RZe2
It is convenient to define the following quantities:
ZL ||Zle2
λ1 ≡ (6.35)
Zle1 + ZL ||Zle2
ZL ||Zle1
λ2 ≡ . (6.36)
Zle2 + ZL ||Zle1
These factors may be viewed as the impedance divider ratio from the open circuit
converter output voltage to the load voltage for the first and second converter’s re-
spectively.
225
The converter transfer functions are summarized here

v̂
= e1 M1 λ1 (6.37)
dˆ1 dˆ2 =0

v̂
= e2 M2 λ2 (6.38)
dˆ2 dˆ1 =0

î 1
= e1 M1 λ1 (6.39)
dˆ1 dˆ =0 R
2
î 1
= e2 M2 λ2 (6.40)
dˆ2 dˆ =0 R
1
îo1 1 1
= − λ1 e1 M1 (6.41)
dˆ1 dˆ =0 Zle1 Ze1
2
îo1 e2 M2
= −λ2 (6.42)
dˆ2 dˆ =0 Ze1
1
îo2 e1 M1
= −λ1 (6.43)
dˆ1 dˆ =0 Ze2
2
îo2 1 1
= − λ2 e2 M2 (6.44)
dˆ2 dˆ =0 Zle2 Ze2
1

v̂ Ze1 Ze2
=− (6.45)
îload dˆ1 =dˆ2 =0 Ze1 + Ze2 + Ze1RZe2

îo1 Ze2
= Ze1 Ze2
(6.46)
îload ˆ ˆ Ze1 + Ze2 + R
d1 =d2 =0
Several linear combinations and transformations of the converter transfer functions

above will be useful for computing closed-loop transfer functions. For instance, the
load voltage:
v̂(dˆ1 , dˆ2 ) = M1 λ1 e1 dˆ1 + M2 λ2 e2 dˆ2 ; (6.47)
the load current:

1
î(dˆ1 , dˆ2 ) = M1 λ1 e1 dˆ1 + M2 λ2 e2 dˆ2 ; (6.48)
R
the first converter’s output current:

1 1 e2 dˆ2
îo1 (dˆ1 , dˆ2 ) = M1 − λ1 e1 dˆ1 − M2 λ2 ; (6.49)
Zle1 Ze1 Ze1
226
Power Systems
the second converter’s output current:

1 1 e1 dˆ1
îo2 (dˆ1 , dˆ2 ) = M2 − λ2 e2 dˆ2 − M1 λ1 . (6.50)
Zle2 Ze2 Ze2
Also, the first converter input current can be found using KCL in Figure 6-5:
!
v̂(dˆ1 , dˆ2)
îin1 (dˆ1 , dˆ2 ) = j1 dˆ1 + M1 îo1 (dˆ1 , dˆ2 ) + . (6.51)
Zce1
Finally, the results in (6.47)-(6.51) may be simplified in the case that the two convert-
ers are sufficiently identical, i.e. M1 = M2 = M, Zle1 = Zle2 = Zle , Ze1 = Ze2 = Ze ,
λ1 = λ2 = λ:

ˆ ˆ ˆ
v̂(d1 , d2) = Mλ e1 d1 + e2 d2 ˆ (6.52)
Mλ ˆ
î(dˆ1 , dˆ2) = e1 d1 + e2 dˆ2 (6.53)
R !
e ˆ
d
1 1 1
îo1 (dˆ1 , dˆ2) = M − λ e1 dˆ1 + e2 dˆ2 (6.54)
Zle Ze
!
e ˆ
d
2 2 1
îo2 (dˆ1 , dˆ2) = M − λ e2 dˆ2 + e1 dˆ1 (6.55)
Zle Ze
!
e 1
ˆ1 1
d 1

îin1 (dˆ1 , dˆ2) = j1 dˆ1 + M 2 + − λ e1 dˆ1 + e2 dˆ2 . (6.56)
Zle Zce Ze
6.6 Regulator Example 1: Dual Voltage-mode Reg-

ulated Power System
The linearized circuit in Figure 6-7 is a linearized model of a multi-converter power
system with two power converters under voltage-mode feedback control. It includes
the general linearized multi-converter model from Figure 6-5 as well as linearized
blocks comprising the basic components required for feedback control.
Figure 6-8 is a block diagram representation of the dual voltage regulated con-
verter system. The block diagram includes a simplified version of the converter block
diagram from Figure 6-6. Because the feedback control for both converters only oper-
227
6.6. Regulator Example 1: Dual Voltage-mode Regulated Power System
îin1
+
−
Le1
v̂f c
+
− j1 (s)d̂1 Ce1
d̂1 (s) H1 (s)
+
v̂ref 1 (s)
FM 1 Gc1 (s) Σ
-
îin2

+
−
+
Le2 î
v̂batt
+
− j2 (s)d̂2 Ce2 v̂(s) R
-
d̂2 (s) H2 (s)
+
v̂ref 2 (s)
FM 2 Gc2 (s) Σ
-
Figure 6-7: Dual voltage regulator system linearized model
ates on the output voltage measurement, the converter output currents are not needed
in this example. Also, the load current perturbations will not be considered in this
example. The ×’s are points that we will break in the block diagram to evaluate loop
transfer functions.
Intuitively, we expect this system to enable the run time integral diagnostics
functionality described in the introduction. The two voltage regulated converters
should behave as low impedance outputs at the load. In generating an excitation
current for EIS measurements of one source, that current should be diverted away
from the load and into the output of the opposite converter. Thus the limitations
that would normally come with and EIS-enabled single converter system are already
overcome with this simple approach.
228
Power Systems
dˆ1 v̂
ˆ
d1 +
v̂
Σ
dˆ2 +
v̂ H1 H2
ˆ
d2
−
a
Fm1 Gc1 Σ
x y
+
v̂ref 1
−
b
Fm2 Gc2 Σ
q z
+
v̂ref 2
Figure 6-8: Dual voltage regulator system block diagram
6.6.1 Closed-Loop Transfer Functions
Here we consider the system in Figures 6-7 and 6-8 in which the second reference
voltage is purely DC, but the first reference voltage is used as a control input. Thus,
v̂ref 1 is designated the “control voltage.” That is,
v̂ref 1 6= 0 (6.57)
v̂ref 2 = 0. (6.58)
229
In this case, the two duty ratios become
dˆ1 = Fm1 Gc1 (v̂ref 1 − H1 v̂) (6.59)
dˆ2 = −Fm2 Gc2 H2 v̂, (6.60)
in which it is explicit that, upon addition of voltage-mode feedback control, both duty
ratios now exhibit a functional dependence on the load voltage, v̂. In this system,
dˆ1 also has a functional dependence on the reference voltage v̂ref 1 which has been
taken as a small-signal control input. For simplicity, the rest of this analysis assumes
identical feedback loops so that Fm1 = Fm2 ≡ Fm , Gc1 = Gc2 ≡ Gc , H1 = H2 ≡ H,
e1 = e2 ≡ e, j1 = j2 ≡ j. With these simplifications,
e1 dˆ1 + e2 dˆ2 = e(dˆ1 + dˆ2 ) (6.61)
and the duty ratios become
dˆ1 = Fm Gc (v̂ref 1 − H v̂) (6.62)
dˆ2 = −Fm Gc H v̂ (6.63)
so that
e(dˆ1 + dˆ2 ) = e (Fm Gc (v̂ref 1 − 2v̂H)) (6.64)
e1 dˆ1 = eFm Gc (v̂ref 1 − H v̂) (6.65)
e2 dˆ2 = −eFm Gc H v̂. (6.66)
v̂ ˆ ˆ
iin1
Here we consider the closed-loop transfer functions, , îo1 , io2 ,
v̂ref 1 v̂ref 1 îo1
and v̂ref 1
.
v̂
Closed Loop Transfer Function v̂ref 1
:
From equation (6.47), the output voltage becomes
v̂ = MλeFm Gc (v̂ref 1 − 2H v̂) (6.67)
230
Power Systems
so that collecting terms leads to
v̂ (1 + 2HMλeFm Gc ) = MλeFm Gc v̂ref 1 (6.68)
and dividing by v̂ref 1 yields the transfer function,
v̂ MeFm Gc λ
= . (6.69)
v̂ref 1 1 + 2MeFm Gc Hλ
It will be convenient to define the following quantity at this point:
T ≡ MeFm Gc H, (6.70)
so that the transfer function can be re-written:
v̂ 1 Tλ
= . (6.71)
v̂ref 1 H 1 + 2T λ
î
:
î v̂
The transfer function vref 1
can be taken from vref 1
quite simply as follows, i.e. î =
v̂/R:
î 1 Tλ
= . (6.72)
v̂ref 1 HR 1 + 2T λ
îo1
:
From equation (6.49), the first converter’s output current becomes

1 1
îo1 = M eFm Gc (v̂ref 1 − H v̂) − λeFm Gc (v̂ref 1 − 2H v̂) (6.73)
Zle Ze
231
so that dividing by v̂ref 1 leads to

îo1 1 v̂ 1 v
=M eFm Gc 1 − H − λeFm Gc 1 − 2H
v̂ref 1 Zle v̂ref 1 Ze v̂ref 1

v̂ 1 1 1 1
=M λeFm Gc 2H − eFm Gc H + eFm Gc − λeFm Gc
v̂ref 1 Ze Zle Zle Ze

v̂ 2λT T T λT
= − + −
v̂ref 1 Ze Zle HZle HZe

v̂ 2λT T T 1 λ
= − + − ,
v̂ref 1 Ze Zle H Zle Ze
(6.74)
v̂
in which the expression for v̂ref 1
may be substituted from the results above leading
to
îo1 1 1 Tλ 2λT T T 1 λ
= − + − . (6.75)
v̂ref 1 Ze H 1 + 2T λ Ze Zle H Zle Ze
Simplifying yields the transfer function,
!
îo1 T λT ( Z2λe − 1
Zle
) 1 λ
= + − . (6.76)
v̂ref 1 HZe 1 + 2T λ Zle Ze
îo2
Closed Loop Transfer Function vref 1
:
From equation (6.50), the second converter’s output current becomes

eFm Gc H v̂ λeFm Gc
îo2 =M − − (v̂ref 1 − 2H v̂) (6.77)
Zle Ze
so that dividing by v̂ref 1 leads to

îo2 eFm Gc H v̂ λeFm Gc v
=M − − 1 − 2H
v̂ref 1 Zle v̂ref 1 Ze v̂ref 1
(6.78)
v̂ 2λT T λT
= − − .
v̂ref 1 Ze Zle HZe
232
Power Systems
v̂
in which the expression for v̂ref 1
may be substituted from the results above leading
to
îo2 1 Tλ 2λT T λT
= − − . (6.79)
v̂ref 1 H 1 + 2T λ Ze Zle HZe
Simplifying in two steps leads to
!
îo2 λT T ( Z2λe − 1
Zle
) 1
= − . (6.80)
v̂ref 1 H 1 + 2T λ Ze
îo2
Closed Loop Transfer Function îo1
:
The ratio of the first converter’s output current to the second converter’s output
current under excitation from v̂ref 1 can be found using a linear combination of two of
the transfer functions above. That is
!−1
îo2 îo2 îo1
= (6.81)
îo1 vref 1 vref 1
leading to
2λ

T(Z − Z1 )
λT e 1
H 1+2T λ
le
− Ze
îo2
= 2λ . (6.82)
îo1 λT ( Z − Z1 )
e 1 λ
1+2T λ
le
+ Zle
− Ze
Note that it would be a misinterpretation to view this ratio as “the output current to
the second converter upon injecting an output current to the first converter” because
the denominator in this ratio was not the input signal in this case.
îin1
Closed Loop Transfer Function vref 1
:
Finally, the transfer function from control voltage to the first converter’s input current
can be found as follows. From equation (6.51), the first converter’s input current
becomes
v̂
îin1 = jFm Gc (v̂ref 1 − H v̂) + M îo1 + . (6.83)
Zce1
233
so that dividing by the control voltage yields
!
îin1 v̂ îo1 M v̂
= jFm Gc 1 − H +M + , (6.84)
vrefˆ1 v̂ref 1 v̂ref 1 Zce v̂ref 1
v̂ îo1
in which the transfer functions v̂ref 1
and v̂ref 1
have already been derived above so no
further simplification is required.
Summary
The results above are summarized here having substituted in the results for the
converter transfer functions:
v̂ 1 λT
= (6.85)
v̂ref 1 H 1 + 2T λ
!
îo1 T λT ( Z2λe − 1
Zle
) 1 λ
= + − (6.86)
v̂ref 1 H 1 + 2T λ Zle Zle
2λ

T(Z − Z1 )
λT e 1
H 1+2T λ
le
− Ze
îo2
= 2λ 1 (6.87)
îo1 λT ( Z − Z )
e 1 λ
1+2T λ
le
+ Zle
− Ze
!
îin1 v̂ îo1 M v̂
= jFm Gc 1 − H +M + , (6.88)
vrefˆ1 v̂ref 1 v̂ref 1 Zce v̂ref 1
T ≡HGc Fm eM (6.89)
ZL ||Zle
λ≡ . (6.90)
Zle + Zle ||ZL
Discussion
From the results in (6.85)-(6.88), some interesting observations can be made about the
behavior of the system in Figure 6-7. Equation (6.85) describes the output voltage
variation in response to the control voltage. For large T , that transfer function
approaches 1/2H. For a sensor gain of unity (H = 1), the result is 1/2. Perturbing
234
Power Systems
the reference voltage for one converter in this two-converter system, perturbs the
output voltage, half as much as it would in a single-converter system.
Equation (6.86) describes the first converter’s output current variation in response
to the control voltage. For large T , that transfer function approaches T /HZle . For
a sensor gain of unity (H = 1), the result is T /Zle . Equation (6.87) says that for
large T , the second converter’s output current is the opposite of the first converter’s
output current. That is, small-signal currents flow out of one converter and into the
other. This behavior is consistent with the intuition that each converter, operating
under voltage-mode feedback control, behaves as a low impedance to the load.
Equation (6.88) describes the first converter’s input current variation in response

îo1
to the control voltage. For large T , that transfer function approaches M v̂ref 1

v̂
because v̂ref 1
approaches 1/H. The first converter’s input current is largely its
output current reflected back through the ideal transformer with transformation ratio
M.
Dividing the limiting results for the load voltage response and the first converter’s
1/2H
input current response leads to M T /Zle
. Because the loop gain is in the denominator,
this is a small quantity. Therefore, the control voltage amplitude needed to generate
suitable excitation currents should lead to relatively small load voltage perturbations.
6.6.2 Open-Loop Transfer Functions
The open-loop transfer functions are needed, most notably to investigate the stability
of the regulator. For this purpose, we examine the block diagram in Figure 6-8.
Breaking the loop at one point for each error signal, e.g. points a and b, will reveal
the required transfer functions. The open-loop transfer functions can be viewed as
a measure of the signal that returns having broken the loop and injected a signal at
the break. By convention, the open-loop transfer functions are the negative of that
235
ratio. Mathematically
y
T1 = − (6.91)
x
z
T2 = − . (6.92)
q
In the case of two voltage feedback loops, these transfer functions are
v̂
T1 = H1 (6.93)
x
v̂
T2 = H2 . (6.94)
q
Expanding the measured signal, v̂, using linear superposition casts the transfer func-
tions in a more useful form
!
dˆ1 v̂ dˆ2 v̂
T1 = H1 + (6.95)
x dˆ1 x dˆ2
!
dˆ2 v̂ dˆ1 v̂
T2 = H2 + . (6.96)
q dˆ2 q dˆ1
v̂ v̂
The converter transfer functions dˆ1
and dˆ2
have already been determined. What is
d1 dˆ2 dˆ1 dˆ2
ˆ
left is to compute the transfer functions x
, x , q , q as determined by the feedback
structure.
The needed transfer functions may be found by inspecting the block diagram. The
duty ratios are
dˆ1 = xGc1 Fm1 (6.97)
and
ˆ ˆ v̂ ˆ v̂
d2 = −Fm2 Gc2 H2 d1 + d2 (6.98)
dˆ1 dˆ2
so that
dˆ1
= Gc1 Fm1 (6.99)
x
and !
dˆ2 dˆ1 v̂ dˆ2 v̂
= −Fm2 Gc2 H2 + . (6.100)
x x dˆ1 x dˆ2
236
Power Systems
Solving the system of equations above yields the needed transfer functions
dˆ1
= Gc1 Fm1 (6.101)
x
and
dˆ2 Fm2 Gc2 H2 Gc1Fm1 dˆv̂
1
=− . (6.102)
x 1 + Fm2 Gc2 H2 ˆv̂ d2
The equivalent transfer functions for the second loop are trivial because of the sym-
metry in this example.
Combining the transfer functions in (6.101)-(6.102) with the converter transfer
functions (6.37)-(6.38) and substituting into the expressions in (6.95)-(6.96) will yield
the loop transfer functions required to evaluate the stability of the dual voltage reg-
ulated system.
Discussion
ˆ
For large, T = Fm Gc H, the second transfer function approaches Gc1 Fm1 H1 v̂/d1
v̂/dˆ
. In-
2
dˆ1
serting this expression and the exact expression for x
into the loop gain, T1 from
(6.95) leads to
T1 ≈ 2H1 Gc1 Fm1 . (6.103)
The second loop transfer function similarly approaches
T2 ≈ 2H2 Gc2 Fm2 . (6.104)
Thus the two loop transfer functions approach twice the loop transfer functions for
two separate single converter systems. This result is due to the symmetrical nature
of the regulator considered in this example.
237
6.7. Regulator Example 2: Master-Slave Current-Voltage Regulated Power System
6.7 Regulator Example 2: Master-Slave Current-

Voltage Regulated Power System
The linearized circuit in Figure 6-9 is a linearized model of a multi-converter power
system with two power converters, one under voltage-mode feedback control and the
other under output current-mode feedback control. This system is sometimes called
a master-slave current-voltage regulated system. The linearized model includes the
general linearized multi-converter model from Figure 6-5 as well as linearized blocks
comprising the basic components required for feedback control.
îin1

+
−
Le1
v̂f c
+
− j1 (s)d̂1 Ce1
Rsense
- +
d̂1 (s) H1 (s)
+
v̂ref 1 (s)
FM 1 Gc1 (s) Σ
-
îin2

+
−
+
Le2
v̂batt îload
+ î
− j2 (s)d̂2 Ce2 v̂(s)
-
d̂2 (s) H2 (s)
+
v̂ref 2 (s)
FM 2 Gc2 (s) Σ
-
Figure 6-9: Master-slave regulator system linearized model
Figure 6-10 is a block diagram representation of the master-slave regulated con-

verter system. The block diagram includes the converter block diagram from Figure
6-6. The ×’s are points that we will break in the block diagram to evaluate loop
transfer functions.
238
Power Systems
îload
îo1
îload
dˆ1 îo1
dˆ1 + + îo1
Σ
+
îo1
dˆ2
Rsense
v̂
îload
v̂
ˆ
d1 +
+ v̂
Σ
+
v̂ H2 H1
ˆ
d2
dˆ2
−
b
Fm2 Gc2 Σ
q z
+
v̂ref 2
−
a
Fm1 Gc1 Σ
x y
+
v̂ref 1
Figure 6-10: Master-slave regulator system block diagram
239
Intuitively, we expect this system to enable the run time integral diagnostics
functionality described in the introduction. The voltage regulated converter should
behave as a low impedance output at the load. In generating an excitation current
for EIS measurements of the first source, that current should be diverted away from
the load and into the output of the voltage-regulated converter. Thus the limitations
that would normally come with and EIS-enabled single converter system are overcome
with this approach. Also, because the first converter is current-regulated, its output
current should remain fixed despite load current perturbations. We will see that
this also implies a relatively fixed input current to the first converter despite load
current perturbations. The voltage-regulated converter naturally accommodates the
excess load current, whether it be positive or negative. Thus the master-slave system
can achieve the current buffering feature needed for fuel cell power processing in
applications having widely varying load power.
6.7.1 Closed-loop Transfer Functions
Here we consider the system in Figures 6-9 and 6-10 in which the second reference
voltage is purely DC, but the first reference voltage is used as a control input. Thus,
v̂ref 1 is designated the “control voltage.” That is,
v̂ref 1 6= 0 (6.105)
v̂ref 2 = 0. (6.106)
In this case, the two duty ratios become

dˆ1 = Fm1 Gc1 v̂ref 1 − H1 Rsense îo1 (6.107)
dˆ2 = −Fm2 Gc2 H2 v̂, (6.108)
in which it is explicit that, upon addition of voltage-mode and current-mode feedback

control, the duty ratios now exhibit a functional dependence on the load voltage, v̂,
and the first converter’s output current, îo1 , respectively. In this system, dˆ1 also has
240
Power Systems
a functional dependence on the reference voltage v̂ref 1 which has been taken as a
small-signal control input. We also consider the case a superimposed load current
perturbation. In this case, the two duty ratios are
dˆ1 = −Fm1 Gc1 H1 Rsense îo1 (6.109)
dˆ2 = −Fm2 Gc2 H2 v̂. (6.110)
In contrast to the first example, we do not assume identical converters here. Ad-
ditionally identical feedback loops is not a valid assumption because the two feedback
loops regulate nonequivalent output variables. Because the analysis of this system is
somewhat more complicated, we approach the analysis starting from a linear signal
decomposition of the transfer functions of interest.
ˆ ˆ
The closed loop transfer functions of interest are v̂
, î , iin1 ,
v̂ref 1 v̂ref 1 v̂ref 1
and iin1
îload
. The
first three of those closed-loop transfer functions take as an input the control signal
ˆ
iin1
v̂ref 1 . The last of those closed-loop transfer functions, îload
, takes the load current
perturbation as the input. For the closed loop transfer responses to the input îload
we leave the results in terms of the already-derived converter transfer functions for
brevity. Because îload is an external input in both the open-loop and closed-loop cases,
the notation for the closed-loop transfer functions from îload should be specified to
avoid confusion. We will use the following notation to specify the closed-loop transfer

functions as opposed to the converter transfer functions from îload : î v̂ , î îo1 .

load CL load CL
The closed loop transfer functions may be written as linear decompositions as
follows (for the control signal input). The transfer function from the control signal
to the load voltage:

v̂ v̂ dˆ1 v̂ dˆ2
= + , (6.111)
v̂ref 1 CL dˆ1 v̂ref 1 dˆ2 v̂ref 1
to the load current:

!
î 1 v̂ dˆ1 v̂ dˆ2
= + , (6.112)
v̂ref 1
CL
R dˆ1 v̂ref 1 dˆ2 v̂ref 1
241
to the first converter’s output current:

îo1 îo1 dˆ1 îo1 dˆ2
= + , (6.113)
v̂ref 1
CL
dˆ1 v̂ref 1 dˆ2 v̂ref 1
and to the second converter’s output current:

= + . (6.114)
v̂ref 1
CL
dˆ1 v̂ref 1 dˆ2 v̂ref 1
Additionally, the first converter’s input current can be written as a linear superposi-
tion as follows
!
îin1 dˆ1 îo1 v̂ 1
= j1 + M1 + . (6.115)
v̂ref 1 v̂ref 1 v̂ref 1 v̂ref 1 CL Zce1
CL CL
The closed-loop transfer with the load current perturbation input may be similarly
written as follows. The transfer function from the load current to the load voltage:

v̂ v̂ dˆ1 v̂ dˆ2
= + , (6.116)
î
load CL dˆ1 îload dˆ2 îload

= + , (6.117)
îload CL dˆ1 îload dˆ2 îload
and to the second converter’s output current:

= + . (6.118)
îload CL dˆ1 îload dˆ2 îload
Additionally, the first converter’s input current can be written as a linear superposi-
tion as follows
!
= j1 + M1 + . (6.119)
îload CL îload îload CL îload CL Zce1
242
Power Systems
The linear decomposition forms of the closed-loop transfer functions above highlight
the contributions of the converter transfer functions and the feedback structure.
The analysis of the closed-loop transfer functions having v̂ref 1 as the input can
dˆ1 dˆ2
be reduced to deriving the transfer functions v̂ref 1
and v̂ref 1
based on the feedback
control in this particular example. The analysis of the closed-loop transfer functions
dˆ1
having îload as the input can be reduced to deriving the transfer functions îload
and
dˆ2
îload
based on the feedback control in this particular example.
dˆ2
Closed Loop Transfer Function dˆ1
:
From the expressions for the duty ratios above, we have

dˆ1 = Fm1 Gc1 v̂ref 1 − H1 Rsense îo1 (dˆ1 , dˆ2 ) . (6.120)
Substituting in the expression for îo1 and solving, we arrive at

dˆ2
Fm1 Gc1 v̂ref 1 + H1 Rsense M2 λ2 eZ2e1
dˆ1 = . (6.121)
1
1 + Fm1 Gc1 H1 Rsense M1 Zle1
− λ1 Z1e1 e1
The expression for the second converter duty ratio provides a second constraint:
dˆ2 = −H2 Fm2 Gc2 v̂(dˆ1 , dˆ2 ) (6.122)
(6.123)
Substituting in the expression for v̂ and solving, we arrive at
H2 Fm2 Gc2 M1 λ1 e1 dˆ1

dˆ2 = − . (6.124)
1 + H2 Fm2 Gc2 M2 λ2 e2
From this second constraint, we identify the intermediate transfer function
dˆ2 H2 Fm2 Gc2 M1 λ1 e1

=− . (6.125)
dˆ1 1 + H2 Fm2 Gc2 M2 λ2 e2
243
dˆ1
:
ˆ
Replacing dˆ2 with the quantity dˆ1 ddˆ2 in the expression for dˆ1 above and solving for dˆ1
1
we arrive at
 ˆ
−1
dˆ1 Fm1 Gc1  Fm1 Gc1 H1 Rsense M2 λ2 Zee1
2 d2
dˆ1
= 1−  , (6.126)
v̂ref 1 α α
where we define

1 1
α ≡ 1 + Fm1 Gc1 H1 Rsense M1 − λ1 e1 . (6.127)
Zle1 Ze1
dˆ2
:
The transfer function from the control input to the second duty ratio can then be
found using the following transformation
dˆ2 dˆ1 dˆ2

= . (6.128)
v̂ref 1 v̂ref 1 dˆ1
dˆ1
Closed Loop Transfer Function îload
:
From the expressions for the duty ratios in the case that îload is activated and v̂ref 1
is deactivated we have
! ! !!
îo1 îo1 îo1
dˆ1 = −Fm1 Gc1 H1 Rsense dˆ1 + dˆ2 + îload (6.129)
dˆ1 dˆ2 îload
It will be useful to identify the following quantities
F1 ≡ Fm1 Gc1 H1 Rsense (6.130)
F2 ≡ Fm2 Gc2 H2 . (6.131)
244
Power Systems
Now solving for the first duty ratio we have

F1 dˆ2 îdô1 + îload î îo1
dˆ1 = −
2
load . (6.132)
1 + F1 îdô1
1
The second duty ratio provides the needed constraint such that

v̂ v̂ v̂
dˆ2 = −F2 dˆ1 + dˆ2 + îload . (6.133)
dˆ1 dˆ2 îload
and solving for the second duty ratio leads to

F2 dˆ1 dˆv̂ + îload î v̂
dˆ2 = −
1
load . (6.134)
1 + F2 dˆv̂
2
Substituting this expression for the second duty ratio into the expression for the first
leads to !
F2 dˆ1 v̂
+F2 îload v̂
d̂1 î îo1 îo1
F1 load − îload
1+F2 v̂ dˆ2 îload
d̂2
dˆ1 = (6.135)
îo1
1 + F1 dˆ1
and solving leads to

v̂ îo1
F1 F2
îload d̂2 îo1
− F1 îload
dˆ1
v̂
1+F2
d̂2
= ! . (6.136)
îload F1 F2 v̂
d̂1
îo1
d̂2
î
1+F1 ô1
d2
îo1
1 + F1 dˆ1
1−
v̂
1+F2
dˆ2
dˆ2
Closed Loop Transfer Function îload
:
The second transfer function can be found having derived the first transfer function
simply:

dˆ1 v̂ v̂
dˆ2 F2 îload dˆ1
+ îload
=− . (6.137)
îload 1 + F2 v̂
dˆ2
245
Summary
Having substituted the results for the converter transfer functions (6.37)-(6.46) into
the linear decompositions in (6.114)-(6.115), the results above with v̂ref 1 as the closed-
loop transfer function input are summarized here. The closed-loop transfer function
from the control signal to the load voltage:

v̂ dˆ1 dˆ2
= e1 M1 λ1 + e2 M2 λ2 , (6.138)
v̂ref 1 CL v̂ref 1 v̂ref 1
to the load current:

î v̂1
= , (6.139)
v̂ref 1 v̂ref 1 R
CL

îo1 1 1 dˆ1 e2 dˆ2
= M1 − λ1 e1 − M2 λ2 , (6.140)
v̂ref 1 Zle1 Ze1 v̂ref 1 Ze1 v̂ref 1
CL
and to the first converter’s input current:

= j1 + M1 + M1 . (6.141)
vrefˆ 1 v̂ref 1 v̂ref 1 v̂ref 1 Zce1
CL
Additionally, we have found
dˆ2 H2 Fm2 Gc2 M1 λ1 e1

=− (6.142)
dˆ1 1 + H2 Fm2 Gc2 M2 λ2 e2
 −1
e2 dˆ2
ˆ
d1 Fm1 Gc1  Fm1 G c1 H 1 Rsense M2 λ 2 Ze1 dˆ1
= 1−  (6.143)
v̂ref 1 α α
dˆ2 dˆ1 dˆ2

= (6.144)
v̂ref 1 v̂ref 1 dˆ1
and defined
1 1
α ≡ 1 + Fm1 Gc1 H1 Rsense M1 − λ1 e1 . (6.145)
Zle1 Ze1
246
Power Systems
Having substituted the results for the converter transfer functions (6.37)-(6.46)
into the linear decompositions in (6.118)-(6.119), the results above with îload as the
closed-loop transfer function input are summarized here. The closed-loop transfer
function from the load current perturbation to the load voltage:

v̂ dˆ1 dˆ2
= e1 M1 λ1 + e2 M2 λ2 , (6.146)
î
load CL îload îload

îo1 1 1 dˆ1 e2 dˆ2
= M1 − λ1 e1 − M2 λ2 , (6.147)
îload CL Zle1 Ze1 îload Ze1 îload
and to the first converter’s input current:

= j1 + M1 + M1 . (6.148)
ˆ
iload îload îload îload

CL Zce1
CL CL
Additionally, we have found

îo1 îo1
dˆ1 F1 F2 î v̂ dˆ2
− F1 î 1 + F v̂
2 dˆ
= load
2
load
(6.149)
îload 1 + F1 dˆ îo1
1 + F2 dˆ − F1 F2 dˆv̂
v̂ îo1
1 + F1
îo1
1 2 1 dˆ2 dˆ2

dˆ1 v̂
dˆ2 F2 îload dˆ1
+ î v̂
=− load (6.150)
1̂load 1 + F2 dˆv̂
2
and defined
F1 ≡ Fm1 Gc1 H1 Rsense (6.151)
F2 ≡ Fm2 Gc2 H2 . (6.152)
Discussion
dˆ2
As the voltage feedback gain, Gc2 , increases toward ∞, the ratio dˆ1
→ −1. The
load voltage response to perturbations of the other control signal, v̂ref 1 , approaches
247
the quantity e1 M1 λ1 − e2 M2 λ2 , a term that defines the difference between the two
converter elements, and will be zero for identical converters. That is as the voltage
feedback gain increases, the output voltage is better regulated as expected.
As the loop gains, F1 and F2 increase toward ∞, the closed-loop transfer functions
dˆ1 dˆ2
îload îload
both collapse. Then, all of the closed-loop transfer functions collapse as
well. Significantly, the input current response to load current perturbations collapses
implying that the current regulated converter input current is well buffered from
transients in the load. Note however that the closed-loop transfer function from îload
to the first converter’s output current depends on the reciprocal of that converters
total open-loop output impedance. At zero frequency (DC), an ideal inductor will
yield a converter open-loop output impedance of zero so the reciprocal will approach
∞. The dependence of the first converter’s input current transfer function on the
first converter’s output current transfer function leads to the subtle point that the
quality of the buffering of the first converter’s input current depends quite strongly
on the ESR’s and other added resistances in series with the first converter’s output.
Only those resistances comprise the zero frequency total converter output impedance.
In other words, the current regulation may be viewed as a means for increasing the
open-loop output impedance of the converter. If, however, there is zero open-loop
output impedance, e.g. at zero frequency having zero ESR, the current regulation
can not present a large output impedance.
6.7.2 Open-Loop Transfer Functions
The open-loop transfer functions can be derived in a similar fashion to those in the
first example. Starting from the general expressions and the block diagram in Figure
6-10
y
T1 = − (6.153)
x
z
T2 = − . (6.154)
q
248
Power Systems
In the case of one voltage and one current feedback loop, these transfer functions are
îo1
T1 = H1 Rsense (6.155)
x
v̂
T2 = H2 . (6.156)
q
Expanding the measured signals using linear superposition casts the transfer functions
in a more useful form
!
dˆ2 îo1 dˆ1 îo1
T1 = H1 Rsense + (6.157)
x dˆ2 x dˆ1
!
dˆ1 v̂ dˆ2 v̂
T2 = H2 + . (6.158)
q dˆ1 q dˆ2
The loop transfer function, T2 , corresponds to the voltage feedback loop evidenced
by the converter transfer functions that it depends on most directly and by the error
signal that it corresponds to in the block diagram of Figure 6-10. The loop transfer
function, T1 , corresponds to the current feedback loop.
v̂ îo1
The converter transfer functions dˆ1
and dˆ2
have already been determined. What
dˆ1 dˆ2 dˆ1 dˆ2
is left is to compute the transfer functions x
, x , q , q as determined by the feedback
structure. The needed transfer functions may be found by inspecting the block dia-
gram. We break the loop at one point at a time to inspect one loop transfer function
at a time.
Breaking the loop at point a, the duty ratios are
dˆ1 = xGc1 Fm1 (6.159)
dˆ2 = −Fm2 Gc2 H2 v̂ (6.160)

v̂ ˆ v̂ ˆ
= −Fm2 Gc2 H2 d1 + d2 (6.161)
dˆ1 dˆ2
249
so that
dˆ1
= Gc1 Fm1 (6.162)
x !
dˆ2 v̂ dˆ1 v̂ dˆ2
= −Fm2 Gc2 H2 + . (6.163)
x dˆ1 x dˆ2 x
dˆ1
= Gc1 Fm1 (6.164)
x
dˆ2 Fm2 Gc2 H2 Gc1Fm1 dˆv̂
1
=− . (6.165)
x 1 + Fm2 Gc2 H2 dˆv̂
2
Breaking the loop at point b, the duty ratios are
dˆ2 = qGc2Fm2 (6.166)
dˆ1 = −Fm1 Gc1 H1 Rsense îo1 (6.167)

!
îo1 ˆ îo1
= −Fm1 Gc1 H1 Rsense d1 + dˆ2 (6.168)
dˆ1 dˆ2
so that
dˆ2
= Gc2 Fm2 (6.169)
q
!
dˆ2 îo1 dˆ1 îo1 dˆ2
= −Fm1 Gc1 H1 Rsense + . (6.170)
q dˆ1 q dˆ2 q
dˆ1
= Gc1 Fm1 (6.171)
q
dˆ2 Fm1 Gc1 H1 Rsense Fm2 Gc2 îdô1
2
=− . (6.172)
q î
1 + Fm1 Gc1 H1 Rsense ˆ o1
d1
Combining the transfer functions in (6.164)-(6.165) and (6.171)-(6.172)with the

converter transfer functions (6.37)-(6.38) and (6.41)-(6.42) and substituting into the
250
Power Systems
expressions in (6.157)-(6.158) will yield the loop transfer functions required to evaluate
the stability of the master-slave voltage-current regulated system.
251
252
Chapter 7
The Effect of Multiple Input

Filters in Multi-converter,
Multi-source Power Systems
In the analyses so far, we have assumed an ideal input source - one that has zero-
valued output impedance. Typical requirements for practical designs specify a max-
imum amount of input current ripple. An input filter is often needed to meet these
requirements. However, the addition of an input filter modifies the effective source
impedance presented to the converter. The designer must know how to select input
filter components so that the ideal input source assumption that was implicit in the
converter design is not significantly undermined.
This chapter complements the multi-converter analysis in Chapter 6 with a method-

ology for choosing the components of multiple input filters in a multi-converter system.
The design guidelines and the methods for quantifying the impact of the added input
filters are developed from an application of the two extra element theorem (2EET).
The methodology could be extended to a system having N converters and N input
filters using the N extra element theorem (NEET). Before addressing the addition
of multiple input filters in a multi-converter system, we first review the analogous
problem for single converter systems.
253
7.1. Single Converter Systems Review: The Extra Element Theorem for Input
Filter Evaluation
7.1 Single Converter Systems Review: The Extra

Element Theorem for Input Filter Evaluation
The treatment of an input filter as a “post-facto” element in a power converter design
is a likely outcome of natural design processes. Incidentally, this treatment is also
analytically advantageous because the converter can be designed without the input
filter and then the extra element theorem (EET) applied to determine the resulting
modification of the converter dynamics. The extra element theorem, best summa-
rized by Middlebrook in [151], allows the designer to replace one cumbersome and
uninsightful calculation, with a few simple and elegant calculations.
7.1.1 Review of the EET
The extra element theorem follows from an application of the principle of “null double
injection” to a linear circuit [151]. Upon addition of an extra element to the circuit,
the transfer function of interest can be modified by using the calculated impedance
seen at the “extra element port” under two special cases:
1. The “null-condition” impedance, Zn−c (s), is calculated for the case correspond-
ing to null-double injection. It is the impedance seen at the extra element
port when the transfer function input signal is directed in such a way that the
transfer function output signal is nulled (equal to zero).
2. The “open-loop” impedance, Zo−l (s), is calculated for the case corresponding
to the open-loop behavior. It is the impedance seen at the extra element port
when the transfer function input signal is deactivated (set to zero).
Based on these definitions of the special-case impedances, it should be clear that any
pair of special-case impedances corresponds to a particular transfer function. That
particular transfer function is specified by its input and output signals.
Fundamentally, the extra element theorem uses the unique information obtained
about the circuit by calculating those two special-case impedances to derive the cir-
cuit’s interaction with the extra element itself. The primary result of the ensuing
254
7. The Effect of Multiple Input Filters in Multi-converter, Multi-source Power
Systems
mathematical manipulations is a statement of the correction factor that multiplies

the original transfer function. For a series extra element (one that replaces a short-
circuit in the original circuit), the correction factor is
Zo (s) !
1+ Zn−c (s)
CF = Zo (s)
, (7.1)
1+ Zo−l (s)
in which Zn−c (s) is the special-case impedance calculated for the null condition,
Zo−l (s) is the special-case impedance calculated for the open-loop condition and Zo (s)
is the impedance of the extra element itself.
7.1.2 Modified Converter Transfer Functions in Single-Converter

Systems
The addition of an input filter modifies the converter transfer functions from Chapter
6. This effect is due to the interaction of the input current perturbation, represented
ˆ in the canonical circuit model of Figure 6-2(b), with the input filter.
by (s)d(s)
Figure 7-1(a) depicts an input filter added onto a converter. The input filter may
be represented to the converter by its Thevenized output impedance (and output
voltage) as suggested by Figure 7-1(b). To calculate the special-case impedances, the
input filter output impedance element, Zo , is left out in favor of the “extra element
port” as suggested by Figure 7-1(c).
Having chosen the converter transfer function to be studied, one can proceed to
derive the corresponding special-case impedances, Zo−l and Zn−c . Based on the def-
initions in Section 7.1.1, the converter transfer function input and output signals
establish the constraints leading to the corresponding special-case impedances. De-
riving the special-case impedances, inserting them into the correction factor from
(7.1) and multiplying by the original converter transfer function yields the corrected
converter transfer function. For instance, the corrected converter transfer function
255
Filter Evaluation
dˆ
Lf
+ +
îload
+ Cf
v̂g − v̂in Converter v̂ R
− −
(a) An input filter added onto a converter’s input.

dˆ
Zo
+ +
îload
+
v̂gth − v̂in Converter v̂ R
− −
(b) The input network is replaced with its Thevenin equiva-

lent.
dˆ
Zin
+ +
Extra elt. port
îload
+
v̂gth − v̂in Converter v̂ R
− −
(c) The filter output impedance is removed leaving the extra

element port.
Figure 7-1: The EET can be applied by considering the special-case impedances at
the extra element port.
from duty ratio to output voltage can be written
G′vd (s) = CFvd Gvd (s). (7.2)
Some example special-case impedances are shown in Table 7.1 for three different
converter types [14]. The results in Table 7.1 were calculated for correcting the duty-
ratio to output voltage converter transfer function, Gvd (s), upon addition of an input
filter [14]. The converter transfer function, Gvd (s), is usually of particular interest
because it is typically “in the loop.” The modification of Gvd (s) by multiplication with
the appropriate correction factor yields a change, and sometimes a degradation, in
the stability of the closed-loop system. For this reason, the special-case impedances
shown in Table 7.1 are historically named ZN and ZD because they appear in the
256
Systems
Table 7.1: Special-case impedances for correcting Gvd (s) in CCM-operated converters
with a fixed load, R [14].
Converter Zn−c (s) Zo−l (s)
R (1+s R +s LC )
L 2
Buck − DR2 D 2 (1+sRC)
sL
(1+s D′2L R +s2 DLC′2 )
Boost −D ′2 R 1 − D ′2 R
D ′2 R (1+sRC)
D ′2 R (1+s D ′2 R +s D ′2 )
L 2 LC
′2
Buck-Boost − DD2R 1 − sDL
D ′2 R D 2 (1+sRC)
numerator and denominator, respectively, of the correction factor for this (typically)
critical transfer function.
7.1.3 Modified Feedback Control in Single-Converter Sys-

tems
From Chapter 7, the converter transfer functions play an important role in the closed-
loop transfer functions for a feedback regulated system. Carrying the correction
factors for the converter transfer functions through to the results for the open-loop
and closed loop transfer functions yields the corrected feedback control behavior.
For example, in equation (6.11), the converter transfer function Gvd (s) appears in
the expression for T (s). The corrected open-loop transfer function becomes
T ′ (s) = Gc (s)Fm G′vd (s)H(s) (7.3)
= Gc (s)Fm CFvd Gvd (s)H(s) (7.4)
= CFvd T (s). (7.5)
The closed-loop transfer function from reference voltage to output voltage is written as
a function of the loop transfer function. Therefore the corrected closed-loop transfer
257
Filter Evaluation
function can be written

′
v̂(s) 1 T ′ (s)
= (7.6)
v̂ref (s) v̂g =0 H(s) 1 + T ′ (s)
îload =0
1 CFvd T (s)
= . (7.7)
H(s) 1 + CFvd T (s)
7.1.4 Practical Interpretations and Impedance Inequalities
The expression for the correction factor in (7.1) reveals guidelines for choosing input
filter elements. If the following “impedance inequalities” are met, the corrected trans-
fer function reduces to the original transfer function and the corresponding converter
dynamics are not significantly altered:
|Zo | << |Zn−c | (7.8)
|Zo | << |Zo−l |. (7.9)
Those impedance inequalities qualitatively set upper bounds on the magnitude of the
input filter’s output impedance. The impedance inequalities constitute useful design
criteria because we can plot the three impedances of interest across frequency (bode
plots) and make sure that, at all frequencies, |Zo (s)| is much less than |Zo−l (s)| and
|Zn−c (s)|.
In the context of the duty ratio to output voltage transfer function, Gvd (s), meet-
ing the first inequality will ensure that the filter output impedance is always less than
the negative incremental resistance presented by the inputs of a regulated converter.
For instance, from Tables 6.2 and 7.2, Zn−c (s) for the Buck converter is −V /ID 2 . The
same result can be derived for a lossless (Pout = Pin ), perfectly-regulated converter
(Vout = V = const.) with a fixed load (Iout = I = const.) as follows:

∂Vin ∂ Pout
Zn−c (s) = =
∂Iin ∂Iin Iin
(7.10)
Pout V
= − 2 = − 2.
Iin ID
258
Systems
A typical plot of the three impedances of interest in Figure 7-2 illustrates the
design choices required to meet the inequalities in (7.8)-(7.9). In practice, meeting
the inequality in (7.8) is often achieved for LC filter designs by using a damping leg
(a series RC) shunting the input terminals to decrease the magnitude peaking in the
LC filter output impedance. Meeting the second inequality (7.9) is usually achieved
by setting the frequency of the 2nd-order peak in the input filter output impedance
below that of the 2nd-order dip in the output filter input impedance (represented by
Zo−l (s)).
Special−Case Impedances for correcting v/d
30
20
10
|Zo(s)|
0 |Zn−c(s)|
Magnitude (dB)
|Zo−l(s)|
−10
−20
−30
−40
−50
3 4 5 6
10 10 10 10
Frequency (Hz)
Figure 7-2: A typical frequency plot of the special case impedances, Zn−c (s), Zo−l (s),
and the input filter output impedance, Zo (s), for a single converter system.
The corrected transfer functions can also be used to determine and bound the
effect of adding an input filter if the impedance inequalities are not strictly met.
For example, bode plots of the corrected open-loop transfer functions can reveal the
degradation of the phase margin and therefore the impact of the input filter on the
closed-loop system stability.
259
Filter Evaluation
7.1.5 Example: Generalized Corrections for Single Converter

Systems
This section presents example derivations of the special-case impedances needed in

the correction factor (7.1). The special-case impedances are derived from the canon-
ical circuit model from Chapter 7. The special-case impedances derived here are
generalized. Their numerical values may be found by looking up the canonical model
parameters in a table like Table 6.2 for the converter topology and transfer function
of interest.
260
Systems
Zin (s) ˆ
e(s)d(s) 1 : M (D) Le
+
−
+
îload (s)
+ Ce v̂(s)
−
v̂gth (s) ˆ
j(s)d(s) R
-
(a) A linearized converter model for calculating the special-

case impedances in the extra element correction factors.
ZD (s)
1 : M (D) Le
+
−
+ Ce v̂(s)
− ˆ =0
d(s) R
-
(b) ZD (s)
ZN (s) ˆ v̂(s) → 0
e(s)d(s) 1 : M (D) Le
+
−
+
− Ce v̂(s)
ˆ
j(s)d(s) R
-
(c) ZN (s)
Zg (s) v̂(s) → 0
1 : M (D) Le
+
−
+ Ce v̂(s)
−
v̂gth (s) R
-
(d) Zg (s)
Ze (s) v̂(s) → 0
1 : M (D) Le
+
−
+
îload (s)
+ Ce v̂(s)
−
R
-
(e) Ze (s)
Figure 7-3: Calculating special-case impedances from the canonical circuit model
261
Filter Evaluation
The circuit used for analysis in this section is shown in Figure 7-3(a). The inde-
ˆ
pendent inputs in that system include the duty ratio, d(s), as well as the (Thevinin)
input voltage, v̂gth (s). It should be understood, before proceeding, that deactivating
ˆ source and opens the correspond-
the duty ratio signal shorts the corresponding ed(s)
ˆ source in that converter model. In analyzing each transfer function, defined
ing j d(s)
by an independent input and a corresponding output, all other independent inputs
are deactivated resulting in a circuit that is a simplified version as shown in Figure
7-3. Here we consider three converter transfer functions, Gvd (s), Gvg (s), and Ze (s).
Open-loop Special-Case Impedance: ZD (s)
For the three converter transfer functions considered here, the open-loop special-case
impedance, Zo−l (s) is the same. In analyzing any of the three converter transfer
functions, the independent inputs not corresponding to the transfer function are de-
activated. Further, for the open-loop special-case impedance, the independent input
corresponding to the transfer function of interest is also deactivated leaving no active
independent inputs. The result for the three transfer functions is the same circuit
shown in Figure 7-3(b), and thus the same input impedance, Zin (s). Historically, the
open-loop impedance has been named ZD (s) because it is the special-case impedance
that appears in the denominator of the correction factor for correcting the transfer
function from duty ratio to output voltage [13]. Because the open-loop special-case
impedances are all the same we name them Zo−l (s) = ZD (s) for all of the transfer
functions.
From the circuit in Figure 7-3(b), ZD can be found as follows. The input impedance
is simply the impedance at the secondary,
Zsec (s) = Zle + R||Zce(s) (7.11)
reflected back through the ideal transformer:
Zle + R||Zce (s)

ZD (s) = , (7.12)
M 2 (D)
262
Systems
1
Zce (s) ≡ (7.13)
sCe
Zle (s) ≡ sLe . (7.14)
Null-Condition Special-Case Impedance for Gvd (s): ZN (s)
The null-condition does not generally allow us to simplify the circuit topologically, or
even to easily write down a closed-form expression of the control signal that leads to
the nulled output signal. In fact, it would (generally) be a misinterpretation of the
null-condition to simply short-circuit the output of the converter in Figure 7-3(a) and,
in most cases, would lead to different and incorrect results. But, the null-condition
often allows us to make observations about the circuit that simplify the calculation,
not of the control signal itself, but of the impedance at the extra element port as a
result of the conditions that the control signal must impose on that circuit to null the
output. For example, to calculate Zn−c (s) for correcting Gvd (s), the transfer function
from dˆ to v̂, in the circuit of Figure 7-3(a), we deactivate the other independent
inputs, v̂g and îload , and null the output v̂ → 0. The resulting circuit is shown in
Figure 7-3(c).
The analysis is simplified by realizing that for a nulled output, the small-signal
voltage across the load impedance is zero so no small-signal current flows through the
load. Therefore, no current flows through Le or through the secondary winding of
the ideal transformer. The primary winding current is therefore also zero. Because
the current through Le is zero, the voltage across it is also zero and the zero-valued
(nulled) output voltage appears at the secondary winding of the ideal transformer.
Therefore, the input voltage and current are simply
ˆ
v̂in = −e(s)d(s) (7.15)
ˆ
îin = j(s)d(s), (7.16)
263
Filter Evaluation
so that dividing the two reveals the null-condition input impedance,
e(s)
ZN (s) = − . (7.17)
j(s)
Again, for historical reasons, and its importance to the key transfer function, Gvd (s),
the null-condition impedance for this case is reserved the name ZN (s) because it
appears in the numerator of the correction factor (7.1).
Null-Condition Special-Case Impedance for Gvg (s): Zg (s)
Having Thevenized the input filter to account for its output impedance, the Thev-
enized input voltage is written
v̂gth (s) = H(s)v̂g (s), (7.18)
where H(s) is the multiplicative Thevenin factor. Deactivating the input voltage
(v̂g = 0) will necessarily deactivate the Thevenized input voltage (v̂gth = 0), i.e.
v̂g = 0 =⇒ v̂gth = 0. (7.19)
To calculate Zn−c (s) for correcting Gvg (s), the transfer function from v̂gth to v̂, in the
circuit of Figure 7-3(a), we deactivate the other independent inputs, dˆ and îload , and
null the output v̂ → 0. The resulting circuit is shown in Figure 7-3(d).
Again, for a nulled output, the small-signal voltage across the load impedance is
zero so no small-signal current flows through the load. Therefore, no current flows
through Le or through the secondary winding of the ideal transformer. The primary
winding current is therefore also zero. Because the current through Le is zero, the
voltage across it is also zero and the zero-valued (nulled) output voltage appears at
the secondary winding of the ideal transformer. Therefore, the input voltage and
264
Systems
current are simply
v̂in = v̂gth (s) (7.20)
îin = 0, (7.21)
Zg (s) = ∞ . (7.22)
It is important to include the nonzero multiplicative factor of H(s) in the corrected

transfer function, G′vg (s). For instance, the original transfer function from input
voltage to output voltage is Gvg (s). Upon addition of the input filter, the corrected
transfer function becomes,
G′vg (s) = CFvg Gvg (s)H(s). (7.23)
Null-Condition Special-Case Impedance for Ze (s): Ze (s)
To calculate Zn−c (s) for correcting Ze (s), the transfer function from îload to v̂, (the
converter open-loop output impedance) in the circuit of Figure 7-3(a), we deactivate
the other independent inputs, dˆ and v̂gth , and null the output v̂ → 0. The resulting
circuit is shown in Figure 7-3(e).
Now, with a nulled output, the small-signal voltage across the load impedance is
zero so the load current source, îload requires that the current through Le and through
the secondary winding of the ideal transformer is equal to −îload . The primary winding
current is therefore equal to −M(D)îload . The corresponding voltage across Le is
reflected back through the ideal transformer so that the input voltage and current are
îload Zle
v̂in = − (7.24)
M(D)
îin = −M(D)îload , (7.25)
265
Filter Evaluation
Zle
Ze (s) = . (7.26)
M 2 (D)
Summary
The generalized results above are summarized in Table 7.2. Those results hold for
CCM-operated converters, and the special-case impedances can be found by looking
up the canonical model parameters in a table such as Table 6.2, where we have defined
1
Zce (s) ≡ (7.27)
sCe
Zle (s) ≡ sLe . (7.28)
Table 7.2: Generalized Input Filter Design Constraints for Single-Converter Systems
Special- Impedance Generalized Transfer

case Value Function
open-
Zle +R||Zce (s)
loop ZD (s) M (D)2
All
−e(s)
null- ZN (s) j(s)
Gvd (s)
Zle
condition Ze (s) M (D)2
Ze (s)
Zg (s) ∞ Gvg (s)
It is noteworthy that substituting the generalized canonical model parameters

from Table 6.2 into our generalized special-case impedances in Table 7.2, and replacing
V /I with R, one arrives at the special-case impedance entries in Table 7.1 for the less
general case having a load R taken from reference [14].
266
Systems
7.2 Multi-converter Systems: The 2EET for Mul-

tiple Input Filter Evaluation
“Although it would be unlikely that one would want to modify a transfer function
to account simultaneously for two previously unrecognized extra elements, there is
considerable potential advantage to be obtained from a Low-Entropy Expression for
a transfer function in which the influences of two designated elements are directly
exposed, in terms of their [driving point impedances].”
– R.D. Middlebrook, The Two Extra Element Theorem [152]
In this section we extend the application of the extra element theorem to account
simultaneously for two added input filters in a multi-converter, multi-source power
system. The extended version of the EET is the 2EET, which will be reviewed first
before deriving the special-case impedances needed in the correction factors for some
key multi-converter transfer functions.
7.2.1 The 2EET
In [152], Middlebrook presents the two extra element theorem (2EET), the principle
result of which is the correction factor for the ith transfer function:
Z1 Z2 (i) Z1 Z2
1+ (i) + (i) + KN (i) (i)
ZN1 |Z =0 ZN2 |Z =0 ZN1 |Z ZN2 |Z =0
CF (i) = 2 1
(i)
2 =0 1
, (7.29)
Z1 Z2 Z1 Z2
1+ (i) + (i) + KD (i) (i)
ZD1 |Z =0 ZD2 |Z =0 ZD1 |Z =0 ZD2 |Z =0
2 1 2 1
where Z1 and Z2 are the output impedances of the first and second input filters
respectively. The subscripts N and D historically represent “numerator” and “de-
nominator” [14]. In the expression shown in (7.29), impedances with an N subscript
are the null-condition impedances while those with a D subscript are the open-loop
impedances. The interaction parameters can be written (they each have two possible
267
7.2. Multi-converter Systems: The 2EET for Multiple Input Filter Evaluation
forms) [152]:
(i) (i)
(i) ZN 1 |Z2 =0 ZN 2 |Z1 =0
KN = (i)
= (i)
(7.30)
ZN 1 |Z2 =∞ ZN 2 |Z1 =∞
(i) (i)
(i) ZD1 |Z2 =0 ZD2 |Z1 =0
KD = (i)
= (i)
, (7.31)
ZD1 |Z2 =∞ ZD2 |Z1 =∞
For the ith open-loop transfer function, there are four special-case impedances
shown explicitly in the expression for the corresponding correction factor (7.29):
(i) (i) (i) (i)
ZN 1 |Z2 =0 , ZN 2 |Z1 =0 , ZD1 |Z2 =0 , and ZD2 |Z1 =0 . Additionally, two more special-case
(i) (i)
impedances are required to calculate the interaction parameters, KN and KD as
shown in equations (7.31).
7.2.2 Modified Converter Transfer Functions in Multi-Converter

Systems
In analogy to the EET for single converter systems, the converter transfer functions
may be corrected by multiplying the converter transfer function by the corresponding
correction factor. Those converter transfer functions that are “in the loop” will carry
the effect of the correction factor to the loop transfer functions and may impact the
stability of the closed-loop system. Some examples of the computations for those
correction factors will be presented at the end of this section.
7.2.3 Modified Feedback Control in Multi-Converter Sys-

tems
Also in analogy to the EET for single converter systems, the closed-loop transfer
functions may be modified upon addition of an input filter by inserting the corrected
converter transfer functions into the feedback system.
268
Systems
7.2.4 Practical Interpretations and Impedance Inequalities
In analogy to the impedance inequalities from (7.8) and (7.9), the expression for the
correction factor in (7.29) or (7.77) suggests that the ith open-loop converter transfer
function will not be impacted significantly if the following impedance inequalities
are met. Recall that meeting these impedance qualities may be sufficient but not
necessary to preserve stability of an otherwise stable regulated power system.
(i)
|Z1 | << | ZN 1 |Z2 =0 | (7.32)
(i)
|Z2 | << | ZN 2 |Z1 =0 | (7.33)
(i)
|Z1 | << | ZD1 |Z2 =0 | (7.34)
(i)
|Z2 | << | ZD2 |Z1 =0 | (7.35)
7.2.5 Example: Correction Factors for v̂/dˆ1, v̂/dˆ2, îo1 /dˆ1, and
îo1 /dˆ2 in a Hybrid Power System
This section derives the special-case impedances needed to find the correction factors
for some of the key converter transfer functions from Chapter 7. Figure 7-4 demon-
strates the addition of input filters to the linearized model of a feedback regulated
multi-converter, multi-source system.
The circuit used for analysis in this section is shown in Figure 7-5. The indepen-
dent inputs in that system include the duty ratios for the two converters, dˆ1 (s) and
dˆ2 (s), as well as their (Thevenin) input voltages, v̂gth1 (s) and v̂gth2 (s). It should be
understood, before proceeding, that deactivating one of the duty ratio signals shorts
ˆ source and opens the corresponding j d(s)
the corresponding ed(s) ˆ source in that con-
verter model. In analyzing each transfer function, defined by an independent input

and a corresponding output, all other independent inputs are deactivated resulting
in a circuit that is a simplified version of the one in Figure 7-5. Here we consider the
converter transfer functions v̂/dˆ1 , v̂/dˆ2 , îo1 /dˆ1 , and îo1 /dˆ2 .
The following quantities are defined. The impedance ZL is all of the impedance
that shunts the output node, ZL ≡ R||Zce1||Zce2 and the effective converter output
269
îin1
Fuel Cell Zf c (s) Input Filter 1 e1 (s)d̂1 1 : M1 (D1 ) îo1
+
−
Lf 1 Le1
v̂f c
+
− j1 (s)d̂1 Ce1
Cf 1
d̂1 (s) H1 (s)
+
v̂ref 1 (s)
FM 1 Gc1 (s) Σ
-
îin2
Battery Zbatt (s) Input Filter 2 e2 (s)d̂2 1 : M2 (D2 ) îo2

+
−
Lf 2 +
Le2 î
v̂batt
+
− j2 (s)d̂2 Ce2 v̂(s) R
Cf 2
-
d̂2 (s) H2 (s)
+
v̂ref 2 (s)
FM 2 Gc2 (s) Σ
-
Figure 7-4: Multiple input filters added to a dual voltage-regulated power system.
impedances are Ze1 ≡ Zle1 ||Zce1 and Ze2 ≡ Zle2 ||Zce2, where Zce1,2 ≡ 1/sCe1,2 and
Zle1,2 ≡ sLe1,2 .
Correction Factor for v̂/dˆ1
Designating v̂/dˆ1 as the 1st transfer function, the superscripts for the six special-case
impedances are all (1). The other independent inputs, dˆ2 (s), v̂gth1 (s) and v̂gth2 (s), are
all deactivated leading to some simplification of the circuit in Figure 7-5.
(1)
The first special-case impedance, ZN 1 |Z2 =0 , is the null-condition impedance at the
first extra element port with the second extra element port shorted. Because it is
a null-condition impedance, analysis of the circuit should address the fact that the
independent input in this transfer function, dˆ1 , will be directed such that the output
voltage, v̂, is nulled. With this condition, and with the other independent inputs
deactivated, the second inductor voltage is zero, v̂le2 = 0, so the current through that
270
Systems
Zin1 (s)
e1 (s)dˆ1 (s) 1 : M (D1 ) îo1
+
−
Le1
+ j1 (s)dˆ1 (s) Ce1

− v̂gth1 (s)
Zin2 (s)
e2 (s)dˆ2 (s) 1 : M (D2 ) îo2
+
−
+
Le2 î
+ j2 (s)dˆ2 (s) Ce2 v̂(s) R

− v̂gth2 (s)
-
Figure 7-5: The circuit used for calculating the special-case impedances for the 2EET
correction factors.
inductor is zero, île2 = 0. Since the output voltage is nulled, v̂ = 0, the load current
is also zero, î = 0, and by KCL the inductor current of the first converter must then
be zero, île1 = 0. There is no current flowing through the first inductor so the voltage
drop across it is zero, v̂le1 = 0, and, by KVL, the voltage across the first secondary
and therefore its primary is zero, v̂pri1 = 0. Therefore, the voltage across the extra
element port is simply v̂in = −e1 dˆ1 (s) and the current through the extra element port
must be îin = j1 dˆ1 (s) so that their ratio - the impedance seen at the extra element
port - is
(1) e1
ZN 1 |Z2 =0 = − . (7.36)
j1
(1)
The second special-case impedance, ZN 2 |Z1 =0 , is the null-condition impedance at
the second extra element port with the first extra element port shorted. Solving the
271
circuit in Figure 7-5 leads to the following two constraints:
îin = île2 M2 (7.37)

v̂le2 île2 Zle2
v̂in = = . (7.38)
M2 M2
Dividing these two constraints leads directly to a statement of the impedance seen at
the second extra element port:
(1) Zle2
ZN 2 |Z1 =0 = . (7.39)
M22
(1)
The third special-case impedance, ZD1 |Z2 =0 , is the open-loop impedance at the
first extra element port with the second extra element port shorted. Now the in-
dependent input in the transfer function of interest is deactivated leaving all of the
independent inputs deactivated. Solving the circuit in Figure 7-5 among these con-
ditions leads to four constraints:
îin = M1 île1 (7.40)

v̂ Zle2 + ZL
île1 = (7.41)
ZL Zle2
vsec
ˆ
v̂in = (7.42)
M1
v̂ (ZL ||Zle2 + Zle1)
v̂sec = . (7.43)
ZL ||Zle2
Combining the first two constraints and combining the last two constraints leads to
v̂ Zle2 + ZL
îin = M1 (7.44)
R Zle2
1 ZL ||Zle2 + Zle1
v̂in = v̂ . (7.45)
M1 ZL ||Zle2
Dividing the two leads to the special-case impedance
(1) Zle1 + ZL ||Zle2

ZD1 |Z2 =0 = . (7.46)
M12
272
Systems
The fourth special-case impedance can be taken from the third from symmetry argu-
ments:
ZD2 |Z1 =0 = . (7.47)
M22
The remaining two special-case impedances are needed to determine the inter-
action parameters in the correction factor. Note that from (7.31), there is some
redundancy in the choice of these final special-case impedances. Here we derive,
(1) (1) (1)
ZN 1 |Z2 =∞ and ZD1 |Z2 =∞ . The fifth special-case impedance, ZN 1 |Z2 =∞ , is the null-
condition impedance at the first extra element port with the second extra element
port open-circuited. Because the second port is open-circuited, the current through
the second primary must be zero, îpri2 = 0, and so must the current through the
second inductor, île2 = 0. Since the output voltage is nulled, v̂ = 0, the load current
is also zero, î = 0, and by KCL the inductor current of the first converter must then
be zero, île1 = 0. Then, there is no current flowing through the first inductor so its
voltage drop is zero, v̂le1 = 0 so that by KVL, the voltage across the first secondary
and therefore its primary is zero, v̂pri1 = 0. Therefore, the voltage across the extra
element port is simply v̂in = −e1 dˆ1 (s) and the current through the extra element port
must be îin = j1 dˆ1 (s) so that their ratio - the impedance seen at the extra element
port - is
(1) e1
ZN 1 |Z2 =∞ = − . (7.48)
j1
This result is identical to the result for the first special-case impedance. This fact
leads to a numerator interaction parameter of unity and an interesting simplification
of the resulting correction factor.
(1)
The sixth and final special-case impedance, ZD1 |Z2 =∞ , is the open-loop impedance
at the first extra element port with the second extra element port open-circuited.
Because the second port is open-circuited, the current through the second primary
must be zero, îpri2 = 0, and so must the current through the second inductor, île2 = 0.
Then, the current through the first inductor becomes
v̂sec1
île1 = . (7.49)
ZL + Zle1
273
The input voltage and current are
v̂sec1
v̂in = (7.50)
M1
v̂sec1
îin = M1 île1 = M1 . (7.51)
ZL + Zle1
Dividing the two leads to the special-case impedance
(1) ZL + Zle1
ZD1 |Z2 =∞ = . (7.52)
M12
The special case impedances for calculating the correction factor of the open-loop
transfer function v̂/dˆ1 derived above are summarized here:
(1) −e1 (s)

ZN 1 |Z2 =0 = (7.53)
j1 (s)
(1) Zle2
ZN 2 |Z1 =0 = 2 (7.54)
M2 (D2 )
ZD1 |Z2 =0 = (7.55)
M12 (D1 )
ZD2 |Z1 =0 = , (7.56)
M22 (D2 )
The additional special-case impedances required to calculate the interaction param-

(1) (1)
eters, KN and KD , are
(1) −e1 (s)

ZN 1 |Z2 =∞ = (7.57)
j1 (s)
(1) ZL + Zle1
ZD1 |Z2 =∞ = . (7.58)
M12 (D1 )
Correction Factor for v̂/dˆ2
Designating v̂/dˆ2 as the 2nd transfer function, the superscripts for the six special-case
The special case impedance for calculating the correction factor of the second
274
Systems
open-loop transfer function of interest, v̂/dˆ2 , can be similarly derived or inferred from
the correction factor for the first by symmetry arguments. This leads to:
(2) Zle1
ZN 1 |Z2 =0 = (7.59)
M12 (D1 )
(2) −e2 (s)
ZN 2 |Z1 =0 = (7.60)
j2 (s)
ZD1 |Z2 =0 = (7.61)
M12 (D1 )
ZD2 |Z1 =0 = (7.62)
M22 (D2 )
and the additional special-case impedances required to calculate the interaction pa-
(2) (2)
rameters, KN and KD , are
(2) −e2 (s)

ZN 2 |Z1 =∞ = (7.63)
j2 (s)
(2) ZL + Zle2
ZD2 |Z1 =∞ = . (7.64)
M22 (D2 )
Correction Factor for îo1 /dˆ1
Similar calculations lead to the special-case impedances for correcting the converter
transfer functions from the duty ratios to the first converter’s output current. The
derivations can be found in Appendix B.3. The special case impedances for calculat-
ing the correction factor of the open-loop transfer function îo1 /dˆ1 derived above are
summarized here:
(3) −e1 (s)

ZN 1 |Z2 =0 = (7.65)
j1 (s)

Zce2 +Zle2
R Zce2
+ Zle2
(3)
ZN 2 |Z1 =0 = (7.66)
M22 (D2 )
ZD1 |Z2 =0 = (7.67)
M12 (D1 )
ZD2 |Z1 =0 = , (7.68)
M22 (D2 )
275
where ZL is the total impedance shunting the converter outputs, i.e. ZL = R||1/(s(C1+
C2 )), in Figure 7-4. The additional special-case impedances required to calculate the
(1) (1)
interaction parameters, KN and KD , are
(3) −e1 (s)

ZN 1 |Z2 =∞ = (7.69)
j1 (s)
(3) ZL + Zle1
ZD1 |Z2 =∞ = . (7.70)
M12 (D1 )
Correction Factor for îo1 /dˆ2
The special case impedances for calculating the correction factor of the open-loop
transfer function îo1 /dˆ2 are derived in Appendix B.4. The results are summarized
here:
(4) Zce1 + Zle1

ZN 1 |Z2 =0 = (7.71)
M12 (D1 )
(4) −e2 (s)
ZN 2 |Z1 =0 = (7.72)
j2 (s)
ZD1 |Z2 =0 = (7.73)
M12 (D1 )
ZD2 |Z1 =0 = , (7.74)
M22 (D2 )
where ZL is the total impedance shunting the converter outputs, i.e. ZL = R||1/(s(C1+
C2 )), in Figure 7-4. The additional special-case impedances required to calculate the
(1) (1)
interaction parameters, KN and KD , are
(4) Zce1 + Zle1

ZN 1 |Z2 =∞ = (7.75)
M12 (D1 )
(4) ZL + Zle1
ZD1 |Z2 =∞ = . (7.76)
M12 (D1 )
Discussion
Note that from the results above, the “numerator interaction parameter” equals one
(i)
(KN = 1) for each of the transfer functions. This fact, which is characteristic of
the hybrid power system in Figure 7-5, simplifies the numerical computation of the
276
Systems
correction factors, CF (i) , because, in that case, the numerator is exactly factorable
as follows:

Z1 Z2
1+ (i) 1+ (i)
ZN1 |Z =0 ZN2 |Z =0
CF (i) = 2
(i)
1
. (7.77)
Z1 Z2 Z1 Z2
1+ (i) + (i) + KD (i) (i)
ZD1 |Z =0 ZD2 |Z =0 ZD1 |Z =0 ZD2 |Z =0
2 1 2 1
7.3 Numerical Computation of High Order Ratio-

nal Polynomials
The transfer functions and correction factors in Chapters 6 and 7 lead to high order
rational polynomials in many practical cases. The numerical computation of those
rationals requires some care. It is helpful and sometimes necessary to compute inter-
mediate numerical values in order to overcome the limits of finite precision computa-
tion. The final numerical value may be computed by forming linear combinations of
the intermediate values according to the form of the correction factor. This technique
is not unlike the cascade implementation for FIR filter design to limit the noisy effects
of finite precision in digital signal processing. Below is an example computation of
a closed loop transfer function in Matlabr . In the style of the analysis here, the
transfer function is left in terms of impedances. The needed impedances are defined
as transfer functions at the beginning of the computation. This eliminates the need
to write the transfer function down explicitly in terms of element values. Interme-
diate numerical values are computed using the freqresp() function and evaluating
the intermediate transfer functions across the desired frequency vector. The result is
always a vector of complex numbers and must be treated with vector arithmetic.
iin1overiload.m
This function returns magnitude and phase vectors for the closed-loop transfer func-

îin1
tion î for the master-slave current-voltage regulated power system. This is
load CL
an example transfer function computation demonstrating the approach to computing
numerical values for high order rational polynomials. This example also demonstrates
277
7.3. Numerical Computation of High Order Rational Polynomials
how Matlabr can be allowed to perform mathematical formulations of transfer func-

tions in a quasi-symbolic way by using the dummy transfer function s to automatically
convert impedances to transfer functions.
function [ mag , p h a s e ] = i i n 1 o v e r i l o a d (M1, M2, e1 , e2 , j 1 , j 2 , Le1 , Le2 , ESRle1 , . . .
ESRle2 , Ce1 , Ce2 , ESRce1 , ESRce2 , Fm1 , Fm2 , Gc1 , Gc2 , H1 , H2 , R, R sen se , eval vector );
s = tf ( ’s ’ );
z l e 1 = ESRle1+s ∗ Le1 ;
z c e 1 = ESRce1 +1/( s ∗Ce1 ) ;
z c e 2 = ESRce2 +1/( s ∗Ce2 ) ;
z e 1 = 1∗ z l e 1 ∗ z c e 1 / ( z l e 1+z c e 1 ) ;
z e 2 = z l e 2 ∗ z c e 2 / ( z l e 2+z c e 2 ) ;
z c = z c e 1 ∗ z c e 2 / ( z c e 1+z c e 2 ) ;
z l = z c ∗R/ ( z c+R ) ;
z l p z l e 1 = ( z l ∗ z l e 1 / ( z l+z l e 1 ) ) ;
lambda1 = f r e q r e s p ( z l p z l e 2 , e v a l v e c t o r ) . / f r e q r e s p ( z l e 1+z l p z l e 2 , e v a l v e c t o r ) ;
lambda2 = f r e q r e s p ( z l p z l e 1 , e v a l v e c t o r ) . / f r e q r e s p ( z l e 2+z l p z l e 1 , e v a l v e c t o r ) ;
F1 = f r e q r e s p ( t f (Fm1∗Gc1∗H1∗ R sen se ) , e v a l v e c t o r ) ;
F2 = f r e q r e s p ( t f (Fm2∗Gc2∗H2 ) , e v a l v e c t o r ) ;
v o v e r i l o a d o l = − f r e q r e s p ( z e 1 ∗ ze2 , e v a l v e c t o r ) . / f r e q r e s p ( z e 1+z e 2+z e 1 ∗ z e 2 /R , e v a l v e c t o r ) ;

i o 1 o v e r i l o a d o l = f r e q r e s p ( ze2 , e v a l v e c t o r ) . / f r e q r e s p ( z e 1+z e 2+z e 1 ∗ z e 2 /R, e v a l v e c t o r ) ;
i o 1 o v e r d 2 = −lambda2 . ∗ f r e q r e s p ( e2 ∗M2/ ze1 , e v a l v e c t o r ) ;
i o 2 o v e r d 1 = −lambda1 . ∗ f r e q r e s p ( e1 ∗M1/ ze2 , e v a l v e c t o r ) ;
i o 1 o v e r d 1 = f r e q r e s p ( e1 ∗M1/ z l e 1 , e v a l v e c t o r )−lambda1 . ∗ f r e q r e s p ( e1 ∗M1/ ze1 , e v a l v e c t o r ) ;
i o 2 o v e r d 2 = f r e q r e s p ( e2 ∗M2/ z l e 2 , e v a l v e c t o r )−lambda2 . ∗ f r e q r e s p ( e2 ∗M2/ ze2 , e v a l v e c t o r ) ;
v o v e r d 1 = lambda1 . ∗ f r e q r e s p ( t f ( e1 ∗M1) , e v a l v e c t o r ) ;
v o v e r d 2 = lambda2 . ∗ f r e q r e s p ( t f ( e2 ∗M2) , e v a l v e c t o r ) ;
d 1 o v e r i l o a d = ( ( ( F1 . ∗ F2 . ∗ v o v e r i l o a d o l . ∗ i o 1 o v e r d 2 ) . / ( f r e q r e s p ( t f ( 1 ) , e v a l v e c t o r ) . . .
+F2 . ∗ v o v e r d 2 )) −F1 . ∗ i o 1 o v e r i l o a d o l ) . / ( ( f r e q r e s p ( t f ( 1 ) , e v a l v e c t o r ) + . . .
F1 . ∗ i o 1 o v e r d 1 ) . ∗ ( f r e q r e s p ( t f ( 1 ) , e v a l v e c t o r ) −(F1 . ∗ F2 . ∗ v o v e r d 1 . ∗ i o 1 o v e r d 2 ) . . .
. ∗ ( f r e q r e s p ( t f ( 1 ) , e v a l v e c t o r )+F1 . ∗ i o 1 o v e r d 1 ) . / ( f r e q r e s p ( t f ( 1 ) , e v a l v e c t o r )+F2 . ∗ v o v e r d 2 ) ) ) ;
d 2 o v e r i l o a d = −F2 . ∗ ( d 1 o v e r i l o a d . ∗ v o v e r d 1+v o v e r i l o a d o l ) . / ( f r e q r e s p ( t f ( 1 ) , e v a l v e c t o r ) . . .
+F2 . ∗ v o v e r d 2 ) ;
i o 1 o v e r i l o a d c l = ( f r e q r e s p (M1/ z l e 1 , e v a l v e c t o r )−lambda1 . / . . .
f r e q r e s p ( ze1 , e v a l v e c t o r ) ) . ∗ f r e q r e s p ( t f ( e1 ) , e v a l v e c t o r ) . ∗ d 1 o v e r i l o a d − . . .
lambda2 . ∗ d 2 o v e r i l o a d . ∗ f r e q r e s p (M2∗ e2 / ze1 , e v a l v e c t o r ) ;
v o v e r i l o a d c l = lambda1 . ∗ d 1 o v e r i l o a d . ∗ f r e q r e s p ( t f ( e1 ∗M1) , e v a l v e c t o r ) + . . .
lambda2 . ∗ d 2 o v e r i l o a d . ∗ f r e q r e s p ( t f ( e2 ∗M2) , e v a l v e c t o r ) ;
r esult = freqresp ( tf ( j1 ) , eval vector ).∗ d1overiload +...

f r e q r e s p ( t f (M1) , e v a l v e c t o r ) . ∗ i o 1 o v e r i l o a d c l + . . .
f r e q r e s p ( t f (M1) , e v a l v e c t o r ) . ∗ v o v e r i l o a d c l . / f r e q r e s p ( z c e 1 , e v a l v e c t o r ) ;
%% R e s u l t s
mag = 20∗ l o g 1 0 ( ab s ( r e s u l t ( : ) ) ) ;
p h a s e = 180/ p i ∗ ( unwrap ( a n g l e ( r e s u l t ( : ) ) ) ) ;
end
278
Chapter 8
Design Example 1: Run-time

Integral Diagnostics of a Grid-Tied
Fuel Cell
In this example, we present the performance of a multi-converter system with integral

EIS functionality for a stationary (grid-tied) application. The load power in this
example is relatively fixed. A dual voltage-regulated system with an auxiliary small-
signal control input provides the needed functionality. In this example, the power
system was built using off-the-shelf switching sections.
For experimentation, a 5 kW Siemens fuel cell stack was available through a
collaboration with Montana State University. This chapter begins with a description
of the fuel cell technology and the configuration of the experimental fuel cell. Two
system identification techniques used in the evaluation of the experimental data are
discussed. The power electronic system is presented along with design considerations
and the resulting performance. Impedance data collected from the experiments using
the multi-converter power system agrees well with impedance data collected using an
exogenous signal source.
In our SOFC stack, and in many similar fuel cell applications, it is neither feasible
nor desirable to remove the stack from service for the purpose of connecting impedance
spectroscopy instrumentation. However, in principle, it is not necessary to remove the
279
8.1. Fuel Cell Overview
load provided that a sufficiently rich test signal can be introduced in addition to the
load, as in [153]. This work demonstrates the use of power electronics to impose a test
signal while delivering power to a load. This characterization consists of calculations
of whole stack impedance spectroscopy and time-domain model parameters, using
both the switching waveform, or “ripple”, of the power electronics connected to the
stack and an exogenous excitation. This method requires only instrumentation at
the stack electrical terminals, and could be integrated with the controls of existing
power electronics to provide non-invasive, low cost stack prognostics. The underlying
motivation of this work, not directly addressed here, is that we may ultimately be
able to improve reliability and mitigate materials challenges through controls at the
electrical terminals that are richly informed of the state of the stack.
8.1 Fuel Cell Overview
− Vcell +
2e− 2− 2e−
O
H
2 .5 O
2
H 2O O2
H2
porous dense porous

anode electrolyte cathode
Ni−YSZ YSZ LSM
Figure 8-1: Conceptual diagram of SOFC energy conversion.
280
8. Design Example 1: Run-time Integral Diagnostics of a Grid-Tied Fuel Cell
Figure 8-1 is a conceptual illustration of the energy conversion mechanism in a

solid oxide fuel cell (SOFC). The cell comprises three layers. The cathode (right) is a
porous, electrically conductive material. Molecular oxygen is reduced to oxygen ions
in the cathode, with electrons supplied by the external circuit. These oxygen ions
move readily from the cathode through a dense electrolyte, which is ion-conducting
but is an electronic insulator. At appropriate temperatures, typically in the vicinity
of 750◦ C, the electrolyte becomes conductive to oxygen by means of oxygen vacancies
in the lattice structure of the material. The anode layer is another porous, electri-
cally conductive cermet material. Oxygen ions arriving from the electrolyte serve
to oxidize fuel and release their electrons to the external circuit. Typical materials
for the cathode/electrolyte/anode structure include lanthanum strontium manganate
(LSM), ytria stabilized zirconia (YSZ), and nickel/YSZ cermet, respectively. While
the overall reaction in 8-1 shows hydrogen as a fuel and water as a product, a basic
advantage of SOFC technology is that the electrolyte is an oxygen ion conductor.
This allows the use of fuels containing carbon, as opposed to hydrogen-conducting
fuel cell technologies.
Figure 8-2 shows a photograph of the actual stack used for testing in this work.
The stack is a 5 kW nominal, Fuel Cell Technologies / Siemens Alpha-8 tubular solid
oxide fuel cell using city natural gas as a fuel. The vents at the top are for intake and
exhaust, and this particular unit was also configured with a recuperator that could be
used to heat water for a combined heat and power application. This unit is designed
for three-phase grid-tie operation. However, for purposes of this study we were able
to access and connect power electronics to the terminals of the stack and monitor the
response of the stack to test signals imposed by those power electronics.
8.1.1 Fuel Cell Impedance Spectroscopy
Electrochemical impedance spectroscopy models the AC electrical terminal response

of a fuel cell (or other electrochemical system) in the vicinity of an operating point
281
Figure 8-2: A 5 kW Siemens / Fuel Cell Technology stack used for testing.
as a linear impedance Z(jω). In particular, for cell voltage and current
vc (t) = Vo + v(t) (8.1)
ic (t) = I0 + i(t), (8.2)
at a DC operating point V0 , I0 , the impedance captures the frequency domain rela-

tionship between the small signal quantities v(t), i(t). Use of this model presumes
that the cell responds linearly over the range of excitation in the vicinity of the bias
point, i.e. that excitation at a single frequency produces a response at that frequency.
Impedance spectroscopy results are generally presented using a Nyquist plot show-
ing real and complex parts of the impedance with frequency as an implicit argument.
An electrochemist can recognize the shapes characteristic of processes in the Nyquist
diagram [147]. Practitioners often extend this non-parametric analysis by fitting
lumped-parameter circuit models, in the frequency domain, and in some cases asso-
282
ciate physical processes with individual circuit elements. In [148], a parameterized

impedance spectroscopy model is used to synthesize an equivalent circuit of an SOFC.
Other examples include the analysis of a PEM cell in [149] and the application to an
SOFC cell in [148]. Frequencies of 0.01Hz to 1MHz are generally used for studying
SOFC systems [142]. For a survey of impedance spectroscopy in fuel cells, see [150].
Under sufficiently rich excitation, an estimate Ẑ(jω) of the impedance response
can be extracted from the terminal voltage and current of a cell. In particular, an
impedance estimate is
V̂c (jω)
Ẑ(jω) = , |ω| > 0, (8.3)
Iˆc (jω)
where V̂c (jω) and Iˆc (jω) are estimates of the spectral content of the electrical terminal
responses vc (t) and ic (t). The process of estimating spectral content of signals using
sampled data and discrete-time Fourier transform techniques, including windowing
and other considerations, is reviewed in [154] among others. The excitation ic (t)
imposed at the electrical terminals must be broadly exciting, in the sense of having
significant power at frequencies where it is desired to have a good estimate of Z(jω).
If Iˆc (jω) at some frequency is small or dominated by noise, the variance in Ẑ(jω) can
be large. In practice, we avoid this by not evaluating Z(jω) for frequencies where the
signal content in the Ic (jω) is small in comparison to a threshold.
8.1.2 Parametric Modeling and Identification
In addition to impedance spectroscopy, it is sometimes useful to model fuel cell re-

sponses using a parameterized model, often in the form of a differential equation that
represents specific physical processes. For example, Hall [155] develops a transient
model of a tubular SOFC including electrochemical, thermal, and mass flow elements.
Wang et al. [156] develop a dynamic model for a proton exchange membrane fuel cell
using electrical circuit elements, and Pasricha et al. [157] provide a dynamic electrical
terminal model of a proton exchange membrane fuel cell. A challenge in developing
parametric, physically-baed models of fuel cells is to restrict the phenomena in the
model to those which are well supported by the observations.
283
With preliminary, non-parametric observations in mind, we propose a very simple

three-parameter model of the stack, i.e.
v(t) = Voc − Ri(t) − Ls i(t), (8.4)
where v(t) is the stack voltage, i(t) is the stack current, Voc is the open circuit stack
d
voltage, R is a resistance, L is a inductance, and s is the dt
operator.
The parameters of (8.4) are conveniently estimated using the operator substitution
technique in [154]. The low-pass filter operator
1
λ= . (8.5)
1 + sτ
can be manipulated to isolate s, i.e.
1−λ
s= . (8.6)
λτ
Substituting s into (8.4) and rearranging so λ appears in the numerator provides
λτ Voc − τ λi(t)R + (λ − 1)i(t)L = τ λv(t). (8.7)
This is appealing because λτ , λi(t), and λv(t) can be evaluated using a discrete-time
implementation of λ applied to the data. These quantities can be arranged in a least-
squares tableau to obtain estimates for the parameters Voc , R, and L. Setting λτ Voc
to the final value, we form the following equations
   
τ −τ λi[1] (λ − 1)i[1]   τ λv[1]
  V  
   oc   
τ −τ λi[2] (λ − 1)i[2]     τ λv[2] 
  R  =   (8.8)
 .. .. ..     .. 
. . .   . 
  L  
τ −τ λi[n] (λ − 1)i[n] τ λv[n]
to estimate the parameters of (8.4).
284
8.2 Dual Voltage Regulated Power System Archi-

tecture
A simplified connection diagram for the EIS-capable multi-converter power system
is shown in Figure 8-3(a). The multi-converter power system was built from off-
r
the-shelf buck converters, SynQor part number PQ48120HTA14NKF. The current
share pins on the two converters were connected so that they shared load current at
startup. The trim pins on the two converters were adjusted after startup so that the
current share control was defeated leaving two voltage regulated converters 1 . The
EIS control signal was superposed on the voltage reference for the fuel cell converter.
1
This was confirmed by SynQor Applications Engineering.
285
8.2. Dual Voltage Regulated Power System Architecture
Fuel Cell VEIS

If c
Zf c Lf 1 v̂
Vin+ EISin Vo+
Vf c + Cf 1
− Buck
Vin− Vo−
R
Lf 2
Vin+ Vo+
Vbatt Cf 2 Buck
Vin− Vo−
(a) A simplified connection diagram of the hybrid system built from off-the-shelf compo-
nents.
Fuel Cell
If c VEIS
Zf c Lf 1 v̂
Vf c + Cf 1
−
R
Lf 2
Vbatt Cf 2
(b) Desired small-signal current paths for EIS excitation signals.
Figure 8-3: A hybrid power system with EIS functionality built from off-the-shelf
components.
286
Conceptually, the hybrid system enables run-time fuel cell diagnostics by provid-
ing a means for exciting the fuel cell with a small-signal current originating at the
secondary source (the battery in this case), while the load current itself is largely
unaffected by the EIS measurement. The small-signal current paths corresponding to
this behavior are depicted in Figure 8-3(b).
Figure 8-4: An oscilloscope screen shot showing the battery and fuel cell currents
during run-time EIS (≈100 Hz). Top to bottom: load voltage (ch2), fuel cell current
(ch3),battery current (ch4), control signal (ch1).
Figures 8-5, 8-6, and 8-7 show calculated and simulated closed-loop transfer func-
tions for the multi-converter power system. The magnitude and phase plots of îo2 /îo1
in Figure 8-5, confirm our intuition that, at low frequency, the currents out of the
two converters are equal and opposite (small-signal currents flow out of one and into
the other). This behavior corresponds to the time-domain data shown in the scope
shot of Figure 8-4, taken from the experimental system of Figure 8-3.
Figures 8-6 and 8-7 show that the transconductance from the control voltage,
v̂ref 1 , to input current, îin1 , is large and the corresponding load voltage perturbation,
287
v̂, is small. This amounts to the desired characteristic of an EIS-capable hybrid power
system that the load voltage will be largely unaffected by the run-time EIS behavior.
288
i /i
o2 o1
−10
Calculated G = 1000
c
−20
Simulated G = 1000
c
Calculated G = 100
c
|io2/io1| (dB)
−30 Simulated G = 100

c
Calculated Gc = 10
−40 Simulated Gc = 10
Calculated Gc = 1
Simulated Gc = 1
−50
−60
1 2 3 4 5 6
10 10 10 10 10 10
Frequency (rad/sec)
(a) Magnitude
io2/io1
180
160
140
120
(deg)
100
o2 o1
∠ i /i
80 Calculated Gc = 1000
Simulated G = 1000
c
Simulated G = 100
c
Simulated Gc = 10
20 Calculated G = 1
c
Simulated Gc = 1
0
0 1 2 3 4 5 6
10 10 10 10 10 10 10
Frequency (rad/sec)
(b) Phase
Figure 8-5: io2 /io1 .
289
i /v
in1 ref1
120
100
80
|iin1/vref1| (dB)
60
Calculated Gc = 1000
40
Simulated Gc = 1000
Calculated Gc = 100
20 Simulated Gc = 100
Calculated Gc = 10
Simulated G = 10
c
0
Calculated Gc = 1
Simulated Gc = 1
−20
0 1 2 3 4 5 6
10 10 10 10 10 10 10
Frequency (rad/sec)
Figure 8-6: |iin1 /vref 1 |.
v/v
ref1
40
20
−20
|v/vref1| (dB)
−40
Calculated Gc = 1000
−60
Simulated G = 1000
c
Calculated Gc = 100
−80
Simulated Gc = 100
Calculated G = 10
−100 c
Simulated Gc = 10
−120 Calculated G = 1
c
Simulated Gc = 1
−140
0 1 2 3 4 5 6
10 10 10 10 10 10 10
Frequency (rad/sec)
Figure 8-7: |v/iref 1|.
290
8.3 Input Filter

The input filters in an EIS-capable hybrid power system may be designed to achieve
several goals simultaneously:
1. Attenuate converter switching ripple
2. Avoid converter instability
3. Pass or even amplify excitation signals
Goals 1) and 2) are typical. Goal 3) is unique to the EIS-capable multi-converter

system because the filter must be designed to allow excitation currents to flow from
the converter input to the terminals of the fuel cell up to a specified frequency.
Lf 1 Lf 3
Fuel Cell Cf 1 Converter

Output Cf 3 Cf 4 Input
RD1
External Components Internal Components
Figure 8-8: The input filter for the fuel cell converter.
For this example, we consider the input filter shown in Figure 8-8, which includes
both the internal input filter components provided on the off-the-shelf Buck converter
from Figure 8-3(a) as well as the external input filter components that we added, Lf 1 ,
Cf 1 and RD1 . The internal input filter components are:
Cf 3 = 8.8 µF (8.9)
Lf 3 = 2.2 µH (8.10)
Cf 4 = 26.4 µF. (8.11)
Having set the pass band and rollover frequencies, largely by choosing Lf 1 , the filter
291
8.3. Input Filter
Bode Plot for Filter Current Transfer Funtion

50
0
Magnitude (db)
−50
−100
−150
3 4 5 6
10 10 10 10
0
Phase (deg)
−180
−360
3 4 5 6
10 10 10 10
Frequency (Hz)
Figure 8-9: The current transfer function for the fuel-cell leg input filter
transfer function is shown in Figure 8-9. The damping leg formed by Cf 1 and RD1 in
Figure 8-8 is intended to limit the magnitude peaking in the output impedance of the
filter. However, as the impedance of the damping leg decreases it provides a shunt
path that diminishes the transmission of excitation currents to the fuel cell terminals.
Moreover, due to natural bandlimiting in the system, the designer may actually want
to exploit the resonance at the edge of the pass band in Figure 8-9 to achieve some
current amplification at that frequency. Both of these considerations qualitatively
lower-bound the damping resistor, RD1 , a constraint which directly contends with
the impedance inequalities in (7.32)-(7.35).
Figure 8-10 shows a magnitude plot of the special-case impedances for correcting
v̂/dˆ1 as well as the output impedances from the filters used in our system. Note that
the two resonances in Zo (solid line) correspond to the two resonances in the filter
transfer function of Figure 8-9. Because the impedance inequalities in (7.32)-(7.35)
292
are not strictly met, as is evidenced by the plot in Figure 8-10, we need to examine the
quantitative impact of the input filters on the converter open-loop transfer functions.
A plot of the correction factors, CF (i) , for the ith converter open-loop transfer function
from (7.29) is the most direct way of analyzing the effect of the input filters on system
stability.
Special−Case Impedances for correcting v/d1

100
ZN1|Z =0
2
80 ZN2|Z =0
1
ZD1|Z =0
60 2
ZD2|Z =0
1
40 Zo1,Zo2
20
|Z| (db)
−20
−40
−60
−80
−100
0 2 4 6 8
10 10 10 10 10
Figure 8-10: The special case impedances for correcting v̂/dˆ1 and the input filter
output impedances with system parameters: VF C = 28V, Vbatt = 48V, Vout =12V,
R = 2Ω, Le = 1µH, Ce = 1µF
Bode plots of the correction factors, CF (1) and CF (2) , for the converter open-
loop transfer functions, v̂/dˆ1 and v̂/dˆ2 respectively, are shown in Figure 8-11.2 The
correction factor, CF (2) , introduces a significant additional phase lag near 105 rps.
However, the phase lag will not degrade the phase margin unless that phase lag
occurs at the cross-over frequency of the entire regulator loop transfer function. In
some cases, i.e. when the impedance inequalities in (7.32)-(7.35) are grossly violated,
2
The simulated data overlayed in the plots of Figure 8-11 was extracted from LTSPICE by
comparing simulations of the open-loop transfer functions with and without the input filters in
place.
293
8.3. Input Filter
the correction factor will contribute phase lag for a wide band of frequencies likely
causing instability. Because the phase lag in this example is contributed for only
a narrow range of frequencies it is unlikely to cause instability. The values for the
external input filter components in this example were
Cf 1 = 100 µF (8.12)
RD1 = 10 Ω (8.13)
Lf 1 = 6 µH. (8.14)
These were also the values for the filters used in the system of Figure 8-3 represented
by Lf and Cf .
294
Extra Element Correction Factor CF1 for v/d1

20
Calculated
10 Simulated
|CF | (db)
0
1
−10
−20
0 2 4 6 8 10
10 10 10 10 10 10
150
Calculated
100 Simulated
∠ CF (deg)
50
1
−50
0 2 4 6 8 10
10 10 10 10 10 10
Frequency (rad/sec)
(a) CF (1)

20
Calculated
10 Simulated
|CF | (db)
0
2
−10
−20
0 2 4 6 8 10
10 10 10 10 10 10
50
0
∠ CF2 (deg)
Calculated
−50
Simulated
−100
−150
0 2 4 6 8 10
10 10 10 10 10 10
Frequency (rad/sec)
(b) CF (2)
Figure 8-11: Correction factors CF (1) and CF (2) with system parameters: VF C = 28V,
Vbatt = 48V, Vout =12V, R = 2Ω, Le = 1µH, Ce = 1µF
295

Figure 8-12 shows an overall schematic of the Siemens 5 kW stack, connections to
the built-in power electronics and storage, and the locations of our measurements.
Under steady-state operation, the unit is remotely configured to regulate current from
the stack. This power is then put on the grid through a three-phase inverter. The
stack current is measured using a Tektronix A6303 current probe, while the voltage
is measured using an isolated, differential Tektronix 5205 probe. Signals from both
probes are recorded using a National Instruments data acquisition system with a PXI-
5122 14-bit analog to digital converter. Sampling was conducted at a minimum of
2MS/s to avoid under-sampling issues. Figures 8-14(a) and 8-14(b) show typical data
collected from this test setup under steady state operating conditions. The current
and voltage levels in Figures 8-14(a) and 8-14(b), nominally 100A and 28V, were
typical of the stack load during testing.
RESISTIVE
LOAD
Modulation
TEKTRONIX
HP 6010A Secondary HYBRID Input
CFG250
POWER Source POWER
FUNCTION
SUPPLY Input SYSTEM
GENERATOR
Primary
Source
Input
i(t)
SOFC +
TEK
DC 48 V DC 3 Phase
v(t) BATTERY
A6303 Grid Tie
STACK - DC STACK
AC 3
Siemens
Stack Current Alpha 8
Command 5 kW Stack
TEK TM5003
POWER
SUPPLY /
AM5030
AMPLIFIER NI CPU
TEK 5205 TEK 1103 PXI 5122
100 MHz POWER
PROBE SUPPLY
Figure 8-12: Schematic illustration of stack, power electronics, and measurements.

Components within the dashed line are within the physical envelope of the Siemens
Alpha 8 unit.
296
8.5 Results
Figure 8-14 shows typical data collected from the test setup in Figure 8-12 with a
1 kHz exogenous excitation imposed by control of the test power electronics. The
triangular ripple current in 8-14 at roughly 12 kHz is due to the operation of the
front-end boost converter in the Siemens power management system. The current
and voltage levels in 8-14, nominally 90 A and 28 V, were typical of the stack load
during testing.
110
Measured Data
Parametric Model
105
100
95
i(t), A
90
85
80
75
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4
Time, ms
Figure 8-13: Measured and predicted stack current as a function of time.
Figure 8-15 shows Nyquist plots of the impedance Ẑ(jω) obtained from the re-
sponse of the stack to the built-in power electronics ripple and the power electronic
test signal. The plots were prepared according to the convention for electrochemical
impedance spectroscopy results. Figure 8-15(a) shows a plot representing impedances
for all frequencies with significant content. The discrete clusters correspond to har-
monics of the triangular boost-converter switching waveform, while the more contin-
uous low-frequency data shows the response to the test signal. As the frequency of
the harmonics increases, the amplitude decreases, and the variance in the impedance
estimate increases. Figure 8-15(b) is an expanded view of the low frequency portion
corresponding to the exogenous excitation. The arc shape of the curve in Figure 8-
297
8.5. Results
15(b) is consistent with the series connection of parallel RC elements often used in
equivalent circuit models of fuel cells.
105 29
100
28.5
95
28
v(t), V
i(t), A
90
27.5
85
27
80
75 26.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Time, ms Time, ms
(a) Stack current as a function of time. (b) Stack voltage as a function of time.
Figure 8-14: Stack current and voltage, measured as indicated in fig:hybridex1 8-

12. The triangle current waveform in 8-14(a) is due to the operation of the DC/DC
converter in the system. The corresponding voltage of the stack appears in 8-14(b).
Data corresponding to a 1 kHz power electronic excitation were used to identify the
parametric model in 8.1.2. The parameter estimates were Voc = 34.1V , R = 0.0690Ω,
and L = 0.43 µH. These results compare favorably to those in [153], where the
values for these parameters based on data taken months earlier were found to be
Voc = 34.7 V, R = 0.0677 Ω, and L = 0.471 µH. The decrease in voltage and
increase in resistance are likely due to the gradual degradation of stack performance
observed over this time period. The latest parameters were used for an output-error
prediction of the time-domain current waveform in response a 5.4 kHz excitation.
This cross-validation result is shown in 8-13.
298
−0.05
−Im{Z(ω)}, Ω
−0.1
−0.15
−0.2
0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1

Re{Z(ω)}, Ω
(a)
0.01
0.008
0.006
0.004
−Im{Z(ω)}, Ω
0.002
−0.002
−0.004
−0.006
−0.008
−0.01
0.06 0.065 0.07 0.075 0.08 0.085 0.09 0.095 0.1
Re{Z(ω)}, Ω
(b)
Figure 8-15: Whole stack impedance spectroscopy results. (a) Stack response to
ripple current and power electronic test signal. (b) Low-frequency portion of stack
response showing response to power electronic test signal.
299
8.5. Results
300
Chapter 9
Design Example 2: Run-time

Integral Diagnostics of a Fuel Cell
under Unmanned Aerial Vehicle
Load Profiles
This section presents a hybrid power system designed for integral fuel cell diagnos-
tics in applications having widely varying load power. The primary function of the
hybrid power system will be to provide a fixed fuel cell operating current with a
superposed frequency sweepable EIS signal despite varying load currents. As an il-
lustrative example, the integral diagnostic functionality of the hybrid power system
is demonstrated under simulated unmanned aerial vehicle (UAV) time-domain load
profiles. The underlying motivation to diagnose and even heal a damaged fuel cell
is demonstrated experimentally through intentional damaging followed by recovery
in conjunction with runtime impedance measurements that support predegradation,
postdegradation, and postrecovery conditions of the fuel cell.
301
9.1. Current-Voltage Regulated Power System Architecture
9.1 Current-Voltage Regulated Power System Ar-

chitecture
The system architecture is a master-slave current-voltage regulated hybrid power

system like the one analyzed in Section 6.7. Figure 9-1 shows a schematic depiction
of the hybrid power system and the basic elements of the feedback control. Figure
9-1(b) shows the small-signal current path for the EIS signal. The nominal system
parameters are shown in Table 9.1.
Table 9.1: Nominal fuel cell master-slave system parameters
Parameter Symbol Value

Fuel cell Voltage Vf c 12 V
Battery Voltage Vbatt 12 V
Fuel cell Current If c 4A
Battery Current Ibatt −2 A to +8 A
Buck switching freq. fsw 400 kHz
Buck switching devices Mi IRFB3607
In our experimental setup, the load is modeled as a time-varying current source.

The fuel cell is furnished by the current-regulated DC/DC converter so that the
fuel cell operating current may be fixed despite variations in the load current. The
battery is furnished by the voltage-regulated DC/DC converter so that it provides the
excess load current while constraining the load voltage. The excess load current may
be positive or negative so the voltage-regulated converter was designed to support
bidirectional current flow. Notably, when the excess load current is negative, the
battery is automatically recharged by the fuel cell.
The design of the buck converters and the feedback control is detailed here. The
feedback control circuitry was designed for good voltage and current regulation, wide
bandwidth to support the frequency sweepable EIS signal as well as the obvious need
for stable closed loop operation. A useful target for the fuel cell (FC) EIS signal
bandwidth is 1 kHz.
302
9. Design Example 2: Run-time Integral Diagnostics of a Fuel Cell under
Unmanned Aerial Vehicle Load Profiles
9.2 Feedback Compensation

In this hard-switched converter topology, there is a fundamental tradeoff among con-
verter efficiency and closed-loop bandwidth that is manifested in the choice of switch-
ing frequency. The requirement for good switching frequency attenuation in the loop
transfer functions contends directly with the requirement for wide loop bandwidth.
The feedback compensation strategy employs a lead compensator to improve the loop
bandwidth and an additional high frequency pole for added attenuation at the switch-
ing frequency. The location of the added high frequency pole was chosen to tradeoff
closed-loop stability (phase margin) for switching frequency attenuation. The loop
transfer functions in Figure 9-2 indicate the tradeoffs described above with reason-
able phase margin and loop bandwidths that ultimately support EIS excitation signals
having sufficient bandwidth.
303
replacemen
9.2. Feedback Compensation
Fuel Cell VEIS

If c îo1
Zf c Lf 1
Vin+ EISin Vo+
Vf c + Cf 1
− Buck
Vin− Vo−
Iload
Lf 2 v̂
Vin+ Vo+
Vbatt Cf 2 Buck
Vin− Vo−
(a) A simplified connection diagram of the hybrid system.
Fuel Cell
If c VEIS
Zf c Lf 1 îo1
Vf c + Cf 1
−
Iload
Lf 2 v̂
Vbatt Cf 2
(b) Desired small-signal current paths for EIS excitation signals.
Figure 9-1: A hybrid power system with EIS functionality built upon a Master-Slave
current-voltage regulated architecture.
304
Bode Diagram
100
50
Magnitude (dB)
−50
−100
0
−45
Phase (deg)
−90
−135
−180
1 2 3 4 5 6 7
10 10 10 10 10 10 10
Frequency (rad/sec)
(a) Current feedback loop
Bode Diagram
40
20
Magnitude (dB)
−20
−40
−60
−80
0
−45
Phase (deg)
−90
−135
−180
2 3 4 5 6 7
10 10 10 10 10 10
Frequency (rad/sec)
(b) Voltage feedback loop
Figure 9-2: Open-loop bode plots indicate tradeoffs among loop bandwidth, switching
frequency attenuation and stability.
305
9.3. Closed-Loop Responses
9.3 Closed-Loop Responses

The closed-loop response was simulated based on the analysis in Chapter 6. The key
closed-loop transfer functions are shown in Figure 9-3.
I /V I /V
in1 ref1 o1 ref1
40 50
20
0
| (db)
|io1/vref1| (db)
0
ref1
−50
|i /v
−20
in1
−100
−40
−60 −150
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
100 0
50 −50
∠ iin1/vref1 (deg)
∠ io1/vref1 (deg)
0 −100
−50 −150
−100 −200
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
Frequency (rad/sec) Frequency (rad/sec)
(a) Control voltage to fuel cell current (b) Control voltage to first converter’s output
current
V/V I /I
ref1 in1 load
50 20
0
0
| (db)
|v/vref1| (db)
−20
in1 load
−50
|i /i
−40
−100
−60
−150 −80
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
200 −150
100
∠ iin1/iload (deg)
∠ v/vref1 (deg)
−200
−250
−100
−200 −300
1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10
(c) Control voltage to load voltage (d) Load current to fuel cell current
Figure 9-3: Simulated closed-loop bode plots indicate suitable fuel cell excitation
current bandwidth, good load voltage regulation and good fuel cell current buffering.
Figure 9-3(a) shows the fuel cell current in response to the control voltage. It
shows a bandwidth that is sufficient for the target 1 kHz upper band limit on fuel
EIS currents. Figure 9-3(c) indicates a relatively small magnitude transfer function
from the control voltage to the load voltage. The response in Figures 9-3(a) and
9-3(c) confirm that the control signal needed to achieve suitable excitation currents
for the EIS measurements should lead to a relatively small disturbance of the load.
Finally, Figure 9-3(d) shows the fuel current response to load current perturbations.
306
The plot shows a significant attenuation at low frequency in this regard indicating
suitable buffering of the fuel cell current from the variations in the load current.
9.3.1 Low Frequency Fuel Cell Current Buffering
From the discussion in Section 6.7, the zero frequency closed-loop output impedance
of the current-regulated converter relies on series resistances. Figure 9-4 shows the
closed loop transfer function of the first converter’s input current to load current
perturbations having added 500 mΩ of series resistance to that converter’s output
inductor. The plots shows an added 20 db of attenuation at low frequency. However
the added resistance represents an extra 50 W of dissipation for 10 A of output
current. Clearly, if this method is used to improve current buffering, there will be a
tradeoff in efficiency, not to mention complexity in thermal management.
Iin1/Iload
20
0
| (db)
−20
in1 load
|i /i
−40
−60
−80
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
−100
−150
∠ iin1/iload (deg)
−200
−250
−300
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
Frequency (rad/sec)
Figure 9-4: Closed loop response from load current to fuel cell current with 500 mΩ
of extra inductor ESR.
307
9.4. Input Filter
9.4 Input Filter
Lin
Cd
ESRd Cin
Rd
Figure 9-5: The basic input filter topology
Having designed the converter to meet the dynamic requirements of the runtime
integral diagnostics, we add an input filter to attenuate switching frequency content
at the fuel cell and battery terminals. The evaluation of the chosen input filters for
regarding their impact on closed-loop stability was guided by the application of the
2EET detailed in Section 7.2. The filter was chosen not only to attenuate switching
ripple, but to pass the excitation signal among the stability guidelines imposed by
the 2EET.
308
Extra Element Correction Factor CF for v/d

1 1 Bode Diagram
0
50
−0.1
|CF1| (db)
Magnitude (dB)
−0.2
−50
−0.3
−0.4 −100
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
−150
1 0
Input Filter 1 TF
0.5 −45
Phase (deg)
∠ CF1 (deg)
0
−90
−0.5
−135
−1
−1.5 −180
1 2 3 4 5 6 7 8 9 2 4 6 8 10
10 10 10 10 10 10 10 10 10 10 10 10 10 10
(a) CF1 , Rd = 0 Ω (b) Input filter 1, Rd = 0 Ω

1 1 Bode Diagram
0.5
0
0
−0.5
|CF1| (db)
Magnitude (dB)
−1 −50
−1.5
−2
−100
−2.5
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
−150
10 0
Input Filter 1 TF
5 −45
Phase (deg)
∠ CF (deg)
0 −90
1
−5 −135
−10 −180
1 2 3 4 5 6 7 8 9 2 4 6 8 10
10 10 10 10 10 10 10 10 10 10 10 10 10 10
(c) CF1 , Rd = 0.5 Ω (d) Input filter 1, Rd = 0.5 Ω

1 1 Bode Diagram
2
0
0
−2
|CF | (db)
Magnitude (dB)
−4 −50
1
−6
−8
−100
−10
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
−150
40 0
Input Filter 1 TF
20 −45
Phase (deg)
∠ CF (deg)
0 −90
1
−20 −135
−40 −180
1 2 3 4 5 6 7 8 9 2 4 6 8 10
10 10 10 10 10 10 10 10 10 10 10 10 10 10
(e) CF1 , Rd = 2 Ω (f) Input filter 1, Rd = 2 Ω
Figure 9-6: The tradeoff between input filter negative phase contribution and band-
width
309
9.4. Input Filter
The basic input filter topology is shown in Figure 9-5. The filter elements Lin
and Cin are chosen for good attenuation at the switching frequency. The capacitor
Cd is chosen to be very large so that it represents a low impedance at frequencies
near the bandwidth imposed by Lin and Cin . The damping resistor, Rd , is chosen
to limit the peaking the output impedance of the input filter in order to satisfy the
impedance inequalities derived from the 2EET in Section 7.2. Decreasing the value
of Rd improves this effect. However, the value of Rd can be optimized to pass EIS
excitation signals. Figure 9-6 illustrates the tradeoff between the first converter’s
input filter bandwidth and the negative phase contribution for one of the correction
factors.
A compromise in the value of Rd was chosen for acceptable phase margin and op-
timized transmission of EIS signals to the fuel cell terminals. The input filter transfer
functions are shown in Figure 9-7. The corresponding extra-element correction factor
bode plots are shown in Figures 9-8 and 9-9. The input filter transfer function for
the fuel cell converter shows good transmission of the EIS signal while the correction
factors indicate acceptable maximum negative phase contributions. Note also that
the negative phase contributions indicated by the correction factors are narrowband.
That is, they will only impact the stability if the location of the negative phase con-
tribution is very close to the cross-over frequency of the corresponding loop transfer
function.
310
Bode Diagram
50
0
Magnitude (dB)
−50
−100
−150
0
Input Filter 1 TF
−45
Phase (deg)
−90
−135
−180
2 4 6 8 10
10 10 10 10 10
Frequency (rad/sec)
(a) Fuel Cell side Input Filter
Bode Diagram
50
0
Magnitude (dB)
−50
−100
−150
0
Input Filter 2 TF
−45
Phase (deg)
−90
−135
−180
2 4 6 8 10
10 10 10 10 10
Frequency (rad/sec)
(b) Battery side Input Filter
Figure 9-7: Input filter transfer functions
311
9.4. Input Filter

1 1
0.5
0
|CF1| (db)
−0.5
−1
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
2
∠ CF1 (deg)
−2
−4
−6
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
Frequency (rad/sec)
(a) CF1

0.6
0.4
|CF2| (db)
0.2
−0.2
−0.4
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
2
∠ CF2 (deg)
−2
−4
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
Frequency (rad/sec)
(b) CF2
Figure 9-8: Extra element correction factors for the voltage feedback loop
312
Extra Element Correction Factor CF for i /d

3 o1 1
0
−0.5
|CF3| (db)
−1
−1.5
−2
−2.5
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
5
∠ CF3 (deg)
0
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
Frequency (rad/sec)
(a) CF3
Extra Element Correction Factor CF4 for io1/d2

0
−0.5
|CF4| (db)
−1
−1.5
−2
−2.5
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
6
∠ CF4 (deg)
0
1 2 3 4 5 6 7 8 9
10 10 10 10 10 10 10 10 10
Frequency (rad/sec)
(b) CF4
Figure 9-9: Extra element correction factors for the current feedback loop
313
9.5. Implementation
9.5 Implementation
The implemented hybrid power system schematic is shown in Appendix B.1.2. The
switching sections are Buck converters using synchronous rectifiers to enable bidirec-
tional current flow. The MOSFETs were chosen to support an output current of 20 A
and an input voltage of 15 V. Light RC snubbers reduce losses resulting from ringing
drain-source ringing. The EIS control signal is ac-coupled into the fuel cell side con-
trol loop at vref ac . To accommodate the possibility of a negative fuel cell operating
current e.g. one that would be appropriate for a reversible fuel cell, an adjustable
offset is added to the fuel cell side output current measurement (“Negative output
current adjust”).
9.5.1 Gain-Lead Compensator-Subtractor
A single op-amp circuit serves as a lead compensator, gain and subtractor on the fuel
cell side. The additional high frequency pole is added by the simple RC low-pass filter
that follows the lead compensator. The lead compensator-gain-subtractor in Figure
9-10(a) has the transfer function
R1 1 + sC(R2 + R3 )
vo = (v1 − v2 ) . (9.1)
R3 1 + sCR2
A block diagram representation of the compensator circuit in the context of the

feedback control loop is shown in Figure 9-10(b).
9.6 Measured Step Responses
Step responses were taken from the implemented system most notably to verify closed-
loop stability. Figure 9-11 shows the step response from the first converter’s control
voltage to the first converter’s output current. The step response indicates suitable
phase margin for the current-feedback loop in agreement with the simulated loop
transfer function in Figure 9-2(a). The small-signal step response shows a 90% rise
314
R1
R3
V2 R2 C
−
Vo
R2 C
+
V1 R3
R1
(a) The gain-lead compensator-subtractor
Gain-Lead compensator-Subtractor
+
vref R1 1+sC(R2 +R3 ) HF
Σ R3 1+sCR2 Pole
−
H
(b) The gain-lead compensator-subtractor block diagram representation
Figure 9-10: The lead compensator subtractor and gain circuit
time of approximately 25 µs. From [92], this corresponds to a closed-loop bandwidth

for a second order system of approximately
2.2
ωh ≈ = 88 krps, (9.2)
tr
which is in good agreement with the simulated closed loop response in Figure 9-3(b).
From [92], because the current-control loop exhibits a phase margin of 45◦ , we expect
approximately a 20% overshoot in the small-signal step response also in agreement
with Figure 9-11(a).
Figure 9-12 shows the large and small step responses from the second converter’s
control voltage to the load voltage. The step responses indicate suitable phase margin
in agreement with the simulated loop transfer function in Figure 9-2(b) and good
315
9.6. Measured Step Responses
voltage regulation. The ripple visible on the small step response in Figure 9-12(a) is
converter ripple not an oscillation.
Figure 9-13 shows the step response from the load current to the first converter’s
input current (the fuel cell current). The low frequency behavior shows an attenua-
tion in agreement with the simulated low frequency behavior in Figure 9-3(d). The
high frequency magnitude response shown in Figure 9-3(d) peaks around 15 kHz cor-
responding to a timescale of about 100 µs. The step response in Figure 9-13 shows
a larger response on the timescale of about 100 µs in agreement with the simulated
frequency behavior.
316
(a) Small step
(b) Large step
Figure 9-11: First converter’s control voltage to first converter’s output current. Ch1:
v̂ref 1 , ch4: îo1
317
9.6. Measured Step Responses
(a) Small step
(b) Large step
Figure 9-12: Second converter’s control voltage to load voltage. Ch1: v̂ref 2 , ch2: v̂
318
(a) Small step
(b) Large step
Figure 9-13: Load current to first converter’s input current. Ch1: îload , ch4: îiin1
319
A connection diagram of the experimental setup is shown in Figure 9-14. The exper-
imental setup consists of the two-converter current-voltage regulated power system,
two power sources and an Agilent N3300A electronic load. The solid-oxide fuel cell
(SOFC) in this experiment was available through a collaboration with Montana State
University (MSU). The fuel cell power source consisted of a subsystem - an electroni-
cally simulated fuel cell stack - the reference simulator. This subsystem, shown on the
left side of Figure 9-14, will be described in Section 9.7.1. The second power source
was a bidirectional power source, either a lead-acid battery or a bipolar linear power
amplifier depending on the particular experiment.
VEIS
Fuel Cell Current Path
α kΩ Vstack+
1 kΩ FC
Load
Rsense
+
−
Vdd
−αVf c Vstack−
DC/DC 10 mΩ
0.1 Ω
Fuel Cell Vf c
−
+
−Vdd Vss,f c
Vdd
1 kΩ
Vbatt+
+
−
Batt.
Battery
−
Vdd
Vbatt−
DC/DC
+ 0.1 Ω
− 1 kΩ
+
−Vdd Vss,batt
1.16 Ω
1 kΩ
−Vdd Ref. Sim. Gnd Load Ret.

Vdd
− 0.1 Ω
1 kΩ
+
−Vdd
Vdd = 23 V
1 kΩ
α = 19
Vdd
− 0.1 Ω
1 kΩ
+
−Vdd
Figure 9-14: The experimental setup block diagram with the Montana State Univer-
sity fuel cell reference simulator.
A photograph of the full experimental setup is shown in Figure 9-15. The power
320
converters and the data acquisition inputs are shown on the left. The measurement,
signal generation and power supplies are shown in the middle of the photo. The fuel
cell reference simulator, fuel cell ovens, mass flow and temperature controllers, and
fuel bottles are shown on the right.
Figure 9-15: A photograph of the full experimental setup including the data acqui-
sition system, power converters, measurement and power supplies, and the fuel cell
setup.
Photographs of the full fuel cell setup are shown in Figures 9-16, 9-16 and 9-18.
Figure 9-16 shows the solid-oxide fuel cell ovens, the mass flow and temperature con-
trollers and the hydrogen and oxygen fuel bottles. The solid-oxide fuel cell ovens with
gas feed-throughs are shown in Figure 9-17. The ovens were heated to a temperature
of 750◦ C. Electrical terminal were available at the top and bottom of each oven. Fig-
ure 9-18 shows a closupe of the mass flow controllers that control the flow of fuel into
the ovens. The nominal fuel rates were 260 SCCM H2, 100 SCCM O2.
321
Figure 9-16: A photograph of the two solid-oxide fuel cell ovens, temperature control
units and mass flow controllers used in the integral diagnostics experiments.
322
Figure 9-17: A closeup photograph of the two solid-oxide fuel cell ovens, temperature
control units and mass flow controllers used in the integral diagnostics experiments.
Figure 9-18: A closeup photograph of the mass flow controllers used to control the
flow of Oxygen and Hydrogen into the solid-oxide fuel cell ovens.
323
Figures 9-19 and 9-20 show the power converter and data acquisition (DAQ)
system connections. The DAQ connections were buffered and low pass filtered. The
array of buffers and low-pass filters built for this purpose is shown on a breadboard
in Figure 9-20.
Figure 9-19: A photograph of the two-converter current-voltage regulated power sys-

tem connected to the data acquisition system in the fuel cell experimental setup.
324
Figure 9-20: A closeup photograph of the data acquisition system buffers and low
pass filters in the fuel cell experimental setup.
325
9.7.1 Reference Simulator
An independent research effort at MSU has led to the successful implementation of a

“Fuel Cell Reference Simulator.” The reference simulator allows for laboratory tests
of a simulated fuel cell stack having only one or two fuel cells. A schematic diagram
of the reference simulator in the context of the experimental setup is shown in Figure
9-14.
Figure 9-21: A closeup photograph of the reference simulator electronics in the fuel
cell experimental setup.
The reference simulator is intended to simulate a series connection (stack) based

on the behavior of only one fuel cell. The simulator measures the fuel cell output
voltage at Vf c and provides a gained and inverted (−α) version at the node labeled
Vstack− . The fuel cell voltage is itself included in the simulated stack voltage because
326
the total simulated stack voltage, Vstack+ − Vstack− , is
Vstack = Vf c − Vstack−
= Vf c + αVf c . (9.3)
The simulated stack voltage is therefore
Vstack = Vf c (1 + α) . (9.4)
The topology allows the load current to flow through the fuel cell itself. Because all
of the fuel cells in a stack would see the same current, the current through the single
fuel cell is equivalent to the simulated stack current. Therefore the terminals Vstack+
and Vstack− simulate a stack of 1 + α replicas of the fuel cell. Additional high power
op-amp gain stages are connected as slave devices to increase the current handling
capability of the reference simulator. Note that the reference simulator ground is
an intermediate reference that is distinct from the simulated stack reference. The
simulated stack reference is generally Vstack− and in this case is connected (through
the current sense resistor) to the load ground (“load return”).
The experimental data presented at the end of this section validates the practical
use of the hybrid power system for EIS of the fuel cell. It also validates the operation
of the reference simulator itself.
327
9.8. UAV Flight Plans
9.8 UAV Flight Plans

Electric flight data for an actual unmanned aerial vehicle was available through a
collaboration with the US Air Force. Data showing the total load current and the
UAV velocity time domain profiles (flight plans) are shown for three different flights in
Figure 9-22. The three different flight plans exhibit some notable and useful features
for the run time integral diagnostics experiments. Flight plan 1 exhibits a rapidly
and widely varying load current through the flight. Flight plan 2 is similar to flight
plan 1 but shows an intermediate landing and takeoff. Flight plan 3 exhibits a slowly
varying load current with one distinct abrupt feature near the middle of the flight.
Flight plan 3 is particularly useful because it can be used in a simple experiment to
determine the extent of the abrupt load transient effects on the EIS measurements.
Figure 9-22: Data for three different flight plans made available through a collabora-
tion with the USAF.
The oscilloscope traces in Figure 9-23 show time domain waveforms about 10
minutes long each corresponding to runtime EIS experiments for the three flight
plans. The channels in the traces are ch1: Battery voltage, ch2: Battery current,
ch3: Fuel cell voltage, ch4: Fuel cell current.
In the oscilloscope traces, the battery current varies widely throughout the flight
328
plan. When the load current is low, the battery current is actually negative indicating
that the battery is being recharged from the fuel cell. The battery voltage varies
somewhat due to its internal resistance as the battery current varies with the load.
Meanwhile, the fuel cell current (and voltage) are largely fixed at the desired operating
point with a superposed EIS signal. The traces clearly show the frequency-swept EIS
signal superposed on the fuel cell current and voltage and the battery current. To a
lesser extent the EIS signal is visible on the battery current signal.
Two EIS sweeps were performed for each iteration of flight plan 3. The two time
segments were chosen such that one occurs during a time when the load current is
slowly varying while the other includes one abrupt transient in the load current.
329
9.8. UAV Flight Plans
(a) Flight Plan 1
(b) Flight Plan 2
(c) Flight Plan 3
Figure 9-23: Oscilloscope traces showing EIS operation during flight plans: ch1:
Battery Voltage ch2: Battery Current ch3: Fuel Cell Voltage ch4: Fuel Cell Current
330
9.9 Empirically-based Frequency Precompensator

The fuel cell current during EIS sweeps is shown in Figure 9-24 for three different
cases. The first plot, in Figure 9-24(a) shows the fuel cell current when the fuel cell
in the reference simulator has been shorted. This is an indication of the ideal input
voltage source transfer function from the control voltage to the first converter’s input
current e.g. the bode plot in Figure 9-3(a). The data in Figure 9-24(a) confirms
the flatness of the passband shown in the simulated bode plot of Figure 9-3(a). The
bandlimiting shown during the high frequency portion of the EIS sweep (near 1 kHz)
is due to the first converter’s input filter transfer function whose bandwidth is roughly
1.5 kHz as shown in Figure 9-7(a). While this particular data is not well-representative
of small-signal behavior, the magnitude response is roughly in agreement with the
small-signal transfer function in Figure 9-3(a), given the control signal amplitude.
FC Current Fixed Load Shorted FC FC Current during EIS Flight Plan 3 without Precompensator
10 10
9 9
8 8
7 7
6 6
Current (A)
Current (A)
5 5
4 4
3 3
2 2
1 1
0 0
0 50 100 150 200 0 50 100 150 200
Time (sec) Time (sec)
(a) EIS sweep with FC Shorted: 500 mVp−p (b) Without Precompensator: 200 mVp−p from
control signal from EIS5 (no Flight Plan) EIS12 (Flight Plan 3)
Figure 9-24: FC currents during EIS sweeps 0.1 Hz to 1 kHz showing the need for
the frequency precompensator.
During experimentation, we observed the effect of the non-zero fuel cell impedance
on the closed loop transfer function from the control voltage, v̂ref 1 to the fuel cell cur-
rent, îf c . An example of this effect is indicated by the data in Figure 9-24(b). Because
the fuel cell output impedance is inductive, the excitation current transmission to the
fuel cell decreased in magnitude with frequency despite the relatively flat pass-band
indicated in the closed-loop transfer function of Figure 9-3(a). This added frequency
331
9.9. Empirically-based Frequency Precompensator
dependence constitutes a practical challenge for running frequency-swept EIS experi-

ments particularly if the control signal amplitude is fixed. A fixed amplitude control
signal leads to an excitation current that may be too small at high frequency or too
large at low frequency. If it is too small, the fuel cell current and voltage pertur-
bations may be below the noise floor of the measurement. If it is too large, the
small-signal assumptions collapse. To solve this problem, an empirically based prec-
ompensator was constructed to recover the flat pass-band that was initially expected.
The precompensator was connected in series with the control signal vref 1,ac in Figure
9-14.
332
R3 C R1
vin 15 V
−
R2 LM741
vo
+
(a) Schematic
(b) Photograph
Figure 9-25: The EIS control signal frequency precompensator constructed based on
observations of the inductive fuel cell source impedance effect on the transmission of
excitation currents to the fuel cell terminals.
333
9.9. Empirically-based Frequency Precompensator
The schematic of the precompensator is shown in Figure 9-25(a). The transfer

function of the precompensator is
vo R1 1 + sC(R2 + R3 )
= . (9.5)
vin R3 1 + sCR2
Based on the dynamics observed during experimentation the pole and zero were placed
at 50 Hz and 10 Hz respectively. The zero-frequency gain, R1 /R3 , was unity so R1 =
R3 . The values used for this design were R1 = 15 kΩ, R2 = 1 kΩ, R3 = 15 kΩ, and
C = 1 µF. Figure 9-26 shows the fuel cell current having added the precompensator.
With the precompensator, a fixed amplitude control signal leads to a relatively fixed
amplitude excitation current.
FC Current during EIS Flight Plan 3 with Precompensator

10
6
Current (A)
0
0 50 100 150 200
Time (sec)
Figure 9-26: With Precompensator: 50 mVp−p from EIS37 (Flight Plan 3)
334
9.10 Fuel Cell Impedance Results

Impedance measurements of the simulated fuel cell stack were taken among various
configurations and load profiles. The frequency range of the impedance measurement
was 0.1 Hz to 1 kHz. The fuel cell operating point was chosen based on its large signal
I − V characteristic. That operating point was a nominal fuel current of If c = 4 A.
Figure 9-27 shows the results from two control experiments. Figure 9-27(a) shows
a comparison of the impedance measured using the reference simulator first with the
fuel cell in place and second with the fuel cell shorted. The Nyquist plot indicates
that the added impedance from the reference simulator and interconnects is negligible
compared to the impedance contributed by the fuel cell.
Figure 9-27(b) shows the impedance measured for a known inductor. The in-
ductor was independently measured to have an inductance of 10.1 µH and a series
resistance of 4 mΩ measured at 100 Hz. The data in the plot shows the impedance
measured for the inductor with 1.5 µH and 15 mΩ of wire inductance and resistance.
The impedance is multiplied by a factor of 20 due to the working operation of the ref-
erence simulator. According to Figure 9-27(b), the inductance at the high frequency
operating point (893 Hz in this case) was
1 1
L ≈1.264 × × = 11.26 µH. (9.6)
2π × 893Hz 20
335
9.10. Fuel Cell Impedance Results
0.15
EIS 5 − Ref Sim Only
EIS 10 − Single Cell Sim Stack
0.1
Negative Imag Impedance (Ω)
0.05
−0.05
−0.1
−0.15
−0.2
0 0.5 1 1.5
Real Impedance (Ω)
(a) Control Expt 1: EIS with FC compared to EIS with the FC shorted
−0.2
−0.4
−0.6
−0.8
−1
X: 0.367
−1.2 Y: −1.264
EIS6 − Inductor Sim Stack
0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45

(b) Control Expt 2: EIS with known inductor
Figure 9-27: Control experiments
336
Figure 9-28 shows the impedance measured for the simulated fuel cell stack with a
fixed load (no flight plan). Also shown is a multiplied impedance measurement for the
single fuel cell. The comparison shows that the simulated output closely represents a
simulation of a stack of fuel cell replicas.
0.15
0.1
0.05
−0.05
EIS 10 − 19.95 x Fuel Cell
EIS 10 − Simulated Stack
−0.1
−0.15
−0.2
0.9 1 1.1 1.2 1.3 1.4 1.5
Figure 9-28: EIS with a fixed load (no flight plan), If c = 4 A
Figure 9-29 shows the comparison of impedance measured at the single cell level
for the two distinct time segments in flight plan 3 at the same fuel cell operating point.
Time segment 1 includes a single abrupt transient in the load while time segment 2
does not. The two impedance measurements are very closely matched suggesting
that the effect of abrupt transients in the load current have a small impact on the
impedance measurement. This is a natural outcome of the hybrid power system
design. Specifically, the current-regulated fuel cell side converter buffers the fuel cell
current from load current transients.
Figure 9-30 shows impedance data measured during the three flight plans. In
the Nqyuist plots the impedance of the simulated stack is overlayed on a multiplied
impedance measured for the single cell. The close matching between the two indicates
337
−3
x 10
8
4
−2
−4
−6
EIS 12 − Flight Plan 3, Time Segment 1
EIS 12 − Flight Plan 3, Time Segment 2
−8
0.045 0.05 0.055 0.06 0.065 0.07 0.075
Figure 9-29: Single Cell EIS during Flight Plan 3 for two different time segments,
If c = 4 A
that the reference simulator accurately simulates a stack of replica fuel cells. The
experiments indicated in the Figure for flight plans 1 and 3 are shown for two slightly
different fuel cell operating points. The data in Figure 9-30(a) was taken for If c = 4.4
A while the data in Figure 9-30(c) was taken for If c = 4 A.
Comparing Figure 9-30(c) to 9-28 indicates good matching between the data taken
with a fixed load and data taken during the flight plan. Comparing Figure 9-30(a)
to Figure 9-30(c) indicates a decrease in the impedance magnitude at higher fuel cell
current.
338
0.15
0.1

0.05
EIS 13 − 19.95 x Fuel Cell Sweep 1

−0.05 EIS 13 − Simulated Stack Sweep 1
−0.1
−0.15
−0.2
0.9 1 1.1 1.2 1.3 1.4 1.5
(a) EIS during Flight Plan 1, If c = 4.4 A
0.15
0.1
0.05
−0.05
−0.1 EIS 14 − 19.95 x Fuel Cell

EIS 14 − Simulated Stack
−0.15
−0.2
0.9 1 1.1 1.2 1.3 1.4 1.5 1.6
(b) EIS during Flight Plan 2, If c = 4.3 A
0.15
0.1
0.05
EIS 12 − 19.95 x Fuel Cell Sweep 1a

−0.05 EIS 12 − Simulated Stack Sweep 1a
−0.1
−0.15
−0.2
0.8 0.9 1 1.1 1.2 1.3 1.4 1.5
(c) EIS during Flight Plan 3, If c = 4 A
Figure 9-30: Nyquist plots showing measured impedances during flight plans.
339
Figure 9-31 shows a comparison of impedance data for a second fuel cell that was
intentionally damaged and then allowed to recover. The cell was degraded for about
11 hours while holding the cell voltage between 50 mV and 30 mV. The fuel cell
current was initially 15 A, but by morning had decreased to 14 A. Fuel rates were
260 SCCM H2, 100 SCCM O2. The cell temperature was 750◦ C.
−3
x 10
12
10
8
EIS 17 − Fuel Cell 2 Pre−degrade

−2 EIS 19 − Fuel Cell 2 Post−degrade
EIS 30 − Fuel Cell 2 Post−recover
−4
0.03 0.035 0.04 0.045 0.05 0.055 0.06 0.065 0.07 0.075
Figure 9-31: Pre-degrade, If c = 4.1 A, degraded If c = 4 A, post-recovery, If c = 4 A
The three plots correspond to pre-degradation, post-degradation, and post-recovery.

The data suggest that the capacitive impedance increases when the fuel cell has been
damaged and decreases when the fuel cell is recovered. The low-frequency resistance
(real-axis intercept) also decreases when the fuel cell is recovered. Additionally, the
data suggest that the fuel cell was somewhat unhealthy prior to degradation.
9.10.1 Discussion
The three states of the fuel cell in Figure 9-31 may be related to changes in the
physical properties of the cell modeled by the incomplete circuit model shown in
340
Figure 9-32 taken from reference [15]. Key elements not included in the circuit model
are the series inductance leading to the crossing of the real axis in all of the Nyquist
plots and additional RC combinations to describe multiple humps in those plots.
In the circuit model of Figure 9-32, C is the equivalent capacitance of double-layer
charge effect, and Ract,cell , Rohm,cell , and Rconc,cell are equivalent resistances of the
activation, ohmic and concentration voltage drops. At low currents, when chemical
reactions start to take place inside the SOFC, a voltage loss (drop) results due to an
activation energy barrier that must be overcome. This is the activation drop [15].
The ohmic resistance of the SOFC consists mainly of the resistance of the electrodes,
electrolyte, and the interconnection between cells [15]. The concentration drop is a
more subtle effect described in detail in reference [15]. “In a SOFC, the two electrodes
are separated by the electrolyte, and two boundary layers are formed, that is, anode-
electrolyte layer and electrolyte-cathode layer. Due to the polarization effect, these
layers, known as electrochemical double-layer charge effect, can store electrical energy
and behave like a super-capacitor [15].”
The low frequency resistance (the real-axis intercept at the right side of the
Nyquist plot), would correspond to the series combination of Rohm,cell + Ract,cell +
Rconc,cell because, at low-frequency, the capacitor, C, can be represented as an open-
circuit. The high frequency resistance (the real-axis intercept at the left side of the
Nyquist plot), would correspond to the resistance, Rohm,cell because, at high frequency,
the capacitor, C, can be represented as a short-circuit. Therefore, the decrease in
the low-frequency real-axis intercept indicated by the cell impedance post-recovery
would correspond to a decrease in the series combination, Rohm,cell +Ract,cell +Rconc,cell.
Meanwhile the high-frequency resistance, Rohm,cell , has not changed post-recovery, so
we may conclude that the series combination Ract,cell +Rconc,cell has decreased in value.
341
Figure 9-32: A circuit model of a solid-oxide fuel cell taken from reference [15].
342
Chapter 10
Per-Panel Photovoltaic Energy

Extraction with Switched-capacitor
Multilevel Output DC/DC
Converters
10.1 Introduction
The total installed cost ($/W) and total cost of ownership ($/Wh) have been well-
studied as the key metrics controlling the grid penetration of solar power [158–161].
Among the factors impacting installed cost (per Watt) are power converter cost and
total (tracking × conversion) efficiency, both of which share strong relations to con-
verter and system complexity. A critical factor impacting the cost of ownership is
the lifetime of the power converter (and implied replacement costs). Cost-effective
solutions for solar energy extraction should address system cost and complexity, con-
version and tracking efficiencies and converter lifetime simultaneously.
The need for suitable tracking efficiency is normally addressed with a maximum
power point tracking (MPPT) algorithm embedded in the control of the converter
or inverter [24, 162]. In the important grid-tied case, 120 Hz power ripple at the
343
10.1. Introduction
panel terminals negatively impacts the MPPT function, but this may be addressed
by augmenting the source with a large electrolytic capacitor [16, 17, 163–169]. How-
ever, the limited lifetime of electrolytic capacitors contends directly with the long-life
characteristic of cost-effective solar conversion. To reconcile this, [158] proposed the
“ripple port” inverter, which still directly interfaces the PV cell, but directs the 120
Hz ripple power to a transformer coupled ripple port and away from the cell.
There is a growing need to implement per-panel MPPT to contend with varying
light levels, temperatures, panel ages, etc. across physically widespread solar arrays
[16, 17, 163–169]. Figures 10-1 and 10-2 illustrate the problem.
P V3 P V3
P V2 P V2
Iload Iload
P V1 P V1
cloud
(a) Simple series string (b) Simple series string, one panel 75 %
shaded
Figure 10-1: Simple series connections of PV panels, unshaded and partially shaded
For a series connection of three identical PV panels as in Figure 10-1(a), a simple

string current sweep leads to perfect tracking efficiency, ηp , for a particular value
of string current. However, when one panel is shaded as in Figure 10-1(b), the
same simple global maximum power point tracking approach can lead to significantly
degraded tracking efficiency. Figure 10-2 shows a comparison between the three panel
tracking efficiency, defined as the ratio of the power extracted from the string to the
maximum achievable extracted power, between the unshaded and partially shaded
cases. When on panel is 75% shaded (its maximum power is one-fourth that of the
other panels), the string tracking efficiency with this simple global maximum power
344
10. Per-Panel Photovoltaic Energy Extraction with Switched-capacitor Multilevel
Output DC/DC Converters
tracking scheme is reduced to less than 40%.
Tracking Efficiency vs. Output Current

100
Simple series string
90 One panel 75 % shaded
80
70
60
η (%)
50
p
40
30
20
10
0
0 0.5 1 1.5 2
I (A)
o
Figure 10-2: 3 panel system tracking efficiencies showing the effect of partial shading
on a series string with an oversimplified global maximum power tracking approach.
The solution to the partial shading problem is per-panel MPPT. A series connec-
tion of PV panels becomes a series connection of converters processing power from
their respective panels. A simplified block diagram illustrating this concept is shown
in Figure 10-3.
There are advantages of a DC/DC module integrated converter (MIC) + central
DC/AC approach over a DC/AC MIC approach. These include the availability of
a single DC bus for an entire array and intermediate power ripple filtering, as well
as added degrees of freedom for MPPT control [16, 17, 170]. With per-panel MPPT,
global tracking efficiency can be significantly improved over simple series or parallel
connections of those panels (see Section 10.2.4), but the installation of per-panel con-
verters impacts the important cost metrics above. Converter lifetime and replacement
costs become even more critical with per-panel conversion.
Many inductor-based converters and inverters have been proposed as module inte-
345
10.1. Introduction
P V3 DC/DC3
P V2 DC/DC2 Iload
P V1 DC/DC1
Figure 10-3: A series connection of PV panels becomes a series connection of con-

verters processing power from their respective panels.
grated converter (MIC) topologies, but they require magnetic components to be either
purchased per-panel or to be integrated into the converter IC [16,17,163–165]. Multi-
level converters have been proposed as per-panel DC/AC converters, but they suffer
from either 120 Hz power ripple at the panel terminals or the need for cost-prohibitive
and / or electrolytic energy storage [166–169].
10.1.1 System Overview
The system level approach in this thesis is illustrated by the DC linearized circuit
model in Figure 10-4. This system shares some key features with other systems
employing DC/DC MICs and a central inverter but differs in at least one key way
[16]. The DC/DC MICs typically operate with local autonomous MPPT control. In
the system proposed here, the responsibility of MPPT is shared among the DC/DC
modules and the central inverter. As a result, the required complexity of the DC/DC
MICs is simplified. Significantly, the system can be implemented with switched-
capacitor multilevel DC/DC converters and a central ripple-port inverter. Per-panel
346
IinN 1 : QN
RoN Io
PVN
Iin2 1 : Q2
Current
PV2 Ro2 Controlled
Ripple port
Inverter Grid
Iin1 1 : Q1
PV1 Ro1
Figure 10-4: A DC linearized model with an N-panel PV string illustrates the system-
level approach. The ideal transformers model the function of the DC/DC MICs.
magnetics are eliminated as are electrolytic capacitors if desired. Any magnetics that
are required for the ripple port inverter need only be purchased once per string. The
DC/DC module conversion ratios are selectable, but discrete. A central question that
is addressed in this work concerns the tracking efficiency that is possible with this
system.
10.1.2 Switched-capacitor Benefits
Switched-capacitor converters achieve current and voltage conversion without mag-

netic energy storage. Figure 10-5 shows the cost and volume per energy storage
(µJ) for a sample of discrete capacitors and inductors suitable for power applications.
These data imply a-priori expected cost and volume benefits of switched-capacitor
converters when compared to inductor-based converters. A detailed discussion can
be found in [171].
Having eliminated magnetic energy storage, discrete implementations can benefit
from the higher energy density and lower specific cost of capacitive energy storage.
There is also a potential to achieve higher levels of integration. Benefits of integration
include reduced parasitic inductances leading to reduced switching loss as well as the
347
10.1. Introduction
Volume and Cost per Energy Capacity: Inductors vs. Capacitors

2
10
1
10
Specific Volume (mm3 / µJ)
0
10
−1
Capacitors
10 Inductors
−2
10
−3
10
−5 −4 −3 −2 −1 0 1
10 10 10 10 10 10 10
Specific Cost ($ / µJ)
Figure 10-5: Specific cost and volume: Discrete inductors (10 µH- 1 mH/100 mA-1 A)
and capacitors (Ceramic and Film 1-10 µF/10-100 V) sampled from Digikey. Energy
was calculated as 12 CV 2 or 21 LI 2 for maximum rated voltages and currents.
cost benefits yielded by batch fabrication techniques for integrated circuits and co-
packaged systems [172].
10.1.3 Total Efficiency
Total efficiency is central to the design and evaluation of the systems in this work.
Here we define total efficiency, η, as the product of tracking efficiency, ηp , and con-
version efficiency, ηc :
η = ηp × ηc . (10.1)
Figure 10-6 depicts a sample of reported tracking and conversion efficiencies in MPPT
algorithms and DC/DC MICs respectively. The two ranges are multiplied yielding a
third range corresponding to total efficiency, η.
348
replacemen
ηp :
87.5% 93.6% 99.6%
ηc :
93% 95.5% 98%
η:
81.4% 89.5% 97.6%
Figure 10-6: A literature survey of total energy extraction efficiency, DC/DC MICs:
[16–23] and MPPT algorithms: [23–28]
10.2 Maximum Power Point Tracking
Maximum power point tracking in the system of Figure 10-4 is simplified by the input
current control of the central inverter and the series connection of the MICs. The
selectable conversion ratios, Qi , allow the DC/DC modules to track local MPP’s as
the string current varies. The central inverter tracks the global MPP by adjusting its
input current.
The run-time global MPPT can be implemented by exploiting time-scale separa-
tion. Here, we take the local MPPT control to operate fast, and the global MPPT
control to operate relatively slowly. Specifically, on the time-scale of local MPPT
control, the string current, Io , may be taken to be static or “quasi-static.” Because
the maximum power point of each panel is defined by a unique maximum power cur-
rent, Imp,i , the quasi-static string current naturally decouples MPPT control among
the modules.
10.2.1 PV Model
Before discussing system performance further, we establish a model of the photo-

voltaic panel and its parameters. The circuit model used here (Figure 10-7) is common
in the literature, e.g. [170]. Given the parameters quoted in a typical datasheet, open-
349
10.2. Maximum Power Point Tracking
Rs Iin
Iph Dp Rp Vin
−
Figure 10-7: PV circuit model
circuit voltage, Voc , and short-circuit current, Isc , and the maximum power voltage
and current, Vmp , and Imp , analysis of the circuit in Figure 10-7 yields the following
results. The circuit model diode forward voltage is
Vdp = Voc (10.2)
and the resistive elements are, respectively,
Voc − Vmp
Rs = (10.3)
Imp
Isc Rs − Voc
Rp = , (10.4)
Imp − Isc
while the photovoltaic current is
Vdp
Iph = Imp + . (10.5)
Rp
In Figure 10-7, when Iin < Imp , the diode, Dp , is forward-biased and it is reverse-
biased otherwise. The resulting panel voltages are
Vin = Vdp − Iin Rs , Iin < Imp
Vin = Rp Iph − (Rs + Rp )Iin , Iin ≥ Imp (10.6)
and the panel power is simply

Pin = Iin Vin . (10.7)
350
For simplicity, the rest of this work assumes the following nominal datasheet values
adapted from a Mitsubishi PV-MF170EB4 [173]. The maximum power (MP) current
and voltage are
Imp = 6.93 A
Vmp = 24.6 V.
The short-circuit current is
Isc = 7.38 A,
and the open-circuit voltage is
Voc = 29 V. (10.8)
These nominal values correspond to the following PV circuit model parameters: Vdp =
29 V, Rs = 0.635 Ω, Rp = 54 Ω, and Iph = 7.47 A. The Mitsubishi PV-MF170EB4
includes 50 cells connected in series and it is 1.58 m x 0.8 m in dimension.
10.2.2 Local Maximum Power Point Tracking
Local MPPT control consists of matching the string current, to the panel’s own Imp,i ’s.
From Figure 10-4, the ith panel current is
Iin,i = Qi Io . (10.9)
Given a quasi-static string current, Io , the modules each choose a Qi to maximize

their panel power. This maximization step can be performed a number of ways. For
instance, the modules may estimate their Imp,i ’s via short-circuit current measure-
ments. References [174–178] discuss MPPT control by this method. A perturb and
observe step may be necessary for good accuracy following the initial Imp guess. In our
system, having discrete conversion ratios, a maximum of two additional observations
351
should be required to determine the actual optimal conversion ratio.

In the simulations that follow, the local algorithm for choosing conversion ratios
was implemented as follows. Given Imp,i either by the short-circuit method described
above or otherwise, the modules attempt to minimize the error |Iin,i − Imp,i |. This
minimization is constrained according to the nonlinear behavior of the PV indicated
in Figure 10-7. Combining equations (10.6) and (10.7), the panel power for the ith
panel can be written:
2
Pin,i = Iin,i Vdp,i − Iin,i Rs,i , Iin,i < Imp,i
2
Pin,i = Iin,i Rp,i Iph,i − (Rs,i + Rp,i )Iin,i , Iin,i ≥ Imp,i . (10.10)
Taking the derivative of (10.10) with respect to Iin yields
∂Pin,i
= Vdp,i − 2Iin,i Rs,i , Iin,i < Imp,i
∂Iin,i
∂Pin,i
= Rp,i Iph,i − 2(Rs,i + Rp,i )Iin,i , Iin,i ≥ Imp,i . (10.11)
∂Iin,i
The term, −2(Rs,i + Rp,i )Iin,i , in the derivative typically leads to a steep decrease
in panel power for Iin ≥ Imp . Absolute errors |Iin,i − Imp,i | impact the panel power
less for Iin,i < Imp,i . Accordingly, the algorithm adopted in this work attempts to
minimize the error |Iin,i − Imp,i | with the following order of preference:
1. Iin,i = Imp,i
2. Iin,i < Imp,i
3. Iin,i > Imp,i .
In the examples presented here, the DC/DC modules each continuously attempt to
match the string current to their own MP currents according to the above algorithm.
Generally, the modules can choose from a set of integral conversion ratios [0,1...Qmax ].
The Q = 0 module configuration is important for good average tracking efficiency. It
is equivalent to the pass-through mode discussed in reference [16] and represents the
352
option for a panel to “sit out” when its maximum power is so low that including it
in the string would have a negative impact on the global MPP.
10.2.3 Global Maximum Power Point Tracking
The string inverter can track the global MPP by adjusting its input current. Figure
10-8 depicts an example of the tracking efficiency achieved as Io is swept, while
the DC/DC modules adjust their conversion ratios. For this example, and for the
rest of this section, tracking efficiency is considered in an otherwise lossless system
(ηc = 100%). The Io sweeps, like the one depicted in Figure 10-8, may be performed
Max Power η = 97.3312%
p
100
90
80
70
60
η (%)
50
p
40
30
20
10
0
0 1 2 3 4 5 6 7 8
Io (A)
Figure 10-8: A single Io sweep: 3 panels, Qavail = [0,1,2,3,4], Imp,vec = [6.898, 4.503,
4.878] A, ∆Io = 1 mA
on a scheduled basis. Alternatively, Io may be varied continuously according to a

particular runtime MPPT algorithm. Section 10.7 presents a simulation of a likely
input current-controlled inverter.
Figure 10-9 shows one cycle of a hypothetical timing diagram that may be used
to quantify the tradeoffs in implementing the global MPPT algorithm. The timing
353
Time Cycle time
Φ1 Φ2 Φ3 Φ4 Φ5
Settle 1 Meas. Io Set Qi Settle 2 Meas. Po Step Io
∆Io
Step Io Uncertainty Uncertainty
Figure 10-9: A hypothetical MPPT timing diagram for one inverter input current
step.
diagram consists of six distinct phases. Additionally, because the local and global
MPPT are asynchronous, i.e. the local MPPT algorithm phases 2-5 are cycled con-
tinuously at each panel, there is timing uncertainty equal to the total amount of time
occupied by phases 2 through 5. In other words, the central inverter must wait a
total of twice the time that it takes a panel to cycle through phases 2 through 5 in
order to guarantee that all of those phases have been completed. The distinct phases
are indicated by the following operations:
Φ1 [Settle 1]: Larger of inverter input current settling time following inverter
command step and module current settling time following a step in load current
Φ2 [Meas. Io ]: Modules measure panel Io
Φ3 [Set Qi ]: Modules select and set conversion ratios, Qi
Φ4 [Settle 2]: Larger of inverter input current settling time following DC bus
voltage step and module current settling time following a change in conversion
ratio
Φ5 [Meas. Po ]: Inverter measures its own input power
Here we have assumed that the first choice of conversion ratio is sufficient and that no
perturb and observe step is required. The validity of this assumption depends on the
accuracy of the short-circuit current maximum power point estimation method. We
also assume that the short-circuit current measurement takes place approximately
once per inverter input current sweep, not continuously. This assumption is impor-
tant because the short-circuit current measurement disrupts the module currents and
therefore necessitates a period of settling time following that measurement.
354
From the timing diagram, there will be tradeoffs among inverter input current
step resolution, sweep width, and sweep time. Instantaneous tracking efficiency will
improve with inverter input current step resolution, but time average tracking effi-
ciency will suffer as the inverter input current sweep time increases. If the sweep is to
take place on a scheduled basis, e.g. every 5 seconds, then the sweep time represents
a down-time. The fractional down-time decreases as the sweep time decreases and
the period between sweeps increases. However, tracking efficiency may also suffer if
the period between sweeps becomes long enough that transient phenomena in lighting
levels, temperature changes etc. are not sufficiently captured.
Here we consider an example. Simulated prototype data in Sections 10.4 and
10.7 will indicate that the cycle time will be dominated by the settling time in the
module currents following a step change in the inverter input current or a change in
conversion ratio. Here we assume that a change in conversion ratio takes place rarely
during the sweep so the cycle time is dominated by the former.
The simulated data in Section 10.4 indicates a settling time of 250 µs in the
module currents following a step change in the load current. The corresponding cycle
time will be approximately 500 µs due to the uncertainty consideration. This cycle
time accommodates 2000 inverter current steps per second. If we assume that the
inverter will sweep from zero to the short-circuit current of the panels (7.38 A in this
example) in 20 mA steps, then a full sweep will take approximately 185 ms. For a
sweep period of 5 seconds, this sweep time represents a fractional downtime of 3.7 %.
The sweep resolution in this example is the same as the sweep resolution used in the
statistical performance evaluations later in this chapter.
10.2.4 Statistical Performance Evaluation
A statistical performance evaluation method was adopted to account for variations in

panel MPP’s. The relevant Matlabr code can be found in Appendix C. Monte Carlo
simulations were performed by allowing Matlabr to choose random (normalized)
Imp,i ’s for each panel. For each simulation, the string current, Io , was swept as
in Figure 10-8 and the maximum efficiencies (tracking, converter, and total) were
355
recorded. Repeating this many times and averaging the results yielded a prediction
of average performance. An example output plot is shown in Figure 10-10. The
Tracking Efficiency Across Number of Panels and Number of Available Levels
100
95
90
85
80
η (%)
p
75
70
65
10
60
5
55
0 5 10 15 0
20 25 30 35 Q
max
Number of Panels
Figure 10-10: Monte Carlo performance prediction: Qavail = [0 : 1 : Qmax ], Monte

Carlo Length = 200, Io,sweep = [0.01 : 0.02 : 6.93] A
plot in Figure 10-10 reveals that tracking efficiency can be very high for only a few
panels. As panels are added, ηp diminishes to a limited extent. The local MPPT
algorithm implemented impacts this behavior significantly. For instance, if the order
of preferences listed in Section 10.2.2 is reversed, the tracking efficiency diminishes
steadily as panels are added rather than flattening as it does in Figure 10-10. The
Monte Carlo simulation results also show how average tracking efficiency improves
as the number of available levels increases. The tracking efficiency predicted for a 3-
panel, 5-level system is approximately 90%. Increasing the number of available levels
to 8 increases the predicted tracking efficiency to 95%.
Finally, it should be noted that the Qmax = 1 case (i.e. Qavail = [0, 1]) is somewhat
representative of a simple series string of panels with bypass diodes. The statistical
data predict roughly 65% average tracking efficiency while a 5-level MIC would im-
356
prove that efficiency to roughly 90%
10.2.5 Effect of spatial panel separation
In the above example, the panels are assumed to have a random and uncorrelated
distribution of MPP’s. Intuitively, this model becomes inappropriate as panels be-
come closely spaced. To model the effect of statistical correlation between MPP’s for
panels arranged in a non-infinite area, the randomly assigned panel MPP’s can be
constrained to a fraction of the full range. The simulation above was repeated having
forced the MPP’s to lie within 50% and 25% of the full range for each Monte Carlo
iteration. The results show universally higher average tracking efficiencies. For in-
stance, the tracking efficiency predicted for a 3-panel, 5-level system is approximately
95.5% and for a 3-panel, 8-level system, 97.4% with a distribution compression of
50%. The simulated results are shown in Figure 10-11.
357
100
95
90
η (%)
85
p
80
75
10
70 5
0 5 10 15 20 25 0
30 35
Q
max
Number of Panels
(a) Compressed Distribution (50%)
100
98
96
ηp (%)
94
92
90 10
88 5
0 5 10 15 20 25 0
30 35 Qmax
Number of Sources
(b) Compressed Distribution (25%)
Figure 10-11: Monte Carlo simulation: Qavail = [0 : 1 : Qmax ], Monte Carlo Length
= 200, Io,sweep = [0.01 : 0.02 : 6.93] A, Compressed Distributions
358
10.3 Switched-capacitor Implementation

One particular realization of the switched-capacitor MICs in Figure 10-4 is the Marx
Multilevel converter. By forming series and parallel combinations of the the input
source and the switched-capacitors, the 5-level Marx converter shown in Figure 10-12
can achieve conversion ratios Qavail = [0, 1, 2, 3, 4].
M3 M6 M9
M1 M4 M7 M10
C1 C2 C3
PV +
M2 M5 M8 M11
Vo
−
Figure 10-12: A 5-Level Marx converter
10.3.1 Efficient Switching Patterns
Switching cycles consist of a recharge phase, φ1 , and an output phase, φ2 . During φ1 ,

the switched-capacitors are disconnected from the load and charged in parallel with
the source. During φ2 , one of several series-parallel configurations of the switched-
capacitors and input source is chosen to achieve the desired conversion ratio. Many
redundant switching configurations are possible (see Appendix D). The switching
configurations shown in Figure 10-13 were chosen for the 5-level Marx to minimize
the conduction losses that will be quantified shortly. Generally, the switching config-
urations were chosen to minimize capacitor droop and the number of switches in the
output current path, both of which lead to loss and load regulation. Rules of thumb
to minimize capacitor droop include 1) utilize the input source to drive the output
during φ2 when possible and 2) utilize all of the switched-capacitors when driving
the output, e.g. parallel-connect redundant capacitors when possible. Note that the
short-circuit current measurement needed for run-time local maximum power point
tracking may be implemented by temporarily activating devices M1 and M2 . The
body diode of device M3 should normally be reverse-biased during the short-circuit
current measurement because the panel voltage should fall below the instantaneous
359
10.3. Switched-capacitor Implementation
capacitor voltage.
Switched-capacitor circuits can achieve very high conversion efficiency by minimiz-
ing the instantaneous current flow through their effective output resistance, Rout,i . In
a DC/DC switched-capacitor circuit, the output is slowly-varying on the time-scale
of one switching period. These facts guide us to particular modes of operation. In
particular, efficient operation can be achieved when the same output phase (φ2 ) con-
figuration is repeated every cycle. In contrast, modulation of the φ2 configuration on
a per cycle basis, e.g. to achieve intermediate conversion ratios, would be ill-advised
as it would lead to continuously varying open circuit converter voltages resulting in
high instantaneous currents (high AC rms currents) through Rout,i . This observation
leads directly to the constraint that the Marx Multilevel converter can (efficiently)
achieve a discrete set of conversion ratios.
360
M3 M6 M9
M1 M4 M7 M10
C1 C2 C3
PV +
M2 M5 M8 M11
Vo
−
(a) Recharge
M3 M6 M9
M1 M4 M7 M10
C1 C2 C3
PV +
M2 M5 M8 M11
Vo
−
(b) Q = 0
M3 M6 M9
M1 M4 M7 M10
C1 C2 C3
PV +
M2 M5 M8 M11
Vo
−
(c) Q = 1
M3 M6 M9
M1 M4 M7 M10
C1 C2 C3
PV +
M2 M5 M8 M11
Vo
−
(d) Q = 2
M3 M6 M9
M1 M4 M7 M10
C1 C2 C3
PV +
M2 M5 M8 M11
Vo
−
(e) Q = 3
M3 M6 M9
M1 M4 M7 M10
C1 C2 C3
PV +
M2 M5 M8 M11
Vo
−
(f) Q = 4
Figure 10-13: Switching configurations
361
10.3.2 Linear Modeling
A linear modeling approach was adapted from the work in [30]. This linear modeling
effort yielded quantitative support for the linear circuit models shown in Figure 10-4
including the output resistances, Ro,i which represent both loss and load regulation
in the switched-capacitor circuits [30].
According to [30], loss and load regulation mechanisms can be differentiated
among two switching speed limiting cases. In the slow-switching-limit (SSL), the
switched-capacitors fully equilibrate yielding impulsive capacitor currents. In the
fast-switching-limit (FSL), the switched-capacitors maintain fixed voltages while ca-
pacitor currents during each switching state are constant [30]. The two switching
t=0 R
+
Vs +
− C Vc
−
Figure 10-14: The canonical circuit for studying the fundamental loss associated with
charging a capacitor.
speed limits can be understood by considering the classic capacitor charging loss
problem depicted in Figure 10-14. The total energy lost in charging the capacitor is
the time-integral of IC (t)2 R:

(Vs − VC (0))2 t
−2t/RC
Etot =− RC e . (10.12)
2R 0
In the SSL, the exponential term is allowed to collapse to -1 and the energy lost
becomes
1
Etot,SSL = C∆VC2 , (10.13)
2
independent of R, and in agreement with the classical result. In the FSL, (10.12) can
be viewed near t = 0 with the Taylor series approximation to the exponential term.
362
This leads to
(Vs − VC (0))2 t
Etot,F SL (t) = , (10.14)
R
i.e. the loss we would expect for two fixed voltages connected across the resistor.
Reference [30] shows how these two loss mechanisms yield asymptotic limits to the
output resistance with proportionalities
1
RSSL ∝ (10.15)
Cfsw
and
RF SL ∝ Rds,on . (10.16)
The method developed in [30] for computing the multipliers to quantify RSSL and
RF SL was adapted to the Marx Multilevel converter here. Example computations
of the effective output resistances can be found in Appendix D. The results are
summarized in Tables 10.1 and 10.2 for Marx converters having between two and eight
available levels. Note that the multipliers in the tables need to be computed for each
conversion ratio (switching pattern) for each number of available levels (topology).
Also note that RF SL depends on the duty ratio between φ1 and φ2 , which was taken as
D = 0.5 (the optimum based on Appendix D) for all switching patterns here. Given
the asymptotic limits, the actual output resistance for any combination of topology,
C, fsw , and Rds,on is generally
Rout ≈ max(RF SL , RSSL ) (10.17)
and the conduction loss per module is simply
Prloss = Io2 Rout . (10.18)
363
Table 10.1: RSSL Multipliers: (×1/Cfsw )

Levels Available: 2 3 4 5 6 7 8
Q=0 0 0 0 0 0 0 0
Q=1 0 0 0 0 0 0 0
Q=2 – 1 1/2 1/3 1/4 1/5 1
Q=3 – – 2 3/2 1 5/6 2/3
Q=4 – – – 3 5/2 2 3/2
Q=5 – – – – 4 7/2 3
Q=6 – – – – – 5 9/2
Q=7 – – – – – – 6
Table 10.2: RF SL Multipliers: (×Rds,on )

Levels Available: 2 3 4 5 6 7 8
Q=0 2 4 6 8 10 12 14
Q=1 2 4 6 8 10 12 14
Q=2 – 8 10 12.4 8.2 17.6 32.4
Q=3 – – 26 24 38 48.4 50.8
Q=4 – – – 64 90 100 100
Q=5 – – – – 130 180 206
Q=6 – – – – – 232 307
Q=7 – – – – – – 378
10.3.3 Switching Loss
The linearized model above captures loss due to output current conduction. Switching
loss is a loss mechanism not explicitly contained in the linearized circuit model of
Figure 10-4. The switching loss for any active switch (one that changes state between
the two switching phases) can be quantified by considering the circuit shown in Figure
10-15. All MOSFETs in the Marx converter reside in at least one loop consisting only
Cgd
Mi d
g
Vg + s
Cds C
− Cgs
Figure 10-15: Switching loss evaluation in the Marx converter for active MOSFETs
of one or two other MOSFETs and a switched-capacitor. In the Marx converter, the
switched-capacitor, C, in Figure 10-15 will nominally exhibit a voltage equal to the
364
panel voltage, Vin , because it is recharged to that potential each cycle. The total
switching loss was estimated in terms of typical data sheet values using [179] for N
active devices as

1
Pswloss = N Qg Vg + Qoss |Vin | + Qrr |Vin | fsw . (10.19)
2
Examining the switching patterns shown in Figure 10-13, one can extract the following
pattern generalizing the number of active switches according to conversion ratio:
N = 1, Q=0 (10.20)
N = 3Q − 2, Q > 0. (10.21)
10.3.4 Inherent Features
Inherent to the topology of the Marx converter are a few interesting features that
may add significant value to a solar power array. As mentioned previously, the Marx
converter has a natural pass-through feature, replicating the function of bypass diodes
and also the pass-through mode presented in [16].
The ability to disconnect each module from the load may be beneficial when
implementing safety disconnect features. Reference [180] discusses the need for a
disconnect in the event of a fire to prevent electrocution hazards that would otherwise
result from the high voltage string output. This disconnect feature may also be
particularly beneficial in implementing an anti-islanding mode. A good discussion of
anti-islanding control and solutions for solar power systems can be found in [181].
The run-time local MPPT algorithm described above can be designed to auto-
matically prevent under-voltage conditions at the panel output. Because the DC/DC
modules continuously choose Qi to closely match Iin,i to Imp,i , they automatically
adjust to over-current conditions, choosing Qi = 0 in the limiting case. This feature
is advantageous when the local control circuitry is powered by the panel itself.
365
10.3.5 Gate Drive
In general, some or all of the MOSFETs in switched-capacitor multilevel output con-

verters may require a gate drive with a continuous floating gate drive voltage because,
the converter itself may not guarantee a periodic charging path to recharge a boot-
strap capacitor. In the Marx converter with the switching patterns shown in Figure
10-13, these devices are M3, M6, M9, M10. A level shift circuit is also required to
translate ground-referenced logic signals to the gate drive output. The recommended
topology (not necessarily the specific parts), adapted from [29], is shown in Figure
10-16.
HV Level Shift
Dbs
Panel Vin VCC VB Cbs

M
IN HO Marx
TTL Rg
VSS VS
Panel GND Co 1N4148

Rcp
1N4148
ICM755
TRIG OUT
RES
THR
Ccp Vp 15 V
GND Cz
Rz
Panel GND
Figure 10-16: The recommended gate drive adapted from IR AN-978 [29].
The 555 timer IC, 1N4148 diodes and floating capacitor form a charge pump
circuit. The resistor between the 555 timer GND and Panel GND and the 15 V
zener, Rz , allows the timer IC to float 15 V below the source of the driven MOSFET.
The low power version of the 555 timer IC (ICM755) is needed in this circuit to
366
achieve low power dissipation in the part itself and to achieve sufficient quiescent
current despite the resistor to ground. The charge pump drives the VB node to twice
its supply voltage referenced to its own floating GND leading to a 15 V floating drive
referenced to the MOSFET source. This voltage can be adjusted by choosing the
voltage of the Zener diode. The “HV Level Shift” could be a commercial high side
driver IC such as the IR2125. However, the high voltage rating of such a part would
be under-utilized for a typical implementation of the system in this work. Therefore,
a more cost-effective gate drive would include a custom level shift circuit.
10.3.6 Non-integral Level Selections
So far, we have considered only switched-capacitor multilevel converters having inte-

gral, boosting sets of conversion ratios. There are many switched-capacitor topolo-
gies that can achieve rational and bucking conversion ratios as well. Such a topology
choice may be beneficial when considering upper bounds on DC bus voltages or other
practical issues. A more thorough investigation will be the subject of future work.
10.4 Simulated Prototype
A 3-panel 510 W system was designed and simulated in SPICE and in Matlabr .
Among the key topological considerations for implementing a practical Marx DC/DC
MIC is the need for a power diode in series with the output of each module. This
diode is required to block current from conducting backwards through the body diode
of the upper MOSFET in the output stage during φ1 . In order to alleviate any
need to synchronize switching action among modules, a local output non-electrolytic
capacitor was placed across each module to create a local DC bus. Figure 10-17 shows
the addition of the output diode, Do , and capacitor, Co , to a 5-level Marx converter.
367
10.4. Simulated Prototype
M3 M6 M9
M1 M4 M7 M10
C1 C2 C3 Do
PV
M2 M5 M8 M11 +
Co Vo
−
Figure 10-17: A 5-Level Marx converter having the added output diode and capacitor.
10.4.1 Number of Levels
The number of levels was chosen using the same Monte Carlo prediction methods
described in Section 10.2.4. Having enumerated loss mechanisms, total efficiency
was used to determine performance. To choose an appropriate number of levels, an
unoptimized but lossy system was simulated using nominal circuit parameters and
MOSFET device characteristics. The predicted performance is plotted in Figure 10-
18. The data show diminishing returns in total efficiency beyond 5 levels. Therefore
a 5-level Marx converter was chosen as the MIC.
10.4.2 MOSFET
Because all of the MOSFETs in the Marx converter reside in loops containing a
switched-capacitor and other MOSFETs only, MOSFET drain-source voltages are
upper bound by the maximum panel voltage. It is particularly advantageous to choose
a panel whose open-circuit voltage is just below a standard value for Vdss . Over-sizing
the MOSFET beyond the required Vds rating would lead to unneeded switching or
conduction loss and a suboptimal design. The MOSFET used in the simulated and
experimental prototypes was chosen for a suitable compromise between on-resistance
and gate charge.
10.4.3 Power Diode
The power diode was chosen primarily to support the peak output current and to
block the peak reverse voltage safely. Secondly, it was chosen for low capacitance,
forward voltage, and ESR. Having added output diodes to the implemented system,
368
Total Efficiency Across Number of Panels and Number of Available Levels
100
95
90
η (%)
85
80
75
0
5 7
4 5 6
10 1 2 3
Qmax
Number of Panels
Figure 10-18: Unoptimized system performance prediction: Qavail = [0 : 1 : Qmax ],

Monte Carlo Length = 400, Io,sweep = [0.01 : 0.02 : 6.93] A, C = 12.5 µF, fsw = 250
kHz, Rdson = 10 mΩ, Qg = 10 nC, Qoss = 5 nC, Qrr = 25 nC,Vg = 15 V, Voc = 29 V,
Vmp = 24.6 V, Isc = 7.38 A, Imp = 6.93 A, Distribution Compression = 50%
the additional losses can be estimated as follows:

Io kT
Vf wd,i = ln n + ESRdiode Io (10.22)
Is + 1 q
X
2
Pdiode = Io Vf wd,i + fsw Cj,i Vrr,i , (10.23)
i
where Vrr is the reverse voltage during φ1 and Cj is the junction capacitance of the
diode. This expression can be used to improve the accuracy of the Monte Carlo
performance predictions. The power diode chosen for this example was the Motorola
MBR20100C Shottky [182]
369
10.4.4 Simulated Performance
A 3-panel system was simulated using SPICE and Matlabr . The performance of
this system was predicted with Monte Carlo methods having incorporated the losses
derived in (10.18), (10.19) and (10.23). A switching frequency of 360 kHz was chosen
based on the simulated loss mechanisms computed above. The results are shown in
Table 10.3. A summary of circuit elements selected for the simulated prototype is
shown in Table 10.4.
Table 10.3: Simulated statistical performance: 5-level, 3 Panel optimized system:
Monte Carlo Length = 100, Distribution Compression = 50%, ∆Io = 1 mA, Diode
Loss = [on], fsw = 360 kHz
efficiency symbol simulated result

tracking ηp 95.43%
conversion ηc 97.56%
total η 93.10%
Table 10.4: Circuit component summary
Component Part No. / Value Note

Switched-capacitors, 12.5 µF Metal Film
Output Capacitor 1 k 4.7 k 6.8 µF
Panel Capacitor 25 µ F 12.5 k 12.5 µF
MOSFET IRF8721
Output Diode MBR20100C Schottky
It is important to realize that the central inverter cannot track panel power, corre-
sponding to ηp , directly. Instead it tracks its input power, corresponding to η. Having
incorporated the loss mechanisms from Section 10.3 and in equation (10.23), this ob-
servation was accounted for in simulation by allowing the inverter to choose the Io
that maximized its input power. Tracking efficiency was recorded for comparison to
total efficiency.
10.4.5 Model Validation
A single experiment was performed in simulation to validate the linear modeling

effort and loss calculations above. A fixed set of conversion ratios and MPPs was
370
chosen for the three panels. Tracking, conversion, and total efficiencies were plotted
for a single Io sweep. Figure 10-19 compares the results for calculated data based
on Section 10.3 and equation (10.23), a SPICE simulation of the linearized model
and a SPICE simulation of the MOSFET system. The difference in ηc between the
linearized model and the other two data sets represents switching and output diode
loss. Errors between the calculated model and FET simulation are likely due to
estimation errors in computing diode and switching losses. Note that in the plots of
Figure 10-19, the maximum in total efficiency lines up closely with the maximum in
tracking efficiency.
Efficiency vs. Output Current

100
η (%)
50 Calculated
p
Simulated Linear Model

Simulated FET Model
0
0 0.5 1 1.5 2
100
η (%)
90 Calculated
c

Simulated FET Model
80
0 0.5 1 1.5 2
100
η (%)
50 Calculated
Simulated FET Model
0
0 0.5 1 1.5 2
Io (A)
Figure 10-19: Model Validation: Single Io sweep, 3 sources, Q = [0, 2, 4], Imp,vec =
[0.007 3.465 6.93] A, C = 12.5 µF, fsw = 360 kHz, MOSFET: IRF8721, Vg = 10 V,
deadtime = 100 ns, Rg = 4 Ω
Time domain waveforms from the simulated system are shown in Figure 10-20.
Figure 10-20(a) shows a zoom-in of the capacitor currents. The shape of those currents
indicates operation between the slow and fast switching limits defined in Section
10.3.2.
371
Capacitor Currents
Ic4
10
I
c5
8 I
c6
4
Current (A)
−2
−4
−6
0.184 0.186 0.188 0.19 0.192 0.194 0.196
Time (ms)
(a) Capacitor Currents
Load Step − System Currents

8
6 Iload
Iin1
5 Iin2
Iin3
Current (A)
−1
0 0.2 0.4 0.6 0.8 1 1.2
Time (ms)
(b) Load Step - Currents
Figure 10-20: Time-domain waveforms.
372
Figure 10-20(b) shows panel input currents during a step change in the load current
from 90% to 100% of the predicted maximum power current. In this example, Panel
1 is bypassed (Q1 = 0) because its MPP is quite low; Iin1 = 0 in the plots. The other
two panels initially settle close to their respective Imp,i ’s - Panel 2 exhibits half of the
photovoltaic current that Panel 3 does. When the load current steps to its maximum
power value, Iin2 and Iin3 settle on their respective Imp,i ’s.
10.5 Experimental Prototype

An experimental prototype was constructed to prove the concepts developed above.
The printed circuit board and schematic can be found in Appendix C. Summaries of
the circuit components and parameters for each of the implemented conversion ratios
are shown in Tables 10.5 and 10.7.
Table 10.5: Experimental prototype parameter summary
Parameter Symbol Value

Switched-capacitor C 12.5 µF
Switching Device Mi IRF8721
Panel Capacitor Cpi 25 µF
Local output Capacitor Coi 12.5 µF
Local output Diode Doi MBR20100C Schottky
Switching freq. Q = 2 fsw,Q2 100 kHz
Panel 1 MP Voltage VM P 1 24.6 V
Panel 1 MP Current IM P 1 6.93 A
Panel 2 MP Voltage VM P 2 24.6 V
Panel 2 MP Current IM P 2 3.47 A
Panel 1 MP PM P 1 170 W
Panel 2 MP PM P 2 85 W
Figure 10-21 shows a connection diagram for the experimental setup consisting
of two series connected modules and the constructed PV circuit models. In this
experiment, a Q = 4 and a Q = 2 module was constructed for comparison to the
model validation simulated data from Figure 10-19. Construction of the Q = 0
module in that simulation was not warranted as it simply represents a short circuit.
373
10.5. Experimental Prototype
Rs1 Ipv1 Do1 Io1

HP6030A +
+ Marx 1 +
+
HP6063B
Vlim1 = 29 V Rp1 Vpv1 Vo1 Co1 E-load
Cp1 − Q=4 −
Ilim1 = 7.47 A − − CC Mode
Rs2 Ipv2 Do2 Io2

HP6010A +
+ Marx 2 +
Vlim2 = 29 V Rp2 Vpv2 Vo2 Co2

Cp2 − Q=2 −
Ilim2 = 3.73 A −
Figure 10-21: A connection diagram depicting the experimental setup for the series
connection of Marx modules and PV circuit models.
Conversion efficiency was measured using HP34401A digital multimeters (DMM’s).

Input and output voltages for each converter were measured at the PCB terminals.
Current sense resistors with nominal values of 10 mΩ each were used to measure
input and output currents. The precise value for each current sense resistor was mea-
sured separately. to within 0.01mΩ using a current-mode and a voltage-mode DMM
simultaneously.
Figures 10-22 and C-1 show photographs of the Marx converter experimental
setup. Figure 10-22 shows the power supplies and measurement equipment. On the
left are the power resistors used to model the photovoltaic panels in this experiment.
Figure C-1 shows a closeup photograph of the two Marx converters and the resistive
elements. The rotary switches along the bottom of each converter determine the
switching pattern and thus the conversion ratio for each converter. Sense resistors
are visible on the input side (left side) for each converter.
10.5.1 Photovoltaic Circuit Model Implementation
Figure 10-23 depicts the experimental construction of the PV circuit models. To

simulate the PV circuit mode from Figure 10-7, the power supplies were set with a
current limit equal to the simulated photovoltaic current Iph (not the short-circuit
current) and a voltage limit equal to the open-circuit or diode forward voltage Vdp .
The values of the resistive elements were computed based on the simulated PV
374
Figure 10-22: A photograph of the switched-capacitor (Marx) converter photovoltaic

experimental validation system.
parameters from the simulation in Figure 10-19 and the mathematical expressions
in equations (10.2)-(10.5) and the nominal panel parameters from (10.8). The first
PV panel, P V1 , was modeled having the peak maximum power conditions (170 W)
while the second, P V2 , was modeled having half the maximum power of the first. The
target and implemented values are summarized in Table 10.6.
Rs Ipv
HP Power Supply + +
Vlim = Vdp Rp Vpv

− −
Ilim = Iph
Figure 10-23: The experimental PV circuit model construction.
375
Table 10.6: The implemented PV circuit model elements
Name Target Value Implementation Actual Value

Rs1 0.635 Ω 0.6 Ω / 50 W + 0.036 Ω / 10 W 0.636 Ω
Rp1 54 Ω 55 Ω / 50 W 55 Ω
Rs2 1.27 Ω 1.25 Ω / 50 W 1.25 Ω
Rp2 108.1 Ω 2×55 Ω / 50 W 110 Ω
Table 10.7: Detailed experimental prototype circuit component values
Component, Parameter Value

Rgi 30 Ω
Dzi 15V 1N5929+2.5V1N5222B
Rcp /Ccp 220 Ω/102
Cbs 104
Cz 104
Co 103
Rosc /Cosc 105 pot / 104
Rdead /Cdead 270 Ω/102
Deadtime 150 ns
Q 2
Rz3 330
Rz6 2 kΩ
Rz9 2 kΩ
Rz10 50 12 W
Q 3
Rz3 330 Ω
Rz6 2 kΩ
Rz9 2 kΩ
Rz10 100 Ω
Q 4
Rz3 330 Ω
Rz6 1 kΩ 12 W
Rz9 200 Ω 43 W
Rz10 200 Ω 43 W
376
Measured PV Ckt. Model Output Power vs. Load Current

1
PV1 Ckt. Model: Rs1 = 0.636 Ω, Rp1 = 55 Ω, Iph1 = 7.47 A, Voc1 = 29 V
Measured MP = 168.885 W @ I = 6.95 A, V = 24.3 V
1 mp1 mp1
180
Measured
160 Simulated
140
120
(W)
100
pv1
80
P
60
40
20
0
0 1 2 3 4 5 6 7 8
I (A)
load
(a) P V1
Measured PV Ckt. Model Output Power vs. Load Current
2
PV2 Ckt. Model: Rs2 = 1.25 Ω, Rp2 = 110 Ω, Iph2 = 3.73 A, Voc2 = 29 V
Measured MP2 = 85.1375 W @ Imp2 = 3.475 A, Vmp2 = 24.5 V
90
Measured
80 Simulated
70
60
(W)
50
pv2
40
P
30
20
10
0
0 0.5 1 1.5 2 2.5 3 3.5 4
Iload (A)
(b) P V2
Figure 10-24: Experimental validation of the artificial PV circuit models.
377
Figure 10-24 shows experimental data validating the large-signal operation of the
PV circuit models constructed as described above. The experimental data is overlayed
on simulated data found using the circuit model in Figure 10-7. The target maximum
power points were 170 W and 85 W respectively. The measured maximum power
points were 168.9 W and 85.1 W. The errors are most likely due to differences between
the implemented and target resistive element values.
10.5.2 Experimental Prototype Performance
The plots in Figure 10-25 show measured efficiency data compared to simulated and
calculated values. The rounding of the peak in the tracking efficiency plot (Figure
10-25(a) is likely due to the slight error in the implementation of the resistive elements
in the PV circuit models. The added loss in the conversion efficiency plot (Figure
10-25(b)) is due to added standby power dissipation and added switching loss. The
plots also included conversion efficiency for a fully discrete implementation whose
standby power dissipation has been optimized. The optimizations are computed in
Section 10.6.
The switching frequencies for modules in the experimental prototype were chosen
based on the measured data in Figure 10-26. A fixed load of 1.5 A was impressed
on each module while the switching frequency was swept within a range yielding safe
operating efficiencies. The switching frequency showing the maximum conversion
efficiency was chosen for each module. Note that the switching frequency yielding the
maximum conversion efficiency generally depends on the conversion ratio.
378

100
90
80
70
60
η (%)
50
p
40
Calculated
30 Simulated FET Model
Measured
20
10
0
0 0.5 1 1.5 2
I (A)
o
(a) Tracking Efficiency
Converter Efficiency vs. Output Current

100
90
80
70
60
Calculated
η (%)
Simulated FET Model

50
Measured
c
Optimized
40
30
20
10
0
0 0.5 1 1.5 2
Io (A)
(b) Converter Efficiency
Figure 10-25: Model Validation: Single Io sweep, 3 sources, Q = [0, 2, 4], Imp,vec =
[0.007 3.465 6.93] A, C = 12.5 µF
379
Measured Converter Efficiency vs. Switching Frequency

Q = 2, Io = 1.5 A, Vin = 24 V, C = 12.5 µF
Peak Efficiency = 93.0796% @ f = 100 kHz, Standby opt. factor = 0.17
sw
94
93
92
91
η (%)
90
c
89
88
87
86
4 5 6
10 10 10
fsw (Hz)
(a) Q = 2
Measured Converter Efficiency vs. Switching Frequency
Q = 4, I = 1.5 A, V = 24 V, C = 12.5 µF
o in
Peak Efficiency = 89.9234% @ fsw = 127.4275 kHz, Standby opt. factor = 0.13
90
89
88
η (%)
87
c
86
85
84
4 5 6
10 10 10
fsw (Hz)
(b) Q = 4
Figure 10-26: Switching frequency choice for the experimental system
380
Figure 10-27 shows a scope shot depicting the operation of the gate drive charge
pump circuit from Figure 10-16 for transistor M6 in the Q = 2 module. The upper
trace is the output voltage of the timer IC and shows the charge pump control voltage
superposed on the transistors source voltage. The transistor source voltage and the
bootstrap node voltage for the high-voltage level shift circuit are shown in the middle
two traces. The total bootstrap voltage is the difference between VS and VB and is
computed on the math channel which shows a DC value of 12.9 V, a voltage suitable
for the working operation of the gate drive circuit.
Figure 10-27: Charge pump operation for M6 in the Q = 2 module. Ch1: VOU T , ch2:
VS , ch3: VB , math: VBS
381
10.6. Efficiency Optimizations
10.6 Efficiency Optimizations
Several conversion efficiency optimizations are immediately clear based on the oper-
ation of the Marx converter. They are discussed here.
10.6.1 Standby Power
Here we compute the standby power dissipation in the experimental system and
speculate what it could be for a reasonably optimized prototype. These optimizations
were taken into account in the experimental performance of Section 10.5.
A significant portion of the standby power dissipation originates in the biasing
resistors for the zener diodes in the gate drive charge pump circuits. Those biasing
resistors should be optimized to provide sufficient bias current for the zener without
dissipating unneeded power. Appropriate values for the zener biasing resistors can be
chosen based on the time-averaged voltage across that resistor. The time-averaged
voltage across the bias resistor divided by the resistance should yield sufficient bias
current for the zener diode. The time-averaged bias resistor voltage is the time-
averaged MOSFET source voltage minus the zener voltage based on the circuit in
Figure 10-16. Therefore the bias resistor value is related to both the MOSFET and
the conversion ratio. Table 10.8 indicates the MOSFET source voltages normalized
by the input voltage across conversion ratios.
Table 10.8: MOSFET source voltages normalized to the input voltage
Recharge Q=0 Q=1 Q=2 Q=3 Q=4

M1 0 0 0 1 1 1
M2 0 0 0 0 0 0
M3 1 1 1 1 1 1
M4 0 0 0 1 1 2
M5 0 0 0 1 1 1
M6 1 1 1 2 2 2
M7 0 0 0 1 2 3
M8 0 0 0 1 1 2
M9 1 1 1 2 2 3
M10 ≈ 12 0 1 2 3 4
M11 0 0 0 1 2 3
382
In the experimental system here, the only MOSFETS needing a charge-sustaining

gate drive are M3, M6, M9, and M10. To compute the biasing resistor we would
consider the minimum input voltage and the minimum zener bias current. For in-
stance, with Vvin,min = 24 V and Iz,min = 18 mA, the time-averaged bias voltage for
the MOSFET M6 in the Q = 2 module is
1+2
< Vbias,M 6,Q2 >= 24 = 36 V. (10.24)
2
The maximum zener bias resistor value for the M6 device in the Q = 2 switching
pattern is then
< Vbias,M 6,Q2 >

Rz6,Q2 ≤ (10.25)
Iz,min
36 V
= = 2 kΩ. (10.26)
0.018 mA
The time-averaged power dissipated in that resistor is
2
< Vbias,M 6,Q2 >
Pbias,M 6,Q2 = (10.27)
Rz6,Q2
2
Vbias,M 6,Q2,rms
= (10.28)
Rz6,Q2
2
2 ∆Vbias,M 6,Q2
< Vbias,M 6,Q2 > + 0.707 2
= (10.29)
Rz6,Q2
2
362 + 0.707 24
2
= = 684 mW, (10.30)
2 × 103
having assumed a square wave of bias voltage and the maximum allowable bias resis-
tance. Clearly, the standby power for the zener bias diode is significant and depends
on the needed bias current to establish the desired nominal zener voltage. As a corol-
lary, the standby power needed to bias the zener diode can be minimized by choosing
a zener diode that requires a minimal amount of bias current. Of course, this sug-
gestion is valid to the extent that the zener bias current is larger than the current
demanded by the charge pump circuit.
383
10.6. Efficiency Optimizations
A related source of standby power dissipation is the power dissipated in the zener
diode itself. This is simply approximated as
Pzi = Ibias,zi Vzi . (10.31)
Clearly, reducing the needed bias current reduces this source of standby power dissi-
pation.
A third source of standby power dissipation originates in the capacitor loss for
charging and discharging the timing capacitor in the charge pump circuit. This loss
is simply
1
Pcp,timing = 2 × Ccp Vzi2 fcp , (10.32)
2
where we have assumed that the timing capacitor is fully charged to the zener volt-
age and fully discharged each switching cycle. Reducing the capacitance value may
constitute a significant optimization. The charge pump switching may be fixed by
increasing the timing resistor by the same factor.
Finally, the 12 V linear regulator used to power the gate drives indicates a max-
imum efficiency of 50% given a minimum input voltage of 24 V. This constitutes a
power dissipation equal to the power delivered by the 12 V rail. If the linear regulator
voltage is increased somewhat, its loss is reduced by the same factor. For instance, the
12 V rail could safely be increased to 18 V without damaging the gate drive circuits.
All of these unoptimized standby power dissipation sources were tabulated. Rea-
sonable optimized values for the fully discrete implementation of the Marx experi-
mental prototype were tabulated as well. The optimized standby power dissipation
numbers were assumed in the conversion efficiency data from Section 10.5. The results
of this exercise are summarized in Table 10.9 for the Q = 2 module.
10.6.2 Run-Time Zener Biasing Optimization
Because the optimal zener bias resistor depends on the conversion ratio, it should
be chosen in run-time to minimize standby power. One approach could be to im-
384
Table 10.9: Standby power optimization results: Q = 2 module.
Source Unoptimized Ref. Optimized

Charge pump Zener M3 684 mW Calc./Meas. 66 mW
Charge pump Zener M10 1.05 W Calc./Meas. 66 mW
Charge pump Timing Caps ×4 130 mW Calc. 26 mW
HV Level Shift ×11 158 mW Assumed 100 mW
ICM7555 ×5 6 mW Datasheet 6 mW
LM7812 162 mW Calc./Meas. 35 mW
LM7805 6 mW Calc. 6 mW
Total 2.9 W → 617 mW
plement a switched set of fixed resistors for each gate drive. The embedded control
in the converter could choose the needed resistor depending on the conversion ratio.
This scheme could be implemented with ground-referenced MOSFETS and TTL level
control signals as indicated by Figure 10-28.
Dzi
Rzi,Q0 Rzi,Q1 Rzi,Q2 Rzi,Q3 Rzi,Q4
4 3 2
TTL 5
Figure 10-28: A possible run time zener bias resistor selection circuit
385
10.7. Input Current-controlled Inverter Dynamics
10.6.3 Run-Time Frequency Scaling
Based on Figure 10-26, the switching frequency yielding the highest conversion ef-
ficiency also depends on the conversion ratio. Therefore, the switching frequency
should also be selected in run-time. This selection may be based on a known set of
optimum switching frequencies for a specific load current.
10.7 Input Current-controlled Inverter Dynamics
A linearized model of the central input current-controlled inverter is shown in Figure

10-29. The closed-loop transfer functions of particular interest can be derived from
that circuit. The transfer function from the inverter input voltage to the inverter
input current is

îin M 2 (D) 1
(s) = 1 (10.33)
v̂in sLe + Re + R k sC
1 + T (s)
and the transfer function from the inverter control voltage to the inverter input current
is
îin A(s)
(s) = , (10.34)
v̂ref 1 + A(s)F (s)
where

M 2 (D)
A(s) = Gc (s)Fm j(s) + e(s) 1 (10.35)
sLe + Re + R k sC
F (s) = HRsense (10.36)
T (s) = AF. (10.37)
The linear model parameters, e, j, M(D), Le , and Re were chosen for a 500 W
buck-derived inverter topology.1 Figure 10-30 shows step responses of the closed-loop
transfer functions in (10.33) and (10.34). They show relatively fast settling times
1
See reference [183] Chapter 8 for a supporting discussion.
386
îin edˆ Le Re
+
−
v̂in + j dˆ R C
−
Rsense
1 : M(D)
H
dˆ
v̂ref + −
Σ Gc Fm
Figure 10-29: A linearized model of an input current-controlled inverter front-end.
in the input current upon step transients in the input voltage (corresponding to the
string DC bus voltage) and the reference voltage (corresponding to the control for
the sweepable input current). The lower plot also indicates a significant attenuation
of the input current response to changes in the input voltage. This attenuation is
largely dependent on the low-frequency magnitude of the loop gain T (s) as indicated
by equation (10.33).
10.8 Conclusions and Further Work
Widespread grid penetration of PV will rely on the reduction of capital cost and
total cost of ownership for solar power systems. It is critical that these factors guide
the design of photovoltaic power circuits and system architectures. This work has
presented a full system approach utilizing switched-capacitor multilevel DC/DC con-
verters. Substantial cost reductions may be possible by providing per-panel MPPT
without the need for per-panel magnetics. Coupling the DC/DC modules with a
ripple port inverter eliminates the need for electrolytic capacitors, enabling long-life
operation.
The approach presented in this chapter can be viewed as follows. Rather than
implementing sophisticated power conversion and MPPT control at each panel, we
387
10.8. Conclusions and Further Work
Step Response i /v
in ref
0.8
Amplitude
0.6
0.4
0.2
0
0 0.2 0.4 0.6 0.8 1 1.2
Time (sec) −9
x 10
Step Response iin/vin
−6
x 10
3
Amplitude
0
0 1 2 3 4 5 6 7
Time (sec) −4
x 10
Figure 10-30: Inverter closed-loop step responses
augment each panel with just enough power conversion and control that a centralized
inverter with MPPT control can largely recover the power that would otherwise be
lost due to partial shading, variations in temperatures, etc. across the solar array.
From this perspective, the system level approach is fundamentally different from the
standard approach to per-panel MPPT. The responsibility of MPPT control is shared
among the panel converters and the central inverter. The result is a simplification of
the needed control at the panel level, allowing the use of switched-capacitor converters
that would otherwise suffer prohibitive drawbacks in this context. Ultimately, the cost
and complexity of the needed per-panel MPPT system may be significantly reduced
compared to other approaches while sacrificing little to no total efficiency.
Topics of ongoing research include investigation of MPPT algorithms and related
system level tradeoffs for control of the central inverter. There exist necessary trade-
offs among switching frequency, converter efficiency, and global tracking efficiency (Io
step size) when considering the dynamics and runtime MPPT approaches for the full
system.
388
Chapter 11
Conclusion
This thesis has investigated the analysis and design of several multisource electri-
cal networks. Applications include power consuming and power generating systems.
Sensing applications are highlighted as a means for controlling power consuming sys-
tems. Hybrid fuel cell systems and multipanel solar arrays are highlighted as multi-
source systems for power generation.
An underlying motivation of this thesis has been to demonstrate the benefits of
multisource electrical networks in energy applications. Fundamentally, multisource
electrical networks provide added degrees of freedom that can add significant advan-
tages in sensing applications and in energy harvesting applications. The advantages
typically come with added complexity in analysis. Therefore an overarching theme
in this thesis has been strategic approaches to the analysis and modeling of multi-
source systems. A primary takeaway from this thesis should be an awareness that
the analytical modeling approach can impact significantly our ability to understand
the behavior of complicated electrical networks. The level of understanding that we
have directly impacts our ability to tailor the design of those systems so that they
serve our application.
This thesis began with the detailed analysis and modeling of the fully-differential
amplifier in Chapter 2. That amplifier constitutes a multisource network in at least
two key ways. First, because the amplifier has a differential-mode input, it can
be viewed as a dual input amplifier. Second, the transformation of the generalized
389
input signal into common-mode and differential-mode signal components yields a
multisource network in the analysis of the fully-differential amplifier response.
Chapters 3-5 explored multisource capacitive sensing occupancy detection sys-
tems. The fully-differential amplifier served as a measurement tool in the multisource
distributed networks. The understanding and design of those systems weighed heavily
on the circuit model and analytical results from Chapter 2. The analytical model of
the fully-differential amplifier was useful in describing carrier suppression techniques
that were central to achieving the performance demonstrated in those examples. Both
natural carrier suppression and active carrier suppression based on multiple signal
sources were demonstrated in examples.
Chapters 6-9 presented the analysis and modeling of multisource multi-converter
power systems for fuel cell power processing. Specific features of the multisource sys-
tems were specified as a-priori design goals. These included fuel cell current buffering
to contend with reliability issues therein and integral diagnostics enabled by run-time
impedance spectroscopy. The linear analysis of the multi-converter systems led to
design guidelines and evaluation methods that enabled successful implementations of
those features in two examples.
Chapter 10 described a method for deploying magneticless per panel solar power
converters. Limitations of the switched-capacitor multilevel output converters were
overcome by examining a linearized model of the system and considering system level
approaches. Decoupling of the maximum power point tracking control among the
panel converters and reasonable tracking efficiency were both achieved as a result of
this analytical approach.
390
Appendix A
Capacitive Sensing Occupancy

Detection
• Lamp sensor hardware
• Dimming ballast hardware
• Lamp sensor software
• Lamp sensor full system simulation
• Lamp sensor practice
• Standalone sensor software
• Fully-differential amplifier detailed derivations
391
A.1. Lamp Sensor Hardware
A.1 Lamp Sensor Hardware

• Photographs
• PCB layout
• Schematic drawings
• Build notes
• Bill of materials.
The lampsensor circuit and PCB, (Rev 2) includes the analog electronics needed
for synchronous detection, the digital electronics needed for interfacing with a PC, and
a DAC for adjusting the DC control voltage on a dimming lamp ballast. The circuit
is implemented on a 4-layer PCB with split ground planes, one for the analog side
and one for the digital side. The ground planes join at the power supply connection
in the middle of the board. The split ground plane layout minimizes the effect of
digital signal return currents on the analog signal processing and vice versa. With
split ground planes it is important to pay attention to inductive loops that may be
formed when bridging the two ground planes. Specifically, traces that bridge the two
ground planes should be accompanied by return traces on the layer below.
392
A. Capacitive Sensing Occupancy Detection
A.1.1 Photographs
Photographs of the lamp sensor PCB and various measurement electrodes are shown
in the Figure below.
(a) Top
(b) Bottom
(c) Electrodes
Figure A-1: Photographs of the lamp sensor electronics and electrodes.
393
A.1.2 PCB Layout
Figure A-2: The Eagle Cadr PCB layout of the lamp sensor, Rev 2.
394
Figure A-3: The Eagle Cadr PCB layout of the lamp sensor, Rev 2 without ground
and power planes drawn.
395
lampsensor_rev2.zip
Layer: lampsensor_rev2.cmp
Figure A-4: Top copper layer.

04 May 2011,08:55 AM
396
04 May 2011,08:55 AM
Layer: lampsensor_rev2.sol
lampsensor_rev2.zip
Figure A-5: Bottom copper layer.
397
lampsensor_rev2.zip
Layer: lampsensor_rev2.ly1
Figure A-6: Inner copper layer 1.

04 May 2011,08:55 AM
398
04 May 2011,08:55 AM
Layer: lampsensor_rev2.ly2
lampsensor_rev2.zip
399
A.1.3 Schematic Drawings
Figure A-8: The analog section of the Eagle Cadr schematic of the lamp sensor, Rev
2.
400
Figure A-9: The digital section of the Eagle Cadr schematic of the lamp sensor, Rev
2.
401
Figure A-10: The ancillary sections of the Eagle Cadr schematic of the lamp sensor,
Rev 2.
402
A.1.4 Build Notes
• Move the LPF to before the buffer and and change it to 10k and 1nF. Use the
0 ohm pads for RMB1 and RMB2 as the 10k and a through hole cap for the
1nF.
• Do solder the solder bridge SJ1 between VDD Molex pin and RICSP=0Ohm.
• CMCLR should not be populated.
403
A.1.5 BOM
The lamp sensor, Rev. 2, bill of materials is shown in the table below. Refer to
Chapter 3 for changes.
Qty Value Device Parts
1 F09HP X1
1 JP2Q ICSP
1 QG5860 11.0592MHZ
1 SJW SJ1
7 0 R-EUM1206 RBA1-2, RFM1-2, RICSP, RMB1-2
1 1N4148SO 1N4148SO DMCLR
2 4-40STANDOFF 4-40STANDOFF U3, U 4
2 10 R-EUM1206 RLPF1, RLPF2
2 10M R-EUM1206 RF1, RF2
1 10k R-EUM1206 RMCLR
2 15pF1% C-EUC1206 CF1, CF4
2 15pf1% C-EUC1206 CF2, CF5
2 20 R-EUM1206 R6, R7
1 22-23-2021 22-23-2021 DIMX
1 22-23-2031 22-23-2031 POWER
1 22-23-2051 22-23-2051 ICSPX
2 22-23-2081 22-23-2081 PORTB, PORTD
4 33UFTANTSMD 33UFTANTSMD ANA5CAP, DIG5CAP, V+CAP, V-CAP
1 33k R-EUM1206 ROCM
22 104 C-EUC1206 C6, CB1-21
8 105 C-EUC1206 CLPF1-2, CM1-52, CMCLR
1 200k R-EUM1206 RF3
2 499 R-EUM1206 RP1, RP2
1 680p C-EUC1206 CF3
2 7805DPAK 7805DPAK ANALOG7805, DIGITAL7805
2 AD790SOIC AD790SOIC COMP-1, COMP-2
2 AD8620 AD8620 JFET-1, JFET-2
1 ADG411 ADG411 MULTIPLIER
1 LT1236 LT1236 REFERENCE
1 LT2051SO-8 LT2051SO-8 BUFFER
1 LTC2440 LTC2440 LTC2440
1 MAX232SOIC MAX232SOIC MAX232
1 MX7224SO-18 MX7224SO-18 DAC
1 PIC16F877PT PIC16F877PT PIC
4 SMAWM5543-ND SMAWM5543-ND ELECTRODE1-2, PLLSMA, REFELECTRODE
14 TESTPOINT5000K-ND TESTPOINT5000K-ND BUSY-SCK
19 ESTPOINTSO5015KCT TESTPOINTSO5015KCT ADC+ - VOCM
1 THS4140 THS4140 DIFFAMP
Table A.1: Lamp sensor, Rev.2 bill of materials.
404
A.2 Dimming Ballast Hardware

• Photographs
• PCB layout
• Build notes
• Bill of materials
• Inductor specifications.
The dimming ballast is a frequency-controlled dimming ballast built around the

International Rectifier IR21592 ballast IC. It drives two 32 W bulbs in a balanced
configuration and takes a DC input voltage between 0 and 5 V as a control input for
the lamp power (brightness). Design software provided by International Rectifier was
used to aid the implementation of this ballast. The outputs from that design software
are included in this Appendix. Some modifications were made to the resulting design.
Those modifications are also described in this Appendix.
405
A.2. Dimming Ballast Hardware
A.2.1 Photographs
Photographs of the dimming ballast, Rev. 2 PCB are shown in the Figure below.
(a) Top
(b) Bottom
Figure A-11: Photographs of the dimming ballast, Rev. 2 PCB.
406
A.2.2 PCB Layout
Figure A-12: The Eagle Cadr PCB layout of the dimming ballast, Rev 2.
407
Figure A-13: The Eagle Cadr PCB layout of the dimming ballast, Rev 2 without
ground and power planes drawn.
408
409
Dimming_Ballast_REV2.zip
Layer: Dimming_Ballast_REV2.cmp
Figure A-14: Top copper layer.

04 May 2011,10:41 AM
Layer: Dimming_Ballast_REV2.sol
04 May 2011,10:41 AM
Figure A-15: Bottom copper layer.

410
04 May 2011,10:41 AM
Layer: Dimming_Ballast_REV2.ly1
411
Layer: Dimming_Ballast_REV2.ly2

04 May 2011,10:41 AM
412
413
A.2.3

Schematic Drawings
Figure A-18: Dimming ballast, Rev. 2 schematic
F1
F2
L RV1 BR1 LPFC DPFC
C1 R6
N CBUS RVAC RSUPPLY
L1 RVDC
E R1 R3
CY RDC
D1 CVDC
C2 R2 RHO LRES:A
R4 ICPFC ICBALLAST
1 8 C5 CVCO 1 16 CDC LBALANCE

R5 C4 CBOOT
R7 2 15 CSNUB
2 7 CPH DBOOT
MPFC 3 14 RLIM2
C3 RBUS 3 6 RDIM LRES:B CH1 CH2 LRES:D
4 13 DCP2
RMULT CVCC1 CVCC2
4 5 RMAX 5 12
RLO RV2
L65651 RMIN 6 11 DCP1 RPU1 CRES
RLIM1 FL. BULBS

RFMIN 7 10
RS RSD1
8 9
RIPH RCS
IR21592 RPU2
DIM CMIN CCS CSO LRES:C CH3 CH4 LRES:E

RSD2
COMMON
A.2.4 Build Notes
Layout notes:
• Wind Lres to inductance value not to turns count. 48 instead of 54 is about

right for 1.2mH. This is because the gap length of the actual core is .5mm while
the design calls for .6mm yielding a higher AL value in the actual core set than
in the designed core set.
• Eliminate buzz and flicker: Short Earth plane to common plane at terminal
block (earth plane) and molex near terminal block (common) to eliminate buzz
and flicker. For EMI filtering, lift Cy outside leg and connect to Earth gnd from
wall and backplane. In next rev, eliminate earth plane, or make both planes
common planes.
Filament heating notes - Daniel Vickery, optimized the component values to

reduce unneeded filament heating - Last updated 2010.09.21:
• Chx: 0.22uF → 0.12uF - This increases the impedance of each heating capacitor,
reducing the voltage across the filaments.
• Cph: 0.27uF → 0.56uF - Doubles the pre-heating time (before ignition).
• Cvco: 0.01uF → 0.022uF - Decreases the slope of the ignition frequency ramp
by a factor of two. This fixes our original striking problems.
• Riph: 24k → 26.1k - Slightly increase the pre-heat filament current.
• Rmin: 27k → 27.4k - Slightly increase the phase shift at minimum power.
• Rmax: 30k → 24k - Slightly decrease the phase shift at maximum power.
A.2.5 BOM
The dimming ballast, Rev. 2, bill of materials is shown in the table below. Refer to
Chapter 3 and to the layout and filament heating notes for changes.
414
IR21592 Bill Of Materials (74 items)

Lamp Type 'T8 32W'
Line Input '80 to 140VAC/300VDC'
7/23/2008, 4:35:05 PM Page 1 Configuration 'Dual lamp parallel/Balance transformer'
Target IC 'IR21592 discrete dimming ballast'
Type Value Rating Tolerance Reference

Bridge Rectifier 1A 1000V BR1
Capacitor 0.33 uF 275VAC C1
Capacitor 0.1 uF 400V C2,CDC
Capacitor 0.01 uF 25V C3,CVCO
Capacitor 0.68 uF 25V C4
Capacitor 0.47 uF 25V C5,CVDC
Capacitor 0.1 uF 25V CBOOT,CMIN,CSD,CVCC1
DC Bus Capacitor 22 uF 350V CBUS
Capacitor 220 pF 25V CCS
Capacitor 0.22 uF 100V CH1,CH2,CH3,CH4
Preheat Time Capacitor 0.27 uF 25V CPH
Resonant Capacitor 0.01 uF 1500V 5% CRES
Capacitor 1.5 nF 630V CSNUB
Capacitor 4.7 uF 25V CVCC2
Y Capacitor 2.2 nF 250VAC CY
Diode 1N4148 D1,DCP2
Fast Recovery Diode 600 V 1A DBOOT
Diode 17 V DCP1
PFC Diode 600 V 1A DPFC
Fuse 2A 250VAC F1
Ballast Control IC IR21592 IC BALLAST
PFC IC L6561 IC PFC
Common-mode Line Filter 2x5.1mH 0.8A L1
Balance Transformer 2x10mH LBALANCE
PFC Inductor 400 uH 2.9 Apk 5% LPFC:A
Secondary Winding 10 Turns LPFC:B
Resonant Inductor 1.2 mH 3.0 Apk 5% LRES:A
Secondary Windings 5 Turns LRES1:B,LRES1:C,LRES2:B,LRES2:C
Half-Bridge MOSFET IRF730 MHS,MLS
PFC MOSFET IRF740 MPFC
Resistor 820 KOhm 200V R1,R2,R3,R4
Resistor 100 KOhm R5,RDC
Resistor 22 KOhm R6
Resistor 20 Ohm R7
Resistor 13.78 KOhm 1% RBUS
Current Sense Resistor 0.62 Ohm 1% RCS
Resistor 5.1 KOhm RDIM
Resistor 47 KOhm 1% RFMIN
Resistor 20 Ohm 5% RHO,RLO
Resistor 24 KOhm 1% RIPH
Resistor 1 KOhm RLIM1
Resistor 10 Ohm RLIM2,RLIM3
Resistor 30 KOhm 1% RMAX
Resistor 18 KOhm 1% RMIN
Resistor 9.1 KOhm RMULT
Resistor 1 M Ohm RPU1,RPU2
Resistor 0.2 Ohm 1% RS
Resistor 220 KOhm RSD1,RSD2
Resistor 270 KOhm 400V RSUPPLY
Varistor 470 V RV1
Resistor 1 M Ohm 400V RVAC
Resistor 130 KOhm RVDC
Figure A-19: Dimming ballast, Rev.2 bill of materials.
415
A.2.6 Inductor Specifications
LRES Inductor (50%)

Lamp Type 'T8 32W'
,1'8&72563(&,),&$7,21
7<3(/5(692/7$*(02'(
&25(6,=( P36/22 *$3/(1*7+ 0.6 PP
%2%%,1 +25,=217$/
&25(0$7(5,$/ 3KLOLSV&6LHPHQV1RUHTXLYDOHQW
120,1$/,1'8&7$1&( 1.2 P+
0$;,080&855(17 2.6 $SN
0$;,080&25(7(03(5$785( &
:,1',1* 67$573,1 ),1,6+3,1 78516 :,5(',$0(7(5PP
0$,1 54 0.3
CATHODE (1) 5 0.2
CATHODE (2) 5 0.2
CATHODE (3) 5 0.2
CATHODE (4) 5 0.2
(/(&75,&$//$<287 3+<6,&$//$<287
7(67 7(67)5(48(1&< N+]
0$,1:,1',1*,1'8&7$1&( 0,1 P+ 0$; P+

0$,1:,1',1*5(6,67$1&( 0,1 2KPV
127(,QGXFWRUPXVWQRWVDWXUDWHDWPD[LPXPFXUUHQWDQGPD[LPXPFRUHWHPSHUDWXUHDWJLYHQ
WHVWIUHTXHQF\
Figure A-20: Dimming ballast, Rev.2 resonant inductor specification.
416
Balance Transformer (50%)

Lamp Type 'T8 32W'
,1'8&72563(&,),&$7,21
7<3(/5(6&855(1702'(
&25(6,=( ( *$3/(1*7+ PP
%2%%,1 +25,=217$/
0,1,080,1'8&7$1&( P+
0$;,080&855(17 $SN

0$;,080&25(7(03(5$785( &
:,1',1* 67$573,1 ),1,6+3,1 78516 :,5(',$0(7(5PP

35,0$5<
6(&21'$5<
(/(&75,&$//$<287 3+<6,&$//$<287
11mm
2.5mm
1 6
2.5mm
16mm 2 5
3 4
7(67 7(67)5(48(1&< N+]
0$,1:,1',1*,1'8&7$1&( 0,1 P+
0$,1:,1',1*5(6,67$1&( 0,1 2KPV
127(,QGXFWRUPXVWQRWVDWXUDWHDWPD[LPXPFXUUHQWDQGPD[LPXPFRUHWHPSHUDWXUHDWJLYHQ
WHVWIUHTXHQF\
Figure A-21: Dimming ballast, Rev.2 current share (balance) transformer specifica-
tion.
417
LPFC Inductor (50%)

Lamp Type 'T8 32W'
,1'8&72563(&,),&$7,21
-. (
&25(6,=( E30/15/7 3C90 *$3/(1*7+ 1.1
=== +25,=217$/
')

0.4
,)
) 2.5 2
,)
) 511 4
:,1',1* 67$573,1 ),1,6+3,1 78516 :,5(',$0(7(5PP

0$,1 77 0.4
, 10 0.2

-) -
-)
* (/)
-0123+
&'')

,
&'

.6"7% "%%$%" $%$%$8"7" %$6$8"7 % $%" $%9#
%%: !"7;<
Figure A-22: Dimming ballast, Rev.2 power factor correction (pfc) transformer spec-
ification.
418
A.3 Lamp Sensor Software
The PIC microcontroller runs the c program (“operating system”) listed in Section
A.3.1. The operating system interfaces with Matlabr through an RS-232 serial
connection. An illustrative flow diagram for the operating system is shown in Figure
A-23. The flow diagram highlights the handshaking operation of the PIC-Matlabr
interface. Handshaking before each event improves the reliability of the software.
The c program is listed in A.3.1. Various “apps” were written as Matlabr scripts
to interface with the lamp sensor. Some useful apps are also listed in this Appendix.
Initialize
PIC ADC
Set Lamp
Brightness
Wait for serial Main Loop

character
from PC...
A Z else
Wait for Read Set lamp

ADC ready... dimlevel to max
from PC brightness
Send
Read ADC dimlevel
to DAC
Transmit
ADC data
to PC
Figure A-23: Flow chart of PIC microcontroller “operating system” listed in A.3.1.
419
A.3. Lamp Sensor Software
A.3.1 PIC Microcontroller Operating System
handshakedimmer2.c
This is the “PIC Operating System.” It is programmed into the PIC onboard the
lampsensor PCB and interfaces with a PC over a serial (RS-232) port. It also employs
some of its output pins with a DAC to control the dimming level of a dimming
fluorescent lamp ballast using a signal voltage between 0 and 5 V. The operating
system can interface with a PC using simple ASCII character handshaking.
#i n c l u d e <p i c . h>
//Make s u r e t o ch an ge p cc . b at t o reflect the c o r r e c t PIC o r you will

// h ave p r o b l e m s up h e r e !
// Program a s r e g u l a r 8 b i t hex o r Intel
//ADC Timing Mode i s : External Serial Cl ock , /CS = 0 O p e r a t i o n (2− w i r e ) , w i t h SDI

// i n p u t s p e e d selection fr om t h e PIC on e a c h c o n v e r s i o n cycle . S ee F i g . 7 i n t h e
// LTC2440 D a t a s h e e t . The PIC s h i f t s i n the speed resolution b y t e on t h e ADC SDI
// p i n w h i l e it supplies the serial clock t o t h e SCK p i n on t h e ADC and w h i l e it
// s h i f t s in t h e ADC o u t p u t d a t a fr om t h e ADC SDO p i n . S ee F i g . 4 i n t h e LTC2440
// D a t a s h e e t .
CONFIG( 0 x3F72 ) ; //No c o d e p r o t . , no d eb u gger , FLASH p r o g . memory w r i t e e n a b l e d

// no LVP, y e s Brown Out R eset , no Watchdog , y e s Power up t i m e r
// High S p eed O s c i l l a t o r
unsigned c h a r MMSB;
unsigned c h a r NNSB;
unsigned c h a r LLSB ;
unsigned c h a r JJSB ;
unsigned c h a r MSB;
unsigned c h a r NSB ;
unsigned c h a r LSB ;
unsigned c h a r SIGN ;
unsigned char trash ;
unsigned char incoming ;
unsigned char status ;
int newlinecount ;
int i;
int j;
int datapoint ;
int dimlevel ;
v o i d ReadADC ( v o i d ) ;
v o i d WriteUART( u n s i g n e d char ) ;
v o i d WriteHex ( u n s i g n e d char ) ;
void getd atab ytes ( void ) ;
void tran smi t ( void ) ;
void f t r a n s m i t ( void ) ;
void d el ay ( void ) ;
v o i d dim5 ( v o i d ) ;
420
void g e t d a t a p o i n t ( void ) ;
void h an d sh ake ( v o i d ) ;
void g e t d i m l e v e l ( void ) ;
v o i d setDAC ( i n t ) ;
void L i n i t ( void ) { // L i n i t just initializes e v e r y t h i n g and c h o o s e s

// a l l of the a p p r o p r i a t e o p t i o n s i n t h e mess o f
// S p e c i a l Registers .
TRISA = 0 b 11110011 ; // Use P or t A t o c o n t r o l and p o l e ADC,

//ADC Busy −> RA1 ( i n p u t )
// S l a v e E n ab l e −> RA0 ( i n p u t )
//A3 and A2 −> Lsb ’ s f o r DAC i n p u t ( o u t p u t s )
// Watch ADCON r e g i s t e r s h e r e and f o r every
// p o r t wh i ch h as AD i n p u t c h a n n e l s ! !
ADCON1 = 0 b 00000110 ; //ADC p i n s : 00000110 sets a l l RA’ s and RE’ s digital .

// A n al og i n p u t p i n s must be TRIS = 1 . A l s o s e e ADCON0.
TRISB = 0 x00 ; // Use P or t B on Harsha ’ s Board t o control

// dimming DAC.
// C o n f i g u r e SPI
TRISC = 0xD0 ; // C o n f i g u r e p o r t C : Rx and Tx s e t (UART) ;
//SDO Output ; SDI c o n f i g u r e d by c o n t r o l reg
// a s i n p u t ;
//SCK o u t p u t ( Mast er ) ; RC<2:0> don ’ t care .
TRISE = 0 x00 ; // P or t E [ 2 : 0 ] i s 3 Msb ’ s f o r DAC i n p u t ( o u t p u t s )
SSPCON = 0 x20 ; // C o n f i g u r e S yn ch r on ou s Serial P or t C o n t r o l R e g i s t e r :

//SSPCON<7:6> don ’ t care ;
// E n ab l e Serial P or t mode f o r SCK, SDO, SDI ( and SS ) ;
// I d l e State for clock i s Low ;
// SPI Mast er Mode , c l o c k = Fosc / 4 .
SSPSTAT = 0 x40 ; // C o n f i g u r e S yn ch r on ou s Serial P or t Status Register :

//SMP Sample a t m i d d l e o f data output time
// Data t r a n s m i t on rising e d g e o f SCK.
//SSPSTAT<5:0> don ’ t care .
// C o n f i g u r e UART
RCSTA = 0 x90 ; // S e t b i t SPEN t o c o n f i g u r e RX and TX a s UART p i n s .
//RCSTA f o r Async c o n t i n u o s receive enable
TXSTA = 0 x24 ; // C o n f i g u r e Tr an sm i t register :

// B i t 7 don ’ t care ( Async ) ; 8− b i t transmission ;
// Tr an sm i t e n a b l e d ; A syn ch r on ou s Mode ; b i t 3 unimp .
// High Baud Rate ; TXSTA<1:0> don ’ t care .
SPBRG =71; // Baud Rate G e n e r a t o r V al u e = 5 f o r 1 1 5 . 2 kbps

// w i t h ( 1 1 . 0 5 9 2MHz Cl ock ) . 71 for 9600
t r a s h = RCREG; // C l e a r S e r i a l Recv i n t e r r u p t flag
421
RCIF = 0 ;
v o i d main ( v o i d ) {
Linit ( ) ; // I n i t i a l i z e PIC and ADC

dim5 ( ) ; // B r i g h t e n lamp
while (1){
h an d sh ake ( ) ;
if ( i n c o m i n g == ’A’ )
{
w h i l e (RA1 == 1 ) // Wait f o r ADC t o finish converting
continue ;
ReadADC ( ) ; // Get t h e c o n v e r s i o n result
getdatabytes ( ) ; // I s o l a t e 24 d a t a b i t s ou t o f 32
ftransmit ( ) ; // Send t h e result to serial port
}
else if ( i n c o m i n g == ’ Z ’ ) // I f i n c o m i n g == ’ Z ’ we a r e going to get

{ // a dimming l e v e l next .
getdimlevel ( ) ; // Read t h e b i n a r y dimlevel value
setDAC ( d i m l e v e l ) ; // S e t t h e DAC i n p u t p i n s
}
else // I f t h e i n c o m i n g c h a r was != ’A’ or ’Z ’

{
t r a s h = RCREG; // C l e a r t h e RCREG
RCIF = 0 ; // and t h e interrupt flag
dim5 ( ) ; // b r i g h t e n lamp t o 100%
}
////////////////////////////////////////////////////////////////
// s u b r o u t i n e s
////////////////////////////////////////////////////////////////
v o i d setDAC ( i n t DAC) { // S e t s the l e f t o v e r PIC p i n s

RE2 = (DAC >> 7 ) &0x01 ; // t o correctly control t h e DAC
RE1 = (DAC >> 6 ) &0x01 ;
RE0 = (DAC >> 5 ) &0x01 ;
RC2 = (DAC >> 4 ) &0x01 ;
RC1 = (DAC >> 3 ) &0x01 ;
RC0 = (DAC >> 2 ) &0x01 ;
RA3 = (DAC >> 1 ) &0x01 ;
RA2 = DAC &0x01 ;
422
void g e t d i m l e v e l ( void ) { // Reads a b i n a r y v a l u e fr om t h e serial port

while ( RCIF == 0 )
continue ;
d i m l e v e l = RCREG;
}
void h an d sh ake ( v o i d ) { // Reads a c h a r a c t e r fr om t h e serial port

while ( RCIF == 0 )
continue ;
i n c o m i n g = RCREG;
}
v o i d dim5 ( v o i d ) { // saw B a l l a s t dim 4 . 9 8 V 3/13/08
PORTE = 0 x07 ;
RC2 = 0 ;
RC1 = 1 ;
RC0 = 1 ;
RA3 = 1 ;
RA2 = 1 ;
}
v o i d dim4 ( v o i d ) {
PORTE = 0 x06 ; // Saw B a l l a s t dim 3 . 9 7 3/13/08
RC2 = 0 ;
RC1 = 0 ;
RC0 = 1 ;
RA3 = 0 ;
RA2 = 0 ;
}
v o i d dim3 ( v o i d ) { // Saw B a l l a s t dim 3 . 0 2 3/13/08

PORTE = 0 x04 ;
RC2 = 1 ;
RC1 = 0 ;
RC0 = 1 ;
RA3 = 1 ;
RA2 = 0 ;
}
v o i d dim2 ( v o i d ) {
PORTE = 0 x03 ; // Saw B a l l a s t dim 2 . 0 2 3/13/08
RC2 = 0 ;
RC1 = 0 ;
RC0 = 1 ;
RA3 = 0 ;
RA2 = 0 ;
}
v o i d dim1 ( v o i d ) { // Saw B a l l a s t dim 1 . 2 6 V 3/13/08

// D e s i r e > 1V
PORTE = 0 x01 ;
RC2 = 1 ;
423
RC1 = 1 ;
RC0 = 1 ;
RA3 = 0 ;
RA2 = 0 ;
}
void d el ay ( void ) {
i = 0;
w h i l e ( i <500) {
j = 0;
w h i l e ( j <1000) {
j = j +1;
continue ;
}
i = i +1;
continue ;
}
}
void tran smi t ( void ) { // Tr an sm i t MSB, t h e n NSB, t h e n LSB
// P l ay w i t h d e l i m i t i n g characters here
WriteUART(MSB) ;
WriteUART(NSB ) ;
WriteUART( LSB ) ;
WriteUART( SIGN ) ;
WriteUART ( 0 ) ; // D e l i m i t w i t h a z e r o .
void f t r a n s m i t ( void ) { // Tr an sm i t MSB, t h e n NSB, t h e n LSB

// P l ay w i t h d e l i m i t i n g characters here
WriteHex (MSB) ;
WriteUART( ’ \ n ’ ) ;
WriteHex (NSB ) ;
WriteHex ( LSB ) ;
WriteHex ( SIGN ) ;
/////////////
v o i d ReadADC ( v o i d ) {
i n t SampRateByte = 0 x48 ; // Th i s is t h e v a l u e we w i l l w r i t e t o SSPBUF t o initiate
// t r a n s m i s s i o n and a l s o t o sen d t o t h e SDI p i n on t h e ADC
// i n order t o program t h e s a m p l i n g rate as follows :
//0 x08 = 3 . 5 2 kHz , 0 x10 = 1 . 7 6 kHz , 0 x00 = 880 Hz , 0 x18 = 880Hz
//0 x20 = 440Hz , 0 x28 = 220Hz , 0 x30 = 110 Hz , 0 x38 = 55 Hz
//0 x40 = 2 7 . 5 Hz , 0 x48 = 1 3 . 7 5 Hz , 0 x78 = 6 . 8 7 5 Hz
SSPBUF = SampRateByte ; // W r i t e t o SSPBUF t o initiate transmission .

// The V al u e w r i t t e n t o SSPBUF o u t p u t s t o t h e ADC’ s SDI p i n
424
// and p r ogr am s t h e sam p l e rate .

//SCK i s o u t p u t t o ADC
while (STAT BF == 0 ) // Wait till Buffer is full

continue ;
MMSB = SSPBUF ; //8 o f 32 i n MSB
SSPBUF = SampRateByte ; // n e x t b y t e
while (STAT BF == 0 )
continue ;
NNSB = SSPBUF ; //9−16 i n NSB
SSPBUF = SampRateByte ; // n e x t b y t e
while (STAT BF == 0 )
continue ;
LLSB = SSPBUF ; //17 −24 i n LSB
SSPBUF = SampRateByte ; // L et t h e ADC f i n i s h so it can

while (STAT BF == 0 ) // s t a r t the next cycle .
continue ;
JJSB = SSPBUF ;
// I leave it a s an e x e r c i s e to the r ead er to figure ou t why

// SSPBUF = SampRateByte ; // I n eed ed this extra on e i n order to
// while (STAT BF == 0 ) // g e t it working .
// continue ;
} // b ack t o main w i t h MMSB, NNSB and LLSB
///////////////////////
const char h e x l o o k u p [ ] = ” 0 1 2 3 4 5 6 7 8 9ABCDEF” ; // A r r ay f o r b i n t o hex c o n v e r s i o n
v o i d WriteHex ( u n s i g n e d char x ) // Con ver t fr om b i n t o hex and w r i t e

{ // t o t h e UART
WriteUART( h e x l o o k u p [ x >> 4 ] ) ;
WriteUART( h e x l o o k u p [ x & 0 x 0 f ] ) ;
}
//////////////////////
v o i d WriteUART( u n s i g n e d char transmitchar ) { // J u s t w r i t e t o t h e UART.

w h i l e ( ! TXIF ) // Wait u n t i l last transmit is done
continue ;
TXREG = t r a n s m i t c h a r ; // W r i t e t o TXREG wh i ch initiates
} // t r a n s m i s s i o n
//////////////////////
void getd atab ytes ( void ) { // Get 24 d a t a b i t s amongst t h e 32 t r a n s m i t t e d bits :

MSB = ( ( (MMSB << 3 ) & 0 b 11111000 ) + ( ( NNSB >> 5 ) & 0 b 00000111 ) ) ;
NSB = ( ( ( NNSB << 3 ) & 0 b 11111000 ) + ( ( LLSB >> 5 ) & 0 b 00000111 ) ) ;
LSB = ( ( ( LLSB << 3 ) & 0 b 11111000 ) + ( ( JJSB >> 5 ) & 0 b 00000111 ) ) ;
SIGN = ( (MMSB >> 5 ) & 0 b 00000001 ) ;
}
425
A.3.2 Matlabr Sensing and Real-time Measurements
dimmerdemo2.m
This script oversees a demonstration of occupancy sensing for a system that can also
control the lamp power level (dimming level).
o%% A lamp s e n s o r demo . You can s p e c i f y a dimming l e v e l with a
%% c o n t i n u o u s v a l u e b et ween 1 and 5 . U ses p l ot d i m m er .m. Works w i t h
%% handshakedimmer2 . c .
f u n c t i o n y = dimmerdemo2 ( r e f , p o i n t s , d i m l e v e l )
clear figure
%% Check t h e ar gu m en t s
if ( n a r g i n ˜=3)
d i s p ( ’ Usage : dimmerdemo2 ( r e f e r e n c e voltage , p o i n t s p e r fr am e , ...
dim l e v e l (1 −5)) ’)
return
else
%% D e f i n e G l o b a l s
g o m a s t e r = ’A ’ ;
s t o p m a s t e r = ’B ’ ;
dimcommand = ’ Z ’ ;
linewidth = 2;
figure (2);
format long ;
printbuf = zeros (1 , points ) ; %I n i t i a l i z e the prinbuffer to zeros .
event = ( [ ] ) ; %I n i t i a l i z e the event buffer
STATUS = 0 ; LAST EVENT = 0 ; %Some v a r i a b l e s
calibrate = ( [ ] ) ; %A u t o c a l i b r a t e t h e o u t p u t p l o t scale
collected = [ ] ;
matrix = [ ] ;
p o r t s=i n s t r f i n d ;
%% I n i t i a l i z e some t h i n g s
STATUS = 0 ;
LAST EVENT = 0 ;
%% Check t h e serial p o r t s and c l e a n u p if n eed ed

if s i z e ( ports , 1 ) > 0
stopasync ( i n s t r f i n d ) ;
fclose ( instrfind );
delete ( instrfind );
end
%% C r e a t e a serial port object

s= s e r i a l ( ’COM4’ , ’ BaudRate ’ , 9600 , ’ D at aBi t s ’ , 8, ’ Parity ’ , ’ none ’ , ...
’ StopBits ’ , 1, ’ terminator ’ , ’ LF ’ , ’ t i m eou t ’ , 2 ) ;
fopen ( s ) ; %Open s e r i a l port d e f i n e d ab ove
%% A d j u s t d i m gai n and d i m o f f s e t iteratively to calibrate for t h e g a i n and

%% o f f s e t in order to achieve dimlevel [ 1 : 5 ] corresponding t o DAC o u t p u t
%% [ 1 : 5 ] V .
d i m gai n = 0 . 7 4 5 ;
dim of fs e t = 255∗(1 −0.058)/5;
426
%Map 1−5 v a l u e o n t o 0−255 b i n a r y o u t p u t v a l u e :

dimlevel = dimlevel − 1; %1−5 −> 0−4
dimlevel = ( dimlevel /4)∗255; %0−4 −> 0−255
d i m l e v e l = d i m l e v e l ∗ d i m gai n ; %c o r r e c t gain error
d i m l e v e l = d i m l e v e l+d i m o f f s e t ; %c o r r e c t offset ( error )
%% S e t t h e initial dimming l e v e l
f p r i n t f ( s , ’ % c ’ , dimcommand ) ;
fwrite (s , dimlevel );
%% Measure t h e n o i s e −f l o o r to calibrate plot scales , event detection

w h i l e ( l e n g t h ( c a l i b r a t e )) <50
collected = [ ] ;
matrix = [ ] ;
f p r i n t f ( s , ’% c ’ , gomaster ) ;
for i =1:4 %C o l l e c t 4 b y t e s fr om t h e ADC
c o l l e c t e d = ( f s c a n f ( s , ’%x ’ ) ) ;
m a t r i x = h o r z c a t ( m at r i x , collected );
end
MSB = ( 2 ˆ 1 6 ) ∗ m a t r i x ( 1 ) ; NSB = ( 2 ˆ 8 ) ∗ m a t r i x ( 2 ) ; LSB = . . .
m a t r i x ( 3 ) ; SIGN = m a t r i x ( 4 ) ;
i f SIGN==0
d a t a p o i n t = −(16777215 −(MSB+NSB+LSB ) ) ;
else
d a t a p o i n t = MSB+NSB+LSB ;
end
c a l i b r a t e = horzcat ( c a li br a t e , datapoint ∗(1/16777215));
STATUS = ’ C a l i b r a t i n g ’
end
calib rat e = cali br ate (35: length ( calib rat e ) ) ;
m i n s c a l e = 1 . 8 ∗ ( max ( c a l i b r a t e )−min ( c a l i b r a t e ) ) ∗ r e f ;
%% The Main Loop

while (1)
%S t op t h e l o o p if you p r e s s q
if st r cm p ( g e t ( 2 , ’ c u r r e n t c h a r a c t e r ’ ) , ’ q ’ )
% C l o s e and wrap up t h e serial port
close (2)
stopasync ( s ) ;
fclose (s );
delete ( s ) ;
clear s;
save printbuf ;
break
end
% The ” P l o t H e l p e r ” s c r i p t
p l ot d i m m er
end
end
427
plotdimmer.m
This script “helps” the demonstration script, dimmerdemo2.m, by plotting a single

data point and also computing signal characteristics, e.g. time-domain windowed
noise, and identifying events in the sensor output e.g. movement of an occupant into
or out of the detection field.
%% A sub−s c r i p t that collects d a t a fr om t h e lamp s e n s o r , plots it ,
%% i n t e r p r e t s it as events , etc .
%% I n i t i a l i z e some v a r i a b l e s
collected = [ ] ;
matrix = [ ] ;
%% C o l l e c t the data p oi n t !
end
%% T r a n s l a t e the 4 data b ytes into a signed integer

MSB = ( 2 ˆ 1 6 ) ∗ m a t r i x ( 1 ) ; NSB = ( 2 ˆ 8 ) ∗ m a t r i x ( 2 ) ; LSB = m a t r i x ( 3 ) ; . . .
SIGN = m a t r i x ( 4 ) ;
i f SIGN==0
d a t a p o i n t = −(16777215 −( MSB+NSB+LSB ) ) ;
else
end
%Output d a t a p o i n t h as units Volts
datapoint = r e f ∗ datapoint /16777215;
%% S h i f t t h e new d a t a p t . in , the last data pt . ou t for a ” roll ing plot ”

printbuf = horzcat ( printbuf ( 2 : points ) , datapoint ) ;
%% Real −t i m e S i g n a l Characteristics , e.g. Noise

format short
% Compute t h e total deviation i n a window o f data
VRANGE = ( max ( p r i n t b u f )−min ( p r i n t b u f ) ) ;
% Compute t h e a v e r a g e i n t h e same window o f data
AVG = sum ( p r i n t b u f ) / ( p o i n t s ) ;
% Compute t h e rms v o l t a g e ab ou t t h e a v e r a g e : Th i s is a useful indication of
% noise i n t h e t i m e−domain when t h e r e i s NO d e t e c t i o n
VACrms uV = ( ( ( 1 / p o i n t s ) ∗ sum ( ( p r i n t b u f −AVG) . ∗ ( p r i n t b u f −AVG) ) ) ˆ 0 . 5 ) / ( 1 e −6)
%% P l o t t i n g
% Upper p l o t : au t o−zooming , c e n t e r e d on t h e d a t a
subplot (3 ,1 ,1) %Th i s window will auto s c a l e unless the deviations
%a r e less t h an some v a l u e ” m i n s c a l e ”
f i x e d s c a l e = 2∗ r e f ∗1 e −2; %S e t up t h e fixed s c a l e window

% Mi d d l e p l o t : Fixed Scale , c e n t e r e d on z e r o
subplot (3 ,1 ,2)
plot ( printbuf , ’ Linewidth ’ , linewidth )
axis ([1 p oi n t s −f i x e d s c a l e fixedscale ]);
y l a b e l ( ’ Volts ’ )
428
%% Event D e t e c t i o n :
%% For t h e final p l o t , we w i l l n eed t o know if there is c u r r e n t l y an ” Event ”
%Use t h e total deviation i n t h e window t o i n d i c a t e an ” Event ”
%I f there i s no e v e n t , zoom i n t o t h e minimum s c a l e on t h e u p p er plot
i f VRANGE < m i n s c a l e
axis ([1 p o i n t s ( min ( p r i n t b u f ) − m i n s c a l e ) ( max ( p r i n t b u f ) + m i n s c a l e ) ] ) ;
STATUS = ’ Q u i e t ” shhhhhh ” ’ ;
%Event d i s p l a y starts here :
%I f Vrange is s m a l l and t h e l e n g t h o f the event is small , there is no
%e v e n t o n g o i n g and any e v e n t t h a t happened was insignificant : reset the
%e v e n t vector
if l e n g t h ( event ) < 6
%I f t h e window is n ot a u t o s c a l e d
event = ( [ ] ) ;
else
%I f t h e r e h as b een an e v e n t l o n g enough in duration then p l o t it
subplot (3 ,1 ,3) %I n t h e bottom p l o t
%Get some v a l u e s t o help plot the event history
l e n g t h e v e n t = l e n g t h ( event ) ;
%These 4 v a l u e s can be u sed to determine direction of travel
e v e n t l e f t = event ( 1 : f l o o r ( 0 . 5 ∗ l e n g t h e v e n t ) ) ;
a v g e v e n t l e f t = ( sum ( e v e n t l e f t ) ) / l e n g t h ( e v e n t l e f t ) ;
e v e n t r i g h t = event ( c e i l ( 0 . 5 ∗ l e n g t h e v e n t ) : l e n g t h e v e n t ) ;
a v g e v e n t r i g h t = ( sum ( e v e n t r i g h t ) ) / l e n g t h ( e v e n t r i g h t ) ;
%Make b ooken d s for the plot history
bookend length = f l o o r (0.3∗ length event ) ;
a v g e v e n t = ( sum ( e v e n t ( 1 : l e n g t h e v e n t ) ) ) / ( l e n g t h e v e n t ) ;
%Glue t h e b ooken d s o n t o t h e e v e n t
event = h orzcat ( ( ones ( 1 , b ooken d l en gth ) ) . ∗ avgevent , . . .
event , ( ones ( 1 , b ooken d l en gth ) ) . ∗ avgevent ) ;
%P l o t t h e wh ol e e v e n t in red in the l a s t window
p l o t ( event , ’r ’ , ’ linewidth ’ , linewidth )
%I d e n t i f y direction of travel
if av g ev ent lef t < avg event right ,
LAST EVENT = ’ L e f t t o R i gh t ’ ;
else
LAST EVENT = ’ R i g h t t o L e f t ’ ;
end
a x i s auto ; %Auto s c a l e t h e e v e n t window
event = ( [ ] ) ; %r e s e t the event vector
%Event d i s p l a y en d s h e r e
end
else
%I f there i s an e v e n t on−g o i n g , autoscale t h e u p p er p l o t and c o n t i n u e .
plot ( printbuf , ’ linewidth ’ , linewidth )
a x i s auto ;
%And c o l l e c t the event data p o i n t s
event = horzcat ( event ( 1 : ( l e n g t h ( event ) ) ) , datapoint ) ;
%A l s o print ’ Event ’
STATUS = ’ Event ’ ;
end
% Drawnow
drawnow
429
A.3.3 Matlabr Time-domain Windowed Noise Measurements
noisedatplot.m
This script takes time-domain data from the lamp sensor and computes a windowed
noise measurement. It averages the rms noise levels from several finite-length windows
to get an estimate of the noise floor.
%% Th i s script m easu r e and com p u t es t i m e−domain windowed n o i s e data .
%% Each window ( fr am e ) i s a f i x e d number o f points long .
f u n c t i o n y = n o i s e d a t a p l o t 2 ( frames , points , datarate , dimlevel )
clear figure
%% Check t h e ar gu m en t s
if ( n a r g i n ˜=4)
d i s p ( ’ Usage : d a t a p l o t ( no . of frames , p o i n t s p e r fr am e , datarate ...
( p o i n t s p e r s e c o n d ) ) , dim l e v e l 1 −5 ’)
return
else
%% I n i t i a l i z e some v a r i a b l e s
g o m a s t e r = ’A ’ ;
s t o p m a s t e r = ’B ’ ;
dimcommand = ’ Z ’ ;
r ef = 5;
linewidth = 2;
figure (2);
format long ;
collected = [ ] ;
matrix = [ ] ;
Vacrms = [ ] ;
STATUS = 0 ;
LAST EVENT = 0 ;
%% Check t h e serial p o r t s and c l e a n u p if n eed ed

if s i z e ( ports , 1 ) > 0
end
%% Open a serial port

s= s e r i a l ( ’COM6’ , ’ BaudRate ’ , 9600 , ’ D at aBi t s ’ , 8, ’ Parity ’ , ’ none ’ , ...
’ StopBits ’ , 1, ’ terminator ’ , ’ LF ’ , ’ t i m eou t ’ , 2 ) ;
fopen ( s ) ; %Open s e r i a l port d e f i n e d ab ove
%A d j u s t d i m gai n and d i m o f f s e t iteratively to calibrate for t h e g a i n and

%o f f s e t in order to achieve dimlevel [ 1 : 5 ] corresponding to
%DAC o u t p u t [ 1 : 5 ] V.
d i m gai n = 0 . 7 6 ;
dimoffset = 255∗(0.96)/5;
%Map 1−5 v a l u e o n t o 0−255 b i n a r y o u t p u t v a l u e :
dimlevel = dimlevel − 1; %1−5 −> 0−4
430
dimlevel = ( dimlevel /4)∗255; %0−4 −> 0−255

d i m l e v e l = d i m l e v e l ∗ d i m gai n ; %c o r r e c t gain error
d i m l e v e l = d i m l e v e l+d i m o f f s e t ; %c o r r e c t offset ( error )
%% S e t t h e intial dim l e v e l
f p r i n t f ( s , ’ % c ’ , dimcommand ) ;
fwrite (s , dimlevel );
%% Measure t h e noise floor for calibrating the p l o t window

w h i l e ( l e n g t h ( c a l i b r a t e ) <40)
collected = [ ] ;
matrix = [ ] ;
f p r i n t f ( s , ’% c ’ , gomaster ) ; %T e l l Mast er PIC t o go
end
MSB = ( 2 ˆ 1 6 ) ∗ m a t r i x ( 1 ) ; NSB = ( 2 ˆ 8 ) ∗ m a t r i x ( 2 ) ; LSB = m a t r i x ( 3 ) ; . . .
SIGN = m a t r i x ( 4 ) ;
i f SIGN==0
d a t a p o i n t = −(16777215 −(MSB+NSB+LSB ) ) ;
else
end
c a l i b r a t e = horzcat ( c a li br a t e , datapoint ∗(1/16777215));
end
calib rat e = cali br ate (20: length ( calib rat e ) ) ;
p r i n t b u f = r e f ∗ c a l i b r a t e ( l e n g t h ( c a l i b r a t e ))∗ ones ( 1 , p o i n t s ) ;
pointcount = 0 ;
framecount = 0 ;
printbufhistory = [ ] ;
%% The Main Loop

while (1)
if p o i n t c o u n t == p o i n t s
p r in t bu f h is t o r y = horzcat ( printbuf his to ry , printbuf );
p r i n t b u f = r e f ∗ c a l i b r a t e ( l e n g t h ( c a l i b r a t e ))∗ ones ( 1 , p o i n t s ) ;
Vacrms = h o r z c a t ( Vacrms , VACrms uV )
pointcount = 0;
framecount = framecount + 1 ;
end
%S t op t h e l o o p if data collection is done OR i f you p r e s s q
if f r a m e c o u n t==f r a m e s | st r cm p ( g e t ( 2 , ’ c u r r e n t c h a r a c t e r ’ ) , ’ q ’ )
% C l o s e and wrap up t h e serial port
close (2)
stopasync ( s ) ;
fclose (s );
delete ( s ) ;
clear s;
%S ave all the data
L en gth of wi n d ow sec = p o i n t s /( d a t a r a t e )
save Length of window sec ;
n o of wi n d ows = frames
save no of windows ;
Dim level = dimlevel
save Dim level ;
Data rate Hz = datarate
save Data rate Hz ;
Window VACrms uV = Vacrms
431
s a v e Window VACrms uV ;
E n d t o en d d ev m V = . . .
( printbufhistory ( length ( printbufhistory ) ) . . .
−p r i n t b u f h i s t o r y ( 1) ) ∗ 1000
s a v e E n d t o en d d ev m V ;
Max dev mV = ( max ( p r i n t b u f h i s t o r y )−min ( p r i n t b u f h i s t o r y ) ) ∗ 1 0 0 0
s a v e Max dev mV ;
Avg Window VACrms uV = sum ( Vacrms ) / l e n g t h ( Vacrms )
s a v e Avg Window VACrms uV ;
Avg output mV = . . .
sum ( p r i n t b u f h i s t o r y ) / l e n g t h ( p r i n t b u f h i s t o r y ) ∗ 1 0 0 0
s a v e Avg output mV ;
s a v e Vacrms ;
save printbufhistory ;
save points ;
save frames ;
% Glue all of the frames together i n t o on e p l o t vector

fr am een d = [ ] ;
for i = 1 : ( f r a m e s −1)
fr am een d = h o r z c a t ( l e n g t h ( p r i n t b u f h i s t o r y ) . . .
−i ∗ points , fr am een d ) ;
end
s a v e fr am een d ;
break
end
% P l o t t h e d a t a a s we go
noisedataplotroll
p o i n t c o u n t = p o i n t c o u n t +1;
end
end
432
A.4 Lamp Sensor Full System Simulation

This appendix presents code and example simulation parameters for the full system
simulation of the lamp sensor system.
A.4.1 SPICE Model Output Voltage Extraction
bash command for extracting data from log files.txt
This command can be used in a unix command line interface to extract data points
from several .log files resulting from several different SPICE simulations. This is
useful when performing a SPICE simulation for several discrete occupant positions
in the lamp sensor simulation. The simulated output voltage among the SPICE
simulations can be tabulated. The result can be plotted as a simulated lamp sensor
output voltage.
Having s a v e d t h e u n i x command e x t r a t l o g s . sh a s an e x e c u t a b l e i n t h e
directory with the log files do :
>> chmod +x e x t r a c t l o g s . sh
wh i ch makes t h e . sh file executable
then
>> . / e x t r a c t l o g s . sh
and s i m u l a t e d o u t p u t . t x t appears in the directory wh er e t h e log files are .
t h e n MATLAB:
>> g e n e r a t e p l o t 2
∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
Unix command i n e x t r a c t l o g s . sh :
for i i n ∗ l o g ; do e c h o −n $ { i / . l o g }” ” ; awk −F ’[ =] ’ ’ / v o u t f d a /{ p r i n t $3 } ’ . . .
$i ; done | tee simulatedoutput . txt
Capacitive Model Validation Plotting
generateplot2.m
This script generates a model validation plot to compare simulated and measured
lamp sensor data.
%% Th i s script plots si mu l ated data overl ayed on e x p t a l d a t a . It extracts
%% s i m u l a t e d d a t a fr om s i m u l a t e d o u t p u t . t x t wh i ch i s g e n e r a t e d by r u n n i n g
%% t h e f o l l o w i n g BASH command i n the si m u l at i on directory having the . log
%% f i l e s fr om t h e LTSPICE s i m u l a t i o n s : for i i n ∗ l o g ; do e c h o −n $ { i / . l o g }”
%% ” ; awk −F ’[ =] ’ ’ / v o u t f d a /{ p r i n t $3 } ’ $i ; done | tee
%% s i m u l a t e d o u t p u t . t x t It extracts e x p t a l d a t a fr om p r i n t b u f . mat wh i ch i s
433
A.4. Lamp Sensor Full System Simulation
%% t h e o u t p u t b u f f e r fr om t h e d a t a p l o t 2 .m s c r i p t r u n w i t h u s i n g a lamp
%% s e n s o r .
%% S i m u l a t e d Data
load simulatedoutput . txt ;
simulatedvod = v e r t c a t ( f l i p u d ( si mu l ated ou tp u t ( 1 : 1 5 , 2 ) ) , . . .
simulatedoutput ( 1 6 : length ( simulatedoutput ) , 2 ) ) ;
%% E x p e r i m e n t a l Data
load p r i n t b u f . mat ;
exptalvod = printbuf ;
%% S i m u l a t e d and e x p t a l offsets
s i m u l a t e d b i a s = simulatedvod ( 1 ) ;
ex pt a lbia s = exptalvod ( 1 ) ;
%% S u b t r a c t t h e offsets
s i m u l a t e d v o d = s i m u l a t e d v o d −s i m u l a t e d b i a s ;
exptalvod = exptalvod − e x pt a lbia s ;
%% I n i t i a l i z e horizontal axis vector

x = −3.6:0.2:3.6;
%% Trim t h e e x p t a l d a t a and x v e c t o r s o t h e y a r e t h e same l e n g t h a s t h e

%% s i m u l a t e d d a t a .
exp tal vod = exp tal vod ( 1 : l e n g t h ( simulatedvod ) ) ;
x = x ( 1 : l e n g t h ( simulatedvod ) ) ;
%% P l o t t h e d a t a
fig ure (1)
p l o t ( x , 1 e3 ∗ s i m u l a t e d v o d , ’ x ’ )
x l i m ( [ min ( x ) max ( x ) ] )
h o l d on ; p l o t ( x , 1 e3 ∗ e x p t a l v o d , ’ − . ’ ) ;
l e g e n d ( ’ S i m u l a t e d ’ , ’ Measured ’ , ’ L o c a t i o n ’ , ’ Best ’ )
t i t l e ( { ’ L am p sen sor R esp on se t o a P a s s i n g 1 . 8 3 m− t a l l Occupant ’ ; . . .
’ Lamp H e i g h t = 2 . 5 8 m, E l e c t r o d e S p a c i n g = 98 cm , Depth = 1 4 . 5 cm ’ ; . . .
’ Simulated floor h e i g h t ( b el ow t i l e ) = −2.5 cm , V s = 200 V , . . .
f c = 50 kHz ’ ; ’ F l o o r E ar t h ed , Gnd E ar t h ed ’ } )
x l a b e l ( ’ Occupant d i s t a n c e fr om c e n t e r o f lamp (m) ’ )
y l a b e l ( ’ Lamp s e n s o r o u t p u t (mV) ’ )
hold off
434
FastCapr Example list File
model.lst
This is an example input (.lst) or “list” file for generating a 3D physical model useful
in extracting lumped capacitances to describe the lamp sensor or other capacitive sys-
tem. The .qui files are each data files (input surfaces) that describe a 3D object. The
.lst file determines their geometric position in the 3D space. ‘+’ signs indicate that
adjacent conductors are to be lumped as one conductor, i.e. capacitances coupling to
the conductors are lumped into one capacitance. The result of this particular .lst file
is pictorially depicted in Figure 3-20.
∗G model . l s t
∗ S yn t ax i s ”C o b j e c t f i l e . q u i r e l . perm x o r i g i n yorigin zorigin ”
∗ Group1
∗ Upper L e f t
C halfbulb . qui 1 0.007 0.0575 0
∗ Group2
∗ Lower R i g h t
C halfbulb . qui 1 0.612 −0.0825 0
∗ Group3
∗ Lower L e f t
C halfbulb . qui 1 0.007 −0.0825 0
∗ Group4
∗ Upper R i g h t
C halfbulb . qui 1 0.612 0.0575 0
∗ Group5
∗ Left Electrode .0762 = 3 in . 0.1524 = 6 in .
C e l e c t r o d e . qui 1 0.12 −0.127 0 . 1 5 2 4
∗ Group6
∗ Right E l e c t r o d e
C e l e c t r o d e . qui 1 1.10 −0.127 0 . 1 5 2 4
∗ Group7 : Lamp Case and o t h e r conductors that will be e a r t h e d

C b a c k p l a n e . q u i 1 0 −0.127 −0.07+
C s i d e p l a n e . q u i 1 −0.011 −0.127 −0.07+
C s ide pla ne . qui 1 1.221 −0.127 −0.07+
C middlepart . qui 1 0.03 −0.05 −0.05+
C middlepart . qui 1 0.23 −0.05 −0.05+
C middlepart . qui 1 0.43 −0.05 −0.05+
C middlepart . qui 1 0.63 −0.05 −0.05+
C middlepart . qui 1 0.83 −0.05 −0.05+
C middlepart . qui 1 1.03 −0.05 −0.05+
C f i x e d l a m p s . q u i 1 −0.47 −1 −0.22+
C f i x e d l a m p s . q u i 1 1 . 8 5 −1 −0.22+
C p o w e r s t r i p . q u i 1 0 −1.2 1.5+
C p i p e . q u i 1 −2.5 −0.1 −0.45+
C duct . qui 1 1.25 −4.0 −1
435
∗ Group8
∗Human C e n t e r e d when x = 0 . 6 1 − 0 . 1 = 0 . 5 1
∗C t a r g e t . q u i 1 0 0 1
C head . q u i 1 −1.4 −0.050 0. 625+
C torso . qui 1 −1.4 −0.225 0. 90+
C l e g s . qui 1 −1.4 0.024 1. 56+
C l e g s . qui 1 −1.4 −0.15 1 . 5 6
∗ Group9
∗ Unmovable f l o a t i n g conducting o b j ec t s : ” cabinet ” f o r short
C c a b i n e t . q u i 1 −2.1 −1.7 0 . 4
∗ Group 10
∗ Floor or whatever is u n d er t h e floor
C b i g f l o o r p a r t . q u i 1 −3.5 −0.5 2. 48+
C b i g f l o o r p a r t . q u i 1 −3.5 0 . 0 2. 48+
C b i g fl o o rp a rt . qui 1 3.5 −0.5 2. 48+

C b i g fl o o rp a rt . qui 1 3.5 0 . 0 2. 48+





C b i g f l o o r p a r t . q u i 1 −2.0 0 2. 48+
436

C b i g f l o o r p a r t . q u i 1 0 −0.5 2. 48+
C b i g f l o o r p a r t . q u i 1 0 0 2. 48+
C b i g f l o o r p a r t . q u i 1 0 . 5 0 2. 48+
C b i g f l o o r p a r t . q u i 1 0 0 . 5 2. 48+


437
FastCapr Example Input Surfaces
Input Surfaces.txt
This is an output screen from a FastCapr simulation summarizing the input surfaces’
dimensions and physical placement in the model. It shows distinct groups of conduc-
tors. Multiple conductors are combined into one group using the ‘+’ sign notation.
Running f a s t c a p 2.0 ( 1 8 S ep 92 )
I n p u t : C: \ Documents and S e t t i n g s \ John Cool ey \
SPICE Cap Model S i m u l a t i o n s Jan and Feb 2010\ FastCap
Working F i l e s \ temp . l s t
Input surfaces :
GROUP1
h a l f b u l b . qu i , conductor
title : ‘ 0 . 6mX0. 0 2 5 mX0. 0 2 5m cu b e ( n=1 e = 0 . 1 )
’
outer permittivity : 1
number o f panels : 98
number o f extra evaluation points : 0
translation : (0.007 0.0575 0)
GROUP2
e l e c t r o d e . qu i , conductor
title : ‘ 0 . 0 2 5 4mX0. 2 5 4mX0. 0 0 1m cu b e ( n=1 e = 0 . 1 )
’
translation : (0.127 −0.127 0 . 1 5 2 4 )
GROUP3
b a c k p l a n e . qu i , conductor
title : ‘ 1 . 2 2mX0. 2 5 4mX0. 0 1m cu b e ( n=1 e = 0 . 1 )
’
translation : (0 −0.127 − 0. 07)
s i d e p l a n e . qu i , conductor
title : ‘ 0 . 0 1mX0. 2 5 4mX0. 1m cu b e ( n=1 e = 0 . 1 )
’
translation : ( − 0. 011 −0.127 − 0. 07)
m i d d l e p a r t . qu i , conductor
title : ‘ 0 . 1 9mX0. 1mX0. 0 8m cu b e ( n=3 e = 0 . 1 )
’
translation : (0.03 −0.05 − 0. 05)
f i x e d l a m p s . qu i , conductor
title : ‘ 0 . 2 5 4mX2mX0. 0 5m cu b e ( n=3 e = 0 . 1 )
’
translation : ( − 0. 47 −1 − 0. 22)
438
p o w e r s t r i p . qu i , conductor
title : ‘ 5mX0. 0 5mX0. 0 5m cu b e ( n=3 e = 0 . 1 )
’
translation : ( 0 −1.2 1 . 5 )
p i p e . qu i , conductor
title : ‘ 5mX0. 1mX0. 1m cu b e ( n=3 e = 0 . 1 )
’
translation : ( − 2. 5 −0.1 − 0. 45)
d u c t . qu i , conductor
title : ‘ 0 . 6mX5mX0. 5m cu b e ( n=3 e = 0 . 1 )
’
translation : ( 1 . 2 5 −4 −1)
GROUP4
head . qu i , conductor
title : ‘ 0 . 1mX0. 1mX0. 2m cu b e ( n=3 e = 0 . 1 )
’
translation : (0 −0.05 0 . 6 1 )
t o r s o . qu i , conductor
title : ‘ 0 . 1mX0. 4 5mX0. 5 5m cu b e ( n=3 e = 0 . 1 )
’
translation : (0 −0.225 0 . 9 )
l e g s . qu i , conductor
title : ‘ 0 . 1mX0. 1 2 7 mX0. 9m cu b e ( n=3 e = 0 . 1 )
’
translation : (0 0.024 1.52)
GROUP5
c a b i n e t . qu i , conductor
title : ‘ 0 . 6mX0. 5mX2m cu b e ( n=3 e = 0 . 1 )
’
translation : ( − 2. 1 −1.7 0 . 4 )
GROUP6
b i g f l o o r p a r t . qu i , conductor
title : ‘ 0 . 4 8mX0. 4 8mX0. 0 5m cu b e ( n=3 e = 0 . 1 )
’
translation : ( − 3. 5 −0.5 2 . 4 6 )
Date : Thu Feb 11 1 5 : 2 8 : 5 4 2010
439
A.4.2 Fully Differential Amplifier Circuit Model Netlist
FDAnetlist.ls
The following netlist was used in the SPICE simulations to capture the linearized
circuit model of the fully-differential front-end amplifier. Refer to Figure 3-25.
. param ad = 2 . 7 9 4 e6
. param ac = 8 7 7 1 . 5
. param Z f = 423 e3
. param d e l t a Z f = 0 . 0
. param d e l Z f = { d e l t a Z f ∗ Z f }
. param Z f 1 = { Z f + 0 . 5 ∗ d e l Z f }
. param Z f 2 = { Z f − 0 . 5 ∗ d e l Z f }
. param nomZf = { ( Z f 1+Z f 2 ) / 2 }
. param Z i n d = { ( 2 ∗ nomZf/(1+ ad ) ) + ( ac ∗ d e l Z f /( 2∗ ( 1+ ad ) ) ) }
. param Z i n c = { 0 . 5 ∗ nomZf}
R3FDA N001FDA edp { 0 . 5 ∗ Z i n d }

R4FDA edm N002FDA { 0 . 5 ∗ Z i n d }
R5FDA e c s o u r c e ec { Zinc }
Vpdummy + N001FDA 0
Vmdummy − N002FDA 0
Bedp edp e c V = 0 . 5 ∗ ( i ( vpdummy)+ i (vmdummy) ) ∗ ( 1 / ( 1 + { ad } ) ) ∗ ( − 0 . 5 ∗ { d e l Z f }

−0.5∗{nomZf }∗{ ac } )
Bedm e c edm V = 0 . 5 ∗ ( i ( vpdummy)+ i (vmdummy) ) ∗ ( 1 / ( 1 + { ad } ) ) ∗ ( − 0 . 5 ∗ { d e l Z f }
−0.5∗{nomZf }∗{ ac } )
Bec e c s o u r c e gnd V= −0.5∗{ d e l Z f } ∗ ( i ( vpdummy)− i (vmdummy) ) ∗ 0 . 5
Bvodp v o p f d a v o c f d a V = 0 . 5 ∗ ( i ( vpdummy)+ i (vmdummy) ) ∗ 0 . 5 ∗ ( − { ad }∗{ d e l Z f }

+{ac }∗{nomZf } ) /( 1+ { ad })+( i ( vpdummy)− i (vmdummy) ) ∗ 0 . 5 ∗ ( 2 ∗ ( { ad }/(1+{ ad } )
) ∗ { nomZf}−{ac }∗{ d e l Z f } /( 2∗ ( 1+ { ad } ) ) )
Bvodm v o c f d a vomfda V = − 0. 5∗ ( i ( vpdummy)+ i (vmdummy) ) ∗ 0 . 5 ∗ ( − { ad }∗{ d e l Z f }

+{ac }∗{nomZf } ) /( 1+ { ad })+( i ( vpdummy)− i (vmdummy) ) ∗ 0 . 5 ∗ ( 2 ∗ ( { ad }/(1+{ ad } ) )
∗{ nomZf}−{ac }∗{ d e l Z f } /( 2∗ ( 1+ { ad } ) ) )
Bvoc v o c f d a gnd V = {Vocm}
440
A.4.3 Full System Simulation SPICE Parameters
model.ls
The following SPICE directives and parameters were used in the full system SPICE
model of the lamp sensor system. Refer to Figure 3-25.
∗∗∗ G e n e r a l P a r a m e t e r s ∗∗∗
. param Vs = 200
. param f c a r r = 50 e3
. param s t o p t i m e = 10/{ f c a r r }
∗∗∗ S i g n a l S o u r c e Model ∗∗∗∗

. param V s t r o n g = {Vs /2}
. param Vweak = {Vs /4}
. param Vend = {Vweak}
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗∗ ∗∗
. param Vsupp = 6
. param RLP = 10
. param CLP = 1 e−6
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗∗ ∗∗∗ ∗∗∗ ∗∗∗ R e s u l t s ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗
. m easu r e Vout RESULT = avg (V( voutp , voutm ) ) fr om 150 u t o 200 u
441
A.4.4 Example Capacitances
capacitances.ls
The following SPICE directives show a tabulation of example capacitances used in

the full systems simulation of the lamp sensor. Refer to Figure 3-25.
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗∗ ∗∗∗ ∗∗∗ ∗∗∗ ∗∗ C a p a c i t a n c e s ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗∗ ∗∗∗ ∗∗∗ ∗∗∗Vary With t a r g e t ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗
∗ Left strong to t a r g e t : 1−8
. param C3 = 300 e −15
∗ Right stron g to t a r g e t : 2−8
. param C5 = 167 e −15
∗ Left electrode to t a r g e t : 5−8
. param C9 = 534 e −15
∗ Right e l e c t r o d e to t a r g e t : 6−8
. param C10 = 187 e −15
∗ T a r g e t t o b a c k p l a n e : 7−8
. param C27 = 14300 e −15
∗ Target to c a b i n e t : 9−8
. param C37 = 2511 e −15
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗∗ ∗∗∗ ∗∗∗ ∗∗∗ ∗∗ ∗∗F i x e d ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗∗ ∗∗∗ ∗∗∗ ∗∗∗
∗ Left source to left e l e c t r o d e : 1−5
. param C1 = 477 e −15
∗ Left strong to left weak : 1−3
. param C11 = 126 e −15
∗ Left strong to right s t r o n g : 1−2
. param C13 =41e −15
∗ Left strong to c a b i n e t : 1−9
. param C35 = 56 e −15
∗ Right stron g to c a b i n e t : 2−9
. param C39 = 62 e −15
∗ L e f t weak t o c a b i n e t : 3−9
. param C41 = 81 e −15
∗ R i g h t weak t o c a b i n e t : 4−9
. param C40 = 53 e −15
∗ Left electrode to c a b i n e t : 5−9
. param C36 = 102 e −15
∗ Right e l e c t r o d e to c a b i n e t : 6−9
. param C38 = 52 e −15
∗ Backp l an e to c a b i n e t :7 −9
. param C42 = 19030 e −15
∗ Left strong to right e l e c t r o d e : 1−6
. param C23 = 27 e −15
∗ Left strong t o b a c k p l a n e : 1−7
. param C25 = 30050 e −15
∗ Left electrode t o b a c k p l a n e : 5−7
. param C26 = 3086 e −15
∗ Left strong t o R i g h t weak : 1−4
. param C33 = 1625 e −15
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗
∗ floor t o b a c k p l a n e : 7−10
. param C43 = 79720 e −15
∗ floor to c a b i n e t : 9−10
. param C44 = 121300 e −15
∗ Left strong to f l o o r : 1−10
442
. param C14 = 321 e −15

∗ Left electrode to f l o o r : 5−10
. param C15 = 401 e −15
∗ Target to floor : ( s h o e ) 8−10
. param C16 = 42400 e −15
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗∗
∗ I n p u t Node C a p a c i t a n c e : Measured
. param C s t r a y = 159 e −12
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗
∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗ S e t by symmetry ∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗∗

. param C2 = {C1}
. param C4 = {C3}
. param C6 = {C5}
. param C7 = {C1}
. param C8 = {C7}
. param C12 = {C11}
. param C17 = {C15}
. param C18 = {C14}
. param C19 = {C14}
. param C20 = {C19}
. param C24 = {C23}
. param C28 = {C26}
. param C29 = {C25}
. param C30 = {C25}
. param C31 = {C30}
. param C32 = {C13}
. param C34 = {C33}
∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗ ∗∗∗ ∗∗ ∗∗ ∗∗
443
A.5. Lamp Sensor Practice
A.5 Lamp Sensor Practice

This Appendix describes the setup, operation and some practical considerations useful
for a working demonstration of the lamp sensor system.
A.5.1 Matlabr Interface and Demonstration
Refer to the code in Appendix A.3.

The PIC microcontroller onboard the lamp sensor is typically programmed with
an “Operating System” (see Appendix A.3.1) that will interface with Matlabr over
an RS-232 (serial) connection. Various Matlabr “applications” were written. Some
examples are included in Appendix A.3. A basic demonstration of the behavior of
the lamp sensor using one of these apps interfaced with the lamp sensor is depicted
in Figure A-24. The plot in Figure A-24 shows data taken from the lamp sensor. The
upper two plots show the same real-time data; the top window auto-zooms, while the
middle window shows the data in a fixed-scale window. The bottom window shows
a history of data corresponding to what Matlabr thought was a detection or an
“event.” The data shown in the upper two windows corresponds to an occupant pass-
ing from one end to the other of the detection field below the lamp. The event history
in the bottom window corresponds to an occupant walking through the detection field
in one direction, then immediately reversing and walking back through the detection
field in the opposite direction.
444
Lampsensor Output
0.08
0.06
Volts
0.04
0.02
−0.02
0 5 10 15 20 25 30 35 40 45 50
0.1
0.05
Volts
−0.05
−0.1
5 10 15 20 25 30 35 40 45 50
0.08
0.06
0.04
Volts
0.02
−0.02
−0.04
0 50 100 150 200 250
Datapoints @ 14 sps
Figure A-24: A screenshot of a Matlabr demonstration output window showing

the lampsensor output voltage. Top: auto-zooming window, Middle: fixed-scale
window, Bottom: Event history window
445
A.5.2 Nulling
The lamp sensor relies on a balanced measurement of the electric fields below the
lamp. When there is no detection, the output of the sensor should be approximately
“nulled” or zero volts. Imbalances in the system either desired (detections of occu-
pants) or undesired cause the lamp sensor output to deviate from that “null-point.”
Figure A-25: A photograph of an adjustable electrode
In practice, it is necessary to null the lamp sensor output by adjusting the relative
depth of the two electrodes. The adjustable electrode shown in Figure A-25 allows
for manual adjustment of the electrode’s depth from the lamp. The depth of the
electrode in Figure A-25 may be adjusted by turning the nylon wing nuts. Nulling
is most easily accomplished by watching the lamp sensor output, e.g. the middle
plot of Figure A-24, while adjusting the depth of one of the electrodes. This process
is iterative, because the adjuster’s hand near the electrode will constitute a strong
detection. Therefore, the adjuster should note the offset while out of the detection
446
field, adjust the electrode depth in one direction and then leave the detection field
again to note the change in offset. The electrode depth can then be adjusted in the
appropriate direction to reduce the offset toward zero volts.
A.5.3 Grounding, Stray Current Return Paths, and Safety

Isolation
The lamp sensor is a quasistatic electric field system. Therefore it relies on closed
circuit paths for measurement of the electric fields below the lamp. In general, there
may not be explicit return paths between the sensing electronics and the signal source
(the lamp). When there is no explicit path, the sensor relies on stray coupling for
signal currents to return to the signal source. From experience and observation of
the lamp sensor behavior both with and without explicit return paths in place, the
stray coupling appears to be both strong and unavoidable. Most notably, the phase
reference amplifier is SE, so that currents must return via the sensor power supply
ground for that measurement to take place. The phase reference signal is largely
unaffected by the presence or lack of an explicit return path.
For experimental or other purposes, it may be necessary to provide an explicit
current return path from the sensor electronics to the signal source. Ultimately, this
requires the direct connection (short circuit or jumper wire) between the sensor power
supply ground (“gnd”) and the lamp ballast ground (“common”). Care must be taken
however, because gnd will typically also be connected to earth ground (“earth”). Be-
cause earth is normally tied directly to the utility neutral wire, that earth connection
also comprises a neutral connection. Therefore, tying gnd to common also ties earth
and therefore neutral to those references. This is a problem when the power supply
for either the sensor electronics or the ballast is not isolated from the utility. In that
case, the ground derived from the utility will be driven to neutral and to line with
a duty cycle determined by the rectifier between the utility and power supply DC
bus. Therefore, unisolated grounds are directly connected to line with some duty
cycle. Connecting them directly to earth and therefore to neutral effectively shorts
447
the utility voltage and will draw damaging levels of current through the intervening
electronics (usually the rectifier for the unisolated power supply). Even without an
explicit earth connection to either power supply, the ground for the serial port is
typically earthed at the PC itself. Therefore, this situation is typical and largely
unavoidable.
The solution is to ensure that all of the power supplies derived from the utility are
isolated with isolation transformers. At the time of this writing, the lamp sensor was
typically powered from an isolated commercial power supply, but some revisions of the
custom lamp ballast were powered directly from the utility. An off-the-shelf 1:1 60 Hz
isolation transformer was typically used to isolate the ballast from the utility in order
to accommodate the short circuit between gnd and common. Practical configurations
of the lamp sensor should ultimately include power supplies that are all isolated.
It is also the case that oscilloscope probe grounds are typically earthed. Therefore,
if a ground-referenced scope measurement is to be made on, for instance, an uniso-
lated ballast, that ballast must first be isolated from the utility with an isolation
transformer.
A.5.4 Modifying Off-the-shelf Fluorescent Lamps
The lamp sensor is made from a commercially available F32T8 fixture designed for
48-inch T8 bulbs. Phillips Alto-series bulbs are typical in our experimental setups.
The original fixture will have a plastic light diffuser panel covering the bulbs. After
this is removed, a long metal ballast cover should be visible in the center of the fixture.
The bulbs should be seated in plastic connectors known as “Tombstones” at each end
of the fixture.
Many modern ballasts are designed for cold-cathode striking, wherein the bulbs
are struck without preheating the filaments. In those cases the filaments are heated by
the bulb current during normal operation. These sorts of fixtures will have “shunted”
tombstones, usually marked with a capital “S” on the back of the package. Each
shunted tombstone shorts together the two connections two each filament. In some
revisions of the custom lamp ballast, filament heating is necessary for proper op-
448
eration. For those ballasts, shunted tombstones must be replaced with standard
un-shunted tombstones.
To install the lamp sensor electronics, remove the metal ballast cover and the
ballast beneath it. In most cases, new holes will need to be drilled in the fixture to
properly mount the dimming ballast. An unpopulated ballast PCB can be used as
a template for drilling. Once holes have been drilled, the dimming ballast can be
mounted using nylon standoffs and screws. Most fixtures will have many knockouts
in the backplane and ends of the fixture for running electrical connections between
the ballast and other boards. If the necessary electronics for the lamp sensor cannot
fit beneath the ballast cover, an electrical project box can be bolted onto the opposite
side of the backplane. Alternatively, electronics can simply rest outside the fixture if
the fixture is mounted on a workbench for experimental purposes. In either case, it is
recommended that the electronics be enclosed in a metal box and that the enclosure
be connected to the power supply ground for the electronics.
A.5.5 Programming the PIC Microcontroller
Programming the lamp sensor board PIC microcontroller can be accomplished with
the Microchipr ’s MPLAB software. A photograph of the lamp sensor board con-
nected to the MPLAB programmer is shown in Figure A-26. A photograph showing
the MPLab connector for the lamp sensor is shown in Figure A-27.
Programming Notes:
• The MPLab in-circuit programmer pin-out for the lamp sensor PCB
through Rev 2 is different from the standard pin-out for MPLab
in-circuit programmers. Two lines must be crossed from the modu-
lar connector to the PCB’s Molex connector. Refer to the MPLab
connector pinout and the lamp sensor PCB and schematics in this
Appendix.
• Do power board during in circuit programming.
• Use Hi-Tech PICC to compile pic code. (.c→.hex)
449
Figure A-26: A photograph of the MPLab ICD 2 programmer puck connected to the
lamp sensor board
• Use MPlab software to program pic. (.hex→onto PIC)
• Jumpers on ICSP jumper headers should be in place so that the pins are shorted
together top to bottom in two columns. These jumpers allow port pins B7 and
B8 to be disconnected from the ICSP Molex if desired in the future.
• The color code for the MPLab connector pin-out is shown in the Table below.
• Note that the blue line is not connected to anything inside the programmer so
it is not used.
With MPLAB and the proper USB drivers for the MPLAB ICD 2 programmer
puck installed, the programming procedure is as follows:
1. Connect the ICD 2 programmer puck to the PC USB port.
450
Signal Color
VPP/MCLR white
VDD black
PGD green
GND red
PGC yellow
Table A.2: MPLab connector pin-out color code.
2. Connect the programmer dongle (molex) to the five-pin programming header

on the senor board.
3. Open MPLAB and the source code file or hex file.
4. Under the “Programmer” menu, go to “Programmer” and select MPLAB ICD

2.
5. Under the “Configure” menu, click “Select Device...” and select the PIC16F877PT.
6. If necessary, click the “BUILD” button to compile the code to generate a .hex
file from the .c file. This .hex file is what is actually copied into the program
memory of the PIC.
7. Under the “Programmer” menu, click “Connect to Programmer”
8. Under the “Programmer” menu, click “Program”
A.5.6 Required PCB Cleaning
If the sensor output appears unusually noisy, then noise or unwanted signals are likely
coupling from the power supply to the input nodes before the front-end amplifier
through flux residue and other oils on the PCB surface. This problem results from
the fact that the front-end amplifier is specifically designed to measure very small
currents, which is an otherwise desirable and intentional design feature. A good
scrubbing with isopropanol followed by a rinse in distilled water (available on tap in
building 13, 2nd floor) has been shown to consistently and significantly resolve this
451
Figure A-27: A photograph of the MPLab ICD 2 connector used for the lamp sensor
revisions 1 and 2.
issue. You can either bake the PCB at low temperature, or use a heat gun to dry it.
- Dan Vickery
452
A.6 Standalone Sensor Software

This appendix includes Matlabr code for operating the standalone sensor system.
The scripts and functions are largely adapted from similar code that was previously
developed for operating the lamp sensor.
A.6.1 Matlabr Detection Pattern Data Collection
sensormatrix.m
This script is an augmented version of dimmerdemo2.m. It has an option to collect a

grid of data from the lamp sensor. sensormatrix.m requires functions:
• collectgrid.m
• getdatapoint.m
• plothelper.m
%% S e n s o r m a t r i x .m i s p r e t t y much t h e same a s s t a n d a l o n e , except pressing

%% ”m” h a v i n g selected the p l o t window will start the grid data collection
%% mode .
f u n c t i o n y = sen sormatri x ( p oi n ts , port , gri d d i men si on x , grid dimensiony)
%% C l e a r e n v i r o n m e n t
close all
clc
%% Check ar gu m en t s
if ( n a r g i n ˜=4)
d i s p ( ’ Usage : s e n s o r m a t r i x ( p o i n t s p e r fr am e , COM p o r t , g r i d x dim . , g r i d y dim . ) ’ )
return
end
%% I n i t i a l i z e some g l o b a l variables
r ef = 5;
figure (2);
linewidth = 2;
format long ;
STATUS = 0 ; LAST EVENT = 0 ;
g o m a s t e r = ’A ’ ;
s t o p m a s t e r = ’B ’ ;
calibr ationlength = 20;
%% I n i t i a l i z e some a r r a y s
collected = [ ] ;
matrix = [ ] ;
453
A.6. Standalone Sensor Software
%% COM P or t H a n d l i n g
p o r t s t r = i n t 2 s t r ( port ) ; %Con ver t COM P or t arg to string
% Close all open serial ports

if s i z e ( ports , 1 ) > 0
end
% D et er m i n e Serial P or t Path ( P l a t f o r m− S p e c i f i c ) :
if i s m a c == 1
s e r i a l p a t h = ’ / dev / t t y . u s b s e r i a l ’ ;
elseif i s u n i x == 1
s e r i a l p a t h = ’ / dev /TTYUSB0 ’ ;
elseif i s p c == 1
%C r e a t e proper serial p at h w i t h p o r t a r g
s e r i a l p a t h = s t r c a t ( ’COM’ , p o r t s t r ) ;
else
d i s p ( ’ Cannot figure ou t serial p o r t p at h . . . . Plese edit the .m f i l e m an u al l y . ’ ) ;
return ;
end
% Define the serial port

s= s e r i a l ( s e r i a l p a t h , ’ BaudRate ’ , 9600 , ’ D at aBi t s ’ , ...
8, ’ Parity ’ , ’ none ’ , ’ StopBits ’ , 1, ’ terminator ’ , ’ LF ’ , . . .
’ t i m eou t ’ , 2 ) ; % c r e a t e a serial port object
%Open s e r i a l port d e f i n e d ab ove
fopen ( s ) ;
%% C a l i b r a t i o n to determine noise floor

while ( length ( c a l i b r a t e )) < c a l i b r a t i o n l e n g t h
datapoint = getdatapoint ( s , gom ast er , ref );
c a l i b r a t e = horzcat ( c a lib r a t e , datapoint ) ;
end
calibr at e = calib ra te (35: length ( calibr at e ) ) ;

%% The Main Loop

while (1)
% if m is pressed , e n t e r data matrix c o l l e c t i o n mode

%E n t e r m a t r i x mode i f you p r e s s m
if st r cm p ( g e t ( 2 , ’ c u r r e n t c h a r a c t e r ’ ) , ’ m’ )
clc
% The f u n c t i o n that prints a grid of deteciton data
c o l l e c t g r i d ( grid dimensionx , grid dimensiony , s, gom ast er , ref );
stopasync ( s ) ;
fclose (s );
delete ( s );
clear s;
break
% if q is pressed , quit
%S t op t h e l o o p if you p r e s s q
elseif st r cm p ( g e t ( 2 , ’ c u r r e n t c h a r a c t e r ’ ) , ’ q ’ )
close (2); % Cl ean up
454
stopasync ( s ) ;
fclose (s );
delete ( s );
clear s;
save printbuf ;
break
end
% Otherwise continue to gen er at e the scrolling p l o t window

plothelper
end
455
collectgrid.m
This function collects sensor data corresponding to a grid of points in the detection
field. It displays visual cues on the monitor so that the occupant can operate the
experiment alone. Each data point is the time-averaged sensor output voltage for a
window that is typically a few seconds in duration.
%% C o l l e c t g r i d .m i s the script that gets the grid data .
%% R e c a l l and p l o t data as follows
%% I n t h e directory wh er e t h e d a t a is saved :
%% >> l o a d grid result ; s u r f (X, Y, Z ) ;
function y = c o l l e c t g r i d ( grid dimensionx , grid dimensiony , s , gom ast er , ref )
%% C l o s e t h e display figure
close all
gridlvl = [ ] ;
datapts = [ ] ;
%% I n t i a l i z e some v a r i a b l e s
dataptlength = 30;
x s c a l e = 9/12; % f e e t per step
y s c a l e = 9/12; % f e e t per step
%% D i s p l a y Start
f1 = figure (1);
d i s p l a y ( ’ Move t o first p o i n t on g r i d . ’ )
u i c o n t r o l ( f 1 , ’ S t y l e ’ , ’ Text ’ , ’ S t r i n g ’ , ’ 1 ’ , ’ F o n t S i z e ’ , 9 4 , ’ u n i t s ’ , . . .
’ N or m al i zed ’ , ’ P o s i t i o n ’ , [ 0 .5 1 .4])
u i c o n t r o l ( f 1 , ’ b a c k g r o u n d c o l o r ’ , [ 0 1 0 ] , ’ u n i t s ’ , ’ N or m al i zed ’ , . . .
’ Position ’ , [ 0 0 1 .2])
pause ( 2 ) ;
%% The d a t a collection loop

%i t e r a t e for all p o i n t s on a g r i d x g r i d matrix
w h i l e ( l e n g t h ( g r i d l v l ) ) < g r i d d i m e n s i o n x∗ g r i d d i m e n s i o n y
% Display instruction to user
d i s p l a y ( [ ’ S t an d Still ! point : ’ , num2str ( l e n g t h ( g r i d l v l ) + 1 ) , ’/ ’ , ...
num2str ( g r i d d i m e n s i o n x∗ g r i d d i m e n s i o n y ) ] )
u i c o n t r o l ( f 1 , ’ S t y l e ’ , ’ Text ’ , ’ S t r i n g ’ , num2str ( l e n g t h ( g r i d l v l ) + 1 ) , . . .
’ F o n t S i z e ’ , 9 4 , ’ u n i t s ’ , ’ N or m al i zed ’ , ’ P o s i t i o n ’ , [ 0 .5 1 .4])
u i c o n t r o l ( f 1 , ’ S t y l e ’ , ’ Text ’ , ’ S t r i n g ’ , ’ S t an d S t i l l ’ , ’ F o n t S i z e ’ , 6 0 . . .
, ’ u n i t s ’ , ’ N or m al i zed ’ , ’ P o s i t i o n ’ , [ 0 .25 1 .2])
’ Position ’ , [ 0 0 1 .2])
pause ( 1 ) ;
%c o l l e c t dataptlength samples of d a t a a t on e p o i n t on g r i d
for j =1: d a t a p t l e n g t h
j
%c o l l e c t d a t a p o i n t fr om t h e s e n s o r
d atap ts = h orzcat ( datapts , datapoint ) ;
end
m ean val u e = mean ( d a t a p t s ) ; % t i m e a v e r a g e t h e d a t a a t on e p o i n t on g r i d
456
display ( [ ’ I recorded ’ , num2str ( 1 0 0 0 ∗ m ean val u e ) ’ mV’ ] ) ;

display ( ’ ’) ;
b eep ( )
g r i d l v l = horzcat ( g r id l v l , m ean val u e ) ; % C o n c a t e n a t e o n t o t h e results array
if l e n g t h ( g r i d l v l ) < g r i d d i m e n s i o n x∗ g r i d d i m e n s i o n y
d i s p l a y ( ’ Move t o n e x t p o i n t on g r i d ’ ) % D i s p l a y instruction to user
u i c o n t r o l ( f 1 , ’ S t y l e ’ , ’ Text ’ , ’ S t r i n g ’ , ’ Move . ’ , ’ F o n t S i z e ’ , 6 0 , . . .
’ u n i t s ’ , ’ N or m al i zed ’ , ’ P o s i t i o n ’ , [ 0 .25 1 .2])
’ Position ’ , [ 0 0 1 .2])
i f mod ( ( l e n g t h ( g r i d l v l ) ) , g r i d d i m e n s i o n x ) == 0 % Time d e l a y
pause ( 4 ) ; % Greater time delay if a t t h e end o f a g r i d row .
else
p a u s e ( 2 ) ; % S h o r t t i m e d e l a y b et ween p o i n t s .
end
end
% clc
datapts = [ ] ; % reset the results array
end
%% D i s p l a y Done
d i s p l a y ( ’ Data collection done . ’ )
close ( f1 )
%% C e n t e r t h e results
g r i d l v l = g r i d l v l − 1. 00001∗ max ( g r i d l v l ) ;
%% Format v e c t o r into matrix

grid result = [ ] ;
for i = 1: grid dimensiony
x result = [ ] ;
for j = 1: grid dimensionx
x r e s u l t = horzcat ( x re s u lt , gridlvl (1));
gr i d l v l = g r i d l v l (2: length ( g r i d l v l ) ) ;
end
g ri d r es u l t = vertcat ( grid resu lt , x result );
end
%% P l o t t i n g
fig ure (3)
[ X, Y ] = m e s h g r i d ( 1 : g r i d d i m e n s i o n x , 1: grid dimensiony ) ;
X = X. ∗ x s c a l e ;
Y = Y. ∗ y s c a l e ;
Z = grid result ;
s u r f (X, Y, Z ) ;
% s u r f (X, Y, 2 0 ∗ l o g 1 0 ( ab s ( Z ) ) ) ;
%% P l o t F o r m a t t i n g
title ( ’ ’);
xlabel ( ’x Position ( ft .) ’);
ylabel ( ’y Position ( ft .) ’);
% z l a b e l ( ’ R esp on se ( db mV) ’ ) ;
z l a b e l ( ’ R esp on se (V ) ’ ) ;
box
%% S ave d a t a
save grid result
end
457
getdatapoint.m
This function polls the lampsensor for a single data point (4 bytes). The same code
is incorporated directly in other scripts, for instance, plotdimmer.m.
%% Th i s function collects on e d a t a b y t e fr om t h e sensor b oar d
function datapoint = getdatapoint ( s , gom ast er , ref )
collected = [ ] ;
matrix = [ ] ;
%% Send t h e command t o t h e sensor

%% Read t h e serial port recv buffer four times for four bytes
f o r k =1:4 %C o l l e c t 4 b y t e s fr om t h e ADC
end
%% T r a n s l a t e the 4 data b ytes into a signed integer

MSB = ( 2 ˆ 1 6 ) ∗ m a t r i x ( 1 ) ; NSB = ( 2 ˆ 8 ) ∗ m a t r i x ( 2 ) ; LSB = m a t r i x ( 3 ) ; SIGN = . . .
matrix ( 4 ) ;
i f SIGN==0
d a t a p o i n t = −(16777215 −( MSB+NSB+LSB ) ) ;
else
end
%% R et u r n t h e v a l u e of the datapoint in Volts

datapoint = r e f ∗ datapoint /16777215;
end
458
plothelper.m
This script is similar to plotdimmer.m. It calls the getdatapoint.m function to poll

the lampsensor for a data point instead of incorporating that code directly in the
script.
%% A sub−s c r i p t that collects d a t a fr om t h e lamp s e n s o r and p l o t s it .
%% C o l l e c t the next data p oi n t

%% S c r o l l the print buffer

printbuf = horzcat ( printbuf ( 2 : points ) , datapoint ) ;
%% P l o t t i n g
%% F i x e d S c a l e ( Mi d d l e ) Window
f i x e d s c a l e = 2∗ r e f ∗1 e −2; %S e t up t h e fixed s c a l e window
subplot (3 ,1 ,2) %f o r the middle p l ot
axis ([1 p oi n t s −f i x e d s c a l e fixedscale ]);
%% Auto s c a l e ( Top ) Window

subplot (3 ,1 ,1)
%% Event D e t e c t i o n
format short
VRANGE = ( max ( p r i n t b u f )−min ( p r i n t b u f ) ) ;
AVG = sum ( p r i n t b u f ) / ( p o i n t s ) ;
VACrms uV = ( ( ( 1 / p o i n t s ) ∗ sum ( ( p r i n t b u f −AVG) . ∗ ( p r i n t b u f −AVG) ) ) ˆ 0 . 5 ) / ( 1 e −6)
i f VRANGE<m i n s c a l e %I f there i s no e v e n t , zoom i n t o t h e minimum s c a l e

axis ([1 p o i n t s ( min ( p r i n t b u f ) − m i n s c a l e ) ( max ( p r i n t b u f ) + m i n s c a l e ) ] ) ;
STATUS = ’ Q u i e t ” shhhhhh ” ’ ;
if l e n g t h ( event ) < 6 %%%Event d i s p l a y starts here :
%I f t h e window is n ot a u t o s c a l e d
event = ( [ ] ) ; %assume t h e e v e n t is o v e r and p r i n t it .
%But if i t ’ s too s h o r t don ’ t actually print it ( g o t o end )
else
%% Event H i s t o r y ( Bottom ) Window

subplot (3 ,1 ,3) %I n t h e bottom p l o t
%Get some v a l u e s t o help plot it i n a c o o l way .
l e n g t h e v e n t = l e n g t h ( event ) ;
%These 4 v a l u e s a r e for the direction detection
e v e n t l e f t = event ( 1 : f l o o r ( 0 . 5 ∗ l e n g t h e v e n t ) ) ;
a v g e v e n t l e f t = ( sum ( e v e n t l e f t ) ) / l e n g t h ( e v e n t l e f t ) ;
e v e n t r i g h t = event ( c e i l ( 0 . 5 ∗ l e n g t h e v e n t ) : l e n g t h e v e n t ) ;
a v g e v e n t r i g h t = ( sum ( e v e n t r i g h t ) ) / l e n g t h ( e v e n t r i g h t ) ;
%Make a bookend for the plot so it looks better
bookend length = f l o o r (0.3∗ length event ) ;
a v g e v e n t = ( sum ( e v e n t ( 1 : l e n g t h e v e n t ) ) ) / ( l e n g t h e v e n t ) ;
%Glue t h e b ooken d s o n t o t h e e v e n t
event = h orzcat ( ( ones ( 1 , b ooken d l en gth ) ) . ∗ avgevent , ...
event , ( ones ( 1 , b ooken d l en gth ) ) . ∗ avgevent ) ;
%p l o t t h e wh ol e e v e n t in red in the l a s t window
459
p l o t ( event , ’r ’ , ’ linewidth ’ , linewidth )

a x i s auto ; %Auto s c a l e t h e e v e n t window
event = ( [ ] ) ; %r e s e t the event vector
end %%%Event d i s p l a y en d s h e r e
else
plot ( printbuf , ’ linewidth ’ , linewidth )
a x i s auto ;
%And c o l l e c t the event data p o i n t s
event = horzcat ( event ( 1 : ( l e n g t h ( event ) ) ) , datapoint ) ;
STATUS = ’ Event ’ ; %A l s o p r i n t ’ Event ’
end
drawnow
460
A.7 Fully-Differential Amplifier Detailed Deriva-

tions
A.7.1 Derivation of Transconductances using the Virtual Short-

ckt. Approximation
Refer to Figure 2-6(c).
Definitions:
i+ − i−
iid ≡ iic ≡ i+ + i− (A.1)
2
∆Zf + Zf ac ∆Zf
ed ≡ −iic ec ≡ −iid (A.2)
2(1 + ad ) 2
Zdm ≡ Z1 + Z2 Zcm ≡ Z1 ||Z2 + Zc (A.3)
!
2Zf + 12 ∆Zf ac Zf
Zd ≡ Zc ≡ (A.4)
(1 + ad ) 2
(Z1 + Z2 )
∆Z ≡ Z1 − Z2 Z≡ (A.5)
2
(Zf 1 + Zf 2 )
∆Zf ≡ Zf 1 − Zf 2 Zf ≡ (A.6)
2
′ 1
vsd ≡ vsd (A.7)
2
Circuit constraints:
(vsc + 12 vsd − ecc )

i+ = (A.8)
Z1
1
(vsc − 2 vsd − ecc )
i− = (A.9)
Z2
ecc = ec + (i+ i− )Zc (A.10)
461
A.7. Fully-Differential Amplifier Detailed Derivations
Ydd Derivation:

iid
Ydd ≡ . (A.11)
vsd vsc =0
( 12 vsd − ecc )
i+ = (A.12)
Z1
( 12 vsd − ecc )
i− = . (A.13)
Z2

′ 1 1 1 1
2iid = vsd + + ecc − +
Z1 Z2 Z1 Z2
(A.14)
′ 1 ∆Z
= vsd + ecc .
Z1 ||Z2 Z1 Z2
Also,
ecc = ec + (i+ + i− )Zc

′ ′
vsd − ecc −vsd − ecc
(A.15)
= ec + + Zc .
Z1 Z2
so that,
Zc ∆Zf ′ ∆ZZc
ecc 1 + =− iid − vsd . (A.16)
Z1 ||Z2 2 Z1 Z2

∆Zf ′ ∆ZZc Z1 ||Z2
ecc = − iid + vsd . (A.17)
2 Z1 Z2 Z1 ||Z2 + Zc
Combining (A.14) and (A.17)

′ 1 ∆Z ∆ZZc Z1 ||Z2 ∆Z ∆Zf Z1 ||Z2
2iid = vsd − − iid
Z1 ||Z2 Z1 Z2 Z1 Z2 (Z1 ||Z2 + Zc ) Z1 Z2 2 (Z1 ||Z2 + Zc )
(A.18)
Collecting terms

∆Z∆Zf Z1 ||Z2 ′ 1 ∆Z ∆ZZc Z1 ||Z2
iid 2+ = vsd − (A.19)
2Z1 Z2 (Z1 ||Z2 + Zc ) Z1 ||Z2 Z1 Z2 Z1 Z2 (Z1 ||Z2 + Zc )
462
′
Recall that vsd = 12 vsd . This leads to a numerator:
1 ∆Z 2 Zc Z1 ||Z2
Ydd,num = − 2 2
Z1 ||Z2 Z1 Z2 (Z1 ||Z2 + Zc )
and a denominator
∆Z∆Zf Z1 ||Z2
Ydd,den = 4 + .
Z1 Z2 (Z1 ||Z2 + Zc )
We recognize the quantity (Z1 ||Z2 +Zc ) as the impedance seen by a purely CM voltage
driving a purely CM input current and rename it Zcm . Then, aiming to eliminate
second-order terms from the numerator, we decompose Z1 ||Z2 and simplify:
Z1 + Z2 ∆Z 2 Zc
Ydd,num = − .
Z1 Z2 Z1 Z2 (Z1 + Z2 )Zcm
Now, recognizing the term (Z1 + Z2 ) as the impedance seen by a purely DM voltage
driving a purely DM input current, we rename it Zdm . Identifying Zdm and combining
terms in the numerator leads to
(Z1 + Z2 )Zdm Zcm − ∆Z 2 Zc

Ydd,num = .
Z1 Z2 Zdm Zcm
Identifying Zcm in the denominator leads to
∆Z∆Zf Z1 ||Z2
Ydd,den = 4 + .
Z1 Z2 Zcm
Moving Zdm Zcm Z1 Z2 from the numerator to the denominator leads to
Ydd,num = (Z1 + Z2 )Zdm Zcm − ∆Z 2 Zc

∆Z∆Zf Z1 ||Z2
Ydd,den = 4+ Zdm Zcm Z1 Z2 .
Z1 Z2 Zcm
Identifying Z1 ||Z2 /Z1Z2 as 1/Zdm and multiplying the denominator through gives
Ydd,den = 4Zdm Zcm Z1 Z2 + Z1 Z2 ∆Z∆Zf .
463
Collecting terms,
Ydd,den = Z1 Z2 (4Zdm Zcm + ∆Z∆Zf ).
Suspecting a more simple result, we expand the Zdm and Zcm terms in the numerator,
temporarily increasing the expression’s entropy:
Ydd,num = Z1 Z1 ||Z2 + 2Z1 Z2 Z1 ||Z2 + 4Z1 Z2 Zc + Z2 Z1 ||Z2 .
Dividing common factors and collecting terms leads to
Ydd,num = Z1 + 2Z1 Z2 + Z2 + 4Zc (Z1 + Z2 )
Ydd,den = (4Zdm Zcm + ∆Z∆Zf )(Z1 + Z2 ).
Factoring the numerator and identifying Zdm and Zcm effectively “applies mental
energy” to the expression and reduces its entropy [31]:
2
Zdm + 4Zc Zdm
Ydd = .
(4Zdm Zcm + ∆Z∆Zf )(Z1 + Z2 )
Dividing out the common factor of Zdm = Z1 + Z2 in the numerator and denominator
gives
Zdm + 4Zc
Ydd = ,
4Zdm Zcm + ∆Z∆Zf
which can be rewritten to match the result in (2.85) using the definitions of Zdm and
Zc in (2.65),
Z + Zf
Ydd = 2 .
Ydc Derivation:

iic
Ydc ≡ . (A.20)
vsd vsc =0
464
( 21 vsd − ecc )
i+ = (A.21)
Z1
1
( vsd − ecc )
i− = 2 . (A.22)
Z2
′
′
vsd − ecc vsd − ecc
iic = −
Z1 Z2

′ 1 1 1 1
= vsd − − ecc + (A.23)
Z1 Z2 Z1 Z2

′ −∆Zf 1
= vsd − ecc
Z1 Z2 Z1 ||Z2
Also,
ecc = ec + iic Zc

∆Zf i+ − i−
=− + iic Zc (A.24)
2 2
′ ′

∆Zf 1 vsd − ecc vsd + ecc
=− + + iic Zc
2 2 Z1 Z2
so that,

∆Zf 1 ∆Zf 1 ′ ∆Zf 1 1
ecc 1 − + = iic Zc − vsd + (A.25)
4 Z1 4 Z2 4 Z1 Z2
and
−1
′ ∆Zf 1 ∆Zf 1 1
ecc = iic Zc − vsd 1+ −
4 Z1 ||Z2 4 Z2 Z1
(A.26)
′ ∆Zf 4Z1 Z2
= iic Zc − vsd
4Z1 ||Z2 4Z1 Z2 + ∆Zf ∆Z
Combining,

′ −∆Z 1 ∆Zf Z1 Z2
iic =vsd +
Z1 Z2 Z1 ||Z2 Z1 ||Z2 (4Z1 Z2 + ∆Zf ∆Z)
(A.27)
−Zc 4Z1 Z2
+ iic
Z1 ||Z2 4Z1 Z2 + ∆Zf ∆Z
465

4Zc Z1 Z2 ′ ∆Z ∆Zf Z1 Z2
iic 1 + = vsd − +
Z1 ||Z2 (4Z1 Z2 + ∆Zf ∆Z) Z1 Z2 (Z1 ||Z2)2 (4Z1Z2 + ∆Zf ∆Z)
(A.28)
Leading to a numerator:

1 −∆Z ∆Zf Z1 Z2
Ydc,num = + 2
(A.29)
2 Z1 Z2 (Z1 ||Z2 ) (4Z1 Z2 + ∆Zf ∆Z)
and a denominator:
4Zc Z1 Z2
Ydc,den = 1 + (A.30)
Z1 ||Z2 (4Z1Z2 + ∆Zf ∆Z)
Expanding Z1 ||Z2 once, Z1 Z2 divides out,

1 −∆Z ∆Zf (Z1 + Z2 )
Ydc,num = + (A.31)
2 Z1 Z2 (Z1 ||Z2)(4Z1 Z2 + ∆Zf ∆Z)
Expanding Z1 ||Z2 again in the numerator

1 −∆Z ∆Zf (Z1 + Z2 )2
Ydc,num = + (A.32)
2 Z1 Z2 (Z1 Z2 )(4Z1Z2 + ∆Zf ∆Z)
Expanding Z1 ||Z2 once, Z1 Z2 divides out of the denominator,
4Zc (Z1 + Z2 )
Ydc,den = 1 + (A.33)
(4Z1 Z2 + ∆Zf ∆Z)
Combining fractions in the numerator
−∆Z
!
1 Z1 Z2
(Z1 Z2 )(4Z1 Z2 + ∆Zf ∆Z) + ∆Zf (Z1 + Z2 )2
Ydc,num = (A.34)
2 (Z1 Z2 )(4Z1 Z2 + ∆Zf ∆Z)
and the denominator
(4Z1 Z2 + ∆Zf ∆Z) + 4Zc (Z1 + Z2 )

Ydc,den = (A.35)
(4Z1 Z2 + ∆Zf ∆Z)
466
(4Z1 Z2 + ∆Zf ∆Z) divides out yielding
−∆Z
!
1 Z1 Z2
(Z1 Z2 )(4Z1 Z2 + ∆Zf ∆Z) + ∆Zf (Z1 + Z2 )2
Ydc,num = (A.36)
2 (Z1 Z2 )
and
Ydc,den = (4Z1 Z2 + ∆Zf ∆Z) + 4Zc (Z1 + Z2 ) (A.37)
Replacing Z1 Z2 with Z1 ||Z2(Z1 + Z2 ) and recognizing Z1 + Z2 as Zdm , in the denom-

inator yields
Ydc,den = 4Z1 ||Z2Zdm + ∆Zf ∆Z + 4Zc Zdm

(A.38)
= 4Zdm (Z1 ||Z2 + Zc ) + ∆Zf ∆Z
and recognizing (Z1 ||Z2 + Zc ) as Zcm yields
Ydc,den = 4Zdm Zcm + ∆Zf ∆Z (A.39)
Expanding ∆Z and ∆Zf in the numerator temporarily increases the expressions en-
tropy
Z2 −Z1
!
1 Z1 Z2
(Z1 Z2 )(4Z1 Z2 + (Zf 1 − Zf 2 )(Z1 − Z2 )) + (Zf 1 − Zf 2 )(Z1 + Z2 )2
Ydc,num =
2 (Z1 Z2 )
(A.40)
Expansion and canceling of terms leads to
Ydc,num = 2(−∆Z + ∆Zf ) (A.41)
and
−∆Z + ∆Zf
Ydc = 2 (A.42)
4Zdm Zcm + ∆Zf ∆Z
467
Ycd Derivation:

iid
Ycd ≡ . (A.43)
vsc vsd =0
(vsc − ecc )
i+ = (A.44)
Z1
(vsc − ecc )
i− = . (A.45)
Z2

vsc − ecc vsc − ecc
2iid = −
Z1 Z
2 (A.46)
−∆Zf ∆Z
= vsc + ecc
Z1 Z2 Z1 Z2
Also,
ecc = ec + (i+ + i− )Zc

∆Zf
=− iid + (i+ + i− )Zc (A.47)
2

∆Zf (vsc − ecc ) (vsc − ecc )
=− iid + + Zc
2 Z1 Z2
so that,
Zc ∆Zf Zc
ecc 1 + =− iid + vsc (A.48)
Z1 ||Z2 2 Z1 ||Z2

∆Zf Zc Z1 ||Z2
ecc = − iid + vsc (A.49)
2 Z1 ||Z2 Z1 ||Z2 + Zc
Combining

∆Z ∆Z Zc ∆Zf Z1 ||Z2 ∆Z
2iid = vsc − + + iid −
Z1 Z2 Z1 Z2 (Z1 ||Z2 + Zc ) 2 (Z1 ||Z2 + Zc ) Z1 Z2
(A.50)
∆Zf ∆ZZ1 ||Z2 ∆Z Zc
iid 2 + = vsc −1 . (A.51)
2Z1 Z2 (Z1 ||Z2 + Zc ) Z1 Z2 (Z1 ||Z2 + Zc )
468

∆Z Zc
Ycd,num = −1 (A.52)
Z1 Z2 Z1 ||Z2 + Zc
∆Zf ∆ZZ1 ||Z2

Ycd,den = 2 + (A.53)
2Z1 Z2 (Z1 ||Z2 + Zc )
Expanding Z1 ||Z2 , (Z1 Z2 ) divides out of the denominator
∆Z∆Zf
Ycd,den = 2 + . (A.54)
2(Z1 + Z2 )(Z1 ||Z2 + Zc )
Recognizing (Z1 + Z2 ) as Zdm and (Z1 ||Z2 + Zc ) as Zcm ,
∆Z∆Zf
Ycd,den = 2 + . (A.55)
2Zdm Zcm
Combining fractions
2Zdm Zcm + 21 ∆Z∆Zf
Ycd,den = . (A.56)
Zdm Zcm
and multiplying the denominator by 2/2 reveals the common denominator term from
the other transconductances

Ycd,den = . (A.57)
2Zdm Zcm
Combining fractions in the numerator leads to

∆Z Zc − Z1 ||Z2 − Zc
Ycd,num =
Z1 Z2 Zcm
(A.58)
∆Z Z1 ||Z2
=−
Z1 Z2 Zcm
Expanding Z1 ||Z2 , Z1 Z2 divides out
∆Z
Ycd,num = −
(Z1 + Z2 )Zcm
(A.59)
∆Z
=−
Zdm Zcm
469
so that the final result is
∆Z
Ycd = −2 (A.60)
Ycc Derivation:

iic
Ycc ≡ . (A.61)
vsc vsd =0
(vsc − ecc )
i+ = (A.62)
Z1
(vsc − ecc )
i− = . (A.63)
Z2
vsc − ecc vsc − ecc

iic = +
Z1 Z
2
1 1 1 1
= vsc + − ecc + (A.64)
Z1 Z2 Z1 Z2

1 1
= vsc − ecc
Z1 ||Z2 Z1 ||Z2
Also,
ecc = ec + iic Zc

∆Zf i+ − i−
=− + iic Zc (A.65)
2 2

∆Zf vsc − ecc vsc − ecc
=− − + iic Zc
4 Z1 Z2
so that,

∆Zf ∆Zf −∆Zf 1 1
ecc 1− + = vsc − + iic Zc (A.66)
4Z1 4Z2 4 Z1 Z2
and,
∆Zf ∆Z 4Z1 Z2
ecc = vsc + iic Zc (A.67)
4 Z1 Z2 4Z1 Z2 + ∆Zf ∆Z
470
Combining,

1 1 ∆Zf ∆Z
iic = vsc −
Z1 ||Z1 Z1 ||Z2 4Z1 Z2 + ∆Zf ∆Z
(A.68)
Zc 4Z1 Z2
+ iic −
Z1 ||Z2 4Z1 Z2 + ∆Zf ∆Z

4Zc Z1 Z2 1 1 ∆Zf ∆Z
iic 1 + = vsc −
Z1 ||Z2 (4Z1 Z2 + ∆Zf ∆Z) Z1 ||Z2 Z1 ||Z2 (4Z1 Z2 + ∆Zf ∆Z)
(A.69)
1 1 ∆Zf ∆Z
Ycc,num = − (A.70)
Z1 ||Z2 Z1 ||Z2 4Z1 Z2 + ∆Zf ∆Z
and a denominator:
4Zc Z1 Z2
Ycc,den = 1 + (A.71)
Z1 ||Z2 (4Z1 Z2 + ∆Zf ∆Z)
Combining fractions in the denominator
Z1 ||Z2 (4Z1 Z2 + ∆Zf ∆Z) + 4Zc Z1 Z2

Ycc,den = (A.72)
Z1 ||Z2(4Z1 Z2 + ∆Zf ∆Z)
Z1 ||Z2 divides out between the numerator and denominator.
∆Zf ∆Z
Ycc,num = 1 − (A.73)
4Z1 Z2 + ∆Zf ∆Z
Z1 ||Z2 (4Z1 Z2 + ∆Zf ∆Z) + 4Zc Z1 Z2

Ycc,den = (A.74)
(4Z1 Z2 + ∆Zf ∆Z)
Then, combining fractions in the numerator yields
4Z1 Z2 + ∆Zf ∆Z − ∆Zf ∆Z

Ycc,num =
4Z1 Z2 + ∆Zf ∆Z
(A.75)
4Z1 Z2
=
4Z1 Z2 + ∆Zf ∆Z
471
so that (4Z1 Z + ∆Zf ∆Z) divides out between the numerator and denominator
Ycc,num = 4Z1 Z2 (A.76)
Ycc,den = Z1 ||Z2 (4Z1 Z2 + ∆Zf ∆Z) + 4Zc Z1 Z2 (A.77)
Expanding Z1 ||Z2 in the denominator,
Z1 Z2
Ycc,den = (4Z1 Z2 + ∆Zf ∆Z) + 4Zc Z1 Z2 (A.78)
Z1 + Z2
Z1 Z2 divides out between the numerator and denominator
Ycc,num = 4 (A.79)
1
Ycc,den = (4Z1Z2 + ∆Zf ∆Z) + 4Zc (A.80)
Z1 + Z2
Combining fractions in the denominator
1
Ycc,den = (4Z1 Z2 + ∆Zf ∆Z + 4Zc (Z1 + Z2 ))
Z1 + Z2
(A.81)
1
= (4Z1 Z2 + ∆Zf ∆Z + 4Zc (Z1 + Z2 ))
Zdm
so that
Ycc,num = 4Zdm (A.82)
Ycc,den = (4Z1 Z2 + ∆Zf ∆Z) + 4Zc (Z1 + Z2 ) (A.83)
Rearranging the denominator
Ycc,den = 4(Z1 Z2 + Zc (Z1 + Z2 )) + ∆Z∆Zf

Z1 Z2
= 4( + Zc )(Z1 + Z2 ) + ∆Z∆Zf
Z1 + Z2 (A.84)
= 4(Z1 ||Z2 + Zc )(Z1 + Z2 ) + ∆Z∆Zf
= 4Zcm Zdm + ∆Z∆Zf
472
and recognizing 4Zdm in the numerator as 8Z, yields the final result
Z
Ycc = 8 (A.85)
4ZcmZdm + ∆Z∆Zf
473
A.7.2 Derivation of Ycd′ using the corrected circuit model
Refer to Figure 2-6(d)
Definitions:
ed = Zed Ycc vsc ec = Zec Ycdvsc (A.86)

∆Zf + Zf ac ∆Zf
Zed ≡ − Zec ≡ − (A.87)
2(1 + ad ) 2
Circuit constraints:
ed
iid = ied +
4Zc
= ied + i′id (A.88)
iic = i+ + i− = i′ic
where
1
i′id ≡ (i′+ − i′− ) (A.89)
2
i′ic ≡ i′+ + i′− = iic (A.90)
and the current through the added DM voltage element is
ied = i+ − i′+
(A.91)
= i′− − i− .
Applying KVL results in two equations:
vsc − i+ Z1 − ed − i′− 2Zc − ec = 0 (A.92)
vsc − i− Z2 + ed − i′+ 2Zc − ec = 0. (A.93)
474
Ycd′ Derivation:
Adding (A.92) and (A.93) leads to:
0 = 2vsc − i+ Z1 − i− Z2 − 2Zc iic − 2ec
= 2vsc − i+ Z1 + Z2 (2iid − i+ ) − 2Zc iic − 2ec (A.94)
= 2vsc − i+ Z1 + Z2 (2Ycd′ vsc − i+ ) − 2Zc Ycc vsc − 2Zec Ycd′ vsc
so that
2vsc (1 + Z2 Ycd′ − Zc Ycc − Zec Ycd′ ) = i+ (Z1 + Z2 ), (A.95)
while subtracting the two leads to:
0 = −i+ Z1 + i− Z2 − 2ed + 2Zc (−i′− + i′+ )
= −i+ Z1 + i− Z2 − ed (A.96)
= −i+ Z1 + i− Z2 − Zed Ycc vsc
so that
i+ Z1 + Zed Ycc vsc
i− = . (A.97)
Z2
Eliminating i− and i+ in favor of iid :
i+ − i−
iid =
2
1 i+ Z1 + Zed Ycc vsc
= i+ −
2 Z
2 (A.98)
1 Z1 1 Zed Ycc vsc
= i+ 1 − −
2 Z2 2 Z2

1 ∆Z Zed Ycc vsc
= − i+ −
2 Z2 2Z2
so that
Zed Ycc vsc 2Z2
i+ = iid + − . (A.99)
2Z2 ∆Z
475
Plugging i+ into (A.95) yields

2Z2 Zed Ycc vsc
2vsc (1 + Z2 Ycd′
− Zc Ycc − Zec Ycd′ )
= 2Z − iid +
∆Z 2Z2

2Z2 ′ Zed Ycc vsc
= 2Z − Ycd vsc + (A.100)
∆Z 2Z2

′ ′ 2Z2 ′ Zed Ycc
2(1 + Z2 Ycd − Zc Ycc − Zec Ycd) = 2Z − Ycd + .
∆Z 2Z2
Collecting terms,

4ZZ2 2Z
Ycd′ 2Z2 − 2Zec + = Ycc −Zed + 2Zc − 2 (A.101)
∆Z ∆Z
and solving,
2Z
Ycc (−Zed ∆Z + 2Zc ) − 2
Ycd′ = 4ZZ2
2Z2 − 2Zec + ∆Z (A.102)
Ycc (−Zed 2Z + 2Zc ∆Z) − 2∆Z
= .
2Z2 ∆Z − 2Zec ∆Z + 4ZZ2
∆Zf
The denominator of Ycd′ can be made symmetric by expanding Zec = − 2
, ∆Z =
Z1 − Z2 and ∆Zf = Zf 1 − Zf 2 . The denominator becomes
′ 1 Z1 + Z2
Ycd,den = 2Z2 (Z1 − Z2 ) + (Zf 1 − Zf 2 )(Z1 − Z2 ) + 4 Z2
2 2
1 1 1 1
= 4Z1 Z2 + Zf 1 Z1 − Zf 1 Z2 − Z1 Zf 2 + Z2 Zf 2 (A.103)
2 2 2 2
1
= 4Z1 Z2 + ∆Z∆Zf
2
and Ycd′ becomes

Ycc (−Zed 2Z + 2Zc ∆Z) − 2∆Z
Ycd′ = . (A.104)
4Z1 Z2 + 12 ∆Z∆Zf
Expanding Zed and Zc in the numerator leads to
∆Zf +ac Zf
Ycc (Z 1+ad
+ Zf ∆Z) − 2∆Z
Ycd′ = (A.105)
4Z1 Z2 + 12 ∆Z∆Zf
476
Which can be rewritten
∆Zf +ac Zf
Ycc (Z 1+ad
+ Zf ∆Z) − 2∆Z
Ycd′ = . (A.106)
4Z1 Z2 + 12 ∆Zf ∆Z
′
Ycds Derivation:
With the small-mismatch approximations,
∆Zf << Zf 1 , Zf 2 , Zf (A.107)
∆Z << Z1 , Z2 , Z. (A.108)
1
Ycc ≈ . (A.109)
Zcm
′
From (A.106), Ycds can be simplified with the approximations in (A.107)-(A.109) as
follows:
1 ac Zf
Zcm
(Z 1+a + Zf ∆Z) − 2∆Z
Ycd′ ≈ d
. (A.110)
4Z1 Z2
Combining fractions
a Z
c f
(Z 1+a + Zf ∆Z) − 2∆ZZcm
Ycd′ ≈ d
4Z1 Z2 Zcm
(A.111)
ac Zf Zf
(Z 1+a d
+ Zf ∆Z) − 2∆Z(Z1 ||Z2 + 2
)
= .
4Z1 Z2 Zcm
Canceling terms in the numerator leads to

ac Zf
Z 1+a d
− 2∆ZZ1 ||Z2
Ycd′ ≈
4Z1 Z2 Zcm

ac Zf
Z 1+ad − ∆ZZ
= (A.112)
4Z1 Z2 Zcm

ac Zf
Z 1+ad − ∆ZZ
= .
4Z1 Z2 Zcm
477
2
Using the small mismatch approximations Z1 Z2 ≈ Z so that Z divides out leaving

ac Zf
1+ad
− ∆Z
Ycd′ ≈
4ZZcm

ac Zf
(A.113)
1+ad
− ∆Z
=
4( Z1 +Z
2
2
)Zcm
So that
ac Zf
1+ad
− ∆Z
′
Ycds = . (A.114)
2Zcm Zdm
478
Appendix B
Multi-converter Systems
• Master-slacve current-voltage regulator hardware
• Matlabr scripts for multi-converter system modeling
• Derivation of special-case impedances for îo1 /dˆ1
• Derivation of special-case impedances for îo1 /dˆ2
479
B.1. Master-Slave Current-Voltage Regulator Hardware
B.1 Master-Slave Current-Voltage Regulator Hard-

ware
• Photograph
B.1.1 Photograph
A photograph of the master-slave regulator system deployed in an experimental set-

ting is shown in the Figure below.
Figure B-1: A closeup photograph of the two-converter current-voltage regulated

power system deployed in the fuel cell experimental setup.
480
B. Multi-converter Systems
B.1.2 Schematic Drawings
Fuel Cell Switching Section

102 20 uH 22.5 A 2xT131-52 11T 14 AWG
4.7
20 uH 22.5 A 2xT131-52 11T 14 AWG snubbers
Vdd M1 B Lo1 C 6V
A
Lin1 IRFB3607
Vfc Cin1 Cd1 Gh1 4.7 R 1/3 500 W
2x2200 uF M2
12 V Gl1 102 Co1
105 ESR 130m each IRFB3607 10 uF 20 mOhm 5W|| 20 mOhm 5W
15V Dz1 Metal Film ESR 2 ohms
Rd 0.2 Rsense
10 mOhm Vss_batt
Vss_fc 10W
1N5352BGOS
200k
- 0.01 V/A +
10k
Fuel Cell Section Feedback Control 0.2 V/A
1
8
Vdd
−2
1/2 OP262
4 +
3 10k A_fc
deadtime: ~300 ns
1N4148 200k 10k
lead compensator-subtractor
14
Vdd Vdd Vss_fc
2 14 3 470 6 5 47k LT1029
Vdd
2.8 V 470k Vrefdc
phi2_1 1N5224B 1k 5V
1k Duty Cycle Limit single turn
7 102 Vdd Vdd 102
2k 8 −6 2.4k Negative output current adjust
2 4 7 Vdd 2
5/6 74HC04 1N4148 73
+
Vref1dc 8 −
1
C AD790 4 +
104
6
− 5 47k 1 4 + Multiturn
phi1_1 10 11 470 8 9 8 5 1/2 OP262 3 105
160k 1/2 OP262
470k 2.4k 102 Vdd
102 8 − 6 1 Hz breakpoint
Vref1dc Trim
7
Vrefac
Vdd Vdd 4 +
100k 5 105 Metal Film
1k Vdd 1/2 OP262
100k
10k 2 4
73
+
1
400 kHz C AD790100k
−
Freq. Adj. 6 5
Vdd 8
470 pF
104 33 uF
Battery Switching Section 102

20 uH 22.5 A T2x131-52 11T 14 AWG 4.7 20 uH 22.5 A 2xT131-52 11T 14 AWG
Vdd M3 snubbers
15 A SPST A B Lo2 C
Lin2 IRFB3607
Vbatt Cin2 Cd2 4.7
2x2200 uF Gh2 M4
12 V 1N5352BGOS 105 Gl2 102 Co2
ESR 130m each 10 uF
15V Dz2 Metal Film IRFB3607 ESR 2 ohms
Rd 0
Vss_batt
Battery Section Feedback Control
deadtime: ~300 ns
A_batt
1N4148 1k
14 102 3V H2 10k
Vdd Vdd 15k
2 4 3 470 6 5 2.8 V 150k 1k
phi2_2 1N5224B 2.4k
1k 100k LT1029 Vrefdc
102 Vdd Duty Cycle Limit 8 Vdd − 2
7 5.1k 5V
2 4 1
73 100k
+
5/6 74HC04 1N4148 1 8 Vdd − 6
C AD790 4 +
104 2.4k 7 8 Vdd 2
6 − 3 102 1/2 OP262 Vref2dc −
5 1
phi1_2 10 11 470 8 9 8 1/2 OP262 4 +
5
100k + Multiturn
150k 15k 4 3 105
102 100k 1/2 OP262
Vdd Vdd
100k Vref2dc Trim
1k Vdd
100k
10k 32 + 4
1 7
400 kHz C AD790 100k
Freq. Adj. 6 −
8 5
Vdd
470 pF
104 33 uF
Figure B-2: Switching sections and feedback control circuits. ‘A’, ‘B’, ‘C’, ‘Vdd’,
‘Vss’, labels above switching section nodes correspond to edge connectors on the
Totem Cards for the respective converters (fuel cell and battery).
481
A Vcc A Vcc
MUR120 MUR120
Vcc Gh1 Vcc Gh2
1 8 Rg 1 8 Rg
Vcc Vb 105 Vcc Vb 105
phi1_1 7 3.9 phi1_2 7 3.9
104 2 IN HO 104 2 IN HO
B.1. Master-Slave Current-Voltage Regulator Hardware

3 IR2125 6 3 IR2125 6
Figure B-3: Gate drives
ERR CS ERR CS
4 COM Vs 5 sh1 4 COM Vs 5 sh1
MUR120 MUR120
Vcc Gl1 Vcc Gl2
1 8 Rg 1 8 Rg
Vcc Vb 105 Vcc Vb 105
phi2_1 7 3.9 phi2_2 7 3.9
104 2 IN HO 104 2 IN HO
3 IR2125 6 3 IR2125 6
ERR CS ERR CS
4 COM Vs 5 4 COM Vs 5
Fuel Cell Battery

482
483
Solder Bridge
Vdd _fc
A_fc 1 3
LM7805
Figure B-4: Linear regulators
2
104 33 uF 104 33 uF
Power only LM7805 for testing control circuitry
Solder Bridge
Vdd _batt
A_batt 1 3
LM7805
2
104 33 uF 104 33 uF
B.2. Matlabr Scripts for Multi-converter System Modeling
B.2 Matlabr Scripts for Multi-converter System

Modeling
This Appendix presents a Matlabr platform for evaluating the performance and
stability of a dual converter power system. The computation of numerical values
for complex high order rational transfer functions is demonstrated in the example
functions. Algebraic manipulation or reduction of low entropy transfer functions by
hand is avoided using the quasi-symbolic method also demonstrated in the example
functions.
B.2.1 Master-slave Current-voltage Regulated Power Sys-

tem Evaluation
MSRM.m
This script is a platform for evaluating the performance and stability of the “master-
slave” current-voltage regulated dual converter fuel cell power system. Supporting
functions include functions that report magnitude and phase vectors for closed-loop
transfer functions derived in Chapter 6 and also 2EET correction factors.
%% AC AND DC A n a l y s i s
clc
clear
close all
s = tf ( ’s ’ );
%% I n p u t s
%Choose plots
DC = 0 ;
CL = 1 ;
OL = 0 ;
OutputFilter = 0;
InputFilter = 0;
CorrectionFactors = 0;
Uncorrectedvoverd1 = 0 ;
Correctedvoverd1 = 0 ;
Uncorrectedvoverd2 = 0 ;
Correctedvoverd2 = 0 ;
FilteredInput = 0;
Single = 0;
Printdata = 0 ;
%Feed b ack l o o p p a r a m e t e r s
H1 = 2 0 ;
484
R sen se = 10 e −3;
H2 = 1 / 2 ;
Fm1 = 1 / 1 . 7 ;
Fm2 = 1 / 1 . 7 ;
% Lead Lag c o m p e n s a t o r C u r r e n t Feed b ack Loop G1 = 1 0 ; wl agp 1 = 6 e4 ; wlagz1
% = 2 e6 ; wl ead p 1 = 1 e6 ; w l e a d z 1 = 1 e6 ; % V o l t a g e Feed b ack Loop G2 = 1 0 ;
% wl agp 2 = 2 e6 ; w l a g z 2 = 2 e6 ; wl ead p 2 = 1 e6 ; w l e a d z 2 = 1 e6 ;
%
% Gc1 = G1∗(1+ s / w l a g z 1 )∗(1+ s / w l e a d z 1 ) / ( ( 1 + s / wl agp 1 )∗(1+ s / wl ead p 1 ) ) ; Gc2 =
% G2∗(1+ s / w l a g z 2 )∗(1+ s / w l e a d z 2 ) / ( ( 1 + s / wl agp 2 )∗(1+ s / wl ead p 2 ) ) ;
% Th i r d o r d e r c o m p e n s a t o r C u r r e n t Feed b ack Loop

G1 = 1 0 ;
wp1 = 4 e5 ;
wz1 = 2 e4 ;
wf1 = 5 e3 ;
% Voltage Feed b ack Loop
G2 = 1 0 ;
wp2 = 4 e5 ;
wz2 = 6 e4 ;
wf2 = 2 e3 ;
Gc1 = G1∗ ( 1/( 1+ s / wf1 ) ) ∗ ( 1+ s / wz1 ) /( 1+ s /wp1 ) ;
Gc2 = G2∗ ( 1/( 1+ s / wf2 ) ) ∗ ( 1+ s / wz2 ) /( 1+ s /wp2 ) ;
% Gc1 = 1 ; Gc2 = 1 ;
% Output Filters
Rwire = 0 . 0 2 ;
l o 1 = 20 e −6;
ESRlo1 = 0 . 0 1 ;
ESRlo1 = 0. 5+ 0. 01+ R sen se+Rwire ;
Co1 = 10 e −6;
ESRco1 = 2 ;
lo2 = lo1 ;
ESRlo2 = 0 . 0 1 ;
Co2 = Co1 ;
ESRco2 = ESRco1 ;
R d i od e1 = 0 . 0 ;
R d i od e2 = 0 . 0 ;
% Input Filters
L i n 1 = 20 e −6;
Cin1 = 1 e −6;
Cd1 = 2∗ 2200 e −6;
Rd1 = 0 . 2 + 0 . 5 ∗ 0 . 1 3 0 ; % = Rd + ESRc
ESRlin1 = 0 . 0 1 ;
ESRcin1 = 0 . 0 1 ;
Lin2 = Lin1 ;
Cin2= Cin1 ;
Cd2 = Cd1 ;
Rd2 = 0 . 2 ∗ 0 . 1 3 0 ;
ESRlin2 = ESRlin1 ;
ESRcin2 = ESRcin1 ;
%S e t points
V fc = 1 2 ;
Vbatt = 1 2 ;
Vout Command = 6 ;
Io1 Command = 8 ;
V = Vout Command ;
I o 1 = Io1 Command ;
Io2 = 8;
485
D1 = V/ V fc ;
D2 = V/ Vbatt ;
I = I o 1+I o 2 ;
% Load R e s i s t i v e : R = V/ I ; Current Source :

R = 1 e9 ;
% S i m u l a t i o n and Swept P a r a m e t e r s V r ef1m i n = 0 ; V r e f 1 r e s = 0 . 0 0 1 ; Vref1max

% = 9;
fsim = logspace ( 1 , 9 ) ;
%% L i n e a r Model : Buck
Le1 = l o 1 ;
Le2 = l o 2 ;
ESRle1 = ESRlo1 ;
ESRle2 = ESRlo2 ;
Ce1 = Co1 ;
Ce2 = Co2 ;
ESRce1 = ESRco1 ;
ESRce2 = ESRco2 ;
z c e 1 = ESRce1 +1/( s ∗Ce1 ) ;
z c e 2 = ESRce2 +1/( s ∗Ce2 ) ;
z c = z c e 1 ∗ z c e 2 / ( z c e 1+z c e 2 ) ;
z l = r e d u c e s y s ( z c ∗R/ ( z c+R ) ) ;
z l s i n g l e 1 = r e d u c e s y s ( z c ∗R/ ( z c+R ) ) ;
z l s i n g l e 2 = r e d u c e s y s ( z c ∗R/ ( z c+R ) ) ;
z l e 1 = s ∗ l o 1+ESRlo1 ;
z l e 2 = s ∗ l o 2+ESRlo2 ;
z e 1 = z l e 1 ∗ z c e 1 / ( z l e 1+z c e 1 ) ;
z e 2 = z l e 2 ∗ z c e 2 / ( z l e 2+z c e 2 ) ;
M1 = D1 ;
M2 = D2 ;
e1 = V/ ( D1 ˆ 2 ) ;
e2 = V/ ( D2 ˆ 2 ) ;
j1 = Io1 ;
j2 = Io2 ;
Rp = R/(1+R/ ESRle1+R/ ESRle2 ) ;
l am b d ap r i m e1 = z l e 1 +( z l e 2 ∗ z l / ( z l e 2+z l ) ) ;
lambda1 = ( z l e 2 ∗ z l / ( z l e 2+z l ) ) / l am b d ap r i m e1 ;
l am b d ap r i m e2 = z l e 2 +( z l e 1 ∗ z l / ( z l e 1+z l ) ) ;
lambda2 = ( z l e 1 ∗ z l / ( z l e 1+z l ) ) / l am b d ap r i m e2 ;
%% Open−l o o p transfer functions
%Pre−e v a l u a t e d v o v e r d and i o 1 o v e r d
[ v1mag , v1p h ase ] = v o v e r d 1 ( H1 , H2 , Gc1 , Gc2 , M1, M2, e1 , e2 , j 1 , j 2 , Fm1 , Fm2 , Le1 , . . .
Le2 , ESRle1 , ESRle2 , Ce1 , Ce2 , ESRce1 , ESRce2 , R, f s i m ) ;
[ v2mag , v2p h ase ] = v o v e r d 2 ( H1 , H2 , Gc1 , Gc2 , M1, M2, e1 , e2 , j 1 , j 2 , Fm1 , Fm2 , Le1 , . . .
[ i1mag , i 1 p h a s e ] = i o 1 o v e r d 1 ( H1 , H2 , Gc1 , Gc2 , M1, M2, e1 , e2 , j 1 , j 2 , Fm1 , Fm2 , Le1 , . . .
[ i2mag , i 2 p h a s e ] = i o 1 o v e r d 2 ( H1 , H2 , Gc1 , Gc2 , M1, M2, e1 , e2 , j 1 , j 2 , Fm1 , Fm2 , Le1 , . . .
%U n e v a l u a t e d v o v e r d for computation o f loop transfer functions

v o v e r d 1 u n e v a l = e1 ∗M1∗ lambda1 ;
v o v e r d 2 u n e v a l = e2 ∗M2∗ lambda2 ;
%U n e v a l u a t e d i o 1 o v e r d for computation o f loop transfer functions
486
i o 1 o v e r d 1 u n e v a l = (M1∗ e1 / z l e 1 −v o v e r d 1 u n e v a l / z e 1 ) ;
i o 1 o v e r d 2 u n e v a l = −v o v e r d 2 u n e v a l / z e 1 ;
%U n e v a l u a t e d d o v e r x for computation o f loop transfer functions

d 1 o v e r x u n e v a l = −i o 1 o v e r d 2 u n e v a l ∗Fm1∗Gc1∗H1∗ R sen se ∗Gc2∗Fm2/(1+Fm1∗Gc1 . . .
∗H1∗ R sen se ∗ i o 1 o v e r d 1 u n e v a l ) ;
d 2 o v e r x u n e v a l = Gc2∗Fm2 ;
%U n e v a l u a t e d d o v e r q for computation o f loop transfer functions

d 1 o v e r q u n e v a l = Gc1∗Fm1 ;
d 2 o v e r q u n e v a l = −H2∗Gc2∗Fm2∗ v o v e r d 1 u n e v a l ∗Gc1∗Fm1/(1+H2∗Gc2∗Fm2 ∗ . . .
voverd2 uneval ) ;
%Loop t r a n s f e r functions w i t h m i n or l o o p s
T1 = H1∗ R sen se ∗ ( d 1 o v e r q u n e v a l ∗ i o 1 o v e r d 1 u n e v a l+d 2 o v e r q u n e v a l ∗ . . .
io1overd2 uneval ) ;
T2 = H2∗ ( d 1 o v e r x u n e v a l ∗ v o v e r d 1 u n e v a l+d 2 o v e r x u n e v a l ∗ v o v e r d 2 u n e v a l ) ;
% Single converter for debugging wh i l e building

%z l p z l e 2 −> z l s i n g l e 1
% v o v e r d 1 u n e v a l s i n g l e = e1 ∗M1∗ z l s i n g l e 1 / ( z l e 1+ z l s i n g l e 1 ) ; Tsingle1 =
% v o v e r d 1 u n e v a l s i n g l e ∗Fm1∗Gc1∗H1 ;
%z l p z l e 1 −> z l s i n g l e 2
% v o v e r d 2 u n e v a l s i n g l e = e2 ∗M2∗ z l s i n g l e 2 / ( z l e 2+ z l s i n g l e 2 ) ; Tsingle2 =
% v o v e r d 2 u n e v a l s i n g l e ∗Fm2∗Gc2∗H2 ;
%% Cl osed −l o o p transfer functions

d 2 o v e r d 1 u n e v a l = −(H2∗Fm2∗Gc2∗M1∗ e1 ∗ z l p z l e 2 / ( z l e 1+z l p z l e 2 ) ) / . . .
(1+H2∗Fm2∗Gc2∗M2∗ e2 ∗ z l p z l e 1 / ( z l e 2+z l p z l e 1 ) ) ;
d e n u n e v a l = 1+Fm1∗Gc1∗H1∗ R sen se ∗M1∗ e1 ∗ ( 1 / z l e 1 −z l p z l e 2 / . . .
( ( z l e 1+z l p z l e 2 ) ∗ z e 1 ) ) ;
d 1 o v e r v r e f 1 u n e v a l = (Fm1∗Gc1/ d e n u n e v a l )/(1 −Fm1∗Gc1∗H1∗ R sen se ∗M2 ∗ . . .
( z l p z l e 1 / ( z l e 2+z l p z l e 1 ) ) ∗ ( e2 / z l e 1 ) ∗ d 2 o v e r d 1 u n e v a l / ( d e n u n e v a l ) ) ;
d2overvref1 uneval = d1overvref1 uneval ∗ d2overd1 uneval ;
[ vmag , vp h ase ] = v o v e r v r e f 1 (M1, M2, e1 , e2 , j 1 , j 2 , Le1 , Le2 , ESRle1 , ESRle2 , Ce1 , . . .

Ce2 , ESRce1 , ESRce2 , Fm1 , Fm2 , Gc1 , Gc2 , H1 , H2 , R, d1overvref1 uneval , . . .
d2overvref1 uneval , fsim ) ;
[ io1mag , i o 1 p h a s e ] = i o 1 o v e r v r e f 1 (M1, M2, e1 , e2 , j 1 , j 2 , Le1 , Le2 , ESRle1 , . . .
ESRle2 , Ce1 , Ce2 , ESRce1 , ESRce2 , Fm1 , Fm2 , Gc1 , Gc2 , H1 , H2 , R, ...
d1overvref1 uneval , d2overvref1 uneval , fsim ) ;
[ i i n 1m ag , i i n 1 p h a s e ] = i i n 1 o v e r v r e f 1 (M1, M2, e1 , e2 , j 1 , j 2 , Le1 , Le2 , . . .
ESRle1 , ESRle2 , Ce1 , Ce2 , ESRce1 , ESRce2 , Fm1 , Fm2 , Gc1 , Gc2 , H1 , H2 , R , ...
d1overvref1 uneval , d2overvref1 uneval , fsim ) ;
[ i i n 1 o v e r i l o a d m a g , i i n 1 o v e r i l o a d p h a s e ] = i i n 1 o v e r i l o a d (M1, M2, e1 , e2 , j 1 , . . .
j 2 , Le1 , Le2 , ESRle1 , ESRle2 , Ce1 , Ce2 , ESRce1 , ESRce2 , Fm1 , Fm2 , Gc1 , Gc2 , H1 , . . .
H2 , R , R sen se , fsim ) ;
%% Output Filter Transfer function

Q1 = z l p z l e 2 / ( z l p z l e 2+z l e 1 ) ;
Q2 = z l p z l e 1 / ( z l p z l e 1+z l e 2 ) ;
%% Input Filter Transfer Function

Z l i n 1 = E S R l i n 1+s ∗ L i n 1 ;
Z l i n 2 = E S R l i n 2+s ∗ L i n 2 ;
Z c i n 1 = ESRcin1+1/( s ∗ Cin1 ) ;
Z c i n 2 = ESRcin2+1/( s ∗ Cin2 ) ;
Zd1 = Rd1+1/( s ∗Cd1 ) ;
Zd2 = Rd2+1/( s ∗Cd2 ) ;
Qin1 = Z c i n 1 ∗Zd1 / ( Z c i n 1+Zd1 ) / ( Z c i n 1 ∗Zd1 / ( Z c i n 1+Zd1)+ Z l i n 1 ) ;
487
Qin2 = Z c i n 2 ∗Zd2 / ( Z c i n 2+Zd2 ) / ( Z c i n 2 ∗Zd2 / ( Z c i n 2+Zd2)+ Z l i n 2 ) ;

[ Qin1mag , Q i n 1p h ase ] = bode ( Qin1 , fsim ) ;
Qin1mag = 20∗ l o g 1 0 ( Qin1mag ( : ) ) ;
Q i n 1p h ase = ( 1 8 0 / p i ) ∗ ( unwrap ( ( p i / 1 8 0 ) ∗ Q i n 1p h ase ( : ) ) ) ;
%% C o r r e c t i o n F a c t o r s for Input Filters

[ CF1mag , CF1phase ] = CFact or 1 ( e1 , e2 , j 1 , j 2 , Le1 , Le2 , ESRle1 , ESRle2 , Ce1 , Ce2 , . . .
ESRce1 , ESRce2 , M1, M2, R , Lin1 , Cin1 , ESRlin1 , ESRcin1 , Cd1 , Rd1 , Lin2 , . . .
Cin2 , ESRlin2 , ESRcin2 , Cd2 , Rd2 , f s i m ) ;
%% P l o t t i n g %%
%% P l o t t i n g C−L t r a n s f e r functions
w h i l e CL == 1
% V
%vmag
figure
subplot (2 ,1 ,1)
% calculated
s e m i l o g x ( f s i m , vmag ) ; h o l d on
% simulated
if P r i n t d a t a == 1
semi l ogx ( fsim , vovervref1acmagdata , ’ x ’ )
% semi l ogx ( fsim , vovervref1acmagdata droop , ’ + ’ )
end
% h l egen d = l egen d ( ’ Cal cu l ated ’ , ’ Simulated ’ ) ;
% s e t ( h l egen d , ’ FontSize ’ , 8 ) ;
t i t l e ( ’V/ V { r e f 1 } ’ )
h = gca ;
s e t (h , ’ Fon tsi ze ’ , 8 , ’ Ycolor ’ , [ 0 . 4 , 0 . 4 , 0 . 4 ] , ’ Xcolor ’ , [ 0 . 4 , 0 . 4 , 0 . 4 ] )
% s e t ( h l egen d , ’ Location ’ , ’ best ’ )
y l a b e l ( ’ | v/ v { r e f 1 } | ( db ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
hold off
g r i d on
box on
%vp h ase
subplot (2 ,1 ,2)
% calculated
s e m i l o g x ( f s i m , vp h ase ) ; h o l d on
% simulated
semi l ogx ( fsim , vovervref1acphasedata , ’ x ’ )
% semi l ogx ( fsim , vovervref1acphasedata droop , ’ + ’ )
end
h = gca ;
y l a b e l ( ’ \ a n g l e v / v { r e f 1 } ( d eg ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
x l a b e l ( ’ Fr equ en cy ( r ad / s e c ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
488
hold off
g r i d on
box on
% IO1
%io1mag
figure
subplot (2 ,1 ,1)
% calculated
s e m i l o g x ( f s i m , io1mag ) ; h o l d on
% simulated
semi l ogx ( fsim , i o1overvref1acmagdata , ’ x ’ )
% semi l ogx ( fsim , i o1overvref1acmagdata droop , ’ + ’ )
end
t i t l e ( ’ I { o1 }/ V { r e f 1 } ’ )
h = gca ;
y l a b e l ( ’ | i { o1 }/ v { r e f 1 } | ( db ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
hold off
g r i d on
box on
%i o 1 p h a s e
subplot (2 ,1 ,2)
% calculated
semi l ogx ( fsim , i o1phase ) ; h o l d on
% simulated
semi l ogx ( fsim , i o 1 o v e r v r e f 1 a c p h a s e d a t a , ’ x ’ )
% semi l ogx ( fsim , i o 1 o v e r v r e f 1 a c p h a s e d a ta d r o o p , ’ + ’ )
end
h = gca ;
y la be l ( ’\ angle i { o1 }/ v { r e f 1 } ( d eg ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
hold off
g r i d on
box on
% IIN1
%i i n 1 m a g
figure
subplot (2 ,1 ,1)
% calculated
semi l ogx ( fsim , iin1mag ) ; h o l d on
% simulated
semi l ogx ( fsim , i i n1overvref1acmagdata , ’ x ’ )
% semi l ogx ( fsim , i i n1overvref1acmagdat a droop , ’ + ’ )
end
t i t l e ( ’ I { i n 1 }/V { r e f 1 } ’ )
489
h = gca ;
y l a b e l ( ’ | i { i n 1 }/ v { r e f 1 } | ( db ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
hold off
g r i d on
box on
%i i n 1 p h a s e
subplot (2 ,1 ,2)
% calculated
semi l ogx ( fsim , i i n 1 p h a s e ) ; h o l d on
% simulated
semi l ogx ( fsim , i i n 1 o v e r v r e f 1 a c p h a s e d a t a , ’ x ’ )
% semi l ogx ( fsim , i i n 1 o v e r v r e f 1 a c p h a s e d a t a d r o o p , ’ + ’ )
end
h = gca ;
y la be l ( ’\ angle i { i n 1 }/ v { r e f 1 } ( d eg ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
hold off
g r i d on
box on
% IIN1overiload
%i i n 1 o v e r i l o a d m a g
figure
subplot (2 ,1 ,1)
% calculated
semi l ogx ( fsim , i i n 1 o v e r i l o a d m a g ) ; h o l d on
% simulated
semi l ogx ( fsim , i i n1overvref1acmagdata , ’ x ’ )
% semi l ogx ( fsim , i i n1overvref1acmagdat a droop , ’ + ’ )
end
t i t l e ( ’ I { i n 1 }/ I { l o a d } ’ )
h = gca ;
y l a b e l ( ’ | i { i n 1 }/ i { l o a d } | ( db ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
hold off
g r i d on
box on
%i i n 1 o v e r i l o a d p h a s e
subplot (2 ,1 ,2)
% calculated
semi l ogx ( fsim , i i n 1 o v e r i l o a d p h a s e ) ; h o l d on
% simulated
semi l ogx ( fsim , i i n 1 o v e r v r e f 1 a c p h a s e d a t a , ’ x ’ )
end
490
h = gca ;
y la be l ( ’\ angle i { i n 1 }/ i { l o a d } ( d eg ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
hold off
g r i d on
box on
CL = 0 ;
end
%% P l o t t i n g O−L t r a n s f e r functions
w h i l e OL == 1
figure
% subplot (1 ,2 ,1)
m ar gi n ( T1 )
% g r i d on
box on
figure
% subplot (1 ,2 ,2)
m ar gi n ( T2 )
box on
OL = 0 ;
end
%% P l o t t i n g Correction Factors
while C o r r e c t i o n F a c t o r s == 1 ,
figure
% Magnitude
subplot (2 ,1 ,1)
% calculated
s e m i l o g x ( f s i m , CF1mag ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd1correctedacmagdata − . . .
voverd1uncorrectedacmagdata , ’ x ’ )
% s e m i l o g x ( f s i m , v o v e r d 1 c o r r e c t e d a c m a g d a t a d r o o p −v o v e r d 1 u n c o r r e c t e d a
% cm agd at a d r oop , ’ o ’ )
end
% P l ot Formatting
h = gca ;
% s e t ( h l egen d , ’ FontSize ’ , 8 ) ; s e t ( h l egen d , ’ Location ’ , ’ best ’ )
y l a b e l ( ’ | CF 1 | ( db ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
t i t l e ( ’ E xt r a Element C o r r e c t i o n F a c t o r CF 1 f o r v/ d 1 ’ )
g r i d on
box on
hold off
% Phase
subplot (2 ,1 ,2)
% calculated
s e m i l o g x ( f s i m , CF1phase ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd1correctedacphasedata − . . .
voverd1uncorrectedacphasedata , ’ x ’ )
491
% s e m i l o g x ( f s i m , v o v e r d 1 c o r r e c t e d a c p h a s e d a t a d r o o p −v o v e r d 1 u n c o r r e c t e
% dacphasedata droop , ’ o ’ )
end
% P l ot Formatting
h = gca ;
y l a b e l ( ’ \ a n g l e CF 1 ( d eg ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
g r i d on
box on
hold off
%% P l o t t i n g C o r r e c t i o n Factor 2
figure
% Magnitude
subplot (2 ,1 ,1)
% calculated
% simulated
semi l ogx ( fsim , voverd2correctedacmagdata − . . .
voverd2uncorrectedacmagdata , ’ x ’ )
% s e m i l o g x ( f s i m , v o v e r d 2 c o r r e c t e d a c m a g d a t a d r o o p −v o v e r d 2 u n c o r r e c t e d a c m a g d a t a d r o o p , ’ o ’ )
end
% P l ot Formatting
h = gca ;
t i t l e ( ’ E xt r a Element C o r r e c t i o n F a c t o r CF 2 f o r v/ d 2 ’ )
g r i d on
box on
hold off
% Phase
subplot (2 ,1 ,2)
% calculated
% simulated
semi l ogx ( fsim , voverd2correctedacphasedata − . . .
voverd2uncorrectedacphasedata , ’ x ’ )
%s e m i l o g x ( f s i m , v o v e r d 2 c o r r e c t e d a c p h a s e d a t a d r o o p −
%v o v e r d 2 u n c o r r e c t e d a c p h a s e d a t a d r o o p , ’ o ’ )
end
% P l ot Formatting
h = gca ;
492
g r i d on
box on
hold off
%% P l o t t i n g C o r r e c t i o n Factor 3 f o r i o 1 / d1
figure
% Magnitude
subplot (2 ,1 ,1)
% calculated
% simulated
semi l ogx ( fsim , i o1overd1correctedacmagdata − . . .
io1overd1uncorrectedacmagdata , ’ x ’ )
% sem i l ogx ( fsim , vover d 2cor r ect ed acm agdat a d r oop−
% voverd2uncorrectedacmagdata droop , ’ o ’ )
end
% P l ot Formatting
h = gca ;
t i t l e ( ’ E xt r a Element C o r r e c t i o n F a c t o r CF 3 f o r i { o1 }/ d 1 ’ )
g r i d on
box on
hold off
% Phase
subplot (2 ,1 ,2)
% calculated
% simulated
semi l ogx ( fsim , i o 1 o v e r d 1 c o r r e c t e da c pha s e da t a − . . .
io1overd1uncorrectedacphasedata , ’ x ’ )
% semi l ogx ( fsim , voverd2correctedacphase data droop −
% voverd2uncorrectedacphasedata droop , ’ o ’ )
end
% P l ot Formatting
h = gca ;
g r i d on
box on
hold off
%% P l o t t i n g C o r r e c t i o n Factor 4 f o r i o 1 / d2
figure
% Magnitude
subplot (2 ,1 ,1)
% calculated
493
% simulated
semi l ogx ( fsim , i o1overd2correctedacmagdata − . . .
io1overd2uncorrectedacmagdata , ’ x ’ )
% sem i l ogx ( fsim , vover d 2cor r ect ed acm agdat a d r oop−
% voverd2uncorrectedacmagdata droop , ’ o ’ )
end
% P l ot Formatting
h = gca ;
t i t l e ( ’ E xt r a Element C o r r e c t i o n F a c t o r CF 4 f o r i { o1 }/ d 2 ’ )
g r i d on
box on
hold off
% Phase
subplot (2 ,1 ,2)
% calculated
% simulated
semi l ogx ( fsim , i o 1 o v e r d 2 c o r r e c t e da c pha s e da t a − . . .
io1overd2uncorrectedacphasedata , ’ x ’ )
% semi l ogx ( fsim , voverd2correctedacphase data droop −
% voverd2uncorrectedacphasedata droop , ’ o ’ )
end
% P l ot Formatting
h = gca ;
g r i d on
box on
hold off
CorrectionFactors = 0;
end
%% P l o t t i n g U n corrected voverd1
while U n c o r r e c t e d v o v e r d 1 == 1 ,
figure
% Magnitude
subplot (2 ,1 ,1)
% calculated
s e m i l o g x ( f s i m , v1mag ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd1uncorrectedacmagdata , ’ x ’ )
% semi l ogx ( fsim , voverd1uncorrectedacmagdata droop , ’ o ’ )
end
494
% P l ot Formatting
t i t l e ( ’ v/ d 1 ’ , ’ F o n t s i z e ’ , 8 ) ;
h = gca ;
y l a b e l ( ’ | v/ d 1 | ( db ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
g r i d on
box on
hold off
% Phase
subplot (2 ,1 ,2)
% calculated
s e m i l o g x ( f s i m , v1p h ase ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd1uncorrectedacphasedata , ’ x ’ )
% semi l ogx ( fsim , voverd1uncorrectedacphasedata droop , ’ o ’ )
end
% P l ot Formatting
h = gca ;
y l a b e l ( ’ \ a n g l e v / d 1 ( d eg ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
g r i d on
box on
hold off
Uncorrectedvoverd1 = 0;
end
%% P l o t t i n g Corrected voverd1
while C o r r e c t e d v o v e r d 1 == 1 ,
figure
% Magnitude
subplot (2 ,1 ,1)
% calculated
c1mag = v1mag+CF1mag ;
s e m i l o g x ( f s i m , c1mag ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd1correctedacmagdata , ’ x ’ ) ;
% semi l ogx ( fsim , voverd1correctedacmagdata droop , ’ o ’ )
end
% P l ot Formatting
t i t l e ( ’ Corrected v/d 1 ’ , ’ Fontsize ’ , 8 ) ;
h = gca ;
g r i d on
box on
hold off
495
% Phase
subplot (2 ,1 ,2)
%c a l c u l a t e d
c 1 p h a s e = v1p h ase+CF1phase ;
semi l ogx ( fsim , c1phase ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd1correctedacphasedata , ’ x ’ )
% semi l ogx ( fsim , voverd1correctedacphase data droop , ’ o ’ )
end
% P l ot Formatting
h = gca ;
g r i d on
box on
hold off
Correctedvoverd1 = 0;
end
%% P l o t t i n g U n corrected voverd2
while U n c o r r e c t e d v o v e r d 2 == 1 ,
figure
% Magnitude
subplot (2 ,1 ,1)
% calculated
s e m i l o g x ( f s i m , v2mag ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd2uncorrectedacmagdata , ’ x ’ )
% semi l ogx ( fsim , voverd2uncorrectedacmagdata droop , ’ o ’ )
end
% P l ot Formatting
t i t l e ( ’ v/ d 2 ’ , ’ F o n t s i z e ’ , 8 ) ;
h = gca ;
s e t ( h l egen d , ’ Location ’ , ’ best ’ )
g r i d on
box on
hold off
% Phase
subplot (2 ,1 ,2)
% calculated
s e m i l o g x ( f s i m , v2p h ase ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd2uncorrectedacphasedata , ’ x ’ )
% semi l ogx ( fsim , voverd2uncorrectedacphasedata droop , ’ o ’ )
end
% P l ot Formatting
496
h = gca ;
g r i d on
box on
hold off
Uncorrectedvoverd2 = 0;
end
%% P l o t t i n g Corrected voverd2
while C o r r e c t e d v o v e r d 2 == 1 ,
figure
% Magnitude
subplot (2 ,1 ,1)
% calculated
c2mag = v2mag+CF2mag ;
s e m i l o g x ( f s i m , c2mag ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd2correctedacmagdata , ’ x ’ )
% semi l ogx ( fsim , voverd2correctedacmagdata droop , ’ o ’ )
end
% P l ot Formatting
t i t l e ( ’ Corrected v/d 2 ’ , ’ Fontsize ’ , 8 ) ;
h = gca ;
g r i d on
box on
hold off
% Phase
subplot (2 ,1 ,2)
%c a l c u l a t e d
c 2 p h a s e = v2p h ase+CF2phase ;
semi l ogx ( fsim , c2phase ) ; h o l d on
% simulated
semi l ogx ( fsim , voverd2correctedacphasedata , ’ x ’ )
% semi l ogx ( fsim , voverd2correctedacphase data droop , ’ o ’ )
end
% P l ot Formatting
h = gca ;
g r i d on
box on
hold off
Correctedvoverd2 = 0;
end
497
%% P l o t t i n g Input Filter transfer functions

while I n p u t F i l t e r == 1 ,
figure
bode ( Qin1 )
legend ( ’ Input F i l t e r 1 TF ’ )
g r i d on
box on
figure
bode ( Qin2 )
legend ( ’ Input F i l t e r 2 TF ’ )
g r i d on
box on
InputFilter = 0;
end
%% P l o t t i n g Output filter transfer functions

while O u t p u t F i l t e r == 1
figure
bode (Q1)
l e g e n d ( ’ Output Filter 1 TF ’ )
g r i d on
box on
figure
bode (Q2)
l e g e n d ( ’ Output Filter 2 TF ’ )
g r i d on
box on
OutputFilter = 0;
end
%% P l o t t i n g Filtered Input Current transfer function

while F i l t e r e d I n p u t == 1 ,
figure
subplot (2 ,1 ,1)
% calculated
s e m i l o g x ( f s i m , i i n 1 m a g+Qin1mag ) ; h o l d on
% simulated
% if P r i n t d a t a == 1
% semi l ogx ( fsim , i i n1overvref1acmagdata , ’ x ’ )
% semi l ogx ( fsim , i i n1overvref1acmagdata droop , ’ + ’ )
% end h l e g e n d = l e g e n d ( ’ C a l c u l a t e d ’ , ’ S i m u l a t e d R { d r oop } =
% 0 ’ , ’ S i m u l a t e d R { d r oop } \ neq 0 ’); s e t ( h l egen d , ’ FontSize ’ , 8 ) ;
t i t l e ( ’ Filtered I { i n 1 }/ V { r e f 1 } ’ )
h = gca ;
y l a b e l ( ’ | i { i n 1 }/ v { r e f 1 } | ( db ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
hold off
g r i d on
box on
%i i n 1 p h a s e
subplot (2 ,1 ,2)
% calculated
s e m i l o g x ( f s i m , i i n 1 p h a s e+Q i n 1p h ase ) ; h o l d on
% simulated
% if P r i n t d a t a == 1
% semi l ogx ( fsim , i i n 1 o v e r v r e f 1 a c p h a s e d a t a , ’ x ’ )
% end h l e g e n d = l e g e n d ( ’ C a l c u l a t e d ’ , ’ S i m u l a t e d R { d r oop } =
498
% 0 ’ , ’ S i m u l a t e d R { d r oop } \ neq 0 ’); s e t ( h l egen d , ’ FontSize ’ , 8 ) ;

h = gca ;
y la be l ( ’\ angle i { i n 1 }/ v { r e f 1 } ( d eg ) ’ , ’ F o n t s i z e ’ , 8 , ’ Col or ’ , ’ k ’ ) ;
hold off
g r i d on
box on
FilteredInput = 0;
end
%% P l o t t i n g Loop t r a n s f e r for single converter for debugging wh i l e building

while S i n g l e == 1 ,
figure
m ar gi n ( T s i n g l e 1 )
box on
g r i d on
figure
m ar gi n ( T s i n g l e 2 )
box on
g r i d on
Single = 0;
end
499
vovervref1.m
This script reports the magnitude and phase of the closed-loop transfer function from
the first converter’s control voltage perturbation to the load voltage perturbation.
function [ mag , p h a s e ] = v o v e r v r e f 1 (M1, M2, e1 , e2 , j 1 , j 2 , Le1 , Le2 , ESRle1 , . . .

ESRle2 , Ce1 , Ce2 , ESRce1 , ESRce2 , Fm1 , Fm2 , Gc1 , Gc2 , H1 , H2 , R, ...
d1overvref1 uneval , d2overvref1 uneval , eval vector );
s = tf ( ’s ’ );
z c e 1 = ESRce1 +1/( s ∗Ce1 ) ;
z c e 2 = ESRce2 +1/( s ∗Ce2 ) ;
z e 1 = z l e 1 ∗ z c e 1 / ( z l e 1+z c e 1 ) ;
z e 2 = z l e 2 ∗ z c e 2 / ( z l e 2+z c e 2 ) ;
z c = z c e 1 ∗ z c e 2 / ( z c e 1+z c e 2 ) ;
z l = z c ∗R/ ( z c+R ) ;
d1overvref1 = freqresp ( d1overvref1 uneval , eval vector );

d2overvref1 = freqresp ( d2overvref1 uneval , eval vector );
t er m 1 = d 1 o v e r v r e f 1 . ∗ f r e q r e s p (M1∗ z l p z l e 2 ∗ e1 , e v a l v e c t o r ) . / . . .
f r e q r e s p ( ( z l e 1+z l p z l e 2 ) , eval vector );
t er m 2 = d 2 o v e r v r e f 1 . ∗ f r e q r e s p (M2∗ z l p z l e 1 ∗ e2 , e v a l v e c t o r ) . / . . .
f r e q r e s p ( ( z l e 2+z l p z l e 1 ) , eval vector );
r e s u l t = t er m 1+t er m 2 ;
%% R e s u l t s
mag = 20∗ l o g 1 0 ( ab s ( r e s u l t ( : ) ) ) ;
p h a s e = 180/ p i ∗ ( a n g l e ( r e s u l t ( : ) ) ) ;
end
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
500
CFactor1.m
This script reports the magnitude and phase of the 2EET correction factor for the
converter transfer function from the first converter’s duty ratio perturbation to the
first converter’s output voltage perturbation (the load voltage).
%% C o r r e c t i o n factor f o r v / d1 f o r TWO i n p u t filters w i t h Output
%% C a p a c i t a n c e s
function [ mag , p h a s e ] = CFact or 1 ( e1 , e2 , j 1 , j 2 , Le1 , Le2 , ESRle1 , ESRle2 , Ce1 , . . .

Ce2 , ESRce1 , ESRce2 , M1, M2, R, Lin1 , Cin1 , ESRlin1 , ESRcin1 , Cd1 , ...
Rd1 , Lin2 , Cin2 , ESRlin2 , ESRcin2 , Cd2 , Rd2 , eval vector )
s = tf ( ’s ’ );
%% T o t a l Shunt Impedance a t Load ( ZL) Due t o addition of output

%% c a p a c i t a n c e s
Z ce1 = ESRce1 +1/( s ∗Ce1 ) ;
Z ce2 = ESRce2 +1/( s ∗Ce2 ) ;
Zc = Z ce1 ∗ Z ce2 / ( Z ce1+Z ce2 ) ;
Z l e 1 = ESRle1+s ∗ Le1 ;
Z l e 2 = ESRle2+s ∗ Le2 ;
ZL = Zc∗R/ ( Zc+R ) ;
%% S p e c i a l −c a s e impedances
Zs1 = t f (−e1 / j 1 ) ;
Zs2 = t f ( Z l e 2 / (M2∗M2 ) ) ;
Zs3 = t f ( ( Z l e 1 +( Z l e 2 ∗ZL/ ( ZL+Z l e 2 ) ) ) / ( M1∗M1 ) ) ; %(R−>ZL )
Zs4 = t f ( ( Z l e 2 +( Z l e 1 ∗ZL/ ( ZL+Z l e 1 ) ) ) / ( M2∗M2 ) ) ; %(R−>ZL )
Zs5 = t f (−e1 / j 1 ) ;
Zs6 = ( ZL+Z l e 1 ) / (M1∗M1 ) ; %(R−>ZL )
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%% F i l t e r Output I m p ed an ces
% Z1 = r e d u c e s y s ( F i l t e r Z o 1 ( Lin1 , Cin1 , ESRlin1 , ESRcin1 , Cd1 , Rd1 ) ) ;
% Z2 = r e d u c e s y s ( F i l t e r Z o 2 ( Lin2 , Cin2 , ESRlin2 , ESRcin2 , Cd2 , Rd2 ) ) ;
Z1 = F i l t e r Z o 1 ( Lin1 , Cin1 , ESRlin1 , ESRcin1 , Cd1 , Rd1 ) ;
Z2 = F i l t e r Z o 2 ( Lin2 , Cin2 , ESRlin2 , ESRcin2 , Cd2 , Rd2 ) ;
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%% I n t e r a c t i o n Parameters
Kn = Zs1 / Zs5 ;
Kd = Zs3 / Zs6 ;
%i f interaction f a c t o r =1 can factor exactly . more n u m e r i c a l l y r o b u s t

if f r e q r e s p (Kn , 1 ) == 1 ,
CF1num = (1+Z1 / Zs1 )∗(1+ Z2/ Zs2 ) ;
else
CF1num = (1+Z1 / Zs1+Z2/ Zs2+Kn∗ ( Z1∗ Z2 / ( Zs1 ∗ Zs2 ) ) ) ;
end
%i f interaction f a c t o r =1 can f a c t o r exactly . more n u m e r i c a l l y r o b u s t

if f r e q r e s p ( Kd , 1 ) == 1 ,
CF1den = (1+Z1 / Zs3 )∗(1+ Z2/ Zs4 ) ;
else
CF1den = (1+Z1 / Zs3+Z2/ Zs4+Kd∗ ( Z1∗ Z2 / ( Zs3 ∗ Zs4 ) ) ) ;
end
%% Compute CF1 i n steps

% CF1num = CF1num1∗CF1num2 :
501
CF1num1 = (1+ Z1/ Zs1 ) ;

CF1num2 = (1+ Z2/ Zs2 ) ;
% CF1den = CF1den1+CF1den2 :
CF1den1 = 1+Z1/ Zs3+Z2/ Zs4 ;
CF1den2 = Kd∗ ( Z1∗Z2 / ( Zs3 ∗ Zs4 ) ) ;
%% E v a l u a t e CF1 n u m er at or and d e n o m i n a t o r n u m e r i c a l l y
CF1num = f r e q r e s p ( CF1num1 , e v a l v e c t o r ) . ∗ f r e q r e s p ( CF1num2 , e v a l v e c t o r ) ;
CF1den = f r e q r e s p ( CF1den1 , e v a l v e c t o r )+ f r e q r e s p ( CF1den2 , e v a l v e c t o r ) ;
%% D i v i d e t h e n u m e r i c a l results to get the numerical Transfer function

%% r e s u l t
CF1 = CF1num . / CF1den ;
%% C o n v e r t e r t o db m agn i t u d e and unwrapped d e g r e e s p h a s e

CF1mag = 20∗ l o g 1 0 ( ab s ( CF1 ( : ) ) ) ;
CF1phase = ( 1 8 0 / p i ) ∗ unwrap ( a n g l e ( CF1 ( : ) ) ) ;
%% R e p o r t i n g
mag = CF1mag ;
p h a s e = CF1phase ;
end
502
B.3 Derivation of Special-case Impedances for îo1/dˆ1
Designating îo1 /dˆ1 as the 3rd transfer function, the superscripts for the six special-case
(3)
The first special-case impedance, ZN 1 |Z2 =0 , is the null-condition impedance at
the first extra element port with the second extra element port shorted. Because
it is a null-condition impedance, analysis of the circuit should address the fact that
the independent input in this transfer function, dˆ1 will be directed such that the
first converter’s output current, îo1 , is nulled. With this condition, and with the
other independent inputs deactivated, the voltage drop across the first converter’s
total output impedance is zero and the second converter output current must also
be zero since the second duty ratio has been deactivated. The output voltage must
be zero since both converter output currents are zero and that voltage appears at
the secondary of the first ideal transformer. The primary voltage of the first ideal
transformer must also be zero. Therefore, the voltage across the extra element port
is simply v̂in = −e1 dˆ1 (s) and the current through the extra element port must be
îin = j1 dˆ1 (s) so that their ratio, the impedance seen at the extra element port is
(3) e1
ZN 1 |Z2 =0 = − . (B.1)
j1
(3)
The second special-case impedance, ZN 2 |Z1 =0 , is the null-condition impedance at
the second extra element port with the first extra element port shorted. Because the
first converter’s output current is zero, the load voltage is simply, e1 dˆ1 M1 and the
e1 dˆ1 M1
second converter’s output current must be îo2 = R
. Solving the circuit in Figure
7-5 leads to
!
M1 e1 dˆ1 Zce2
îin = M2 (B.2)
R Zce2 + Zle2

1 ˆ 1
v̂in = e1 d1 M1 + îin Zle2 . (B.3)
M2 M2
503
B.3. Derivation of Special-case Impedances for îo1 /dˆ1
Dividing these two leads to

(3) 1 Zce2 + Zle2
ZN 2 |Z1 =0 = 2 R + Zle2 . (B.4)
M2 Zce2
(1)
independent inputs deactivated. This condition is identical to that for the open-loop
impedance found for correcting any other transfer function. The result can be taken
directly from the correction factor derivation for v̂/dˆ1 , for instance:

ZD1 |Z2 =0 = . (B.5)
M12
ments:
ZD2 |Z1 =0 = . (B.6)
M22
The remaining two special-case impedances are needed to determine the inter-
action parameters in the correction factor. Note that from (7.31), there is some
redundancy in the choice of these final special-case impedances. Here we derive,
(3) (3) (3)
ZN 1 |Z2 =∞ and ZD1 |Z2 =∞ . The fifth special-case impedance, ZN 1 |Z2 =∞ , is the null-
condition impedance at the first extra element port with the second extra element
port open-circuited. Because the second port is open-circuited, the current through
the second primary must be zero, îpri2 = 0 and so must the current through the
second inductor, île2 = 0. Since the first converter’s output current is nulled, îo1 = 0,
the voltage drop across the first converter’s total output impedance is zero, so that by
KVL, the voltage across the first secondary and therefore its primary is zero, v̂pri1 = 0.
Therefore, the voltage across the extra element port is simply v̂in = −e1 dˆ1 (s) and the
current through the extra element port must be îin = j1 dˆ1 (s) so that their ratio, the
504
impedance seen at the extra element port is
(3) e1
ZN 1 |Z2 =∞ = − . (B.7)
j1
This result is identical to the result for the first special-case impedance. This fact leads
to a numerator interaction parameter that of unity and an interesting simplification
(3)
at the first extra element port with the second extra element port open-circuited. The
result can be taken directly from the correction factor derivation for v̂/dˆ1 , for instance:
(3) Zle1 + ZL
ZD1 |Z2 =∞ = . (B.8)
M12
B.4 Derivation of Special-case Impedances for îo1/dˆ2
Designating îo1 /dˆ2 as the 4th transfer function, the superscripts for the six special-case
(4)
The first special-case impedance, ZN 1 |Z2 =0 , is the null-condition impedance at the
first extra element port with the second extra element port shorted. Because it is
a null-condition impedance, analysis of the circuit should address the fact that the
independent input in this transfer function, dˆ2 will be directed such that the first
converter’s output current, îo1 , is nulled. With this condition, and with the other
independent inputs deactivated, the input voltage can be written in terms of the
nonzero load voltage as
1 Zce1 + Zle1
v̂in = v̂ (B.9)
M1 Zce1
and the input current is the transformed current through Ce1 also written in terms
of the load voltage as
v̂
îin = M1 (B.10)
Zce1
505
and dividing the two yields the result
(4) Zce1 + Zle1

ZN 1 |Z2 =0 = . (B.11)
M12 (D1 )
(4)
The second special-case impedance, ZN 2 |Z1 =0 , is the null-condition impedance
at the second extra element port with the first extra element port shorted. The
voltage drop across the second converter’s total output impedance is zero and the
first converter output current must also be zero since the first duty ratio has been
deactivated. The output voltage must be zero since both converter output currents
are zero and that voltage appears at the secondary of the second ideal transformer.
The primary voltage of the second ideal transformer must also be zero. Therefore, the
voltage across the extra element port is simply v̂in = −e2 dˆ2 (s) and the current through
the extra element port must be îin = j2 dˆ2 (s) so that their ratio, the impedance seen
at the extra element port is
(4) e2
ZN 2 |Z1 =0 = − . (B.12)
j2
(4)
independent inputs deactivated. This condition is identical to that for the open-loop
impedance found for correcting any other transfer function. The result can be taken
directly from the correction factor derivation for v̂/dˆ1 , for instance:

ZD1 |Z2 =0 = . (B.13)
M12
ments:
ZD2 |Z1 =0 = . (B.14)
M22
The remaining two special-case impedances are needed to determine the interac-
tion parameters in the correction factor. Note that from (7.31), there is some redun-
506
(4)
dancy in the choice of these final special-case impedances. Here we derive, ZN 1 |Z2 =∞
(4) (4)
and ZD1 |Z2 =∞ . The fifth special-case impedance, ZN 1 |Z2 =∞ , is the null-condition
impedance at the first extra element port with the second extra element port open-
circuited. With this condition, and with the other independent inputs deactivated,
the input voltage can be written in terms of the nonzero load voltage as

1 Zce1 + Zle1
v̂in = v̂ (B.15)
M1 Zce1
and the input current is the transformed current through Ce1 also written in terms
of the load voltage as
v̂
îin = M1 (B.16)
Zce1
and dividing the two yields the result
(4) Zce1 + Zle1

ZN 1 |Z2 =∞ = . (B.17)
M12 (D1 )
This result is identical to the result for the first special-case impedance. This fact leads
to a numerator interaction parameter that of unity and an interesting simplification
(4)
at the first extra element port with the second extra element port open-circuited. The
result can be taken directly from the correction factor derivation for v̂/dˆ1 , for instance:
(4) Zle1 + ZL
ZD1 |Z2 =∞ = . (B.18)
M12
507
508
Appendix C
Switched-capacitor Multilevel
• Hardware
• Matlabr scripts for switched-capacitor system modeling
509
C.1. Hardware
C.1 Hardware
• Photograph
• PCB layout
• Build notes
• Bill of materials
C.1.1 Photograph
A photograph of the marx converters in the two-converter photovoltaic experimental

setup is shown in the Figure below.
Figure C-1: A closeup photograph of the two marx converters in the experimental
setup.
510
C. Switched-capacitor Multilevel Output DC/DC Converters
C.1.2 PCB Layout
Figure C-2: The Eagle Cadr PCB layout of the marx converter.
511
C.1. Hardware
Figure C-3: The Eagle Cadr PCB layout of the marx converter without ground and
power planes drawn.
512
05 May 2011,08:26 PM
Layer: marx_R1.cmp
marx_R1.zip
Figure C-4: Top copper layer
513
marx_R1.zip
Layer: marx_R1.sol
Figure C-5: Bottom copper layer

C.1. Hardware
514
05 May 2011,08:26 PM
C.1.3 Schematic Drawings
Figure C-6: Switching section
515
C.1. Hardware
Figure C-7: Gate drives, sheet 1
516
517
C.1. Hardware
518
Figure C-10: Switching pattern selection switches
519
C.1. Hardware
Figure C-11: Oscillator
520
Figure C-12: Power
521
C.1. Hardware
C.1.4 Build Notes
• Note that not all charge pumps need to be populated. Generally, for this exper-
iment only the charge pumps for M3, M6, M9, and M10 need to be populated.
• CS pins on IR2125 are grounded; should be connected to Vs...will need to hack

a fix on this rev of the PCB; and include it in any future revs..also see absolute
max ratings in 2125 Datasheet Cs must be within Vs and Vb Gnd will destroy
it
• Adjust deadtime timing resistor empirically
• Adjust zener bias diodes empirically or per time averaged source node voltage
calculation
• Adjust Rg empirically
• Adjust Zener empirically
• Add antiparallel diodes to Rg (1N4148) with anode at gate.
• Missing Vcc diodes on IR2125’s (1N4148 or MUR120)
• Oscillator is connected in such a way that D is not generally 50%. Remove 1k

resistor, NC pin 7 on the 555 and connect the 1k resistor end of the pot to pin
3.
• The values of capacitors C11 and C12 and all analogous pairs are switched in
the Eagle schematic. C11 should be 102, C12 should be 104
522
C.1.5 BOM
The Marx converter bill of materials is shown in the table below. Refer to Section
10.5 for changes.
Table C.1: Marx converter bill of materials.
Qty Value Device Parts
24 1N4148DO35-10 1N4148DO35-10 D2, D3, D4, D6, D7, D9, D10, D12, D13, D15, D16,
D18, D19, D21, D22, D24, D25, D27, D28, D30, D31,
D33, D34, D36
3 1k R-US-0207/10 R1, R3, R4
11 4 R-US-0207/10 RG1-11
11 4.7k R-US-0207/10 R5, R7, R9, R11, R13, R15, R17, R19, R21, R23, R25
11 12V Zener ZENER-DIODEDO41Z10 D5, D8, D11, D14, D17, D20, D23, D26, D29, D32, D35
1 12uF/300V C-US275-205X316 COUT-3
4 33u C-US050-050X075 C6, C7, C8, C65
1 74HC04 74ALS04N IC3
11 100k R-US-0207/10 R6, R8, R10, R12, R14, R16, R18, R20, R22, R24, R26
2 102 C2.5/6 C1, C2
11 102 C5/2.5 C12, C16, C20, C24, C28, C32, C36, C40, C44, C48, C52
11 103 C5/2.5 C13, C17, C21, C25, C29, C33, C37, C41, C45, C49, C53
38 104 C2.5/6 C3-5, C9, C10, C11, C14, C15, C18, C19, C22, C23,
C26, C27, C30, C31, C34, C35, C38, C39, C42, C43,
C46, C47, C50, C51, C54-63, C66, C67
1 105 BOURNEPOT3310Y001 R2
5 105/100V C-US225-062X268 C1-1, C2-1, C3-1, CP1, CP4
2 105/250V C-US225-087X268 COUT-1, COUT-2
5 475/100V C-US225-062X268 C1-2, C2-2, C3-2, CP2, CP5
1 680 pF C2.5/6 C64
5 685/100V C-US225-087X268 C1-3, C2-3, C3-3, CP3, CP6
1 7805 7805TV IC1
1 7812 7805TV IC4
1 CMCHOKE B82725A-CMCHOKE U5
11 ICM755 LM555N IC5, IC6, IC7, IC8, IC9, IC10,
IC11-15
11 IR2125 IR2125 U6-16
11 IRF8721 FDS5680 M1-11
1 LM555N LM555N IC2
1 MBR20100C MUR620CT D1
11 SP4T SW-C10 SW1-11
4 STANDOFF4-40 STANDOFF4-40 U17, U18, U19, U20
523
C.2. Matlabr Scripts for Switched-capacitor System Modeling
C.2 Matlabr Scripts for Switched-capacitor Sys-

tem Modeling
This Appendix includes Matlabr scripts and functions for modeling the perfor-
mance of a Marx converter system for distributed solar power processing.
C.2.1 Monte Carlo Performance Prediction
montecarlo_Io_stepping.m
This script iterates computations of the Marx converter performance through ran-
domized panel lighting levels. It records the maximum efficiency for each iteration
and averages the results among all of the iterations. The result is a statistical perfor-
mance prediction of the Marx converter system. This script requires functions:
• Io_sweep.m
• single_sim_single_Io.m
• etapsim_single_Io.m
• Qsim_single_Io.m
• Rout_lookup.m
• varycolor.m
%% P er for m many r e p e a t e d simulations of t h e PV syst em having selected a

%% random distribution of normalized insolation levels across all of the
%% p a n e l s each time . Avg t h e results to get a pr e di c ti o n of r e a l avg
%% p e r f o r m a n c e . ( Montecarlo simulation )
%% C l e a r e n v i r o n m e n t
clear
close all
%% C l e a r screen
clc
%% I n p u t s
% Figure
f ig no = 10;
524
Plotonly = 0 ;
Plot2D = 0 ;
Plot3D = 0 ;
Single system = 1;
Diode loss = 1;
%Load Data if Plotonly

if P l o t o n l y == 1
l o a d m at l ab . mat
Plotonly = 1 ;
end
% Circuit E l em en t s
%C p e r level p e r module ( i . e . the actual value of the c a p a c i t o r C)
C = 1 2 . 5 e −6;
Ron = 8 . 5 e −3; %FET Ron
Qg = 8 . 3 e −9; %Gate Charge (C)
Qoss = 5 e −9; %Qoss (C)
Qrr = 15 e −9; %R e v e r s e r e c o v e r y c h a r g e (C)
Vg = 1 0 ; %Gate D r i v e V o l t a g e (V)
f s w = 360 e3 ;
% PV P a r a m e t e r s
Voc nom = 2 9 ;
Vmp nom = 2 4 . 6 ;
Isc nom = 7 . 3 8 ;
Imp nom = 6 . 9 3 ;
%S i m u l a t i o n C o n t r o l s Converter Loss 1 : ON o r 0 : OFF −> i m p l em en t ed i n

%e t a p s i m s i n g l e I o b a s e d on Q, C, fsw , Ron
Ro = 1 ;
montecarlo length = 100;
I om i n = 0 . 0 1 ;
I o r e s c o a r s e = 20 e −3;
I o r e s f i n e = 20 e −3;
Iorescoarse = Ioresfine ;
Iomax = 6 . 9 3 ;
Qmin = 0 ;
Q r es = 1 ;
Qmaxmax = 4 ;
min number of sources = 3 ;
max number of sources = 3 ;
Compress range = 0 . 5 ;
% Make 0 f o r Iosweep to s e l e c t random I s c ’ s o r select a vector
Isc vec norm = 0 ;
%% Check t o make s u r e we can compute Ro f o r all s w i t c h i n g p a t t e r n s and s t o p if n ot

i f Qmaxmax > 7 && Ro == 1
d i s p ( ’ Dont h ave Ro v a l u e s f o r Qmax > 7 ! ! ’ )
return
end
%% C r e a t e simulation vectors
montecarlo vec = 1 : montecarlo length ;
Number of sources vec = min number of sources : max number of sources ;
if S i n g l e s y s t e m == 1
Qmax vec = Qmaxmax ;
else
Qmax vec = 1 : 1 : Qmaxmax ;
end
525
if P l o t o n l y == 0
montecarlo avg etap array = [ ] ;
montecarlo avg etac array = [ ] ;
montecarlo avg eta array = [ ] ;
f o r Qmax = Qmax vec
%% Check Rout Lookup g e t t i n g e t c = 100% f o r Qmax = 1 c a s e n ot right
Q a v a i l = Qmin : Q r es : Qmax ; %V ar yi n g Q avail ( r e s e t Qmax e a c h t i m e )
montecarlo avg etap vec = [ ] ;
montecarlo avg etac vec = [ ] ;
montecarlo avg eta vec = [ ] ;
for Number of sources = Number of sources vec
etap vec = [ ] ;
etac vec = [ ] ;
eta vec = [ ] ;
for i = montecarlo vec
Qmax
Q avail ;
Number of sources
Montecarlo N = i
r e s u l t s a r r a y = I o s w e e p ( Iomin , Ioresfine , Iorescoarse , ...
Iomax , Q avail , N u m b e r o f s o u r c e s , Voc nom , Vmp nom , ...
I sc n om , Imp nom , Ro , C, fsw , Ron , Qg , Qoss , Qrr , Vg , ...
Com p r ess r an ge , Isc vec norm , Diode loss ) ;
etap = r e s u l t s a r r a y ( : , 1 ) ;
etac = r e s u l t s a r r a y ( : , 2 ) ;
eta = r e s u l t s a r r a y ( : , 3 ) ;
% Find etamax i n d e x
etamax = max ( e t a ) ;
e t a m a x i n d e x = f i n d ( etamax == e t a ) ;
if l e n g t h ( etamax index ) > 1 % o n l y want on e
etamax index = etamax index ( 1 ) ;
end
% Find e t a p e t a c and e t a a t etamax i n d e x
etapmax = e t a p ( e t a m a x i n d e x ) ;
etacmax = e t a c ( e t a m a x i n d e x ) ;
% Concatenate onto results vectors
e t a p v e c = h o r z c a t ( e t a p v e c , etapmax ) ;
et ac v ec = horzcat ( etac vec , etacmax ) ;
e t a v e c = h o r z c a t ( e t a v e c , etamax ) ;
end
montecarlo avg etap vec = horzcat ( montecarlo avg etap vec , ...
mean ( e t a p v e c ) ) ;
montecarlo avg etac vec = horzcat ( montecarlo avg etac vec , ...
mean ( e t a c v e c ) ) ;
montecarlo avg eta vec = horzcat ( montecarlo avg eta vec , ...
mean ( e t a v e c ) ) ;
end
montecarlo avg etap array = vertcat ( montecarlo avg etap array , ...
montecarlo avg etap vec )
montecarlo avg etac array = vertcat ( montecarlo avg etac array , ...
montecarlo avg etac vec )
montecarlo avg eta array = vertcat ( montecarlo avg eta array , ...
montecarlo avg eta vec )
end
end
%% E x t r a c t converter efficiency fr om e t a p and e t a : eta = etap ∗ etac

% montecarlo avg etac array =
% 100∗ m o n t e c a r l o a v g e t a a r r a y . / m o n t e c a r l o a v g e t a p a r r a y ;
526
%% Data P l o t t i n g
Iores = Ioresfine ;
i f Ro == 0
Rout = s p r i n t f ( ’ O ff ’ ) ;
else
Rout = s p r i n t f ( ’ On ’ ) ;
end
% 2D
if Plot2D == 1
%e t a p
figure
% t i t l e a r r a y = { [ ’ Tracking Efficiency v s . Number o f Sources across
% Q {max } ’ ] ; [ ’ Q { a v a i l } = [ ’ num2str ( Qmin) ’: ’ num2str ( Q r es )
% ’ : Q {max } ] , M o n t e c a r l o L en gt h = ’
% num2str ( m o n t e c a r l o l e n g t h ) ] ; [ ’ I { o , sweep } = [ ’ num2str ( I om i n ) ’: ’
% num2str ( I o r e s ) ’: ’ num2str ( Iomax ) ’ ] A, Conv . L o s s = [ ’ Rout ’ ] ’ ] ; [ ’C
% = ’ num2str ( 1 e6 ∗C) ’ \muF, f {sw} = ’ num2str ( f s w / 1 0 0 0 ) ’ kHz ,
% R { d son } = ’ num2str ( Ron ∗ 1 0 0 0 ) ’ m\Omega , Q { g } = ’ num2str ( Qg∗1 e9 )
% ’ nC , Q { o s s } = ’ num2str ( Qoss ∗1 e9 ) ’ nC , Q { r r } = ’
% num2str ( 1 e9 ∗ Qrr ) ’ nC , V g = ’ num2str ( Vg ) ’ V ’ ] ; [ ’ V { oc } = ’
% num2str ( Voc nom ) ’ V, V {mp} = ’ num2str ( Vmp nom ) ’ V, I { sc } = ’
% num2str ( I s c n o m ) ’ A, I {mp} = ’ num2str ( Imp nom ) ’
% A’ ] ; [ ’ Distribution Com p r essi on = ’ num2str ( 1 0 0 ∗ C o m p r e s s r a n g e )
% ’% ’]};
legend vec = [ ] ;
l e g e n d v e c = Qmax vec ’ ;
ColorSet = varycolor ( length ( legend vec ) ) ;
s e t ( gca , ’ Col or O r d er ’ , ColorSet ) ;
hold all ;
plot ( Number of sources vec , montecarlo avg etap array ’ ) ;
ylabel ( ’\ eta p (%) ’)
x l a b e l ( ’ Number o f Sources ’ )
title ( title array );
g r i d on
box on
drawnow
l e g e n d ( num2str ( l e g e n d v e c ) , ’ L o c a t i o n ’ , ’ Best ’ ) ;
%e t a c
figure
% t i t l e a r r a y = { [ ’ Converter Efficiency v s . Number o f Sources across
% ’% ’]};
legend vec = [ ] ;
hold all ;
plot ( Number of sources vec , montecarlo avg etac array ’ ) ;
527
ylabel ( ’\ eta c (%) ’)
g r i d on
box on
drawnow
%e t a
figure
% t i t l e a r r a y = { [ ’ Total Efficiency v s . Number o f Sources across
% ’% ’]};
legend vec = [ ] ;
hold all ;
plot ( Number of sources vec , montecarlo avg eta array ’ ) ;
y l a b e l ( ’\ eta (%) ’)
g r i d on
box on
drawnow
end
%3D
if Plot3D == 1
% etap
figure
% t i t l e a r r a y = { [ ’ Tracking Efficiency v s . Number o f Sources across
% ’% ’]};
s u r f ( N u m b e r o f s o u r c e s v e c , Qmax vec , montecarlo avg etap array ) ;
z label ( ’\ eta p (%) ’)
528
y l a b e l ( ’ Q {max } ’ )
g r i d on
box on
drawnow
% etac
figure
% t i t l e a r r a y = { [ ’ Converter Efficiency v s . Number o f Sources across
% ’% ’]};
s u r f ( N u m b e r o f s o u r c e s v e c , Qmax vec , montecarlo avg etac array ) ;
z label ( ’\ eta c (%) ’)
y l a b e l ( ’ Q {max } ’ )
g r i d on
box on
drawnow
% eta
figure
% t i t l e a r r a y = { [ ’ Total Efficiency v s . Number o f Sources across
% ’% ’]};
s u r f ( N u m b e r o f s o u r c e s v e c , Qmax vec , montecarlo avg eta array ) ;
z l a b e l ( ’\ eta (%) ’)
y l a b e l ( ’ Q {max } ’ )
g r i d on
box on
drawnow
end
529
Io_sweep.m
This function returns all of the results for a single string current sweep.
%% Sweep I o t o find g l o b a l MPPT i n Io s t e p p i n g syst em
function r e s u l t s a r r a y = I o s w e e p ( Iomin , Ioresfine , Iorescoarse , ...
Iomax , Q avail , N u m b e r o f s o u r c e s , Voc nom , Vmp nom , I sc n om , ...
Imp nom , Ro , C, fsw , Ron , Qg , Qoss , Qrr , Vg , Com p r ess r an ge , ...
Isc vec norm , Diode loss )
%% C l e a r screen
% clc
%% P l o t ?
Plot on = 0;
%% Choose Isc ’ s : If I s c v e c n o r m = 0 , c h o o s e random I s c ’ s else use the

%% g i v e n Isc vec norm .
if I s c v e c n o r m == 0
Isc vec norm = [ ] ;
for i = 1 : Number of sources
I s c v e c n o r m = h o r z c a t ( I s c v e c n o r m , (1− C o m p r e s s r a n g e + . . .
C o m p r e s s r a n g e ∗ r an d ) ) ;
end
end
%% C o a r s e Sweep t o l o c a l i z e MPP: r e s u l t s = [ etap e t a and Q]

if I o r e s f i n e ˜= I o r e s c o a r s e
I o v e c c o a r s e = I om i n : I o r e s c o a r s e : Iomax ;
results array coarse = [ ] ;
for Io = Io ve c co a rse
Io ;
r e s u l t s = s i n g l e s i m s i n g l e I o ( Q avail , Isc vec norm , ...
Voc nom , Vmp nom , I sc n om , Imp nom , Ro , C , fsw , Ron , . . .
Qg , Qoss , Qrr , Vg , Io ) ;
r e s u l t s = horzcat ( r e s u lt s , Io , Isc vec norm ) ;
resu lts array coa rse = vertcat ( results array coarse , results );
end
%% D et er m i n e b a l l p a r k max I o
B a l l p a r k m a x I o = I o v e c c o a r s e ( f i n d ( max ( r e s u l t s a r r a y c o a r s e ( : , 1 ) ) . . .
== r e s u l t s a r r a y c o a r s e ( : , 1 ) ) ) ;
I o m i n f i n e = B a l l p a r k m a x I o −I o r e s c o a r s e ;
I o m a x f i n e = B a l l p a r k m a x I o+I o r e s c o a r s e ;
else
I o m i n f i n e = I om i n ;
I o m a x f i n e = Iomax ;
end
%% F i n e Sweep : r e s u l t s = [ etap e t a and Q]

% Bound I o sweep
I o v e c f i n e = Iominfine : I o r e s f i n e : Iomaxfine ;
results array fine = [ ] ;
for Io = I o v e c f i n e
Io ;
[ etap etac e t a Q] = s i n g l e s i m s i n g l e I o ( Q a v a i l , Isc vec norm , ...
Voc nom , Vmp nom , I sc n om , Imp nom , Ro , C, fsw , Ron , Qg , Qoss , ...
Qrr , Vg , Io , Diode loss ) ;
re s u l t s a rr a y f i n e = vertcat ( re su lts a rray f in e , ...
[ etap etac eta Q Io Isc vec norm ] ) ;
end
530
results array = results array fine ;
%% Data P l o t t i n g if P l o t o n == 1
if P l o t o n == 1
MPP etap = max ( r e s u l t s a r r a y f i n e ( : , 1 ) ) ;
i f Ro == 0
Rout = s p r i n t f ( ’ O ff ’ ) ;
else
Rout = s p r i n t f ( ’ On ’ ) ;
end
figure
plot ( I o vec f ine , results array fine (: ,1))
% t i t l e ( { [ ’ Tracking Efficiency v s . Output
% Cu r r en t ’ ] ; [ num2str ( N u m b e r o f s o u r c e s ) ’ sources ’ ] ; [ ’ Q { a v a il } = [ ’
% num2str ( Q a v a i l ) ’] , Coarse \ Delta I o = ’ num2str ( 1 0 0 0 ∗ I o r e s c o a r s e )
% ’ mA, Fine \ Delta I o = ’ num2str ( 1 0 0 0 ∗ I o r e s f i n e ) ’ mA, Conv . Loss =
% [ ’ Rout ’ ] ’ ] ; [ ’ Imp { v e c } = [ ’ num2str ( Imp nom∗ I s c v e c n o r m ) ’]
% A ’ ] ; [ ’ V { oc } = ’ num2str ( Voc nom ) ’ V, V {mp} = ’ num2str ( Vmp nom ) ’
% V, I { s c } = ’ num2str ( I s c n o m ) ’ A, I {mp} = ’ num2str ( Imp nom ) ’
% A ’ ] ; [ ’ Max Power \ e t a p = ’ num2str ( MPP etap ) ’% ’]})
xlabel ( ’ I o (A) ’ )
grid
box on
if I o r e s f i n e ˜= I o r e s c o a r s e
plot ( Io vec coarse , results array coarse (: ,1))
xlabel ( ’ I o (A) ’ )
grid
box on
end
end
% Isc vec norm
end
531
single_sim_single_Io.m
This function returns the efficiencies and conversion ratios for a single string current
value.
function [ etap etac e t a Q] = s i n g l e s i m s i n g l e I o ( Q a v a i l , Isc vec norm , ...
Voc nom , Vmp nom , I sc n om , Imp nom , Ro , C, fsw , Ron , Qg , Qoss , Qrr , ...
Vg , Io , Diode loss )
%% A s i n g l e Marx PV syst em simulation returning a set o f Qs and e t a p
%% C l e a r screen
% clc
%% D et er m i n e number o f sources fr om l e n g t h o f Isc vector

Number of sources = length ( Isc vec norm ) ;
%% D e f i n e P a n e l s
Voc vec = [ ] ;
Isc vec = [ ] ;
Vmp vec = [ ] ;
I m p vec = [ ] ;
% Th i s assu m es Imp nom i s g i v e n ( known t o t h e m a n u f a c t u r e r ) and t h a t Imp i s

% linearly proporitional to I s c wh i ch is m easu r ed i n r u n t i m e . Vmp can be
% arbitrary s i n c e we a r e m at ch i n g Iin t o Imp wh i ch i s unique to the
% maximum power p o i n t and t h u s t o t h e c o r r e c t Vmp.
% For s i m p l i c i t y and w i t h o u t significant loss of g e n e r a l i t y we can assume
% t h a t Vmp i s fixed .
for j = 1: Number of sources
Isc norm = Isc vec norm ( j ) ;
Imp = I s c n o r m ∗Imp nom ;
I s c = Isc n orm ∗ Isc nom ;
Vmp = Vmp nom ;
Voc = Voc nom ;
I m p vec = h o r z c a t ( I m p vec , Imp ) ;
I s c v e c = horzcat ( Isc vec , Isc );
Vmp vec = h o r z c a t ( Vmp vec , Vmp ) ;
V o c v e c = h o r z c a t ( V oc vec , Voc ) ;
end
%% C a l c u l a t e PV model p a r a m e t e r s a s on P . 14 o f book 9/10−

Rs vec = [ ] ;
R p vec = [ ] ;
R s v e c = h o r z c a t ( R s vec , ( V o c v e c ( j )−Vmp vec ( j ) ) . / I m p vec ( j ) ) ;
R p vec = h o r z c a t ( Rp vec , ( I s c v e c ( j ) ∗ R s v e c ( j )− V o c v e c ( j ) ) / ( I m p vec ( j ) . . .
−I s c v e c ( j ) ) ) ;
end
%% D et er m i n e actual P h o t o v o l t a i c Currents a s on P . 1 4 o f book 9/10−

Iph vec = [ ] ;
I p h v e c = h o r z c a t ( I p h v e c , I m p vec ( j )+ V o c v e c ( j ) / R p vec ( j ) ) ;
end
%% D e f i n e MP’ s
MP vec = [ ] ;
MP vec = h o r z c a t ( MP vec , I m p vec ( j ) ∗ Vmp vec ( j ) ) ;
end
532
%% Find Q
Q = Q s i m s i n g l e I o ( I m p vec , Io , Q avail ) ;
%% Compute e t a p e t a c and e t a
[ etap etac eta ] = e t a p s i m s i n g l e I o ( Number of sources , Iph vec , ...
I m p vec , V oc vec , R s vec , Rp vec , Q, MP vec , Ro , C, fsw , Ron , ...
Qg , Qoss , Qrr , Vg , Q avail , Io , Diode loss );
return
533
etapsim_single_Io.m
This function returns the efficiencies achieved for a single string current.
function [ etap etac eta ] = e t a p s i m s i n g l e I o ( Number of sources , ...
Iph vec , I m p vec , V oc vec , R s vec , Rp vec , Q, MP vec , Ro , C, ...
fsw , Ron , Qg , Qoss , Qrr , Vg , Q avail , Io , Diode loss )
%% Compute t h e tracking efficiency given a s e t o f Qs
%% C a l c u l a t e Pin o f e a c h p a n e l a s on P . 2 a t t a c h m e n t book 9/10−

Pin vec = [ ] ;
Iin vec = [ ] ;
Vin vec = [ ] ;
V o vec = [ ] ;
Rout vec = [ ] ;
Pswloss vec = [ ] ;
Vdrev vec = [ ] ;
% Ouput D i od e
Cd = 10 e −12; % Output D i od e C a p a c i t a n c e
I s = 159 e −6; % Output D i od e I s
n = 1.76; % Output D i od e Q u a l i t y factor
ESRd = 0 . 0 2 ; % Output D i od e ESR
kTonq = 25 e −3;
Vd = l o g ( I o / I s +1)∗n∗kTonq+ESRd∗ I o ; % Output D i od e i d e a l voltage

I i n = Q( j ) ∗ I o ;
% Nonlinear e q u a t i o n s f o r Vin depend on s t a t e o f PV D i od e

if I i n < I m p vec ( j ) %%D i od e on
Vin = V o c v e c ( j )− I i n ∗ R s v e c ( j ) ;
elseif I i n >= I m p vec ( j ) %% D i od e o f f
Vin = R p vec ( j ) ∗ I p h v e c ( j ) −( R s v e c ( j )+ R p vec ( j ) ) ∗ I i n ;
end
% H an d l e t h e Q = 0 Case : Load i s open n ot shorted ( Vin = Voc n ot 0 V)

i f Q( j ) == 0
Vin = V o c v e c ( j ) ;
Iin = 0; % Redundant t o I i n = Q( j ) ∗ I o
end
% Compute Pin
Pin = I i n ∗ Vin ;
% Nan Ch ecki n g
if i s n a n ( Vin ) % if Vin = 0/0 s e t it to 0
Vin = 0 ;
end
if isnan ( I i n ) % if I i n = 0/0 s e t it to 0
Iin = 0;
end
if i s n a n ( Pin ) % if Pin = 0/0 s e t it to 0
Pin = 0 ;
end
% Lossless o r n ot
i f Ro ˜= 0
Rout = R o u t l o o k u p ( Q a v a i l , Q( j ) , C, fsw , Ron ) ;
else
Rout = 0 ;
534
Qg = 0 ;
Qoss = 0 ;
Qrr = 0 ;
end
% Find s w i t c h i n g loss as a f u n c t i o n o f Vin

% Number o f active switches
i f Q( j ) ˜= 0
N = 3∗Q( j ) −2;
e l s e i f Q( j ) == 0
N = 1;
end
P s w l o s s = N∗ (Qg∗Vg∗ f s w +0.5∗ Qoss ∗ ab s ( Vin ) ∗ f s w+Qrr ∗ ab s ( Vin ) ∗ f s w ) ;
% Enumerate t h e results
R o u t v e c = h o r z c a t ( R ou t vec , Rout ) ;
Pswloss vec = horzcat ( Pswloss vec , Pswloss ) ;
V i n v e c = h o r z c a t ( V i n v e c , Vin ) ;
I in v e c = horzcat ( Iin vec , Iin );
Pin vec = horzcat ( Pin vec , Pin ) ;
V o vec = h o r z c a t ( Vo vec ,Q( j ) ∗ Vin ) ;
V d r e v v e c = h o r z c a t ( V d r ev vec ,Q( j ) ∗ Vin−Vin ) ;
end
% D eb u ggi n g and Op . Pt r e p o r t i n g
% Vin vec
% Iin vec
% V o vec
% Pin vec
% Print initial conditions referenced t o gnd t o h e l p w i t h LTSPICE
% Vin1 = V i n v e c ( 1 )
% Vin2 = V o vec (1)+ V i n v e c ( 2 )
% Vin3 = V o vec (1)+ V o vec (2)+ V i n v e c ( 3 )
% Vo1 = V o vec ( 1 )
% Vo2 = V o vec (1)+ V o vec ( 2 )
% Vo = sum ( V o vec )
%% C a l c u l a t e tracking efficiency etap

Pin = sum ( P i n v e c ) ;
MPtot = sum ( MP vec ) ;
R o u t t o t = sum ( R o u t v e c ) ;
% P d i o d e l o s s t o t = I o ∗Vd+ESRd∗ I o ˆ 2 ;
if D i o d e l o s s == 1
P d i o d e l o s s t o t = N u m b e r o f s o u r c e s ∗ I o ∗Vd + . . .
f s w ∗Cd∗sum ( V d r e v v e c . ∗ V d r e v v e c ) ;
else
Pdiodeloss tot = 0;
end
P s w l o s s t o t = sum ( P s w l o s s v e c ) ;
P r l o s s t o t = Rout tot∗ Io ˆ2;
Ploss = Pswloss tot + Pr loss t ot + Pdiodeloss tot ;
Pout = Pin−P l o s s ;
% Not i n t e r e s t e d in N e g a t i v e Power c o n d i t i o n s
if Pout < 0
Pin = 0 ;
Pout = 0 ;
end
%% R e p o r t i n g : report t h e maximum e t a p fou n d

e t a p = 100∗ Pin /MPtot ;
e t a c = 100∗ Pout / Pin ;
535
e t a = 100∗ Pout /MPtot ;
% NaN c h e c k i n g Pin = 0 −> a l l Q = 0

if isnan ( etac ) % if e t a c = 0/0 s e t it to 0
etac = 100;
end
return
536
Qsim_single_Io.m
This function returns the conversion ratios for a set of Marx converters for a single
string current based on the local maximum power point tracking algorithm.
f u n c t i o n Q vec = Q s i m s i n g l e I o ( I m p vec , Io , Q avail )
%% A s i m u l a t i o n o f the set o f Q’ s d e t e r m i n e d by e a c h module i n d e p e n d e n t l y
%% o f the others having a f i x e d I o and s e t of a v a i l a b l e Q’ s .
% clc
%% B e g i n i a l i z e the variables
Q vec = [ ] ;
Iin avail = [ ] ;
N u m b e r o f s o u r c e s = l e n g t h ( I m p vec ) ;
%% D et er m i n e t h e set of available input currents given this Io

I i n a v a i l = Q avail ∗ Io ;
%% D i s t r i b u t e panels into their a p p r o p r i a t e Q’ s

Source = j ;
I i n e r r o r = I m p vec ( j )− I i n a v a i l ;
n e g i n d i c e s = f i n d ( s i g n ( I i n e r r o r ) == −1);
p o s i n d i c e s = f i n d ( s i g n ( I i n e r r o r ) == 1 ) ;
z e r i n d i c e s = f i n d ( s i g n ( I i n e r r o r ) == 0 ) ;
Iin error neg = Iin er ror ( neg indices ) ;
Iin error pos = Iin error ( pos indices );
Iin error zer = Iin error ( zer indices );
% Would l i k e I i n = Imp , I i n < Imp , I i n > Imp i n that order of

% preference . Pin d i m i n i s h e s s l o w l y a s Iin d e c r e a s e s beyond Imp b u t
% decreases ab ru p tl y as Iin i n c r e a s e s beyond Imp .
if l e n g t h ( I i n e r r o r z e r ˜= 0 )
Q i n d ex = z e r i n d i c e s ( 1 ) ;
elseif l e n g t h ( I i n e r r o r p o s ˜=0)
p o s i n d e x = f i n d ( ab s ( I i n e r r o r p o s ) == min ( ab s ( I i n e r r o r p o s ) ) ) ;
Q i n d ex = p o s i n d i c e s ( p o s i n d e x ) ;
elseif l e n g t h ( I i n e r r o r n e g ˜= 0 )
n e g i n d e x = f i n d ( ab s ( I i n e r r o r n e g ) == min ( ab s ( I i n e r r o r n e g ) ) ) ;
Q i n d ex = n e g i n d i c e s ( n e g i n d e x ) ;
end
%a l s o o n l y want on e i n d e x n ot a wh ol e bunch
if l e n g t h ( Q i n d ex > 1 )
Q i n d ex = Q i n d ex ( 1 ) ;
end
Q = Q a v a i l ( Q i n d ex ) ;
Q vec = h o r z c a t ( Q vec , Q ) ;
end
return
537
Rout_lookup.m
This function returns the effective output resistance value for a Marx converter given
the switched-capacitor value, the switching frequency and the MOSFET on resistance
value.
function r e s u l t = R o u t l o o k u p ( Q a v a i l , Q, C, fsw , Ron )
%% M u l t i p l i e r arrays
%Check t h e s e arrays for accuracy especially regarding Q = 0 cases , t h e n go
%b ack and make s u r e FET s e l e c t i o n script is also accurate
%Qmax = 1 2 3 4 5 6 7
Rssl mult = [0 0 0 0 0 0 0; % Q = 0
0 0 0 0 0 0 0; % Q = 1
0 1 1/2 1/3 1/4 1/5 1 ; % Q = 2
0 0 2 3/2 1 5/6 2 / 3 ; % Q = 3
0 0 0 3 5/2 2 3/2; % Q = 4
0 0 0 0 4 7/2 3 ; % Q = 5
0 0 0 0 0 5 9/2; % Q = 6
0 0 0 0 0 0 6 % Q = 7
];
%Qmax = 1 2 3 4 5 6 7
Rfsl mult = [2 4 6 8 10 12 14; % Q = 0
2 4 6 8 10 12 14; % Q = 1
0 8 10 12.444 8.2 17.6 32.39; % Q = 2
0 0 26 24 38 48.4 50.8; % Q = 3
0 0 0 64 90 100 100; % Q = 4
0 0 0 0 130 180 206; % Q = 5
0 0 0 0 0 232 307; % Q = 6
0 0 0 0 0 0 378 % Q = 7
];
%% Compute a b s o l u t e SSL and FSL Rout v a l u e s

R s s l = R s s l m u l t (Q+1 ,max ( Q a v a i l ) ) ∗ 1 / (C∗ f s w ) ;
R f s l = R f s l m u l t (Q+1 ,max ( Q a v a i l ) ) ∗ Ron ;
%% FSL o r SSL
Rout = max ( R s s l , R f s l ) ;
r e s u l t = Rout ;
end
538
varycolor.m
This function was written by Daniel Helmick and was found at Matlab Central
online. It was used to control the 3D mesh color gradient in the output plots from
the Monte Carlo simulations.
function C o l o r S e t=v a r y c o l o r ( NumberOfPlots )
% VARYCOLOR P r o d u c e s c o l o r s w i t h maximum v a r i a t i o n on p l o t s with m u l t i p l e
% lines .
%
% VARYCOLOR(X) r e t u r n s a matrix of d i m e n s i o n X by 3 . The m a t r i x may be
% u sed in c o n j u n c t i o n with the p l o t command o p t i o n ’ color ’ to vary the
% color of lines .
%
% Y el l ow and White c o l o r s wer e n ot u sed because of their poor
% translation to presentations .
%
% Example Usage :
% NumberOfPlots =50;
%
% C o l o r S e t=v a r y c o l o r ( NumberOfPlots ) ;
%
% figure
% h o l d on ;
%
% f o r m=1: NumberOfPlots
% p l o t ( o n e s ( 2 0 , 1 ) ∗m, ’ Col or ’ , C o l o r S e t (m, : ) )
% end
%C r e a t e d by D a n i e l H el m i ck 8/12/200 8
e r r o r ( n a r g c h k ( 1 , 1 , n a r g i n ))% c o r r e c t number o f i n p u t arguements??

e r r o r ( nargoutchk ( 0 , 1 , n a r g o u t ))% c o r r e c t number o f output arguements??
%Take c a r e of the anomolies

if NumberOfPlots<1
ColorSet = [ ] ;
elseif NumberOfPlots==1
C o l o r S e t =[0 1 0];
C o l o r S e t =[0 1 0 ; 0 1 1];
C o l o r S e t =[0 1 0 ; 0 1 1 ; 0 0 1];
C o l o r S e t =[0 1 0 ; 0 1 1 ; 0 0 1 ; 1 0 1];
C o l o r S e t =[0 1 0 ; 0 1 1 ; 0 0 1 ; 1 0 1 ; 1 0 0];
C o l o r S e t =[0 1 0 ; 0 1 1 ; 0 0 1 ; 1 0 1 ; 1 0 0 ; 0 0 0];
e l s e %d e f a u l t and wh er e t h i s function h as an a c t u a l advantage
%we h ave 5 s e g m e n t s t o distribute the plots

EachSec= f l o o r ( NumberOfPlots / 5 ) ;
%how many e x t r a lines are there?

E x t r a P l o t s=mod ( NumberOfPlots , 5 ) ;
%i n i t i a l i z e ou r vector
539
C o l o r S e t=z e r o s ( NumberOfPlots , 3 ) ;
%Th i s is to deal with the extra plots t h a t don ’ t fit nicely into the
%s e g m e n t s
A d j u s t=z e r o s ( 1 , 5 ) ;
f o r m=1: E x t r a P l o t s
A d j u s t (m) = 1 ;
end
SecOne =EachSec+A d j u s t ( 1 ) ;
SecTwo =EachSec+A d j u s t ( 2 ) ;
S ecTh r ee =EachSec+A d j u s t ( 3 ) ;
S ecFou r =EachSec+A d j u s t ( 4 ) ;
SecFive =EachSec ;
f o r m=1: SecOne
C o l o r S e t (m, : ) = [ 0 1 (m−1)/( SecOne − 1 ) ] ;
end
f o r m=1:SecTwo
C o l o r S e t (m+SecOne , : ) = [ 0 ( SecTwo−m) / ( SecTwo ) 1];
end
f o r m=1: S ecTh r ee
C o l o r S e t (m+SecOne+SecTwo , : ) = [ (m) / ( S ecTh r ee ) 0 1];
end
f o r m=1: S ecFou r
C o l o r S e t (m+SecOne+SecTwo+S ecTh r ee , : ) = [ 1 0 ( SecFour −m) / ( S ecFou r ) ] ;
end
f o r m=1: S e c F i v e
C o l o r S e t (m+SecOne+SecTwo+S ecTh r ee+SecFour , : ) = [ ( S e c F i v e−m) / ( S e c F i v e ) 0 0];
end
end
540
Appendix D
Switched-capacitor DC/DC Marx

Converter Loss Models
D.1 Introduction
The primary goal of this work was to develop a starting point for generalizations in
loss modeling of DC/DC switched-capacitor marx converters, building from the work
in [30] by Seemen et. al. This work generally attempts to treat the marx converter as
a specific type of switched-capacitor converter. However, we will study how the marx
converter fundamentally compares and contrasts to other types of switched-capacitor
converters based on the choice of switching pattern. The result of that discussion
will be a proposed classification of marx converter configurations based on switching
patterns.
We can recognize the marx converter as both a switched-capacitor and a multilevel
output converter. The motivation here is to exploit the marx converter as an inductor-
less boosting multilevel DC/DC converter (it may be used, although under-utilized, as
a bucking DC/DC converter as well). Specifying the DC/DC case as opposed to the
DC/AC case basically indicates a load with a large enough capacitance to maintain
a fixed steady state output voltage over the timescale of one switching period. One
example will show how the efficiency and load regulation behavior of the converter
is fundamentally altered when leaving the big load capacitance limit. The implica-
541
D.1. Introduction
tions of switch implementation and its effect on the fundamental operation of these
converters will also be discussed later.
D.1.1 Literature Review
This work builds from the work by Seeman in [30]. Seeman describes a new framework
for analyzing switched-capacitor circuits that results in simple-to-understand two-port
models like that shown in Figure D-1. In Figure D-1, the ideal transformer models
the conversion from input to open-circuit output voltage and the output resistance
RO , captures both load regulation and loss in the circuit. The intent of this work was
to apply Seeman’s framework to the marx converter.
Figure D-1: The simple two-port model of switched-capacitor DC/DC converters

proposed by Seeman. The model captures open-circuit voltage, load regulation and
loss with one ideal transformer and one resistor [30].
Reference [184] by Maksimovic:PESC95 and Makowski provides analyses and mod-

eling of switched-capacitor converters that motivated Seeman to develop his new
straight forward abstractions. References [185–189] describe analyses of specific types
of switched-capacitor converters including so-called “voltage-multiplier” converters
and multilevel DC/DC converters. The principle result in reference [186] is a gen-
eralized two-port model of the AC/DC voltage multiplier circuit in what amounts
to the slow-switching-limit (SSL). In reference [185], a similar analysis is carried for
AC/DC voltage multiplier circuits in what amounts to the fast-switching-limit (FSL).
Reference [190] presents the two-port model from Figure D-1 for an FSL step-down
542
D. Switched-capacitor DC/DC Marx Converter Loss Models
switched-capacitor converter. Reference [187] details the losses in a multilevel flying

capacitor DC/DC converter using both energy methods for capacitor balancing and
enumerating power dissipated in conducting interconnects.
The main difference between the previous work and the work of Seemen et. al. is in
the simplified abstractions that he presents for both the switching speed limits. These
abstractions are drawn from a fundamental understanding of the loss mechanisms.
This work uses Seeman’s framework when it is applicable, but also uses straight
forward circuit analysis similar to that in the references described above, when the
framework is not applicable. Seemen’s framework is reviewed in Section D.6.
Reference [190] provides references for review and examples of control techniques
for multilevel output converters. In particular, it focuses on the modulation tech-
nique for DC output multi-level converters that is the crux of the switching pattern
described in Section D.7. In this modulation technique, the output is modulated
between the two levels that span the desired steady-state output voltage.
D.1.2 Analytical and Model Validation Approaches in this

Work
The analysis of marx converters here focuses on load regulation and loss modeling.
For now, each switching pattern studied is assumed to be implemented with finite
on-resistance switches that can block voltage and carry current in both directions.
Practical switch implementations must be carefully chosen to actually achieve the
behaviors developed here. That being said, switch implementations might also be
chosen to fundamentally alter the behaviors developed here. This will be discussed
further in Section D.8.
While the marx converter may be extended to an arbitrary number of output
voltage levels, the analysis here attempts to understand its load regulation and loss
behavior across the fundamental types of switching patterns by first focusing only on
the three-level cases (the simplest form of the marx converter). Section D.6 contains
an example in which the model is extended to four levels.
543
D.2. Switching Speed Limit Definitions
Model validation was carried out in simulation with LTSPICE. I found it easier
to model converter behavior across effective switching frequency regimes by varying
the switched-capacitor and output capacitor values, rather than actually varying the
switching frequency. By varying these capacitor values, I was able to model the
transition between the slow-switching-limit (SSL) and the fast-switching-limit (FSL)
behaviors without adjusting switching frequency and all of the ancillary values that
would require. Therefore, capacitor values that seem impractically large in simulation,
are only that way to demonstrate relative switching speed. In those cases, a practical
implementation of the converter could just as easily contain more reasonable capacitor
values but with an increased switching frequency instead.
Switch on-resistances are often assumed to be equal in the analyses and are always
held at Ron = 10mΩ in the simulations here.
D.2 Switching Speed Limit Definitions

As described by Seeman et. al., in the slow-switching-limit (SSL), the switched-
capacitors fully equilibrate so that capacitor currents can be modeled as impulsive,
reaching nearly zero Amps in a time that is very small compared to the switching
period [30]. On the other hand, in the fast-switching-limit (FSL), the switched-
capacitors maintain fixed voltages and capacitor currents during each switching state
are constant [30]. The plots of capacitor voltage and current in both switching limits
shown in Figure D-2 demonstrate these points for a simulated 3-level marx converter.
The two switching speed limits can be understood by considering the classic capac-
itor charging loss problem depicted in Figure D-3. The loss associated with charging
the capacitor from VC (0) for a time, t, can be found as follows. The total energy lost
is Z ∞
Etot = IC (τ )2 Rdτ (D.1)
t=o
where, by inspection the capacitor voltage is
VC (t) = (Vin − VC (0))(1 − e−t/RC ) + VC (0) (D.2)
544
Figure D-2: In the SSL, capacitor voltages equilibrate each half-cycle and currents
are impulsive. In the FSL, capacitor voltages are constant and capacitor currents are
fixed during each half cycle in the big capacitance limit.
Vin −VC (0) −t/RC

and the capacitor current, CdVc (t)/dt = R
e . Plugging this into the
integral above leads to
(Vin − VC (0))2 t
Etot =− RC e−2t/RC 0 . (D.3)
2R
At this point, we see that the value of R to the left of the exponential is about
to cancel. What is left only depends on R in the exponential term. In the slow-
switching-limit, this exponential term is allowed to collapse to (-1) because the final
time, t, is very long compared to the RC time-constants in the circuit. In that case,
the energy lost becomes
1
Etot,SSL = (Vin − VC (0))2 C (D.4)
2
or
1
Etot,SSL = C∆VC2 , (D.5)
2
545
D.2. Switching Speed Limit Definitions
Figure D-3: The canonical circuit for studying the fundamental loss associated with
charging a capacitor.
a result that is useful in calculating loss whenever a capacitor is allowed to charge

to its resting value (until no current flows). The result in eqn. (D.5) is independent
of the resistance, R, mathematically, because the exponential term containing it was
allowed to collapse in the slow-switching-limit. If, however, the exponential is not
allowed to collapse, the total energy lost becomes
1
Etot (t) = (Vin − VC (0))2 C(1 − e−2t/RC ), (D.6)
2
which does depend on R and, in the fast-switching-limit, can be viewed near t=0
with the Taylor series approximation to the exponential term so that
1 2t 0
Etot,F SL (t) = (Vin − VC (0))2 C(1 − (e0 − e t)). (D.7)
2 RC
Finally, the total loss reduces to that which we would expect for two fixed voltages
connected across the resistor:
(Vin − VC (0))2 t
Etot,F SL (t) = . (D.8)
R
The result in eqn. (D.8) does depend on R because, mathematically, the exponential
term was not allowed to collapse. When the exponential term was allowed to collapse,
the total loss necessarily simplified to a quantity fundamentally independent of R. On
the other hand, when the exponential term was not allowed to collapse, the total loss
was fundamentally dependent on the value of R. While these results apply neatly to
SSL and FSL, we will generally use this understanding to differentiate fundamental
546
loss mechanisms in the marx converter based on the instantaneous conditions imposed
on the circuit by the input source and the load.
D.2.1 Generalization of SSL to Finite R-C Loads
As stated above, in the slow-switching limit, the switched-capacitor voltages equi-

librate to the voltages connected across them each half cycle. However, when a
switched-capacitor is connected to a non-ideal voltage source, such as a finite R-C
load, during one of its phases, this statement needs to be generalized. In the SSL, the
switched-capacitor voltages equilibrate during cycles when they are connected to the
ideal input voltage source, and nearly equilibrate otherwise. Figure D-4 shows the
SSL capacitor voltage for a 3-level marx converter with a large load capacitance and
a smaller load capacitance. In these cases, SSL may be identified by the equilibration
of the switched-capacitor voltage for the phase during which it is connected to the
ideal input voltage source.
Figure D-4: In the SSL, the capacitors have time to fully equilibrate. With a finite R-
C load, the output voltage ripple allows for a time-varying equilibration point during
some phases.
547
D.3. Switching Pattern Classification of Marx Converters
D.3 Switching Pattern Classification of Marx Con-

verters
This section describes a classification of marx converters switching patterns that
differentiates the types of converters analyzed here. The switched-capacitor converters
studied in Seeman et. al. [30], largely fall into one class described here. In [30], the
author points out how the switching patterns may lead to constrained or under-
constrained charge-balance problems:
“[T]ypical of most step-down converters, the input source is connected to

the circuit during only one phase (phase 2 in this case). As no charge
flows from the input source during phase 1 (in this example), the phase-2
input-source charge flow is identified as qin . Likewise, for most step-up
converters, the output source is connected to the converter during only
one phase. For the few converters where both sources are connected to the
converter during both phases, it may be possible to determine a starting
constraint by inspection. If such a constraint does not exist, one can fall
back to the matrix-based methods [184] for determining the ac vector.” [30]
In the marx converter, it is possible to connect both sources to the circuit during
both (or all if more than two) phases. It is also possible to connect the load directly to
the input source or directly to ground. In this work, I consider “single-phase” patterns
that drive the load during one phase, leaving it disconnected during the other phase,
and also “multi-phase” patterns that drive the load during more than one phase. I
also consider “non-isolated” switching patterns which include a phase that connects
the load directly to the input source (or ground) and “isolated” patterns which only
drive the load with switched-capacitors.
For this work, I organized the types of converters (switching patterns) analyzed
into the chart shown in Table D.1. In Section D.8, I suggest how a more complete
classification might be made. For now, the classification proposed here separates
my analyses into demonstrative examples. For instance, the “Class-II” switching
548
patterns are similar to those analyzed by Seeman et. al. and the Class-III patterns
are similar to multilevel output DC/DC converters. The Class-0, single-phase non-
isolated pattern is not useful for boosting DC/DC converters because it requires
that the load be connected directly to ground or the input during one phase and
disconnected during the other. Therefore, I analyzed only Class-I,II, and III types
from Table D.1.
Table D.1: Classification of Switching Patterns Analyzed
non-isolated isolated
single-phase 0 II
multi-phase I III
D.4 3-Level Marx Switch States

An example FET implementation of a three-level marx converter and the idealized
switch implementation are shown in Figure D-5. The ideal implementation is the one
analyzed in this work.
The three-level marx converter is capable of driving its output to 0,1, or 2 times
its input voltage. For each case, there are generally redundant switching states that
produce the same desired output voltage. Here, I considered only non-destructive
switch states, i.e. ones that did not short the input source directly to ground. Non-
destructive “Zero-states” (meaning states that drive the output to 0V) for the 3-level
marx converter are depicted in Figures D-6. Non-destructive “one-states” and “two-
states” are shown in Figures D-7 and D-8 respectively.
In this work, I am mostly concerned with one and two-states to produce a step-
up in voltage from input to output. Within the one-states, states 1 − 1v′ drive the
output directly from the input source. State 1v′′ drives the output with the switched-
capacitor, C1 . Also, states 1′′ , 1′v , 1v and 1v′ discharge C1 , while state 1′ recharges C1
and states 1 and 1′′′ do not charge or discharge C1 .
549
D.4. 3-Level Marx Switch States
(a) An FET implementation of a 3-level marx converter.
(b) Ideal switch representation of a 3-level marx converter.
Figure D-5: 3-level marx converter example FET implementation and the ideal switch
implementation used for the analysis here.
There is only one two-state for the three-level marx and it is shown in Figure D-8.
In the two-state, the output is driven by the series combination of the input source
and the switched-capacitor.
One can already understand that the degree to which the switched-capacitor can
hold up the output voltage during states 1v′′ and 2 is related to both loss and load
regulation. A heavier load will draw more charge per unit time from the capacitor in
these states leading to a drop in the capacitor voltage and a corresponding drop in the
average output voltage of the converter. Furthermore, this same drop in the capacitor
voltage leads to a loss proportional to 1/2(∆VC )2 fsw , so the same mechanism that
accounted for output voltage droop or load regulation also accounts for loss.
Reducing the effective output resistance can be accomplished by increasing the

capacitance value or by increasing the switching frequency. Either approach reduces
the total change in voltage on the capacitor for a given load current. Increasing the
switching frequency or the capacitor value enough causes the voltage on the capacitor
550
(a) 0 (b) 0′
(c) 0′′ (d) 0′′′
Figure D-6: 0-output switch states.
to remain fixed and yields the fast-switching-limit. In the FSL, the output resistance
is lower-bound by the resistances of the interconnects in the circuit, which are usually
dominated by the on-state resistances of the switches. Therefore, we expect to see
effective resistances in the SSL like 1/C1 fsw and in the FSL like Ron .
D.5 Class-I Marx
The first type of switching pattern that I studied was the Class-I marx. This class
is fundamentally different from the switched-capacitor circuits considered in [30].
Here, the input source is connected directly to the output during one phase (phase
1) while the switched-capacitor drives the output toward twice the input voltage
during a second phase (phase 2). Because charge is transferred, during phase 1,
directly between the input source and load, the periodic steady state charge balance
constraint on the switched-capacitor is not sufficient to constrain the total charge to
the output. This means that the charge-balance analysis used by Seeman does not
apply well to this class of switching patterns. The need for an additional constraint
will be evident in the analysis below.
In the case of the three-level class-I marx, phase 1 must be switching state 1′ drawn
551
D.5. Class-I Marx
(a) 1 (b) 1′
(c) 1′′ (d) 1′′′
(e) 1′v (f) 1v
(g) 1v′ (h) 1v′′
Figure D-7: 1-states.
in Figure D-7 because phase 2 must be switching state 2 and the switched-capacitor
must be recharged during each cycle. The two states are shown simplified in Figure
D-9.
This converter can be solved for output voltage, Vout , in the slow switching limit as
follows. We first assume that the output voltage is fixed at some steady-state value,
Vout , because it contains a sufficiently large capacitance Cout . We also assume that
the switched-capacitor equilibrates quickly during each half cycle as defined by the
552
Figure D-8: The only 2-state (2).
(a) Phase 1 (b) Phase 2
Figure D-9: The two simplified switching states of the class-1 converter.
SSL. Since we are looking for the average output voltage, we can write
< Vout >=< Iout > Rload (D.9)
where < Iout > is the average current into the load:
(1) (2)
< Iout >= fsw (∆qout + ∆qout ) = fsw (∆qout ) (D.10)
and the superscripts denote phases. Now, the charge delivered to the load in phase 1
is
(1) (1) (1)
∆qout = −∆qin − ∆qC , (D.11)
where ∆qc is the charge delivered to C1 . From Figure D-9, the charge delivered
to the load in phase 2 all comes from the capacitor. In periodic steady state, the
charge off the capacitor in phase 2 must equal the charge onto it in phase 1, so
(2) (2) (1)
∆qout = −∆qc = +∆qc . This is the charge-balance constraint. Therefore, the total
output charge over one full cycle is
(1) (2) (1)

∆qout = ∆qout + ∆qout = −∆qin . (D.12)
553
D.5. Class-I Marx
(1)
To find ∆qin , in this case, we can integrate the input current during phase 1 as
follows. Z !
t1 (1)
(1) Vin − Vc (τ )
−∆qin = dτ, (D.13)
0 Rsw3
where t1 is the time spent in phase 1. The capacitor voltage during phase 1 can be
shown to be
Vin + Vout Vin + Vout
Vc(1) (t) = Vc (0) − e−t/τ1 + , (D.14)
2 2
where we have assumed, in calculating the capacitor voltage, that Rsw3 = Rsw4 = Ron
and also τ1 = Ron C1 /2. Carrying out the integral in eqn. (D.13) leads to

(1) 1 1 1 3 −t1/τ 1
−∆qin = t1 (Vin − Vout ) + ( Vout − Vin )τ1 (e − 1) , (D.15)
Ron 2 2 2
which, in the SSL reduces to
(1) 1
−∆qin = (Vin − Vout )t1 = ∆qout , (D.16)
2Ron
meaning that the short charge time of the switched-capacitor could have been ignored
and only the current transferred directly from the input to the load considered. The
expression in (D.16) can be identified as the necessary additional constraint that
charge-balance analysis alone would not have provided in the class-1 converter. It
captures the energy lost when the input source is connected directly to the load and
depends on Ron and t1 , fundamentally different from the losses associated with SSL
charging and discharging of the switched-capacitor.
Now, the average output current becomes
fsw
< Iout >= t1 (Vin − Vout ). (D.17)
2Ron
Combining this with eqn. (D.9) and assuming a 50% duty ratio, so that t1 = Tsw /2
the output voltage becomes

Rload
Vout = Vin . (D.18)
4Ron + Rload
554
The result in eqn. (D.18) is just an expression of the fact that the switched-capacitor
really does nothing in the slow-switching limit. Connecting the input source to load
“D” of the time leads to (1/D) times the series resistance between the input source
and the output during phase 1. Therefore, we can see that this switching pattern will
not allow a step-up in voltage for a DC output voltage in the SSL. Varying the duty
ratio will vary the coefficient that appears in front of the Ron term in the denominator
of eqn. (D.18), changing the effective output resistance of the converter but still not
allowing a step-up in voltage.
A plot of the result from eqn. (D.18) is shown compared to simulated data for a
three-level class-I marx converter. Note that as the load capacitance is increased in
simulation the load regulation curve approaches that of the model which assumes a
fixed DC output voltage corresponding to Cout = ∞.
Figure D-10: Load regulation in the SSL class-I three-level marx for D=0.5.
Because the SSL class-I marx behaves like a resistor, it is not useful as a boosting
DC/DC converter. However, it is interesting to point out at this point how the
behavior of this converter changes as the load capacitance varies. That is to say, the
555
D.5. Class-I Marx
converter’s “load regulation” and efficiency depend on how fixed the output voltage
is. Plots of simulated data for load regulation and efficiency across values of the
load capacitance are shown in Figures D-11(a) and D-11(b) respectively. As the load
capacitance decreases, the converter starts to behave like a DC/AC converter or a
DC/DC converter with increasing output voltage ripple. It should be clear from the
plots of Figure D-11 that if the load were not treated correctly, i.e. in the big load
capacitance limit, the wrong behavior could be inferred.
556
(a) Simulated load-regulation across load capacitance.
(b) Simulated efficiency across load capacitance.
Figure D-11: SSL Class-I simulated load regulation and η: the fundamental behavior
of the marx converter changes between DC/DC mode (big Cload ) and DC/AC mode
(small Cload ).
557
D.5. Class-I Marx
Although the class-I converter in SSL was not useful as a boosting DC/DC con-
verter, we can also consider the fast-switching-limit. In the FSL, the capacitor voltage
is fixed. Again, referring to Figure D-9, the output voltage can be solved for as follows.
Starting from the constraint that
Vout = Iout Rload , (D.19)
where average quantities Vout and Iout are now assume without the carats. The time-
averaged output current is
(1) (2)
Iout = (1 − D)Iout + DIout . (D.20)
Solving the two states for their output currents yields
Rsw2 Rsw2
(1) Vc − Vout (1 + Rsw3
) + V
Rsw3 in
Iout = Rsw2
(D.21)
Rsw4 + R sw3
(Rsw3 + Rsw4)
(2) Vin + Vc − Vout
Iout = (D.22)
Rsw1 + Rsw4
where Rswi is the on-resistance of the ith switch (all assumed to be Ron previously).
The second constraint is that the average capacitor current is zero (charge balance)
and can be written:
(1 − D)Ic(1) + DIc(2) = 0. (D.23)
Solving the capacitor current in the two states yields
R +R R +R
1 Vout (1 − sw3Rsw4 sw4 ) + Vc sw3Rsw4 sw4 − Vin
Ic(1) = (D.24)
Rsw3 1+ R sw2
Rsw4
(Rsw3 + Rsw4 ) Rsw31
Vin + Vc − Vout
Ic(2) = (D.25)
Rsw1 + Rsw4
Combining these two independent equations yields the capacitor voltage, Vc and the
output voltage, Vout , in terms of D ′ s and Rsw
′
s in closed form. After simplification
558
and assuming that all switches have on-resistance Ron , the output voltage becomes
Vin D ′ Rload (2D ′ + 3D)

Vout = (D.26)
2(D ′ )2 Rload + 2D ′Rload D + 4D ′ Ron + 3DRon
and the capacitor voltage becomes
−(−2D ′ Ron − D ′ Rload D − 2(D ′ )2 Rload + 3DRon )Vin

Vc = (D.27)
2(D ′ )2 Rload + 2D ′Rload D + 4D ′ Ron + 3DRon
The loss can be derived by adding up the losses in the switches as follows. The losses
in the two phases are
(1) (1) (1)

Ploss = (Ic(1) )2 Rsw2 + (Iout )2 Rsw4 + (Ic(1) − Iout )2 Rsw3 (D.28)
(2) (Vin + Vc − Vout )2
Ploss = , (D.29)
Rsw1 + Rsw4
(1) (1)
where Ic and Iout were solved for above. The time-averaged loss is
(1) (2)
Ploss,tot = D ′ Ploss + DPloss . (D.30)
Combining eqns. (D.29) with eqns. (D.25), (D.22), (D.26)and (D.27) yields the power
loss in closed form. Finally, efficiency can be calculated as
Ploss
η = (1 + 2
)−1 . (D.31)
Vout /Rload
Model validation plots of load regulation and efficiency for the FSL class-1 marx are
shown in Figure D-12.
559
D.5. Class-I Marx
(a) Load-regulation
(b) Efficiency
Figure D-12: Model and simulation of load regulation and efficiency plots at FSL for
the Class-I marx converter.
560
These results show that the FSL class-I marx may produce a step-up in voltage.
However, efficiencies are generally poor and are at a maximum for a narrow load
range. The control approach here would perhaps be to adjust the duty ratio in order
to optimize efficiency as the load varies.
D.6 Class-II Marx

The framework developed by Seemen et. al. can be directly applied to the class-II
marx switching patterns. These consist of one phase in which the switched-capacitors
are connected to the input source and one phase when they are connected to the
output. In neither phase, is there a direct connection between the input and output
source so all of the loss and load regulation is the result of capacitor charging and
discharging. Therefore, charge-balance analysis can fully constrain the analysis of
these switching patterns. Starting with the three-level marx, we can build the loss
model shown in Figure D-1 for both switching speed limits.
Here, we choose the switching state shown in Figure D-13 as the phase 1 state
to recharge the capacitor while the load is disconnected. The other state is chosen
Figure D-13: The recharging state.
to achieve a step-up in voltage using state 2. The two states are shown simplified in
Figure D-14. The charge-balance analysis here is well-constrained enough that the
open-circuit voltage transfer and the output resistance can be found simultaneously.
561
D.6. Class-II Marx
Figure D-14: The two simplified switching states of the class-1 converter.
In the SSL, the charge-balance analysis goes as follows.
Phase 1 Phase 2
(1) (2)
∆qc = qA ∆qc = −qout
(1) (2)
∆qin = −qA ∆qin = −qout
(1) (2)
∆qout = 0 ∆qout = qout
From the charge balance constraint imposed on the capacitor in periodic steady state,
qA = −qout . The charge multiplier vectors are
(1) (1)
a(1)
c = [∆qout /qout , ∆qc(1) /qout , ∆qin /qout ] (D.32)
(2) (2)
a(2)
c = [∆qout /qout , ∆qc(2) /qout , ∆qin /qout ], (D.33)
where qout is the total charge into the load. These vectors become
a(1)
c = [0, 1, −1] (D.34)
a(2)
c = [1, −1, −1], (D.35)
and the sum of the two, ac , is

ac = [1, 0, −2] (D.36)
which says that qin /qout = −2 so that the open-circuit voltage transfer ratio is
qin
M =− =2 (D.37)
qout
because the open-circuit voltage indicates the no-loss case. (The vector ac should also
562
have zero values for all entries other than the ends). From Seeman et. al. [30], the
slow-switching-limit output resistance is
X (ac,i )2
RSSL = (D.38)
i
Ci fsw
which can be evaluated for either charge multiplier vector and becomes
1
RSSL = (D.39)
fsw C1
for this three-level marx. The FSL output resistance can be taken from the switch
multiplier vector, which keeps track of the charge through each interconnect in order
to maintain the same charge-balance constraint above. Using the reference polarities
on the switches, the switch multiplier vector consists of the charge through each
interconnect, when it is on, normalized by the total output charge, qout .
(2) (1) (1) (2) (1)

ar = [ar1 , ar2 , ar3 , ar4 , ar5 ] = [−1, 1, 1, 1, 0]. (D.40)
From Seeman et. al., the FSL output resistance can be found as
X Ri (ar,i )2
RF SL = (D.41)
i
Di
where Ri is the ith switch on-resistance, and Di is the duty ratio corresponding to the
phases during which the respective switches are on. Defining DTsw as the time spent
in phase 2, the FSL output resistance becomes
Rsw1 Rsw2 Rsw3 Rsw4

RF SL = + + + . (D.42)
D 1−D 1−D D
If we assume that all switch resistances are Ron , this results simplifies to
2Ron
RF SL = , (D.43)
D(1 − D)
563
D.6. Class-II Marx
while the open-circuit voltage above applies here as well. Finally, efficiency can be
taken directly from the model proposed by Seeman in Figure D-1 as
Req
η =1− . (D.44)
Req + Rload
These results were compared to simulated data. First, the simulated output resis-
2
tance, calculated as Ploss,meas /Iout,meas was plotted against the SSL and FSL output
resistance asymptotes in Figure D-15, showing good agreement.
Figure D-15: Simulated and modeled output resistance across switching speed limits.
Model validation plots of load regulation and efficiency for both switching speed
limits are shown in Figure D-16. These plots show that as the load becomes heavier,
the converter’s efficiency decreases. That is, the class-II converter is very efficient
when the load voltage is close to the open-circuit voltage of the converter. One can
think of this behavior as that of a linear regulator. Therefore, we could regulate the
output voltage by varying the output resistance using the switching frequency of the
class-II converter.
564
(a) SSL Load Regulation (b) SSL Efficiency
(c) FSL Load Regulation (d) FSL Efficiency
Figure D-16: Model and simulation of load regulation and efficiency plots at SSL and
FSL.
The FSL model also shows that efficiency gets worse as we depart from a 50%
duty ratio. In the FSL, the optimal duty ratio for efficiency can be calculated as
follows.
dRF SL −D −2 1
= Ron + (D.45)
dD (1 − D) D(1 − D)2
and setting this derivative equal to zero leads to the expression
Dopt = 1 − Dopt (D.46)
which is only satisfied for

Dopt = 0.5 (D.47)
565
D.6. Class-II Marx
as confirmed by the plot in Figure D-17.
Figure D-17: Simulated and modeled efficiency, η, vs. Rload across duty ratio, D.
D.6.1 Extension to 4-Level Example
The charge balance analysis above can be easily extended to more than three levels.
A four-level marx converter is depicted in Figure D-18. First, we consider briefly the
converter’s behavior when boosting to two times the input voltage.
The switching states that allow boosting to twice the input voltage are shown in
Figure D-19. There are three redundant 2-states and one useful recharge state that
recharges both switched-capacitors, C1 and C2 , which we will call the ⋆-state.
This example highlights a subtlety in the calculation of RF SL . In Seeman [30], only
switches that are on during one phase and off during the other are ever considered.
This is because if a switch is on in both phases, the converter could presumably be
implemented without it. However, when using a marx converter in the way that I am
proposing, we may want to keep those switches around to, for instance, “reconfigure”
566
(a) An FET implementation of a 4-level marx converter.
(b) Ideal switch representation of a 4-level marx converter.
Figure D-18: 4-level marx converter example FET implementation and the ideal
switch implementation used for the analysis here.
the converter between the 1-2 boosting mode here and the 1-3 boosting mode that I
analyze later. For now, I analyze the FSL case assuming that “always-on” switches
are ideal because they could be eliminated. However, to analyze the so-called recon-
figurable converter that includes those switches’ on-resistances, I will show how the
effect of their losses can be added back into the final result.
Charge balance analysis for the three possible switching patterns in the SSL yields
the following results. For each converter the open-circuit voltage gain in both the SSL
and FSL is always
M =2. (D.48)
The output resistances are,
567
D.6. Class-II Marx
(a) Phase 1
(b) Phase 2 choices
Figure D-19: The simplified switching states of the four-level class-2 converter for
boosting to twice the input voltage.
Pattern RSSL RF SL
1 2Ron
⋆−2 C2 fsw D(1−D)
1 2Ron
⋆ − 2′ C1 fsw D(1−D)
C1 +C2 8(D−2)
⋆ − 2′′ C1 C2 fsw D(1−D)
where we have assumed that all switches have on-state resistance Ron and D cor-
responds to the time spent in phase 2. From this analysis, either of the first two
switching patterns wins over the third in both switching speed limits based on output
resistance.
In order to add back in the effect of the always-on switches in a reconfigurable
marx converter the RF SL results would be modified as follows. Now, the switch
multiplier vector ar cannot generally be written as a the superposition of the two
switch multiplier vectors. Instead, we would keep track of the switch multiplier vectors
(1) (2)
for each phase ar and ar since the always-on switches will have non-zero entries in
568
both. The current in each switch during each phase is
(j)
(j) qr,i fsw
ir,i = (j)
(D.49)
Di
so that we can write the currents in terms of the switch multiplier vector entries in
each phase:
(j) (j)
(j) ar,i qout fsw ar,i iout
ir,i = (j)
= (j)
. (D.50)
Di Di
Now, the time-averaged power loss in general is the sum of each i2 Ron loss for all
switches:  !2 
(j)
1  (j) ar,i iout
Ploss = Di Tsw Ri (j)
 (D.51)
Tsw Di
over all i switches and over all j phases. Then, the loss in the always-on switches is
(j)
X (ar,i )2 i2out
Ploss,alwayson = Ri (j)
(D.52)
i,j Di
and the total loss is the sum of the losses in the always-on switches and the normal
switches:
Ploss,tot = Ploss,alwayson + Pnormal . (D.53)
Because all charge is still transferred through capacitor charging and discharging, we
can assume a loss model like the one shown in Figure D-1 so that the equivalent output
resistance is just RF SL = Ploss,tot /i2out . Now, the new output resistance becomes
(j)
X (ar,i )2 X (ar,i )2
RF SL,new = Ri (j)
+ Ri (D.54)
i−alwayson,j Di i−normal
Di
where the first term is new and the second term is the old expression for RF SL .
Finally, we can study the four-level marx boosting to three times the input voltage.
The switching states for this case are shown in Figure D-20.
The charge balance analysis goes as follows.
569
D.6. Class-II Marx
(a) Phase 1
(b) Phase 2
Figure D-20: The simplified switching states of the four-level class-2 converter for
boosting to three times the input voltage.
Phase 1 Phase 2
(1) (2)
∆qin = −qA ∆qc = −qout
(1) (2)
∆qc1 = qA − qB ∆qin = −qout
(1) (2)
∆qc2 = qB ∆qin = −qout
(1) (2)
∆qout = 0 ∆qout = qout
and the periodic state charge balance conditions on the switched-capacitors yields
qA − qB = qout (D.55)
qB = qout (D.56)
570
so that the charge multiplier vectors become
a(1)
c = [0, 1, 1, −2] (D.57)
a(2)
c = [1, −1, −1, −1] (D.58)
ac = [1, 0, 0, −3] (D.59)
implying the open circuit voltage transfer ratio of
M =3 (D.60)
and the SSL output resistance
1 1
RSSL = + . (D.61)
C1 fsw C2 fsw
Inspecting the circuits in Figure D-20 with the charge multiplier vectors above
yields the switch multiplier vector
ar = [1, −2, −2, 1, 1, −1, 1, 0] (D.62)
and noting that the duty ratio D corresponds to the time spent in state-3, the FSL
output resistance becomes
1 1
RF SL = (Rsw1 + Rsw4 + Rsw7 ) + (4Rsw2 + 4Rsw3 + Rsw5 + Rsw6 ). (D.63)
D 1−D
If we assume that all switches have the same on-resistance,
3Ron 10Ron
RF SL = + . (D.64)
D 1−D
Model validation plots of load regulation and efficiency for both switching speed
limits are shown in Figure D-21. These plots, like the ones for the three-level class-II
marx, show that efficiency is best when the output voltage equals the open-circuit
output voltage. They also show that both load regulation and efficiency are best at a
571
D.6. Class-II Marx
50% duty ratio as derived above. Because the class-II marx operates most efficiently
when the open-circuit output voltage equals the load voltage (light loads), it may be
advantageous to use a so-called reconfigurable class-II marx converter that can switch
between boosting modes. For instance, this four-level converter might boost to three
times the input voltage under some conditions but if the load becomes heavier or if the
input voltage increases, it might be reconfigured in real-time to boost only to twice
the input voltage. Both of these modes can be achieved with the switching patterns
described and analyzed in this section. This real-time reconfiguring approach may be
one way that the marx converter could be controlled to efficiently regulate the output
voltage amidst load and input voltage variations.
(a) SSL Load-regulation (b) SSL efficiency
(c) FSL Load-regulation (d) FSL efficiency
Figure D-21: Model and simulation agreement of load regulation and efficiency for
the four-level marx boosting to three times the input voltage.
572
D.7 Class-III Marx
The class-III marx is similar to multi-level DC/DC converters because it drives the
output to two different voltage levels. In order to balance the switched-capacitors,
recharge phases must be included between states that drive the output to the two
levels. Therefore, for the three-level marx, the switching pattern ends up being that
shown in Figure D-22. Phases 1 and 3 are both the recharge switch state from the
class-II three-level marx and are the three-level equivalent of the ⋆-state from the
four-level class-II marx. Phases 2 and 4 come from the marx switch states presented
in the beginning of this work.
(c) Phase 3 (d) Phase 4
Figure D-22: The four simplified switching states of the class-III converter. Phases 1
and 3 are the same recharging switch state.
I approached the analysis of the class-III marx in the SSL as follows. Using the
573
D.7. Class-III Marx
fact that the switched-capacitor equilibrates during each phase to
Vc(1) = Vin (D.65)
Vc(2) = Vout (D.66)
Vc(3) = Vin (D.67)
Vc(4) = Vout − Vin , (D.68)
so that the changes in capacitor voltage from cycle-to-cycle are
∆Vc(1−2) = Vout − Vin (D.69)
∆Vc(2−3) = Vin − Vout (D.70)
∆Vc(3−4) = 2Vin − Vout (D.71)
∆Vc(4−1) = Vout − 2Vin (D.72)
and adding up the 1/2C∆VC2 losses per cycle the time averaged power loss is
Ploss = C1 fsw ((Vout − 2Vin )2 + (Vout − Vin )2 ). (D.73)
From here, we can recognize the loss terms and try to form a loss model of this
converter. The proposed loss model, shown in Figure D-23, includes a resistance that
bridges the ideal transformer as well as one that looks like the output resistance in
the original loss model of Figure D-1.
Figure D-23: The loss and load regulation model for the class-III marx.
574
From the proposed loss model in Figure D-23, the open circuit voltage can be found
using KCL and taking into account the ideal transformation of the input voltage to
the secondary:
Vin − Voc Voc − 2Vin
= , (D.74)
Req1 Req2
where Req1 = Req2 = 1/fsw C1 . Now the open circuit voltage can be solved as
3
Voc = Vin (D.75)
2
as we’d expect from the action of the converter. By applying the load to the loss
model, the load regulation of the output voltage can be found again with KCL,
Vin − Voc Voc − 2Vin

= + Iout , (D.76)
Req1 Req2
where we can substitute Iout = Vout /Rload (time-averaged quantities) and collect terms
to get

Rload
Vout = 3Vin (D.77)
2Rload + Req
where Req = 1/fsw C1 .
Now, efficiency can be calculated as
Ploss
η = 1− , (D.78)
Pin
where Ploss can be found by plugging the output voltage from eqn. (D.77) into eqn.
(D.73) to get a closed-form expression of Ploss .
Pin can be calculated by finding Iin from the loss model as
5Vin − 3Vout
Iin = (D.79)
Req
into which we can plug Vout from eqn. (D.77) to get a closed-form expression of
Pin = Vin Iin and the efficiency in the slow-switching-limit.
In the FSL, we treat the capacitor voltage as fixed. Adding up the switch losses
575
D.7. Class-III Marx
in each phase leads to the time-averaged power loss:
(Vc − Vin )2 (1) (Vc − Vout )2 (2) (Vin + Vc − Vout )2 (4)

Ploss = 2D + D + D , (D.80)
2Ron 2Ron 2Ron
where we have assumed that all switches have on-resistance Ron and that the time
spent in phases 1 and 3 are the same and represented by D (1) = D (3) . Note that
D (1) + D (2) + D (3) + D (4) = 1.
The capacitor voltage can be found from the charge-balance constraint
X Vin − Vc (1) Vout − Vc (2) Vout − Vc − Vin (4)

Ron i(j)
c = 0 = 2D + D + D (D.81)
j
2 2 2
which leads to (2) +D (4)

Vin (D (1) − 21 D (4) ) + Vout ( D 2
)
Vc = D (2) +D (4)
. (D.82)
D (1) + 2
The output voltage can be found from Vout = Iout Rload :
Rload
Vout = D (2) (Vc − Vout ) + D (4) (Vin + Vc − Vout ) . (D.83)
2Ron
Plugging Vc into this expression for Vout leads to the closed-form solution. Finally,
efficiency here can be calculated as
Ploss
η = (1 + 2
)−1 (D.84)
Vout /Rload
using the expression for Ploss in eqn. (D.80) with the expressions for capacitor voltage
in eqn. (D.82) and output voltage in eqn. (D.83). Model validation plots of load
regulation and efficiency for the class-III marx in both switching speed limits are
shown in Figure D-24. In the FSL plots, the duty ratio is the time spent in phase 2
with respect to phase 4 holding the total D (2) + D (4) = 0.5.
From the plots, we see that in the SSL, this converter can achieve a step-up in
voltage but suffers from poor efficiency. On the other hand, in the FSL, the converter
can achieve both a variable step-up in voltage and good efficiency for extreme duty
576
ratios as defined above. In the class-III marx, efficiency is best at some optimum load
point as opposed to the class-II marx, for which the lightest load is optimum.
From these observations, we can conclude that the class-II converter is best suited
for light loads or situations in which the open-circuit output voltage of the converter
can be adjusted to suit the load. On the other hand, the class-III converter may
achieve better efficiencies at medium loads. Further work might investigate how the
converter behaves in FSL when varying all four duty ratios D (1) , D (2) , D (3) and D (4)
for the four phases in the class-III switching pattern.
(a) SSL Load-regulation (b) SSL efficiency
(c) FSL Load-regulation (d) FSL efficiency
Figure D-24: Model and simulation agreement of load regulation and efficiency for
the three-level class-III marx.
577
D.8. Discussion, Conclusion, and Further Work
D.8 Discussion, Conclusion, and Further Work
This work should serve as a vantage point from which further work could investigate
how to effectively utilize the marx converter as a DC/DC converter. The analysis and
model validation of the types of converters here are intended to serve as demonstrative
examples of how one could treat the converter under different switching patterns.
The results show that the class-I converter generally yields poor efficiency and can
only provide a step-up in voltage in the fast-switching-limit. However, the class-II
converter yields excellent efficiency at light loads, similar to the switched-capacitor
converters analyzed by Seeman et. al. in [30], and may be reconfigured on the fly to
match the load voltage to the convert’s open-circuit output voltage in order to regulate
efficiently despite load and input variations. Furthermore, the class-III converter
shows good efficiency especially at extreme duty ratios and medium loads. Therefore,
sophisticated control approaches could reconfigure the marx converter between classes
of switching patterns to achieve good efficiency across a wide range of loads.
In the analyses provided here, the switches were assumed to be able to block
voltage and carry current in both directions. This assumption directly impacts the
analysis of the converters. Figure D-25 shows one example of a switch implementa-
tion that enables bidirectional carrying and blocking. Further work might investigate
optimal switch implementations for each class of switching pattern or for converters
that are intended to be reconfigured between switching patterns. Further work might
also show how the converter might be fundamentally altered by changing the switch
implementation characteristics. It may be that there are switching pattern-switch
implementation combinations that lead to very advantageous converter characteris-
tics.
The switching pattern classification proposed here is not intended to be complete.

It is only intended to organize the converters analyzed. Therefore, further work could
generalize the switching pattern classification. For instance, a complete switching pat-
tern classification could capture patterns in which the input and output are connected
to the circuit an arbitrary number of times per full cycle and how these intersect with
578
Figure D-25: A “fully-capable” switch implementation.
the isolated and non-isolated cases. Ultimately, such classifications along with their
loss models could be generalized to an arbitrary number of levels. Also, there are
several loss mechanisms not considered here such as gate loss. Study of these loss
mechanisms could ultimately lead to preference of one redundant switching pattern
over another or even one switching pattern classification over another.
Finally, the effect of adding the loss due to always-on switches back into the class-II
reconfigurable converter could be validated against simulation. Also, all of the results
could also be generalized to capture differences in on-state switch resistances, whereas
in these analyses, I generally assumed that they were all the same for simplicity.
579
D.8. Discussion, Conclusion, and Further Work
580
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Analysis, Modeling and Design of Energy

Management and Multisource Power Systems

Submitted to the Department of Electrical Engineering and Computer Science

Thesis Supervisor: Steven B. Leeb

2 Analysis and Modeling of Fully-differential Closed-loop Op-amp Cir-

2.3.1 Model Correction . . . . . . . . . . . . . . . . . . . . . . . . . 62

3 Capacitive Sensing Fluorescent Lamps 79

3.3.15 The Eﬀect of Stray Input Capacitance on Noise . . . . . . . . 116

4 Dimmable Solid-state Lamp with Integral Occupancy Detection 161

4.2.7 Analysis of Power Electronic Losses . . . . . . . . . . . . . . . 174

5 Standalone Capacitive Sensing Occupancy Detectors 187

6 Analysis and Modeling of Feedback-regulated Multi-converter, Multi-

6.7.1 Closed-loop Transfer Functions . . . . . . . . . . . . . . . . . 240

7 The Effect of Multiple Input Filters in Multi-converter, Multi-source

8 Design Example 1: Run-time Integral Diagnostics of a Grid-Tied

8.5 Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297

9 Design Example 2: Run-time Integral Diagnostics of a Fuel Cell

10 Per-Panel Photovoltaic Energy Extraction with Switched-capacitor

10.3 Switched-capacitor Implementation . . . . . . . . . . . . . . . . . . . 359

A Capacitive Sensing Occupancy Detection 391

A.1.5 BOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404

B Multi-converter Systems 479

C Switched-capacitor Multilevel Output DC/DC Converters 509

D Switched-capacitor DC/DC Marx Converter Loss Models 541

D.8 Discussion, Conclusion, and Further Work . . . . . . . . . . . . . . . 578

2-1 A FD closed-loop op-amp circuit . . . . . . . . . . . . . . . . . . . . 42

3-21 An example FastCapr output matrix . . . . . . . . . . . . . . . . . . 128

3-22 Fluorescent bulb voltage (top) and current (bottom). . . . . . . . . . 131

3-23 Photographs of the hanging lamp experimental setup. . . . . . . . . . 134

3-24 Comparison between simulated and measured occupancy sensor output

3-25 A SPICE simulation of the capacitive model, F-D Transimpedance

3-26 The block diagram of the auto-dimming lamp sensor. Transimpedance

3-27 A simpliﬁed schematic of the frequency-controlled dimming ballast.

4-1 Bidirectional LED modules. . . . . . . . . . . . . . . . . . . . . . . . 164

4-11 Training runs (source calibration) x = 0 cm . . . . . . . . . . . . . . 179

7-1 The EET can be applied by considering the special-case impedances

8-1 Conceptual diagram of SOFC energy conversion. . . . . . . . . . . . . 280

8-5 io2 /io1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

8-6 |iin1 /vref 1 |. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

8-7 |v/iref 1|. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290

8-11 Correction factors CF (1) and CF (2) with system parameters: VF C =

8-12 Schematic illustration of stack, power electronics, and measurements.

8-13 Measured and predicted stack current as a function of time. . . . . . 297

8-14 Stack current and voltage, measured as indicated in ﬁg:hybridex1 8-

9-5 The basic input ﬁlter topology . . . . . . . . . . . . . . . . . . . . . . 308

9-7 Input ﬁlter transfer functions . . . . . . . . . . . . . . . . . . . . . . 311

9-10 The lead compensator subtractor and gain circuit . . . . . . . . . . . 315

9-11 First converter’s control voltage to ﬁrst converter’s output current.

A-1 Photographs of the lamp sensor electronics and electrodes. . . . . . . 393

A-4 Top copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396

A-5 Bottom copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 397

A-6 Inner copper layer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 398

A-7 Inner copper layer 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 399

A-11 Photographs of the dimming ballast, Rev. 2 PCB. . . . . . . . . . . . 406

A-14 Top copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409

A-15 Bottom copper layer. . . . . . . . . . . . . . . . . . . . . . . . . . . . 410

A-16 Inner copper layer 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . 411

A-17 Inner copper layer 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 412

A-18 Dimming ballast, Rev. 2 schematic . . . . . . . . . . . . . . . . . . . 413