CS4238B

CrystalClear Advanced Audio System with 3D Sound

• Integrated QSOUND® 3D Sound Technology General Description
• Compatible with Sound Blaster , Sound Blaster®
The CS4238B is a single chip multimedia audio system
ProTM, and Windows Sound SystemTM
that provides compatibility with the Microsoft Windows
• Advanced MPC3-Compliant Input and Output Mixer Sound System standard and will run software written to
• Enhanced Stereo Full Duplex Operation the Sound Blaster and Sound Blaster Pro interfaces.
• Dual Type-F DMA Support The CS4238B is fully compliant with Microsoft’s PC’ 97
• Industry Leading Delta-Sigma Data Converters and WHQL audio requirements. The product includes
• Fully Plug-and-Play ISA Compatible an internal FM synthesizer and Plug-and-Play external

• 3.3 V or 5 V ISA Bus Operation

interfaces for Wavetable, CD-ROM, and modem de-
vices. In addition, the CS4238B includes hardware
• Programmable Power Management
master volume control pins as well as extensive power
• Hardware Master Volume Control
management and QSOUND 3D sound technology.
• Enhanced Digital Gameport
• CS9236 Wavetable Digital Audio Interface
• MPU-401 MIDI Interface
• Consumer IEC-958 Digital Output (S/PDIF)
ORDERING INFORMATION:
• CS4236/CS4232/CS4231 Register Compatible CS4238B-KQ 100 pin TQFP, 14x14x1.4mm

XTALI XTALO VREF REFFLT L/RFILT

OSCILLATOR VREF

INPUT MIXER
Sample Rate
Converters

LINEAR

Σ
SAMPLE

Stereo

µ-LAW
A/D
FIFO

ISA GAIN GAIN L/RLINE

16

BUS A-LAW
SD<7:0> INTERFACE ADPCM

SA<11:0> GAIN L/RAUX1

IOR
SERIAL
IOW PLUG SHIFT
AND L/RAUX2
Loopback GAIN
AEN PLAY CMAUX2
Monitor
Attenuation
CODEC
IOCHRDY GAIN L/RMIC
REG
I/F
IRQ<A:F> FM
Synthesizer
DRQ<A:C> Config GAIN
IO
IRQ ATTN. MIN
DACK<A:C>
Sample Rate

DMA
Converters

Σ
LINEAR OUTPUT MIXER
SAMPLE

DIGITAL MOUT
µ-LAW
FIFO

Σ
MIXER
16

QSound

Decode A-LAW
Stereo
DSP

Σ
D/A

Logic ADPCM GAIN L/ROUT

DIGITAL/ MPU-401 Peripherals XIOW

CS9236 DSP Synth. Interface WSS
SA<12:15> ANALOG UART or Hardware & XIOR
CD-ROM, Modem, or SERIAL SERIAL S/PDIF SBPRO
(CDROM) JOYSTICK with Volume Control EEPROM XD<7:0>
Upper Address Bits PORT PORT Registers
(Modem) LOGIC FIFOS Interface XA<2:0>

JOYSTICK WAVETABLE DSP SERIAL MIDI SCS/ SINT/ MUTE BRESET

SERIAL PORT PORT UP DOWN

Advanced Product Information This document contains information for a new product. Cirrus
Logic, Inc. reserves the right to modify this product without notice.
Cirrus Logic, Inc SEP ’97
P.O. Box 17847, Austin, TX 78760 Copyright  Cirrus Logic, Inc. 1997 DS215PP4
(All Rights Reserved)
(512) 445 7222 Fax: (512) 445 7581 1
http://www.cirrus.com
 CS4238B

TABLE OF CONTENTS

CS4238B PERFORMANCE SPECIFICATIONS 3 CS9236 WAVETABLE SERIAL DATA PORT....78

GENERAL DESCRIPTION ................................. 12 WSS CODEC SOFTWARE DESCRIPTION .......79
ISA Bus Interface............................................. 13 Calibration ........................................................79
PLUG AND PLAY ............................................... 15 Changing Sampling Rate .................................80
PnP Data ......................................................... 16 Changing Audio Data Formats.........................81
Loading Resource Data................................... 17 Audio Data Formats .........................................81
Loading Firmware Patch Data......................... 17 DMA Registers .................................................85
The Crystal Key ............................................... 18 Digital Loopback...............................................86
Bypassing Plug and Play................................. 19 Timer Registers ................................................86
Hardware Configuration Data .......................... 20 WSS Codec Interrupt .......................................86
Hostload Procedure ......................................... 24 Error Conditions ...............................................87
External E2PROM............................................ 24 DIGITAL HARDWARE DESCRIPTION...............87
WINDOWS SOUND SYSTEM CODEC .............. 26 Bus Interface ....................................................87
Enhanced Functions (MODEs)........................ 26 Volume Control Interface .................................87
FIFOs ............................................................... 27 Crystal/Clock ....................................................88
WSS Codec PIO Register Interface ................ 27 General Purpose Output Pins ..........................88
DMA Interface.................................................. 28 Reset and Power Down ...................................89
Sound System Codec Register Interface ........ 29 Multiplexed Pin Configuration...........................89
Direct Mapped Registers (R0-R3) ............... 29 ANALOG HARDWARE DESCRIPTION .............90
I/O Data Registers (R3) ............................... 34 Line-Level Inputs Plus MPC Mixer...................90
Indirect Mapped Registers (I0-I31) .............. 35 Microphone Level Inputs ..................................91
WSS Extended Registers (X0-X25) ............ 48 Mono Input .......................................................91
SOUND BLASTER INTERFACE........................ 57 Line-Level Outputs ...........................................92
Mode Switching ............................................... 57 Mono Output with Mute Control .......................92
Sound Blaster Register Interface .................... 57 Miscellaneous Analog Signals..........................92
Sound Blaster Mixer Registers .................... 59 GROUNDING AND LAYOUT ..............................92
GAME PORT INTERFACE ................................. 60 POWER SUPPLIES.............................................93
CONTROL INTERFACE ..................................... 61 ADC/DAC FILTER RESPONSE..........................95
Control Register Interface................................ 61 PIN DESCRIPTIONS ...........................................97
Control Indirect Registers (C0-C8) .................. 65 ISA Bus Interface Pins .....................................98
QSound 3D Sound Overview .......................... 68 Analog Inputs ...................................................99
The QXpander 3D Stereo Process ................. 69 Analog Outputs.................................................100
QXpander Space Control ................................ 69 MIDI Interface...................................................101
QXpander Volume Control .............................. 70 External FM Synthesizer Interface ...................101
Speakers vs. Headphones .............................. 70 External Peripheral Port ...................................101
QSound Guide to Optimal Listening................ 70 Joystick/DSP Serial Port Interface ...................103
Consumer IEC-958 Digital Output................... 71 CS9236 Wavetable Serial Port Interface .........104
MPU-401 INTERFACE ........................................ 72 CDROM Interface.............................................105
MPU-401 Register Interface ............................ 72 Volume Control.................................................106
MIDI UART ...................................................... 73 Miscellaneous ...................................................106
MPU-401 "UART" Mode Operation ................. 73 Power Supplies ................................................107
FM SYNTHESIZER (Internal)............................. 73 PARAMETER DEFINITIONS...............................108
EXTERNAL PERIPHERAL PORT...................... 74 PACKAGE PARAMETERS .................................109
Synthesizer Interface ....................................... 74 APPENDIX A: E2PROM TYPICAL DATA ..........110
CDROM Interface ............................................ 75 APPENDIX B: CS4238B DIFFERENCES...........112
Modem Interface.............................................. 76
DSP SERIAL AUDIO DATA PORT.................... 76

Windows and Windows Sound System are registered trademarks of Microsoft Corporation.
Sound Blaster and Sound Blaster Pro are registered trademarks of Creative Labs.
Adlib is a registered trademark of Adlib Corporation.
QSOUND, QXpander, Q1, QSpace, Virtual Audio and the QSound Logo are registered trademarks of QSound Labs, Inc.
QSound technology is protected by US and foreign patents.

2 DS215PP4
 CS4238B

ANALOG CHARACTERISTICS TA = 25 °C; VA, VD1, VDF1-VDF4 = +5V

Input Levels: Logic 0 = 0V, Logic 1 = VD1; 1 kHz Input Sine wave; Sample Frequency, Fs = 44.1 kHz;
Measurement Bandwidth is 20 Hz to 20 kHz - unweighted, 16-bit linear coding.)
Parameter* Symbol Min Typ Max Units
Analog Input Characteristics - Minimum Gain Setting (0dB); unless otherwise specified.
ADC Resolution (Note 1) 16 Bits
ADC Differential Nonlinearity (Note 1) ±0.5 LSB
Instantaneous Dynamic Range Line Inputs IDR 80 85 dB
(Note 2) Mic Inputs 72 79 dB
Total Harmonic Distortion Line Inputs THD 0.006 0.02 %
Mic Inputs 0.01 0.025 %
Interchannel Isolation Line to Line Inputs 80 dB
Line to Mic Inputs 80 dB
Line-to-AUX1 90 dB
Line-to-AUX2 90 dB
Interchannel Gain Mismatch Line Inputs ±0.5 dB
Mic Inputs ±0.5 dB
Programmable Input Gain Span Line Inputs 21.5 22.5 dB
Gain Step Size 1.3 1.5 1.7 dB
ADC Offset Error 0 dB gain ±10 ±100 LSB
Full Scale Input Voltage: (MGE=1) MIC Inputs 0.26 0.28 Vpp
(MGE=0) MIC Inputs 2.6 2.8 Vpp
LINE, AUX1, AUX2, MIN Inputs 2.6 2.8 Vpp
Gain Drift ±100 ppm/°C
Input Resistance (Note 1) Mic Inputs 8 11 kΩ
Other Inputs 20 23 kΩ
Input Capacitance (Note 1) 15 pF
Notes: 1. This specification is guaranteed by characterization, no production testing.
2. MGE = 1 (see WSS Indirect Reg I0, I1).

*Parameter definitions are given at the end of this data sheet.

Specifications are subject to change without notice.

DS215PP4 3
 CS4238B

ANALOG CHARACTERISTICS (Continued)

Parameter* Symbol Min Typ Max Units

Analog Output Characteristics - Minimum Attenuation (0dB); unless otherwise specified.
DAC Resolution (Note 1) 16 Bits
DAC Differential Nonlinearity (Note 1) ±0.5 LSB
Dynamic Range -Total All Outputs TDR 95 dB
-Instantaneous IDR 80 85 dB
Total Harmonic Distortion (Note 3) THD 0.01 0.02 %
Interchannel Isolation Line Out (Note 3) 95 dB
Interchannel Gain Mismatch Line Out ±0.1 ±0.5 dB
Voltage Reference Output - VREF 2.0 2.2 2.5 V
Voltage Reference Output Current - VREF (Notes 1,4) 100 400 µA
DAC Programmable Attenuation Span 100 106.5 dB
DAC Attenuation Step Size +12 dB to -81 dB 1.3 1.5 1.7 dB
-82.5 dB to -94.5 dB 1.0 1.5 2 dB
DAC Offset Voltage ±1 ±10 mV
Full Scale Output Voltage: OUT, MOUT (Notes 3) 2.6 2.8 3.2 Vpp
Gain Drift 100 ppm/°C
Deviation from Linear Phase (Passband) (Note 1) 1 Degree
External Load Impedance (Note 1) 10 kΩ
Mute Attenuation 80 dB
Total Out-of-Band Energy 0.6xFs to 100 kHz (Note 1) -45 dB
Audible Out-of-Band Energy 0.6xFs to 22 kHz (Fs=8kHz) -70 dB
(Note 1)
Power Supply
Power Supply Current Digital, Operating 80 91 mA
Analog, Operating 25 31 mA
Total Operating 105 122 mA
Total Power Down 100 400 µA
Power Supply Rejection 1 kHz (Note 1) 40 dB
Notes: 3. 10 kΩ, 100 pF load.
4. DC current only. If dynamic loading exists, then the voltage reference output must be buffered
or the performance of ADCs and DACs will be degraded.

4 DS215PP4
 CS4238B

MIXERS (TA = 25 °C; VA, VD1, VDF1-VDF4 = +5V; Input Levels: Logic 0 = 0V, Logic 1 = VD1;
1 kHz Input Sine wave, Measurement Bandwidth is 20 Hz to 20 kHz - unweighted.
Parameter Symbol Min Typ Max Units
Mixer Gain Range Span LINE, AUX1, AUX2 45 46.5 dB
MIC, MIN 42 45 dB
Hardware Master 44 48 dB
(Digital) Wavetable, Monitor, PC Wave, DSP, FM 90 94.4 dB
Step Size MIC, LINE, AUX1, AUX2 1.3 1.5 1.7 dB
MIN 2.3 3.0 3.7 dB
Hardware Master 1.6 2.0 2.4 dB
(Digital) Wavetable, Monitor, PC Wave, DSP, FM 0.9 1.5 2.0 dB
Dynamic Range -Total 94.5 dB
(Analog Mixers) -Instantaneous 91 dB
Total Harmonic Distortion (Note 3) 0.002 %
(Analog Mixers)

ABSOLUTE MAXIMUM RATINGS (AGND, DGND, SGND = 0V, all voltages with respect to 0V.)
Parameter Symbol Min Max Units
Power Supplies: Digital VD1 -0.3 6.0 V
VDF1-VDF4 -0.3 6.0 V
Analog VA -0.3 6.0 V
Total Power Dissipation (Supplies, Inputs, Outputs) 1 W
Input Current per Pin (Except Supply Pins) -10.0 +10.0 mA
Output Current per Pin (Except Supply Pins) -50 +50 mA
Analog Input Voltage -0.3 VA+0.3 V
Digital Input Voltage: SA<11:0>, IOR, IOW, AEN
SD<7:0>, DACK<A:C> -0.3 VD1+0.3 V

All other digital inputs -0.3 VDF+0.3 V

Ambient Temperature (Power Applied) -55 +125 °C
Storage Temperature -65 +150 °C
Warning: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.

RECOMMENDED OPERATING CONDITIONS (AGND, DGND, SGND = 0V,

all voltages with respect to 0V.)
Parameter Symbol Min Typ Max Units
Power Supplies: Digital VD1 4.75 5.0 5.25 V
(Note 5) 3.0 3.3 3.6 V
Digital Filtered VDF1-VDF4 4.75 5.0 5.25 V
Analog VA 4.75 5.0 5.25 V
Operating Ambient Temperature TA 0 25 70 °C
Note 5. When VD1 is powered from 3.3 Volts, all ISA bus input pins, except DRQA, must also be 3.3 Volts.
DRQA is internally powered from the VDF supply and must have a 5 Volt interface. To use DRQA in
a 3.3 Volt application, a level translator is needed.

DS215PP4 5
 CS4238B

DIGITAL FILTER CHARACTERISTICS (Note 1)

Parameter Symbol Min Typ Max Units
Passband 0 0.40xFs Hz
Frequency Response -1.0 +0.5 dB
Passband Ripple (0-0.40xFs) ±0.1 dB
Transition Band 0.40xFs 0.60xFs Hz
Stop Band 0.60xFs Hz
Stop Band Rejection 74 dB
Group Delay 8- and 16-bit formats 10/Fs s
Stereo ADPCM format 14/Fs s
Mono ADPCM format 18/Fs s
Group Delay Variation vs. Frequency ADCs 0.0 µs
DACs 0.1/Fs µs

DIGITAL CHARACTERISTICS (TA = 25°C; VA, VDF1-VDF4 = 5V, VD1 = 5V/3V;

AGND, DGND1, SGND1-SGND4 = 0V.)

Parameter Symbol Min Max Units

High-level Input Voltage Digital Inputs VIH 2.0 V
XTALI VD-1.0 V
Low-level Input Voltage VIL 0.8 V
High-level Output Voltage:
ISA Bus Pins (except DRQA) I0 = -24.0 mA VOH 2.4 VD1 V
DRQA I0 = -24.0 mA 2.4 VDF V
IOCHRDY, SDA/XD0 (Note 6) 2.4 VDF V
All Others I0 = -1.0 mA 2.4 VDF V
Low-level Output Voltage: ISA Bus Pins I0 = 24.0 mA VOL 0.55 V
I0 = 18.0 mA 0.4 V
IOCHRDY I0 = 8.0 mA 0.4 V
All Others I0 = 4.0 mA 0.4 V
Input Leakage Current (Digital Inputs) -10 10 µA
Output Leakage Current (High-Z Digital Outputs) -10 10 µA
Note 6. Open Collector pins. High level output voltage dependent on external pull up (required) used and
number of peripherals (gates) attached.

6 DS215PP4
 CS4238B

Timing Parameters(TA = 25 °C; VA, VD1, VDF1-VDF4 = +5V; outputs loaded with 30pF
Input Levels: Logic 0 = 0V, Logic 1 = VD1)
Parameter Symbol Min Max Units
E2PROM Timing (Note 1)
SCL Low to SDA Data Out Valid tAA 0 3.5 µs
Start Condition Hold Time tHD:STA 4.0 µs
Clock Low Period tLSCL 4.7 µs
Clock High Period tHSCL 4.0 µs
Start Condition Setup Time tSU:STA 4.7 µs
(for a Repeated Start Condition)
Data In Hold Time tHD:DAT 0 µs
Data In Setup Time tSU:DAT 250 ns
SDA and SCL Rise Time (Note 7) tR 1 µs
SDA and SCL Fall Time tF 300 ns
Stop Condition Setup Time tSU:STO 4.7 µs
Data Out Hold Time tDH 0 ns
Notes 7. Rise time on SDA is determined by the capacitance of the SDA line with all connected gates and the
external pullup resistor required.

tF t HSCL t LSCL tR

XA0/SCL

t SU:STA t HD:STA t HD:DAT t SU:DAT t SU:STO

XD0/SDA (IN)

t AA t DH

XD0/SDA (OUT)

E2PROM 2-Wire Interface Timing

DS215PP4 7
 CS4238B

TIMING PARAMETERS (Continued)

Parameter Symbol Min Max Units
Parallel Bus Timing
IOW or IOR strobe width tSTW 90 ns
Data valid to IOW rising edge (write cycle) tWDSU 22 ns
IOR falling edge to data valid (read cycle) tRDDV 60 ns
SA <> and AEN setup to IOR or IOW falling edge tADSU 22 ns
SA <> and AEN hold from IOW or IOR rising edge tADHD 10 ns
DACK<> inactive to IOW or IOR falling edge (DMA cycle tSUDK1 60 ns
immediately followed by a non-DMA cycle) (Note 8)
DACK<> active from IOW or IOR rising edge (non-DMA tSUDK2 0 ns
cycle completion followed by DMA cycle) (Note 8)
DACK<> setup to IOR falling edge (DMA cycles) tDKSUa 25 ns
DACK<> setup to IOW falling edge (Note 8) tDKSUb 25 ns
Data hold from IOW rising edge tDHD2 15 ns
DRQ<> hold from IOW or IOR falling edge DTM(I10) = 0 tDRHD 45 ns
(assumes no more DMA cycles needed) DTM(I10) = 1 -25
Time between rising edge of IOW or IOR to next falling tBWDN 80 ns
edge of IOW or IOR
Data hold from IOR rising edge tDHD1 0 25 ns
DACK<> hold from IOW rising edge tDKHDa 25 ns
DACK<> hold from IOR rising edge tDKHDb 25 ns
RESDRV pulse width high (Note 1) tRESDRV 1 ms
Initialization Time (Note 1, 9) tINIT 130 1200 ms
EEPROM Read Time (Note 1, 10) tEEPROM 1 420 ms
XTAL, 16.9344 MHz, frequency (Notes 1, 11) 16.92 16.95 MHz
XTALI high time (Notes 1, 11) 24 ns
XTALI low time (Notes 1, 11) 24 ns
Sample Frequency (Note 1) Fs 3.918 50 kHz
Serial Port Timing
SCLK rising to SDOUT valid (Note 1) tPD1 60 ns
SCLK rising to FSYNC transition (Note 1) tPD2 -20 20 ns
SDIN valid to SCLK falling (Note 1) tS1 30 ns
SDIN hold after SCLK falling (Note 1) tH1 30 ns
Notes: 8. AEN must be high during DMA cycles.
9. Initialization time depends on the power supply circuitry, as well as the the type of clock used.
10. EEPROM read time is dependent on amount of data in EEPROM. Minimum time relates to no
EEPROM present. Maximum time relates to EEPROM data size of 2k bytes.
11. The Sample frequency specification must not be exceeded.

8 DS215PP4
 CS4238B

t
pd2
FSYNC SF1,0=01,10

t t
pd2 pd2
FSYNC SF1,0=00

SCLK
t
t s1
sckw t
h1
SDIN MSB, Left

SDOUT MSB, Left

t
pd1

DSP Serial Port Timing

DRQ<>

t DKSUa t DRHD

DACK<>

t STW t DKHDb

IOR

t RDDV t DHD1

SD<7:0>

8-Bit Mono DMA Read/Capture Cycle

t RESDRV

RESDRV

t t EEPROM
INIT

XD0/XA0 EEPROM read

SD<7:0> Codec responds to ISA activity

Reset Timing

DS215PP4 9
 CS4238B

DRQ<>

t DKSUb t DRHD

DACK<>

t STW t DKHDa

IOW

t WDSU t DHD2

SD<7:0>

8-Bit Mono DMA Write/Playback Cycle

DRQ<>

DACK<>

IOR/IOW

tBWDN

LEFT/LOW RIGHT/HIGH
SD<7:0> BYTE BYTE

8-Bit Stereo or 16-Bit Mono DMA Cycle

DRQ<>

DACK<>

IOR/IOW
t BWDN

LEFT/LOW LEFT/HIGH RIGHT/LOW RIGHT/HIGH

SD<7:0> BYTE BYTE BYTE BYTE

16-Bit Stereo or ADPCM DMA Cycle

10 DS215PP4
 CS4238B

DRQ<>

t SUDK1 t SUDK2

DACK<>

IOR

t RDDV t DHD1

SD<7:0>

t ADSU t ADHD

SA<>

AEN

I/O Read Cycle

DRQ<>

t SUDK1 t SUDK2

DACK<>

t STW

IOW

t WDSU tDHD2

SD<7:0>

t ADSU tADHD

SA<>

AEN

I/O Write Cycle

DS215PP4 11
 CS4238B

GENERAL DESCRIPTION LOGICAL DEVICE 3: MPU401

This device is comprised of six physical devices
LOGICAL DEVICE 4: CDROM
along with Plug-and-Play support for two addi-
tional external devices. The internal devices are: LOGICAL DEVICE 5: Modem
Windows Sound System Codec
Sound Blaster Pro Compatible Interface Logical Device 0 consists of three physical de-
Game Port (Joystick) vices. The WSS Codec and the Synthesizer are
Control grouped together since the original Windows
MPU-401 Sound System board expected an FM synthesizer
FM Synthesizer if the codec was present. The Sound Blaster Pro
The two external devices are: Compatible interface, SBPro, is also grouped to
IDE CDROM allow the WSS Codec and the SBPro to share
Modem Interrupts and DMA channels. The Synthesizer
device could be the internal FM synthesizer, or a
A full ISA interface with Plug and Play compati- synthesizer externally located on the Peripheral
bility and an External Peripheral Port for Port. The external synthesizer interface supports
interfacing to external devices (i.e. Wave-Table both FM and wavetable synthesizers such as the
Synthesizer, CDROM, and Modem) is included. CS9233. The WSS Codec, FM synthesizer, and
Since the Wave-Table Synthesizer and CDROM the SBPro compatible devices are internal to the
analog inputs are external, mapping as shown in part.
Figure 5, on page 58, must be used to maintain
Sound Blaster compatibility, i.e. CDROM analog Logical Device 1 is the Game Port that supports
must be connected to the AUX2 analog inputs of up to two joystick devices.
the mixer.
Logical Device 2 is the Control device that sup-
On power up, this part requires a RESDRV sig- ports global features of the part. This device uses
nal to initialize the internal configuration. When I/O locations to control power management,
initially powered up, the part is isolated from the joystick rate, and PnP resource data loading.
bus, and each device supported by the part must
be activated via software. Once activated, each Logical Device 3 is the MPU-401 interface. The
device responds to the resources given (Address, MPU-401 MIDI interface includes a 16-byte
IRQ, and DMA channels). The eight devices FIFO for data transmitted out the MIDOUT pin
listed above are grouped into six logical devices, and a 16-byte FIFO for data received from the
as shown in Figure 1 (bracketed features are sup- MIDIN pin.
ported, but typically not used). The six logical
devices are: Logical Device 4 supports an IDE CDROM con-
nected to the peripheral port. This interface, on
LOGICAL DEVICE 0: the external peripheral port, can support
Windows Sound System Codec (WSS Codec) CDROMs with up to 8 I/O locations and sup-
Adlib/Sound Blaster-compatible Synthesizer ports both the base address and the alternate base
Sound Blaster Pro Compatible Interface address, an interrupt, and a DMA channel. Al-
though this logical device is listed as a CDROM,
LOGICAL DEVICE 1: Game Port
any external device that fits within the resources
LOGICAL DEVICE 2: Control listed above may be substituted.

12 DS215PP4
 CS4238B

PnP ISA Bus

Interface

Logical Device 0 Logical Device 1 Logical Device 2 Logical Device 3 Logical Device 4 Logical Device 5

WSS Codec: Game Port: Control: MPU-401: CDROM: Modem:

I/O: WSSbase I/O: GAMEbase I/O: CTRLbase I/O: MPUbase I/O: I/O: COMbase
2 DMA Chan. [1 Interrupt] 1 Interrupt CDbase [1 Interrupt]
1 Interrupt ACDbase
[1 Interrupt]
[1 DMA Chan.]

Figure 1. Logical Devices

Synthesis:
I/O: SYNbase
[1 Interrupt]

municate with the various functional blocks

SBPro: within the part via two types of accesses: Pro-
I/O: SBbase
(DMA shared)
grammed I/O (PIO) access, and DMA access.
(Interrupt shared)
A number of configuration registers must be pro-
grammed prior to any accesses by the host
computer. The configuration registers are pro-
Logical Device 5 supports a modem connected grammed via a Plug-and-Play configuration
to the peripheral port. This interface, on the ex- sequence or via configuration software provided
ternal peripheral port, supports modems with 2 by Crystal Semiconductor.
to 256 I/O locations (only SA2-SA0 are buffered
through the part) and supports a base address I/O CYCLES
and an interrupt. Although this logical device is
Every device that is enabled, requires I/O space.
listed as a modem, any external device that fits
An I/O cycle begins when the part decodes a
within the resources listed above may be substi-
valid address on the bus while the DMA ac-
tuted.
knowledge signals are inactive and AEN is low.
The IOR and IOW signals determine the direc-
ISA Bus Interface
tion of the data transfer. For read cycles, the part
The 8-bit parallel I/O and 8-bit parallel DMA will drive data on the SD<7:0> lines while the
ports provide an interface which is compatible host asserts the IOR strobe. Write cycles require
with the Industry Standard Architecture (ISA) the host to assert data on the SD<7:0> lines and
bus. The ISA Interface enables the host to com- strobe the IOW signal. Data is latched on the ris-
ing edge of the IOW strobe.

DS215PP4 13
 CS4238B

I/O ADDRESS DECODING DMA CYCLES

The logical devices use 10-bit or 12-bit address The part supports up to three 8-bit ISA-compat-
decoding. The Synthesizer, Sound Blaster, Game ible DMA channels. The default hardware
Port, MPU-401, CDROM, and Modem devices connections, which can be changed through the
support 10-bit address decoding, while the Win- hardware configuration data, are:
dows Sound System and Control devices support DMA A = ISA DMA channel 0
12-bit address decoding. Devices that support DMA B = ISA DMA channel 1
10-bit address decoding, require A10 and A11 be DMA C = ISA DMA channel 3
zero for proper decode; therefore, no aliasing oc-
curs through the 12-bit address space. The typical configuration would require two
DMA channels. One for the WSS Codec and
To prevent aliasing into the upper address space, Sound Blaster playback, and the other for WSS
a "16-bit decode" option may be used, where the Codec capture (to support full-duplex). The
upper address bits SA12 through SA15 are con- CDROM, if used, can also support a DMA chan-
nected to the part. SA12-SA15 are then decoded nel, although this is not typical.
to be 0,0,0,0 for all logical device address de-
coding. When the upper address bits are used, DMA cycles are distinguished from control reg-
the CDROM and Modem interfaces are no ister cycles by the generation of a DRQ (DMA
longer available since the upper address pins are Request). The host acknowledges the request by
multiplexed with the CDROM and Modem inter- generating a DACK (DMA Acknowledge) sig-
faces (See Reset and Power Down section). If nal. The transfer of audio data occurs during the
the CDROM or Modem is needed, the circuit DACK cycle. During the DACK cycle the ad-
shown in Figure 2 can replace the SA12 through dress lines are ignored.
SA15 pins and provide the same functionality.
Four cascaded OR gates, using a 74ALS32, can The digital audio data interface uses DMA re-
replace the ALS138 in Figure 2, but causes a quest/grant pins to transfer the digital audio data
greater delay in address decoding. between the part and the ISA bus. Upon receipt
of a DMA request, the host processor responds
ISA Bus 74ALS138 with an acknowledge signal and a command
1 15
SA12 A Y0 AEN strobe which transfers data to and from the part,
2
SA13 B Y1 eight bits at a time. The request pin stays active
SA14 3
C Y2 until the appropriate number of 8-bit cycles have
Y3
occurred. The number of 8-bit transfers will vary
depending on the digital audio data format, bit
Y4
4 resolution, and operation mode.
SA15 G2A Y5
5 Y6
AEN G2B The DMA request signal can be asserted at any
6
+5V G1 Y7 time. Once asserted, the DMA request will re-
main asserted until a complete DMA cycle
occurs. A complete DMA cycle consists of one
Figure 2. 16-bit Decode Circuit or more bytes depending on which device inter-
nal to the part is generating the request.

14 DS215PP4
 CS4238B

The CM isolates the cards, assigns Card Select

INTERRUPTS Numbers, reads PnP card resource requirements,
For Plug-and-Play flexibility, six interrupt pins and allocates resources to the cards based on
are supported, although only one or two are typi- system resource availability. The ICU is used to
cally used. The default hardware connections, keep the BIOS and the CM informed of the cur-
which can be modified through the hardware rent system configuration. It also aids users in
configuration data, are: determining configurations for non-PnP ISA
IRQ A = ISA Interrupt 5 cards. A more thorough discussion of the Con-
IRQ B = ISA Interrupt 7 figuration Manager and the ISA Configuration
IRQ C = ISA Interrupt 9 Utility can be found in the Product Development
IRQ D = ISA Interrupt 11 Information document of the Plug and Play Kit
IRQ E = ISA Interrupt 12 by Intel Corp. In a PnP BIOS system, the BIOS
IRQ F = ISA Interrupt 15 is responsible for configuring at least all system
board PnP devices. Some systems require addi-
The typical configuration would support two in- tional software to aid the BIOS in configuring
terrupt sources: one shared between the WSS PnP ISA cards. The PnP BIOS can execute all
Codec and the Sound Blaster Pro compatible de- PnP functions independently of the type of oper-
vices, and the other for the MPU401 device. ating system. However, if a PnP aware operating
Interrupts are also supported for the Synthesizer, system is present, the PnP responsibilities are
Control, CDROM devices, but are typically not shared between the BIOS and the operating sys-
used. If the modem logical device (LD5) is used, tem. For more information regarding PnP BIOS,
it would typically support an interrupt. please refer to the latest revision of the Plug and
Play BIOS Specification published by Compaq
PLUG AND PLAY Computer, Phoenix Technologies, and Intel.
The Plug-and-Play (PnP) interface logic is com- The Plug and Play configuration sequence maps
patible with the Intel/Microsoft Plug-and-Play the various functional blocks of the part (logical
specification, version 1.0a, for an ISA-bus de- devices) into the host system address space and
vice. Since the part is an ISA-bus device, it only configures both the DMA and interrupt channels.
supports ISA-compatible IRQs and DMA chan- The host has access to the part via three 8-bit
nels. Plug and Play compatibility allows the PC auto-configuration ports: Address port (0279h),
to automatically configure the part into the sys- Write Data port (0A79h), and relocatable Read
tem upon power up. Plug and Play capability Data port (020Bh - 03FFh). The read data port is
optimally resolves conflicts between Plug and relocated automatically by PnP software when a
Play and non-Plug and Play devices within the conflict occurs.
system. Alternatively, the PnP feature can be by-
passed. See the Bypassing PnP section for more The configuration sequence is as follows:
information. For a detailed Plug-and-Play proto-
col description, please refer to the Plug and Play 1. Host sends a software key which places all
ISA Specification. PnP cards in the sleep state (or Plug-and-
Play mode).
To support Plug-and-Play in ISA systems that do
not have a PnP BIOS or a PnP-aware operating 2. The Crystal part is isolated from the system
system, the Configuration Manager (CM) TSR using an isolation sequence.
and an ISA Configuration Utility (ICU) from In-
tel Corp. are used to provide these functions.

DS215PP4 15
 CS4238B

3. A unique identifier (handle) is assigned to the The CM determines the necessary resource re-
part and the resource data is read. quirements for the system and then programs the
part through the configuration registers. The con-
4. After all cards’ resource requirements are de- figuration register data is written one logical
termined, the host uses the handle to assign device at a time. After all logical devices have
conflict-free resources been configured, CM activates each device indi-
vidually. Each logical device is now available on
5. After the configuration registers have been the ISA bus and responds to the programmed
programmed, each configured logical device address range, DMA channels, and interrupts that
is activated. have been allocated to that logical device.

6. The part is then removed from Plug-and-Play PnP Data

mode. Hardware Configuration and Plug-and-Play re-
source data must be loaded into the part’s RAM.
Upon power-up, the chip is inactive and must be The data may be stored in an external E2PROM
enabled via software. The Crystal part monitors or may be downloaded from the host.
writes to the PnP Auto-Configuration Address
port (0279h). If the host sends a PnP initiation To load the data, refer to the Loading Resource
key, consisting of a series of 32 predefined byte Data section. The following is the Plug-and-Play
writes, the hardware will detect the key and resource data:
place the part into the Plug-and-Play (PnP)
mode. Another method to program the part is to The first nine bytes of the PnP resource data are
use a special Crystal initiation key which func- the Plug-and-Play ID, which uniquely identifies
tions like the PnP initiation key, but can be the Crystal part from other PnP devices. The
invoked by the user at any time. However, the Crystal default is broken down as follows:
Crystal Key only supports one Crystal part per 0Eh, 63h - Crystal ID - ’CSC’ in compressed
system. The Crystal key and special commands ASCII. (See the PnP Spec for more
are detailed in the Crystal Key and Bypassing information)
PnP sections. 42h - Oem ID. A unique Oem ID must be ob-
tained from Crystal for each unique
The isolation sequence uses a unique 72-bit se- Crystal product used.
rial identifier. The host performs 72 pairs of I/O 38h - Crystal product ID for the CS4238B
read accesses to the Read Data port. The identi- FFh, FFh, FFh, FFh - Serial number. This can
fier determines what data is put on the data bus be modified by each OEM to uniquely
in response to those read accesses. When the iso- identify their card.
lation sequence is complete, the CM assigns a ??h - Checksum.
Card Select Number (CSN) to the part. This
number distinguishes the Crystal part from the Of the 9-byte serial number listed above, Crystal
other PnP devices in the system. The Configura- software uses the first two bytes to indicate the
tion Manager (CM) then reads the resource data presence of a Crystal part, and the fourth byte,
from the Crystal part. The 72-bit identifier and 0x38, to indicate the CS4238B; therefore, these
the resource data is either stored in an external three bytes must not be altered.
user-programmable E2PROM, or loaded via a
"hostload" procedure from BIOS before PnP
software is initiated.

16 DS215PP4
 CS4238B

The next 3 bytes are the PnP version number. External E2PROM section for more information
The default is version 1.0a: 0Ah, 10h, 01h. on the serial E2PROM interface and E2PROM
programming.
The next sequence of bytes are the ANSI identi-
fier string. The default is: 82h, 0Eh, 00h, The format for the data stored in the E2PROM is
’Crystal Codec’, 00h. as follows:

The logical device data must be entered using (Hardware Configuration Data:)
the PnP ISA Specification format. Typical logical 2 bytes E2PROM validation: 55h, BBh
device values are found in Table 1. The
E2PROM version for this data is found in Ap- 2 bytes length of resource data in E2PROM
pendix A.
19 bytes Hardware Configuration
Loading Resource Data
(Plug and Play Resource Data:)
A serial E2PROM interface allows user-program- 9 bytes Plug and Play ID
mable serial number and resource data to be
stored in an external E2PROM. The interface is 3 bytes Plug and Play version number
compatible with devices from a number of ven-
dors and the size may vary according to specific Variable number of bytes of user defined
customer requirements. The maximum size for ASCII ID string
resource data supported by the part’s internal
RAM is 384 bytes of combined Hardware Con- Logical Device 0 (Windows Sound System,
figuration and PnP resource data. With the FM Synthesizer, Sound Blaster Pro) data
addition of the 4-byte header, the maximum
amount of E2PROM space used would be 388 Logical Device 1 ( Game Port) data
bytes. However, the part also supports firmware
Logical Device 2 ( Control) data
upgrades via the E2PROM. The maximum size
E2PROM supported is 2k bytes. After power-up, Logical Device 3 ( MPU-401) data
the existence of an E2PROM is checked by read-
ing the first two bytes from the E2PROM Logical Device 4 ( CD-ROM) data
interface. If the data from the E2PROM port
reads 55h and BBh, then the rest of the Logical Device 5 (Modem) data
E2PROM data is loaded into the internal RAM.
If the first two bytes aren’t correct, the E2PROM End of Resource byte & checksum byte
is assumed not to exist and a "hostload" proce-
dure must be used to load the internal RAM. The Firmware patch code.
Hostload procedure can be found in the Hostload
section. For motherboard designs, an E2PROM A typical E2PROM data load, in assembly for-
should still be included, to allow faster integrat- mat, can be found in Appendix A.
ing of resource and firmware patch data. This
allows updates without respiring BIOS code. If Loading Firmware Patch Data
the part is installed on a plug-in card, then an An external E2PROM is read during the power-
external E2PROM is required to ensure that the up sequence that stores Hardware Configuration
proper PnP resource data is loaded into the inter- and PnP data, and firmware patch data. The part
nal RAM prior to a PnP sequence. See the contains RAM and ROM to run the core proces-

DS215PP4 17
 CS4238B

sor. The RAM allows updates to the core proces-

sor functionality. Placing the firmware patches The Crystal Key
in E2PROM, gives the maximum functionality at NOTE: The Crystal Key cannot differentiate be-
power-up without the need for a software driver. tween multiple Crystal Codecs in a system;
therefore, ONLY ONE Crystal part is allowed in
The firmware patch data is typically included at systems using the Crystal Key. To allow multiple
the end of the PnP resource data. Crystal pro- parts in a system, the Plug-and-Play isolation se-
vides a utility that will read in patch data from a quence must be used since it supports multiple
file, and append it to the PnP resource data. The parts via the serial identifier used in the isolation
patch file must be obtained from Crystal. sequence.

Physical Device Logical Device Best Choice Acceptable Sub optimal Sub optimal
Choice 1 Choice 1 Choice 2
WSS 0 ANSI ID = WSS/SB
16-bit address WSSbase 534h-534h 534-608h 534-FFCh
decode Length/Alignment 4/4 4/D4h 4/4
high true IRQ 5 5,7,9,11,12,15 5, 7, 9, 11, 12, 15
edge sensitive (SB share) (SB share) (SB share)
8-bit, count by DMA 1 0, 3 0, 1, 3
byte, type A (SB share) (SB share) (SB share)
same DMA 0, 3 0, 1, 3 ----
Synthesis 0
16-bit address SYNbase 388h 388h 388-3F8h
decode Length/Alignment 4/8 4/8 4/8
IRQ ---- ---- ----
SB Pro 0
16-bit address SBbase 220h 220-260h 220-300h
decode Length/Alignment 16/16 16/32 16/32
Game Port 1 ANSI ID = GAME
16-bit address GAMEbase 200h 208h
decode Length/Alignment 8/8 8/8
Control 2 ANSI ID = CTRL
16-bit address CTRLbase 120-3F8h
decode Length/Alignment 8/8
IRQ ----
MPU401 3 ANSI ID = MPU
16-bit address MPUbase 330h 330-360h 330-3E0h
decode Length/Alignment 2/8 2/8 2/8
IRQ 9 9,11,12,15 ----

---- Feature not supported in the listed configuration, but is supported through customization.

Table 1. Typical Motherboard Plug-and-Play Resource Data

18 DS215PP4
 CS4238B

The Crystal key places the part in the configura- To use the SLAM method, the following se-
tion mode. Once the Crystal key has been quence must be followed:
initiated, new PnP resource data can be down-
loaded by a hostload sequence, or an alternate 1. Host sends 32-byte Crystal key to I/O
method of programming the configuration regis- 0279h, chip enters configuration mode.
ters may be used. This alternate method is
referred to as the "SLAM" method. The SLAM 2. Host programs CSN (Card Select Number)
method allows the user to directly access the by writing a 06h and 00h to I/O 0279h.
configuration registers, configure, and activate
the chip, and then, optionally, disable the PnP 3. Host programs the configuration registers of
and/or Crystal key feature. The SLAM method each logical device by writing to I/O 0279h.
uses commands that are similar to the PnP com- The following data is the maximum amount
mands; however, they are different since the user of information per device. All current devices
has direct access to the configuration registers. only need a subset of this data:
To use the SLAM method, see the Bypassing Logical Device ID (15h, xxh)
PnP section. xxh is logical device number: 0-5

The following 32 bytes, in hex, are the Crystal I/O Port Base Address 0 (47h, xxh, xxh)
key: high byte , low byte
96, 35, 9A, CD, E6, F3, 79, BC,
I/O Port Base Address 1 (48h, xxh, xxh)
5E, AF, 57, 2B, 15, 8A, C5, E2 high byte , low byte
F1, F8, 7C, 3E, 9F, 4F, 27, 13,
I/O Port Base Address 2 (42h, xxh, xxh)
09, 84, 42, A1, D0, 68, 34, 1A high byte , low byte

Bypassing Plug and Play Interrupt Select 0 (22h, xxh)

The SLAM method allows the user to bypass the Interrupt Select 1 (27h, xxh)
Plug and Play features and, as an option, allows
the part to act like a non-Plug and Play or legacy DMA Select 0 (2Ah, xxh)
device; however, the SLAM method only sup-
ports one Crystal IC per system. The user DMA Select 1 (25h, xxh)
directly programs the resources into the part, and
then optionally disables the PnP and/or the Crys- Activate Device (33h, 01h)
tal Key, which forces the part to disregard any (33h, 00h deactivates a device)
future PnP or Crystal initiation key sequences
(All activated logical devices appear as legacy 4. Repeat #3 for each logical device to be en-
devices to PnP). The Crystal and PnP keys can abled. (Not all devices need be enabled.)
also be disabled through the E2PROM.
5. Host activates chip by writing a 79h to 279h.

6. (Optional) Host disables PnP Key by writing

a 55h to CTRLbase+5. The part will not par-
ticipate in any future PnP cycles. The Crystal
Key can also be disabled by writing a 56h to
CTRLbase+5.

DS215PP4 19
 CS4238B

NOTE: To enable the PnP/Crystal Keys after

they have been disabled by the SLAM Hardware Configuration Data
method, bring the RESDRV pin to a logic The Hardware Configuration data contains map-
high or remove power from the device. ping information that links interrupt and DMA
pins with actual interrupt numbers used by PnP
The following illustrates typical data sent using and SLAM procedures. This data also controls
the SLAM method. the XCTL0/XA2 pin functionality. The Hard-
006h, 001h ; CSN=1 ware Configuration data precedes the PnP
Resource data.
015h, 000h ; LOGICAL DEVICE 0
047h, 005h, 034h ; WSSbase = 0x534 The Hardware Configuration data is either 19 or
048h, 003h, 088h ; SYNbase = 0x388 23 bytes long and contains the data necessary to
042h, 002h, 020h ; SBbase = 0x220 configure the part. If an E2PROM is not used
022h, 005h ; WSS & SB IRQ = 5 (Hostload), the first four bytes are not needed,
02Ah, 001h ; WSS & SB DMA0 = 1 which means the configuration data is only 19
025h, 003h ; WSS capture DMA1 = 3 bytes long. The configuration data maps the
033h, 001h ; activate logical device 0 many functions of the logical devices to the
physical pins of the chip. Table 2 lists the Hard-
015h, 001h ; LOGICAL DEVICE 1 ware Configuration bytes. The detailed bit
047h, 002h, 000h ; GAMEbase = 0x200 descriptions for each byte follows below.
033h, 001h ; activate logical device 1
HW Config. Byte 5: ACDbase Address Length
015h, 002h ; LOGICAL DEVICE 2
047h, 001h, 020h ; CTRLbase = 0x120 Mask, Default = 00000000
033h, 001h ; activate logical device 2 D7 D6 D5 D4 D3 D2 D1 D0
res res res res res CM2 CM1 CM0

015h, 003h ; LOGICAL DEVICE 3 CM2-CM0 Address bit masks for the Alternate
047h, 003h, 030h ; MPUbase=0x330 CDROM address decode, ACDbase.
See the CDROM Interface section
022h, 009h ; MPU IRQ = 9 for more details on ACDbase
033h, 001h ; activate logical device 3
000 - ACDCS low for 1 byte
001 - ACDCS low for 2 bytes
079h ; activate Crystal device 011 - ACDCS low for 4 bytes
111 - ACDCS low for 8 bytes
If all the above data is sent, after the Crystal key, xxx - all others, RESERVED
all devices except the CDROM and Modem will
respond to the appropriate resources given.

20 DS215PP4
 CS4238B

BYTE Default Description

2
1 55h E PROM validation byte 1.
The first two bytes tell the Crystal Codec that the E2PROM exists.
2 BBh E2PROM validation byte 2
3 00h High byte for length of resource data in E2PROM
4 DDh Low byte for length of resource data in E2PROM
5 00h Alternate CDROM (Logical Device 4), ACDbase, Address length mask
6 03h Modem (Logical Device 5), COMbase, Address length mask
7 80h Misc. Configuration Bits: Interrupt Pin Polarities, Key Disables, VCEN, & LD4 features
8 00h Global Configuration Bits: IFM, VCF1 and VCF0, WTEN, SPS
9 0Bh Code Base Byte - Must be 0x0B
10* 20h RESERVED - Must be 0x20
11* 04h RESERVED - Must be 0x04
12* 08h RESERVED - Must be 0x08
13* 10h RESERVED - Must be 0x10
14* 80h RESERVED - Must be 0x80
15* 00h RESERVED - Must be 0x00
16* 00h RESERVED - Must be 0x00
17 00h External Peripheral Port I/O Decode Address Length 00 = 4 bytes, 08 = 8 bytes
08h causes XCTL0/XA2 pin to change to peripheral port address bit XA2.
18* 48h RESERVED - Must be 0x48
19 75h IRQ A/B Selection: Lower nibble = A, Upper nibble = B.
Along with next two bytes - specify hardware interrupts tied to IRQA-IRQF pins
20 B9h IRQ C/D Selection: Lower nibble = C, Upper nibble = D.
21 FCh IRQ E/F Selection: Lower nibble = E, Upper nibble = F.
22 10h DMA A/B Selection: Lower nibble = A, Upper nibble = B.
This byte and the next byte - specify hardware DRQ/DACKs tied to the DMAA-DMAC pins
23 03h DMA C Selection: Lower nibble = C, Upper nibble = reserved (must be 0).

NOTE:The first four bytes are exclusive to the E2PROM and are not used in the Hostload mode.
* Currently not supported. Must be set to default values given in the table.

Table 2. Hardware Configuration Data

DS215PP4 21
 CS4238B

HW Config. Byte 6: COMbase Address Length HW Config. Byte 7: Misc. Configuration Bits,
Mask, Default = 00000011 Default = 10000000
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
MM7 MM6 MM5 MM4 MM3 MM2 MM1 MM0 IHCD IHS PKD CKD IHM VCEN SDD ACDB7D

MM7-MM0 Address bit masks for Logical Device ACDB7D Alternate CDROM, data Bit 7 Disable.
5, typically a modem address, When set, SD7 is held in a high
COMbase. See the Modem Interface impedance state when reading from
Section for more details on ACDbase+1 (only this one address).
COMbase. This bit provides support for IDE al-
ternate base address sharing with
00000000 - MCS low for 1 byte the floppy disk controller.
00000001 - MCS low for 2 bytes
00000011 - MCS low for 4 bytes SDD SD Disable. When set, SD<7:0> are
00000111 - MCS low for 8 bytes high impedance on reads from any
00001111 - MCS low for 16 bytes peripheral port address: External syn-
00011111 - MCS low for 32 bytes thesis, CDROM or Modem devices.
00111111 - MCS low for 64 bytes Allows external buffers to bypass the
01111111 - MCS low for 128 bytes part while still allowing PnP address
11111111 - MCS low for 256 bytes support. This bit is also internally
xxxxxxxx - all others, RESERVED forced on whenever WTEN or SPS
in HW Config. byte 8, or C8, is set.
NOTE: The part only buffers the lower three address
bits onto the peripheral port. When setting the ad- VCEN Volume Control Enable. When set,
dress decode greater than 8 bytes, the upper the UP, DOWN, and MUTE pins be-
address bits should be buffered externally. come active and provide a hardware
master volume control.

IHM Interrupt High - Modem (LD5). When

set, MINT is active high. When clear,
MINT is active low.

CKD Crystal Key disable. When set, blocks

the part from receiving the Crystal
key. Note that if both CKD and PKD
are set, software will be unable to re-
configure the part.

PKD PnP Key disable. When set, blocks

the part from receiving the Plug-and-
Play key. Note that if both CKD and
PKD are set, software will be unable
to reconfigure the part.

IHS Interrupt High - Synthesizer. When

set, SINT is active high. When clear,
SINT is active low.

IHCD Interrupt High - CDROM. When set,

CDINT is active high. When clear,
CDINT is active low.

22 DS215PP4
 CS4238B

10 - MUTE is not used. Two button

volume control. Pressing the up
HW Config. Byte 8: Global Configuration Bits, and down buttons simultaneously
Default = 00000000 causes the volume to mute.
D7 D6 D5 D4 D3 D2 D1 D0 Pressing up or down un-mutes.
IFM VCF1 VCF0 SLAD WTEN SPS res res 11 - UP pin is not used. The
MUTE pin functions as the Up
res Must be set to zero to allow compat- function. With this exception, this
ibility with future upgrades. mode functions similarly to the
pervious two-button mode. This
mode provides backwards
SPS DSP Serial Port Switch. When
compatibility with the CS4236.
set, switches the DSP serial port
pins from the second joystick to the
IFM Internal FM. When set, the internal
XD4-XD1 pins. Then, when SPE in
I16 is set, the XD4-XD1 pins convert FM synthesizer is enabled. When
to the DSP serial port pins. Once clear, FM must be provided on the
this bit is enabled, the SD bus will external LINE analog inputs.
not be driven when accesses occur
to peripheral port devices. This func- HW Config. Byte 9: Code Base Byte,
tion is also available in C8.
Default = 00001011
WTEN WaveTable Serial Port Enable. When D7 D6 D5 D4 D3 D2 D1 D0
set, forces XD7-XD5 pins to convert CB7 CB6 CB5 CB4 CB3 CB2 CB1 CB0
to the CS9236 Single-Chip Wave-
table Music Synthesizer serial port CB7-CB0 Code Base Byte. Determines the code
pins. Once this bit is enabled, the base located in the E2PROM. If not
SD bus will not be driven when ac- correct, the Firmware code after the
cesses occur to peripheral port PnP resource data is not loaded.
devices. This function is also avail-
able in C8. 0x0B - CS4238B
0x43 - CS4236
SLAD Soundblaster Alternate Line Disable.
When clear, Sound Blaster (SB)
Synthesizer Volume changes affect The next 7 bytes are reserved for future expan-
the LINE Alternate (X0/X1) volume. sion and must be set to their default values as
When set, SB Synthesizer Volume
listed in Table 2
changes do not affect X0/X1 regis-
ters.
The next byte of hardware configuration data is
VCF1,0 Hardware Volume Control Format. byte 17 in Table 2. This byte determines the
These bits control the format of the function of the XCTL0/XA2 pin. The default of
hardware volume control pins UP, 0, forces the pin to the control function XCTL0,
DOWN, and MUTE. The volume con-
trol is enabled by setting VCEN in and the external peripheral port supports only 4
the previous Hardware Configuration I/O locations through XA0-XA1. If this byte is
byte. set to 08h, the pin switches to the XA2 function
and the peripheral port supports 8 I/O locations
00 - MUTE is a toggle switch. When through XA2-XA0.
MUTE is low, the volume is muted.
01 - MUTE is a momentary switch.
MUTE toggles between mute and The next byte, listed as byte 18, is reserved for
un-mute. Pressing the up or down future expansion and must be set to 0x48.
switch always un-mutes.

DS215PP4 23
 CS4238B

Bytes 19 through 21 map the interrupt number to 2. Write 57h (Jump to ROM) command to
the actual interrupt pins A - F. As shown in the CTRLbase+5.
table, the byte 20 default is 0xB9; therefore,
IRQC, which is the lower nibble, maps to the 3. Download the PnP resource data.
ISA interrupt 9. Likewise IRQD, which is the
upper nibble, maps to the ISA interrupt 11 a. Send download command by writing AAh
(0Bh). to CTRLbase+5.

Bytes 22 and 23 map the DMA channel number b. Send starting download address (4000h)
to the actual DMA pins A-C. As shown in the by writing low byte (00h) first, and then
table, the byte 22 default is 0x10; therefore, high byte (40h) to CTRLbase+5.
DRQA/DACKA is the lower nibble which maps
to the ISA DMA channel 0. Likewise c. Send the Hardware Configuration and re-
DRQB/DACKB is the upper nibble which maps source data in successive bytes to
to the ISA DMA channel 1. CTRLbase+5. This includes the Hardware
Configuration and the PnP resource data.
Hostload Procedure The PnP resource format is described in
the PnP Data section. The resource header
This procedure is provided for backwards com- should not contain the first four bytes
patibility with the CS4236. Since the E2PROM which are only used for E2PROM loads.
allows all resource and firmware patch data to be
loaded at power-up, this procedure is typically 4. End download by writing 00h to
not used. To download PnP resource data from CTRLbase+6.
the host to the part’s internal RAM, use the fol-
lowing sequence: 5. If any of the Hardware Configuration Data
(first 19 bytes) has changed, 5Ah must be
1. Configure Control I/O base address, written to CTRLbase+5 to force the part to
CTRLbase, by one of two methods: regular internally update this information.
PnP cycle or Crystal Key method.

a. The host can use the regular PnP cycle to The new PnP data is loaded and the part is ready
program the CTRLbase, and then place the for the next PnP cycle.
chip in the wait_for_key_state
External E2PROM
b. If the Crystal Key method is used:
The Plug and Play specification defines 32 bits
First, send the 32-byte Crystal key to I/O of the 72-bit Serial Identifier as being a user de-
address 0279h. (The Crystal Key only fined serial number. The E2PROM is used to
supports one Crystal part per system.) change the user section of the identifier, store
default resource data for PnP, Hardware Con-
Second, configure logical device 2 base figuration data specific to the Crystal part, and
address, CTRLbase, by writing to I/O firmware patches to upgrade the core processor
0279h (15h, 02h, 47h, xxh, xxh, 33h, functionality.
01h, 79h).
Note: The two xxh represent the base_ad-
dress_high and base_address_low
respectively. The default is: 01h, 20h.

24 DS215PP4
 CS4238B

The E2PROM interface uses an industry standard The maximum Hardware Configuration and PnP
2-wire interface consisting of a bi-directional resource RAM data supported is 384 bytes, and
data line and a clock line driven from the part. a four byte header; therefore, the maximum
After power-on the part looks for the existence amount of data storage, without firmware
of an E2PROM device and loads the user de- patches, in E2PROM would be 388 bytes. The
fined data. The existence is determined by the maximum size E2PROM supported is 2k bytes.
first two bytes read (0x55 followed by 0xBB). If This allows the inclusion of firmware patches af-
the first two bytes are correct, the part reads the ter the PnP resource data.
next two bytes to determine the length of data in
the E2PROM. The length bytes indicate the If an external E2PROM exists, it is accessed by
number of bytes left to be read (not including the serial interface and is connected to the XD0
the two validation bytes or two length bytes). As and XA0 pins. The two-wire interface is control-
shown in Figure 3, the E2PROM is read using a led by three bits in the Control logical device,
start bit followed by a dummy write, to initialize Hardware Control Register (CTRLbase+1). The
the address to zero. Then another start bit and serial data can be written to or read from the
device address, followed by all the data. Since E2PROM by sequentially writing or reading that
the part uses the sequential read properties of the register. The three register bits, D0, D1, D2 are
E2PROM, only one E2PROM, is supported labeled CLK, DOUT, and DIN/EEN respectively.
(ganged E2PROMs are not supported). The DIN/EEN bit, when written to a one, en-
ables the E2PROM serial interface. When the
Some E2PROMs that are compatible with this DIN/EEN bit is written to a zero, the serial inter-
interface are: face is disabled. The DIN/EEN bit is also the
Atmel AT24Cxx series Data In (DIN) signal to read back data from the
MicroChip 24LCxxB series E2PROM. The XD0 pin is a bi-directional open-
National NM24CxxL series drain data line supporting DIN and DOUT;
Ramtron FM24Cxx series therefore, to read the correct data, the DOUT bit
SGS Thompson ST24Cxx series must be set to a one prior to performing a read
Xicor X24Cxx series of the register. Otherwise, the data read back
where the xx is replaced by 02, 04, 08, or 16 from DIN/EEN will be all zeros. The E2PROM
based on the size of the E2PROM desired. The data can then be read from the DIN/EEN bit.
size of 16 (2k bytes) is preferred since it allows The CLK bit timing is controlled by the host
the maximum flexibility for upgrading firmware software. This is the serial clock for the
patches. Other E2PROMs compatible with Fig- E2PROM. The DOUT bit is used to write/pro-
ure 3 and the timing parameters listed in the gram the data out to the E2PROM. An external
front of the data sheet may also be used. pull-up resistor is required on XD0 because it is
an open-drain output. Use the guidelines in the

Part Bank No
Part Read
Crystal IC Start Address Write Address Start Acknowledge Acknowledge
Address Stop
S 1 0 1 0 0 0 0 0 A 0 0 0 0 0 0 0 0 AS 1 0 1 0 0 0 0 1 A Data A Data 1P

EEPROM Acknowledge Data

Figure 3. EEPROM Format

DS215PP4 25
 CS4238B

specific E2PROM data sheet to select the value WINDOWS SOUND SYSTEM CODEC
of the pull-up resistor (a typical value would be The WSS Codec software interface consists of 4
3.3kΩ). I/O locations starting at the Plug and Play ad-
dress ’WSSbase’, and supports 12-bit address
Programming the E2PROM: decoding. If the upper address bits, SA12-SA15
1. Configure Control I/O base address by one are used, they must be 0 to decode a valid ad-
of two methods: regular PnP cycle or Crystal dress. The WSS Codec also requires one
Key method. interrupt and one or preferably two DMA chan-
nels, one for playback and one for capture. Since
a. The host can use the regular PnP cycle to the WSS Codec and Sound Blaster device are
program the logical device 2 I/O base ad- mutually exclusive, the two devices share the
dress, and then place the chip in the same interrupt and DMA playback channel.
wait_for_key_state
The WSS Codec/Mixer is register compatible
b. If the Crystal Key method is used: with the Microsoft Windows Sound System.
Functions include stereo Analog-to-Digital and
First, write to I/O 0279h, send the 32- Digital-to-Analog converters (ADCs and DACs),
byte Crystal key. (The Crystal Key only analog mixing, anti-aliasing and reconstruction
supports one Crystal part per system.) filters, line and microphone level inputs, optional
A-Law/µ-Law coding, simultaneous capture and
Second, configure the Control I/O base
playback (at independent sample frequencies)
address by writing 15h, 02h, 47h, 01h,
and a parallel bus interface. Five analog inputs
20h, 33h, 01h, 79h to 0279h.
are provided and four can be mixed to the ADC
mixer. All five can be mixed with the output of
2. Refer to the specific data sheet for the
the DAC with full volume control. Several data
E2PROM you are using for timing require-
modes are supported including 8- and 16-bit lin-
ments and data format. Also, refer to the
ear as well as 8-bit companded, 4-bit ADPCM
Loading Resource Data section of this data
compressed, and 16-bit big Endian.
sheet for the E2PROM resource data format.
Enhanced Functions (MODEs)
3. Send the E2PROM data in successive bits to
CTRLbase+1 (Hardware Control Register) The initial state is labeled MODE 1 and forces
while following the E2PROM data sheet for- the part to appear as a CS4248. The more popu-
mat. lar second mode, MODE 2, forces the part to
appear as a CS4231 super set and is compatible
The E2PROM now contains the PnP resource with the CS4232. To switch from MODE 1 to
data. For this new data to take effect, the part MODE 2, the CMS1,0 bits, in the MODE and
must be reset, causing the part to read the ID register (I12), should be set to 10 respec-
E2PROM during initialization. Crystal can pro- tively. When MODE 2 is selected, the bit IA4 in
vide a utility, RESOURCE.EXE, to program the Index Address register (R0) will be decoded
E2PROMs through the Control logical device in- as a valid index pointer providing 16 additional
terface. registers and increased functionality over the
CS4248.

To reverse the procedure, set the CMS1,0 bits to

00 and the part will resume operation in

26 DS215PP4
 CS4238B

MODE 1. Except for the Capture Data Format and then makes requests as positions inside the
(I28), Capture Base Count (I30/31), and Alter- FIFO are emptied, thereby keeping the playback
nate Feature Status (I24) registers, all other FIFO as full as possible. Thus when the system
Mode 2 functions retain their values when re- cannot respond within a sample period, the FIFO
tur ning to Mode 1. The WS S Codec is starts to empty, avoiding a momentary loss of
backwards compatible with the CS4236, audio data. If the FIFO runs out of data, the last
CS4232, CS4231 and CS4248. valid sample can be continuously output to the
DACs (if DACZ in I16 is set) which will elimi-
The additional MODE 2 functions are: full-du- nate pops from occurring.
plex support, a programmable timer, Mono In
and Mono Out support. When capture is enabled, the capture FIFO tries
to continually stay empty by making requests
MODE 3 is selected by setting CMS1,0 to 11. every sample period. Thus when the system can-
MODE 3 allows access to new bits in the indi- not respond within a sample period, the capture
rect registers I0-I31, and allows access to a third FIFO starts filling, thereby avoiding a loss of
set of "extended registers" which are designated data in the audio data stream.
X0-X17+X25. The extended registers are ac-
cessed through I23. The additional MODE 3 WSS Codec PIO Register Interface
functions are: Four I/O mapped locations are available for ac-
cessing the Codec functions and mixer. The
1. A full symmetrical mixer. This changes the in- control registers allow access to status, audio
put multiplexer to a input mixer. data, and all indirect registers via the index reg-
isters. The IOR and IOW signals are used to
2. Independent sample frequency control on the define the read and write cycles respectively. A
ADCs and DACs. PIO access to the Codec begins when the host
puts an address on to the ISA bus which matches
3. Programmable Gain and Attenuation on the WSSbase and drives AEN low. WSSbase is pro-
Microphone inputs. grammed during a Plug and Play configuration
sequence. Once a valid base address has been
4. Independent control over the volume of inter- decoded then the assertion of IOR will cause the
nal FM synthesis and external wavetable. WSS Codec to drive data on the ISA data bus
lines. Write cycles require the host to assert data
5. Volume control on the DSP serial port input on the ISA data bus lines and strobe the IOW
data. signal. The WSS Codec will latch data into the
PIO register on the rising edge of the IOW
6. Stereo volume on the monitor feedback path. strobe.
FIFOs The audio data interface typically uses DMA re-
The WSS Codec contains 16-sample FIFOs in quest/grant pins to transfer the digital audio data
both the playback and capture digital audio data between the WSS Codec and the bus. The WSS
paths. The FIFOs are transparent and have no Codec is responsible for asserting a request signal
programming associated with them. whenever the Codec’s internal buffers need updat-
ing. The bus responds with an acknowledge
When playback is enabled, the playback FIFO signal and strobes data to and from the Codec, 8
continually requests data until the FIFO is full, bits at a time. The WSS Codec keeps the request

DS215PP4 27
 CS4238B

pin active until the appropriate number of 8-bit data, and the capture DMA requests will be
cycles have occurred to transfer one audio sam- routed to the DMA pair specified by the DMA
ple. Note that different audio data types will Channel Select 1 resource data.
require a different number of 8-bit transfers.
DUAL DMA CHANNEL MODE
DMA Interface The WSS Codec supports a single and a dual
The second type of parallel bus cycle from the DMA channel mode. In dual DMA channel
WSS Codec is a DMA transfer. DMA cycles are mode, playback and capture DMA requests and
distinguished from PIO register cycles by the as- acknowledges occur on independent DMA chan-
sertion of a DRQ followed by an nels. In dual DMA mode, SDC should be set to
acknowledgment by the host by the assertion of 0. The Playback- and Capture-Enables (PEN,
DACK (with AEN high). While the acknow- CEN, I9) can be changed without a Mode
ledgment is received from the host, the WSS Change Enable (MCE, R0). This allows for
Codec assumes that any cycles occurring are proper full duplex control where applications are
DMA cycles and ignores the addresses on the independently using playback and capture.
address lines.
SINGLE DMA CHANNEL (SDC) MODE
The WSS Codec may assert the DMA request When two DMA channels are not available, the
signal at any time. Once asserted, the DMA re- SDC mode forces all DMA transfers (capture or
quest will remain asserted until a complete DMA playback) to occur on a single DMA channel
cycle occurs to the part. DMA transfers may be (playback channel). The trade-off is that the
terminated by resetting the PEN and/or CEN bits WSS Codec will no longer be able to perform
in the Interface Configuration register (I9), de- simultaneous DMA capture and playback.
pending on the DMA that is in progress
(playback, capture, or both). Termination of To enable the SDC mode, set the SDC bit in the
DMA transfers may only happen between sample Interface Configuration register (I9). With the
transfers on the bus. If DRQ goes active while SDC bit asserted, the internal workings of the
resetting PEN and/or CEN, the request must be WSS Codec remain exactly the same as dual
acknowledged with DACK and a final sample mode, except for the manner in which DMA re-
transfer completed. quest and acknowledges are handled.
DMA CHANNEL MAPPING The playback of audio data will occur on the
Mapping of the WSS Codec’s DRQ and DACK playback channel exactly as dual channel opera-
onto the ISA bus is accomplished by the Plug tion; however, the capture audio channel is now
and Play configuration registers. If the Plug and diverted to the playback channel. Alternatively
Play resource data specifies only one DMA stated, the capture DMA request occurs on DMA
channel for the Codec (or the codec is placed in channel select 0 for the WSS Codec. (In
SDC mode) then both the playback and capture MODEs 2 and 3, the capture data format is al-
DMA requests should be routed to the same ways set in register I28.) If both playback and
DRQ/DACK pair (DMA Channel Select 0). If capture are enabled, the default will be playback.
the Plug and Play resource data specifies two SDC does not have any affect when using PIO
DMA channels for the Codec, then the playback accesses.
DMA request will be routed to the DMA pair
specified by the DMA Channel Select 0 resource

28 DS215PP4
 CS4238B

Sound System Codec Register Interface

Direct Registers: (R0-R3)
The Windows Sound System codec is mapped
via four locations. The I/O base address, Address Reg. Register Name
WSSbase, is determined by the Plug and Play WSSbase+0 R0 Index Address register
configuration. The WSSbase supports four direct WSSbase+1 R1 Indexed Data register
registers, shown in Table 3. The first two direct WSSbase+2 R2 Status register
registers are used to access 32 indirect registers
WSSbase+3 R3 PIO Data register
shown in Table 4. The Index Address register
(WSSbase+0) points to the indirect register that Table 3. WSS Codec Direct Register
is accessed through the Indexed Data register
(WSSbase+1). Index Register Name
I0 Left ADC Input Control
This section describes all the direct and indirect I1 Right ADC Input Control
registers for the WSS Codec. Table 5 details a I2 Left Aux #1 Volume
summary of each bit in each register with Ta- I3 Right Aux #1Volume
bles 6 through 15 illustrating the majority of I4 Left Aux #2 Volume
decoding needed when programming the WSS I5 Right Aux #2 Volume
logical device, and are included for reference. I6 Left DAC (PC Wave) Volume
When enabled, the WSS Codec default state is I7 Right DAC (PC Wave) Volume
defined as MODE 1. MODE 1 is backwards I8 Fs & Playback Data Format
compatible with the CS4248 and only allows ac- I9 Interface Configuration
cess to the first 16 indirect registers. Putting the I10 Pin Control
part in MODE 2 or MODE 3, using CMS1,0 bits I11 Error Status and Initialization
in the MODE and ID register (I12), allows ac- I12 MODE and ID
cess to indirect registers 16 through 31. Putting I13 Monitor Loopback Volume
the part in MODE 3 also allows access to the I14 Playback Upper Base Count
extended registers through I23 and other ex- I15 Playback Lower Base Count
tended features in the indirect registers. I16 Alternate Feature Enable I
I17 Alternate Feature Enable II
I18 Left Line (Synthesizer) Volume
DIRECT MAPPED REGISTERS
I19 Right Line (Synthesizer) Volume
The first two WSS Codec registers provide indi- I20 Timer Low Byte
rect accessing to more codec registers via an I21 Timer High Byte
index register. The other two registers provide I22 Alternate Sample Frequency
status information and allow audio data to be I23 Extended Register Access (X regs)
transferred to and from the WSS Codec without I24 Alternate Feature Status
using DMA cycles or indexing. I25 Compatibility ID
I26 Mono Input & Output Control
Note that register defaults are listed in binary I27 Reserved
form with reserved bits marked with ’x’ to indi- I28 Capture Data Format
cate unknown. To maintain compatibility with I29 Reserved
future parts, these reserved bits must be written I30 Capture Upper Base Count
as 0, and must be masked off when the register I31 Capture Lower Base Count
is read. The current value read for reserved bits
is not guaranteed on future revisions.
Table 4. WSS Codec Indirect Registers

DS215PP4 29
 CS4238B

Direct Registers: WSSbase (R0-R3)

ADDRESS D7 D6 D5 D4 D3 D2 D1 D0
WSSbase+0 R0 INIT MCE TRD IA4 IA3 IA2 IA1 IA0
WSSbase+1 R1 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
WSSbase+2 R2 CU/L CL/R CRDY SER PU/L PL/R PRDY INT
WSSbase+3 R3 CD7/PD7 CD6/PD6 CD5/PD5 CD4/PD4 CD3/PD3 CD2/PD2 CD1/PD1 CD0/PD0

Indirect Registers: (I0-I31)

IA4-IA0 D7 D6 D5 D4 D3 D2 D1 D0
0 LSS1 LSS0 LMGE - LAG3 LAG2 LAG1 LAG0
1 RSS1 RSS0 RMGE - RAG3 RAG2 RAG1 RAG0
2 LX1OM LX1IM LX1BM LX1G4 LX1G3 LX1G2 LX1G1 LX1G0
3 RX1OM RX1IM RX1BM RX1G4 RX1G3 RX1G2 RX1G1 RX1G0
4 LX2OM LX2IM - LX2G4 LX2G3 LX2G2 LX2G1 LX2G0
5 RX2OM RX2IM - RX2G4 RX2G3 RX2G2 RX2G1 RX2G0
6 LDM LDG6 LDG5 LDG4 LDG3 LDG2 LDG1 LDG0
LPM res LPA5 LPA4 LPA3 LPA2 LPA1 LPA0
7 RDM RDG6 RDG5 RDG4 RDG3 RDG2 RDG1 RDG0
RPM res RPA5 RPA4 RPA3 RPA2 RPA1 RPA0
8§ FMT1 FMT0 C/L S/M CFS2 CFS1 CFS0 C2SL
9§ CPIO PPIO - CAL1 CAL0 SDC CEN PEN
10 XCTL1 XCTL0 OSM1 OSM0 DEN DTM IEN -
11 COR PUR ACI DRS ORR1 ORR0 ORL1 ORL0
12 1 CMS1 CMD0 - ID3 ID2 ID1 ID0
13 LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 - LBE
14 PUB7 PUB6 PUB5 PUB4 PUB3 PUB2 PUB1 PUB0
15 PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB0
16 OLB TE CMCE PMCE SF1 SF0 SPE DACZ
17 TEST TEST TEST TEST APAR - XTALE HPF
18 LLOM LLIM LLBM LLG4 LLG3 LLG2 LLG1 LLG0
LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0
19 RLOM RLIM RLBM RLG4 RLG3 RLG2 RLG1 RLG0
RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0
20 TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0
21 TU7 TU6 TU5 TU4 TU3 TU2 TU1 TU0
22 SRE DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 CS2
23 XA3 XA2 XA1 XA0 XRAE XA4 - ACF
24 - TI CI PI CU CO PO PU
25 0 0 0 0 0 0 1 1
26 MIM MOM MBY - MIA3 MIA2 MIA1 MIA0
27 - - - - - - - -
28 FMT1 FMT0 C/L S/M - - - -
29 - - - - - - - -
30 CUB7 CUB6 CUB5 CUB4 CUB3 CUB2 CUB1 CUB0
31 CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1 CLB0

Table 5. WSS Codec Direct & Indirect Register Bits

30 DS215PP4
 CS4238B

bit5 bit4 bit3 bit2 bit1 bit0 WG5-0 (X16,17) LBA5-0, PA5-0, SPA5-0, FMA5-0
0 0 0 0 0 0 0 12.0 dB 0.0 dB
1 0 0 0 0 0 1 10.5 dB -1.5 dB
2 0 0 0 0 1 0 9.0 dB -3.0 dB
3 0 0 0 0 1 1 7.5 dB -4.5 dB
. . . . . . . - .
8 0 0 1 0 0 0 0 dB -12.0 dB
. . . . . . . - .
. . . . . . . - .
60 1 1 1 1 0 0 -78.0 dB -90.0 dB
61 1 1 1 1 0 1 -79.5 dB -91.5 dB
62 1 1 1 1 1 0 -81.0 dB -93.0 dB
63 1 1 1 1 1 1 -82.5 dB -94.5 dB

Table 6. Wavetable, Loopback, PC Wave, DSP Serial, & FM

bit3 bit2 bit1 bit0 Input Gain Mono In

(I0,I1) (I26) G4 G3 G2 G1 G0 Level
0 0 0 0 0 0.0 dB 0.0 dB 0 0 0 0 0 0 12.0 dB
1 0 0 0 1 1.5 dB -3.0 dB 1 0 0 0 0 1 10.5 dB
2 0 0 1 0 3.0 dB -6.0 dB 2 0 0 0 1 0 9.0 dB
3 0 0 1 1 4.5 dB -9.0 dB 3 0 0 0 1 1 7.5 dB
. . . . . - . 4 0 0 1 0 0 6.0 dB
. . . . . - . 5 0 0 1 0 1 4.5 dB
. . . . . - . 6 0 0 1 1 0 3.0 dB
12 1 1 0 0 18.0 dB -36.0 dB 7 0 0 1 1 1 1.5 dB
13 1 1 0 1 19.5 dB -39.0 dB 8 0 1 0 0 0 0.0 dB
14 1 1 1 0 21.0 dB -42.0 dB 9 0 1 0 0 1 -1.5 dB
15 1 1 1 1 22.5 dB -45.0 dB 10 0 1 0 1 0 -3.0 dB
11 0 1 0 1 1 -4.5 dB
Table 7. Input ADC Gain and Mono In Levels 12 0 1 1 0 0 -6.0 dB
. . . . . . .
. . . . . . .
. . . . . . .
24 1 1 0 0 0 -24.0 dB
25 1 1 0 0 1 -25.5 dB
LIS1 LIS0 LEVEL 26 1 1 0 1 0 -27.0 dB
RIS1 RIS0 27 1 1 0 1 1 -28.5 dB
0 0 0 dB 28 1 1 1 0 0 -30.0 dB
0 1 -6 dB 29 1 1 1 0 1 -31.5 dB
1 0 30 1 1 1 1 0 -33.0 dB
-12 dB
1 1 -18 dB Table 10. AUX1, AUX2, LINE
Table 8. Input Mixer Attenuation

CFS
2 1 0 C2SL = 0 C2SL=1 FMT1 FMT0 C/L Data Format
0 0 0 8.0 kHz 5.51 kHz 0 0 0 Linear, 8-bit unsigned
0 0 1 16.0 kHz 11.025 kHz 0 0 1 µ-Law, 8-bit companded
0 1 0 27.42 kHz 18.9 kHz 0 1 0 Linear, 16-bit two’s
0 1 1 32.0 kHz 22.05 kHz complement, Little Endian
1 0 0 N/A 37.8 kHz 0 1 1 A-Law, 8-bit companded
1 0 1 N/A 44.1 kHz 1 0 1 ADPCM, 4-bit, IMA compatible
1 1 0 48.0 kHz 33.075 kHz 1 1 0 Linear, 16-bit two’s
1 1 1 9.6 kHz 6.62 kHz complement, Big Endian
Table 9. Sample Frequencies Table 11. WSS Codec Data Format

DS215PP4 31
 CS4238B

Decimal Hex Digital Analog LEVEL Decimal Sample Rate Divider

Value Value Atten. Atten. Value
64 40 0 dB 12.0 dB 12.0 dB 0 50.40 KHz 16 X 21
65 41 0 dB 10.5 dB 10.5 dB 1 48.00 KHz 353
66 42 0 dB 9.0 dB 9.0 dB 2 32.00 KHz 529
67 43 0 dB 7.5 dB 7.5 dB 3 27.42 KHz 617
68 44 0 dB 6.0 dB 6.0 dB 4 16.00 KHz 1058
69 45 0 dB 4.5 dB 4.5 dB 5 9.600 KHz 1764
70 46 0 dB 3.0 dB 3.0 dB 6 8.000 KHz 2117
71 47 0 dB 1.5 dB 1.5 dB 7 6.620 KHz 2558
72 48 res res res 8 50.40 KHz 16 X 21
- - - - - - - -
127 7F res res res 21 50.40 KHz 16 X 21
0 0 0 dB 0.0 dB 0.0 dB 22 48.10 KHz 16 X 22
1 1 0 dB -1.5 dB -1.5 dB 23 46.01 KHz 16 X 23
2 2 0 dB -3.0 dB -3.0 dB 24 44.10 KHz 16 X 24
3 3 0 dB -4.5 dB -4.5 dB 25 42.36 KHz 16 X 25
4 4 0 dB -6.0 dB -6.0 dB 26 40.70KHz 16 X 26
5 5 0 dB -7.5 dB -7.5 dB - - -
6 6 0 dB -9.0 dB -9.0 dB 189 5600 KHz 16 X 189
- - - - - 190 5570.5 KHz 16 X 190
23 17 0 dB -34.5 dB -34.5 dB 191 5541.4 KHz 16 X 191
24 18 -6 dB -30.0 dB -36.0 dB 192 5512.5 KHz 16 X 192
25 19 -6 dB -31.5 dB -37.5 dB - - -
26 1A -6 dB -33.0 dB -39.0 dB 255 5512.5 KHz 16 X 192
27 1B -6 dB -34.5 dB -40.5 dB Table 14. A/D Sample Rate (SRAD7-SRAD0)
28 1C -12 dB -30.0 dB -42.0 dB
29 1D -12 dB -31.5 dB -43.5 dB
30 1E -12 dB -33.0 dB -45.0 dB
31 1F -12 dB -34.5 dB -46.5 dB
32 20 -18dB -30.0 dB -48.0 dB Decimal Sample Rate Divider
- - - - - Value
62 3E -60 dB -33.0 dB -93.0 dB 0 50.40 KHz 16 X 21
1 48.00 KHz 353
Table 12. Master Digital Gain 2 32.00 KHz 529
3 27.42 KHz 617
4 16.00 KHz 1058
5 9.600 KHz 1764
MG4 MG3 MG2 MG1 MG0 LEVEL
6 8.000 KHz 2117
0 0 0 0 0 0 22.5 dB
7 6.620 KHz 2558
1 0 0 0 0 1 21.0 dB
8 50.40 KHz 16 X 21
2 0 0 0 1 0 19.5 dB
- - -
3 0 0 0 1 1 18.0 dB
21 50.40 KHz 16 X 21
- - - - - - -
22 48.10 KHz 16 X 22
11 0 1 0 1 1 6.0 dB
23 46.01 KHz 16 X 23
12 0 1 1 0 0 4.5 dB
24 44.10 KHz 16 X 24
13 0 1 1 0 1 3.0 dB
25 42.36 KHz 16 X 25
14 0 1 1 1 0 1.5 dB
26 40.70 KHz 16 X 26
15 0 1 1 1 1 0 dB
27 39.20 KHz 16 X 27
- - - - - - -
28 37.80 KHz 16 X 28
28 1 1 1 0 0 -19.5 dB
- - -
29 1 1 1 0 1 -21.0 dB
255 4.150 KHz 16 X 255
30 1 1 1 1 0 -22.5 dB
31 1 1 1 1 1 -24.0 dB Table 15. D/A Sample Rate (SRDA7-SRDA0)

Table 13. Microphone Gain

32 DS215PP4
 CS4238B

During initialization and software power down

Index Address Register (PM1,0 = 01), this register CANNOT be written
and always reads 10000000 (80h)
(WSSbase+0, R0)
D7 D6 D5 D4 D3 D2 D1 D0
INIT MCE TRD IA4 IA3 IA2 IA1 IA0 Indexed Data Register
(WSSbase+1, R1)
IA3-IA0 Index Address: These bits define the D7 D6 D5 D4 D3 D2 D1 D0
address of the indirect register ac- ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
cessed by the Indexed Data register
(R1). These bits are read/write.
ID7-ID0 Indexed Data register: These bits are
IA4 Allows access to indirect registers 16 the indirect register referenced by
- 31. In MODE 1, this bit is re- the Indexed Address register (R0).
served and must be written as zero.
During initialization and software power down
TRD Transfer Request Disable: This bit, of the WSS Codec, this register can NOT be
when set, causes DMA transfers to written and is always read 10000000 (80h)
cease when the INT bit of the Status
Register (R2) is set. Independent for
playback and capture interrupts. Status Register
(WSSbase+2, R2, Read Only)
0 - Transfers Enabled (playback and D7 D6 D5 D4 D3 D2 D1 D0
capture DRQs occur uninhibited) CU/L CL/R CRDY SER PU/L PL/R PRDY INT
1 - Transfers Disabled (playback and
capture DRQ only occur if INT bit
INT Interrupt Status: This indicates the
is 0)
status of the internal interrupt logic
of the WSS Codec. This bit is
MCE Mode Change Enable: This bit must cleared by any write of any value to
be set whenever the current mode
this register. The IEN bit of the Pin
of the WSS Codec is changed. The Control register (I10) determines
Data Format (I8, I28) and Interface whether the state of this bit is re-
Configuration (I9) registers CANNOT flected on the IRQ pin assigned to
be changed unless this bit is set. the WSS Codec.
The exceptions are CEN and PEN
which can be changed "on-the-fly". Read States
The DAC output is muted when
MCE is set.
0 - Interrupt inactive
1 - Interrupt active
INIT WSS Codec Initialization: This bit is
read as 1 when the Codec is in a
PRDY Playback Data Ready. The Playback
state in which it cannot respond to
Data register (R3) is ready for more
parallel interface cycles. This bit is
data. This bit would be used when di-
read-only.
rect programmed I/O data transfers
are desired.
Immediately after RESET (and once the WSS
Codec has left the INIT state), the state of this 0 - Data still valid. Do not overwrite.
register is: 010x0000 (binary - where ’x’ indi- 1 - Data stale. Ready for next host
cates unknown). data write value.

DS215PP4 33
 CS4238B

PL/R Playback Left/Right Sample: This bit CL/R Capture Left/Right Sample: This bit
indicates whether data needed is for indicates whether the capture data
the Left channel or Right channel in waiting is for the Left channel or
all data formats except ADPCM. In Right channel in all audio data for-
ADPCM it indicates whether the first mats except ADPCM. In ADPCM it
two or last two bytes of a 4-byte set indicates whether the first two or last
(8 ADPCM samples) are needed. two bytes of a 4-byte set (8 ADPCM
samples) are waiting.
0 - Right or 3/4 ADPCM byte needed
1 - Left, Mono, or 1/2 ADPCM byte 0 - Right or 3/4 ADPCM byte available
needed 1 - Left, Mono, or 1/2 ADPCM byte
available
PU/L Playback Upper/Lower Byte: This bit
indicates whether the playback data CU/L Capture Upper/Lower Byte: This bit
needed is for the upper or lower indicates whether the capture data
byte of the channel. In ADPCM it in- ready is for the upper or lower byte
dicates, along with PL/R, which one of the channel. In ADPCM it indi-
of the four ADPCM bytes is needed. cates, along with CL/R, which one of
four ADPCM bytes is available.
0 - Lower or 1/3 ADPCM byte needed
1 - Upper, any 8-bit format, or 2/4 0 - Lower or 1/3 ADPCM byte
ADPCM byte needed. available
1 - Upper, any 8-bit format, or 2/4
SER Sample Error: This bit indicates that a ADPCM byte available
sample was not serviced in time and
an error has occurred. The bit indi-
cates an overrun for capture and Note on PRDY/CRDY: These two bits are de-
underrun for playback. If both the signed to be read as one when action is required
capture and playback are enabled,
by the host. For example, when PRDY is set to
the source which set this bit can not
be determined. However, the Alter- one, the device is ready for more data; or when
nate Feature Status register (I24) the CRDY is set to one, data is available to the
can indicate the exact source of the host. The definition of the CRDY and PRDY bits
error. are therefore consistent in this regard.
CRDY Capture Data Ready. The Capture
Data register (R3) contains data I/O DATA REGISTERS
ready for reading by the host. This The PIO Data register is two registers mapped to
bit would be used for direct pro- the same address. Writes to this register sends
grammed I/O data transfers.
data to the Playback Data register. Reads from
0 - Data is stale. Do not reread the this register will receive data from the Capture
information. Data register.
1 - Data is fresh. Ready for next
host data read. During initialization and software power down
of the WSS Codec, this register CANNOT be
written and is always read 10000000 (80h)

34 DS215PP4
 CS4238B

Capture I/O Data Register INDIRECT MAPPED REGISTERS

(WSSbase+3, R3, Read Only) These registers are accessed by placing the ap-
D7 D6 D5 D4 D3 D2 D1 D0 propriate index in the Index Address register
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0 (R0) and then accessing the Indexed Data regis-
ter (R1). A detailed description of each indirect
CD7-CD0 Capture Data Port. This is the control register is given below. All reserved bits should
register where capture data is read be written zero and may be 0 or 1 when read.
during programmed I/O data trans-
fers. Note that indirect registers 16-31 are not avail-
able when in MODE 1 (CMS1,0 in MODE and
The reading of this register will increment the ID register I12 are both zero).
state machine so that the following read will be
from the next appropriate byte in the sample. Left ADC Input Control (I0)
The exact byte which is next to be read can be Default = 000x0000
determined by reading the Status register (R2). D7 D6 D5 D4 D3 D2 D1 D0
Once all relevant bytes have been read, the state LSS1 LSS0 LMGE res LAG3 LAG2 LAG1 LAG0
machine will point to the last byte of the sample
until a new sample is received from the ADCs. LAG3-LAG0 Left ADC Gain. The least significant
Once the Status register (R2) is read and a new bit represents +1.5 dB, with
sample is received from the FIFO, the state ma- 0000 = 0 dB. See Table 7.
chine and Status register (R2) will point to the res Reserved. Must write 0. Could read
first byte of the new sample. as 0 or 1.

During initialization and software power down LMGE This bit has no function in MODE 3.
of the WSS Codec, this register can NOT be In MODEs 1 & 2 it controls the
20 dB gain boost for the left MIC in-
written and is always read 10000000 (80h) put to the ADC.

Playback I/O Data Register LSS1-LSS0 Left output loopback. In MODE 3,

setting these bits to 11 enables the
WSSbase+3, R3, Write Only) left output loopback into the input
D7 D6 D5 D4 D3 D2 D1 D0 mixer. Bit combinations of 01, 10,
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 and 00 disable the loopback.
In MODEs 1 & 2, the input mixer is
PD7-PD0 Playback Data Port. This is the control used as a multiplexer where these
register where playback data is bits select the left ADC input source.
written during programmed IO data 00 - LLINE
transfers. 01 - LAUX1
10 - LMIC
Writing data to this register will increment the 11 - Left Output Mixer Loopback
playback byte tracking state machine so that the
following write will be to the correct byte of the
sample. Once all bytes of a sample have been
written, subsequent byte writes to this port are
ignored. The state machine is reset after the
Status register (R2) is read, and the current sam-
ple is sent to the DACs via the FIFOs.

DS215PP4 35
 CS4238B

the gain stage, is muted.

In MODEs 1 & 2, this bit is not avail-
Right ADC Input Control (I1) able and internally forced on (muted).
Default = 000x0000
D7 D6 D5 D4 D3 D2 D1 D0 LX1OM Left Auxiliary #1 Mute. When set to 1,
RSS1 RSS0 RMGE res RAG3 RAG2 RAG1 RAG0 the left Auxiliary #1 input, LAUX1, to
the output mixer through the gain
RAG3-RAG0 Right ADC Gain. The least significant stage, is muted.
bit represents +1.5 dB, with To Output
0000 = 0 dB. See Table 7. LX1OM Mixer
LAUX1 LX1G4-G0
(Line In) To Input
res Reserved. Must write 0. Could read Mixer
LX1IM
as 0 or 1. +12 to -34.5 dB

RMGE This bit has no function in MODE 3. LX1BM

In MODEs 1 & 2 it controls the
20 dB gain boost for the right MIC in-
put to the ADCs. Right Auxiliary #1 Volume (I3)
Default = 11101000
RSS1-RSS0 Right output loopback. In MODE 3 D7 D6 D5 D4 D3 D2 D1 D0
setting these bits to 11 enables the RX1OM RX1IM RX1BM RX1G4 RX1G3 RX1G2 RX1G1 RX1G0
right output loopback into the input
mixer. Other bit combinations dis-
RX1G4-RX1G0 Right Auxiliary #1, RAUX1, Mix Gain.
able the loopback.
The least significant bit represents
In MODEs 1 & 2, the input mixer is
1.5 dB, with 01000 = 0 dB.
used as a mux. where these bits se-
See Table 10.
lect the right ADC input source.
00 - RLINE
RX1BM Right Auxiliary #1 Bypass Mute. In
01 - RAUX1
MODE 3, when set, the right Auxil-
10 - RMIC
iary #1 input, RAUX1, (bypassing
11 - Right Output Mixer Loopback
the gain) to the input mixer is muted.
In MODEs 1 & 2, this bit is not avail-
Left Auxiliary #1 Volume (I2) able and is internally controlled by
RSS1,0 in I1.
Default = 11101000
D7 D6 D5 D4 D3 D2 D1 D0 RX1IM Right Auxiliary #1 Mute. When set to 1,
LX1OM LX1IM LX1BM LX1G4 LX1G3 LX1G2 LX1G1 LX1G0 the right Auxiliary #1 input, RAUX1,
to the input mixer through the gain
LX1G4-LX1G0 Left Auxiliary #1, LAUX1, Mix Gain. stage, is muted.
The least significant bit represents In MODEs 1 & 2, this bit is not avail-
1.5 dB, with 01000 = 0 dB. able and internally forced on (muted).
See Table 10.
RX1OM Right Auxiliary #1 Mute. When set to 1,
LX1BM Left Auxiliary #1 Bypass Mute. In the right Auxiliary #1 input, RAUX1,
MODE 3, when set, the left Auxiliary to the output mixer through the gain
#1 input, LAUX1, (bypassing the stage, is muted.
gain) to the input mixer, is muted. In
MODEs 1 & 2, this bit is not avail- To Output
able and is internally controlled by RX1OM Mixer
RAUX1 RX1G4-G0
LSS1,0 in I0. (Line In) To Input
RX1IM Mixer
LX1IM Left Auxiliary #1 Mute. In MODE 3, +12 to -34.5 dB
when set, the left Auxiliary #1 input,
LAUX1, to the input mixer through RX1BM

36 DS215PP4
 CS4238B

RX2OM Right Auxiliary #2 Mute. When set to

1, the right Auxiliary #2 input,
Left Auxiliary #2 Volume (I4)
RAUX2, to the output mixer through
Default = 11x01000 the gain stage, is muted.
D7 D6 D5 D4 D3 D2 D1 D0 To Output
LX2OM LX2IM res LX2G4 LX2G3 LX2G2 LX2G1 LX2G0 RX2OM Mixer
RAUX2 RX2G4-G0
(Line In) To Input
LX2G4-LX2G0 Left Auxiliary #2, LAUX2, Mix Gain.
RX2IM Mixer
The least significant bit represents
1.5 dB, with 01000 = 0 dB. +12 to -34.5 dB
See Table 10.
Left DAC (PC Wave) Volume (I6)
res Reserved. Must write 0.
Default = 10000000
LX2IM Left Auxiliary #2 Mute. In MODE 3, D7 D6 D5 D4 D3 D2 D1 D0
when set to 1, the left Auxiliary #2 in- LDM LDG6 LDG5 LDG4 LDG3 LDG2 LDG1 LDG0
put, LAUX2, to the input mixer LPM res LPA5 LPA4 LPA3 LPA2 LPA1 LPA0
through the gain stage, is muted.
In MODEs 1 & 2, this bit is not avail- If both IFM (X4 or Global Config. byte) and WTEN
able and internally forced on (muted). (C8 or Global Config. byte) are cleared, this register
is the master digital audio volume for the left channel
LX2OM Left Auxiliary #2 Mute. When set to 1, with the following bit definitions:
the left Auxiliary #2 input, LAUX2, to
the output mixer through the gain LDG6-LDG0 Left DAC Master Volume. The least
stage, is muted. significant bit represents 1.5 dB, with
To Output 0000000 = 0 dB. The total range is
Mixer +12 to -94.5 dB. See Table 12.
LAUX2 LX2OM
LX2G4-G0
(Line In) To Input LDM Left DAC Master Mute. When set, the
LX2IM Mixer left DAC output is muted.
+12 to -34.5 dB
If IFM or WTEN is set, this register controls the left
channel volume for data coming from the ISA bus
Right Auxiliary #2 Volume (I5)
only (and X14 is the left channel digital audio master
Default = 11x01000 volume) with the following bit descriptions.
D7 D6 D5 D4 D3 D2 D1 D0
RX2OM RX2IM res RX2G4 RX2G3 RX2G2 RX2G1 RX2G0 LPA5-LPA0 Left PC Wave Attenuation. The least
significant bit represents -1.5 dB,
RX2G4-RX2G0 Right Auxiliary #2, RAUX2, Mix Gain. with 000000 = 0 dB. The total range
The least significant bit represents is 0 to -94.5 dB. See Table 6.
1.5 dB, with 01000 = 0 dB.
See Table 10. res Reserved. Must write 0. Could read
as 0 or 1.
res Reserved. Must write 0. Could read
as 0 or 1. LPM Left PC Wave Mute. When set, the
left PCM input to the digital mixer
RX2IM Right Auxiliary #2 Mute. In MODE 3, summer will be muted.
when set, the right Auxiliary #2 in-
put, RAUX2, to the input mixer
through the gain stage, is muted.
In MODEs 1 & 2, this bit is not avail-
able and internally forced on (muted).

DS215PP4 37
 CS4238B

CFS2-CFS0 Clock Frequency Divide Select: These

bits select the audio sample fre-
Right DAC (PC Wave) Volume (I7)
quency for both capture and
Default = 10000000 playback. The actual audio sample
D7 D6 D5 D4 D3 D2 D1 D0 frequency depends on which clock
RDM RDG6 RDG5 RDG4 RDG3 RDG2 RDG1 RDG0 base (C2SL) is selected. Note that
RPM res RPA5 RPA4 RPA3 RPA2 RPA1 RPA0 these bits can be disabled by setting
SRE in I22 or IFSE in X11.
If both IFM (X4 or Global Config. byte) and WTEN CAUTION: CFS2-CFS0 can only be
(C8 or Global Config. byte) are cleared, this register changed while MCE (R0) is set.
is the master digital audio volume for the right chan-
nel with the following bit definitions: DIVIDE C2SL = 0 C2SL = 1
0 - 3072 8.0 kHz 5.51 kHz
RDG6-RDG0 Right DAC Master Volume. The least 1 - 1536 16.0 kHz 11.025 kHz
significant bit represents 1.5 dB, with
2 - 896 27.42 kHz 18.9 kHz
0000000 = 0 dB. The total range is
+12 to -94.5 dB. See Table 12. 3 - 768 32.0 kHz 22.05 kHz
4 - 448 N/A 37.8 kHz
RDM Right DAC Master Mute. When set, 5 - 384 N/A 44.1 kHz
the left DAC output is muted. 6 - 512 48.0 kHz 33.075 kHz
7 - 2560 9.6 kHz 6.62 kHz
If IFM or WTEN is set, this register controls the right
channel volume for data coming from the ISA bus
only (and X15 is the right channel digital audio mas-
ter volume) with the following bit descriptions. S/M Stereo/Mono Select: This bit deter-
mines how the audio data streams
are formatted. Selecting stereo will
RPA5-RPA0 Right PC Wave Attenuation. The least
result in alternating samples repre-
significant bit represents -1.5 dB,
senting left and right audio channels.
with 000000 = 0 dB. The total range
is 0 to -94.5 dB. See Table 6. Mono playback plays the same
audio sample on both channels.
Mono capture only captures data
res Reserved. Must write 0. Could read
from the left channel. In MODE 1,
as 0 or 1.
this bit is used for both playback and
capture. In MODEs 2 and 3, this bit
RPM Right PC Wave Mute. When set, the
is only used for playback, and the
right PCM input to the digital mixer
capture format is independently se-
summer will be muted.
lected via I28. MCE (R0) or PMCE
(I16) must be set to modify S/M.
Fs and Playback Data Format (I8) See Changing Audio Data Formats
section for more details.
Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0 0 - Mono
FMT1 FMT0 C/L S/M CFS2 CFS1 CFS0 C2SL
1 - Stereo

C2SL Clock 2 Source Select: This bit selects

the clock base used for the audio
sample rates for both capture and
playback. Note that this bit can be
disabled by setting SRE in I22 or by
setting IFSE in X11.
CAUTION: C2SL can only be
changed while MCE (R0) is set.

See Table below.

38 DS215PP4
 CS4238B

C/L, FMT1, and FMT0 bits set the audio data format ables PIO capture mode. CEN may
as shown below. In MODE 1, FMT1, be set and reset without setting the
which is forced low, FMT0, and C/L MCE bit.
are used for both playback and cap-
ture. In MODEs 2 and 3, these bits 0 - Capture Disabled (capture DRQ
are only used for playback, and the and PIO inactive)
capture format is independently se- 1 - Capture Enabled
lected via register I28. MCE (R0) or
PMCE (I16) must be set to modify SDC Single DMA Channel: This bit will force
the upper four bits of this register. BOTH capture and playback DMA re-
See Changing Audio Data Formats quests to occur on the Playback
section for more details. DMA channel. This bit forces the
WSS Codec to use one DMA chan-
FMT1† FMT0 C/L Audio Data Format nel. Should both capture and
D7 D6 D5 playback be enabled in this mode,
0 0 0
only the playback will occur. See the
Linear, 8-bit unsigned
DMA Interface section for further ex-
0 0 1 µ-Law, 8-bit companded planation.
0 1 0 Linear, 16-bit two’s
complement, Little Endian 0 - Dual DMA channel mode
0 1 1 A-Law, 8-bit companded 1 - Single DMA channel mode
1 0 0 RESERVED
1 0 1 ADPCM, 4-bit, IMA compatible CAL1,0 Calibration: These bits determine
1 1 0 Linear, 16-bit two’s which type of calibration the WSS
complement, Big Endian Codec performs whenever the Mode
1 1 1 Change Enable (MCE) bit, R0,
RESERVED
changes from 1 to 0. The number of
sample periods required for calibra-
† FMT1 is not available in MODE 1 (forced to 0). tion is listed in parenthesis.

Interface Configuration (I9) 0 - No calibration (0)

1 - Converter calibration (321)
Default = 00x01000 2 - DAC calibration (120)
D7 D6 D5 D4 D3 D2 D1 D0 3 - Full calibration (450)
CPIO PPIO res CAL1 CAL0 SDC CEN PEN
PPIO Playback PIO Enable: This bit deter-
PEN Playback Enable. This bit enables mines whether the playback data is
playback. The WSS Codec will transferred via DMA or PIO.
generate a DRQ and respond to
DACK signal when this bit is en- 0 - DMA transfers
abled and PPIO=0. If PPIO=1, PEN 1 - PIO transfers
enables PIO playback mode. PEN
may be set and reset without setting CPIO Capture PIO Enable: This bit deter-
the MCE bit. mines whether the capture data is
transferred via DMA or PIO.
0 - Playback Disabled (playback DRQ
and PIO inactive) 0 - DMA transfers
1 - Playback Enabled 1 - PIO transfers

CEN Capture Enabled. This bit enables the Caution: This register, except bits CEN and
capture of data. The WSS Codec PEN, can only be written while in Mode Change
will generate a DRQ and respond to
Enable (either MCE or PMCE). See the Chang-
DACK signal when CEN is enabled
and CPIO=0. If CPIO=1, CEN en- ing Sampling Rate section for more details.

DS215PP4 39
 CS4238B

XCTL1-XCTL0 XCTL Control: These bits are reflected

on the XCTL1,0 pins of the part.
Pin Control (I10)
NOTE: These pins are multiplexed
Default = 0000000x with other functions; therefore, they
D7 D6 D5 D4 D3 D2 D1 D0 may not be available on a particular
XCTL1 XCTL0 OSM1 OSM0 DEN DTM IEN res design.

res Reserved. Must write 0. Could read 0 - TTL logic low on XCTL1,0 pins
as 0 or 1. 1 - TTL logic high on XCTL1,0 pins

IEN Interrupt Enable: This bit enables the Error Status and Initialization (I11, Read Only)
interrupt pin. The Interrupt pin will re-
flect the value of the INT bit of the Default = 00000000
Status register (R2). The interrupt D7 D6 D5 D4 D3 D2 D1 D0
pin is active high. COR PUR ACI DRS ORR1 ORR0 ORL1 ORL0

0 - Interrupt disabled ORL1-ORL0 Overrange Left Detect: These bits

1 - Interrupt enabled determine the overrange on the left
ADC channel. These bits are up-
DTM DMA Timing Mode. MODE 2 & 3 only. dated on a sample by sample basis.
When set, causes the current DMA
request signal to be deasserted on 0 - Less than -1.5 dB
the rising edge of the IOW or IOR 1 - Between -1.5 dB and 0 dB
strobe during the next to last byte of 2 - Between 0 dB and 1.5 dB
a DMA transfer. When DTM = 0 the overrange
DMA request is released on the fall- 3 - Greater than 1.5 dB overrange
ing edge of the IOW or IOR during
the last byte of a DMA transfer. ORR1-ORR0 Overrange Right Detect: These bits
determine the overrange on the
DEN Dither Enable: When set, triangular Right ADC channel.
pdf dither is added before truncating
the ADC 16-bit value to 8-bit, un- 0 - Less than -1.5 dB
signed data. Dither is only active in 1 - Between -1.5 dB and 0 dB
the 8-bit unsigned data mode. 2 - Between 0 dB and 1.5 dB
overrange
0 - Dither enabled 3 - Greater than 1.5 dB overrange
1 - Dither disabled
DRS DRQ Status: This bit indicates the
OSM1-OSM0 These bits are enabled by setting current status of the DRQs assigned
SRE = 1 in I22. These bits in com- to the WSS Codec.
bination with DIV5-DIV0 and CS2
(I22) determine the current sample 0 - Capture AND Playback DRQs are
rate of the WSS Codec when presently inactive
SRE = 1. Note that these bits can 1 - Capture OR Playback DRQs are
be disabled by setting IFSE in X11. presently active

00 - 12kHz < Fs ≤ 24kHz ACI Auto-calibrate In-Progress: This bit

01 - Fs > 24kHz indicates the state of calibration.
10 - Fs ≤ 12kHz
11 - reserved 0 - Calibration not in progress
1 - Calibration is in progress

40 DS215PP4
 CS4238B

PUR Playback underrun: This bit is set

when playback data has not arrived
Monitor Loopback Volume (I13)
from the host in time to be played.
As a result, if DACZ = 0, the last Default = 000000x0
valid sample will be sent to the D7 D6 D5 D4 D3 D2 D1 D0
DACs. This bit is set when an error LBA5 LBA4 LBA3 LBA2 LBA1 LBA0 res LBE
occurs and will not clear until the
Status register (R2) is read. LBE Loopback Enable: When set to 1, the
ADC data is digitally mixed with data
COR Capture overrun: This bit is set when sent to the DACs. This bit controls
the capture data has not been read the loopback enable for both chan-
by the host before the next sample nels regardless of how SLBE in X10
arrives. The old sample will not be is set.
overwritten and the new sample will
be ignored. This bit is set when an 0 - Loopback disabled
error condition occurs and will not 1 - Loopback enabled
clear until the Status register (R2) is
read. res Reserved. Must write 0. Could read
as 0 or 1.
The SER bit in the Status register (R2) is simply
a logical OR of the COR and PUR bits. This LBA5-LBA0 Loopback Attenuation: These bits
enables a polling host CPU to detect an error determine the attenuation of the loop-
condition while checking other status bits. back from ADC to DAC. The least
significant bit represents -1.5 dB,
with 000000 = 0 dB. See Table 6.
MODE and ID (I12)
Default = 100x1010 LBA5-LBA0 control left and right
channels when SLBE in X10 is
D7 D6 D5 D4 D3 D2 D1 D0
clear. When SLBE = 1, these bits
1 CMS1 CMS0 res ID3 ID2 ID1 ID0
only control the left channel and
RLBA5- RLBA0 in X10 control the
ID3-ID0 Codec ID: These four bits indicate the right.
ID and initial revisions of the codec.
Further revisions are expanded in in-
direct register I25 through the Playback Upper Base (I14)
CS4236 and C1 for newer chips. Default = 00000000
These bits are read only. D7 D6 D5 D4 D3 D2 D1 D0
PUB7 PUB6 PUB5 PUB4 PUB3 PUB2 PUB1 PUB0
0001 - Rev B CS4248/CS4231
1010 - All other revisions and parts.
See Registers X25 or C1. PUB7-PUB0 Playback Upper Base: This register is
the upper byte which represents the
res Reserved. Must write 0. Could read 8 most significant bits of the 16-bit
as 0 or 1. Playback Base register. Reads from
this register return the same value
which was written. The Current
CMS1,0 Codec Mode Select bits: Enables the
Count registers cannot be read.
Extended registers and functions of
When set for MODE 1 or SDC, this
the part.
register is used for both the Play-
back and Capture Base registers.
00 - MODE 1
01 - Reserved
10 - MODE 2
11 - MODE 3

DS215PP4 41
 CS4238B

mat bits (D7-D4) for the playback

channel, I8. MCE in R0 must be
Playback Lower Base (I15) used to change the sample fre-
Default = 00000000 quency.
D7 D6 D5 D4 D3 D2 D1 D0
PLB7 PLB6 PLB5 PLB4 PLB3 PLB2 PLB1 PLB0 CMCE Capture Mode Change Enable.
When set, it allows modification of
PLB7-PLB0 Lower Base Bits: This register is the the stereo/mono and audio data for-
lower byte which represents the 8 mat bits (D7-D4) for the capture
least significant bits of the 16-bit channel, I28. MCE in R0 must be
Playback Base register. Reads from used to change the sample fre-
this register return the same value quency in I8.
which was written. When set for
MODE 1 or SDC, this register is TE Timer Enable: This bit, when set, will
used for both the Playback and Cap- enable the timer to run and interrupt
ture Base registers. the host at the specified frequency
in the timer registers.

Alternate Feature Enable I (I16) OLB Output Level Bit: Provided for back-
Default = 00000000 wards compatibility with the CS4236.
This bit does nothing on this chip.
D7 D6 D5 D4 D3 D2 D1 D0
OLB TE CMCE PMCE SF1 SF0 SPE DACZ
Alternate Feature Enable II (I17)
DACZ DAC Zero: This bit will force the out-
put of the playback channel to AC Default = 0000x000
zero when an underrun error occurs D7 D6 D5 D4 D3 D2 D1 D0
TEST TEST TEST TEST APAR res XTALE HPF
1 - Go to center scale
0 - Hold previous valid sample HPF High Pass Filter: This bit enables a
DC-blocking high-pass filter in the
SPE DSP Serial Port Enable. When digital filter of the ADC. This filter
set, audio data from the ADCs is forces the ADC offset to 0.
sent out SDOUT and audio data
from SDIN is sent to the DACs. 0 - disabled
MCE in R0 must be set to change 1 - enabled
this bit.
XTALE Crystal Enable. Provided for back-
1 - Enable serial port wards compatibility with the
0 - Disable serial port. ISA Bus CS4231A. This bit does nothing on
used for audio data. the this part.

SF1,SF0 Serial Format. Selects the format of res Reserved. Must write 0. Could read
the serial port when enabled by as 0 or 1.
SPE. MCE in R0 must be set to
change these bits. APAR ADPCM Playback Accumulator Reset.
While set, the Playback ADPCM
0 - 64-bit enhanced. Figure 9. accumulator is held at zero. Used
1 - 64-bit. Figure 10. when pausing a playback stream.
2 - 32-bit. Figure 11.
3 - ADC/DAC. Figure 12. TEST Factory Test. These bits are used for
factory testing and must remain at 0
PMCE Playback Mode Change Enable. for normal operation.
When set, it allows modification of
the stereo/mono and audio data for-

42 DS215PP4
 CS4238B

When IFM=1 (X4 or Global Config. byte) and

FMRM=1 (X4), FM remapping is enabled. When
Left Line (Synthesizer) Volume (I18) WTEN=1 (C8 or Global Config. byte) and
Default = xxxxxxxx WTRMD=0 (X4), Wavetable remapping is enabled. If
D7 D6 D5 D4 D3 D2 D1 D0 either synthesizer remap is enabled, left LINE ana-
LLOM LLIM LLBM LLG4 LLG3 LLG2 LLG1 LLG0 log volume is controlled through X0. With remapping
LR7 LR6 LR5 LR4 LR3 LR2 LR1 LR0 the bit definitions are:

This register controls either the left LINE input or is LR7-LR0 Left Remapped Register.
remapped to control the internal FM (X6) or external
CS9236 Wavetable synthesizer (X16), or both. When When IFM=1 and FMRM=1, writes
no remapping occurs, the bit definitions are: to I18 will write the Internal FM regis-
ter X6.
LLG4-LLG0 Left LINE Volume. This register is
used to control the LLINE analog in- When WTEN=1 and WTRMD=0,
put volume to the mixers. The least writes to I18 will write the Wavetable
significant bit represents 1.5 dB, with synthesis register X16.
01000 = 0 dB. See Table 10.
Right Line (Synthesizer) Volume (I19)
LLBM Left LINE Bypass Mute. In MODE 3,
when set to 1, the analog Left Line Default = xxxxxxxx
Input, LLINE, (bypassing the gain D7 D6 D5 D4 D3 D2 D1 D0
block) to the input mixer is muted. RLOM RLIM RLBM RLG4 RLG3 RLG2 RLG1 RLG0
In MODEs 1 & 2, this bit is not avail- RR7 RR6 RR5 RR4 RR3 RR2 RR1 RR0
able and is internally controlled by
LSS1,0 in I0. This register controls either the right LINE input or is
remapped to control the internal FM (X7) or external
LLIM Left LINE Input Mute. In MODE 3, CS9236 Wavetable synthesizer (X17), or both. When
when set to 1, the Left Line Input, no remapping occurs, the bit definitions are:
LLINE, from the volume control to
the input mixer is muted. RLG4-RLG0 Right LINE Volume. This register is
In MODEs 1 & 2, this bit is not avail- used to control the RLINE analog in-
able and internally forced on (muted). put volume to the mixers. The least
significant bit represents 1.5 dB, with
LLOM Left LINE Output Mute. 01000 = 0 dB. See Table 10.
When set to 1, the Left Line Input,
LLINE, from the volume control to RLBM Right LINE Bypass Mute. In MODE 3,
the output mixer is muted. when set to 1, the analog Right Line
Input, RLINE, (bypassing the gain
block) to the input mixer is muted.
In MODEs 1 & 2, this bit is not avail-
To Output
Mixer able and is internally controlled by
LLINE LLOM RSS1,0 in I1.
LLG4-G0
(Synthesis) To Input
LLIM Mixer
+12 to -34.5 dB

LLBM

DS215PP4 43
 CS4238B

RLIM Right LINE Input Mute. In MODE 3,

when set to 1, the Right Line Input,
Timer Upper Base (I21)
RLINE, from the volume control to
the input mixer is muted. Default = 00000000
In MODEs 1 & 2, this bit is not avail- D7 D6 D5 D4 D3 D2 D1 D0
able and internally forced on (muted). TU7 TU6 TU5 TU4 TU3 TU2 TU1 TU0

RLOM Right LINE Output Mute. TU7-TU0 Upper Timer Bits: This is the high
When set to 1, the Right Line Input, order byte of the 16-bit timer. The
RLINE, from the volume control to time base is determined by the fre-
the output mixer is muted. quency base selected from either
To Output C2SL in I8 or CS2 in I22.
RLOM Mixer
RLINE RLG4-G0 C2SL = 0 - 24.576MHz / 245
(Synthesis) To Input (9.969 µs)
RLIM Mixer
+12 to -34.5 dB C2SL = 1 - 16.9344MHz / 168
(9.92 µs)
RLBM
When IFM=1 and FMRM=1, FM remapping is en-
abled. When WTEN=1 and WTRMD=0, Wavetable Alternate Sample Frequency Select (I22)
remapping is enabled. If either synthesizer remap is Default = 00000000
enabled, right LINE analog volume is controlled D7 D6 D5 D4 D3 D2 D1 D0
through X1. With remapping the bit definitions are: SRE DIV5 DIV4 DIV3 DIV2 DIV1 DIV0 CS2

RR7-RR0 Right Remapped Register.

CS2 Clock 2 Base Select. This bit selects
the base clock frequency used for
When IFM=1 and FMRM=1, writes
generating the audio sample rate.
to I19 will write the Internal FM regis-
Note that the part uses only one
ter X7.
crystal to generate both clock base
frequencies. This bit can be disabled
When WTEN=1 and WTRMD=0,
by setting IFSE in X11.
writes to I19 will write the Wavetable
synthesis register X17.
0 - 24.576 MHz base
1 - 16.9344 MHz base
Timer Lower Base (I20)
DIV5 - DIV0 Clock Divider. These bits select the
Default = 00000000 audio sample frequency for both cap-
D7 D6 D5 D4 D3 D2 D1 D0 ture and playback. These bits can
TL7 TL6 TL5 TL4 TL3 TL2 TL1 TL0
be overridden by IFSE in X11.

TL7-TL0 Lower Timer Bits: This is the low order Fs = (2*XT)/(M*N)

byte of the 16-bit timer base register.
Writes to this register cause both XT = 24.576 MHz CS2 = 0
timer base registers to be loaded XT = 16.9344 MHz CS2 = 1
into the internal timer; therefore, the
upper timer register should be N = DIV5-DIV0
loaded before the lower. Once the 16 ≤ N ≤ 49 for XT = 24.576 MHz
count reaches zero, an interrupt is 12 ≤ N ≤ 33 for XT = 16.9344 MHz
generated, if enabled, and the timer
is automatically reloaded with these
base registers.

44 DS215PP4
 CS4238B

(M set by OSM1,0 in I10)

M = 64 for Fs > 24 kHz
Alternate Feature Status (I24)
M = 128 for 12 kHz < Fs ≤ 24 kHz
M = 256 for Fs ≤ 12 kHz Default = x0000000
D7 D6 D5 D4 D3 D2 D1 D0
SRE Alternate Sample Rate Enable. When res TI CI PI CU CO PO PU
this bit is set to a one, bits 0-3 of I8
will be ignored, and the sample fre- PU Playback Underrun: When set,
quency is then determined by CS2, indicates the DAC has run out of
DIV5-DIV0, and the oversampling data and a sample has been missed.
mode bits OSM1, OSM0 in I10. Note
that this register can be overridden PO Playback Overrun: When set,
(disabled) by IFSE in X11. indicates that the host attempted to
write data into a full FIFO and the
Extended Register Access (I23) data was discarded.

Default = 00000xx0 CO Capture Overrun: When set,

D7 D6 D5 D4 D3 D2 D1 D0 indicates that the ADC had a sample
XA3 XA2 XA1 XA0 XRAE XA4 res ACF to load into the FIFO but the FIFO
was full. In this case, this bit is set
ACF ADPCM Capture Freeze. When set, and the new sample is discarded.
the capture ADPCM accumulator
and step size are frozen. This bit CU Capture Underrun: Indicates the host
must be set to zero for adaptation to has read more data out of the FIFO
continue. This bit is used when than it contained. In this condition,
pausing a ADPCM capture stream. the bit is set and the last valid byte
is read by the host.
res Reserved. Must write 0. Could read
as 0 or 1. PI Playback Interrupt: Indicates an
interrupt is pending from the play-
XA4 Extended Register Address bit 4. back DMA count registers.
Along with XA3-XA0, enables ac-
cess to extended registers X16, CI Capture Interrupt: Indicates an
X17, and X25. MODE 3 only. interrupt is pending from the capture
DMA count registers.
XRAE Extended Register Access Enable.
Setting this bit converts this register TI Timer Interrupt: Indicates an interrupt
from the extended address register is pending from the timer registers
to the extended data register. To con-
vert back to an address register, R0 res Reserved. Must write 0. Could read
must be written. MODE 3 only. as 0 or 1.

XA3-XA0 Extended Register Address. Along The PI, CI, and TI bits are reset by writing a "0"
with XA4, sets the register number to the particular interrupt bit or by writing any
(X0-X17+X25) accessed when value to the Status register (R2).
XRAE is set. MODE 3 only. See the
WSS Extended Register section for
more details.

DS215PP4 45
 CS4238B

res Reserved. Must write 0. Could read

as 0 or 1.
Compatibility ID (I25)
Default = 00000011 MBY Mono Bypass. MBY connects MIN
D7 D6 D5 D4 D3 D2 D1 D0 directly to MOUT with an attenuation
V2 V1 V0 CID4 CID3 CID2 CID1 CID0 of 9 dB. When MBY = 1, MIM
should be set to 1.
CID4-CID0 Chip Identification. Distinguishes
between this chip and previous 0 - MIN not connected directly to
codec chips that support this register MOUT.
set. This register is fixed to indicate 1 - MIN connected directly to MOUT.
code compatibility with the CS4236.
X25 or C1 should be used to further MOM Mono Output Mute. In MODE 3, MOM
differentiate between parts that are will mute the left Line Out to the
compatible with the CS4236. mono mix output, MOUT. The right
Line Out mute, MOMR, is in X5. In
All Chips: 00011 - CS4236, CS4238B MODE 2, MOM mutes left and right
00010 - CS4232/CS4232A Line Out to MOUT. This mute is inde-
00000 - CS4231/CS4231A pendent of the line output mute.

V2-V0 Version number. As enhancements 0 - no mute

are made to the part, the version 1 - mute
number is changed so software can
distinguish between the different ver- MIM Mono Input Mute. In MODE 3, MIM
sions. mutes the MIN analog input to the
left output mixer channel. MIMR in
000 - Compatible with the CS4236 X4 mutes MIN analog input to the
right output mixer channel. In
These bits are fixed for compatibility MODE 2, MIM mutes both left and
with the CS4236. Register X25 or right channels. The mono input pro-
C1 may be used to differentiate be- vides mix for the "beeper" function in
tween the CS4236 and newer chips. most personal computers.

0 - no mute
Mono Input and Output Control (I26) 1 - muted
Default = 101x0000
D7 D6 D5 D4 D3 D2 D1 D0
MIM MOM MBY res MIA3 MIA2 MIA1 MIA0

MIA3-MIA0 Mono Input Attenuation. When MIM

is 0, these bits set the level of MIN
summed into the mixer. MIA0 is the
least significant bit and represents
3 dB attenuation, with 0000 = 0 dB.
See Table 7.

46 DS215PP4
 CS4238B

Reserved (I27) Reserved (I29)

Default = xxxxxxxx Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
res res res res res res res res res res res res res res res res

res Reserved. Must write 0. Could read res Reserved. Must write 0. Could read
as 0 or 1. as 0 or 1.

Capture Data Format (I28) Capture Upper Base (I30)

Default = 0000xxxx Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
FMT1 FMT0 C/L S/M res res res res CUB7 CUB6 CUB5 CUB4 CUB3 CUB2 CUB1 CUB0

res Reserved. Must write 0. Could read CUB7-CUB0 Capture Upper Base: This register is
as 0 or 1. the upper byte which represents the
8 most significant bits of the 16-bit
S/M Stereo/Mono Select: This bit deter- Capture Base register. Reads from
mines how the capture audio data this this register returns the same
stream is formatted. Selecting stereo value that was written.
will result with alternating samples
representing left and right audio
channels. Selecting mono only cap-
Capture Lower Base (I31)
tures data from the left audio Default = 00000000
channel. MCE (R0) or CMCE (I16) D7 D6 D5 D4 D3 D2 D1 D0
must be set to modify S/M. See CLB7 CLB6 CLB5 CLB4 CLB3 CLB2 CLB1 CLB0
Changing Audio Data Formats sec-
tion for more details. CLB7-CLB0 Lower Base Bits: This register is the
lower byte which represents the 8
0 - Mono least significant bits of the 16-bit
1 - Stereo Capture Base register. Reads from
this register returns the same value
C/L, FMT1, FMT0 set the capture data format in which was written.
MODEs 2 and 3. See Table 11 or
register I8 for the bit settings and
data formats. The capture data for-
mat can be different than the
playback data format; however, the
sample frequency must be the same
and is set in I8. MCE (R0) or CMCE
(I16) must be set to modify this regis-
ter. See Changing Audio Data
Formats section for more details.

DS215PP4 47
 CS4238B

WSS EXTENDED REGISTERS Address Reg. Register Name

The Windows Sound System codec contains WSSbase+0 R0 Reset Address
three sets of registers: R0-R3, I0-I31, and X0- WSSbase+1 R1 Address/Data access
I23 Indexed Address/Data
X25. R0-R3 are directly mapped to the ISA bus
through WSSbase+0 through WSSbase+3 re-
spectively. R0 and R1 provide access to the Extended Register Access (I23)
indirect registers I0-I31. The third set of registers D7 D6 D5 D4 D3 D2 D1 D0
XA3 XA2 XA1 XA0 XRAE XA4 res ACF
are extended registers X0-X25 that are indirectly
mapped through the WSS register I23. I23 acts Table 16. WSS Extended Register Control
as both the extended address and extended data
register. These extended registers are only avail-
able when in MODE 3. Index Register Name
X0 Left LINE Alternate Volume
X1 Right LINE Alternate Volume
Accessing the X registers requires writing the
X2 Left MIC Volume
register address to I23 with XRAE set. When
X3 Right MIC Volume
XRAE is set, I23 changes from an address regis-
X4 Synthesis and Input Mixer Control
ter to a data register. Subsequent accesses to I23
X5 Right Input Mixer Control
access the extended data register. To convert I23 X6 Left FM Synthesis Volume
back to the extended address register, R0 must X7 Right FM Synthesis Volume
be written which internally clears XRAE. As- X8 Left DSP Serial Port Volume
suming the part is in MODE 3, the following X9 Right DSP Serial Port Volume
steps access the X registers: X10 Right Loopback Monitor Volume
X11 DAC Mute and IFSE Enable
1. Write 17h to R0 (to access I23). X12 Independent ADC Sample Freq.
R1 is now the extended address register. X13 Independent DAC Sample Freq.
2. Write the desired X register address to R1 X14 Left Master Digital Audio Volume
with XRAE = 1. X15 Right Master Digital Audio Volume
R1 is now the extended data register. X16 Left Wavetable Serial Port Volume
3. Write/Read X register data from R1. X17 Right Wavetable Serial Port Volume
X18-X24 Reserved
To read/write a different X register:
4. Write 17h to R0 again. (resets XRAE) Table 17. WSS Extended Registers
R1 is now the extended address register.
5. Write the new X register address to R1
with XRAE = 1.
R1 is now the new extended data register.
6. Read/Write new X register data from R1.

48 DS215PP4
 CS4238B

Control Registers for the Extended Registers

ADDRESS D7 D6 D5 D4 D3 D2 D1 D0
WSSbase+0 R0 INIT MCE TRD IA4 IA3 IA2 IA1 IA0
WSSbase+1 R1 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0
I23 XA3 XA2 XA1 XA0 XRAE XA4 - ACF

Extended Registers: (X0-X17, X25)

XA4 - XA0 D7 D6 D5 D4 D3 D2 D1 D0
X0 LLAOM LLAIM LLABM LLAG4 LLAG3 LLAG2 LLAG1 LLAG0
X1 RLAOM RLAIM RLABM RLAG4 RLAG3 RLAG2 RLAG1 RLAG0
X2 LMIM LMOM LMBST LMG4 LMG3 LMG2 LMG1 LMG0
X3 RMIM RMOM RMBST RMG4 RMG3 RMG2 RMG1 RMG0
X4 MIMR LIS1 LIS0 IFM WTRMD FMRM - -
X5 MOMR RIS1 RIS0 - - - - -
X6 LFMM - LFMA5 LFMA4 LFMA3 LFMA2 LFMA1 LFMA0
X7 RFMM - RFMA5 RFMA4 RFMA3 RFMA2 RFMA1 RFMA0
X8 LSPM - LSPA5 LSPA4 LSPA3 LSPA2 LSPA1 LSPA0
X9 RSPM - RSPA5 RSPA4 RSPA3 RSPA2 RSPA1 RSPA0
X10 SLBE - RLBA5 RLBA4 RLBA3 RLBA2 RLBA1 RLBA0
X11 LDMIM RDMIM IFSE - - - - -
X12 SRAD7 SRAD6 SRAD5 SRAD4 SRAD3 SRAD2 SRAD1 SRAD0
X13 SRDA7 SRDA6 SRDA5 SRDA4 SRDA3 SRDA2 SRDA1 SRDA0
X14 LDMOM LDMG6 LDMG5 LDMG4 LDMG3 LDMG2 LDMG1 LDMG0
X15 RDMOM RDMG6 RDMG5 RDMG4 RDMG3 RDMG2 RDMG1 RDMG0
X16 LWM - LWG5 LWG4 LWG3 LWG2 LWG1 LWG0
X17 RWM - RWG5 RWG4 RWG3 RWG2 RWG1 RWG0
X25 V2 V1 V0 CID4 CID3 CID2 CID1 CID0

Table 18. Extended Register Bit Summary

DS215PP4 49
 50

DSP SERIAL PORT

Mute X2L, X3R Gain X2L

MIC
DSP Audio Data Serial Port NOTE: The symbol X3R

s
s
shows the active bit(s) for the Mute I2L, I3R

s
s
s
s
s
register function specified

s
Mute I2L, I3R Gain I2L AUX1
I3R (LINE IN)

s
Analog Input

s
s
s
s
s
Mixer Atten. Mute I4L, I5R Gain I4L AUX 2
16-bit Gain I0L X4L I5R (CDROM)

s
SRC
A/D I1R X5R

s
s
s
s
s
Mute I18L, I19R

s
s
s
s
*

s
s

s
Atten. X8L Loopback Atten. Mute I18L, I19R Gain I18L LINE
X9R I13L & (R) * * I19R (Syn.)

s
s
s
s
s
s
s

s
s
s
s
s
X10 Stereo Enable
s
s
s
s
s
s

Mute
s

Mute X8L X10R X11L

s
s
s
s
s
s
s
X9R Loopback enable I13 X11R

s
PnP ISA Interface

20dB X2L
s

Master Digital Mute X2L, X3R

Gain X3R
Digital Mixer Volume Output

s
s
Mute I6L 16 bit Gain X14L Loopback
Mute I2L, I3R
I7R DSP X15R I0L, I1R
D/A

s
s
s
s
s
s
Mute I4L, I5R

s
s
s

s
s
s
Mute X6L Mute I18L, I19R
Atten. I6L Mute X16L
* X7R Analog *
I7R * X17R

s
s

Mute X14L Output

s
s
s
s
s
s

Master LINE
Atten. X6L X15R
Volume OUT
s

* X7R Mute
SRC Gain X16L Mixer
s
s
s
s
s
s

I26L

s
* X17R X5R
Mute I26L

s
s
s
s
s
s

FM Synthesizer enable Mono Bypass

X4R
X4
s

Atten.
s

MONO
Atten. I26 -9db
Wavetable Serial Port OUT
* I18/I19 can be remapped to control
s
s
s
s
C8
s

X6/X7 and X16/X17. If remapping is Mute I26

enabled, X0/X1 control LINE inputs

CS4238B
DS215PP4

WAVETABLE SERIAL PORT MIN UP/DOWN/MUTE

Figure 4. MODE 3 Mixer (assumes IFM or WTEN is set)
 CS4238B

Left LINE Alternate Volume (X0) Right LINE Alternate Volume (X1)
Default = 11101000 Default = 11101000
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
LLAOM LLAIM LLBAM LLAG4 LLAG3 LLAG2 LLAG1 LLAG0 RLAOM RLAIM RLABM RLAG4 RLAG3 RLAG2 RLAG1 RLAG0

LLAG4-LLAG0 Left LINE Alternate Volume. This RLAG4-RLAG0 Right LINE Alternate Volume.
register is used to control the LLINE This register is used to control the
analog input volume to the mixers RLINE analog input volume to the
when I18 is remapped to control FM mixers when I19 is remapped to con-
and/or Wavetable Serial Port vol- trol FM and/or Wavetable Serial Port
ume. The remapping bits are FMRM volume. The remapping bits are
and WTRMD (X4). The least signifi- FMRM and WTRMD in X4. The
cant bit represents 1.5 dB, with least significant bit represents
01000 = 0 dB. See Table 10. 1.5 dB, with 01000 = 0 dB.
See Table 10.
LLABM Left LINE Alternate Bypass Mute.
When set to 1, the analog Left Line RLABM Right LINE Alternate Bypass Mute.
Input, LLINE, (bypassing the gain When set to 1, the analog Right Line
block) to the input mixer is muted. Input, RLINE, (bypassing the gain
block) to the input mixer is muted.
LLAIM Left LINE Alternate Input Mute.
When set to 1, the Left Line Input, RLAIM Right LINE Alternate Input Mute.
LLINE, from the volume control to When set to 1, the Right Line Input,
the input mixer is muted. RLINE, from the volume control to
the input mixer is muted.
LAOM Left LINE Alternate Output Mute.
When set to 1, the Left Line Input, RLAOM Right LINE Alternate Output Mute.
LLINE, from the volume control to When set to 1, the Right Line Input,
the output mixer is muted. RLINE, from the volume control to
the output mixer is muted.
To Output
LLAOM Mixer
LLINE LLAG4-G0 To Output
(Synthesis) To Input RLAOM Mixer
RLINE RLAG4-G0
LLAIM Mixer (Synthesis) To Input
+12 to -34.5 dB
RLAIM Mixer
+12 to -34.5 dB
LLABM
RLABM

DS215PP4 51
 CS4238B

To Output
Mixer
Left MIC Volume (X2) RMIC RMOM +20 dB
RMG4-G0 RMBST
Input To Input
Default = 11001111 Mixer
RMIM
D7 D6 D5 D4 D3 D2 D1 D0 +22.5 to -22.5 dB
LMIM LMOM LMBST LMG4 LMG3 LMG2 LMG1 LMG0

LMG4-LMG0 Left Microphone Gain. Synthesis and Input Mixer Control (X4)
The least significant bit represents
1.5 dB, with 01111 = 0 dB. Default = 100001xx
See Table 13. D7 D6 D5 D4 D3 D2 D1 D0
MIMR LIS1 LIS0 IFM WTRMD FMRM res res
LMBST Left Microphone 20 dB boost.
When set to 1, the signal to the out- res Reserved. Must write 0. Could be
put mixer is given a 20 dB boost. read as 0 or 1.

LMOM Left Microphone Output Mixer Mute. FMRM FM Volume Control Remap. This bit
When set to 1, the signal to the out- only functions when IFM = 1.
put mixer is muted.
If FMRM = 1, internal FM Synthesis
LMIM Left Microphone Input Mixer Mute. volume is controlled by I18/I19
When set to 1, the signal to the in- (writes to I18/I19 get remapped to
put mixer is muted. X6/X7). Analog LINE volume is con-
trolled by X0/X1.
To Output
+20 dB Mixer
LMIC LMOM If FMRM = 0, internal FM synthesis
LMG4-G0 LMBST
Input To Input volume is controlled by X6/X7 only.
Mixer
LMIM
+22.5 to -22.5 dB
WTRMD WaveTable Volume Remap Disable.
This bit only functions when
WTEN = 1 (C8/Global Config. byte).
Right MIC Volume (X3)
Default = 11001111 If WTRMD = 0, the Wavetable Serial
D7 D6 D5 D4 D3 D2 D1 D0 Port volume is controlled by I18/I19
RMIM RMOM RMBST RMG4 RMG3 RMG2 RMG1 RMG0 (writes to I18/I19 get remapped to
X16/X17). Analog LINE volume is
controlled by X0/X1.
RMG4-RMG0 Right Microphone gain.
The least significant bit represents
If WTRMD = 1, the Wavetable Serial
1.5 dB, with 01111 = 0 dB.
Port volume is controlled by
See Table 13.
X16/X17 only.
RMBST Right Microphone 20 dB boost. NOTE: If FMRM = 1, and
When set to 1, the signal to the out- WTRMD = 0, I18/I19 control both in-
put mixer is given a 20 dB boost. ternal FM and Wavetable Serial Port
volume.
RMOM Right Microphone Output Mixer Mute.
When set to 1, the signal to the out- IFM Internal FM enable. When set to 1,
put mixer is muted. the internal FM synthesis engine is
enabled. Setting this bit also
RMIM Right Microphone Input Mixer Mute. changes I6/7 from the master digital
When set to 1, the signal to the in- audio volume to the ISA bus wave
put mixer is muted. volume control. X14/15 becomes the

52 DS215PP4
 CS4238B

master digital audio volume. This bit res Reserved. Must write 0. Could read
can be set through the Hardware as 0 or 1.
Configuration data in the EEPROM.
LFMM Left FM mute. When set to 1, the
LIS1-LIS0 Left Input Mixer Summer Attenuator. left internal FM input to the digital
This attenuates the inputs to the left mixer is muted.
input mixer to enable overload pro-
tection when multiple input sources
are utilized. The least significant bit Internal FM
LFMA5-A0 To Digital Mixer
Synthesizer LFMM
represents 6 dB of attenuation, Summer
where 00 yields 0 dB of attenuation.
0 to -94.5 dB
See Table 8.

MIMR Mono Input Mute to the Right Output

mixer. When set to 1, the MIN signal
Right FM Synthesis Volume (X7)
to the right output mixer is muted. Default = 1x000000
D7 D6 D5 D4 D3 D2 D1 D0
RFMM res RFMA5 RFMA4 RFMA3 RFMA2 RFMA1 RFMA0
Right Input Mixer Control (X5)
Default = 000xxxxx NOTE: This FM volume register can also be control-
D7 D6 D5 D4 D3 D2 D1 D0 led through I19 when IFM = 1 and FMRM = 1.
MOMR RIS1 RIS0 res res res res res
RFMA5-RFMA0 Right Internal FM Synthesis Volume.
res Reserved. Must write 0. Could be The least significant bit represents
read as 0 or 1. 1.5 dB, with 000000 = 0 dB.
See Table 6.
RIS1-RIS0 Right Input Mixer Summer Attenuator.
This attenuates the inputs to the res Reserved. Must write 0. Could read
right input mixer to enable overload as 0 or 1.
protection when multiple input
sources are utilized. The least signifi- RFMM Right FM mute. When set to 1, the
cant bit represents 6 dB of right internal FM input to the digital
attenuation, where 00 yields 0 dB of mixer is muted.
attenuation. See Table 8.
Internal FM
MOMR Mono Output Mute from the Right Synthesizer
RFMA5-A0 To Digital Mixer
RFMM Summer
Line Out, ROUT, to the mono output
mixer. When set to 1, the signal to
0 to -94.5 dB
the mono output mixer from the
Right Line Out is muted.
Left DSP Serial Port Volume (X8)
Left FM Synthesis Volume (X6) Default = 0x000000
Default = 1x000000 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 LSPM res LSPA5 LSPA4 LSPA3 LSPA2 LSPA1 LSPA0
LFMM res LFMA5 LFMA4 LFMA3 LFMA2 LFMA1 LFMA0
LSPA4-LSPA0 Left DSP Serial Port Attenuation.
NOTE: This FM volume register can also be control- The least significant bit represents
led through I18 when IFM = 1 and FMRM = 1. 1.5 dB, with 000000 = 0 dB.
See Table 6.
LFMA5-LFMA0 Left Internal FM Synthesis Volume.
The least significant bit represents res Reserved. Must write 0. Could read
1.5 dB, with 000000 = 0 dB. as 0 or 1.
See Table 6.

DS215PP4 53
 CS4238B

LSPM Left DSP Serial Port Mute. When set SLBE Stereo LoopBack Enable. When set to
to 1, the Left DSP Serial Port input 1, control over the Left and Right
(SDIN) to the digital mixer is muted. loopback volume is separated.
RLBA5-RLBA0 (X10) control the
Right channel, and LBA5-LBA0 (I13)
Serial
LSPA5-A0 To Digital Mixer control the Left channel.
Port LSPM Summer When set to 0, LBA5-LBA0 (I13) con-
trol both channels.
0 to -94.5 dB

DAC Mute and IFSE Enable (X11)

Right DSP Serial Port Volume (X9) Default = 110xxxxx
Default = 0x000000 D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0 LDMIM RDMIM IFSE res res res res res
RSPM res RSPA5 RSPA4 RSPA3 RSPA2 RSPA1 RSPA0
res Reserved. Must write 0. Could read
RSPA4-RSPA0 Right DSP Serial Port Attenuation. as 0 or 1.
The least significant bit represents
1.5 dB, with 000000 = 0 dB. IFSE Independent Sample Freq. Enable.
See Table 6. When set to 1, the extended
registers X12 and X13 are used to
res Reserved. Must write 0. Could read set the sample rate, and registers I8,
as 0 or 1. I10 (OSM1,0), and I22 are ignored.
X12 and X13 cannot be modified un-
RSPM Right DSP Serial Port Mute. When less this bit is set to 1.
set to 1, the Right DSP Serial Port
input (SDIN) to the digital mixer is RDMIM Right Digital Master Input Mixer Mute.
muted. When set to 1, the output from the
Right DAC is Muted to the Right in-
put mixer. See Figure 4.
Serial
RSPA5-A0 To Digital Mixer
Port RSPM Summer LDMIM Left Digital Master Input Mixer Mute.
When set to 1, the output from the
0 to -94.5 dB Left DAC is Muted to the Left input
mixer. See Figure 4.
Right Loopback Monitor Volume (X10)
Independent ADC Fs (X12)
Default = 0x111111
D7 D6 D5 D4 D3 D2 D1 D0 Default = xxxxxxxx
SLBE res RLBA5 RLBA4 RLBA3 RLBA2 RLBA1 RLBA0 D7 D6 D5 D4 D3 D2 D1 D0
SRAD7 SRAD6 SRAD5 SRAD4 SRAD3 SRAD2 SRAD1 SRAD0
RLBA5-RLBA0 Right Channel Loopback Attenuation.
These bits determine the attenuation SRAD7-SRAD0 Sample Rate frequency select for
of the loopback from the right ADC the A/D converter. This register is
to the right digital mixer. LBE in I13 only in effect (and can only be writ-
must be set to enable loopback. The ten) while IFSE=1 in X11.
least significant bit represents -1.5 See Table 14.
dB, with 000000 = 0 dB. See Table 6.

res Reserved. Must write 0. Could read

as 0 or 1.

54 DS215PP4
 CS4238B

Independent DAC Fs (X13) Right Master Digital Audio Volume (X15)

Default = xxxxxxxx Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SRDA7 SRDA6 SRDA5 SRDA4 SRDA3 SRDA2 SRDA1 SRDA0 RDMOM RDMG6 RDMG5RDMG4RDMG3RDMG2RDMG1RDMG0

SRDA7-SRDA0 Sample Rate frequency select for This register becomes the master digital audio vol-
the D/A converter. This register is ume control for the left channel when either IFM or
only in effect (and can only be writ- WTEN is set to one.
ten) while IFSE=1 in X11. See Table
15. RDMG6-RDMG0 Right Digital Master Mixer Attenu-
ation. The least significant bit
represents 1.5 dB, with 000000 =
Left Master Digital Audio Volume (X14) 0 dB. See Table 12.
Default = 00000000
D7 D6 D5 D4 D3 D2 D1 D0 RDMOM Right Digital Master Output Mixer Mute.
LDMOM LDMG6 LDMG5 LDMG4 LDMG3 LDMG2 LDMG1 LDMG0 When set, the Right DAC output is
muted to the Right output mixer.
This register becomes the master digital audio vol- Note: This bit is controlled
ume control for the left channel when either IFM or by register (X11)
WTEN is set to one. Digital Analog
To Input
From Digital Mixer
LDMG6-LDMG0Left Digital Master Mixer Attenuation. Mixer DAC
RDMIM

The least significant bit represents Summer To Output

RDMOM Mixer
1.5 dB, with 000000 = 0 dB. 0 to -60dB +12 to -34.5dB
See Table 12.
RDMG6-G0

LDMOM Left Digital Master Output Mixer Mute.

When set to 1, the output of the Left
DAC is muted to the Left output
mixer.
Note: This bit is controlled
by register (X11)

Digital Analog
To Input
From Digital LDMIM Mixer
Mixer DAC
Summer To Output
LDMOM Mixer
0 to -60dB +12 to -34.5dB

LDMG6-G0

DS215PP4 55
 CS4238B

Left Wavetable Serial Port Volume (X16) Chip Version and ID (X25)
Default = 00000000 Default = 11001001
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
LWM res LWG5 LWG4 LWG3 LWG2 LWG1 LWG0 V2 V1 V0 CID4 CID3 CID2 CID1 CID0

This Wavetable volume register can also be control- This register was added to Revision C silicon. In revi-
led through I18 when WTEN=1 (C8 or Global Config. sion B, this register read 0x00.
byte) & WTRMD=0 (X4).
CID5-CID0 Chip Identification. Distinguishes
LWG5-LWG0 Left Wavetable Serial Port Gain. between this chip and other codec
Least significant bit represents chips that support this register set.
1.5 dB, with 01000 = 0 dB. This register is identical to C1 and
See Table 6. replaces the ID register in I25.

res Reserved. Must write 0. Could read 00000 - CS4238B, Revision B

as 0 or 1. 01001 - CS4238B

LWM Left Wavetable Serial Port Mute. V2-V0 Version Number. As enhancements
When set, the Left Wavetable Serial are made, the version number is
Input to the digital mixer is muted. changed so software can distinguish
between the different versions of the
same chip.
Right Wavetable Serial Port Volume (X17)
Default = 00000000 000 - Revision B
D7 D6 D5 D4 D3 D2 D1 D0 110 - Revision C/D
RWM res RWG5 RWG4 RWG3 RWG2 RWG1 RWG0 111 - Revision E

This Wavetable volume register can also be control-

led through I19 when WTEN=1 (C8 or Global Config.
byte) & WTRMD=0 (X4).

RWG5-RWG0 Right Wavetable Serial Port Gain.

Least significant bit represents
1.5 dB, with 01000 = 0 dB.
See Table 6.

res Reserved. Must write 0. Could read

as 0 or 1.

RWM Right Wavetable Serial Port Mute.

When set, the Right Wavetable Se-
rial Input to the digital mixer is
muted.

56 DS215PP4
 CS4238B

SOUND BLASTER INTERFACE

Sound Blaster Direct Register Interface
The Sound Blaster Pro compatible interface is
the third physical device in logical device 0. The Sound Blaster software interface utilizes 10-
Since the WSS Codec and the Sound Blaster are bit address decoding and is compatible with
mutually exclusive, the WSS Codec interrupt Sound Blaster and Sound Blaster Pro interfaces.
and playback DMA channel are shared with the 10-bit addressing requires that the upper address
Sound Blaster interface. To map volume controls bits be 0 to decode a valid address, i.e. no alias-
properly, the external devices: synthesizer (when ing occurs. This device requires 16 I/O locations
used), CDROM, etc., must be connected to the located at the PnP address ’SBbase’. The follow-
proper analog inputs as illustrated in Figure 5. ing registers, shown in Table 19, are provided
for Sound Blaster compatibility.
Mode Switching
Left/Right FM Registers,
To facilitate switching between different func-
SBbase+0 - SBbase+3
tional modes (i.e. Sound Blaster and Windows
These registers are mapped directly to the appro-
Sound System), logic is included to handle the
priate FM synthesizer registers.
switch transparently to the host. No special soft-
ware is required on the host side to perform the
Mixer Address Register,
mode switch.
SBbase+4, write only
This register is used to specify the index address
for the mixer. This register must be written be-
fore any data is accessed from the mixer
registers. The mixer indirect register map is
shown in Table 20.

Address Description Type

SBbase+0 Left FM Status Port Read
SBbase+0 Left FM Register Status Port Write
SBbase+1 Left FM Data Port Write Only
SBbase+2 Right FM Status Port Read
SBbase+2 Right FM Register Status Port Write
SBbase+3 Right FM Status Port Write Only
SBbase+4 Mixer Register Address Write Only
SBbase+5 Mixer Data Port Read/Write
SBbase+6 Reset Write Only
SBbase+8 FM Status Port Read Only
SBbase+8 FM Register port Write
SBbase+9 FM Data Port Write Only
SBbase+A Read Data Port Read Only
SBbase+C Command/Write Data Write
SBbase+C Write Buffer Status (Bit 7) Read
SBbase+E Data Available Status (Bit 7) Read

Table 19. Sound Blaster Pro Compatible I/O Interface

DS215PP4 57
 CS4238B

MIC
MIC V A
AUX1
LINE O D
LINE
FM L C
CD DIG
ATTN
VOL
A
U
X
1

Σ
U
LINE OUT
X
2

L
I
N
E

D V
DIG VOICE Σ A O
C L

V
MONO IN
PC SPEAKER O
L

Figure 5. SBPro Mixer Mapping

Register D7 D6 D5 D4 D3 D2 D1 D0
00H DATA RESET
02H RESERVED
04H VOICE VOLUME LEFT VOICE VOLUME RIGHT
06H RESERVED
08H RESERVED
0AH X X X X X MIC MIXING
0CH X X X INPUT SELECT X
0EH X X X X X X VSTC X
20H RESERVED
22H MASTER VOLUME LEFT MASTER VOLUME RIGHT
24H RESERVED
26H FM VOLUME LEFT FM VOLUME RIGHT
28H CD VOLUME LEFT CD VOLUME RIGHT
2AH RESERVED
2CH RESERVED

Table 20. SBPro Compatible Mixer Interface

58 DS215PP4
 CS4238B

Mixer Data Register, Voice Volume Register,

SBbase+5 Mixer Index 04H, Default = 99H
This register provides read/write access to a par- This register provides 8 steps of voice volume
ticular mixer register depending on the index control each for the right and left channels.
address specified in the Mixer Address Register.
Microphone Mixing Register,
Reset Mixer Index 0AH, Default = 01H
SBbase+6, write only This register provides 4 steps of microphone vol-
When bit D[0] of this register is set to a one and ume control.
then set to a zero, a reset of the Sound Blaster
interface will occur. Input Control Register,
Mixer Index 0CH
Read Data Port This register selects the input source to the ADC.
SBbase+A, read only D2,D1 - 00 - Microphone
When bit D[7] of the Data Available Register, 01 - CD Audio
SBbase+E, is set =1 then valid data is available 10 - Microphone
in this register. The data may be the result of a 11 - Line In
Command that was previously written to the
Command/Write Data Register or digital audio Output Control Register,
data. Mixer Index 0EH
VSTC - 0 - Mono Mode
Command/Write Data 1 - Stereo Mode
SBbase+C, write only
The Command/Write Data register is used to Master Volume Register,
send Sound Blaster Pro commands. Mixer Index 22H, Default = 99H
This register provides 8 steps of master volume
Write Buffer Status, control each for the right and left channels.
SBbase+C, read only
The Write Buffer Status register bit D[7] indi- FM Volume Register,
cates when the SBPro interface is ready to Mixer Index 26H, Default = 99H
accept another command to the Command/Write This register provides 8 steps of FM volume
Data register. D[7]=1 indicates ready. D[7]=0 in- control each for the right and left channels.
dicates not ready.
CD Volume Register,
Sound Blaster Mixer Registers Mixer Index 28H, Default = 01H
The Sound Blaster mixer registers are shown in This register provides 8 steps of CD volume
Table 20. The Sound Blaster mixer to WSS control each for the right and left channels.
Codec mixer mapping is shown in Figure 5.
Line-In Volume Register,
Reset Register, Mixer Index 2EH, Default = 01H
Mixer Index 00H This register provides 8 steps of line-in volume
Writing any value to this register will reset the control each for the right and left channels.
mixer to default values.

DS215PP4 59
 CS4238B

GAME PORT INTERFACE JAB1 Joystick A, Button 1 (pin 2)

The Game Port logical device software interface JAB2 Joystick A, Button 2 (pin 7)
utilizes 10-bit address decoding and is located at
PnP address ’GAMEbase’. 10-bit addressing re- JBB1 Joystick B, Button 1 (pin 10)
quires that the upper address bits be 0 to decode
a valid address, i.e. no aliasing occurs. For back- JBB2 Joystick B, Button 2 (pin 14)
wards compatibility, the Game Port consists of 8
I/O locations where the lower 6 alias to the same
location, which consists of one read and one Two bits, JR1 and JR0, are located in the Con-
write register. trol register space (CTRLbase+0) for defining
the speed of the Game Port Interface. Four dif-
Plug and Play configuration capability will allow ferent rates are software selectable for use with
the joystick I/O base address, GAMEbase, to be various joysticks and to support older software
located anywhere within the host I/O address timing loops with aliasing (roll-over) problems.
space. Currently most games software assume
that the joystick I/O port is located at 200h. GAMEbase+6
D7 D6 D5 D4 D3 D2 D1 D0
res res res res res res res res
A write to the GAMEbase register triggers four
timers. A read from the same register returns
res Must not write any value to this
four status bits corresponding to the joystick fire register. May read any value.
buttons and four bits that correspond to the out-
put from the four timers. GAMEbase+7
D7 D6 D5 D4 D3 D2 D1 D0
A button value of 0 indicates the button is res res res res res res res res
pressed or active. The button default state is 1.
When GAMEbase is written, the X/Y timer bits res Must not write any value to this
go high. Once GAMEbase is written, each timer register. May read any value.
output remains high for a period of time deter-
mined by the current joystick position. The
The Game Port hardware interface consists of
number in parenthesis below is the joystick con-
8 pins that connect directly to the standard game
nector pin number.
port connector. Buttons must have a 4.7 kΩ pul-
lup resistor and a 1000 pF capacitor to ground.
X/Y coordinates must have a 5.6 nF capacitor to
GAMEbase+0 - GAMEbase+5 ground and a 2.2 kΩ series resistor to the appro-
D7 D6 D5 D4 D3 D2 D1 D0
priate joystick connector pin. For a detailed
JBB2 JBB1 JAB2 JAB1 JBCY JBCX JACY JACX hardware description, see the Reference Design
Data Sheet.
JACX Joystick A, Coordinate X (pin 3)

JACY Joystick A, Coordinate Y (pin 6)

JBCX Joystick B, Coordinate X (pin 11)

JBCY Joystick B, Coordinate Y (pin 13)

60 DS215PP4
 CS4238B

CONTROL INTERFACE PDM Power Down Mixer. When set, the

analog mixer is powered down and
The Control logical device includes registers for all mixer control registers (in
controlling various functions of the part that are WSSbase space) are reset to de-
not included in the other logical device blocks. fault values.
These functions include game port rate control PDP* Power Down Processor. When set,
and programmable power management, as well places the internal processor in an
as extra mixing functions. idle state. This effects the PnP inter-
face, MPU-401, and SBPro devices.
Control Register Interface
PDC* Power Down Codec. When set,
The Control logical device software interface oc- ADCs and DACs are powered down.
cupies 8 I/O locations, utilizes 12-bit address
decoding, and is located at PnP address CONSW controls host interrupt generation
’CTRLbase’. If the upper address bits, SA12- when a context switch occurs
SA15 are used, they must be 0 to decode a valid 0 - no interrupt on context switch
address. This device can also support an inter- 1 - Control interrupt generated on
rupt. Table 21 lists the eight Control registers. context switch

Address Register
PM1,0 Power Management. These bits are
CTRLbase+0 Joystick & Power Control
provided for backwards compatibility.
CTRLbase+1 E2PROM Interface For new designs, the bits in
CTRLbase+2 Block Power Down CTRLbase+2 should be used.
CTRLbase+3 Control Indirect Address Reg.
CTRLbase+4 Control Indirect Data Register 00 - All functions active.
CTRLbase+5 Control/RAM Access 01 - A/D and D/A powered down.
Mixer still active, but volume reg-
CTRLbase+6 RAM Access End
isters are frozen. Disables PDC
CTRLbase+7 Global Status and PDM bits.
10 - Full part power down. All
Table 21. Control Logical Device Registers functions are disabled except
reads and writes to this register.
All internal logic, including PnP
config. registers are reset. To exit
Joystick and Power Control this power-down mode, PM1/0
CTRLbase + 0, Default = 00000000 must be reset, through CTRLbase+
D7 D6 D5 D4 D3 D2 D1 D0 0, and then the entire chip must be
PM1 PM0 CONSW PDC PDP PDM JR1 JR0 reinitialized.
11* - WSS Codec, SBPro, MPU-401,
JR1,0 Joystick rate control. Selects operating and PnP interfaces, and the analog
speed of the joystick (changes the mixer are powered down.
trigger threshold for the X/Y coordi-
nates).
* NOTE: The SBPro, PnP, and MPU-401 interfaces
00 - slowest speed are linked together. Setting PM1,0 or PDP will power
01 - medium slow speed all three interfaces down; however, if any one of the
10 - medium fast speed interfaces is written to, they will all power back up
11 - fastest speed automatically. PM1,0 and PDP always reflects the
value written, not whether the three devices are pow-
ered up or not.

DS215PP4 61
 CS4238B

E2PROM Interface 10 - Codec Input mux is mixed into

CTRLbase+1, Default = 10000000 output mixer. A/D input is from
line outputs. This facilitates the Mic
D7 D6 D5 D4 D3 D2 D1 D0
mixed to output, and the output
ICH ISH ADC1 ADC0 IMH DIN/ DOUT CLK
EEN
recorded by the ADCs.
11 - reserved.
CLK This bit is used to generate the clock
for the Plug and Play E2PROM.
EEN must be set to 1 to make this
bit operational.

DOUT This bit is used to output serial data

to the Plug and Play E2PROM. EEN
must be set to 1 to make this bit op-
erational.

DIN/EEN When read (DIN), this bit reflects

the XD0 pin, which should be serial
data output from the Plug and Play
E2PROM. EEN and DOUT must be
1 for this bit to function.

When written (EEN), enables the

E2PROM interface: CLK and DOUT
onto the peripheral port pins. Writing:

0 - E2PROM interface disabled

1 - E2PROM interface enabled

IMH* Interrupt polarity - Modem. When set,

the MINT pin is an active high sig-
nal. When low, MINT is an active
low signal.

ADC1,0 These two bits are used to control

an additional A/D mux and enable
for an analog loopback path. These
two mixing paths provide Karaoke
support. These bits are provided for
backwards compatibility. New soft- Figure 6. MODE 2 Mixer Addition
ware should use the MIC volume
control in MODE 3 registers X2/X3 ISH* Interrupt polarity - External Synthe-
to support MIC mix to the output sizer. When set, the SINT pin is an
mixer. See Figure 6. active high signal. When low, SINT
is an active low signal.
00 - Normal. A/D input from the input
mux. ICH* Interrupt polarity - CDROM. When set,
01 - Codec Input mux is mixed into the CDINT pin is an active high sig-
output mixer. A/D input is from nal. When low, CDINT is an active
the input mux. This facilitates the low signal.
Mic mixed to output, but only Mic
recorded. * Note: These bits can be initialized through the
Hardware Configuration data.

62 DS215PP4
 CS4238B

PDWN Global Power Down. When set, the

entire chip is powered down, except
Block Power Down
reads and writes to this register.
CTRLbase+2, Default = 00000000 When this bit is cleared, a full cali-
D7 D6 D5 D4 D3 D2 D1 D0 bration is initiated. All registers retain
PDWN SRC VREF MIX ADC DAC PROC FM their values; therefore, normal opera-
tion can resume after calibration is
FM Internal FM synthesizer powered down completed. When clearing this bit,
when set. the internal processor stays in power-
down until accesses occur to
PROC Processor set to idle mode. When set, processor interface (Sound Blaster,
places the internal processor in an MPU, or PnP accesses). If hardware
idle state. This effects the PnP inter- volume control is enabled, this bit
face, MPU401, and SBPro devices. should be written to 0 twice causing
Any command to any one of these the processor to go active (which
interfaces will cause the processor reenables the hardware volume).
to go active.
NOTE: Software should mute the DACs and Mixers
DAC DAC power down. When set, powers and FM volume when asserting any power down
down the D/A converters, serial modes to prevent clicks and pops.
ports, and internal FM synthesizer.
The DACs should be muted prior to
setting this bit to prevent audible
Control Indirect Address Register
pops. CTRLbase+3
D7 D6 D5 D4 D3 D2 D1 D0
ADC ADC power down. When set, powers res res res res CA3 CA2 CA1 CA0
down the A/D Converters.
CA3-CA0 Address bits to access the Control
MIX Mixer power down. All analog input Indirect registers C0-C8 through
and output channels are powered CTRLbase+4
down, except MIN and MOUT (as-
suming VREF is not powered down). res Reserved. Could read as 0 or 1.
If MIX is 1 and VREF is 0, the MBY Must write as 0.
bit in the WSS I26 register is forced
on. The outputs should be muted
prior to setting this bit to prevent Control Indirect Data Register
audible pops.
CTRLbase+4
VREF VREF power down. When set, powers D7 D6 D5 D4 D3 D2 D1 D0
CD7 CD6 CD5 CD4 CD3 CD2 CD1 CD0
down the entire mixer. Since
powering down VREF, powers down
the entire analog section, some audi- CD7-CD0 Control Indirect Data register. This
ble pops can occur. register provides access to the indi-
rect registers C0-C8, where
SRC Internal Sample-Rate Converters are CTRLbase+3 selects the actual reg-
powered down. Only 44.1 kHz sam- ister. See the Control Indirect
ple frequency is allowed when this Register section for more details.
bit is set.

DS215PP4 63
 CS4238B

Control/RAM Access Global Status

CTRLbase+5, Default = xxxxxxxx CTRLbase+7, Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0 CWSS ICTRL ISB IWSS IMPU res res res

CR7-CR0 This register controls the loading of res Reserved. Could read as 0 or 1.
the part’s internal RAM. RAM sup-
port includes hardware configuration IMPU MPU-401 Interrupt status.
and PnP default resource data, as
well as program memory. See the 0 - no interrupt pending
Hostload Procedure section for more 1 - an interrupt is pending
information. Commands are followed
by address and data information. IWSS Windows Sound System Interrupt
status.
Commands: 0x55 - Disable PnP Key
0 - no interrupt pending
0x56 - Disable Crystal Key 1 - an interrupt is pending

0x57 - Jump to ROM ISB Sound Blaster Interrupt status.

0x5A - Update Hardware Configura- 0 - no interrupt pending

tion Data. 1 - an interrupt is pending

0xAA - Download RAM. Address ICTRL Control Logical Device 2 Interrupt

followed by data. (Stopped by writ- status. Interrupts are generated on
ing 0 to CTRLbase+6) a context switch between WSS and
SBPro modes.
RAM Access End 0 - no interrupt pending
CTRLbase+6, Default = xxxxxxxx 1 - an interrupt is pending
D7 D6 D5 D4 D3 D2 D1 D0
RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 CWSS Context - WSS. Indicates the current
context.
RE7-RE0 A 0 written to this location resets the
previous location, CTRLbase+5, 0 - Sound Blaster Emulation
from data download mode to com- 1 - Windows Sound System
mand mode.

64 DS215PP4
 CS4238B

Control Indirect Registers

The Control Indirect registers are accessed Address Register Name
thr ough CTRLbase+3 and CTRLbase+4. CTRLbase+3 Control Indirect Address
CTRLbase+3 is the address register and CTRLbase+4 Control Indirect Data
CTRLbase+4 is the data register used to access
Table 22. Control Indirect Access Registers
C0 through C8 indirect registers.

Index Register Name

WSS Master Control (C0) C0 WSS Master Control
Default = 0xxxxxxx C1 Version / Chip ID
D7 D6 D5 D4 D3 D2 D1 D0 C2 3D Space and Volume
RWSS res res res res res res res C3 3D Enable
C4 Consumer Serial Port
res Reserved. Must write 0. Could read C5 Lower Channel Status
as 0 or 1. C6 Upper Channel Status
C7 Reserved
RWSS Reset WSS registers. Setting this bit
C8 CS9236 Wavetable Control
forces the WSS registers to zero,
then clearing this bit forces the WSS Table 23. Control Indirect Registers
registers to their default state.

Version / Chip ID (C1)

Default = 11001001
D7 D6 D5 D4 D3 D2 D1 D0
V2 V1 V0 CID4 CID3 CID2 CID1 CID0

CID4-CID0 Chip Identification. Distinguishes

between this chip and other codec
chips that support this register set.
This register is identical to the WSS
X25 register.

01001 - CS4238B

V2-V0 Version number. As enhancements

are made, the version number is
changed so software can distinguish
between the different versions of the
same chip.

101 - Revision B
110 - Revision C/D
111 - Revision E

DS215PP4 65
 CS4238B

3D Space and Volume (C2) Consumer Serial Port Enable (C4)

Default = 00100000 Default = 0000xxxx
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
SPC3 SPC2 SPC1 SPC0 3DV3 3DV2 3DV1 3DV0 CSPE CSBR U V res res res res

3DV3-3DV0 QXpander processed "Volume". res Reserved. Must write 0. Could read
The least significant bit represents as 0 or 1.
1.5 dB attenuation, with 0000=0 dB.
See Table 24. V The Validity bit in a sub-frame of
digital audio data.
SPC3-SPC0 QXpander processed "Space".
The least significant bit represents U The User bit in a sub-frame of digital
1.5 dB attenuation, with 0000=0 dB. audio data.
See Table 24.
CSBR Channel Status Block Reset. When
set, resets the channel status block
3D Enable (C3) boundary.
Default = 0x0xxxxx
D7 D6 D5 D4 D3 D2 D1 D0 CSPE Consumer Serial Port Enable. When
res res 3DSO QSEN res res res res set, the serial port output format con-
verts to the consumer standard for
res Reserved. Must write 0. Could read digital audio transmission, compat-
as 0 or 1. ible with the consumer portion of
IEC-958. An older version of the
QSEN QSound Enable. Must be set to 1 to standard is also called S/PDIF. Note
enable the QXpander 3D Sound that the serial port is still enabled us-
DSP. ing the SPE bit in WSS I16. For
more information on the consumer
3DSO 3D Serial Output. When set, SDOUT digital audio transmission format see
data comes from the DAC inputs Crystal’s Application Note 22 titled
which includes 3D effects. Typically Overview of Digital Audio Interface
used when CSPE in C4 is set and Data Structures.
determines the data used on the
Consumer Serial Port output pin.

0 - SDOUT from the ADCs.

1 - SDOUT from the QXpander DSP.

bit3 bit2 bit1 bit0 Space (SPC3-SPC0) 3D Volume (3DV3-3DV0)

0 0 0 0 0 0.0 dB 0.0 dB
1 0 0 0 1 -1.5 dB -1.5 dB
2 0 0 1 0 -3.0 dB -3.0 dB
3 0 0 1 1 -4.5 dB -4.5 dB
. . . . . - -
8 1 0 0 0 -12.0 dB -12.0 dB
. . . . . - -
12 1 1 0 0 -18.0 dB -18.0 dB
13 1 1 0 1 -19.5 dB -19.5 dB
14 1 1 1 0 -21.0 dB -21.0 dB
15 1 1 1 1 -22.5 dB -22.5 dB

Table 24. QXpander 3D Sound Control

66 DS215PP4
 CS4238B

Lower Channel Status (C5) Upper Channel Status (C6)

Default = xxxxxxxx Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
CS9 CS8 CS5 CS4 CS3 CS2 CS1 res CS25 CS24 CS15 CS14 CS13 CS12 CS11 CS10

res Reserved. Must write 0. Could read CS8-CS14 Category Code channel status bits.
as 0 or 1. Note that CS8 and CS9 are con-
tained in register C5. These bits
CS1 Channel Status bit 1: Audio. When define the type of product transmit-
clear, indicates that the transmitted ting and are used in the SCMS copy
data is digital audio and suitable for protection scheme to interpret the L
conversion to an analog signal. bit.

0 - Digital Audio 0000000 - General

1 - Non-Audio Data 0000001 - Experimental
0001xxx - Solid State Memory
CS2 Channel Status bit 2: Copy/Copyright 001xxxx - Broadcast
This bit, along with the L bit and the 010xxxx - Digital/Digital Converters
category codes, form the SCMS 01100xx - ADCs w/o copy protection
copy protection scheme. 01101xx - ADCs with copy protection
0111xxx - Broadcast
0 - copy inhibited/copyright asserted 100xxxx - Laser-Optical
1 - copy permitted/copyright not 101xxxx - Musical Instruments
asserted. 110xxxx - Magnetic Tape or Disk
111xxxx - Reserved.
CS4, CS3 Channel Status bits 4,3: Pre-emphasis
CS15 L or Generation Status. This bit
00 - None changes polarity based on the cate-
01 - 50/15µs - 2 channel audio gory codes above. For most
categories:
CS5 Channel Status bit 5: Lock
0 - No indication, 1st generation or
0 - Source Fs Locked higher.
1 - Source Fs Unlocked. 1 - Original/Commercially pre-
recorded data.
CS8, CS9 Lower two Category Code bits. See
the next register for a complete de- The above definition is reversed for
scription. category codes:
001xxxx - Broadcast
0111xxx - Broadcast
NOTE: More information on copy protection can 100xxxx - Laser-Optical
be found in the Sanchez AES paper titled An
CS25, CS24 Channel Status bits 25, 24. Sample
Understanding and Implementation of the SCMS frequency.
Serial Copy Management System for Digital
Audio Transmission. 00 - 44.1 kHz Sample Frequency.
This is the only Fs supported.

DS215PP4 67
 CS4238B

res Reserved. Must write 0. Could read

as 0 or 1.
Reserved (C7)
Default = xxxxxxxx
D7 D6 D5 D4 D3 D2 D1 D0 QSound 3D Sound Overview
res res res res res res res res
QSound Labs’ QXpander stereo enhancement is
res Reserved. Must write 0. Could read intended to provide a more realistic, more im-
as 0 or 1. mersive and thus more enjoyable listening
experience from any existing pre-mixed source
CS9236 Wavetable Control (C8) material auditioned over loudspeakers by broad-
Default = xxxx0000 ening the size of the perceived stereo image.
D7 D6 D5 D4 D3 D2 D1 D0 Sounds originate outside of the normal stereo
res res res res WTEN SPS DMCLK BRES sound field, drawing attention away from the
speakers as the true source of emission and thus
BRES Force BRESET low. When set, the creating a powerful impression of realism.
BRESET pin is forced low. Useful for
power management of peripherals.
The QXpander process from QSound Labs is
DMCLK Disable MCLK. When set, the MCLK based on the patented Q1TM technology used in
pin of the CS9236 Wavetable Syn- the world of professional recording, video games
thesizer serial interface is forced low and multimedia. The Q1 process was developed
providing a power savings mode. through intensive research activities and close
SPS DSP Serial Port Switch. When set,
collaboration with members of the professional
switches the DSP serial port pins recording industry.
from the 2nd joystick to the XD4-
XD1 pins. When SPE in I16 is set, The QXpander stereo expander was developed
XD4-XD1 convert to the DSP serial from the Q1 process with the addition of specific
port pins. Once SPS is enabled, the
SD<7:0> bus will not be driven when
architectural components designed to handle the
accesses occur to peripheral port de- unique requirements of stereo processing.
vices. SPS can also be set in the QXpander spatially expands any existing pre-re-
E2PROM Hardware Configuration corded stereo productions independent of
data, Global Configuration byte. recording encoding or lack of it.
WTEN Wavetable Serial Port Enable. When,
set, forces XD7-XD5 pins to convert QSound’s QXpander spatial enhancement is
to the CS9236 Single-Chip Wave- unique in that it can be enjoyed over extended
table Music Synthesizer serial port periods of time with no discomfort. The QXpan-
pins. Once WTEN is enabled, the der process does not cause any unnatural
SD<7:0> bus will not be driven when
pressure anomalies at the ear drums of the lis-
accesses occur to peripheral port de-
vices. WTEN can also be set in the tener that, while inaudible, may produce an
E2PROM Hardware Configuration uncomfortable feeling that fatigues the listener
data, Global Configuration byte. rather quickly.
Setting this bit also changes I6/I7
from master digital audio volume to
Additionally, the QXpander process differs from
ISA bus wave volume. X14/15 be-
come the master digital audio stereo and other enhancement algorithms in that
volume. it ‘centers’ the stereo expansion such that the full

68 DS215PP4
 CS4238B

expansion effect can be heard at a single listener sounds to the far left and the other places sounds
location without having to move from side to to the far right, beyond the positions of the
side to hear various audio images. physical speakers.

QXpander is a patented process that works with The left stereo input channel is applied to the
any existing stereo recorded material. QXpander left placement processor and the right channel
is not required in the recording process. This connects to the right placement processor. The
means a listener’s entire audio library can be en- amount of processed signal summed into the out-
hanced by QXpander by simply playing it puts can be increased using SPC3-0 to increase
through the CS4238B Crystal chip. Like stereo, the expansion effect. These outputs are summed
any two-speaker stereo system is adequate. internally such that the output is a single two-
channel stereo mix.
Other notable features of Crystal’s CS4238B
QXpander DSP include: Built around the two processors is a special net-
work that allows mono (equal in both channels)
• Elements of the stereo image that are widely information to bypass both processors and be re-
placed in the original stereo mix will appear well combined with the output. Without this
beyond the physical speaker positions, at the pe- arrangement, mono information would be ap-
riphery of the new QSpaceTM sound field. plied, unattenuated, to both left and right
modified Q1 processors, creating undesirable
• The remaining elements of the mix will appear side effects.
in the same relative positions as in the original
source material, but will be expanded propor- QXpander Space Control
tionately. The QXpander Space adjustment, SPC3-0 in C2,
controls the digital output levels from the modi-
• Mono (center) information will remain solid, fied Q1 processors. These outputs contain the
natural-sounding, and properly positioned. spatial information that allows us to perceive
sounds from coming all around and the direc-
• Correct loudness balance of the various sounds tional cues that we use to determine the
in a recording are maintained. localization of those sounds.
• Provides excellent imaging of panned sounds. Turning up the Space control increases the
amount of processed directional information, re-
• Correct frequency content compared to the stores the proper localization of the original
original recording is maintained. sounds, and expands the width of the overall
sound stage. Turning down the Space control at-
The QXpander 3D Stereo Process tenuates the processed signal components and
The patented QSound QXpander architecture es- thus limits the intensity of these effects.
sentially consists of a pair of modified Q1
localization processors with a special mono-han- QXpander 3D sound is enabled by setting QSEN
dling network as illustrated in Figure 7. in C3 to 1. Although proper listening levels are
subjective and program dependent, QSound Labs
The two modified Q1 processors are configured has found that subtler settings are better suited to
to locate sounds on opposite sides: one places

DS215PP4 69
 CS4238B

high fidelity applications such as music listening, Unfortunately there is no universal 3D algorithm
whereas more extreme settings are ideal for that is equally effective in both cases. QXpander,
video games. as implemented in the CS4238B Crystal chip, is
designed for speaker listening. Auditioning
The QXpander algorithm requires a stereo input QXpander-processed material over headphones is
in order to produce spatially broadened output. If in no way objectionable except that the expan-
adjusting the Space control yields no change in sion effect is lost.
the sound image, the input signal is probably
mono. QSound Virtual Audio Guide to Optimal
Listening
QXpander 3D Volume Control
These guidelines will help you get the maximum
The QXpander 3D Volume adjustment, 3DV3-0 enjoyment from your stereo system. Since
in C2, determines the overall level of the final QXpander is a stereo process, the following will
left and right digital signals going to the DACs. provide optimum results from Qsound Virtual
Audio. The aim of the following suggestions is
Speakers vs. Headphones simply to set up the playback system symmetri-
Most audio parameters relating to timbre, rela- cally, so that both left and right speakers are
tive volume, etc. are considered essentially similarly arranged.
equivalent on speakers and headphones. 3D
audio is somewhat unique in this respect. This • Both speakers should be placed at the same
uniqueness is a result of the mechanics of sound distance from the listening position.
location in human listeners and the fact that the
transfer of sound from the transducers to the lis- • Both speakers should be at the same angle,
tener’s ears is characterized by significant (Facing straight forward or turned slightly to-
differences between loudspeaker and headphone ward the listening position; whichever is
listening. preferred.) and same height.

Modified L
Σ
L
Q1
Filter
Master Digital

SPC3-0 3DV3-0 Stereo

L to
Volume

Digital Monaural 16-bit Analog

Mixer Network QSEN ∆-Σ Mixers
R
DAC

Σ
R Modified
Q1
Filter R
SPC3-0 3DV3-0

Figure 7. QXpander Block Diagram

70 DS215PP4
 CS4238B

• The speakers should not be too far apart. The SDOUT pin can either be on joystick B’s
For example, in a multimedia setup, they CX pin or it can be on the peripheral port data
should be just to either side of the video bus pin XD3, controlled by the SPS bit in the
monitor. Hardware Configuration data or register C8.

• If the system has a balance control, it The data going out SDOUT can come from the
should be centered. If, on the other hand, ADC or from the DAC interface (which includes
each speaker has its own volume control, QSound 3D Sound if enabled). This functionality
they should be adjusted so that the speakers is controlled by the 3DSO bit in register C3.
are as closely matched in relative volume as
possible. For the receiving device to function properly, the
Channel Status bits in C5 and C6 must be set
• The speakers must be in phase. Most multi- properly. See the Sanchez AES paper An Under-
media speakers use connectors that standing and Implementation of the SCMS Serial
automatically ensure proper phasing, but Copy Management System for Digital Audio
some systems (e.g. home stereos) having Transmission for more details on setting the
separate speakers and amplifier use two ter- Channel Status information.
minals for each connection point. Care
should be taken to make sure the phasing is Figure 8 illustrates the circuit necessary for im-
correct. plementation of the IEC-958 consumer interface.
An external buffer is required to drive the cur-
Although stereo imaging can be heard off axis, rent needed to drive the 75 Ω interface (415 Ω
the best listening location for stereo effects, in- or 12 mA).
cluding dramatic sound stage broadening, is
centered between the speakers. By properly con- 374 Ω
figur ing the playback system, maximum SDOUT
enjoyment of the QSound QXpander audio en- RCA
hancement, built into the CS4238B Advanced 90.9 Ω
Phono
Audio System, can be achieved.

Consumer IEC-958 Digital Output

The CS4238B supports the industry standard Figure 8. IEC-958 Consumer Interface
IEC-958 consumer digital interface. Sometimes
this standard is referred to S/PDIF which refers
to an older version of this standard. This output The transformers can be obtained from:
provides an interface, external to the PC, for Pulse Engineering
storing digital audio (as in a DAT or recordable Telecom Products Group
CD-ROM) or playing digital audio from digital San Diego, CA
speakers. (619) 268-2400
or
The interface is enabled by turning on the CSPE Schott Corporation
bit in C4 and SPE in I16. The data is sent out Wayzata, MN
the SDOUT DSP serial interface pin. The other (612) 475-1173
DSP serial interface pins still function properly
when SDOUT is used for the IEC-958 interface.

DS215PP4 71
 CS4238B

MPU-401 INTERFACE All MIDI transmit data is transferred through a

16-byte FIFO and receive data through a 16-byte
The MPU-401 is an intelligent MIDI interface
FIFO. The FIFO gives the ISA interface time to
that was introduced by Roland in 1984. Voyetra
respond to the asynchronous MIDI transfer rate
Technologies subsequently introduced an IBM-
of 31.25K baud.
PC plug in card that incorporated the MPU-401
functionality. The MPU-401 has become the de-
The Command/Status Registers occupy the same
facto standard for controlling MIDI devices via
address and are used to send instructions to and
IBM-PC compatible personal computers.
receive status information from the MPU-401.
Although the MPU-401 does have some intelli-
Command Register, write only
gence, a non-intelligent mode is available in
MPUbase+1
which the MPU-401 operates as a basic UART.
D7 D6 D5 D4 D3 D2 D1 D0
CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0
By incorporating hardware to emulate the MPU-
401 in UART mode, MIDI capability is CS7-CS0 Each write to the Command/Status
supported. Register must be monitored and the
appropriate acknowledge generated.
MPU-401 Register Interface
Status Register, read only
The MPU401 logical device software interface
MPUbase+1, Default = xxxxxxxx
occupies 2 I/O locations, utilizes 10-bit address
D7 D6 D5 D4 D3 D2 D1 D0
decoding, and is located at PnP address RXS TXS CS5 CS4 CS3 CS2 CS1 CS0
’MPUbase’. 10-bit addressing requires that the
upper address bits be 0 to decode a valid ad- CS5-CS1 D0-D5 are the 6 LSBs of the last
dress, i.e. no aliasing occurs. The standard base command written to this port.
address is 330h. This device also uses an inter-
rupt, typically 9. The PnP alignment for the TXS Transmit Buffer Status Flag.
MPU-401 must be a multiple of 8.
0 - Transmit buffer not full
1 - Transmit buffer full
MPUbase+0 is the MIDI Transmit/Receive port
and MPUbase+1 is the Command/Status port. In RXS Receive Buffer Status Flag
addition to I/O decodes the only additional func-
tionality required from an ISA bus viewpoint is 0 - Data in Receive buffer
1 - Receive buffer empty
the generation of a hardware interrupt whenever
data has been received into the receive buffer.
When in "UART" mode, data is received into the
MIDI Transmit/Receive Port, receive buffer FIFO and a hardware interrupt is
MPUbase+0, default = xxxxxxxx generated. Data can be received from two
D7 D6 D5 D4 D3 D2 D1 D0 sources: MIDI data via the UART serial input or
TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0 acknowledge data that is the result of a write to
the Command Register (MPUbase+1). The inter-
TR7-TR0 The MIDI Transmit/Receive Port is
used to send and receive MIDI data
rupt is cleared by a read of the MIDI Receive
as well as status information that Port (MPUbase+0).
was returned from a previously sent
command.

72 DS215PP4
 CS4238B

UART mode operation is defined as follows:

MIDI UART
The UART is used to convert parallel data to the 1. All writes to the Transmit Port, MPUbase+0,
serial data required by MIDI. The serial data rate are placed in the transmit buffer FIFO.
is fixed at 31.25K baud (±1%). The serial data Whenever the transmit buffer FIFO is not
format is RS-232 like: 1 start bit, 8 data bits, and empty, the next byte is read from the buffer
1 stop bit. and sent out the MIDOUT pin. The Status
Register, MPUbase+1, bit 6, TXS is updated
In multimedia systems, the MIDI pins are typi- to reflect the transmit buffer FIFO status.
cally connected to the joystick connector. See the
Reference Design Data Sheet for detailed infor- 2. All reads of the Receive Port, MPUbase+0,
mation. return the next byte in the receive buffer
FIFO. When serial data is received from the
MIDIN pin, it is placed in the next receive
MPU-401 "UART" Mode Operation
buffer FIFO location. If the buffer is full,
After power-up reset, the interface is in "non- the last location is overwritten with the new
UART" mode. Non-UART mode operation is data. The Status Register, MPUbase+1,
defined as follows: bit 7, RXS is updated to reflect the new re-
ceive buffer FIFO state.
1. All writes to the Transmit Port, MPUbase+0,
are ignored. 3. A write to the Command Register,
MPUbase+1, of FFh will return the interface
2. All reads of the Receive Port, MPUbase+0, to non-UART mode.
return the last received buffer data.
4. All other writes to the Command Register,
3. All writes to the Command Port, MPUbase+1, MPUbase+1, are ignored.
are monitored and acknowledged as follows:
a. A write of 3Fh sets the interface into FM SYNTHESIZER (Internal)
UART operating mode. An acknowledge
is generated by putting an FEh into the This part contains a games-compatible internal
receive buffer FIFO which generates an FM synthesizer. When enabled, this internal FM
interrupt. synthesis engine responds to both the SBPro FM
synthesis addresses as well as the SYNbase ad-
b. A write of A0-A7, ABh, ACh, ADh, AFh dresses.
places an FEh into the receive buffer
FIFO (which generates an interrupt) fol- To enable the internal FM synthesis engine, the
lowed by a one byte write to the receive IFM bit in the Hardware Configuration data,
buffer FIFO of 00h for A0-A7, and ABh byte 8 (Global Configuration Byte) must be set.
commands, 15h for ACh, 01h for ADh, This bit is also available in WSS register X4.
and 64h for AFh commands.
Volume control for the internal FM synthesizer is
c. All other writes to the Command Port are
supported through X6 and X7 in the WSS ex-
ignored and an acknowledge is gener-
tended register space. The volume range is 0 dB
ated by putting an FEh into the receive
to -94.4 dB with 000000 equal to 0 dB. After
buffer FIFO which generates an interrupt.

DS215PP4 73
 CS4238B

volume is applied to the PCM FM data, it is as the Yamaha OPL3LS, or the Crystal Semicon-
summed into the digital mixer which is then ductor CS9233 wave-table synthesizer chip. This
summed into the analog output mixer. interface consists of:

For backwards compatibility with analog-mixed SCS - chip select

external FM devices, I18 and I19 in the WSS SINT - Synthesizer Interrupt
logical device can be remapped to control the
volume of internal FM. Remapping is controlled The other signals such as address bits, data
through the FMRM bit in X4 register. When strobes, data, and reset are provided by the Ex-
IFM = 1, and FMRM = 1, writes to I18 and I19 ternal Peripheral Port. The interface allows the
are remapped to X6 and X7 respectively. When host computer to access up to eight I/O mapped
remapping is enabled, the LINE analog input locations. When using an external FM synthe-
volume is controlled through X0/1. When sizer, SCS will respond to the SYNbase decode
FMRM = 0, internal FM volume is only control- addresses as well as the SBPro mapped FM syn-
led through X6/7. thesizer addresses. The PnP synthesizer
alignment must be a multiple of 8.
The synthesizer interface is compatible with the
Adlib and Sound Blaster standards. The typical The polarity of SINT is programmable via Hard-
Adlib I/O address is SYNbase = 388h. ware Configuration data, IHS in byte 7, or
through CTRLbase+1. The default is active low
Standard Adlib Synthesizer I/O Map (IHS = 0).
Address Name Type
SYNbase+0 FM Status Read Only Since the typical FM interface only requires four
SYNbase+0 FM Address 0 Write Only I/O address and does not use an interrupt, the
SYNbase+1 FM Data 0 Write Only XA2 address and the SINT pins are multifunc-
SYNbase+2 FM Address 1 Write Only tion pins that default to XCTL0 and XCTL1. To
SYNbase+3 FM Data 1 Read Only use XCTL0/XA2 as an address pin, the hardware
resource data must be changed. See the Hard-
EXTERNAL PERIPHERAL PORT ware Configuration Data section for more
An external peripheral port is provided for inter- information. To use XCTL1/SINT/ACDCS/
facing devices external to the part. These may DOWN as an interrupt for the synthesizer,
include the CS9233 Wavetable synthesizer, VCEN (in the Hardware Configuration data)
CDROM interface, modem interface, and Plug must be zero, a pulldown resistor must be placed
and Play E2PROM. on the XIOW pin. Since XCTL1 and SINT are
rarely used the pin has a third multiplexed func-
The External Peripheral Port consists of the fol- tion, ACDCS, which is described in the
lowing signals: 8-bit data bus, 2 or 3 address CDROM section below. The fourth multiplexed
lines, read strobe, write strobe, and reset signal. function is the hardware volume control pin
DOWN which is controlled through the VCEN
External Synthesizer Interface bit. See the Volume Control Interface section for
more details. Note that ACDCS takes precedence
This part contains an internal FM synthesis en-
over XCTL1/SINT. Also DOWN, when VCEN is
gine. For backwards compatibility the default is
set, takes precedence over all other functions.
to use an external FM-type synthesizer chip such

74 DS215PP4
 CS4238B

from one to eight bytes. The default is 1 byte. In

CDROM Interface legacy IDE CDROM drives, the alternate
An IDE CDROM controller interface is provided CDROM address plus 1, ACDbase+1, is typi-
that supports Enhanced as well as Legacy IDE cally shared with the floppy controller, which
CDROM drives. This interface includes two pro- only drives data bit 7. Therefore, a bit in the
grammable chip selects and on-chip hardware to Hardware Configuration data keeps the SD7 pin
map DMA and interrupt signals to the ISA bus. from driving data bit 7 when that address is de-
coded. This bit is labeled ACDB7D and is
There are five pins that make up the CDROM located in the Hardware Configuration data, byte
interface which consist of: 7. When using ACDCS, the SINT function
should be selected and a pullup placed on this
CDCS - chip select, COMbase address line, which will allow this pin to powerup inac-
CDINT - interrupt, COMint tive. If XCTL1 is selected, it will powerup low;
CDRQ - DMA request, COMdma therefore, ACDCS will be low until ACDbase is
CDACK - DMA acknowledge, COMdma programmed to a non-zero value.
ACDCS - alternate chip select, ACDbase
The default address space for the peripheral port
The four basic CDROM interface pins are multi- is 4 I/O locations where XCTL0/XA2 defaults to
function pins that default to the upper address the control pin XCTL0. To use XCTL0/XA2 as
bits SA12 - SA15. To use the pins as a CDROM the XA2 address pin, thereby increasing the ad-
interface, a pulldown resistor must be placed on dress range of the peripheral port to 8 locations,
XIOR (XIOR must be buffered if driving TTL the hardware resource data must be changed. See
logic). Once the CDROM interface is selected, the Hardware Configuration Data section. Even
the CDROM DMA pins are further multiplexed though the default address space is only 4 loca-
with the Modem pins. Therefore, a fifth logical tions, the alignment for CDbase must be a
device, typically a modem, can be used if the division of 8.
CDROM doesn’t support DMA. See the Modem
Interface section for more details. To make the CDROM interface more flexible,
two global bits, located in the Hardware Con-
The fifth CDROM pin ACDCS is multiplexed figuration data section - byte 7, allow control
with XCTL1/SINT/DOWN. This chip select sup- over the polarity of the CDROM interrupt pin
ports the alternate CDROM chip select used for CDINT, and whether the SD<7-0> pins drive the
status in legacy IDE drives. The volume control ISA bus or not. The first bit is IHC which de-
pin DOWN has the highest precedence; there- faults to 1 indicating that CDINT is an active
fore, the VCEN bit must be zero to use this pin high interrupt. IHC is also controllable through
for the CDROM interface. Given that VCEN is CTRLbase+1. The second bit is SDD - SD<7:0>
zero, if the base address for ACDCS, which is bus Disable. When this bit is set, the part will
ACDbase, is programmed to a non-zero value, not drive the ISA Data bus SD<7:0> pins, on
this pin converts to ACDCS. ACDbase, base ad- reads from either CDbase or ACDbase addresses.
dress 1 in LD4, is programmed via PnP or via This bit allows external data buffers to be used for
the SLAM method. Once this pin is set to a CDROM that bypasses the XD<7:0> bus and
ACDCS, the only way to revert to XCTL1 or connects directly to the ISA bus. Note that SDD
SINT is to reset the part. The range of addresses affects any peripheral port device which includes
that ACDCS will respond to is programmable the external FM and modem interfaces.
via the Hardware Configuration data, byte 5,

DS215PP4 75
 CS4238B

to the DSP serial port when SPE is set (MCE

Modem Interface must be 1 to change SPE). If SPS is 1, XD<4:1>
The modem interface, Logical Device 5 (LD5) convert to the DSP serial port when SPE is set.
consist of: In this case, SD<7:0> is disabled on reads of pe-
ripheral port addresses (CDROM, modem, etc.)
MCS - Modem Chip Select since XD<7:0> is no longer available.
MINT - Modem Interrupt
The DSP audio serial port is software enabled
The other signals such as address bits, data via the SPE bit in the WSS Codec indirect regis-
strobes, data, and reset are provided by the Ex- ter I16. The ISA interface is fully active in this
ternal Peripheral Port. The interface allows the mode. While the serial port is enabled, audio
host computer to access up to eight I/O mapped data may still be read from the ADCs over the
locations. ISA bus, and the DACs will sum data from the
SDIN pin, the parallel ISA bus data, and the in-
The Modem signals are multiplexed with both ternal FM synthesizer engine. The serial port
the upper ISA address pins, and the CDROM sample frequency is always 44.1 kHz regardless
DMA pins. To enable the Modem, first a pull- of the ISA bus sample frequency, and the data
down resistor must be placed on XIOR which format is always two’s complement 16-bit linear.
disables the upper ISA address pins. Second, the
Modem base address, COMbase, must be pro- FSYNC and SCLK are always output from the
grammed to a non-zero value which will convert part when the serial port is enabled. The serial
the SA13/CDACK/MCS pin to the modem chip port can be configured in one of four serial port
select MCS, and the SA15/CDRQ/MINT pin to formats, shown in Figures 9-12. SF1 and SF0 in
the modem interrupt pin MINT. Once these two I16 select the particular format. MCE in R0 must
pins switch to modem pins, they can only be be set to change SF1/0. Both left and right audio
changed by resetting the part. COMbase, Logical words are always 16 bit two’s complement.
Device 5 base address 0, is programmed via PnP When the mono audio format is selected, the
or the SLAM method. right channel output is set to zero and the left
channel input is summed to both DAC channels.
The polarity of MINT is programmable via
Hardware Configuration data, IHM in byte 7, or The first format - SPF0, shown in Figure 9, is
through CTRLbase+1. The default is active low called 64-bit enhanced. This format has 64
(IHM = 0). SCLKs per frame with a one bit period wide
FSYNC that precedes the frame. The first 16 bits
DSP SERIAL AUDIO DATA PORT occupy the left word and the second 16 bits oc-
cupy the right word. The last 32 bits contain four
The WSS Codec includes a DSP serial audio in- status bits and 28 zeros. This is the only mode
terface for transferring digital audio data that contains status information.
between the part and an external serial device
such as a DSP processor. The DSP serial port The second serial format - SPF1, shown in Fig-
pins are multiplexed with either the #2 joystick ure 10, is called 64-bit mode. This format has 64
inputs of the Game Port interface or a portion of SCLKs per frame, with FSYNC high transitions
the XD peripheral bus. The selection is made via at the start of the left data word and low transi-
the SPS bit located in Control register C8, or the tions at the start of the right data word. Both the
Global Config. byte in the Hardware Configura- left and right data words are followed by 16 ze-
tion data. If SPS is 0, the joystick B pins convert ros.
76 DS215PP4
 CS4238B

FSYNC

SCLK ...

SDOUT 15 14 13 12 ... 0 15 14 ... 0 8 zeros INT 7 zeros CEN PEN OVR 13 zeros

16 Bits 16 Bits 32 Bits

Left Data Right Data

SDIN 15 14 13 12 ... 0 15 14 ... 0

16 Bits 16 Bits INT = Interrupt Bit

Left Data Right Data CEN = Capture Enable
PEN = Playback Enable
OVR = Left Overrange or
Right Overrange

Figure 9. 64-bit Enhanced Mode (SF1,0 = 00)

FSYNC

SCLK ... ...

SDOUT/ 15 14 13 ... 0 15 14 13 ... 0 15

SDIN
16 Clocks 16 Clocks 16 Clocks 16 Clocks
Left Data Right Data
Figure 10. 64-bit Mode (SF1,0 = 01)

FSYNC

SCLK ... ... 32 No-Clock bit periods

SDOUT/ 15 14 13 ... 0 15 14 13 ... 0 15 14

SDIN ...

16 Clocks 16 Clocks
Left Data Right Data Left Data

Figure 11. 32-bit Mode (SF1,0 = 10)

DS215PP4 77
 CS4238B

The third serial format - SPF2, shown in Fig- ADC and DAC data on the SDOUT allows ex-
ure 11, is called 32-bit mode. This format has 32 ternal modem DSPs to cancel the local audio
SCLKs per frame and FSYNC is high for the source from the local microphone signal.
left channel and low for the right channel. The
absolute time is similar to the other two modes CS9236 WAVETABLE SERIAL PORT
but SCLK is stopped after the right channel is A digital interface to the Crystal CS9236 Single-
finished. SCLK is held stopped until the start of Chip Wavetable Music Synthesizer is provided
the next frame (stopped for 32 bit period times). that allows the CS9236 PCM audio data to be
This mode is useful for DSPs that do not want summed digitally into the output digital mixer.
the interrupt overhead of the 32 unused bit peri- The Wavetable Serial port pins are multiplexed
ods. As an example, if a DSP serial word length with the XD7-XD5 external bus pins; therefore,
is 16 bits, then four interrupts will occur in SPF0 when this serial interface is enabled, any external
and SPF1 modes. In mode SPF2 the DSP will peripheral (CDROM, modem, etc.) will need an
only be interrupted twice. external buffer to the ISA bus. This serial port is
enabled via the WTEN bit located in Control
The fourth serial format - SPF3, shown in Fig- register C8 or in the Global Configuration byte
ure 12, is called ADC/DAC mode. This format in the Hardware Configuration data. The hard-
has 64 SCLKs per frame, with FSYNC high ware connections to the CS9236 are illustrated in
transitions at the start of the left ADC data word Figure 13.
and low transitions at the start of the right ADC
data word. For serial data in, SDIN, both the left Volume control for the serial port is supported
and right 16-bit DAC data word should be fol- through X16 and X17 in the WSS extended reg-
lowed by zeros. For serial data out, SDOUT, ister space. The volume range is +12 dB to
both the left and right ADC data words are fol- -82.5 dB with 001000 equal to 0 dB. After vol-
lowed by 16 bits of the DAC data words. The ume is applied to the PCM data, it is summed
DAC data words are tapped off the data stream into the digital mixer which is then summed into
right before the data enters the Codec DACs (af- the analog output mixer.
ter all digital summing is done). Having the

FSYNC

SCLK ... ...

SDIN 15 14 13 ... 0 15 14 13 ... 0 15

DAC 16 Clocks DAC 16 Clocks

SDOUT 15 14 13 ... 0 15 14 13 ... 0 15 14 13 ... 0 15 14 13 ... 0 15

ADC 16 Clocks DAC 16 Clocks ADC 16 Clocks DAC 16 Clocks

Left Data Right Data

Figure 12. ADC/DAC Mode (SF1,0 = 11)

78 DS215PP4
 CS4238B

For backwards compatibility with analog-mixed

wavetable devices, I18 and I19 in the WSS logi- Calibration
cal device can be remapped to control the The WSS Codec has four different calibration
volume of the Wavetable serial port. Remapping modes. The selected calibration occurs whenever
is controlled through the WTRMD bit in X4 reg- the Mode Change Enable (MCE, R0) bit goes
ister. When WTEN = 1, and WTRMD = 0, form 1 to 0.
writes to I18 and I19 are remapped to X16 and
X17 respectively. When remapping is enabled, The completion of calibration can be determined
the LINE analog input volume is controlled by polling the Auto-Calibrate In-Progress bit in
through X0/1. When WTRMD = 1, the the Error Status and Initialization register (ACI,
Wavetable Serial Port volume is only controlled I11). This bit will be high while the calibration is
through X16/17. in progress and low once completed. Transfers
CS9236 enabled during calibration will not begin until
100 Ω
MCLK
the calibration cycle has completed. Since the
MCLK5I
part always operates at 44.1 kHz internally, all
LRCLK LRCLK calibration times are based on 44.1 kHz sample
SDATA SOUT periods.
BRESET RST The Calibration procedure is as follows:
PDN
100k Ω 100k Ω
1) Place the WSS Codec in Mode Change
MIDOUT MIDI_IN
Enable using the MCE bit of the Index Ad-
MIDIN XTAL3I dress register (R0).

2) Set the CAL1,0 bits in the Interface Configura-

Midi In Midi Out tion register (I9).
Joystick Connector
3) Return from Mode Change Enable by reset-
Figure 13. CS9236 Wavetable Serial Port Interface ting the MCE bit of the Index Address
register (R0).
WSS CODEC SOFTWARE DESCRIPTION 4) Wait until 80h NOT returned
The WSS Codec must be in Mode Change En-
able Mode (MCE=1) before any changes to the 5) Wait until ACI (I11) cleared to proceed
Interface Configuration register (I9) or the Sam-
ple Frequency (lower four bits) in the Fs & NO CALIBRATION (CAL1,0 = 00)
Playback Data Format registers (I8) are allowed. This is the fastest mode since no calibration is
The actual audio data formats, which are the up- performed. This mode is useful for games which
per four bits of I8 for playback and I28 for require the sample frequency be changed
capture, can be changed by setting MCE (R0) or quickly. This mode is also useful when the codec
PMCE/CMCE (I16) high. The exceptions are is operating full-duplex and an ADC data format
CEN and PEN which can be changed "on-the- change is desired. This is the only calibration
fly" via programmed I/O writes. All outstanding mode that does not affect the DACs (i.e. mute
DMA transfers must be completed before new the DACs). The No Calibration mode takes zero
values of CEN or PEN are recognized. sample periods.

DS215PP4 79
 CS4238B

CONVERTER CALIBRATION (CAL1,0 = 01) Changing Sampling Rate

This calibration mode calibrates the ADCs and The internal states of the WSS Codec are syn-
the DACs, but does not calibrate any of the ana- chronized by the selected sampling frequency.
log mixing channels. This is the second longest The sample frequency can be set in one of three
calibration mode, taking 321 sample periods at fashions. The standard WSS Codec method uses
44.1 kHz. Because the analog mixer is not cali- the Fs & Playback Data Format register (I8) to
brated in this mode, any signals fed through the set the sample frequency. The changing of either
mixer will be unaffected. The calibration se- the clock source or the clock frequency divide
quence is as follows: requires a special sequence for proper WSS
The DACs are muted Codec operation:
The ADCs are calibrated
The DACs are calibrated 1) Place the WSS Codec in Mode Change En-
The DACs are unmuted able using the MCE bit of the Index Address
register (R0).
DAC CALIBRATION (CAL1,0 = 10)
This calibration mode only clears the DACs 2) During a single write cycle, change the Clock
(playback) interpolation filters leaving the ADC Frequency Divide Select (CFS) and/or
unaffected. This is the second fastest calibration Clock 2 Base Select (C2SL) bits of the Fs &
mode (no cal. is the fastest) taking 120 sample Playback Data Format register (I8) to the de-
periods at 44.1 kHz to complete. The calibration sired value. (The data format may also be
sequence is as follows: changed.)
The DACs are muted
The DAC filters are cleared 3) The WSS Codec resynchronizes its internal
The DACs are unmuted states to the new frequency. During this time
the WSS Codec will be unable to respond.
FULL CALIBRATION (CAL1, 0 = 11) Writes to the WSS Codec will not be recog-
nized and reads will always return the value
This calibration mode calibrates all offsets, 80 hex.
ADCs, DACs, and analog mixers. Full calibra-
tion will automatically be initiated on power up 4) The host now polls the WSS Codec’s Index
or anytime the WSS Codec exits from a full Address register (R0) until the value 80 hex
power down state. This is the longest calibration is no longer returned. On slow processor sys-
mode and takes 450 sample periods at 44.1 kHz tems, 80h may occur to fast; therefore, it
to complete. The calibration sequence is as fol- may never be seen by software.
lows:
All outputs are muted (DACs and mixer) 5) Once the WSS Codec is no longer responding
The mixer is calibrated to reads with a value of 80 hex, normal op-
The ADCs are calibrated eration can resume and the WSS Codec can
The DACs are calibrated be removed from MCE.
All outputs are unmuted
A second method of changing the sample fre-
quency is to disable the sample frequency bits in
I8 (lower four bits) by setting SRE in I22. When
this bit is set, OSM1 and OSM0 in I10, along

80 DS215PP4
 CS4238B

with the rest of the bits in I22, are used to set the The WSS Codec always orders the left channel
sample frequency. Once enabled, these bits can data before the right channel. Note that these
be changed without doing an MCE cycle. definitions apply regardless of the specific for-
mat of the data. For example, 8-bit linear data
The third method supports independent sample streams look exactly like 8-bit companded data
frequencies (Fs) for capture and playback. The streams. Also, the left sample always comes first
independent sample frequency mode is enabled in the data stream regardless of whether the sam-
by setting IFSE in X11. Once enabled, the other ple is 16-bit or 8-bit in size.
two methods for setting Fs (I8, I10, and I22) are
disabled. The capture (ADC) Fs is set in X12 There are four data formats supported by the
and the playback (DAC) Fs is set in X13. WSS Codec during MODE 1 operation: 16-bit
signed (little endian), 8-bit unsigned, 8-bit com-
Changing Audio Data Formats panded µ-Law, and 8-bit companded A-Law.
In MODE 1, MCE must be used to select the See Figures 14-17.
audio data format in I8. Since MCE causes a
calibration cycle, it is not ideal for full-duplex Additional data formats are supported in MODE
operation. In MODE 2 and 3, individual Mode 2 and 3: 4-bit ADPCM, and 16-bit signed Big
Change Enable bits for capture and playback are Endian. See Figures 18 through 21. With the ad-
provided in register I16. MCE (R0) must still be dition of the Big Endian and ADPCM audio data
used to select the sample frequency, but PMCE formats, the WSS Codec is compliant with the
(playback) and CMCE (capture) allow changing IMA recommendations for digital audio data for-
the respective data formats without causing a mats (and sample frequencies).
calibration to occur. Setting PMCE (I16) clears
the playback FIFO and allows the upper four 16-BIT SIGNED
bits of I8 to be changed. Setting CMCE (I16) The 16-bit signed format (also called 16-bit 2’s
clears the capture FIFO and allows the upper complement) is the standard method of repre-
four bits of I28 to be changed. senting 16-bit digital audio. This format gives
96 dB theoretical dynamic range and is the
Audio Data Formats standard for compact disk audio players. This
In MODE 1 operation, all data formats of the format uses the value -32768 (8000h) to repre-
WSS Codec are in "little endian" format. This sent maximum negative analog amplitude, 0 for
format defines the byte ordering of a multibyte center scale, and 32767 (7FFFh) to represent
word as having the least significant byte occupy- maximum positive analog amplitude.
ing the lowest memory address. Likewise, the
most significant byte of a little endian word oc- 8-BIT UNSIGNED
cupies the highest memory address. The 8-bit unsigned format is commonly used in
the personal computer industry. This format de-
The sample frequency is always selected in the livers a theoretical dynamic range of 48 dB. This
Fs & Playback Data Format register (I8). In format uses the value 0 (00h) to represent maxi-
MODE 1 the same register, I8, determines the mum negative analog amplitude, 128 for center
audio data format for both playback and capture; scale, and 255 (FFh) to represent maximum
however, in MODE 2 and 3, I8 only selects the positive analog amplitude. The 16-bit signed and
playback data format and the capture data format 8-bit unsigned transfer functions are shown in
is independently selectable in the Capture Data Figure 22.
Format register (I28).

DS215PP4 81
 CS4238B

32-bit Word Time

sample 6 sample 5 sample 4 sample 3 sample 2 sample 1

MONO MONO MONO MONO

31 24 23 16 15 8 7 0

Figure 14. 8-bit Mono, Unsigned Audio Data

32-bit Word Time

sample 3 sample 3 sample 2 sample 2 sample 1 sample 1

RIGHT LEFT RIGHT LEFT

31 24 23 16 15 8 7 0

Figure 15. 8-bit Stereo, Unsigned Audio Data

32-bit Word Time

sample 6 sample 5 sample 4 sample 3 sample 2 sample 1

MONO MONO
31 24 23 16 15 8 7 0

Figure 16. 16-bit Mono, Signed Little Endian Audio Data

32-bit Word Time

sample 3 sample 3 sample 2 sample 2 sample 1 sample 1

RIGHT LEFT
31 24 23 16 15 8 7 0

Figure 17. 16-bit Stereo, Signed Little Endian Audio Data

82 DS215PP4
 CS4238B

32-bit Word Time

sample 8 sample 7 sample 6 sample 5 sample 4 sample 3 sample 2 sample 1

MONO MONO MONO MONO MONO MONO MONO MONO

31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0

Figure 18. 4-bit Mono, ADPCM Audio Data

32-bit Word Time

sample 4 sample 4 sample 3 sample 3 sample 2 sample 2 sample 1 sample 1

RIGHT LEFT RIGHT LEFT RIGHT LEFT RIGHT LEFT

31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0

Figure 19. 4-bit Stereo, ADPCM Audio Data

32-bit Word Time

sample 4 sample 4 sample 3 sample 3 sample 2 sample 2 sample 1 sample 1

MONO LO MONO HI MONO LO MONO HI

23 16 31 24 7 0 15 8

Figure 20. 16-bit Mono, Signed Big Endian Audio Data

32-bit Word Time

sample 2 sample 2 sample 2 sample 2 sample 1 sample 1 sample 1 sample 1

RIGHT LO RIGHT HI LEFT LO LEFT HI

23 16 31 24 7 0 15 8

Figure 21. 16-bit Stereo, Signed Big Endian Audio Data

DS215PP4 83
 CS4238B

on the specifics of the format, contact the IMA

8-BIT COMPANDED at (410) 626-1380. Figures 18 and 19 illustrate
The 8-bit companded formats (A-Law and µ- the ADPCM data flow.
Law) come from the telephone industry. µ-Law
The ADPCM format is unique with respect to
is the standard for the United States/Japan while
the FIFO depth and the DMA Base register
A-Law is used in Europe. Companded audio al-
value. The ADPCM format fills the FIFOs com-
lows either 64 dB or 72 dB of dynamic range
pletely (64 bytes); therefore, the FIFOs hold 64
using only 8-bits per sample. This is accom-
stereo samples and 128 mono samples. When
plished using a non-linear companding transfer
samples are being transferred using DMA, the
function which assigns more digital codes to
DMA request stays active for four bytes, similar
lower amplitude analog signals with the sacrifice
to the 16-bit stereo data mode. In PIO mode, the
of precision on higher amplitude signals. The µ- Status register (R2) indicates which of the four
Law and A-Law formats of the WSS Codec bytes is being transferred.
conform to the CCITT G.711 specifications. Fig-
ure 23 illustrates the transfer function for both When CEN is 0 (capture disabled), the ADPCM
A- and µ-Law. Please refer to the standards men- block’s accumulator and step size are cleared.
tioned above for an exact definition. When CEN is enabled, the ADPCM block will
start converting. Care should be taken to insure
ADPCM COMPRESSION/DECOMPRESSION that the "overrun" condition never occurs, other-
In MODE 2 and 3, the WSS Codec also con- wise the data may not be constructed properly
tains Adaptive Differential Pulse Code upon playback. If pausing the capture sequence is
Modulation (ADPCM) for improved perform- desired, the ADPCM Capture Freeze bit (ACF,
ance and compression ratios over µ-Law or I23) should be set. When this bit is set, the
A-Law. The ADPCM format is compliant with ADPCM algorithm will continue to operate until a
the IMA standard and provides a 4-to-1 com- complete word (4 bytes) is written to the FIFO.
pression ratio (i.e. 4 bits are saved for each Then the ADPCM’s block accumulator and step
16-bit sample captured). For more information size will be frozen. The software must continue

+FS
ANALOG VALUE

-FS
A-Law: 2Ah 15h 55h/D5h 95h AAh
u-Law: 00h 3Fh 7Fh/FFh BFh 80h
DIGITAL CODE

Figure 22. Linear Transfer Functions Figure 23. Companded Transfer Functions

84 DS215PP4
 CS4238B

reading until the FIFO is empty, at which time For all data formats except ADPCM, the DMA
the requests will stop. When ACF is cleared, the Base registers must be loaded with the number
ADPCM adaptation will continue. of samples, minus one, to be transferred between
"DMA Interrupts". Stereo data contains twice as
When PEN is cleared (playback disabled), the many samples as mono data; however, 8-bit data
ADPCM block’s accumulator and step size are and 16-bit data contain the same number of sam-
cleared. When PEN is set, the ADPCM block ples. Symbolically:
will start converting. When pausing the playback
stream is desired, audio data should not be sent DMA Base register16 = NS - 1
to the codec which will cause a data underrun.
This can be accomplished by disabling the DMA Where NS is the number of samples transferred
controller or not sending data in PIO mode. The between interrupts and the "DMA Base regis-
underrun will be detected by the WSS Codec ter16" consists of the concatenation of the upper
and the adaptation will freeze. When data is sent and lower DMA Base registers.
to the codec, adaptation will resume. It is critical
that all playback ADPCM samples are sent to the For the ADPCM data format, the contents of the
codec, since dropped samples will cause errors DMA Base registers is calculated differently
in adaptation. Whereas toggling PEN resets the from any other data format. The Base registers
accumulator and step size, the APAR bit (I17) must be loaded with the number of BYTES to be
only resets the accumulator without affecting the transferred between "DMA interrupts", divided
step size. by four, minus one. The same equation is used
whether the data format is stereo or mono
DMA Registers ADPCM. Symbolically:
The DMA registers allow easy integration of this
part into ISA systems. Peculiarities of the ISA DMA Base register16 = Nb/4 - 1
DMA controller require an external count
mechanism to notify the host CPU of a full Where Nb is the number of BYTES transferred
DMA buffer via interrupt. The programmable between interrupts and the "DMA Base regis-
DMA Base registers provide this service. ter16" consists of the concatenation of the upper
and lower DMA Base registers.
The act of writing a value to the Upper Base
register causes both Base registers to load the PLAYBACK DMA REGISTERS
Current Count register. DMA transfers are en- The playback DMA registers (I14/15) are used
abled by setting the PEN/CEN bit while for sending playback data to the DACs in
PPIO/CPIO is clear. (PPIO/CPIO can only be MODE 2 and 3. In MODE 1, these registers
changed while the MCE bit is set.) Once trans- (I14/15) are used for both playback and capture;
fers are enabled, each sample that is transferred therefore, full-duplex DMA operation is not pos-
by a DMA cycle will decrement the Current sible.
Count register (with the exception of the
ADPCM format) until zero is reached. The next When the playback Current Count register rolls
sample after zero generates an interrupt and re- under, the Playback Interrupt bit, PI, (I24) is set
loads the Current Count registers with the values causing the INT bit (R2) to be set. The interrupt
in the Base registers. is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Playback
Interrupt bit, PI (I24).

DS215PP4 85
 CS4238B

If the sum of the digital mixer inputs is greater

CAPTURE DMA REGISTERS than full scale, WSS Codec will send the appro-
The Capture DMA Base registers (I30/31) pro- priate full scale value to the DACs (clipping).
vide a second pair of Base registers that allow
full-duplex DMA operation. With full-duplex op- Timer Registers
eration capture and playback can occur The Timer registers are provided for synchroni-
simultaneously. These registers are provided in zation, watch dog and other functions where a
MODE 2 and 3 only. high resolution time reference is required. This
counter is 16 bits and the exact time base, listed
When the capture Current Count register rolls in the register description, is determined by the
under, the Capture Interrupt bit, CI, (I24) is set clock base frequency selected.
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status The Timer register is set by loading the high and
register (R2), or writing a "0" to the Capture In- low registers to the appropriate values and set-
terrupt bit, CI (I24). ting the Timer Enable bit, TE, in the Alternate
Feature Enable register (I16). This value will be
Digital Loopback loaded into an internal Current Count register
Digital Loopback is enabled via the LBE bit in and will decrement at approximately a 10 µsec
the Loopback Control register (I13). This loop- rate. When the value of the Current Count regis-
back routes the digital data from the ADCs to ter reaches zero, an interrupt will be posted to
the DACs. There are two Methods of control- the host and the Timer Interrupt bit, TI, is set in
ling this loopback. The first method does not the Alternate Feature Status register (I24). On
allow separate control over the attenuation level the next timer clock the value of the Timer regis-
of the left and right channels. Changes to the ters will be loaded into the internal Current
attenuation bits of register I13 will simultane- Count register and the process will begin again.
ously affect both the left and the right channels. The interrupt is cleared by any write to the
The other method of controlling loopback, is to Status register (R2) or by writing a "0" to the
set the SLBE bit in register X10. This separates Timer Interrupt bit, TI, in the Alternate Feature
the attenuation levels of the left and right chan- Status register (I24).
nels. With SLBE enabled, the attenuation bits of
register I13 only control the left channel, and the WSS Codec Interrupt
attenuation bits of register X10 control the right The INT bit of the Status register (R2) always
channel. The LBE bit in register I13 still en- reflects the status of the WSS Codec’s internal
ables, or disables digital loopback for both interrupt state. A roll-over from any Current
channels. Loopback is then summed into the Count register (DMA playback, DMA capture, or
digital mixer. The digital loopback is illustrated Timer) sets the INT bit. This bit remains set until
in Figure 4. Since the WSS Codec allows selec- cleared by a write of ANY value to Status regis-
tion of different data formats between capture ter (R2), or by clearing the appropriate bit or bits
and playback, if the capture channel is set to (PI, CI, TI) in the Alternate Feature Status regis-
mono and the playback channel set to stereo, the ter (I24).
mono input (mic) data will be mixed into both
channels of the output mixer.

86 DS215PP4
 CS4238B

The Interrupt Enable (IEN) bit in the Pin Control Reference Design Data Sheet contains all the
register (I10) determines whether the interrupt schematics, layout plots and a Bill of Materials;
assigned to the WSS Codec responds to the in- thereby providing a complete example.
terrupt event. When the IEN bit is low, the
interrupt is masked and the IRQ pin assigned to Bus Interface
the WSS Codec is held low. However, the INT The ISA bus interface is capable of driving a
bit in the Status register (R2) always responds to 24mA data bus load and therefore does not re-
the counter. quire any external data bus buffering. See the
Reference Design Data Sheet for a typical con-
Error Conditions nection diagram.
Data overrun or underrun could occur if data is
not supplied to or read from the WSS Codec in Volume Control Interface
an appropriate amount of time. The amount of Three hardware master volume control pins are
time for such data transfers depends on the fre- supported: volume up, volume down, and mute.
quency selected within the WSS Codec. Hardware volume control is enabled by setting
the VCEN bit in the Hardware Configuration
Should an overrun condition occur during data data, byte 7 (Misc. Config. Byte). Once VCEN
capture, the last whole sample (before the over- is set, the SCS/UP pin converts to the volume up
run condition) will be read by the DMA function and the XCTL1/SINT/ACDCS/DOWN
interface. A sample will not be overwritten while pin converts to the volume down function. The
the DMA interface is in the process of transfer- volume control pins affect the master volume
ring the sample. control output after the analog output mixer. The
UP and DOWN pins, when low, increment and
Should an underrun condition occur in a play- decrement the master volume. These two pins
back case the last valid sample will be output would use SPST momentary switches. The
(assuming DACZ = 0) to the digital mixer. This MUTE pin supports three options: push-on/push-
will mask short duration error conditions. When off, momentary (similar to the up/down
the next complete sample arrives from the host functions), and non-existent where pressing up
computer the data stream will resume on the and down simultaneously mutes the output vol-
next sample clock. ume. As shown in Figure 24, the three pins
require external pullups and are active low. The
The overrun and underrun error bits in the Alter- circuit also contains an optional RC for EMI and
nate Feature Status register, I24, are cleared by ESD protection.
first clearing the condition that caused the over-
run or underrun error, followed by writing the The volume control range is +12 to -36 dB in
particular bit to a zero. As an example, to clear 2 dB steps. Pressing the up button, increments
the playback underrun bit PU, first a sample the volume. Pressing the down button, decre-
must be sent to the WSS Codec, and then the PU ments the volume. Holding either of these
bit must be written to a zero. buttons in the low state causes the volume to to
continue changing.
DIGITAL HARDWARE DESCRIPTION
The best example of hardware connection for the The mute function is supported using three for-
different sections of this part such as joystick mats. These formats are selected using the VCF1
connector, ISA bus, and peripheral port connec- and VCF0 bits in the Hardware Configuration
tions is the Reference Design Data Sheet. The data, Global Config. byte.

DS215PP4 87
 CS4238B

The three formats listed above as illustrated in

VDF Figure 25.

A four th format for mute exists, where

10 k Ω 10 k Ω 10 k Ω
VCF1,0 = 11, which is backwards compatible
UP Up with the CS4236. This mode is similar to the
100 Ω 100 Ω
DOWN Down two button mode, except the MUTE pin is used
100 Ω as the up function and the UP pin is not used.
MUTE Mute
100 pF 100 pF 100 pF
Crystal / Clock
GND
Two pins have been allocated to allow the inter-
facing of a crystal oscillator: XTALI and
Figure 24. Volume Control Circuit XTALO. The crystal should be designed as fun-
damental mode, parallel resonant, with a load
In the first format, where VCF1,0 = 00, the mute capacitor of between 10 and 20 pF. The capaci-
function is a toggle or push-on/push-off style. tors connected to each of the crystal pins should
When the MUTE pin is low, the master out vol- be twice the load capacitance specified to the
ume is muted. Pressing the up or down buttons crystal manufacturer.
have no effect while the mute switch is on.
An external CMOS clock may be connected to
In the second format, where VCF1,0 = 01, the the crystal input XTALI in lieu of the crystal.
mute function is a momentary switch (similar to When using an external CMOS clock, the
up and down). When MUTE goes low the mas- XTALO pin must be left floating with no trace
ter out volume mutes if it was un-muted and or external connection of any kind.
vise-versa (the mute button alternates between
mute and un-mute). If the master volume is General Purpose Output Pins
muted and up or down is pressed, the volume
automatically un-mutes. Two general purpose outputs are provided to en-
able control of external circuitry (i.e. mute
In the third format, where VCF1,0 = 10, the function). XCTL1 and XCTL0 in the WSS
MUTE pin is not used. This is a two-button for- Codec register I10 are output directly to the ap-
mat where pressing up and down simultaneously propriate pin when enabled.
mutes the master volume. If the master volume
is muted and up or down is individually pressed, Pin XCTL0/XA2 becomes an output for XCTL0
the volume automatically un-mutes. whenever the resource data for the CDROM or
Synthesizer specifies a logical device address

Up Up Up

Down Down Down

Mute Mute Mute
GND GND GND

VCF1,0 = 00 VCF1,0 = 01 VCF1,0 = 10

Figure 25. Volume Control Formats

88 DS215PP4
 CS4238B

range that is four bytes. If the address range is Software low-power states are available through
specified to be eight bytes, then XA2 becomes bits in the Control logical device register space.
an output for SA2 from the ISA bus. This part supports the same power down bits
contained in the CS4232; however, new power
Pin XCTL1/SINT/ACDCS/DOWN is initially down modes are provided in CTRLbase+2 that
controlled by the VCEN bit in the Hardware allow for a more efficient power management
Configuration data. If VCEN is zero, this pin be- routine. This register allows individual blocks
comes an output for XCTL1 when the state of within the part to be powered down. See the
the XIOW pin is sampled high during a high to CONTROL INTERFACE section for more infor-
low transition of the RESDRV pin. This pin also mation.
becomes an output for ACDCS if ACDbase is
programmed to a non-zero value. If XIOW is Multiplexed Pin Configuration
sampled low and ACDbase is never programmed On the high to low transition of the RESDRV
to a non-zero value, SINT becomes an input for pin, the part samples the state of the XIOR and
the external Synthesizer interrupt. XIOW has an XIOW pins. Both of these pins have internal
internal pullup resistor. ACDCS takes prece- 100kΩ pullups to +5V. If either of these pins is
dence over the other two functions. The first pulled low externally, they must be buffered be-
time ACDbase is programmed to a non-zero fore connecting to a TTL input (as in a CDROM
value, the pin converts to ACDCS. The only way port) since TTL cannot be pulled low.
to convert back to XTAL1 or SINT is to reset
the part. VCEN has the highest precedence and The state of XIOR at the time RESDRV is
will cause this pin to convert to the DOWN brought low determines the function of the
function whenever VCEN is set. CDROM interface pins. If XIOR is sampled
high, then CDCS, CDACK, CDINT, CDRQ are
Reset and Power Down used to input SA12, SA13, SA14, SA15 respec-
A RESDRV pin places the part into maximum tively. If XIOR is sampled low (external
power conservation mode. When RESDRV goes pulldown) then CDCS, CDACK, CDINT, CDRQ
high, the PnP registers are reset - all logical de- become the standard CDROM interface pins.
vices are disabled, all analog outputs are muted, Since many CDROM drives do not use DMA,
and the voltage reference then slowly decays to the CDRQ and CDACK pins are further multi-
ground. When RESDRV is brought low, an in- plexed with MCS and MINT respectively. MCS
itialization procedure begins which causes a full is the Modem chip select that responds to COM-
calibration cycle to occur. When initialization is base addresses, and MINT is the modem
completed, the registers will contain their reset interrupt input. These two pins comprise logical
value and the part will be isolated from the bus. device 5. The first time COMbase is pro-
RESDRV is required whenever the part is pow- grammed to non-zero (assuming XIOR was
ered up. The initialization time varies based on sampled low), CDACK/MCS and CDRQ/MINT
whether an E2PROM is present or not and the switch to MCS and MINT respectively. Once
size of the data in the E2PROM. After RESDRV this switch occurs, the only way to revert to the
goes low, the CS4236 should not be written to CDROM DMA pins is to reset the part or re-
for approximately one and one half second to move power.
guarantee that the part is ready to respond to
commands. The exact timing is specified in the The XCTL1/SINT/ACDCS/DOWN pin state is
Timing Section in the front of this data sheet. first determined by VCEN. If VCEN is set this
pin is forced to the DOWN volume control pin.

DS215PP4 89
 CS4238B

If VCEN is zero, then if ACDbase is ever pro- The analog input interface is designed to accom-
grammed to a non-zero value, this pin converts modate four stereo inputs and one mono input.
to the ACDCS pin and keeps this function until Four of these sources are mixed to the ADC.
the part is reset (or VCEN is set to one). If These inputs are: a stereo line-level input
ACDbase is never programmed non-zero, then (LINE), a stereo microphone input (MIC), a ste-
the state of XIOW at the time RESDRV is reo CD-ROM input (AUX2), and a stereo
brought low determines whether the pin is auxiliary line-level input (AUX1). The LINE
XCTL1 or SINT. If XIOW is sampled low (ex- and AUX1 inputs have two paths to the Input
ternal pulldown) then XCTL1/SINT/ Mixer. One path is direct with no volume con-
ACDCS/DOWN functions as an input for the trol. The other path goes through an inverting
synthesizer interrupt. If XIOW is sampled high amplifier, which enables volume control. Care
(pin left unconnected) then XCTL1/SINT/ should be taken to select only one of these dual
ACDCS/DOWN becomes an output for XCTL1. paths, because the inverting path will cancel the
signal of the non-inverting path at the Input
This part contains another multiplexed pin, Mixer. The LINE, MIC, AUX1, and AUX2 in-
SCS/UP. This pin provides the FM synthesizer puts have paths after their volume controls, to
chip select or the hardware volume control "vol- the output mixer. The output mixer has the addi-
ume up" feature. Since an internal FM tional input of a mono input channel. All audio
synthesizer exists, this pin would normally be inputs should be capacitively coupled.
used for the volume control feature. Setting
VCEN forces this pin to the UP volume control To obtain Sound Blaster mixer compatibility, the
function. When VCEN is clear, this pin is the mapping of external devices to analog inputs is
SCS chip select function. important. An external FM or Wavetable synthe-
sizer analog output must be connected to the
ANALOG HARDWARE DESCRIPTION LINE input. The internal FM’s volume control,
The analog hardware consist of an MPC when enabled, maps to the LINE analog mixer
Level 2-compatible mixer (four stereo mix registers. The CDROM analog outputs must be
sources), three line-level stereo inputs, a stereo connected to the AUX2 inputs, and the external
microphone input, a mono input, a mono output, Line Inputs must be connected to the AUX1 ana-
and a stereo line output. This section describes log inputs.
the analog hardware needed to interface with
these pins. Since some analog inputs can be as large as
2 VRMS, the circuit shown in Figure 26 can be
Line-Level Inputs Plus MPC Mixer used to attenuate the analog input to 1 VRMS
which is the maximum voltage allowed for the
The analog inputs consist of four stereo analog line-level inputs.
inputs, and one mono input. As shown in Fig-
ure 4, the input to the ADCs comes from the 6.8 kΩ 1.0 µF
Input Mixer that selects any combination of the R
following: LINE, AUX1, AUX2, MIC, the DAC 1.0 µF
output, and the output from the analog output L
mixer. Unused analog inputs should be con- 6.8 kΩ
nected together and then connected through a 6.8 kΩ 6.8 kΩ
capacitor to analog ground.
Figure 26. Line Inputs

90 DS215PP4
 CS4238B

The AUX2 line-level inputs have an extra pin,

2 kΩ
CMAUX2, which provides a pseudo-differential 47 kΩ
input for both LAUX2 and RAUX2. This pin VREF
+
takes the common-mode noise out of the AUX2 47 kΩ 1 µF
inputs when connected to the ground coming MC33078 or
MC33178
from the AUX2 analog source. Connecting the 0.1 µF
0.33 µF
AUX2 pins as shown in Figure 27 provides extra LMIC
noise attenuation coming from the CDROM X7R
4.7 kΩ
drive, thereby producing a higher quality signal. RMIC
Since the better the resistors match, the better the 2.7 nF 0.33 µF
common-mode attenuation, one percent resistors NPO
are recommended. If CMAUX2 is not used, it 600 Ω
+
should be connected through an AC cap to ana- 10 µF
log ground.
Figure 28. Left or Mono Microphone Input
(All resistors 1%)
6.8 kΩ 1.0 µF
RAUX2 Mono Input
3.4 kΩ 1.0 µF
CMAUX2 The mono input, MIN, is useful for mixing the
LAUX2 output of the "beeper" (timer chip), provided in
6.8 kΩ 1.0 µF all PCs, with the rest of the audio signals. The
6.8 kΩ 3.4 kΩ 6.8 kΩ attenuation control allows 16 levels in -3dB
steps. In addition, a mute control is provided.
The attenuator is a single channel block with the
Figure 27. Differential CDROM In resulting signal sent to the output mixer where it
is mixed with the left and right outputs. Fig-
Microphone Level Inputs ure 29 illustrates a typical input circuit for the
Mono In. If MIN is driven from a CMOS gate,
The microphone level inputs, LMIC and RMIC,
include a selectable -22.5 dB to +22.5 dB gain the 4.7kΩ should be tied to AGND instead of
stage for interfacing to an external microphone. VA+. Although this input is described for a low-
An additional 20 dB gain block is available in quality beeper, the input is of the same
the path to the output mixer. The 20 dB gain high-quality as all other analog inputs and may
block can be switched off to provide another ste- be used for other purposes. At power-up, the
reo line-level input. Figure 28 illustrates a MIN line is connected directly to the MOUT pin
single-ended microphone input buffer circuit that (with 9 dB of attenuation) allowing the initial
will support lower gain mics. If a mono micro- beeps, heard when the computer is initializing, to
phone is all that is desired, the RMIC input pass through.
+5VA (Low Noise) or
should be connected to the output of the mono
AGND - if CMOS Source
op amp, used for LMIC, through its own AC
coupling capacitor. The circuit in Figure 28 sup- 4.7 kΩ
ports dynamic mics and phantom-powered mics 1 47 kΩ
MIN
that use the right channel of the jack for power. 0.1 µF
2.7 nF

Figure 29. Mono Input

DS215PP4 91
 CS4238B

the ADCs. By placing these filters at the input to

Line Level Outputs the ADCs, low-pass filters at each analog input
The analog output section provides a stereo line- pin are avoided.
level output. The other output types (headphone
and speaker) can be implemented with external The REFFLT pin is used to lower the noise of
circuitry. LOUT and ROUT outputs should be the internal voltage reference. A 1µF (must not
capacitively coupled to external circuitry. Both be greater than 1µF) and 0.1µF capacitor to ana-
LOUT and ROUT need 1000 pF NPO capacitors log ground should be connected with a short
between the pin and AGND. wide trace to this pin. No other connection
should be made, as any coupling onto this pin
Mono Output with Mute Control will degrade the analog performance of the
codec. Likewise, digital signals should be kept
The mono output, MOUT, is a sum of the left
away from REFFLT for similar reasons.
and right output channels, attenuated by 6dB to
prevent clipping at full scale. The mono out
The VREF pin is typically 2.2 V and provides a
channel can be used to drive the PC-internal
common mode signal for single-supply external
mono speaker using an appropriate drive circuit.
circuits. VREF only supports light DC loads and
This approach allows the traditional PC-sounds
should be buffered if AC loading is needed. For
to be integrated with the rest of the audio sys-
tem. Figure 30 illustrates a typical speaker driver typical use, a 0.1 µF in parallel with a 10 µF ca-
circuit. The mute control is independent of the pacitor should be connected to VREF.
line outputs allowing the mono channel to mute
the speaker without muting the line outputs. The GROUNDING AND LAYOUT
power-up default has MIN connected to MOUT Figure 31 is a suggested layout for motherboard
providing a pass-through for the beeps heard at designs and Figure 32 is a suggested layout for
power-up. add-inn cards. For optimum noise performance,
+5V the device should be located across a split ana-
Ferrite Bead log/digital ground plane. The digital ground
470 pF plane should extend across the ISA bus pins as
0.1 µF well as the internal digital interface pins.
10 kΩ 16 kΩ
DGND1 is ground for the data bus and should
4 6 5
MOUT be electrically connected to the digital ground
3 8 plane which will minimize the effects of the bus
0.22 µF 1 µF + 2 1 7

MC34119
RESDRV
or LM4861
Figure 30. Mono Output

Miscellaneous Analog Signals

The LFILT and RFILT pins must have a 1000 pF
NPO capacitor to analog ground. These capaci-
tors, along with an internal resistor, provide a
single-pole low-pass filter used at the inputs to

92 DS215PP4
 CS4238B

interface due to transient currents during bus to the system digital power supply. VD1 can also
switching. SGND1-4 are the substrate grounds be connected to a 3.3V supply providing a 3.3V
and should also be connected to the digital ISA interface. When connected to a 3.3V supply,
ground plane to minimize coupling into the ana- all ISA bus input pins (SA15-0, SD7-0, DACKs,
log section. Figure 33 shows the recommended etc.) must be at 3.3V levels (not 5V), with the
positioning of the decoupling capacitors. The ca- exception of the DRQA pin. DRQA is internally
pacitors must be on the same layer as, and close connected to the VDF supplies and remains a
to, the part. The vias shown go through to the 5 Volt pin even when the ISA bus is run at
ground and power plane layers. Vias, power sup- 3.3 Volts. When the ISA bus is powered from
ply traces, and REFFLT traces should be as large 3.3 Volts, DRQA can be be used through a level
as possible to minimize the impedance. translator, or DRQA can remain used. If DRQA
is not used, all references to this pin should be
POWER SUPPLIES removed in the PnP Resource data. Even though
The power supply providing analog power the ISA bus is at 3.3V, the peripheral port is still
should be as clean as possible to minimize cou- at a 5V potential including XD7-0 and all chip
pling into the analog section and degrading select and address pins.
analog performance.
VDF1 through VDF4 provide power to internal
The VD1 is isolated from the rest of the power digital sections of the codec and should be qui-
supply pins and provide digital power for the eter than VD1. This can be achieved by using a
asynchronous parallel ISA bus (except for
DRQA). The VD1 pin can be connected directly

Di Crystal Analog
g it
al Part Ground
Gr
o un
d No
1

ise

Digital Digital Ground Noise

Ground

Power
e
Nois Connector
d
un
G ro
al
igi t
D

Figure 31. Suggested Motherboard Layout

DS215PP4 93
 CS4238B

Speaker Out CD-ROM

Speaker In

Analog Ground

Crystal
Part
1

Digital Ground

Figure 32. Suggested Add-In Card Layout

1µF
PIN 80 +
AGND PIN 79
PIN 98 .1µ F PIN 97 PIN 81
VDF3 SGND3 .1µ F REFFLT
VA .1µF
PIN 1
XD7

Analog PIN 71
TEST

PIN 66
SGND2

.1µF
Digital
PIN 17
VDF1 PIN 65
VDF2
= vias through to
power/ground plane
.1µF
PIN 54
VDF4
PIN 18
SGND1
.1µF

PIN 53
SGND4

PIN 45 PIN 46
VD1
DGND1
.1µ F

Figure 33. Recommended Decoupling Capacitor Positions

94 DS215PP4
 CS4238B

ferrite bead to the VD1 supply as shown in the

Reference Design Data Sheet. These pins must
be connected to a 5V supply.

VA provides power to the sensitive analog sec-

tions of the chip and should have a clean,
regulated supply to minimize power supply cou-
pled noise in the analog inputs and outputs.

ADC/DAC FILTER RESPONSE PLOTS

Figures 34 through 39 show the overall fre-
quency response, passband ripple, and transition
band for the ADCs and DACs. Figure 40 shows
the DACs’ deviation from linear phase. Since the
10
filter response scales based on sample frequency 0
selected, all frequency response plots x-axis are -10
shown from 0 to 1, where 1 is equivalent to Fs. -20
Therefore, for any given sample frequency, mul- -30
Magnitude (dB)

tiply the x-axis values by the sample frequency -40

selected to get the actual frequency. -50

-60

-70

-80

-90

-100
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Input Frequency ( x Fs)

Figure 34. ADC Filter Response

0.2 0

0.1 -10

0.0 -20

-0.1 -30
Magnitude (dB)
Magnitude (dB)

-0.2 -40

-0.3 -50

-0.4 -60

-0.5 -70

-0.6 -80

-0.7 -90

-0.8 -100
0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.40 0.45 0.50 0.55 0.60 0.65 0.70
Input Frequency ( x Fs) Input Frequency ( x Fs)

Figure 35. ADC Passband Ripple Figure 36. ADC Transition Band

DS215PP4 95
 CS4238B

10 0.2

0 0.1
-10 0.0
-20
-0.1

Magnitude (dB)
Magnitude (dB)

-30
-0.2
-40
-0.3
-50
-0.4
-60
-0.5
-70

-80 -0.6

-90 -0.7

-100 -0.8
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency ( x Fs) Input Frequency ( x Fs)

Figure 37. DAC Filter Response Figure 38. DAC Passband Ripple

0 2.0

-10
1.5
-20
1.0
-30
∆ Phase (degrees)
Magnitude (dB)

0.5
-40

-50 0.0

-60 -0.5
-70
-1.0
-80
-1.5
-90

-100 -2.0
0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50
Input Frequency ( x Fs) Input Frequency ( x Fs)

Figure 39. DAC Transition Band Figure 40. Deviation from Linear Phase

96 DS215PP4
 CS4238B

PIN DESCRIPTIONS

SA13*/CDACK/MCS

SA15*/CDRQ/MIN T
SA14*/CDINT
SA12*/CDCS

RESDRV
CMAUX2

REFFLT
SGND3

RAUX2
LAUX2
XTALO

AGND

RFILT
RLINE
MOUT
MUTE

VREF
LLINE
VDF3

LFILT
RMIC
XTALI

LMIC
MIN

VA
94
98
97
96
95

93
92

90
99

91

89
88
87

85
84
83

81
86

82

76
100

77
80
79
78
XD7/SDATA 1 75 LAUX1
XD6/LRCLK 2 74 RAUX1
XD5/MCLK 3 73 LOUT
XD4/FSYNC 4 72 ROUT
CS4238B-KQ
XD3/SDOUT 5 71 TEST
XD2/SDIN 6 70 JAB1
XD1SCLK 7 69 JBB1*/FSYNC
SDA/XD0 8 68 JACX
SCS/UP 9 67 JBCX*/SDOUT
XIOR 10 66 SGND2
XIOW 11 65 VDF2
100-PIN

XCTL0*/XA2 12 64 JBCY*/SDIN
TQFP

XA1 13 63 JACY
SCL/XA0 14 62 JBB2*/SCLK
BRESET 15 61 JAB2
XCTL1*/SINT/ACDCS/DOWN 16 60 MIDOUT
VDF1 17 59 MIDIN
SGND1 18 58 DACKA (DACK0*)
(INT15*) IRQF 19 57 DACKC (DACK3*)
(INT12*) IRQE 20 56 DACKB (DACK1*)
(INT11*) IRQD 21 55 DRQA (DRQ0*)
(INT9*) IRQC 22 54 VDF4
(INT7*) IRQB 23 53 SGND4
(INT5*) IRQA 24 (TOP VIEW) 52 DRQC (DRQ3*)
SA0 25 51 DRQB (DRQ1*)
37
36
30
31
32

34
26

28
29

33

35

38

40
41
27

39

42

47
43
44
45
46

49
50
48
DGND1
SA1
SA2
SA3
SA4
SA5

VD1
AEN
SA11

IOW
IOR
SA10

SD0

SD3

SD4
SD5
SD6
SD7
SA6
SA7
SA8
SA9

SD2
SD1
IOCHRDY

* Defaults - See individual pin descriptions for more details

DS215PP4 97
 CS4238B

ISA Bus Interface Pins

SA<11:0> - System Address Bus, Inputs

These signals are decoded during I/O cycles to determine access to the various functional
blocks within the part as defined by the configuration data written during a Plug and Play
configuration sequence.

SA<15:12> - Upper System Address Bus, Inputs

These signals are multi-function pins, shared with the CDROM and modem interface, that
default to the upper address bits SA12 through SA15. These pins are generally used for
motherboard designs that want to eliminate address decode aliasing. Using these pins as upper
address bits forces the part to only accept valid address decodes when A12-A15 = 0. If these
pins are not used for address decodes (or for CDROM support), they should be tied to SGND.

SD<7:0> - System Data Bus, Bi-directional, 24mA drive

These signals are used to transfer data to and from the part and associated peripheral devices.
Reads from peripheral devices can be disabled (the part does not drive the SD<7:0> pins) by
setting the SDD bit in the Hardware Configuration data. Reads from peripheral devices are
automatically disabled whenever the XD pins are used as serial port pins (SPS/SPE or WTEN
set to one).

AEN - Address Enable, Input

This signal indicates whether the current bus cycle is an I/O cycle or a DMA cycle. This signal
is low during an I/O cycle and high during a DMA cycle.

IOR - Read Command Strobe, Input

This active low signal defines a read cycle to the part. The cycle may be a register read or a
read from the part’s DMA registers.

IOW - Write Command Strobe, Input

This active low signal indicates a write cycle to the part. The cycle may be a write to a control
register or a DMA register.

IOCHRDY - I/O Channel Ready, Open Drain Output, 8mA drive

This signal is driven low by the part during ISA bus cycles in which the part is not able to
respond within a minimum cycle time. IOCHRDY is forced low to extend the current bus
cycle. The bus cycle is extended until IOCHRDY is brought high.

DRQ<A,B,C> - DMA Requests, Outputs, 24mA drive

These active high outputs are generated when the part is requesting a DMA transfer. This
signal remains high until all the bytes have been transferred as defined by the current transfer
data type. The DRQ<A,B,C> outputs must be connected to 8-bit DMA channel request signals
only. The defaults on the ISA bus are DRQA = DRQ0, DRQB = DRQ1, and DRQC = DRQ3.
The defaults can be changed by modifying the Hardware Resource data. Note that DRQA is a
5 Volt-only pin. When the ISA bus is run at 3.3 Volts, DRQA can either be used with the proper
level translator, or DRQA can be left unconnected and not used.

98 DS215PP4
 CS4238B

DACK<A,B,C> - DMA Acknowledge, Inputs

The assertion of these active low signals indicate that the current DMA request is being
acknowledged and the part will respond by either latching the data present on the data bus
(write) or putting data on the bus (read). The DACK<A,B,C> inputs must be connected to 8-bit
DMA channel acknowledge lines only. The defaults on the ISA bus are DACKA = DACK0,
DACKB = DACK1, and DACKC = DACK3. The defaults can be changed by modifying the
Hardware Resource data.

IRQ <A:F>- Host Interrupt Pins, Outputs, 24mA drive

These signals are used to notify the host of events which need servicing. They are connected to
specific interrupt lines on the ISA bus. The IRQ<A:F> are individually enabled as per
configuration data that is generated during a Plug and Play configuration sequence. The defaults
on the ISA bus are IRQA = INT5, IRQB = INT7, IRQC = INT9, IRQD = INT11,
IRQE = INT12, IRQF = INT15. The defaults can be changed by modifying the Hardware
Configuration data loaded from the E2PROM.

Analog Inputs

LLINE - Left Line Input

Nominally 1 VRMS max analog input for the Left LINE channel, centered around VREF. A
programmable gain block provides volume control and is located in either I18 or X0 based on
how synthesis is mapped. LLINE is typically used for Left Channel Synthesis (FM or
Wavetable).

RLINE - Right Line Input

Nominally 1 VRMS max analog input for the Right LINE channel, centered around VREF. A
programmable gain block provides volume control and is located in either I19 or X1 based on
how synthesis is mapped. RLINE is typically used for Right Channel Synthesis (FM or
Wavetable).

LMIC - Left Mic Input

Microphone input for the Left MIC channel, centered around VREF. A programmable gain
block provides volume control and is located in X2. In MODE 3, the output mixer has an extra
selectable 20 dB of gain controlled by the LMBST bit.

RMIC - Right Mic Input

Microphone input for the Right MIC channel, centered around VREF. A programmable gain
block provides volume control and is located in X3. In MODE 3, the output mixer has an extra
selectable 20 dB of gain controlled by the RMBST bit.

LAUX1 - Left Auxiliary #1 Input

Nominally 1 VRMS max analog input for the Left AUX1 channel, centered around VREF. A
programmable gain block provides volume control and is located in I2. Typically used for an
external Left line-level input.

DS215PP4 99
 CS4238B

RAUX1 - Right Auxiliary #1 Input

Nominally 1 VRMS max analog input for the Right AUX1 channel, centered around VREF. A
programmable gain block provides volume control and is located in I3. Typically used for an
external Right line-level input.

LAUX2 - Left Auxiliary #2 Input

Nominally 1 VRMS max analog input for the Left AUX2 channel, centered around VREF. A
programmable gain block provides volume control and is located in I4. Typically used for the
Left channel CDROM input.

RAUX2 - Right Auxiliary #2 Input

Nominally 1 VRMS max analog input for the Right AUX2 channel, centered around VREF. A
programmable gain block provides volume control and is located in I5. Typically used for the
Right channel CDROM input.

CMAUX2 - Common Mode Auxiliary #2 Input

Common mode ground input for the LAUX2 and RAUX2 inputs. Typically connected to the
CDROM ground input to provide common-mode noise rejection. The impedance on this pin
should be one half the impedance on the LAUX2 and RAUX2 inputs.

MIN - Mono Input

Nominally 1 VRMS max analog input, centered around VREF, that goes through a
programmable gain stage (I26) into both channels of the output mixer. This is a general purpose
mono analog input that is normally used to mix the typical "beeper" signal on most computers
into the audio system.

Analog Outputs

LOUT - Left Line Level Output

Analog output from the mixer for the left channel. Nominally 1 VRMS max centered around
VREF. This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.

ROUT - Right Line Level Output

Analog output from the mixer for the Right channel. Nominally 1 VRMS max centered around
VREF. This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.

MOUT - Mono Output

MOUT is nominally 1 VRMS max analog output, centered around VREF. This output is a
summed analog output from both the left and right output channels of the mixer. MOUT
typically is connected to a speaker driver that drives the internal speaker in most computers. In
MODE2, MOM in I26 mutes both channels going into MOUT. In MODE 3, MOM in I26
mutes the left channel and MOMR in X5 mutes the right channel.

100 DS215PP4
 CS4238B

MIDI Interface

MIDOUT - MIDI Out Transmit Data, Output, 4mA drive

This output is used to send MIDI data serially out to a external MIDI device. Normally
connected to pin 12 of the joystick connector for use with breakout boxes.

MIDIN - MIDI In Receive Data, Input

This input is used to receive serial MIDI data from an external MIDI device. This pin should
have a 4.7 kΩ pullup attached and is normally connected to pin 15 of the joystick connector for
use with breakout boxes.

External FM Synthesizer Interface

SCS - Synthesizer Chip Select, Output, 4 mA drive

By default, SCS/UP is an active low output forced low when a valid address decode to an
external FM synthesizer, as defined in the Plug and Play configuration registers, has occurred.
When the internal FM synthesizer is enabled, this pin is no longer used as an FM synthesizer
chip select. This pin can be used for a hardware volume up pin by setting VCEN in the
Hardware Configuration data.

SINT - Synthesizer Interrupt, Input

This pin, XCTL1/SINT/ACDCS/DOWN, defaults to the XCTL1 output which is controlled by
the XCTL1 bit in the WSS register I10. If VCEN in the Hardware Configuration data is set, this
pin converts to the DOWN volume control function. If VCEN is zero, and ACDbase is never
programmed to a non-zero value, this pin can be changed to SINT input by connecting a 10 kΩ
resistor between the XIOW pin and SGND. The polarity of SINT can be programmed through
CTRLbase+1 register, the ISH bit, or the Hardware Configuration data. SINT defaults to an
active low input that should be driven by the external FM synthesizer interrupt output pin. This
pin can also be configured at a second CDROM Chip Select, ACDCS, to support the alternate
IDE CDROM decode. (See the CDROM section for more information.) The pin is switched to
the CDROM alternate chip select when VCEN is zero and the base address is first programmed
to non-zero through the E2PROM data or PnP commands.

External Peripheral Port

XD<7:1> - External Data Bus bits 7 through 1, Bi-directional, 4mA drive

These pins are used to transfer data between the ISA bus and external devices such as the
modem and CDROM. These pins are also multiplexed with two serial ports. A DSP serial port
can be connected through the XD4-XD1 pins. This interface is multiplexed onto these external
data bus pins OR the 2nd Joystick pins based on the SPS (Serial Port Switch) bit. The second
serial port connects to the CS9236 Single-Chip Wavetable Music Synthesizer and uses pins
XD7-XD5. This serial port is enabled via the WTEN bit. Both SPS and WTEN are located in
either C8 in the Control logical device, or the Global Configuration byte in the E2PROM
Hardware Configuration data.

DS215PP4 101
 CS4238B

SDA/XD0 - External Data Bus bit 0/E2PROM Data Pin, Bi-directional, Open Drain,4mA sink
This open-drain pin must have an external pullup (3.3 kΩ) and is used to transfer data between
the ISA bus bit 0, SD0, and external devices such as a modem or CDROM. SDA/XD0 is also
used in conjunction with SCL/XA0 to access an external serial E2PROM. When an E2PROM is
used, the SDA/XD0 pin should be connected to the data pin of the E2PROM device and
provides a bi-directional data port. The E2PROM is used to set the Plug and Play resource data.

XCTL0/XA2 - XCTL0 or External Address SA2, Output, 4mA drive

This pin either outputs ISA bus address SA2 or XCTL0 depending on the Hardware
Configuration data. The default is XCTL0 which is controlled by the XCTL0 bit in the WSS
register I10. This pin changes to address bit XA2 if the Hardware Configuration data indicates
that the peripheral port requires more than four I/O addresses.

XA1 - External Address, Output, 4mA drive

This pin outputs ISA bus address SA1.

XA0/SCL - External Address, Output/Serial Clock, Output, 4mA drive

This pin outputs the ISA bus address SA0. When E2PROM access is enabled, via EEN in
CTRLbase+1, then SCL is used as a clock output to the E2PROM.

BRESET - Buffered Reset, Output, 4mA drive

This active low signal goes low whenever the RESDRV pin goes high. This pin is also software
controllable through the BRES bit in register C8 in the Control Logical Device space. BRES
provides a software power down and reset control over devices connected to the Crystal Codec
such as the CS9236 Single-Chip Wavetable Music Synthesizer.

XIOR - External Read Strobe, Output, 4mA drive (SA12-SA15/CDROM selection)

This active low signal goes low whenever (SCS, CDCS, or MCS) and IOR goes low. When
RESDRV goes low, this pin also selects either the CDROM/Modem port or SA12 - SA15 and
contains an internal pullup of approximately 100 kΩ. When XIOR is left high (default), pins
91-94 are SA15-SA12 respectively. To enable the CDROM and Modem ports, an external 10kΩ
resistor must be tied between this pin and SGND.

XIOW - External Write Strobe, Output, 4mA drive (XCTL1/SINT/ACDCS/DOWN selection)

This active low signal goes low whenever (SCS or CDCS or MCS) and IOW goes low. When
RESDRV goes low, this pin also selects either XCTL1 or SINT and contains an internal pullup
of approximately 100 kΩ. When XIOW is left high (default), pin 16 is the XCTL1 function (or
ACDCS, based on a non-zero value being programmed into the alternate CDROM address
register). To change the pin to SINT, an external 10kΩ resistor must be tied between this pin
and SGND.

102 DS215PP4
 CS4238B

Joystick/DSP Serial Port Interface

JACX, JACY - Joystick A Coordinates, Input

These pins and are the X/Y coordinates for Joystick A. They should have a 5.6nF capacitor to
ground and a 2.2kΩ resistor to the joystick connector pins 3 and 6, respectively.

JAB1, JAB2 - Joystick A Buttons, Input

These pins are the switch inputs for Joystick A. They should be connected to joystick connector
pins 2 and 7, respectively; as well as have a 1nF capacitor to ground, and a 4.7kΩ pullup
resistor.

JBCX/SDOUT - Joystick B Coordinate X/Serial Data Output, Input/Output

When this pin is used as a second joystick, it is the X coordinates input for Joystick B; and
should have a 5.6nF capacitor to ground and a 2.2kΩ resistor to the joystick connector pin 11.
When the serial port is enabled, SPE = 1 in I16, this pin is the serial data output. The DSP
serial port SDOUT pin can be switched to XD3 via the SPS bit. This would facilitate using the
DSP serial port and the second joystick simultaneously.

JBCY/SDIN - Joystick B Coordinate Y/Serial Data Input, Input

When this pin is used as a second joystick, it is the Y coordinates input for Joystick B; and
should have a 5.6nF capacitor to ground and a 2.2kΩ resistor to the joystick connector pin 13.
When the serial port is enabled, SPE = 1 in I16, this pin is the serial data input. The DSP serial
port SDIN pin can be switched to XD2 via the SPS bit. This would facilitate using the DSP
serial port and the second joystick simultaneously.

JBB1/FSYNC - Joystick B Button 1/Frame Sync, Input/Output

When this pin is used as a second joystick, it is the switch 1 input for Joystick B; and should be
connected to joystick connector pin 10; as well as have a 1nF capacitor to ground, and a 4.7kΩ
pullup resistor. When the serial port is enabled, SPE = 1 in I16, this pin is the serial frame sync
output. The DSP serial port FSYNC pin can be switched to XD4 via the SPS bit. This would
facilitate using the DSP serial port and the second joystick simultaneously.

JBB2/SCLK - Joystick B Button 2/Serial Clock, Input/Output

When this pin is used as a second joystick, it is the switch 2 input for Joystick B; and should be
connected to joystick connector pin 14; as well as have a 1nF capacitor to ground, and a 4.7kΩ
pullup resistor. When the serial port is enabled, SPE = 1 in I16, this pin is the serial clock
output. The DSP serial port SCLK pin can be switched to XD1 via the SPS bit. This would
facilitate using the DSP serial port and the second joystick simultaneously.

DS215PP4 103
 CS4238B

CS9236 Wavetable Serial Port Interface

A digital interface to the Crystal CS9236 Single-Chip Wavetable Music Synthesizer is provided
that allows the CS9236 PCM audio data to be summed digitally on the Crystal Codec without
the need for an external DAC. The Wavetable Serial Port interface pins are multiplexed with the
XD7-XD5 external bus pins. This serial port is enabled via the WTEN bit which is located in
the Global Configuration byte in the E2PROM Hardware Configuration data, or C8. The
interface typically consists of the three pins listed below as well as:
connecting the Crystal Codec MIDOUT pin to the CS9236 MIDI_IN pin, and
connecting the Crystal Codec BRESET pin to the CS9236 PDN and RST pins.
(The BRES bit in C8 provides a maximum software power-down mode for the
CS9236 by driving the BRESET signal low whenever BRES is set.)

SDATA - Wavetable Serial Audio Data, Input

This pin is multiplexed with the XD7 external data bus pin. When use as SDATA, this input
supplies the serial audio PCM data to be digitally mixed to the DACs of the Crystal codec. The
data consists of left and right channel 16-bit data delineated by LRCLK. This pin should be
connected to the SOUT output pin on the CS9236. This pin should also have a weak pull-down
resistor of approx. 100 kΩ to minimize power-down currents and allow for stuffing options.

LRCLK - Wavetable Serial Left/Right Clock, Input

This pin is multiplexed with the XD6 external data bus pin. When use as LRCLK, this input
supplies the serial data alignment signal that delineates left from right data. This pin should be
connected to the LRCLK output pin on the CS9236. This pin should also have a weak
pull-down resistor of approx. 100 kΩ to minimize power-down currents and allow for stuffing
options.

MCLK - Wavetable Master Clock, Output

This pin is multiplexed with the XD5 external data bus pin. When use as MCLK, this output
supplies the 16.9344 MHz master clock that controls all the timing on the CS9236. This pin
should be connected to the MCLK5I input pin on the CS9236. MCLK can be disabled in
software using the DMCLK bit in C8 in the Control logical device space. DMCLK provides a
partial software power-down mode for the CS9236.

104 DS215PP4
 CS4238B

CDROM and Modem Interface

The four CDROM pins are multi-function and default to ISA upper address bits SA12-SA15.
To enable the CDROM port, an external 10kΩ resistor must be tied between XIOR and SGND.
XIOR is sampled on the falling edge of RESDRV. If the CDROM interface doesn’t support
DMA, the two CDROM DMA pins can be converted to support Logical Device 5, a modem
interface.

CDCS - CDROM Chip Select, Output, 4mA drive

This output goes low whenever an address is decoded that matches the value programmed into
the CDROM base address register.

ACDCS - Alternate CDROM Chip Select, Output, 4mA drive

This pin, XCTL1/SINT/ACDCS/DOWN, is multiplexed with three other functions, and defaults
to the XCTL1 output which is controlled by the XCTL1 bit in the WSS I10. This pin can also
be configured at a second CDROM Chip Select, ACDCS, to support the alternate IDE CDROM
decode. The pin is switched to the CDROM alternate chip select when the base address
ACDbase is first programmed to non-zero through the E2PROM data or PnP commands. This
output then goes low whenever an address is decoded that matches the value programmed into
the CDROM alternate base address register, ACDbase. This pin can also be used as the volume
up pin DOWN by setting VCEN in Control register C0 or the Hardware Configuration data.
VCEN has the highest precedence over the other pin functions.

CDINT - CDROM Interrupt, Input

This pin is used to input an interrupt signal from the CDROM interface. The part can be
programmed, through the plug-and-play resource data, to output this signal to the appropriate
ISA bus interrupt line. The polarity if this input can be programmed through CTRLbase+1
register, bit ICH, or the Hardware Configuration data; the default is active high.

CDRQ/MINT - CDROM DMA Request, or Modem Interrupt, Input

This pin can be used to input the DMA request signal from the CDROM interface. The part can
be programmed, through the plug-and-play resource data, to output this signal to the
appropriate ISA bus DRQ line.
This pin can also be used to input an interrupt signal from a modem. The pin is switched to
MINT when the LD5 base address, COMbase, is first programmed to non-zero through the PnP
data or a hostload. The polarity of MINT can be programmed through CTRLbase+1 register,
IMH bit, or the Hardware Configuration data; the default is active low.

CDACK/MCS - CDROM DMA Acknowledge, or Modem Chip Select, Output, 4mA drive
This pin can be used to output the ISA bus-generated DMA acknowledge signal to the CDROM
interface. Alternately, this pin can be used to output an active low Modem chip select, MCS.
The pin is switched to the modem chip select when the LD5 base address, COMbase, is first
programmed to non-zero through the PnP data or a hostload.

DS215PP4 105
 CS4238B

Volume Control
The volume control pins are enabled by setting VCEN in the Hardware Configuration data,
Misc. Hardware Config. byte. The VCF1,0 bits in the Hardware Configuration data, Global
Configuration byte, set the format for the volume control pins. Each pin must have an external
pullup resistor (10kΩ) and either a momentary or toggle style switch based on format. Typically
a 100Ω series resistor and a capacitor to ground, capacitor on the switch side of the series
resistor, would be included on each pin for ESD protection and to help with EMI emissions.

UP - Volume Up
The SCS/UP pin is multiplexed with the external Synthesizer chip select. This pin is switched
to the UP function when VCEN is set. When UP is low, the master volume output for left and
right channels are incremented.

DOWN - Volume Down

The XCTL1/SINT/ACDCS/DOWN is a multiplexed pin that can be used as XCTL1, the
external FM synthesizer interrupt, the alternate CDROM chip select, or the Volume Down pin.
This pin is switched to the DOWN function when VCEN is set. When DOWN is low, the
master volume output for left and right channels are decremented.

MUTE - Volume Mute

The MUTE pin function can be toggle, momentary, or non-existent based on the VCF1,0 bits.
The MUTE function is enabled when VCEN is set.

Miscellaneous

XTALI - Crystal Input

This pin will accept either a crystal, with the other pin attached to XTALO, or an external
CMOS clock. XTAL must have a crystal or clock source attached for proper operation. The
crystal frequency must be 16.9344 MHz and designed for fundamental mode, parallel resonance
operation.

XTALO - Crystal Output

This pin is used for a crystal placed between this pin and XTALI. If an external clock is used
on XTALI, this pin must be left floating with no traces or components connected to it.

RESDRV - Reset Drive, Input

Places the part in lowest power consumption mode. All sections of the part are shut down and
consuming minimal power. The part is reset and in power down mode when this pin is logic
high. The falling edge also latches the state of XIOR and XIOW to determine the functionality
of dual mode pins. This signal is typically connected to the ISA bus signal RESDRV. RESDRV
must be asserted whenever the part is powered up to initialize the internal registers to a known
state. This pin, when high, also drives the BRESET pin low.

106 DS215PP4
 CS4238B

VREF - Voltage Reference, Output

All analog inputs and outputs are centered around VREF which is nominally 2.1 Volts. This
pin may be used to level shift external circuitry, although any AC loads should be buffered.

REFFLT - Reference Filter, Input

Voltage reference used internal to the part. A 0.1 µF and a 1 µF (must not be bigger than 1 µF)
capacitor with short fat traces must be connected to this pin. No other connections should be
made to this pin.

LFILT - Left Channel Antialias Filter Input

This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.

RFILT - Right Channel Antialias Filter Input

This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.

TEST - Test
This pin must be tied to ground for proper operation.

Power Supplies

VA - Analog Supply Voltage

Supply to the analog section of the codec.

AGND - Analog Ground

Ground reference to the analog section of the codec. This pin should be placed on an analog
ground pin separate from other chip grounds.

VD1 - Digital Supply Voltage

Digital supply for the parallel data bus section of the codec.

DGND1 - Digital Ground

Digital ground reference for the parallel data bus section of the part. These pins are isolated
from the other grounds and should be connected to the digital ground section of the board (see
Figure 33).

VDF1, VDF2, VDF3, VDF4 - Digital Filtered Supply Voltage

Digital supply for the internal digital section of the codec (except for the parallel data bus).
These pins should be filtered, using a ferrite bead, from VD1.

SGND1, SGND2, SGND3, SGND4 - Substrate Ground

Substrate ground reference for the codec . These pins are connected to the substrate of the die.
Optimum layout is achieved by placing SGND1/2/3/4 on the digital ground plane with the
DGND pin as shown in Figure 33.

DS215PP4 107
 CS4238B

PARAMETER DEFINITIONS

Resolution
The number of bits in the input words to the DACs, and in the output words in the ADCs.

Differential Nonlinearity
The worst case deviation from the ideal code width. Units in LSB.

Total Dynamic Range

TDR is the ratio of the RMS value of a full scale signal to the lowest obtainable noise floor. It
is measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e.
attenuation bits for the DACs at full attenuation). Units in dB.

Instantaneous Dynamic Range

IDR is the ratio of a full-scale RMS signal to the RMS noise available at any instant in time,
without changing the input gain or output attenuation settings. It is measured using S/(N+D)
with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal.
Use of a small input signal reduces the harmonic distortion components to insignificance when
compared to the noise. Units in dB.

Total Harmonic Distortion (THD)

THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of
the test signal. THD is measured using an input signal which is 3dB below typical full-scale,
and referenced to typical full scale.

Interchannel Isolation
The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz
0 dB signal present on the other channel. Units in dB.

Interchannel Gain Mismatch

For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units in dB.

Offset Error
For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input
grounded. For the DACs, the deviation in volts of the output from VREF with mid-scale input
code.

108 DS215PP4
 CS4238B

PACKAGE PARAMETERS

D
100-pin TQFP - Package Code ’Q’
D1 Symbol Description MIN NOM MAX
N Lead Count 100
A Overall Height 1.66
A1 Stand Off 0.00
b Lead Width 0.14 0.20 0.26
c Lead Thickness 0.077 0.127 0.177
D Terminal Dimension 15.70 16.00 16.30
D1 Package Body 14.0
E Terminal Dimension 15.70 16.00 16.30
E1 Package Body 14.0
e1 Lead Pitch 0.40 0.50 0.60
E E1 L1 Foot Length 0.30 0.50 0.70
T Lead Angle 0.0° 12.0°

Notes:
1) Dimensions in millimeters.
100

2) Package body dimensions do not include mold protrusion,

1 which is 0.25 mm.
3) Coplanarity is 0.004 in.
4) Lead frame material is AL-42 or copper, and lead finish
is solder plate.
5) Pin 1 identification may be either ink dot or dimple.
L1 e1 b 6) Package top dimensions can be smaller than bottom
dimensions by 0.20 mm.
7) The "lead width with plating" dimension does not include
a total allowable dambar protrusion of 0.08 mm (at
T c maximum material condition).
8) Ejector pin marks in molding are present on every package.
A
A1

DS215PP4 109
 CS4238B

APPENDIX A: TYPICAL MOTHERBOARD E2PROM DATA

; EEPROM Validation Bytes

DB 055H, 0BBH ; EEPROM Validation Bytes: CS4238B

DB 001H ; EEPROM data length upper byte

DB 00FH ; lower byte, Listed Size = 271

; Hardware Configuration Data

DB 000H ; ACDbase Addr. Mask Length = 1 bytes
DB 003H ; COMbase Addr. Mask Length = 4 bytes
DB 080H ; MCB: IHCD
DB 080H ; GCB1: IFM
DB 00BH ; Code Base Byte
DB 020H ; RESERVED
DB 004H ; RESERVED
DB 008H ; RESERVED
DB 010H ; RESERVED
DB 080H ; RESERVED
DB 000H ; RESERVED
DB 000H ; RESERVED

; Hardware Mapping Data

DB 000H ; 00=4/08=8 peripheral port size, XCTL0/XA2
DB 048H ; RESERVED
DB 075H ; IRQ selection A & B - B= 7, A=5
DB 0B9H ; IRQ selection C & D - D=11, C=9
DB 0FCH ; IRQ selection E & F - F=15, E=12
DB 010H ; DMA selection A & B - B= 1, A=0
DB 003H ; DMA selection C - C=3

; PnP Resource Header - PnP ID for CS4238B IC, OEM ID = 42

DB 00EH, 063H, 042H, 038H, 0FFH,0FFH,0FFH,0FFH,037H ; CSC4238 FFFFFFFF
DB 00AH, 010H, 001H ; PnP version 1.0, Vender version 0.1
DB 082H, 009H, 000H, ’CMB4238B’, 000H ; ANSI ID

; LOGICAL DEVICE 0 (Windows Sound System & SBPro)

DB 015H, 00EH, 063H, 000H, 000H, 000H ; EISA ID: CSC0000

DB 082H, 007H, 000H, ’WSS/SB’, 000H ; ANSI ID

DB 031H, 000H ; DF Best Choice
DB 02AH, 002H, 028H ; DMA: 1 - WSS & SBPro
DB 02AH, 009H, 028H ; DMA: 0,3 - WSS & SBPro capture
DB 022H, 020H, 000H ; IRQ: 5 Interrupt Select 0
DB 047H, 001H, 034H, 005H, 034H, 005H, 004H, 004H ;16b WSSbase: 534
DB 047H, 001H, 088H, 003H, 088H, 003H, 008H, 004H ;16b SYNbase: 388
DB 047H, 001H, 020H, 002H, 020H, 002H, 020H, 010H ;16b SBbase: 220

DB 031H, 001H ; DF Acceptable Choice 1

DB 02AH, 00AH, 028H ; DMA: 1,3 - WSS & SBPro
DB 02AH, 00BH, 028H ; DMA: 0,1,3 - WSS & SBPro capture
DB 022H, 0A0H, 09AH ; IRQ: 5,7,9,11,12,15 Interrupt Select 0

110 DS215PP4
 CS4238B

DB 047H, 001H, 034H, 005H, 0FCH, 00FH, 004H, 004H ;16b WSSbase: 534-FFC
DB 047H, 001H, 088H, 003H, 088H, 003H, 008H, 004H ;16b SYNbase: 388
DB 047H, 001H, 020H, 002H, 060H, 002H, 020H, 010H ;16b SBbase: 220-260

DB 031H, 002H ; DF Suboptimal Choice 1

DB 02AH, 00BH, 028H ; DMA: 0,1,3 - WSS & SBPro
DB 022H, 0A0H, 09AH ; IRQ: 5,7,9,11,12,15 Interrupt Select 0
DB 047H, 001H, 034H, 005H, 0FCH, 00FH, 004H, 004H ;16b WSSbase: 534-FFC
DB 047H, 001H, 088H, 003H, 0F8H, 003H, 008H, 004H ;16b SYNbase: 388-3F8
DB 047H, 001H, 020H, 002H, 000H, 003H, 020H, 010H ;16b SBbase: 220-300

DB 038H ; End of DF for Logical Device 0

; LOGICAL DEVICE 1 (Game Port)

DB 015H, 00EH, 063H, 000H, 001H, 000H ; EISA ID: CSC0001

DB 082H, 005H, 000H, ’GAME’, 000H ; ANSI ID

DB 031H, 000H ; DF Best Choice
DB 047H, 001H, 000H, 002H, 000H, 002H, 008H, 008H ;16b GAMEbase: 200

DB 031H, 001H ; DF Acceptable Choice 1

DB 047H, 001H, 008H, 002H, 008H, 002H, 008H, 008H ;16b GAMEbase: 208

DB 038H ; End of DF for Logical Device 1

; LOGICAL DEVICE 2 (Control)

DB 015H, 00EH, 063H, 000H, 010H, 000H ; EISA ID: CSC0010

DB 082H, 005H, 000H, ’CTRL’, 000H ; ANSI ID

DB 047H, 001H, 020H, 001H, 0F8H, 00FH, 008H, 008H ;16b CTRLbase: 120-FF8

; LOGICAL DEVICE 3 (MPU-401)

DB 015H, 00EH, 063H, 000H, 003H, 000H ; EISA ID: CSC0003

DB 082H, 004H, 000H, ’MPU’, 000H ; ANSI ID

DB 031H, 000H ; DF Best Choice
DB 022H, 000H, 002H ; IRQ: 9 Interrupt Select 0
DB 047H, 001H, 030H, 003H, 030H, 003H, 008H, 002H ;16b MPUbase: 330

DB 031H, 001H ; DF Acceptable Choice 1

DB 022H, 000H, 09AH ; IRQ: 9,11,12,15 Interrupt Select 0
DB 047H, 001H, 030H, 003H, 060H, 003H, 008H, 002H ;16b MPUbase: 330-360

DB 031H, 002H ; DF Suboptimal Choice 1

DB 047H, 001H, 030H, 003H, 0E0H, 003H, 008H, 002H ;16b MPUbase: 330-3E0

DB 038H ; End of DF for Logical Device 3

DB 079H, 09EH ; End of Resource Data, Checksum

DS215PP4 111
 CS4238B

APPENDIX B: DIFFERENCES BETWEEN THE CS4236 AND THE CS4238B

This part is designed to be hardware and software backwards compatible with the CS4236 and will
drop into an existing CS4236 socket without any hardware modifications. Properly written code for the
CS4236 will run on the this Codec. However, the CS4238B has enhancements over the CS4236 that
provide extra functionality.
The differences are as follows:
1. CTRLbase+3 is redefined to be an indirect address register and CTRLbase+4 is redefined to be an
indirect data register. These registers allows access to C0 through C8 indirect registers.
2. CDSDD in the Global Configuration byte of the Hardware Configuration data has been renamed
SDD and its function expanded. On this part, setting SDD disables peripheral port reads from driv-
ing the ISA data bus for ALL peripheral port devices, e.g. CDROM and MODEM. On the CS4236,
setting CDSDD disables peripheral port reads for the CDROM device ONLY.
3. The Serial Port works continuously once enabled. CEN and PEN do not have any effect on the se-
rial port. On the CS4236, CEN and PEN disabled their respective part of the serial port when set to
zero.
4. The GAME Logical Device (Joystick) only aliases from GAMEbase+0 to GAMEbase+5. GAME-
base+6 and GAMEbase+7 are reserved. This Codec also contains support for Digital Assist of
analog joysticks to support the Microsoft Direct Input initiative.
5. I25 was defined as a Version and Chip ID register in the CS4236. This register is now redefined as
a Compatibility register and is identical to the CS4236 to allow software written to the CS4236 to
work properly on this part. The Version and Chip ID for this chip has been moved to Control indi-
rect register C1 and WSS indirect register X25 (Rev. C or greater).
6. I27 and I29 in the WSS space are reserved.
7. When IFM is enabled (and remapping is enabled) I18/I19 return the same value written when mute
is enabled. On the CS4236, I18/19 returns 0xBF when mute is enabled.
8 The OLB bit in I16 is no longer functional and internally is set as if OLB is on.
9. The MIC input impedance is now 8 kΩ minimum.

112 DS215PP4
 CS4238B

The added features over the CS4236 are as follows:

10. QSOUND 3D Sound Technology is added and is controlled through C2 and C3 registers.
11. A Wavetable Serial Port interface is added for connection to the CS9236 Single-Chip Wavetable
Music Synthesizer. The pins are multiplexed with the XD7-XD5 pins and are controlled by the
WTEN bit in C8 or the Global Configuration byte in the Hardware Configuration data.
12. The DSP serial port can be multiplexed to the XD4-XD1 pins to allow the DSP serial port and the
second joystick to be used simultaneously. The multiplexing is controlled by the SPS bit in C8 or
the Global Configuration byte in the Hardware Configuration data.
13. Hardware volume control supports 4 formats.
14. New bits are added to the Global Configuration byte of the Hardware Configuration data:
VCF1 and VCF0 Hardware Volume Control Format bits
SLAD which disables Sound Blaster Synthesis volume changes from affecting LINE volume.
WTEN to enable the Wavetable Serial Port
SPS to switch the DSP serial port pins from the second joystick to the XD4-XD1 pins
15. The Consumer digital audio transmission format supported on the DSP serial port through the C4-
C6 registers is new.
16. Serial Port Format 3 (I16) is a new DSP serial port format.
17. A symmetrical mixer (the input mixer is new) is included and is supported by a new mode,
MODE 3. This mode is enabled by setting the CMS1,0 bits in WSS I12 to 11. Note that the
CS4236 MODE2 bit has been renamed CMS1 (Codec Mode Select 1). CMS1 is backwards compat-
ible with the CS4236 MODE2 bit.
18. The MIC can be mixed directly to the output mixer with full volume control.
19. Hardware Configuration byte 9 was reserved in the CS4236 (at 0x43) and is now used as a Code
Base Byte that determines the firmware code compatibility in the E2PROM. When firmware code
for this part is loaded in the E2PROM this byte must be changed to 0x0B. This provides backwards
compatibility by ignoring CS4236-based firmware code, which has this byte set to 0x43, while still
reading the Hardware Configuration and PnP data from CS4236-programmed E2PROM.
20. 3.3 Volt ISA bus support is added. This includes all ISA pins except DRQA (which still runs at
5 Volts). When the VD1 pin is powered from a 3.3 Volt supply, the ISA bus connected to it must
also run at 3.3 Volts.

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