APPROACH TO DESIGN FOR STABILITY A SYSTEM COMPRISING A NON-IDEAL

CURRENT SOURCE AND A GENERIC LOAD

Ferdinando Tonicello (1), Christophe Delepaut (1), Manuel Martin Alfonso(1), Tatiana Perez Soriano(1), Tobias
Kuremyr (1), Mariel Triggianese(1)
(1)
ESA-ESTEC, Noordwijk, The Netherlands, Email: Ferdinando.Tonicello@esa.int,
Christophe.Delepaut@esa.int, Manuel.Martin@esa.int, Tatiana.Perez.Soriano@esa.int,
Tobias.Kuremyr@esa.int, Mariel.Triggianese@esa.int

ABSTRACT 2. ASSUMPTIONS
A systematic approach is presented, allowing the The proposed approach should be valid in any case
verification of the stability of a system comprising a when small signal stability has a sense, e.g. if one can
non-ideal current source and a generic load. The linearize the system under analysis around a given
proposed approach is based on a three-step verification operational point. It is anyhow necessary to run the
method, and on the check of the stability of the system approach for a number of possible operating points, if
by application of source-load interface requirements the linearised system (the relevant poles and zeroes of
control. It allows to verify that the combination of the the transfer functions of interest) depends from the
non-ideal current source connected to specific loads selected operating point. For example, if the current
results in a stable system without the need of source is based on the current provided at the drain of a
performing intrusive verifications (e.g. accessing and power MOSFET, it is known that the relevant trans-
opening the control loop for each load case). The conductance DC gain, and gate to source, source to
approach seems specifically useful in relation to power drain, and gate to drain capacitances are function of the
distribution systems based on latching or fold-back DC operating point (current and voltage). As a
current limiters, which are widely used in European consequence, the control loop built around the power
space power industry. MOSFET has to be studied for a number of applicable
operating points to be sure that stability is ensured for
1. INTRODUCTION each one of them.
The design of the stability of an electrical system
3. DESCRIPTION OF PROPOSED APPROACH
comprising a non-ideal current source and a generic
load might become rather difficult when the possible
dynamic load characteristics can vary over a wide
range.
The main issue is that the stability of the non-ideal
current source depends heavily on the nature of the
load. A typical case is the design of a latching current Figure 1. Linearising the non-ideal current source
limiter when a number of possible loads are considered:
it soon appears very difficult to size for stability of the First of all, let us identify all DC currents and voltages
current limiter loop when the envelope of the possible with capital letters (e.g. Io, I1, V1, V2, etc) while
loads is taken into account (including failure scenarios, variations around the operating point are identified with
harness contribution, common an differential mode small cap letters (e.g. . io, i1, v1, v2, etc).
filter design options, etc). Let us give a look to Fig.1.
The proposed approach is based on a three-step The (linearised!) current source circuit is described with
verification method, and on the check of the system a Norton equivalent network, comprising an ideal
stability by application of source-load interface current source (isource) with a impedance (ZSc) in parallel.
requirements control. It seems to have an undoubted It is possible in any case to describe a linear (or
advantage over the study of the current loop stability linearised network) in this way, also if a relevant control
with the conventional Bode or Nyquist approach applied loop is present and/or if dependent voltage or current
for each load case, especially because the load nature sources are present in the current source circuit.
might not be known in detail to the designer of the Note that the isource is not related to the DC current
current source from the beginning, and it might be source Io: according to the Mayer-Norton’s theorem
difficult, if not impossible, to practically run the ([2], [3]), the current source isource represents the current
analysis for all load envelope cases. variations given by the relevant circuit in short-circuit
conditions and the impedance ZSc represents the
differential impedance read at the terminals of the
current source circuit when all independent voltage or
current sources are set to zero. the output voltage Vo to the expected DC value will not
If the current source circuit is supposed to regulate DC allow to have information about the output impedance
current, and no other “variation” source is identified (for ZSc (see Fig.1 or Fig. 2), since whatever its value is, the
example, due to power supply ripple injection, or impedance will be short-circuited by the application of a
modulation due to noise sources) then isource can be fixed DC voltage (e.g. the relevant variation will be
removed (e.g. it is substituted by an open circuit). vo=0).
In any case isource can also be identified with the
generator reporting the adjustments to the output current 3.2 Step 2: analyse current loop stability of the current
required by the internal control loop (see the example source circuit
made in Fig.2, where the voltage reference to the After setting the required DC voltage at the output of
current loop vref is normally giving a DC reference, e.g. the current source circuit, and having performed the
vref = 0). linearization around the DC operating point, the relevant
loop stability can be analysed and optimised.
For space power purposes, it might be convenient to
define minimum stability criteria for the loop: it is
advised to follow the indications of standard [7], e.g.
ensure a phase margin of 50° and a gain margin of
10dB.
It is easy to demonstrate that if the circuit is the one of
Fig.2 and vref=0, then the closed loop impedance ZSc is

Figure 2. Non ideal current source with internal ∙ ∙ 1 ∙ (1)

control loop
e.g. it is equal to the open loop output impedance ZS
Note that the actual position of the current sensor may increased by a factor equal to the open loop gain
differ from the one shown in Fig.2, and that additional (1+Z·Y), where Y is the direct transfer of the loop (Y=
transfer functions and impedances might be present in isource/ ve) and Z is the feedback transfer function
the loop of regulation from the point where the current (Z=vf/io).
sensor reads the current and the position of the In general, the highest the loop gain, the larger ZSc will
equivalent source isource. For example, normally in a be. Note that the common aim is to get the highest
current limiter the current sensor is in series with a p- possible output impedance of the current source for all
channel power MOSFET source, while the output frequencies (e.g. to approximate as much as possible an
current appears at the relevant drain. In any case the ideal current source, and increase the chances of
equivalent circuit shown in Fig.1 remains valid, in case independent behaviour with respect to any load – see
the additional transfer functions can be introduced from also step 3). Before then implementing the second
the point of regulation to the output as required. stability check (step 3), it is then generally convenient
to design the current control loop with high bandwidth
3.1 Step 1: fix the operating point, and linearise the and the best achievable gain and phase margins.
circuit around it
3.3 Step 3: perform the stability check applied to the
First of all, let us make an important observation. ratio of source and load impedances
With reference to Fig.1, when an operating point is
fixed, it is clear that the linearised networks that appear With reference to Fig.1, , in absence of the source output
at the left (current source circuit) and at the right (load) impedance ZSc, (e.g. assuming that ZSc, is infinite, or
of the connection point will have poles and zeroes, replaced by an open circuit), the current into the load
transfer functions and impedances that do not depend on would only depend on the equivalent current source
the other network ones, but just on the selected isource, and therefore, if the impedance ZL is stable (e.g.
operating point. there are no poles in it with positive real part), no
In particular, the current source circuit, including its additional stability check would be required.
internal control loop, can be studied and optimised by The (unavoidable) presence of the source impedance ZSc
fixing the relevant output voltage Vo to the expected requires though an additional stability check. With
DC value. The relevant controlled current Io will result reference to Fig.1, it is easy to derive that the quantity
in consequence of the relevant voltage application. that we want to keep under control ( the current into the
Of course if the relevant transfer functions poles and load io ) is linked to the current provided by the ideal
zeroes depend on the operating point, the control loop source isource by the following relationship:
analyses shall be performed for a set of different
operating points (power supply voltage levels, output (2)
voltage levels, etc). Note that the effect of having fixed
It is convenient observing that there is a complete requirement for a simple application of the Bode
analogy between the verification of the stability of a stability criterion) is not satisfied, and some
generic control loop and the one relevant to the ratio of revised/enhanced method is required:
source and load impedance shown in Eq.2.
For the control loop example shown in Fig.3, the Revised Bode Stability Criterion for control loops
stability analysis has to be performed on the equation (sufficient condition for stability):
(2), where the “critical” analysis refers to the open loop
gain - product G·H - and can be performed with the A closed-loop system is stable if the open loop is
Nyquist or Bode criteria. stable and the frequency response of the open-loop
transfer function has an amplitude ratio of less than
unity at all frequencies corresponding to θ =-180°-
n*360°, where n=0,1,2,...,∞.
Revised Bode Stability Criterion (from [1]).

If we apply the revised criterion above to the ratio io /

isource given in Eq.2, we can summarise it as follows:
Revised Bode Stability Criterion for equation 2
(sufficient condition for stability):
Figure 3. Conventional control loop example
The ratio io / isource given in equation 1 is stable if the
(3) ratio ZL/ZSc is stable and if the frequency response of
∙
the ratio ZL/ZSc has an amplitude ratio of less than
unity at all frequencies corresponding to θ =-
The verification of stability of Eqs. 2 and 3 can be 180°±n*360°, where n=0,1,2,...,∞.
performed using the same theoretical tools (Nyquist or
Bode), with the only difference that the open loop gain
G·H in Eq.3 is now substituted by the ratio of load to In order to be sure to avoid poorly damped transients, it
source impedance ZL /ZSc in Eq.2 is anyhow convenient to identify some additional
For people non-familiar with the application of the stability margins: minimum phase margin (5dB or so)
Nyquist criterion, it is suggested to make use of revised when the modulus of ZL/ZSc is equal to 1, minimum
(extended) Bode criteria, as it is explained in [1]. gain margin (30° or so) when the phase of ZL/ZSc is
In fact, it is frequent that the ratio of load/source equal to =-180°±n*360°, where n=0,1,2,...,∞.
impedance shown in Eq.2 often results in multiple The negative sign before n*360 has been added to take
crossings of the zero dB line and/or the -180°- n·360° into account that the ratio of impedances in Eq.2 does
phase line (n=0,1,2,3…). not necessarily show a delay between injected and
As a consequence, the usual monotonic reduction of the response signal as it normally happens in conventional
open loop gain with frequency (that is the normal control loops.

Figure 4. Implementation example 1

4. FIRST EXAMPLE OF APPLICATION 90V, 130V), an AC analysis is performed after setting
V16=1V AC in the circuit of Fig.5.
Let us consider the linear current regulator shown in
Fig.4. The example is taken by a real design case for a 11.75A

terrestrial application, and represents a very difficult

control and impedance matching problem. 11.70A

The block CM1 is a DC/DC ideal transformer that

multiplies the current at the left of the relevant insertion 11.65A

point to the number n_MOS (n_MOS=12 in our

example). The linear regulator is supposed to work to 11.60A

cover load transients for any input voltage from 20 to

150V, and with a output voltage going from 0 to 130V. 11.55A

In steady state conditions the source voltage V2 is

adjusted to reduce the voltage drop across the linear 11.50A

regulator to 20V maximum (with a low bandwidth

control). 11.45A
-40 -20 0 20 40 60 80 100

The linear regulator need to provide current to a ... I(V17)

TEMP

capacitive load (C18) and to a user shunt system (M3 Figure 6. Example 1, DC temperature sweep
and surrounding components) through some meters of
harness (relevant resistance is R7 and inductance is L1, The Bode diagram, shown in Fig.7, shows satisfactory
both function of the harness length Lh). Some RC results(bandwidth equal to 1.8 to 2.3MHz, phase margin
damping of the load is necessary (see the series R21 and higher than 57°, gain margin higher than 10dB).
C19).
80

4.1 Step 1: fix the operating point, and linearise the 40

circuit around it
0

The linear regulator is disconnected from the load and

applied a DC output voltage varying in steps from 0V to SEL>>
-40

130V in steps of 10V (voltage source V17), as shown in 200

db(v(a))-db(v(b)) 0

Fig.5.
The DC analysis performed by varying the temperature 100

between -40 to 100 °C and by parametrically changing

the DC output voltage as mentioned proves the good 0

DC stability of the circuit (see Fig.6).

-100
100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz
p(v(a))-p(v(b)) 0
Frequency

Figure 7. Example 1, Bode diagram

4.3 Step 3: perform the stability check applied to the

ratio of source and load impedances

After setting the AC voltage source V16 to 0V, and AC

current source I3 to 1A (see Fig.4), the source and load
impedances can be directly compared (by evaluating
respectively ZSc = V(P)/I(VM1) and ZL= V(P)/I(VM2)).
The analysis is performed parametrically changing the
input voltage V2 to the values xxV, 100V and 150V.
Note that an input voltage higher than xxV is needed to
allow the minimum guaranteed voltage drop across the
Figure 5. Example 1, step 1 linear regulator when output voltage is zero (xxV
depending on the harness resistance).
Note that the linearization of the circuit around the Each analysis is done for a different harness length (3m,
operating point is done automatically by PSPICE when 10m, 30m).
running the AC analysis (see step 2). The value of xxV is set accordingly and respectively to
43V (3m), 46 (10m) and 53V (30m).
4.2 Step 2: analyse current loop stability of the In the impedance plots (Fig. 8, 9 and 10), the phase is
current source circuit evaluated with a sign inversion for practical reasons
(e.g. the critical checks according to the above
For each DC step of the source V17 (0V, 30V, 60V,
mentioned Revised Bode Stability Criterion have to be It is clear that the system as it is requires at least 3m of
performed at the frequencies corresponding to phase θ harness, or equivalent inductance / resistance, to have a
=+180°+n*360°, where n=0,1,2,...,∞). minimum gain margin with respect to the above
In general, there are only two crossing point to the mentioned Revised Bode Stability Criterion.
critical phase value for all harness length and all input This is clear if you give a look to Fig.11 where the
voltages under analysis, one at low frequency (around harness length has been reduced to 0.1m with
30-40 KHz) and another at higher frequency (at Vin=42.5V: the gain margin at approximately 2.1 MHz
approximately 80 to 330KHz). For all the other cases is –12.6dB, and the Revised Bode Stability Criterion is
the margin is higher (around 10dB for the+180° phase not satisfied.
crossing point with the highest frequency and the
minimum input voltage value).
100

50
100

0
50

-50
0

-100
-50 db(v(p))-db(i(vm1)) db(v(p))-db(i(vm2))
600

-100
db(v(p))-db(i(vm1)) db(v(p))-db(i(vm2))
600 400

400 200

SEL>>
200 0
100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz
-p(i(vm1))+p(i(vm2)) 180 180+360
SEL>> Frequency
0
100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz Figure 10. Source-load impedance ratio for harness
-p(i(vm1))+p(i(vm2)) 180 180+360
Frequency length of 30m, Vin =53, 100 and 150V.
Figure 8. Source-load impedance ratio for harness
100
length of 3m, Vin =43, 100 and 150V.
50
100

0
50

-50
0
SEL>>
-100
-50 db(v(p))-db(i(vm1)) db(v(p))-db(i(vm2))
600
SEL>>
-100
db(v(p))-db(i(vm1)) db(v(p))-db(i(vm2))
600 400

400 200

200 0
100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz
-p(i(vm1))+p(i(vm2)) 180 180+360
Frequency
0
100Hz 1.0KHz 10KHz 100KHz 1.0MHz 10MHz Figure 11. Source-load impedance ratio for harness
-p(i(vm1))+p(i(vm2)) 180 180+360
Frequency length of 0.1m, Vin =42.5V.
Figure 9. Source-load impedance ratio for harness
length of 10m, Vin =46, 100 and 150V. Note that the Revised Bode Stability Criterion just give
a sufficient and not a necessary condition for stability!
For all critical phase crossing points, there is a It means that in the case shown in Fig.11 we cannot
minimum of gain margin (e.g. the amplitude of the confirm that the stability is achieved. The final stability
source impedance is higher than the load impedance). check can be done either by application of the Nyquist
The worst condition (about 5dB margin) is found at criterion, or simply by transient analysis. Let us opt for
harness length of 3m and for the minimum input voltage the (simpler) verification by transient analysis.
of 43V. In Fig.12 a transient analysis plot is shown, where in the
For all the other cases the margin is higher (around 9- circuit of Fig.4 the shunt device built around the
10dB for the+180° phase crossing point with the highest MOSFET M3 is activated. Fig.12 shows the MOSFET
frequency and the minimum input voltage value). command voltage V(CMD), the current provided by the
linear current regulator on the harness I(R7) and the
20V

waveform of a current provided to another shunt stage 10V

by an ideal current source (same current as the linear
current regulator) and loaded by a 100nF capacitor (C10 SEL>>
0V
in Fig.4). 20A
V(CMD)

The behaviour is indeed not acceptable. There is a

persistent oscillation at approximately 1.2MHz when 10A

the shunt switch is open, and another one (lower

amplitude) at around 2MHz when the shunt switch is 0A

closed.
I(R7)
20A
20V

10A
10V

SEL>> 0A
0V 159.6us 200.0us 250.0us 282.6us
V(CMD) I(R13)
40A Time

Figure 13. Shunt operation for harness length of 3m,

20A
Vin =43V.

The circuit has been breadboarded and tested in our

0A
I(R7)
40A
laboratory.
20A
The current sensing and amplifier circuit is of common
application, there is an additional amplification stage
0A that is not revealed due to similarity with industrial
159.6us
I(R13)
200.0us 250.0us 282.6us
solutions.
The current limiter is loaded by an inductive load (LM)
Time

Figure 12. Shunt operation for harness length of 0.1m, and a resistive one (RL), that can be short circuited by
Vin =42.5V. an external switch (U1 in Fig.14; in the lab has been
realised with manual short circuit connection).
On the other side, the operation of the linear current At the output of the current limiter an optional damping
regulator when the shunt action is activated for all cases RC network (Rd, Cd) has been considered (but not
mentioned before (and for which the revised Bode implemented since the beginning).
criterion confirm stability) is acceptable (see following To avoid current oscillations to be damped on short
Fig.13, and relevant to the worst case condition - 43V circuit applications, the output diode D2 has been not
input and 3m harness -, the quantities shown being the mounted.
same described for Fig.12).
5.1 Step 1: fix the operating point, and linearise the
5. SECOND EXAMPLE OF APPLICATION circuit around it
Let us consider the linear current regulator shown in The current limiter has been characterised in our
Fig.14. The example is taken by a real design case for a laboratory, the DC current limit value has been set and
latching current limiter. verified at 1A.

Figure 14. Implementation example 2

5.2 Step 2: analyse current loop stability of the
current source circuit

The current limiter output (point P in Fig.14) has been

connected either to a short circuit or to a fixed voltage
source of 5 and 10VDC.
The excitation voltage for the current limiter loop
characterisation has been provided with an Agilent
network analyser (model 4935A) at the position of V11
in Fig.14 by a hand-made transformer constituted by a
Tektronics AC probe (model P6012), a winding of 20
turns of enamelled copper wire with a resistor of 1 Ohm
in parallel.
The signals appearing at the points A and B in Fig.14
have been made available to the relevant A and R inputs
of the network analyser.
The relevant current limiter open loop transfer function
is given in Fig.15 (output short circuit: blue trace;
output at 5VDC: red trace; output at 10VDC: green
trace).
Figure 16. Example 2, source-load impedance ratio

The phase of the load inductor impedance is not shown,

being equal to 90° in all the frequency range of interest.
The closest situation to an instable ratio according to the
revised Bode criterion is at 5KHz, for the largest
inductor value (1mH) and for the highest output DC
voltage considered (10V): in this case the load-source
phase difference is approximately 90-(-86)=176°. This
is not a instability condition, but the stability margin to
is rather small in this case, as it is for all other inductor
values considered.
The situation is indeed confirmed by the application of a
sudden short circuit at the output, as shown in Fig 17
(the initial condition being a load current equal to
0.77A).

Figure 15. Example 2, Bode diagrams

The control loop bandwidth varies between 120KHz

Time
(10VDC at the output) and 420KHz (output short
circuit), with a phase margin better than 60° and a Figure 17. Example 2, transient on output short circuit
assumed gain margin better than 10dB.
To improve the situation, a practical solution is to add
5.3 Step 3: perform the stability check applied to the the RC damping network shown in Fig.14, with a
ratio of source and load impedances capacitor large enough to cause a resonance with the
max inductance (1mH) at frequency lower than 5KHz
The current limiter output impedance has been (selection: Cd=3uF for resonance at approximately
measured placing at the current limiter output the 2.9KHz), and a resistor Rd in series to keep the
voltage excitation (obtained by the transformer built as resonance peak sufficiently lower (about 5dB) from the
described in para 5.2) on a DC voltage level equal to 0V current limiter output impedance (Rd=15 Ohm, for a
(short circuit), 5V and 10V. The stability check has margin of about 7dB).
been performed with inductive load (LM in Fig. 14) Such provision gives enough margin also for the other
equal to 10, 100 and 1000 uH, see Fig. 16. load inductance cases, as shown in Fig.18.
 6. CONCLUSIONS
An approach has been presented that allows in a three-
step procedure to optimise the stability performances of
a generic (real) current source, in relation to the
impedance of the source itself when connected to a
generic load. The main advantages of the presented
approach is the possibility to optimise independently the
current source dynamic behaviour and to specify clear
interface requirements for the source and load
impedances in order to preserve the overall system
stability: when the source impedance is known with its
envelope of variability, it is possible to specify clear
criteria to the load impedance in order to guarantee the
overall stability performances of the system.
This seems to be a major advantage especially in
relation to power distribution systems based on latching
or fold-back current limiters.
Figure 18. Example 2, source-load impedance ratio
with RC damping circuit (Rd=15 Ohm, Cd=3uF) 7. REFERENCES
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The effect of the RC damping network is completely analysis using Bode plots, Chemical Engineering
confirmed in time domain, when performing a short Education Journal, Summer 2001, Vol. 35 No.3
circuit transient a the output of the current limiter, see http://citeseerx.ist.psu.edu/viewdoc/download?doi
Fig.19. =10.1.1.120.4683&rep=rep1&type=pdf

2. Norton, E. L. (1926). Technical Report TM26–0–

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3. H. F. Mayer, “Ueber das Ersatzschema der

Verstärkerröhre [On equivalent circuits for
electronic amplifiers],” Telegraphen- und
Fernsprech-Technik, vol. 15, pp. 335–337, 1926.

4. Middlebrook, R.D.; , "Null double injection and

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5. Riccobono, A. ; Santi, E., Comprehensive review

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systems,Energy Conversion Congress and
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Figure 19. Example 2, transient on output short circuit

with RC damping circuit