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    CST202 QP

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    Sreedevi R Krishnan
    APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY Fourth Semester B.Tech Degree Examination June 2022 (2019 scheme)

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    CST202 QP

    Uploaded by

    Sreedevi R Krishnan
    70 views2 pages
    APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY Fourth Semester B.Tech Degree Examination June 2022 (2019 scheme)

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    CST202-QP

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    APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY Fourth Semester B.Tech Degree Examination June 2022 (2019 scheme)

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    70 views2 pages

    CST202 QP

    Uploaded by

    Sreedevi R Krishnan
    APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY Fourth Semester B.Tech Degree Examination June 2022 (2019 scheme)

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 2

    B 02000CST202052101 Pages: 2

    Reg No.:_______________ Name:__________________________


    APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY
    Fourth Semester B.Tech Degree Examination June 2022 (2019 scheme)

    Course Code: CST202


    Course Name: Computer Organization and Architecture
    Max. Marks: 100 Duration: 3 Hours
    PART A
    (Answer all questions; each question carries 3 marks) Marks
    1 Describe auto increment and decrement addressing mode with help of 3
    example?
    2 Name the registers which are connected to both external and internal bus? What 3
    are the signals associated with these registers?
    3 Write the register transfer logic format for a conditional control statement, Give 3
    an example?
    4 Discuss the logic used behind the booth multiplication algorithm 3
    5 Draw a 3X2 array multiplier? 3
    6 Discuss about pipeline hazards? 3
    7 Write a note on micro-program control? 3
    8 What are different types of control organization? 3
    9 What are interrupts, List the sequence of steps following an interrupt request? 3
    10 Which design feature of SRAM cells helps in value retention without refresh? 3
    PART B
    (Answer one full question from each module, each question carries 14 marks)
    Module -1
    11 a) Compare and contrast single bus and multi-bus organization of CPU? 4
    b) Write the three-address, two-address and one-address representations of the 10
    operation below with relevant assumptions, evaluate following:
    i, (A+B) * (C+D)
    ii, C<- [A] + [B]
    12 a) With the help of a neat figure, describe the data path inside the processor? 6
    b) Draw the diagram of single bus organization, write the control sequence for the 8
    instruction ADD [R2],R3 for the above mentioned single bus organization.
    Module -2
    13 a) Describe processor organization with diagram using i) scratchpad memory 10
    ii) Two-port memory iii) Accumulator register

    b) Draw and explain about true/complement circuit? 4

    Page 1 of 2
    02000CST202052101

    14 a) Give the structure of status register, which is connected to 8bit ALU . 8


    b) Design 4-bit combinational logic shifter which will perform the operation given 6
    below with 2 control variable H1&H0?
    i) Shrl
    ii) clear
    iii) Load all bits with 1
    Module -3
    15 a) Draw the flowchart and explain restoring division method with an example? 6
    b) Describe in detail about data hazards and resolution techniques? 8
    16 a) Draw the flowchart of Booth's multiplication algorithm and multiply -5 X -4 8
    using booths algorithm?
    b) Identify the various types of hazards occurring during the execution of the 6
    following program in a pipelined system. Where the pipeline consist of five
    stages, opcode fetch , instruction decode, operand fetch, execution, store the
    result. All stages take equal time duration

    MOV [R1],[R2]
    MOV R3,[R1]
    SUB R2,R3
    ADD R1,R3
    CALL 5000
    MOV R2,R3
    Module -4
    17 a) With the help of a diagram explain the functioning of a micro-program 10
    sequencer in a micro-programmed controlled processor?
    b) Compare instruction formats of horizontal and vertical microinstructions? 4
    18 a) Explain the organization of micro-programmed computer with a block 8
    diagram?
    b) Explain with an example one flip-flop per state method of control organization? 6
    Module -5
    19 a) Explain in detail about the mechanisms for accessing I/O devices? 9
    b) Discuss about different types of read only memories? 5
    20 a) Explain internal organization of 1 K X 8 memory chip with suitable diagram 5
    b) How does the various mapping scheme present in cache memory differ from each 9
    other.

    ***

    Page 2 of 2

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