Applied II Note

A.
A Science and Technology University School of Electrical Engineering and Computing
Chapter One
Feedback Amplifiers
A feedback amplifier is one in which a fraction of the amplifier output is fed back to the input
circuit. This partial dependence of amplifier output on its input helps to control the output. A
feedback amplifier consists of two parts: an amplifier and a feedback circuit.
(i) Positive feedback

If the feedback voltage (or current) is so applied as to increase the input voltage (i.e. it is in phase
with it), then it is called positive feedback. Other names for it are: regenerative or direct
feedback. Since positive feedback produces excessive distortion, it is seldom used in amplifiers.
However, because it increases the power of the original signal, it is used in oscillator circuits.
(ii) Negative feedback

If the feedback voltage (or current) is so applied as to reduce the amplifier input (i.e. it is 180°
out of phase with it), then it is called negative feedback. Other names for it are: degenerative or
inverse feedback. Negative feedback is frequently used in amplifier circuits.
Principle of Feedback Amplifiers

For an ordinary amplifier i.e. one without feedback, the voltage gain is given by the ratio of the
output voltage Vo and input voltage Vi. As shown in the block diagram of Fig. 1.1, the input
voltage Vi is amplified by a factor of A to the value Vo of the output voltage.
Fig. 1.1
A = Vo /Vi
This gain A is often called open-loop gain.
Dept. Electrical & Electronics Eng Applied Electronics II (EEEG – 2202) Prepared by: Sh. F 1
A.A Science and Technology University School of Electrical Engineering and Computing
Suppose a feedback loop is added to the amplifier (Fig. 1.2). If Vo´ is the output voltage with
feedback, then a fraction β* of this voltage is applied to the input voltage which, therefore,
becomes (Vi ± βVo´) depending on whether the feedback voltage is in phase or antiphase with it.
Assuming positive feedback, the input voltage will become (Vi + βVo´). When amplified A
times, it becomes A(Vi + βVo´).
Fig 1.2
Therefore
A (Vi + βVo´) = Vo´
or
Vo´ (1 – βA) =AVi
The amplifier gain A´ with feedback is given by
is called positive feedback
is called negative feedback
The term ‘βA’ is called feedback factor whereas β is known as feedback ratio. The expression (1
± βA) is called loop gain. The amplifier gain A´ with feedback is also referred to as closed loop
gain because it is the gain obtained after the feedback loop is closed. The sacrifice factor is
defined as S = A/A´.
(a) Negative Feedback

The amplifier gain with negative feedback is given by
Obviously, A´ < A because | 1 + βA | > 1.

Suppose, A = 90 and β = 1/10 = 0.1
Then, gain without feedback is 90 and with negative feedback is
As seen, negative feedback reduces the amplifier gain. That is why it is called degenerative
feedback. A lot of voltage gain is sacrificed due to negative feedback. When | βA | » 1, then
It means that A´ depends only on β. But it is very stable because it is not affected by changes in
temperature, device parameters, supply voltage and from the aging of circuit components etc.
Since resistors can be selected very precisely with almost zero temperature-coefficient of
resistance, it is possible to achieve highly precise and stable gain with negative feedback.
(b) Positive Feedback

The amplifier gain with positive feedback is given by
Since [1- βA] 1,
Suppose gain without feedback is 90 and β = 1/100 = 0.01, then gain with positive feedback is
Since positive feedback increases the amplifier gain. It is called regenerative feedback. If βA =
1, then mathematically, the gain becomes infinite which simply means that there is an output
without any input! However, electrically speaking, this cannot happen. What actually happens is
that the amplifier becomes an oscillator which supplies its own input. In fact, two important and
necessary conditions for circuit oscillation are
1. The feedback must be positive,
2. Feedback factor must be unity i.e. βA = +1
Advantages of Negative Feedback

The numerous advantages of negative feedback are:
1. higher fidelity i.e. more linear operation
2. highly stabilized gain
3. increased bandwidth i.e. improved frequency response
4. less amplitude distortion
5. less harmonic distortion
6. less frequency distortion
7. less phase distortion
8. reduced noise
9. input and output impedances can be modified as desired
Example 1.1
In the series-parallel (SP) feedback amplifier of Fig. 1.3, calculate
(a) open-loop gain of the amplifier (c) closed-loop gain of the amplifier
(b) gain of the feedback network (d) sacrifice factor, S
Fig 1.3
Solution
(a) Since 1 mV goes into the amplifier and 10 V comes out
(b) The feedback network is being driven by the output voltage of 10 V.

Gain of the feedback network β
(c) So far as the feedback amplifier is concerned, input is (250 + 1) = 251 mV and final
output is 10 V.
Hence, gain with feedback is
A´ = 10 V/251 mV = 40
(d) The sacrifice factor is given by
Example 1.2
Calculate the gain of a negative feedback amplifier whose gain without feedback is 1000 and β =
1/10. To what value should the input voltage be increased in order that the output voltage with
feedback equals the output voltage without feedback?
Solution
Since | βA | » 1, the closed-loop gain is
The new increased input voltage is given by

Vi´ = Vi (1 + βA) = 50 (1 + 0.04 × 100) = 250 mV
Gain Stability
The gain of an amplifier with negative feedback is given by
Taking logs of both sides, we have loge A´ = loge A – loge (1 + βA)

Differentiating both sides, we get
If βA » 1, then the above expression becomes
Example 1.3
An amplifier has an open-loop gain of 400 and a feedback of 0.1. If open-loop gain changes by
20% due to temperature, find the percentage change in closed-loop gain.
Solution
Here, A = 400, β = 0.1, dA/A = 20% = 0.2
Now,
It is seen that while the amplifier gain changes by 20%, the feedback gain changes by only 0.5%
i.e. an improvement of 20/0.5 = 40 times
Feedback over Several Stages

Multistage amplifiers are used to achieve greater voltage or current amplification or both. In such
a case, we have a choice of applying negative feedback to improve amplifier performance. Either
we apply some feedback across each stage or we can put it in one loop across the whole
amplifier.
A multistage amplifier is shown in Fig. 1.4. In Fig. 1.4 (a) each stage of the n-stage amplifier has
a feedback applied to it. Let A and β1 be the open-loop gain and feedback ratio respectively of
each stage and A1 the overall gain of the amplifier. Fig. 1.4 (b) shows the arrangement where n
amplifiers have been cascaded in order to get a total gain of An. Let the overall feedback factor
be β2 and the overall gain A2. The values of the two gains are given as
Fig. 1.4
Differentiating the above two expressions, we get
For the two circuits to have the same overall gain, A1 = A2. Hence, from Eqn. (i) above, we get
If n = 1, then the denominator in the above equation becomes unity so that fractional gain
variations are the same as expected. However, for n > 1 and with (1 + Aβ1) being a normally
large quantity, the expression dA2/A2 will be less than dA1/A1. It means that the overall feedback
would appear to be beneficial as far as stabilizing of the gain is concerned.
Example 1.4
An amplifier with 10% negative feedback has an open-loop gain of 50. If open-loop gain
increases by 10%, what is the percentage change in the closed-loop gain?
Solution
Let and be the closed-loop gains in the two cases and A1 and A2 the open-loop gains
respectively.
(i)
(ii) When open-loop gain changes by 10%, then A2 = 50 + 0.1 × 50 = 55
Percentage change in closed-loop gain is
Example 1.5
Write down formulae for (i) gain (ii) harmonic distortion of a negative feedback amplifier in
terms of gain and distortion without feedback and feedback factor. If gain without feedback is 36
dB and harmonic distortion at the normal output level is 10%, what is (a) gain and (b) distortion
when negative feedback is applied, the feedback factor being 16 dB.
Solution
Distortion ratio is defined as the ratio of the amplitude of the largest harmonic to the amplitude
of the fundamental.
Now, dB gain = 20 log10 A

36 = 20 log10 A, A = 63
dB feedback factor = 20 log10 βA
16 = 20 log10 βA or βA = 6.3
(a) Af = A/(1 + βA) = 63/(1 + 6.3) = 6.63 or 18.72 dB

(b) D´ = 10 per cent/ (1 + 6.3) = 1.4 per cent
Increased Bandwidth
The bandwidth of an amplifier without feedback is equal to the separation between the 3 dB
frequencies f1 and f2.
BW = f2 – f1
Where f1 = lower 3 dB frequency, and f2 = upper 3 dB frequency. If A is its gain, the gain-
bandwidth product is A × BW.
Now, when negative feedback is applied, the amplifier gain is reduced. Since the gain-bandwidth
product has to remain the same in both cases, it is obvious that the bandwidth must increase to
compensate for the decrease in gain. It can be proved that with negative feedback, the lower and
upper 3 dB frequencies of an amplifier become.
Fig. 1.5
As seen from Fig. 1.5, f1´ has decreased whereas f2´ has increased thereby giving a wider
separation or bandwidth. Since gain-bandwidth product is the same in both cases.
A × BW = A´ × BW´ or A (f2 – f ´1) = A (f ´2 – f ´1)
Example 1.6
An RC-coupled amplifier has a mid-frequency gain of 200 and a frequency response from 100
Hz to 20 kHz. A negative feedback network with β = 0.02 is incorporated into the amplifier
circuit. Determine the new system performance.
Solution
f2 ´ = f0 (1 + βA) = 20(1 + 0.02 × 200) = 100 Hz

dW´ = f2´– f1´ 100 kHz
Incidentally, it may be proved that gain-bandwidth product remains constant in both cases.
dW = f2 – f1 20 kHz
A × dW = 200 × 20 = 4000 kHz;
A´ × dW´= 40 ×100 = 4000 kHz
As expected, the two are equal.
Forms of Negative Feedback
The four basic arrangements for using negative feedback are shown in the block diagram of Fig.
1.6. As seen, both voltage and current can be feedback to the input either in series or in parallel.
The output voltage provides input in Fig. 1.6 (a) and (b). However, the input to the feedback
network is derived from the output current in Fig. 1.6 (c) and (d).
(a) Voltage-series Feedback

It is shown in Fig. 1.6 (a). It is also called shunt-derived series-fed feedback. The amplifier and
feedback circuit are connected series-parallel. Here, a fraction of the output voltage is applied in
series with the input voltage via the feedback. As seen, the input to the feedback network is in
parallel with the output of the amplifier. Therefore, so far as Vo is concerned, output resistance
of the amplifier is reduced by the shunting effect of the input to the feedback network. It can be
proved that
Similarly, Vi sees two circuit elements in series: (i) the input resistance of the amplifier and (ii)
output resistance of the feedback network. Hence, input resistance of the amplifier as a whole is
increased due to feedback. It can be proved that
Ri´ =Ri (1 + β A)
In fact, series feedback always increases the input impedance by a factor of (1 + βA). (b)
Voltage-shunt Feedback It is shown in Fig. 1.6 (b). It is also known as shunt-derived shunt-fed
feedback i.e. it is parallel-parallel (PP) prototype. Here, a small portion of the output voltage is
coupled back to the input voltage parallel (shunt).
Since the feedback network shunts both the output and input of the amplifier, it decreases both
its output and input impedances by a factor of 1/(1 + βA)
A shunt feedback always decreases input impedance.
(c) Current-series Feedback
It is shown in Fig. 1.6 (c). It is also known as series-derived series-fed feedback. As seen, it is a
series-series (SS) circuit. Here, a part of the output current is made to feedback a proportional
voltage in series with the input. Since it is a series pick-up and a series feedback, both the input
and output impedances of the amplifier are increased due to feedback.
(d) Current-shunt Feedback
It is shown in Fig. 1.6 (d). It is also referred to as series-derived shunt-fed feedback. It is a
parallel-series (PS) prototype. Here, the feedback network picks up a part of the output current
and develops a feedback voltage in parallel (shunt) with the input voltage. As seen, feedback
network shunts the input but is in series with the output. Hence, output resistance of the amplifier
is increased whereas its input resistance is decreased by a factor of loop gain.
Fig. 1.6
The effects of negative feedback on amplifier characteristics are summarized below:
Characteristics Type of Feedback

Voltage series Voltage shunt Current series Current shunt
Voltage gain decreases decreases decreases decreases
Bandwidth increases increases increases increases
Harmonic Distortion decreases decreases decreases decreases
Noise decreases decreases decreases decreases
Input Resistance increases decreases increases decreases
Output Resistance decreases decreases increases increases
Shunt-derived Series-fed Voltage Feedback

The basic principle of such a voltage-controlled feedback is illustrated by the block diagram of
Fig.1.7. Here, the feedback voltage is derived from the voltage divider circuit formed of R1 and
R2. As seen, the voltage drop across R1 forms the feedback voltage Vf.
Fig.1.7
Example 1.7
In the voltage-controlled negative feedback amplifier of Fig. 1.8, calculate (a) voltage gain
without feedback (b) feedback factor (c) voltage gain with feedback. Neglect VBE and use re = 25
mV/IE.
Fig. 1.8
Solution
(a)
Now,
(b)
(c)
Current-series Feedback Amplifier
Fig. 1.9 shows a series-derived series-fed feedback amplifier circuit. Since the emitter resistor is
unbypassed, it effectively provides current-series feedback. When IE passes through RE, the
feedback voltage drop Vf = IE RE is developed which is applied in phase opposition to the input
voltage Vi. This negative feedback reduces the output voltage V0. This feedback can, however,
be eliminated by either removing or bypassing the emitter resistor.
It can be proved that
Fig.1.9
Example 1.8
For the current-series feedback amplifier of Fig.1.9, calculate (i) voltage gain without feedback,
(ii) feedback factor, (iii) voltage gain with feedback. Neglect VBE and use re = 25 mV/IE.
Solution
(i)
Now,
(ii)
(iii)
Voltage-shunt Negative Feedback Amplifier

The circuit of such an amplifier is shown in Fig. 1.10. As seen, a portion of the output voltage is
coupled through RE in parallel with the input signal at the base. This feedback stabilizes the
overall gain while decreasing both the input and output resistances. It can be proved that β =
RC/RF.
Fig.1.10
Current-shunt Negative Feedback Amplifier

The two-stage amplifier employing such a feedback is shown in Fig. 1.11. The feedback circuit
(consisting of CF and RF) samples the output current and develops a feedback voltage in parallel
with the input voltage. The unbypassed emitter resistor of Q2 provides current sensing. The
polarity of the feedback voltage is such that it provides the negative feedback.
Fig.1.11
Chapter Two
Differential Amplifiers
Operational Amplifiers
The operational amplifier is a direct-coupled high gain amplifier usable from 0 to over 1MHz to
which feedback is added to control its overall response characteristic i.e. gain and bandwidth.
The op-amp exhibits the gain down to zero frequency.
Such direct coupled (dc) amplifiers do not use blocking (coupling and by pass) capacitors since
these would reduce the amplification to zero at zero frequency. Large by pass capacitors may be
used but it is not possible to fabricate large capacitors on an IC chip. The capacitors fabricated
are usually less than 20 pf. Transistor, diodes and resistors are also fabricated on the same chip.
Differential Amplifiers
Differential amplifier is a basic building block of an op-amp. The function of a differential
amplifier is to amplify the difference between two input signals.
How the differential amplifier is developed? Let us consider two emitter-biased circuits as shown
in fig.2.1.
Fig.2.1
The two transistors Q1 and Q2 have identical characteristics. The resistances of the circuits are
equal, i.e. RE1 = RE2, RC1 = RC2 and the magnitude of +VCC is equal to the magnitude of? VEE.
These voltages are measured with respect to ground.
To make a differential amplifier, the two circuits are connected as shown in fig.2.1. The two
+VCC and? VEE supply terminals are made common because they are same. The two emitters are
also connected and the parallel combination of RE1 and RE2 is replaced by a resistance RE. The
two input signals v1 & v2 are applied at the base of Q1 and at the base of Q2. The output voltage
is taken between two collectors. The collector resistances are equal and therefore denoted by RC
= RC1 = RC2.
Ideally, the output voltage is zero when the two inputs are equal. When v 1 is greater than v2 the
output voltage with the polarity shown appears. When v1 is less than v2, the output voltage has
the opposite polarity. The differential amplifiers are of different configurations.
The four differential amplifier configurations are following:

1. Dual input, balanced output differential amplifier
2. Dual input, unbalanced output differential amplifier
3. Single input balanced output differential amplifier
4. Single input unbalanced output differential amplifier
Fig.2.2
These configurations are shown in fig. 2.2, and are defined by number of input signals used and
the way an output voltage is measured. If use two input signals, the configuration is said to be
dual input, otherwise it is a single input configuration. On the other hand, if the output voltage is
measured between two collectors, it is referred to as a balanced output because both the
collectors are at the same dc potential w.r.t. ground. If the output is measured at one of the
collectors w.r.t. ground, the configuration is called an unbalanced output.
A multistage amplifier with a desired gain can be obtained using direct connection between
successive stages of differential amplifiers. The advantage of direct coupling is that it removes
the lower cut off frequency imposed by the coupling capacitors, and they are therefore, capable
of amplifying dc as well as ac input signals.
Dual Input, Balanced Output Differential Amplifier

The circuit is shown in fig. 2.1, v1 and v2 are the two inputs, applied to the bases of Q1 and Q2
transistors. The output voltage is measured between the two collectors C 1 and C2, which are at
same dc potentials.
D.C. Analysis
To obtain the operating point (ICQ and VCEQ) for differential amplifier dc equivalent circuit is
drawn by reducing the input voltages v1 and v2 to zero as shown in fig.2.3.
Fig.2.3
The internal resistances of the input signals are denoted by RS because RS1= RS2. Since both
emitters biased sections of the different amplifier are symmetrical in all respects, therefore, the
operating point for only one section need to be determined. The same values of ICQ and VCEQ can
be used for second transistor Q2.
Applying KVL to the base emitter loop of the transistor Q1
Generally, because is the internal resistance of input signal.
The value of RE is set up the emitter current in transistor Q1 and Q2 for a given value of VEE. The
emitter current in Q1 and Q2 are independent of collector resistance RC.
The voltage at the emitter of Q1 is approximately equal to -VBE if the voltage drop across R is
negligible. Knowing the value of IC the voltage at the collector VC is given by
VC =VCC - IC RC
and VCE = VC - VE
= VCC - IC RC + VBE
VCE = VCC + VBE - ICRC
From the two equations VCEQ and ICQ can be determined. This dc analysis is applicable for all
types of differential amplifier.
Example 2.1
The following specifications are given for the dual input, balanced output differential amplifier
of fig.2.1: RC = 2.2 kΩ, RE = 4.7 kΩ, Rin 1 = Rin 2 = 50 Ω, +VCC = 10V, -VEE = -10 V, βdc =100
and VBE = 0.715V. Determine the operating points (ICQ and VCEQ) of the two transistors.
Solution:
The value of ICQ can be obtained from equation (Eqn 1)
The voltage VCEQ can be obtained from equation (Eqn 2).
The values of ICQ and VCEQ are same for both the transistors.
Dual Input, Balanced Output Difference Amplifier

The circuit is shown in fig.2.4 v1 and v2 are the two inputs, applied to the bases of Q1 and Q2
transistors. The output voltage is measured between the two collectors C1 and C2, which are at
same dc potentials.
Fig.2.4
A.C. Analysis
In previous lecture dc analysis has been done to obtain the operating point of the two transistors.
To find the voltage gain Ad and the input resistance Ri of the differential amplifier, the ac
equivalent circuit is drawn using r-parameters as shown in fig.2.5. The dc voltages are reduced to
zero and the ac equivalent of CE configuration is used.
Fig.2.5
Since the two dc emitter currents are equal. Therefore, resistance r'e1 and r'e2 are also equal and
designated by r'e. This voltage across each collector resistance is shown 180° out of phase with
respect to the input voltages v1 and v2. This is same as in CE configuration. The polarity of the
output voltage is shown in Figure. The collector C2 is assumed to be more positive with respect
to collector C1 even though both are negative with respect to ground.
Applying KVL in two loops 1 & 2
Substituting current relations,
Again, assuming RS1/β and RS2/β are very small in comparison with RE and re' and therefore
neglecting these terms,
Solving these two equations, ie1 and ie2 can be calculated.
The output voltage VO is given by

VO = VC2 - VC1
= -RC iC2 - (-RC iC1)
= RC (iC1 - iC2)
= RC (ie1 - ie2)
Substituting ie1, & ie2 in the above expression
Therefore,
Thus a differential amplifier amplifies the difference between two input signals. Defining the
difference of input signals as vd = v1 - v2 the voltage gain of the dual input balanced output
differential amplifier can be given by
Differential Input Resistance:

Differential input resistance is defined as the equivalent resistance that would be measured at
either input terminal with the other terminal grounded. This means that the input resistance R i1
seen from the input signal source v1 is determined with the signal source v2 set at zero. Similarly,
the input signal v1 is set at zero to determine the input resistance Ri2 seen from the input signal
source v2. Resistance RS1 and RS2 are ignored because they are very small.
Substituting ie1,
Since
Similarly,
The factor of 2 arises because re' of each transistor is in series.
To get very high input impedance with differential amplifier is to use Darlington transistors or
FET.
Output Resistance
Output resistance is defined as the equivalent resistance that would be measured at output
terminal with respect to ground. Therefore, the output resistance RO1 measured between collector
C1 and ground is equal to that of the collector resistance RC. Similarly the output resistance RO2
measured at C2 with respect to ground is equal to that of the collector resistor RC.
RO1 = RO2 = RC
The current gain of the differential amplifier is undefined. Like CE amplifier the differential
amplifier is a small signal amplifier. It is generally used as a voltage amplifier and not as current
or power amplifier.
Example 2.2
The following specifications are given for the dual input, balanced-output differential amplifier:
RC = 2.2 kΩ, RB = 4.7 kΩ, Rin1 = Rin2 = 50 Ω, +VCC= 10V, -VEE = -10 V, βdc =100 and VBE =
0.715V.
a. Determine the voltage gain
b. Determine the input resistance
c. Determine the output resistance
Solution:
(a). the parameters of the amplifiers are same as discussed in example 2.1. The operating point of
the two transistors obtained in the lecture are given below ICQ = 0.988 mA VCEQ=8.54V
The ac emitter resistance
Therefore, substituting the known values in voltage gain equation, we obtain
(b). The input resistance seen from each input source is given by:
(c) The output resistance seen looking back into the circuit from each of the two output terminals
is given by
Inverting & Non - inverting Inputs

In a differential amplifier, the output voltage VO is given by
VO = Ad (V1 - V2), When V2 = 0, VO = Ad V1 & when v1 = 0, VO = - Ad V2
Therefore the input voltage V1 is called the non inventing input because positive voltage V1
acting alone produces a positive output voltage VO. Similarly, the positive voltage V2 acting
alone produces a negative output voltage hence V2 is called inverting input. Consequently B1 is
called non - inverting input terminal and B2 is called inverting input terminal.
Common mode Gain and common Mode rejection ratio

A common mode signal is the one that drives both inputs of a differential amplifier equally. The
common mode signal is interference, static and other kinds of undesirable pickup etc.
The connecting wire on the input bases act like small antennas. If a differential amplifier is
operating in an environment with lot of electromagnetic interference, each base picks up an
unwanted interference voltage. If both the transistors were matched in all respects then the
balanced output would be theoretically zero. This is the important characteristic of a differential
amplifier. It discriminates against common mode input signals. In other word, it refuses to
amplify the common mode signals.
The practical effectiveness of rejecting the common signal depends on the degree of matching
between the two CE stages forming the differential amplifier. In other words, more closely are
the currents in the input transistors, the better is the common mode signal rejection e.g. If V1 and
V2 are the two input signals, then the output of a practical op-amp cannot be described by simply
V0 = Ad (V1 - V2)
In practical differential amplifier, the output depends not only on difference signal but also upon
the common mode signal VC (average).
Vd = (V1 – V2) and VC = ½ (V1 + V2)
The output voltage, therefore can be expressed as
VO = A1 V1 + A2 V2
Where A1 & A2 are the voltage amplification from input 1(2) to output under the condition that
input 2 (1) is grounded.
Substituting in output voltage equation
The voltage gain for the difference signal is Ad and for the common mode signal is AC.
The ability of a differential amplifier to reject a common mode signal is expressed by its
common mode rejection ratio (CMRR). It is the ratio of differential gain Ad to the common mode
gain AC.
Date sheet always specify CMRR in decibels CMRR = 20 log CMRR.
Therefore, the differential amplifier should be designed so that is large compared with the ratio
of the common mode signal to the difference signal. If = 1000, VC = 1mV, Vd = 1 µV, then
It is equal to first term. Hence for an amplifier with = 1000, a 1 µV difference of potential
between two inputs gives the same output as 1mV signal applied with the same polarity to both
inputs.
Dual Input, Unbalanced Output Differential Amplifier:

In this case, two input signals are given however the output is measured at only one of the two
collector w.r.t. ground as shown in fig. 2.6. The output is referred to as an unbalanced output
because the collector at which the output voltage is measured is at some finite dc potential with
respect to ground.
Fig.2.6
In other words, there is some dc voltage at the output terminal without any input signal applied.
DC analysis is exactly the same as that of the first case.
AC Analysis
The output voltage gain in this case is given by
The voltage gain is half the gain of the dual input, balanced output differential amplifier. Since at
the output there is a dc error voltage, therefore, to reduce the voltage to zero, this configuration is
normally followed by a level translator circuit.
Differential amplifier with swamping resistors

By using external resistors R'E in series with each emitter, the dependence of voltage gain on
variations of r'e can be reduced. It also increases the linearity range of the differential amplifier.
Fig.2.7. shows the differential amplifier with swamping resistor R'E. The value of R'E is usually
large enough to swamp the effect of r'e.
Fig.2.7
From the equation, can be obtained as
The new voltage gain is given by
The input resistance is given by
The output resistance with or without is the same i.e.
Example 2.3
The specifications are given again for the dual input, unbalanced-output differential amplifier:
RC = 2.2 kΩ, RB= 4.7 kΩ, Rin1 = Rin2= 50Ω, +VCC = 10V, -VEE= -10 V, βdc =100 and VBE=
0.715V.
Determine the voltage gain, input resistance and the output resistance.
Solution:
Since the component values remain unchanged and the biasing arrangement is same, the ICQ and
VCEQ values as well as input and output resistance values for the dual input, unbalanced output
configuration must be the same as those for the dual input, balanced output configuration.
Thus, ICQ = 0.988 mA

VCEQ = 8.54 V
Ri1 = Ri2 = 5.06 kΩ
Ro = 2.2 kΩ
The voltage gain of the dual input, unbalanced output differential amplifier is given by
Constant Current Bias

In the dc analysis of differential amplifier, we have seen that the emitter current IE depends upon
the value of βdc. To make operating point stable IE current should be constant irrespective value
of βdc.
For constant IE, RE should be very large. This also increases the value of CMRR but if RE value
is increased to very large value, IE (quiescent operating current) decreases. To maintain same
value of IE, the emitter supply VEE must be increased. To get very high value of resistance RE and
constant IE, current, current bias is used.
Fig.2.8
Fig. 2.8 shows the dual input balanced output differential amplifier using a constant current bias.
The resistance RE is replace by constant current transistor Q3. The dc collector current in Q3 is
established by R1, R2, & RE. Applying the voltage divider rule, the voltage at the base of Q3 is
Because the two halves of the differential amplifiers are symmetrical, each has half of the current
IC3.
The collector current, IC3 in transistor Q3 is fixed because no signal is injected into either the
emitter or the base of Q3.
Besides supplying constant emitter current, the constant current bias also provides a very high
source resistance since the ac equivalent or the dc source is ideally an open circuit. Therefore, all
the performance equations obtained for differential amplifier using emitter bias are also valid.
As seen in IE expressions, the current depends upon VBE3. If there is a change in temperature,
VBE, and current IE also changes. To improve thermal stability, a diode is placed in series with
resistance R1as shown in fig. 2.9.
Fig.2.9
This helps to hold the current IE3 constant even though the temperature changes. By applying
KVL to the base circuit of Q3.
is the diode voltage. Thus,
If are so chosen that
Then
Therefore, the current IE3 is constant and independent of temperature because of the added diode
D. Without D the current would vary with temperature because VBE3 decreases approximately by
2mV/° C. The diode has same temperature dependence and hence the two variations cancel each
other and IE3 does not vary appreciably with temperature. Since the cut in voltage VD of diode
approximately the same value as the base to emitter voltage VBE3 of a transistor, the above
condition cannot be satisfied with one diode. Hence two diodes are used in series for VD. In this
case the common mode gain reduces to zero.
Some times Zener diode may be used in place of diodes and resistance as shown in fig. 2.10.
Zener is available over a wide range of voltages and can have matching temperature coefficient
The voltage at the base of transistor QB is
Fig.2.10
The value of R2 is selected so that I2 = 1.2 IZ (min) where IZ is the minimum current required
causing the Zener diode to conduct in the reverse region, which is to block the rated voltage VZ.
Where I2 = 1.2 IZ (min)
Current Mirror
The circuit in which the output current is forced to equal the input current is said to be a current
mirror circuit. Thus in a current mirror circuit, the output current is a mirror image of the input
current. The current mirror circuit is shown in fig. 2.11.
Fig.2.11
Once the current I2 is set up, the current IC3 is automatically established to be nearly equal to I2.
The current mirror is a special case of constant current bias and the current mirror bias requires
of constant current bias and therefore can be used to set up currents in differential amplifier
stages. The current mirror bias requires fewer components than constant current bias circuits.
Since Q3 and Q4 are identical transistors the current and voltage are approximately same
Summing currents at node
Generally is large enough, therefore is small.
For satisfactory operation two identical transistors are necessary.
Chapter Three
Operational Amplifier
In this chapter you will learn
1. The terminal characteristics of the ideal op amp.
2. How to analyze circuits containing op amps, resistors, and capacitors.
3. How to use op amps to design amplifiers having precise characteristics.
4. How to design more sophisticated op-amp circuits, including summing amplifiers,
instrumentation amplifiers, integrators, and differentiators.
5. Important non-ideal characteristics of op amps and how these limit the performance of
basic op-amp circuits.
6. Application of an operational amplifier
Introduction
An operational amplifier, or op-amp, is a very high gain differential amplifier with high input
impedance and low output impedance. Typical uses of the operational amplifier are to provide
voltage amplitude changes (amplitude and polarity), oscillators, filter circuits, and many types of
instrumentation circuits. An op-amp contains a number of differential amplifier stages to achieve
a very high voltage gain.
Figure 3.1 shows a basic op-amp with two inputs and one output as would result using a
differential amplifier input stage. Each input results in either the same or an opposite polarity (or
phase) output, depending on whether the signal is applied to the plus (+) or the minus (-) input.
Figure 3.1 Basic op-amp

Single-Ended Input
Single-ended input operation results when the input signal is connected to one input with the
other input connected to ground. Figure 3.2 shows the signals connected for this operation. In
Fig. 3.2a, the input is applied to the plus input (with minus input at ground), which results in an
output having the same polarity as the applied input signal. Figure 3.2b shows an input signal
applied to the minus input, the output then being opposite in phase to the applied signal.
Figure 3.2 Single ended operations
Double-Ended (Differential) Input

In addition to using only one input, it is possible to apply signals at each input. This is being a
double-ended operation. Figure 3.3a shows an input, Vd, applied between the two input terminals
(recall that neither input is at ground), with the resulting amplified output in phase with that
applied between the plus and minus inputs. Figure 3.3b shows the same action resulting when
two separate signals are applied to the inputs, the difference signal being Vi1 - Vi2.
Figure 3.3 Double-ended (differential) operation
Double-Ended Output
While the operation discussed so far had a single output, the op-amp can also be operated with
opposite outputs, as shown in Fig. 3.4. An input applied to either input will result in outputs from
both output terminals, these outputs always being opposite in polarity. Figure 3.5 shows a single-
ended input with a double-ended output. As shown, the signal applied to the plus input results in
two amplified outputs of opposite polarity. Figure 3.6 shows the same operation with a single
output measured between output terminals (not with respect to ground). This difference output
signal is Vo1 - Vo2. The difference output is also referred to as a floating signal since neither
output terminal is the ground (reference) terminal. Notice that the difference output is twice as
large as either Vo1 or Vo2 since they are of opposite polarity and subtracting them results in
twice their amplitude [i.e., 10 V - (-10 V) = 20 V]. Figure 3.7 shows a differential input,
differential output operation. The input is applied between the two input terminals and the output
taken from between the two output terminals. This is fully differential operation.
Figure 3.4 Double-ended output
Figure 3.5 Double-ended output with single-ended input Figure 3.6 Double-ended output
Figure 3.7 Differential-input, differential-output operation
Common-Mode Operation
When the same input signals are applied to both inputs, common-mode operation results, as
shown in Fig. 3.8. Ideally, the two inputs are equally amplified, and since they result in opposite
polarity signals at the output, these signals cancel, resulting in 0 V output. Practically, a small
output signal will result.
Figure 3.8 Common-mode operation
Differential and Common Mode Operation

One of the more important features of a differential circuit connection, as provided in an op-amp,
is the circuit’s ability to greatly amplify signals that are opposite at the two inputs, while only
slightly amplifying signals that are common to both inputs. An op-amp provides an output
component that is due to the amplification of the difference of the signals applied to the plus and
minus inputs and a component due to the signals common to both inputs. Since amplification of
the opposite input signals is much greater than that of the common input signals, the circuit
provides a common mode rejection as described by a numerical value called the common-mode
rejection ratio (CMRR) discussed in chapter 2.
Differential Inputs
When separate inputs are applied to the op-amp, the resulting difference signal is the difference
between the two inputs.
Vd = Vi1 - Vi2
Common Inputs
When both input signals are the same, a common signal element due to the two inputs can be
defined as the average of the sum of the two signals.
Vc = ½ (Vi1+Vi2)
Output Voltage
Since any signals applied to an op-amp in general have both in-phase and out-of phase
components, the resulting output can be expressed as
Vo = AdVd + AcVc
Where Vd _ difference voltage
Vc _ common voltage
Ad _ differential gain of the amplifier
Ac _ common-mode gain of the amplifier
Opposite Polarity Inputs

If opposite polarity inputs applied to an op-amp are ideally opposite signals, Vi1 = - Vi2 = Vs, the
resulting difference voltage is
Vd = Vi1 - Vi2 = Vs - (-Vs) = 2Vs
While the resulting common voltage is
Vc=½ (Vi1 + Vi2) = ½ [Vs + (-Vs)] = 0
So that the resulting output voltage is
Vo = AdVd + AcVc = Ad (2Vs) + 0 = 2 AdVs
This shows that when the inputs are an ideal opposite signal (no common element), the output is
the differential gain times twice the input signal applied to one of the inputs.
Same Polarity Inputs

If the same polarity inputs are applied to an op-amp, Vi1 = Vi2 = Vs, the resulting difference
voltage is
Vd = Vi1 - Vi2 = Vs - Vs = 0
While the resulting common voltage is
Vc=½ (Vi1 + Vi2) = ½ (Vs +Vs) = Vs
So that the resulting output voltage is
Vo = AdVd + AcVc = Ad (0) + AcVS = AcVS
This shows that when the inputs are ideal in-phase signals (no difference signal), the output is the
common-mode gain times the input signal, Vs, which shows that only common-mode operation
occurs.
Ideal Operational Amplifiers
The circuit symbol for the operational amplifier is shown in Figure 3.1. The operational amplifier
is a differential amplifier having both inverting and non inverting input terminals. (We discussed
differential amplifiers in chapter 2) The input signals are denoted as vi1 (t) and vi2 (t) (As usual,
we use lowercase letters to represent general time-varying voltages. Often, we will omit the time
dependence and refer to the voltages simply as vi1 and vi2.
An ideal operational amplifier has the following characteristics:

 Infinite input impedances
 Infinite gain for the differential input signal
 Zero gain for the common-mode input signal
 Zero output impedance
 Infinite bandwidth
An equivalent circuit for the ideal operational amplifier consists simply of a controlled source as
shown in Figure 3.9. The open-loop gain AOL is very large in magnitude. Ideally it is infinite.
Op amps are generally used with feedback networks that return part of the output signal to the
input. Thus, a loop is created in which signals flow through the amplifier to the output and back
through the feedback network to the input. AOL is the gain of the op amp without a feedback
network. That is why we call it the open-loop gain.
We assume that the open-loop gain AOL is constant. Thus, there is no distortion, either linear or
nonlinear, and the output voltage VO has a wave shape identical to that of the differential input
vid = V1 - V2. AOL is actually a function of frequency.
Figure 3.9 Equivalent circuit of the ideal op amp

Power-Supply Connections
For a real op amp to function properly, one or more dc supply voltages must be applied, as
shown in Figure 3.10. Often, however, we do not explicitly show the power supply connections
in circuit diagrams.
Figure 3.10 Op-amp symbol showing the dc power supplies, Vcc and Vee
Op-Amp Basics
An operational amplifier is a very high gain amplifier having very high input impedance
(typically a few mega ohms) and low output impedance (less than 100Ω). The basic circuit is
made using a difference amplifier having two inputs (plus and minus) and at least one output.
Figure 3.11 shows a basic op-amp unit.
Figure 3.11 Basic op-amp

As discussed earlier, the plus (+) input produces an output that is in phase with the signal
applied, while an input to the minus (-) input results in an opposite polarity output. The ac
equivalent circuit of the op-amp is shown in Fig. 3.12a. As shown, the input signal applied
between input terminals sees input impedance, Ri, typically very high. The output voltage is
shown to be the amplifier gain times the input signal taken through an output impedance, Ro,
which is typically very low. An ideal op-amp circuit, as shown in Fig. 3.12b, would have infinite
input impedance, zero output impedance, and an infinite voltage gain.
Figure 3.12 Ac equivalent of op-amp circuit: (a) practical; (b) ideal
Basic Op-Amp
The basic circuit connection using an op-amp is shown in Fig. 3.13. The circuit shown provides
operation as a constant-gain multiplier. An input signal, V1, is applied through resistor R1 to the
minus input. The output is then connected back to the same minus input through resistor Rf. The
plus input is connected to ground. Since the signal V1 is essentially applied to the minus input,
the resulting output is opposite in phase to the input signal. Figure 3.14a shows the op-amp
replaced by its ac equivalent circuit. If we use the ideal op-amp equivalent circuit, replacing Ri
by an infinite resistance and Ro by zero resistance, the ac equivalent circuit is that shown in Fig.
3.14b. The circuit is then redrawn, as shown in Fig. 3.14c, from which circuit analysis is carried
out.
Figure 3.13 Basic op-amp connection
Figure 3.14 Operation of op-amp as constant-gain multiplier: (a) op-amp ac equivalent circuit;
(b) ideal op-amp equivalent circuit; (c) redrawn equivalent circuit.
From the redrawn equivalent circuit, and using superposition, we can solve for the voltage V1 in
terms of the components due to each of the sources. For source V1 only (- AvVi set to zero),
For source - AvVi only (V1 set to zero),
The total voltage Vi is then
Which can be solved for Vi as
If Av 1 and Av R1 Rf, as is usually true, then
Solving for Vo/Vi, we get
So that
The result, in the above equation, shows that the ratio of overall output to input voltage is
dependent only on the values of resistors R1 and Rf provided that Av is very large.
Unity Gain
If Rf = R1, the gain is
So that, the circuit provides unity voltage gain with 180° phase inversion. If Rf is exactly R1, the
voltage gain is exactly 1.
Constant Magnitude Gain

If Rf is some multiple of R1, the overall amplifier gain is a constant. For example, if Rf = 10R1,
then
and the circuit provides a voltage gain of exactly 10 along with an 180° phase inversion from the
input signal. If we select precise resistor values for Rf and R1, we can obtain a wide range of
gains, the gain being as accurate as the resistors used and is only slightly affected by temperature
and other circuit factors.
Virtual Ground and Summing Point

In Fig. 3.15a is shown an Op amp which employs negative feedback with the help of resistor Rf
which feeds a portion of the output to the input. Since input and feedback currents are
algebraically added at point A, it is called the summing point. The concept of virtual ground
arises from the fact that input voltage Vi at the inverting terminal of the Op amp is forced to such
a small value that, for all practical purposes, it may be assumed to be zero. Hence, point A is
essentially at ground voltage and is referred to as virtual ground. Obviously, it is not the actual
ground, which, as seen from Fig. 3.15a, is situated below.
Fig.3.15a
The output voltage is limited by the supply voltage of, typically, a few volts. As stated before,
voltage gains are very high. If, for example, Vo = - 10 V and Av = 20,000, the input voltage
would then be
A virtual short so that no current goes through the short to ground. Current goes only through
resistors R1 and Rf as shown.
Figure 3.15b Virtual ground in an op-amp

Using the virtual ground concept, we can write equations for the current I as follows:
Which can be solved for Vo /V1:
The virtual ground concept, which depends on Av being very large, allowed a simple solution to
determine the overall voltage gain.
Op-Amp Parameters
Before going into various practical applications using op-amps, we should become familiar with
some of the parameters used to define the operation of the unit. These specifications include both
dc and transient or frequency operating features.
Offset Currents and Voltages

While the op-amp output should be 0 V when the input is 0 V, in actual operation there is some
offset voltage at the output. For example, if one connected 0 V to both op-amp inputs and then
measured 26 mV (dc) at the output, this would represent 26 mV of unwanted voltage generated
by the circuit and not by the input signal. Since the user may connect the amplifier circuit for
various gain and polarity operations, however, the manufacturer specifies an input offset voltage
for the op-amp. The output offset voltage is then determined by the input offset voltage and the
gain of the amplifier, as connected by the user. The output offset voltage can be shown to be
affected by two separate circuit conditions. These are: (1) an input offset voltage, VIO, and (2) an
offset current due to the difference in currents resulting at the plus (+) and minus (-) inputs.
Input Offset Voltage, VIO

The manufacturer’s specification sheet provides a value of VIO for the op-amp. To determine the
effect of this input voltage on the output, consider the connection shown in Fig. 3.16. Using Vo =
AVi, we can write
Solving for Vo, we get
From which we can write
The above equation shows how the output offset voltage results from a specified input offset
voltage for a typical amplifier connection of the op-amp.
Figure 3.16 Operation showing effect of input offset voltage, VIO

Example 3.1
Calculate the output offset voltage of the circuit in Fig. 3.17. The op-amp spec lists VIO = 1.2
mV.
Fig 3.17
Solution
Output Offset Voltage Due To Input Offset Current, IIO
An output offset voltage will also result due to any difference in dc bias currents at both inputs.
Since the two input transistors are never exactly matched, each will operate at a slightly different
current. For a typical op-amp connection, shown in Fig. 3.18, an output offset voltage can be
determined as follows. Replacing the bias currents through the input resistors by the voltage drop
as shown in Fig. 3.19, we can determine the expression for the resulting output voltage. Using
superposition, the output voltage due to input bias current I +IB, denoted by V +o, is
While the output voltage due to only , denoted by , is
Figure 3.18 Op-amp connection showing input bias currents Figure 3.19 Redrawn circuit of Fig. 3.18
For a total output offset voltage of
Since the main consideration is the difference between the input bias currents rather than each
value, we define the offset current IIO by
Since the compensating resistance RC is usually approximately equal to the value of R1, using
RC = R1 in the total offset voltage equation, we can write
Resulting in
Example 3.2
Calculate the offset voltage for the circuit of Fig. 3.17 for op-amp specification listing IIO = 100
nA.
Solution
Total Offset due to VIO and IIO

Since the op-amp output may have an output offset voltage due to both factors covered above,
the total output offset voltage can be expressed as
[Vo(offset)] = [Vo(offset due to VIO)] + [Vo(offset due to IIO)]
The absolute magnitude is used to accommodate the fact that the offset polarity may be either
positive or negative.
Example 3.3
Calculate the total offset voltage for the circuit of Fig. 3.20 for an op-amp with specified values
of input offset voltage, VIO = 4 mV and input offset current IIO =150 nA.
Figure 3.20 op amp circuit for example 3.3

Solution
The offset due to VIO is
Resulting in a total offset
Input Bias Current, IIB

A parameter related to IIO and the separate input bias currents and is the average bias
current defined as
One could determine the separate input bias currents using the specified values IIO and IIB. It can
be shown that for >
Example 3.4
Calculate the input bias currents at each input of an op-amp having specified values of IIO = 5
nA and IIB = 30 nA.
Solution
Op-Amp Frequency Parameters

An op-amp is designed to be a high-gain, wide-bandwidth amplifier. This operation tends to be
unstable (oscillate) due to positive feedback. To ensure stable operation, op-amps are built with
internal compensation circuitry, which also causes the very high open-loop gain to diminish with
increasing frequency. This gain reduction is referred to as roll-off. In most op-amps, roll-off
occurs at a rate of 20 dB per decade.
Gain Bandwidth
Because of the internal compensation circuitry included in an op-amp, the voltage gain drops off
as frequency increases. Op-amp specifications provide a description of the gain versus
bandwidth. Figure 3.21 provides a plot of gain versus frequency for a typical op-amp. At low
frequency down to dc operation the gain is that value listed by the manufacturer’s specification
AVD (voltage differential gain) and is typically a very large value. As the frequency of the input
signal increases the open-loop gain drops off until it finally reaches the value of 1 (unity). The
frequency at this gain value is specified by the manufacturer as the unity-gain bandwidth, B1.
While this value is a frequency (see Fig. 3.21) at which the gain becomes 1, it can be considered
a bandwidth, and since the frequency band from 0 Hz to the unity-gain frequency is also a
bandwidth. One could therefore refer to the point at which the gain reduces to 1 as the unity-gain
frequency (f1) or unity-gain bandwidth (B1).
Figure 3.21 Gain versus frequency plot
Another frequency of interest is that shown in Fig. 3.21, at which the gain drops by 3 dB (or to
0.707 the dc gain, AVD), is the cutoff frequency of the op-amp, fC. In fact, the unity-gain
frequency and cutoff frequency are related by
f1 = AVD fC
Example 3.5
Determine the cutoff frequency of an op-amp having specified values B1 = 1 MHz and AVD =
200 V/mV.
Solution
Since f1 = B1 = 1 MHz, to calculate the cutoff frequency
Slew Rate, SR
Another parameter reflecting the op-amp’s ability to handling varying signals is slew rate,
defined as
Slew rate = maximum rate at which amplifier output can change in volts per microsecond (V/µs)
with t in µsec
Example 3.6
For an op-amp having a slew rate of SR = 2 V/µs, what is the maximum closed-loop voltage gain
that can be used when the input signal varies by 0.5 V in 10 µs?
Solution
Since Vo = ACLVi, we can use
From which we get
Any closed-loop voltage gain of magnitude greater than 40 would drive the output at a rate
greater than the slew rate allows, so the maximum closed-loop gain is 40.
Maximum Signal Frequency

The maximum frequency that an op-amp may operate at depends on both the bandwidth (BW)
and slew rate (SR) parameters of the op-amp. For a sinusoidal signal of general form
Vo = K sin (2 f t)
The maximum voltage rate of change can be shown to be
Maximum signal rate of change = 2 fK V/s

To prevent distortion at the output, the rate of change must also be less than the slew rate, that is,
2 fK SR
K SR
So that
Example 3.7
For the signal and circuit of Fig. 3.22, determine the maximum frequency that may be used. Op-
amp slew rate is SR = 0.5 V/µs, V1 = 0.02 V and ω = 300x103 rad/sec.
Fig 3.22
Solution
For a gain of magnitude
The output voltage provides
Since the signal’s frequency, ω = 300 x103 rad/s, is less than the maximum value determined
above, no output distortion will result.
Inverting and non-inverting Amplifier

Inverting Amplifier
The most widely used constant-gain amplifier circuit is the inverting amplifier, as shown in Fig.
3.23. The output is obtained by multiplying the input by a fixed or constant gain, set by the input
resistor (R1) and feedback resistor (Rf). This output also being inverted from the input. We can
write
Figure 3.23 Inverting constant-gain multiplier
Example 3.1
If the circuit of Fig. 3.23 has R1 = 100 kΩ and Rf = 500 kΩ, what output voltage results for an
input of V1 = 2 V?
Solution
Non-inverting Amplifier
The connection of Fig. 3.24a shows an op-amp circuit that works as a non-inverting amplifier or
constant-gain multiplier. It should be noted that the inverting amplifier connection is more
widely used because it has better frequency stability. To determine the voltage gain of the circuit,
we can use the equivalent representation shown in Fig. 3.24b. Note that the voltage across R1 is
V1 since Vi 0 V. This must be equal to the output voltage, through a voltage divider of R1 and
Rf, so that
This result in
Figure 3.24 Non-inverting constant gain multiplier

Example 3.2
Calculate the output voltage of a non-inverting amplifier (as in Fig. 3.23) for values of V1 = 2 V,
Rf = 500 kΩ, and R1 = 100 kΩ.
Solution
Unity Follower
The unity-follower circuit, as shown in Fig. 3.25a, provides a gain of unity (1) with no polarity
or phase reversal. From the equivalent circuit (see Fig. 3.25b) it is clear that
Vo = V1
and that the output is the same polarity and magnitude as the input. The circuit operates like an
emitter or source follower circuit except that the gain is exactly unity.
Figure 3.25 (a) Unity follower; (b) virtual-ground equivalent circuit
OP - Amp applications
Constant Gain Multiplier
One of the most common op-amp circuits is the inverting constant-gain multiplier, which
provides a precise gain or amplification. Figure 3.26 shows a standard circuit connection with the
resulting gain being given by
Figure 3.26 Fixed-gain amplifier
Example 3.3
Determine the output voltage for the circuit of Fig. 3.27 with a sinusoidal input of 2.5 mV.
Figure 3.27 Circuit for Example 3.3
Solution
The circuit of Fig. 3.27 uses a 741 op-amp to provide a constant or fixed gain, so the gain is
The output voltage is then
A non - inverting constant-gain multiplier is provided by the circuit of Fig. 3.28, with the gain
given by
Figure 3.28 Non - inverting fixed-gain amplifier

Example 3.4
Calculate the output voltage from the circuit of Fig. 3.29 for an input of 120 µV.

Solution
The gain of the op-amp circuit is calculated to be
The output voltage is then
Multiple-Stage Gains
When a number of stages are connected in series, the overall gain is the product of the individual
stage gains. Figure 3.30 shows a connection of three stages. The first stage is connected to
provide non - inverting gain. The next two stages provide an inverting gain. The overall circuit
gain is then non - inverting and calculated by
Where
Figure 3.30 Constant-gain connection with multiple stages
Example 3.5
Calculate the output voltage using the circuit of Fig. 3.30 for resistor components of value Rf =
470 kΩ, R1 = 4.3 kΩ, R2 = 33 kΩ, and R3 = 33 kΩ for an input of 80 µV.
Solution
The amplifier gain is calculated to be
So that
Example 3.6
Show the connection of an LM124 quad op-amp as a three-stage amplifier with gains of +10, -
18, and - 27. Use a 270 kΩ feedback resistor for all three circuits. What output voltage will result
for an input of 150 µV?
Solution
For the gain of +10:
For the gain of - 18:
For the gain of - 27:
The circuit showing the pin connections and all components used is in Fig. 3.31. For an input of
V1 = 150 µV, the output voltage will be
Figure 3.31 Circuit for Example 3.6 (using LM124)
Summing amplifier
Another popular use of an op-amp is as a summing amplifier. Figure 3.32 shows the connection
with the output being the sum of the three inputs, each multiplied by a different gain. The output
voltage is
Figure 3.32 Summing amplifier

Example 3.7
Calculate the output voltage for the circuit of Fig. 3.33. The inputs are V1 = 50 mV sin (1000t)
and V2 = 10 mV sin (3000t)

Solution
The output voltage is
Voltage Subtraction
Two signals can be subtracted, one from the other, in a number of ways. Figure 3.34 shows two
op-amp stages used to provide subtraction of input signals. The resulting output is given by
Figure 3.34 Circuit to subtract two signals
Example 3.8
Determine the output for the circuit of Fig. 3.34 with components Rf = 1 MΩ, R1 = 100 kΩ, R2 =
50 kΩ, and R3 = 500 kΩ.
Solution
The output voltage is calculated to be
The output is seen to be the difference of V2 and V1 multiplied by a gain factor of – 20.
Another connection to provide subtraction of two signals is shown in Fig. 3.35. This connection
uses only one op-amp stage to provide subtracting two input signals. Using superposition the
output can be shown to be
Figure 3.35 Subtraction circuit
Integrator
So far, the input and feedback components have been resistors. If the feedback component used
is a capacitor, as shown in Fig. 3.36a, the resulting connection is called an integrator. The
virtual-ground equivalent circuit (Fig. 3.36b) shows that an expression for the voltage between
input and output can be derived in terms of the current I. The virtual ground is considered at the
junction of R and XC to the ground point (since Vi 0 V) but no current goes into ground at that
point. The capacitive reactance can be expressed as
Figure 3.36 Integrator

Where s = jω is in the Laplace notation.* Solving for Vo/V1 yields
The expression above can be rewritten in the time domain as
The function of an integrator is to provide an output voltage which is proportional to the integral
of the input voltage.
Figure 3.37
A simple example of integration is shown in Fig. 3.37 where input is dc level and its integral is a
linearly-increasing ramp output. The actual integration circuit is shown in Fig. 3.36.
Summing integrator
Fig. 3.38 (a) shows a summing integrator as used in an analog computer. It shows all the three
resistors and the capacitor. The analog computer representation of Fig. 3.38 (b) indicates only the
scale factor for each input. The output voltage is calculated as follows
Figure 3.38
Example 3.9
A 5-mV, 1-kHz sinusoidal signal is applied to the input of an Op-amp integrator of Fig. 3.39 for
which R = 100 K and C = 1 μF. Find the output voltage. V1 = 5 sin 2 πft = 5 sin 2000 π t
Figure 3.39 Integrator circuit for Example 3.9
Solution
Scale factor =
The equation for the sinusoidal voltage is

V1 = 5 sin 2 πft = 5 sin 2000 π t
Obviously, it has been assumed that at t = 0, V1 = 0
Differentiator
Its function is to provide an output voltage which is proportional to the rate of the change of the
input voltage. It is an inverse mathematical operation to that of an integrator. As shown in Fig.
3.40, when we feed a differentiator with linearly-increasing ramp input, we get a constant dc
output.
Figure 3.40
Differentiator circuit can be obtained by interchanging the resistor and capacitor of the integrator
circuit.
Figure 3.41 Op – amp differentiator circuit
Let i = rate of change of charge =
Now,
Therefore,
Taking point A as virtual ground
Output voltage is proportional to the derivate of the input voltage and the constant of
proportionality (i.e., scale factor - RC).
Example 3.10
The input to the differentiator circuit of Fig. 3.41 is a sinusoidal voltage of peak value of 5 mV
and frequency 1 kHz. Find out the output if R = 1000 KΩ and C = 1 μF.
Solution
The equation of the input voltage is
V1 = 5 sin 2 π × 1000 t = 5 sin 2000 πt mV
As seen, output is a co sinusoidal voltage of frequency 1 kHz and peak value 1000 π mV.
Comparator
It is a circuit which compares two signals or voltage levels. The circuit is shown in Fig. 3.42 and
(like that of the unity follower) is the simplest because it needs no additional external
components. If V1 and V2 are equal, then V0 should ideally be zero. Even if V1 differs from V2
by a very small amount, V0 is large because of amplifier’s high gain. Hence, circuit of Fig. 3.42
can detect very small changes which is another way of saying that it compares two signals.
Figure 3.42 Op – amp comparator

Active Filters
A popular application uses op-amps to build active filter circuits. A filter circuit can be
constructed using passive components: resistors and capacitors. An active filter additionally uses
an amplifier to provide voltage amplification and signal isolation or buffering. A filter that
provides a constant output from dc up to upper cutoff frequency fOH and then passes no signal
above that frequency is called an ideal low-pass filter. The ideal response of a low-pass filter is
shown in Fig. 3.43a. A filter that provides or passes signals above lower cutoff frequency fOL is a
high-pass filter, as indicated in Fig. 3.43b. When the filter circuit passes signals between the
lower and upper cutoff frequency, it is called a band pass filter, as indicated in Fig.3.43c.
Figure 3.43 Ideal filter response: (a) low-pass; (b) high-pass; (c) band pass
Low-Pass Filter
A first-order, low-pass filter using a single resistor and capacitor as in Fig. 3.44a has a practical
slope of - 20 dB per decade, as shown in Fig. 3.44b (rather than the ideal response of Fig. 3.43a).
The voltage gain below the cutoff frequency is constant at
A cutoff frequency
Figure 3.44 First-order low-pass active filter
Example 3.11
Calculate the cutoff frequency of a first-order low-pass filter for R1 = 1.2 kΩ and C1 = 0.02 µF.
Solution
High-Pass Active Filter

First- and second-order high-pass active filters can be built as shown in Fig. 3.45. The amplifier
gain and the amplifier lower cutoff frequency are
With a second-order filter R1 = R2, and C1 = C2 results in the same cutoff frequency.
Figure 3.45 High-pass filter: (a) first order; (b) second order; (c) response plot
Example 3.12
Calculate the cutoff frequency of a second-order high-pass filter as in Fig. 3.45b for R1 = R2 =
2.1 kΩ, C1 = C2 = 0.05 µF, and Ro1 = 10 kΩ, Rof = 50 kΩ.
Solution
The cutoff frequency is
Band pass Filter

Figure 3.46 shows a band pass filter using two stages, the first is a high-pass filter and the second
is a low-pass filter, the combined operation of the two is being the desired band pass response.
Figure 3.46 Band pass active filter

Example 3.13
Calculate the cutoff frequencies of the band pass filter circuit of Fig. 3.46 with R1 = R2 = 10 kΩ,
C1 = 0.1 µF, and C2 = 0.002 µF.
Solution
Chapter Four
Wave shaping Circuits
Introduction
In the design of electronic systems, the need frequently arises for signals having prescribed
standard waveforms, for example, sinusoidal, square, triangular, or pulse. Systems in which
standard signals are required include computer and control systems where clock pulses are
needed for, among other things, timing; communication systems where signals of a variety of
waveforms are utilized as information carriers; and test and measurement systems where signals,
again of a variety of waveforms, are employed for testing and characterizing electronic devices
and circuits.
Multivibrators (MV)
These devices are very useful as pulse generating, storing and counting circuits. They are
basically two-stage amplifiers with positive feedback from the output of one amplifier to the
input of the other. This feedback (Fig. 4.1) is supplied in such a manner that one transistor is
driven to saturation and the other to cut-off. It is followed by new set of conditions in which the
saturated transistor is driven to cut-off and the cut-off transistor is driven to saturation.
There are three basic types of MVs distinguished by the type of coupling network employed.
1. astable multivibrator (AVM),
2. monostable multivibrator (MMV),
3. bistable multivibrator (BMV). The first one is the non-driven type whereas the other two are
the driven type (also called triggered oscillators).
Figure 4.1
1. Astable Multivibrator (AMV)

It is also called free-running relaxation oscillator. It has no stable state but only two quasi-stable
(half-stable) states between which it keeps oscillating continuously of its own accord without any
external excitation.
In this circuit, neither of the two transistors reaches a stable state. When one is ON, the other is
OFF and they continuously switch back and forth at a rate depending on the RC time constant in
the circuit. Hence, it oscillates and produces pulses of certain mark-to-space ratio. Moreover, two
outputs (180° out of phase with each other) are available. It has two energy-storing elements i.e.
two capacitors.
2. Monostable Multivibrator (MMV)

It is also called a single-shot or single swing or a one-shot multivibrator. Other names are: delay
multivibrator and univibrator.
It has
(i) One absolutely stable (stand-by) state and (ii) one quasistable state
It can be switched to the quasi-stable state by an external trigger pulse but it returns to the stable
condition after a time delay determined by the value of circuit components. It supplies a single
output pulse of a desired duration for every input trigger pulse. It has one energy-storing element
i.e. one-capacitor.
3. Bistable Multivibrator (BMV)

It is also called as flip-flop multivibrator. It has two absolutely stable states. It can remain in
either of these two states unless an external trigger pulse switches it from one state to the other.
Obviously, it does not oscillate. It has no energy storage element. Detailed discrete circuits for
the above MVs are discussed below after listing their uses.
Uses of Multivibrators
Some of their uses are:
1. as frequency dividers
2. as saw tooth generators
3. as square wave and pulse generators
4. as a standard frequency source when synchronized by an external crystal oscillator

5. for many specialized uses in radar and TV circuits
6. as memory elements in computers
Astable Multivibrator
Fig. 4.2 shows the circuit of a symmetrical collector-coupled AMV using two similar transistors.
It consists of two CE amplifier stages, each providing a feedback to the other. The feedback ratio
is unity and positive because of 180° phase shift in each stage. Hence, the circuit oscillates.
Because of the very strong feedback signal, the transistors are driven either to saturation or to
cut-off (they do not work on the linear region of their characteristics).
The transistor Q1 is forward-biased by VCC and R1 whereas Q2 is forward-biased by VCC and R2.
The collector-emitter voltages of Q1 and Q2 are determined respectively by RL1 and RL2 together
with VCC. The output of Q1 is coupled to the input of Q2 by C2 whereas output of Q2 is coupled to
Q1 by C1.
Note that it is not essential to draw the coupling leads at 45° to the vertical as shown but it is
usually done because it helps to identify the circuit immediately as MV.
Figure 4.2 Astable Multivibrator circuit with an o/p wave form
The output can be taken either from point A or B though these would be phase-reversed with
respect to each other as shown in Fig. 4.2.
Circuit Operation
The circuit operation would be easy to understand if it is remembered that due to feedback
(i) when Q1 is ON, Q2 is OFF and
(ii) when Q2 is ON, Q1 is OFF.
When the power is switched on by closing S, one of the transistors will start conducting before
the other does (or slightly faster than the other). Suppose that Q1 starts conducting before Q2
does. The feedback system is such that Q1 will be very rapidly driven to saturation and Q2 to cut-
off.
The following sequence of events will occur:
1. Since Q1 is in saturation, whole of VCC drops across RL1. Hence, VC1 = 0 and point A is at zero
or ground potential.
2. Since Q2 is in cut-off i.e. it conducts no current, there is no drop across R L2. Hence, point B is
at VCC.
3. Since A is at 0 V, C2 starts to charge through R2 towards VCC.
4. When voltage across C2 rises sufficiently (i.e. more than 0.7 V), it biases Q2 in the forward
direction so that it starts conducting and is soon driven to saturation.
5. VC2 decreases and becomes almost zero when Q2 gets saturated. The potential of point B
decreases from VCC to almost 0 V. This potential decrease (negative swing) is applied to the
base of Q1 through C1. Consequently, Q1 is pulled out of saturation and is soon driven to cut-
off.
6. Since, now, point B is at 0 V, C1 starts charging through R1 towards the target voltage VCC.
7. When voltage of C1 increases sufficiently, Q1 becomes forward-biased and starts conducting.
In this way, the whole cycle is repeated.
It is seen that the circuit alternates between a state in which Q1 is ON and Q2 is OFF and a state
in which Q1 is OFF and Q2 is ON. The time in each state depends on RC values. Since each
transistor is driven alternately into saturation and cut-off the voltage wave from at either
collector (points A and B in Fig. 4.2) is essentially a square waveform with peak amplitude equal
to VCC (Fig. 4.3).
Figure 4.3
Switching Times
It can be proved that off-time for Q1 is T1 = 0.69 R1C1 and that for Q2 is T2 = 0.69 R2C2.
Hence, total time-period of the wave is
T = T1 + T2= 0.69 (R1C1 + R2 C2)
If R1 = R2 = R and C1 = C2 = C i.e. the two stages are symmetrical, then T = 1.38 RC
Frequency of Oscillation
It is given by the reciprocal of time period,
Minimum Values of β
To ensure oscillations, the transistors must saturate for which minimum values of β are as under:
Example 1
Determine the period and frequency of oscillation for an astable multivibrator with component
values: R1 = 2 K, R2 = 20 K, C1 = 0.01 μF and C2 = 0.05 μF.
Solution
T1 = 0.69 × 2 k × 0.01 μF = 13.8 μs
T2 = 0.69 × 20 k × 0.05 μF = 690 μs

T = T1 + T2 = 13.8 μs + 690 μs = 703.8 μs
f =1/T = 1/703.8μs = 1.42 kHz
Monostable Multivibrator (MMV)

A typical MMV circuit is shown in Fig. 4.4. Here, Q1 is coupled to Q2 base as in an AMV but the
other coupling is different. In this multivibrator, a single narrow input trigger pulse produces a
single rectangular pulse whose amplitude, pulse width and wave shape depend upon the values
of circuit components rather than upon the trigger pulse.
Initial Condition
In the absence of a triggering pulse at C2 and with S closed,
Figure 4.4 Monostable multivibrator circuit

1. VCC provides reverse bias for C/B junctions of Q1 and Q2 but forward-bias for E/B junction of
Q2 only. Hence, Q2 conducts at saturation.
2. VBB and R3 reverse bias Q1 and keep it cut off.
3. C1 charges to nearly VCC through RL1 to ground by the low-resistance path provided by
saturated Q2.
As seen, the initial stable state is represented by
(i) Q2 conducting at saturation and (ii) Q1 cut-off
When Trigger Pulse is applied

When a trigger pulse is applied to Q1 through C2, MMV will switch to its opposite unstable state
where Q2 is cut-off and Q1 conducts at saturation. The chain of circuit actions is as under:
1. If positive trigger pulse is of sufficient amplitude, it will override the reverse bias of the E/B
junction of Q1 and give it a forward bias. Hence, Q1 will start conducting.
2. As Q1 conducts, its collector voltage falls due to voltage drop across RL1. It means that
potential of point A falls (negative-going signal). This negative-going voltage is fed to Q2 via
C1 where it decreases its forward bias.
3. As collector current of Q1 starts decreasing, potential of point B increases (positive-going
signal) due to lesser drop over RL2. Soon, Q2 comes out of conduction.
4. The positive-going signal at B is fed via R1 to the base of Q1 where it increases its forward bias
further. As Q1 conducts more, potential of point A approaches 0 V.
5. This action is cumulative and ends with Q1 conducting at saturation and Q2 cut-off.
Return to Initial Stable State

1. As point A is at almost 0 V, C1 starts to discharge through saturated Q1 to ground.
2. As C1 discharges, the negative potential at the base of Q2 is decreased. As C1 discharges
further, Q2 is pulled out of cut-off.
3. As Q2 conducts further, a negative-going signal from point B via R1 drives Q1 into cut-off.
Hence, the circuit reverts to its original state with Q2 conducting at saturation and Q1 cut-off.
It remains in this state till another trigger pulse comes along when the entire cycle repeats
itself. As shown in Fig. 4.4, the output is taken from the collector of Q2 though it can also be
taken from point A of Q1. The width of this pulse is determined by the time constant of C1 R2.
Since this MV produces one output pulse for every input trigger pulse it receives, it is called
mono or one-shot multivibrator.
The width or duration of the pulse is given by T = 0.69 C1R2. It is also known as the one-shot
period.
Uses
1. The falling part of the output pulse from MMV is often used to trigger another pulse generator
circuit thus producing a pulse delayed by a time T with respect to the input pulse.
2. MMV is used for regenerating or rejuvenating old and worn out pulses. Various pulses used in
computers and telecommunication systems become somewhat distorted during use. A MMV
can be used to generate new, clean and sharp pulses from these distorted and used ones.
Example 2
A 20 kHz, 75% duty cycle square (tp) wave is used to trigger continuously, a monostable
multivibrator with triggered pulse duration of 5μs. What will be the duty cycle of the waveform
at output (B) of the monostable multivibrator (refer to Fig. 4.4).
Solution
Time period of the square wave
Since the duty cycle of the square wave is 75%, therefore the time interval during which the
input waveform is at a higher voltage level 0.75 × 50 μs = 37.5 μs. Fig. 4.5 (a) shows a sketch of
the input waveform which is used to trigger the monostable multivibrator.
Now the monostable multivibrator is triggered once each time a new pulse arrives. The
monostable multivibrator remains triggered only for a duration, tp = 5 μs. A sketch of the
waveform at the output (B) of the monostable multivibrator is as shown in Fig. 4.5 (b).
Figure 4.5
Bistable Multivibrator (BMV)
The basic circuit is shown in Fig. 4.6. As stated earlier, it has two absolutely stable states. It can
stay in one of its two states indefinitely (as long as power is supplied) changing to the other state
only when it receives a trigger pulse from outside. When it receives another triggering pulse,
only then it goes back to its original state. Since one trigger pulse causes the MV to ‘flip’ from
one state to another and the next pulse causes it to ‘flop’ back to its original state, the BMV is
also popularly known as ‘flip-flop’ circuit. The BMV circuit shown in Fig. 4.6 differs from the
AMV circuit of Fig. 4.2 in the following respects:
1. the base resistors are not joined to VCC but to a common source –VBB
2. the feedback is coupled through two resistors (not capacitors)
Figure 4.6 Bistable multivibrator circuit

Circuit Action
If Q1 is conducting, then the fact that point A is at nearly 0 V makes the base of Q2 negative (by
the potential divider R2 – R4) and holds Q2 off.
Similarly, with Q2 OFF, the potential divider from VCC to –VBB (RL2, R1, and R3) is designed to
keep base of Q1 at about 0.7 V ensuring that Q1 conducts. It is seen that Q1 holds Q2 OFF and Q3
holds Q1 ON.
Suppose, now, a positive pulse is applied momentarily to R, it will cause Q2 to conduct. As

collector of Q2 falls to zero, it cuts Q1 OFF and, consequently, the BMV switches over to its
other state.
Similarly, a positive trigger pulse applied to S will switch the BMV back to its original state.
Uses
1. in timing circuits as a frequency divider
2. in counting circuits
3. in computer memory circuits
Schmitt Trigger
The Schmitt trigger is a binary circuit and closely resembles a MV. It has two stable states and
the magnitude of the input voltage determines which of the two is possible. It is also called
emitter-coupled binary oscillator because positive feedback occurs by coupling through emitter
resistor RE.
The Quiescent Condition

As shown in Fig. 4.7, it consists of two similar transistors Q1 and Q2 coupled through RE.
Resistors R1, R3 and R4 form a voltage divider across VCC and –VBB which places a small positive
voltage (forward bias) on the base of Q2. Hence, when power is first switched ON, Q2 starts
conducting. The flow of current through RE places a small reverse bias on the base of Q1, thereby
cutting it OFF. Consequently, collector of Q1 rises to VCC. This positive voltage, coupled to the
base of Q2 through R3, drives Q2 into saturation and holds it there.
Hence, in the initial static or quiescent condition of the Schmitt trigger,

1. Q2 is in saturation 3. collector of Q2 is at 0 V
2. Q1 is cut-off 4. collector of Q1 is at VCC
Figure 4.7 Schmitt trigger circuit

Circuit Action
Suppose, positive half-cycle of the input ac voltage is applied to the trigger input first. Let us
further suppose that this positive voltage is sufficient to overcome the reverse bias on the base of
Q1 placed there by the voltage drop across RE. Then, the chain of events that follows is as under:
1. Q1 comes out of cut-off and starts to conduct
2. as it does so, its collector voltage drops (swings negative)

3. this negative-swinging voltage coupled to the base of Q2 via R3 reduces its forward bias
and hence its emitter current
4. with reduced emitter current, voltage drop across RE is reduced;
5. consequently, reverse bias of Q1 is further lowered and it conducts more heavily
6. as a result, collector voltage of Q1 falls further, thereby driving Q2 still closer to cut-off
This process is cumulative and ends up with

(a) Q1 conducting at saturation with its collector voltage almost zero
(b) Q2 becoming cut-off with its collector voltage nearly VCC
Negative Half-cycle of the Input Voltage

Now, when the negative half-cycle of the input voltage is applied
1. Q1 becomes reverse-biased. Consequently, its collector current falls and collector voltage rises
(i.e. potential of point A increases towards VCC)
2. this positive-swinging voltage is coupled to the base of Q2 through R3 and, as a result, Q2 is
driven to saturation
3. this re-establishes the original conditions of
(a) Q1 cut off with collector voltage at VCC and
(b) Q2 at saturation with collector voltage at 0 V
It completes one cycle. This cycle is repeated as the input voltage rises and falls again. Hence,
each cycle of the Schmitt trigger produces a positive-going pulse at its output which is taken out
from the collector of Q2 i.e. from point B in Fig. 4.8
Output Pulse Width

It depends on the time during which Q2 is conducting. It, in turn, depends on the input voltage,
within the limits imposed by emitter resistor RE.
Figure 4.8
Uses
1. It is frequently used for wave-shaping purposes. As shown in Fig. 4.8, it can convert inputs
with any wave shape into output pulses having rectangular or square wave shapes. That is
why Schmitt trigger is often called a ‘squaring’ circuit or a ‘squarer’ circuit.
2. It can reshape worn-out pulses by giving them sharp leading and trailing edges.
3. Since a change of state occurs whenever the input crosses a trigger point, the Schmitt trigger is
often used as a level detector i.e. as a pulse height discriminator.
Timer IC Circuit Unit Operation

Another popular analog–digital integrated circuit is the versatile 555 timer. The IC is made of a
combination of linear comparators and digital flip-flops as described in Fig. 4.9. The entire
circuit is usually housed in an 8-pin package as specified in Fig. 4.9. A series connection of three
resistors sets the reference voltage levels to the two comparators at 2/3VCC and 1/3VCC, the output
of these comparators setting or resetting the flip-flop unit. The output of the flip-flop circuit is
then brought out through an output amplifier stage. The flip-flop circuit also operates a transistor
inside the IC, the transistor collector usually being driven low to discharge a timing capacitor.
Figure 4.9 Details of 555 timer IC
Astable Operation
One popular application of the 555 timer IC is as an astable multivibrator or clock circuit. The
following analysis of the operation of the 555 as an astable circuit includes details of the
different parts of the unit and how the various inputs and outputs are utilized. Figure 4.10 shows
an astable circuit built using an external resistor and capacitor to set the timing interval of the
output signal.
Figure 4.10 Astable multivibrator using 555 IC
Capacitor C charges toward VCC through external resistors RA and RB. Referring to Fig. 4.10, the
capacitor voltage rises until it goes above 2/3VCC. This voltage is the threshold voltage at pin 6,
which drives comparator 1 to trigger the flip-flop so that the output at pin 3 goes low. In
addition, the discharge transistor is driven on, causing the output at pin 7 to discharge the
capacitor through resistor RB. The capacitor voltage then decreases until it drops below the
trigger level (VCC/3). The flip flop is triggered so that the output goes back high and the
discharge transistor is turned off, so that the capacitor can again charge through resistors RA and
RB toward VCC. Figure 17.18a shows the capacitor and output waveforms resulting from the
astable circuit. Calculation of the time intervals during which the output is high and low can be
made using the relations
Thigh 0.7(RA + RB) C
Tlow 0.7RBC
The total period is
T = period = Thigh + Tlow
The frequency of the astable circuit is then calculated using
Figure 4.11 astable multivibrator circuit with 555 timer
Figure 4.11 b wave forms of the astable multivibrator circuit with timer
The period can be directly calculated from

T = 0.693(RA + 2RB) C 0.7(RA + 2RB) C
Example 3
Determine the frequency and draw the output waveform for the circuit of Fig. 4.11a.
Solution
Monostable Operation
The 555 timer can also be used as a one-shot or monostable multivibrator circuit, as shown in
Fig. 4.12. When the trigger input signal goes negative, it triggers the one shot, with output at pin
3 then going high for a time period
Thigh = 1.1RAC
Referring back to Fig. 4.9, the negative edge of the triggering input causes comparator 2 to
trigger the flip-flop, with the output at pin 3 going high. Capacitor C charges toward VCC through
resistor RA. During the charge interval, the output remains high. When the voltage across the
capacitor reaches the threshold level of 2/3VCC, comparator 1 triggers the flip-flop, with output
going low. The discharge transistor also goes low, causing the capacitor to remain at near 0 V
until triggered again. Figure 4.12b shows the input trigger signal and the resulting output
waveform for the 555 timer operated as a one-shot. Time periods for this circuit can range from
microseconds to many seconds, making this IC useful for a range of applications.
Figure 4.12 (a) mono stable multivibrator circuit with 555 timer
Figure 4.12 (b) wave forms of mono stable multivibrator circuit with 555 timer
Example 4
Determine the period of the output waveform for the circuit of Fig. 4.12 above given RA = 7.5
kΩ, C = 0.1 µF, C = 0.01 µF, VCC and triggered by a negative pulse.
Solution
Thigh = 1.1RAC = 1.1(7.5 x 10 3) (0.1 x 10 - 6) = 0.825 ms
Oscillators
What is an Oscillator?
An electronic oscillator may be defined in any one of the following four ways:
1. It is a circuit which converts dc energy into ac energy at a very high frequency
2. It is an electronic source of alternating current or voltage having sine, square or saw tooth or
pulse shapes
3. It is a circuit which generates an ac output signal without requiring any externally applied
input signal
4. It is an unstable amplifier. These definitions exclude electromechanical alternators producing
50 Hz ac power or other devices which convert mechanical or heat energy into electric energy.
Comparison between an Amplifier and Oscillator

As discussed in Chapter 1, an amplifier produces an output signal whose waveform is similar to
the input signal but whose power level is generally high. This additional power is supplied by the
external dc source. Hence, an amplifier is essentially an energy convertor i.e. it takes energy
from the dc power source and converts it into ac energy at signal frequency. The process of
energy conversion is controlled by the input signal. If there is no input signal, there is no energy
conversion and hence there is no output signal.
An oscillator differs from an amplifier in one basic aspect: the oscillator does not require an
external signal either to start or maintain energy conversion process (Fig. 4.13). It keeps
producing an output signal so long as the dc power source is connected.
Moreover, the frequency of the output signal is determined by the passive components used in
the oscillator and can be varied as well.
Figure 4.13 comparison of oscillator and amplifier

Classification of Oscillators
Electronic oscillators may be broadly divided into two broad groups:
(i) Sinusoidal (or harmonic) oscillators: produce an output having sine wave form.
(ii) Non-sinusoidal (or relaxation) oscillators: produce an output of square, rectangular or saw
tooth waveform or is of pulse shape.
Sinusoidal oscillators may be further subdivided into:

(a) Tuned-circuits or LC feedback oscillators such as Hartley, Colpitts and Clapp etc
(b) RC phase-shift oscillators such as Wien-bridge oscillator
(c) Negative-resistance oscillators such as tunnel diode oscillator
(d) Crystal oscillators such as Pierce oscillator
(e) Heterodyne or beat-frequency oscillator (BFO)
The active devices in an electronic oscillator are bipolar, FETs or uni junction transistors and
operate as class A, B or C. Class A operation is used in high-quality audio frequency oscillators.
However, radio frequency oscillators are usually operated as class C.
Damped and Undamped Oscillations

Sinusoidal oscillations produced by oscillators may be
(i) damped or
(ii) Undamped
(i) Damped Oscillations
Oscillations whose amplitude keeps decreasing (or decaying) with time are called damped or
decaying oscillations. The waveform of such oscillations is shown in Fig. 4.14 (a). These are
produced by those oscillator circuits in which I 2R losses take place continuously during each
oscillation without any arrangement for compensation. Ultimately, the amplitude of the
oscillations decays to zero when there is not enough energy to supply circuit losses. However,
the frequency or time-period remains constant because it is determined by the circuit parameters.
Sinusoidal oscillators serve a variety of functions in telecommunications and in electronics. The

most important application in telecommunication is the use of sine waves as carrier signal in
both radio and cable transmissions.
Sine wave signals are also used in frequency response testing of various types of systems and
equipment including analogue communication channels, amplifiers and filters and closed-loop
control systems.
Figure 4.14 damped and undamped oscillation wave forms
(ii) Undamped Oscillations

Oscillations whose amplitude remains constant i.e. does not change with time are called
undamped oscillations. These are produced by those oscillator circuits which have no losses or if
they have, there is provision for compensation. The constant-amplitude and constant-frequency
sinusoidal waves shown in Fig. 4.14 (b) are called carrier waves and are used in communication
transmitters for transmitting low-frequency audio information to far off places.
The Oscillatory Circuit

It is also called LC circuit or tank circuit. The oscillatory circuit (Fig. 4.15) consists of two
reactive elements i.e. an inductor and a capacitor. Both are capable of storing energy. The
capacitor stores energy in its electric field whenever there is potential difference across its plates.
Similarly, a coil or an inductor stores energy in its magnetic field whenever current flows
through it. Both L and C are supposed to be loss-free (i.e. their Q-factors are infinite). As shown
in Fig. 4.15 (a), suppose the capacitor has been fully-charged from a dc source. Since S is open,
it cannot discharge through L. Now, let us see what happens when S is closed.
1. When S is closed [Fig. 4.15 (b)] electrons move from plate A to plate B through coil L as
shown by the arrow (or conventional current flows from B to A). This electron flow
reduces the strength of the electric field and hence the amount of energy stored in it.
2. As electronic current starts flowing, the self-induced emf in the coil opposes the current
flow. Hence, rate of discharge of electrons is somewhat slowed down.
3. Due to the flow of current, magnetic field is set up which stores the energy given out by
the electric field [Fig. 4.15 (b)].
4. . As plate A loses its electrons by discharge, the electron current has a tendency to die
down and will actually reduce to zero when all excess electrons on A are driven over to
plate B so that both plates are reduced to the same potential. At that time, there is no
electric field but the magnetic field has maximum value.
5. . However, due to self-induction (or electrical inertia) of the coil, more electrons are
transferred to plate B than are necessary to make up the electron deficiency there. It
means that now plate B has more electrons than A. Hence, capacitor becomes charged
again though in opposite direction as shown in Fig. 4.15 (c).
6. The magnetic field L collapses and the energy given out by it is stored in the electric field
of the capacitor.
7. After this, the capacitor starts discharging in the opposite direction so that, now, the
electrons move from plate B to plate A [Fig. 65.3 (d)]. The electric field starts collapsing
whereas magnetic field starts building up again though in the opposite direction. Fig. 4.15
(d) shows the condition when the capacitor becomes fully discharged once again.
8. However, these discharging electrons overshoot and again an excess amount of electrons
flow to plate A, thereby charging the capacitor once more.
9. This sequence of charging and discharging continues. The to and fro motion of electrons
between the two plates of the capacitor constitutes an oscillatory current.
It may be also noted that during this process, the electric energy of the capacitor is converted
into magnetic energy of the coil and vice versa.
These oscillations of the capacitor discharge are damped because energy is dissipated away
gradually so that their amplitude becomes zero after sometime. There are two reasons for the
loss of the energy:
a. some energy is lost in the form of heat produced in the resistance of the coil and
connecting wires and
b. some energy is lost in the form of electromagnetic (EM) waves that are radiated
out from the circuit through which an oscillatory current is passing
Figure 4.15 simple LC oscillator circuit
Both these losses subtract energy from the circuit with the result that circuit current decreases
gradually till it becomes zero. The waveform of the oscillatory has damped output wave form.
Frequency of Oscillatory Current

The frequency of time-period of the oscillatory current depends on two factors:
(a) Capacitance of the Capacitor
Larger the capacitor, greater the time required for the reversal of the discharge current i.e. lower
its frequency.
(b) Self-inductance of the Coil
Larger the self-inductance, greater the internal effect and hence longer the time required by the
current to stop flowing during discharge of the capacitor.
The frequency of this oscillatory discharge current is given by
Where L = self-inductance in μH and C = capacitance in μF
Damped oscillations are not good for radio transmission purpose because of their limited range
and excessive distortion. For good radio transmission, we need undamped oscillations which can
be produced if some additional energy is supplied in correct phase and correct direction to the LC
circuit for making up the I2R losses continually occurring in the circuit.
Frequency Stability of an Oscillator

The ability of an oscillator to maintain a constant frequency of oscillation is called its frequency
stability. Following factors affect the frequency stability:
1. Operating Point of the Active Device
The Q-point of the active device (i.e. transistor) is so chosen as to confine the circuit operation
on the linear portion of its characteristic. Operation on non-linear portion varies the parameters
of the transistor which, in turn, affects the frequency stability of the oscillator.
2. Inter-element Capacitances
Any changes in the inter-element capacitances of a transistor particularly the collector- to-emitter
capacitance cause changes in the oscillator output frequency, thus affecting its frequency
stability. The effect of changes in inter-element capacitances can be neutralized by adding a
swamping capacitor across the offending element added capacitance being made part of the tank
circuit.
3. Power Supply
Changes in the dc operating voltages applied to the active device shift the oscillator frequency.
This problem can be avoided by using regulated power supply.
4. Temperature Variations
Variations in temperature cause changes in transistor parameters and also change the values of
resistors, capacitors and inductors used in the circuit. Since such changes take place slowly, they
cause a slow change (called drift) in the oscillator output frequency.
5. Output Load
A change in the output load may cause a change in the Q-factor of the LC tuned circuit thereby
affecting the oscillator output frequency.
6. Mechanical Vibrations
Since such vibrations change the values of circuit elements, they result in changes of oscillator
frequency. This instability factor can be eliminated by isolating the oscillator from the source of
mechanical vibrations.
Essentials of a Feedback LC Oscillator

The essential components of a feedback LC oscillator shown in Fig. 4.16 are:
1. A resonator which consists of an LC circuit. It is also known as frequency determining
network (FDN) or tank circuit.
2. An amplifier whose function is to amplify the oscillations produced by the resonator.
3. A positive feedback network (PFN) whose function is to transfer part of the output energy to
the resonant LC circuit in proper phase. The amount of energy fed back is sufficient to meet
I2R losses in the LC circuit.
The essential condition for maintaining oscillations and for finding the value of frequency is
It means that
(i) The feedback factor or loop gain | βA | = 1,
(ii) The net phase shift around the loop is 0° (or an integral multiple of 360°). In other words,
feedback should be positive.
The above conditions form Barkhausen criterion for maintaining a steady level of oscillation at a
specific frequency. Majority of the oscillators used in radio receivers and transmitters use tuned
circuits with positive feedback. Variations in oscillator circuits are due to the different way by
which the feedback is applied. Some of the basic circuits are:
1. Armstrong or Tickler or Tuned-base Oscillator: it employs inductive feedback from

collector to the tuned LC circuit in the base of a transistor.
2. Tuned Collector Oscillator: it also employs inductive coupling but the LC tuned circuit is in
the collector circuit.
3. Hartley Oscillator: here feedback is supplied inductively.
4. Colpitts Oscillator: here feedback is supplied capacitively
5. Clapp Oscillator: it is a slight modification of the Colpitts oscillator
Tuned Oscillator
Such an oscillator using a transistor in CE configuration is shown in Fig. 4.16. Resistors R1, R2
and R3 determine the dc bias of the circuit. The parallel R3C2 network in the emitter circuit is a
stabilizing circuit to prevent signal degeneration. As usual, C1 is the dc blocking capacitor. The
mutually-coupled coils L1 and L forming primary and secondary coils of an RF transformer
provide the required feedback between the collector and base circuits. The amount of feedback
depends on the coefficient of coupling between the two coils. The CE connected transistor itself
provides a phase shift of 180° between its input and output circuits. The transformer provides
another 180° phase shift and thus producing a total phase shift of 360° which is an essential
condition for producing oscillations.
The parallel-tuned LC circuit connected between base and emitter is the frequency determining
network (FDN) i.e. it generates the oscillations at its resonant frequency.
Figure 4.16 Tuned oscillator
Circuit operation
The moment switch S is closed, collector current is set up which tends to rise to its quiescent
value. This increase in IC is accompanied by:
1. An expanding magnetic field through L1 which links with L and
2. An induced e.m.f. called feedback voltage in L.
Two immediate reactions of this feedback voltage are:
(i) Increase in emitter-base voltage (and base current) and
(ii) A further increase in collector current IC.
It is followed by a succession of cycles of
1. An increase in feedback voltage
2. An increase in emitter-base voltage and
3. An increase in IC until saturation is reached.
Meanwhile, C gets charged. As soon as IC ceases to increase, magnetic field of L1 ceases to

expand and thus no longer induces feedback voltage in L. Having been charged to maximum
value, C starts to discharge through L. However, decrease in voltage across C causes the
following sequence of reactions:
1. A decrease in emitter-base bias and hence in IB
2. A decrease in IC
3. A collapsing magnetic field in L1
4. An induced feedback voltage in L though, this time, in opposite direction;

5. Further decrease in emitter-base bias and so on till IC reaches its cut-off value.
During this time, the capacitor having lost its original charge, again becomes fully charged
though with opposite polarity. Transistor being in cut-off, the capacitor will again begin to
discharge through L. Since polarity of capacitor charge is opposite to that when transistor was in
saturation, the sequence of reactions now will be
1. An increase in emitter-base bias 5. A further increase in emitter-base bias and
2. An increase in IC 6. So on till IC increases to its saturation
3. An expanding magnetic field in L1 value.
4. An induced feedback voltage in L
This cycle of operation keeps repeating so long as enough energy is supplied to meet losses in
the LC circuit.
The output can be taken out by means of a third winding L2 magnetically coupled to L1. It has
approximately the same waveform as collector current.
The frequency of oscillation is equal to the resonant frequency of the LC circuit.
Tuned Collector Oscillator

Such an oscillator using a transistor in CE configuration is shown in Fig. 4.17.
(i) Frequency Determining Network (FDN)
It is made up of a variable capacitor C and a coil L which forms primary winding of a step-down
transformer. The combination of L and C forms an oscillatory tank circuit to set the frequency of
oscillation.
Resistors R1, R2 and R3 are used to dc bias the transistor. Capacitor C1 and C2 act to bypass R3
and R2 respectively. So that, they have no effect on the ac operation of the circuit. Moreover, C2
provides ac ground for transformer secondary L1.
(ii) Positive Feedback

Feedback between the collector-emitter circuit and base-emitter circuit is provided by the
transformer secondary winding L1 which is mutually-coupled to L. As far as ac signals are
concerned, L1 is connected to emitter via low-reactance capacitors C2 and C1.
Figure 4.17 Tuned collector oscillator circuit
Since transistor is connected in CE configuration, it provides a phase shift of 180° between its
input and output circuits. Another phase shift of 180° is provided by the transformer thus
producing a total phase shift of 360° between the output and input voltages resulting in positive
feedback between the two.
(iii) Amplifying Action

The transistor amplifier provides sufficient gain for oscillator action to take place.
(iv) Working
When the supply is first switched on, a transient current is developed in the tuned LC circuit as
the collector current rises to its quiescent value. This transient current initiates natural
oscillations in the tank circuit. These natural oscillations induce a small emf into L1 by mutual
induction which causes corresponding variations in base current. These variations in IB are
amplified β times and appear in the collector circuit. Part of this amplified energy is used to meet
losses taking place in the oscillatory circuit and the balance is radiated out in the form of
electromagnetic waves.
The frequency of oscillatory current is almost equal to the resonant frequency of the tuned
circuit.
Tuned Drain Oscillator (FET)

The basic circuit is illustrated in Fig. 4.18. It is similar to the tuned collector oscillator of Fig.
4.17. Because of its high input impedance and high voltage amplification, a FET can be used to
construct very simple and efficient oscillator circuit. This frequency of oscillation is given by
Where rd = ac drain resistance

The value of mutual inductance required for maintaining oscillations is
Example 5
A tuned-collector oscillator has a fixed inductance of 100 μH and has to be tunable over the
frequency band of 500 kHz to 1500 kHz. Find the range of variable capacitor to be used.
Solution
Resonant frequency is given by
Where L and C refer to the tank circuit

When fo = 500 kHz
C = 1/4π 2 × (500 × 103)2 × 100 ×10–6= 1015 pF
When fo = 1500 kHz
C = 1015/ (1500/500)2=113 pF
Hence, capacitor range required is 113 – 1015 pF
Hartley Oscillator
In Fig. 4.18 (a) is shown a transistor Hartley oscillator using CE configuration. Its general
principle of operation is similar to the tuned-collector oscillator discussed above. It uses a single
tapped-coil having two parts marked L1 and L2 instead of two separate coils. So far as ac signals
are concerned, one side of L2 is connected to base via C1 and the other to emitter via ground and
C3. Similarly, one end of L1 is connected to collector via C2 and the other to common emitter
terminal via C3. In other words, L1 is in the output circuit i.e. collector-emitter circuit whereas
L2 is in the base-emitter circuit i.e. input circuit. These two parts are inductively-coupled and
form an auto-transformer or a split-tank inductor. Feedback between the output and input circuits
is accomplished through autotransformer action which also introduces a phase reversal of 180°.
This phase reversal between two voltages occurs because they are taken from opposite ends of an
inductor (L1 - L2 combination) with respect to the tap which is tied to common transistor terminal
i.e. emitter which is ac grounded via C3. Since transistor itself introduces a phase shift of 180°,
the total phase shift becomes 360° thereby making the feedback positive or regenerative which is
essential for oscillations. As seen, positive feedback is obtained from the tank circuit and is
coupled to the base via C1. The feedback factor is given by the ratio of turns in L2 and L1 i.e. by
N2/ N1 and its value ranges from 0.1 to 0.5. Fig. 4.18 (b) shows the equivalent circuit of Hartley
oscillator.
Resistors R1 and R2 form a voltage divider for providing the base bias and R3 is an emitter
swamping resistor to add stability to the circuit. Capacitor C3 provides ac ground thereby
preventing any signal degeneration while still providing temperature stabilization. Radio-
frequency choke (RFC) provides dc load for the collector and also keeps ac currents out of the dc
supply VCC.
Figure 4.18 Hartley oscillator circuit
The frequency of oscillation is given by
The output from the tank may be taken out by means of another coil coupled either to L1 or L2.
Example 6
Calculate the oscillation frequency for the transistor Hartley oscillator circuit (refer to Fig. 4.18).
Given the circuit values: LRFC = 0.5 mH, L1 = 750 μH, L2 = 750 μH, M = 150 μH and C = 150
pF.
Solution
Colpitts Oscillator
This oscillator is essentially the same as Hartley oscillator except for one difference. Colpitts
oscillator uses tapped capacitance whereas Hartley oscillator uses tapped inductance Fig. 4.19 (a)
shows the complete circuit with its power source and dc biasing circuit whereas Fig. 4.19 (b)
shows its ac equivalent circuit. The two series capacitors C1 and C2 form the voltage divider used
for providing the feedback voltage (the voltage drop across C2 constitutes the feedback voltage).
The feedback factor is C1/C2. The minimum value of amplifier gain for maintaining oscillations
is
The tank circuit consists of two ganged capacitors C1 and C2 and a single fixed coil. The
frequency of oscillation (which does not depend on mutual inductance) is given by
Transistor itself produces a phase shift of 180°. Another phase shift of 180° is provided by the
capacitive feedback thus giving a total phase shift of 360° between the emitter-base and collector
base circuits. Resistors R1 and R2 form a voltage divider across VCC for providing base bias, R3 is
for emitter stabilization and RFC provides the necessary dc load resistance RC for amplifier
action. It also prevents ac signal from entering supply dc VCC. Capacitor C5 is a bypass capacitor
whereas C4 conveys feedback from the collector-to-base circuit. When S is closed, a sudden
surge of collector current shock-excites the tank circuit into oscillations which are sustained by
the feedback and the amplifying action of the transistor. Colpitts oscillator is widely used in
commercial signal generators up to 1 MHz Frequency of oscillation is varied by gang-tuning the
two capacitors C1 and C2.
Figure 4.19 Colpitts oscillator circuit
Example 7
Determine the circuit oscillation frequency for a transistor Colpitts oscillator shown in Fig.
4.19(a). Given, L = 100 μH, LRFC = 0.5 mH, C1 = 0.005 μF, C2 = 0.01 μF. C6 = 10 μF
Solution
For a transistor Colpitts oscillator, the oscillation frequency,
Clapp Oscillator
It is a variation of Colpitts oscillator and is shown in Fig. 4.20 (a). It differs from Colpitts
oscillator in respect of capacitor C3 only which is joined in series with the tank inductor. Fig.
4.20 (b) shows the ac equivalent circuit.
Addition of C3 (i) improves frequency stability and (ii) eliminates the effect of transistor's
parameters on the operation of the circuit. The operation of this circuit is the same as that of the
Colpitts oscillator.
The frequency of oscillation is given by
Crystal Controlled Oscillator

Fig. 4.21 shows the use of a crystal to stabilize the frequency of a tuned-collector oscillator
which has a crystal (usually quartz) in the feedback circuit. The LC tank circuit has a frequency
of oscillation
The circuit is adjusted to have a frequency near about the desired operating frequency but the
exact frequency is set by the crystal and stabilized by the crystal. For example, if natural
frequency of vibration of the crystal is 27 MHz, the LC circuit is made to resonate at this
frequency.
As usual, resistors R1, R2 and R3 provide a voltage divider stabilized dc bias circuit. Capacitor C1
by passes R3 in order to maintain large gain. RFC coil L1 prevents ac signals from entering dc
line whereas RC is the required dc load of the collector. The coupling capacitor C2 has negligible
impedance at the operating frequency but prevents any dc link between collector and base. Due
to extreme stability of crystal oscillations, such oscillators are widely used in communication
transmitters and receivers where frequency stability is of prime importance.
Figure 4.21 Crystal controlled oscillator circuit
Modulation and Demodulation

Introduction
For successful transmission and reception of intelligence (code, voice, music etc.) by the use of
radio waves, two processes are essential:
(i) modulation and (ii ) demodulation
Speech and music etc. are sent thousands of kilometers away by a radio transmitter. The scene in
front of a television camera is also sent many kilometers away to viewers. Similarly, a Moon
probe or Venus probe checking its environments sends the information it gathers millions of
kilometers through space to receivers on earth. In all these cases, the carrier is the high-
frequency radio wave. The intelligence i.e. sight, sound or other data collected by the probe is
impressed on the radio wave and is carried along with it to the destination.
Modulation is the process of combining the low-frequency signal with a very high-frequency
radio wave called carrier wave (CW). The resultant wave is called modulated carrier wave. This
job is done at the transmitting station.
Demodulation is the process of separating or recovering the signal from the modulated carrier
wave. It is just the opposite of modulation and is performed at the receiving end.
What is a Carrier Wave?
It is a high-frequency undamped radio wave produced by radio-frequency oscillators. As seen

from Fig. 4.22, the output of these oscillators is first amplified and then passed on to an antenna.
This antenna radiates out these high-frequency (electromagnetic) waves into space. These waves
have constant amplitude and travel with the velocity of light. They are inaudible i.e. by
themselves they cannot produce any sound in the loudspeaker of a receiver. As their name
shows, their job is to carry the signal (audio or video) from transmitting station to the receiving
station. The resultant wave is called modulated carrier wave.
Figure 4.22
Radio Frequency Spectrum

Radio frequencies used by different communication systems extend from very low frequencies to
extra high frequencies as tabulated below along with their acronym abbreviations.
Table 4.1 radio frequency spectrum
Frequency Designation Abbreviation Uses
very low
3-30 kHz VLF long distance telegraphy broadcasting
frequency
low Long distance point-to-point service, navigational
30-300 kHz LF
frequency aids, sounds broadcasting and line carrier systems.
medium sound broadcasting, ship-shore services and line
300 kHz-3MHz MF
frequency carrier systems
high Medium and long-distance point-to-point services,
3-30 MHz HF
frequency sound broadcasting, linear carrier systems.
very high
30-300 MHz VHF short-distance communication, TV
frequency
ultra high
300 MHz-3GHz UHF sound broadcasting, radar
frequency
super high
3-30 GHz SHF Outer-space radio communication, point-to-point
frequency microwave communication systems and radar.
extra high
30-300 GHz EHF Outer-space radio communication, point-to-point
frequency microwave communication systems and radar.
Sound
It is a sort of disturbance which requires some physical medium for its propagation. Human
voice consists of a series of compressions and rarefactions which travel through air with a
velocity of about 345 m/s. The frequency range of human voice is from 20 - 4000 Hz which lies
within the audible range of 20 to 20,000 Hz. Variations in human voice can be converted into
corresponding variations in electric current with the help of a microphone as shown in Fig.4.23.
Figure 4.23 human speech signal as seen through oscilloscope
The two main characteristics of sound:

(i) Intensity: It is the energy content of the wave. It depends on its amplitude. In fact, intensity
of a wave is directly proportional to the square of its amplitude i.e. I a2. Sensation of loudness
felt by a listener depends directly on the intensity of the wave falling on his ears.
(ii) Frequency: It produces the sensation called pitch. Audible sounds have a frequency range
from 20 Hz to 20,000 Hz.
Need for Modulation

Sometimes, beginners question the necessity of modulation i.e. using a carrier wave to carry the
low-frequency signal from one place to another. The purposes of modulation are:
1. They have relatively short range
2. If everybody started transmitting these low-frequency signals directly, mutual
interference will render all of them ineffective
3. Size of antennas required for their efficient radiation would be large i.e. about 75 km as
explained below
For efficient radiation of a signal, the minimum length of an antenna is one quarter wavelength
(λ/4). The antenna length L is connected with the frequency of the signal wave by the relation
L = 75 × 10 6/f meters. For transmitting an audio signal of f = 1000 Hz, L = 75 × 10 6/10 3
=
75,000 m = 75 km. In view of this immense size of antenna length, it is impractical to radiate
audio-frequency signals directly into space.
Hence, the solution lies in modulation which enables a low-frequency signal to travel very large
distances through space with the help of a high-frequency carrier wave. These carrier waves need
Reasonably-sized antennas and produce no interference with other transmitters operating in the
same area.
Methods of Modulation
The mathematical expression for a sinusoidal carrier wave is
e = EC sin (ωc t + φ) = EC sin (2 πfc t + φ)
Obviously, the waveform can be varied by any of its following three factors or parameters:
1. EC — the amplitude 2. fc — the frequency 3. φ — the phase
Accordingly, there are three types of sine-wave modulations known as:
1. Amplitude Modulation (AM)
Here, the information or AF signal changes the amplitude of the carrier wave without changing
its frequency or phase.
2. Frequency Modulation (FM)
In this case, the information signal changes the frequency of the carrier wave without changing
its amplitude or phase.
3. Phase Modulation (PM)

Here, the information signal changes the phase of the carrier wave without changing its other two
parameters.
Amplitude Modulation
In this case, the amplitude of the carrier wave is varied in proportion to the instantaneous
amplitude of the information signal or AF signal. Obviously, the amplitude (and hence the
intensity) of the carrier wave is changed but not its frequency. Greater the amplitude of the AF
signal, greater the fluctuations in the amplitude of the carrier wave.
The process of amplitude modulation is shown graphically in Fig. 4.24. For the sake of
simplicity, the AF signal has been assumed sinusoidal [Fig. 4.24 (a)]. The carrier wave by which
it is desired to transmit the AF signal is shown in Fig. 4.24 (b). The resultant wave called
modulated wave is shown in Fig. 4.24 (c).
Figure 4.24 wave forms
Percent Modulation
It indicates the degree to which the AF signal modulates the carrier wave
The ratio B/A expressed as a fraction is called modulation index (MI)

m = M.I. × 100
From Fig. 4.24, it is seen that B = 1 V and A = 1.5 V
Modulation may also be defined in terms of the values referred to the modulated carrier wave.
Where Ec(max) and Ec(min) are the maximum and minimum values of the amplitude of the
modulated carrier wave.
Again, from Fig. 4.24 we see that
Fig. 4.25 shows a modulated wave with different degrees of modulation. As before, both the
signal and carrier waves are assumed to be sine waves.
Figure 4.25
Frequency Modulation
As the name shows, in this modulation, it is only the frequency of the carrier which is changed
and not its amplitude. The amount of change in frequency is determined by the amplitude of the
modulating signal whereas rate of change is determined by the frequency of the modulating
signal. As shown in Fig. 4.26, in an FM carrier, information (or intelligence) is carried as
variations in its frequency.
Figure 4.26 FM signal wave forms
Demodulation or Detection
When the RF modulated waves, radiated out from the transmitter antenna, after travelling
through space, strike the receiving aerials, they induce very weak RF currents and voltages in
them. If these high-frequency currents are passed through headphones or loudspeakers, they
produce no effect on them because all such sound-producing devices are unable to respond to
such high frequencies due to large inertia of their vibrating discs etc. Neither will such RF
currents produce any effect on human ear because their frequencies are much beyond the audible
frequencies (20 to 20,000 Hz approximately). Hence, it is necessary to demodulate them first in
order that the sound-producing devices may be actuated by audio-frequency current similar to
that used for modulating the carrier wave at the broadcasting station.
This process of recovering AF signal from the modulated carrier wave is known as demodulation
or detection.
The demodulation of an AM wave involves two operations:

(i) rectification of the modulated wave and
(ii) elimination of the RF component of the modulated wave
However, demodulation of an FM wave involves three operations (i) conversion of frequency

changes produced by modulating signal into corresponding amplitude changes, (ii) rectification
of the modulating signal and (iii) elimination of RF component of the modulated wave.
Chapter Five
Digital Electronics
5.1. Brief overview of Basic and derived logic gates
5.2. Realization of discrete logic gates
5.3. Digital integrated circuits and logic families
5.4. Comparison of common logic families
INTRODUCTION
The term digital is derived from the way computers perform operations, by counting digits. For
many years, applications of digital electronics were confined to computer systems. Today,
digital technology is applied in a wide range of areas in addition to computers. Such applications
as television, communications systems, radar, navigation and guidance systems, military
systems, medical instrumentation, industrial process control, and consumer electronics use
digital techniques. Over the years digital technology has progressed from vacuum-tube circuits to
discrete transistors to complex integrated circuits.
DIGITAL AND ANALOG QUANTITIES

Electronic circuits can be divided into two broad categories, digital and analog. Digital
electronics involves quantities with discrete values, and analog electronics involves quantities
with continuous values. Although you will be studying digital fundamentals in this chapter, you
should also know something about analog because many applications require both; and
interfacing between analog and digital is important.
An analog quantity is one having continuous values. A digital quantity is one having a discrete
set of values. Most things that can be measured quantitatively occur in nature in analog form. For
example, the air temperature changes over a continuous range of values. During a given day, the
temperature does not go from, say, 70° to 71 ° instantaneously; it takes on all the infinite values
in between. If you graphed the temperature on a typical summer day, you would have a smooth,
continuous curve similar to the curve in Figure 5.1. Other examples of analog quantities are time,
pressure, distance, and sound.
Figure 5.1 Graph of an analog quantity (temperature versus time)
The Digital Advantage

Digital representation has certain advantages over analog representation in electronics
applications. For one thing, digital data can be processed and transmitted more efficiently and
reliably than analog data. Also, digital data has a great advantage when storage is necessary. For
example, music when converted to digital form can be stored more compactly and reproduced
with greater accuracy and clarity than form. Noise (unwanted voltage fluctuations) does not
affect digital data nearly as much as it does analog signals.
Figure 5.2 Sampled value representations (quantization) of the analog quantity in Figure 5.1
An Analog Electronic System

A public address system, used to amplify sound so that it can be heard by a large audience, is one
simple example of an application of analog electronics. The basic diagram in Figure 5.3
illustrates that sound waves, which are analog in nature, are picked up by a microphone and
converted to a small analog voltage called the audio signal. This voltage varies continuously as
the volume and frequency of the sound changes and is applied to the input of a linear amplifier.
The output of the amplifier, which is an increased reproduction of input voltage, goes to the
speaker(s). The speaker changes the amplified audio signal back to sound waves that have a
much greater volume than the original sound waves picked up by the microphone.
Figure 5.3 Basic audio public address system
A System Using Digital and Analog Methods

The compact disk (CD) player is an example of a system in which both digital and analog
circuits are used. The simplified block diagram in Figure 5.4 illustrates the basic principle. Music
in digital form is stored on the compact disk. A laser diode optical system picks up the digital
data from the rotating disk and transfers it to the digital-to-analog converter (DAC).
Figure 5.4 Basic block diagram of a CD player

Binary Digits, Logic Levels, and Digital Waveforms
Digital electronics involves circuits and systems in which there are only two possible states.
These states are represented by two different voltage levels: A HIGH and a LOW. The two states
can also be represented by current levels, bits and bumps on a CD or DVD etc. In digital systems
such a computers, combinations of the two states, called codes, are used to represent numbers,
symbols, alphabetic characters, and other types of information. The two-state number system is
called binary, and its two digits are 0 and 1. A binary digit is called a bit.
Binary Digits
Each of the two digits in the binary system, 1 and 0, is called a bit, which is a contraction of the
words binary digit. In digital circuits, two different voltage levels are used to represent the two
bits. Generally, 1 is represented by the higher voltage, which we will refer to as a HIGH, and a 0
is represented by the lower voltage level, which we will refer to as a LOW. This is called
positive logic and will be used throughout the book.
HIGH = 1 and LOW = 0
Another system in which a 1 is represented by a LOW and a 0 is represented by a HIGH is called
negative logic.
Digital Waveforms
Digital waveforms consist of voltage levels that are changing back and forth between the HIGH
and LOW levels or states. Figure 5.5 (a) shows that a single positive-going pulse is generated
when the voltage (or current) goes from its normally LOW level to its HIGH level and then back
to its LOW level. The negative-going pulse in Figure 5.5 (b) is generated when the voltage goes
from its normally HIGH level to its LOW level and back to its HIGH level. A digital waveform
is made up of a series of pulses.
Figure 5.5 Ideal pulses
An important characteristic of a periodic digital waveform is its duty cycle, which is the ratio of
the pulse width (tw) to the period (T). It can be expressed as a percentage.
Example 5.1
A portion of a periodic digital waveform is shown in Figure 5.6. The measurements are in
milliseconds. Determine the following:

(a) Period (b) frequency (c) duty cycle
Figure 5.6
Solution
(a) The period is measured from the edge of one pulse to the corresponding edge of the next
pulse. In this case T is measured from leading edge to leading edge, as indicated. T
equals 10 ms
(b)
(c)
Number systems, operations and codes

Introduction
The binary number system and digital codes are fundamental to computers and to digital
electronics in general. In this chapter, the binary number system and its relationship to other
number systems such as decimal, hexadecimal, and octal is presented. Arithmetic operations
with binary numbers are covered to provide a basis for understanding how computers and many
other types of digital systems work. Also, digital codes such as binary coded decimal (BCD), the
Gray code, and the ASCII are covered.
Decimal Numbers
You are familiar with the decimal number system because you use decimal numbers every day.
Although decimal numbers are commonplace, their weighted structure is often not understood.
In the decimal number system each of the ten digits, 0 through 9 represents a certain quantity. As
you know, the ten symbols (digits) do not limit you to expressing only ten different quantities
because you use the various digits in appropriate positions within a number to indicate the
magnitude of the quantity.
For example, you wish to express the quantity twenty-three, you use (by their respective
positions in the number) the digit 2 to represent the quantity twenty and the digit 3 to represent
the quantity three.
Binary Numbers
The binary number system has two digits (bits). The binary number system has a base of 2. The
binary number system is another way to represent quantities. It is less complicated than the
decimal system because it has only two digits. The decimal system with its ten digits is a base
ten system; the binary system with its two digits is a base-two system. The two binary digits
(bits) are 1 and 0. The position of a 1 or 0 in a binary number indicates its weight or value within
the number, just as the position of a decimal digit determines the value of that digit. The weights
in a binary number are based on powers of two.
Counting in Binary
To learn to count in the binary system, first look at how you count in the decimal system. You
start at zero and count up to nine before you run out of digits. You then start another digit
position (to the left) and continue counting 10 through 99. At this point you have exhausted all
two digit combinations. So a third digit position is needed to count from 100 through 999. The
same is to count in binary system.
Decimal
Number Binary Number
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 1 0 1 0
11 1 0 1 1
12 1 1 0 0
13 1 1 0 1
14 1 1 1 0
15 1 1 1 1
An Application
Learning to count in binary will help you to basically understand how digital circuits can be used
to count events. This can be anything from counting items on an assembly line to counting
operations in a computer. Let's take a simple example of counting tennis balls going into a box
from a conveyor belt. Assume that nine balls are to go into each box.
The counter in Figure 5.7 counts the pulses from a sensor that detects the passing of a ball and
produces a sequence of logic levels (digital wavefom1s) on each of its four parallel outputs. Each
set of logic levels represents a 4-bit binary number (HIGH = 1 and LOW = 0), as indicated. As
the decoder receives these waveforms, it decodes each set of four bits and converts it to the
corresponding decimal number in the 7-segment display. When the counter gets to the binary
state of 1001, it has counted nine tennis balls, the display shows decimal 9, and a new box is
moved under the conveyor. Then the counter goes back to its zero state (0000), and the process
starts over.
Figure 5.7 Illustration of a simple binary counting application
Hexadecimal Numbers
The hexadecimal number system has sixteen characters; it is used primarily as a compact way of
displaying or writing binary numbers because it is very easy to convert between binary and
hexadecimal. As you are probably aware, long binary numbers are difficult to read and write
because it is easy to drop or transpose a bit. Since computers and microprocessors understand
only 1s and 0s, it is necessary to use these digits when you program in "machine language."
Imagine writing a sixteen bit instruction for a microprocessor system in 1s and 0s.
Decimal Binary Hexadecimal
Number Number Number
0 0000 0
1 0001 1
2 0010 2
3 0011 3
4 0100 4
5 0101 5
6 0110 6
7 0111 7
8 1000 8
9 1001 9
10 1010 A
11 1011 B
12 1100 C
13 1101 D
14 1110 E
15 1111 F
ASCII
ASCII is the abbreviation for American Standard Code for Information Interchange. Pronounced
"askee," ASCII is a universally accepted alphanumeric code used in most computers and other
electronic equipment. Most computer keyboards are standardized with the ASCII. When you
enter a letter, a number, or control command, the corresponding ASCII code goes into the
computer.
Basic Logic Gates
There are three basic logic gates each of which performs a basic logic function, they are called
NOT, AND and OR. All other logic functions can ultimately be derived from combinations of
these three. For each of the three basic logic gates a summary is given including the logic
symbol, the corresponding truth table and the Boolean expression.
The NOT gate
The NOT gate is unique in that it only has one input. It looks like
The input to the NOT gate is inverted i.e the binary input state of 0 gives an output of 1 and
the binary input state of 1 gives an output of 0.
is known as "NOT A" or alternatively as the complement of .

The truth table for the NOT gate appears as below
0 1
1 0
The AND gate
The AND gate has two or more inputs. The output from the AND gate is 1 if and only if all of
the inputs are 1, otherwise the output from the gate is 0. The AND gate is drawn as follows
The output from the AND gate is written as (the dot can be written half way up the line as
here or on the line. Note that some textbooks omit the dot completely).
The truth table for a two-input AND gate looks like
0 0 0
0 1 0
1 0 0
1 1 1
It is also possible to represent an AND gate with a simple analogue circuit, this is illustrated as
an animation.
The OR Gate
The OR gate has two or more inputs. The output from the OR gate is 1 if any of the inputs is 1.
The gate output is 0 if and only if all inputs are 0. The OR gate is drawn as follows
The output from the OR gate is written as . The truth table for a two-input OR gate
looks like
0 0 0
0 1 1
1 0 1
1 1 1
Other Logic Gates
The three basic logic gates can be combined to provide more complex logical functions. Four
important logical functions are described here, namely NAND, NOR, XOR and XNOR. In each
case a summary is given including the logic symbol for that function, the corresponding truth
table and the Boolean expression.
The NAND gate
The NAND gate has two or more inputs. The output from the NAND gate is 0 if and only if all
of the inputs are 1 otherwise the output is 1. Therefore the output from the NAND gate is the
NOT of A AND B (also known as the complement or inversion of . ). The NAND gate is
drawn as follows
Where: the small circle immediately to the right of the gate on the output line is known as an
invert bubble.
The output from the NAND gate is written as (the same rules apply regarding the
placement and appearance of the dot as for the AND gate - see the section on basic logic gates).
The Boolean expression reads as "A NAND B". The truth table for a two-input NAND
gate looks like
0 0 1
0 1 1
1 0 1
1 1 0
The NOR gate
The NOR gate has two or more inputs. The output from the NOR gate is 1 if and only if all
of the inputs are 0, otherwise the output is 0. This output behavior is the NOT of A OR B.
The NOR gate is drawn as follows
The output from the NOR gate is written as which reads "A NOR B". The truth table for
a two-input NOR gate looks like
0 0 1
0 1 0
1 0 0
1 1 0
THE EXCLUSIVE - OR (XOR) gate
The exclusive-OR or XOR gate has two or more inputs. For a two-input XOR the output is
similar to that from the OR gate except it is 0 when both inputs are 1. This cannot be extended to
XOR gates comprising 3 or more inputs however.
In general, an XOR gate gives an output value of 1 when there are an odd number of 1's on the
inputs to the gate. The truth table for a 3-input XOR gate below illustrates this point. The XOR
gate is drawn as
The output from the XOR gate is written as which reads "A XOR B". The truth table for
a two-input XOR gate looks like
0 0 0
0 1 1
1 0 1
1 1 0
For a 3-input XOR gate with inputs , and the truth table is given by
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 1
THE EXCLUSIVE-NOR (XNOR) gate
The exclusive-NOR or XNOR gate has two or more inputs. The output is equivalent to inverting the
output from the exclusive-OR gate described above. Therefore an equivalent circuit would comprise an
XOR gate, the output of which feeds into the input of a NOT gate.
In general, an XNOR gate gives an output value of 1 when there are an even number of 1's on
the inputs to the gate. The truth table for a 3-input XNOR gate below illustrates this point.
The XNOR gate is drawn using the same symbol as the XOR gate with an invert bubble on the
output line as is illustrated below
The output from the XNOR gate is written as which reads "A XNOR B". The truth table
for a two-input XNOR gate looks like
0 0 1
0 1 0
1 0 0
1 1 1
For a 3-input XNOR gate with inputs , and the truth table is given by
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
Logic Families
There are several different families of logic gates. Each family has its capabilities and
limitations, its advantages and disadvantages. The following list describes the main logic
families and their characteristics.
Diode Logic (DL)

Diode logic gates use diodes to perform AND and OR logic functions. Diodes have the property
of easily passing an electrical current in one direction, but not the other. Thus, diodes can act as a
logical switch.
Diode logic gates are very simple and inexpensive, and can be used effectively in specific
situations. However, they cannot be used extensively, as they tend to degrade digital signals
rapidly. In addition, they cannot perform a NOT function, so their usefulness is quite limited.
Diode OR Circuit
The above figure shows two diodes D1 & D2 with a resistor load. The table shows the voltage
truth table for the circuit.
With both inputs at 0V, the output is at 0V.
With either diode input at +5V, the respective diode will be forward biased and current will flow
through the diode and the load resistor. For silicon junction diodes, the output voltage will be
approximately 0.7V less than the input voltage, due to the voltage drop across the forward biased
diode.
With both inputs at +5V, the output will still be 0.7V less than the supply value (that is, 4.3V).
Note: If the input voltages for the two inputs are different, then the output voltages will depend
on the inputs. Table below shows the voltage truth table for inputs of +3V & +5V.
Converting the voltage levels of the above truth table to logic levels 0 & 1 and using positive
logic gives the truth table shown below
From the above table it can be seen that the output is at logic 1 if input A OR B OR both inputs
are at logic 1. The circuit therefore performs the OR function.
Circuits having inputs and an output, the output depending on the logic states of the inputs, are
referred to as gates. A circuit with the OR characteristic is referred to as an OR gate.
Such a gate with two inputs would be referred to as a 2-input OR gate, one with three inputs a 3-
input OR gate, etc.
Diode AND Circuit
The above figure shows two diodes D1 & D2 and resistor R1 forming an AND circuit. The table
shows the voltage truth table for the circuit.
With both inputs at 0V, the diodes will be forward biased and the output will be 0.7V, this being
the voltage drops across a forward biased silicon junction diode.
With either diode input at 0V, the respective diode will be forward biased and the output voltage
will again be approximately 0.7V.
With both inputs at +5V, both diodes will be reverse biased and the output voltage will be the
supply value (that is, +5V) provided there is no load resistor connected to the output circuit.
With a load resistor RL connected to the output circuit the output voltage will be reduced to the
value 5 x RL/ (R1 + RL). This is illustrated in the figure below
Converting the voltage levels of the previous table to logic levels 0 & 1 and using positive logic
gives the truth table shown below
From the above table it can be seen that the output is at logic 1 only if inputs A AND B are at
logic 1. The circuit therefore performs the AND function.
Such a circuit with two inputs would be referred to as a 2-input AND gate, one with three inputs
a 3-input AND gate, etc.
Resistor-Transistor Logic (RTL)
Resistor-transistor logic gates use Transistors to combine multiple input signals, which also
amplify and invert the resulting combined signal. Often an additional transistor is included to re
invert the output signal. This combination provides clean output signals and either inversion or
non-inversion as needed.
RTL gates are almost as simple as DL gates, and remain inexpensive. They also are handy
because both normal and inverted signals are often available. However, they do draw a
significant amount of current from the power supply for each gate. Another limitation is that
RTL gates cannot switch at the high speeds used by today's computers, although they are still
useful in slower applications.
Although they are not designed for linear operation, RTL integrated circuits are sometimes used
as inexpensive small-signal amplifiers, or as interface devices between linear and digital circuits.
Diode-Transistor Logic (DTL)
By letting diodes perform the logical AND or OR function and then amplifying the result with a
transistor, we can avoid some of the limitations of RTL. DTL takes diode logic gates and adds a
transistor to the output, in order to provide logic inversion and to restore the signal to full logic
levels.
Transistor Application as a Switch
The above figure shows an NPN transistor circuit with base feed resistor R1 and collector load
resistor R2. The table shows the voltage and positive logic truth tables for the circuit.
With the input at 0V, there will be no base current and hence the transistor will be turned OFF.
There will be no collector current, so the output voltage from the collector will be the supply
value (+5V), provided there is no load resistance connected to the output.
With the input at +5V, there will be a current flow in the base-emitter circuit and the transistor
will be turned ON. The value of R1 is arranged to allow sufficient collector current to flow for
the collector voltage to fall to approximately zero. Under this condition the transistor is said to be
saturated.
Example
With a collector load resistor of 1kΩ and a supply voltage of +5V, the collector current required
to saturate the transistor will be:
With a transistor current gain of 20, the minimum base current required is:
There will be 0.7V drop across the transistor base - emitter junction and 4.3V across R1 (5V -
0.7V = 4.3V).
The maximum value of R1 to allow 0.25mA current to flow is:
Normally a lower value for R1 would be used to ensure that the transistor saturates.
From the truth tables it can be seen that the output logic level is the inverse of the input logic
level. The circuit acts as an inverter and is referred to as a NOT gate.
Diode Transistor NOR Gate
The above figure shows a 2-input diode-transistor circuit and the table shows the voltage and
logic truth tables for the circuit.
With both inputs at 0V, the transistor will be turned OFF and the output voltage will be at +5V.
With either or both inputs at +5V, the transistor will be saturated and the output will be at 0V.
The output states are the inverse of those for an OR gate. That is, it is a NOT OR gate and is
referred to as a NOR gate.
Diode-Transistor NAND Gate
The above figure shows a 2-input diode-transistor circuit and the table shows the voltage and
logic truth tables for the circuit.
With either or both inputs at 0V, the junction of R1 & R3 will be held at 0.7V, due to the voltage
drop across the forward biased diode. The transistor will be turned OFF and hence the output
voltage will be at +5V.
With both inputs at +5V, the transistor base - emitter circuit will be fed via R3 & R1, the
transistor will be saturated and the output will be at 0V.
The output states are the inverse of those for an AND gate. That is, it is a NOT AND gate and is
referred to as a NAND gate.
In practice, to ensure that the transistor base voltage is less than 0.7V with either input at 0V, the
resistor R1 is normally replaced with a diode as shown below
Effect of Logic Convention on Gate Characteristics
The above tables show the voltage truth table characteristics of a gate and also the logic truth
tables for positive and negative logic conventions.
For positive logic the gate has an output of logic 1 only with both inputs at logic 1 and therefore
represents an AND gate.
For negative logic convention, the gate has an output of logic 1 when either or both inputs are at
logic 1 and therefore represents an OR gate.
The above tables show the voltage truth table for a gate and its corresponding positive and
negative logic truth tables. The gate represents an OR gate for positive logic and an AND gate
for negative logic.
Transistor – Transistor Logic (TTL)
The physical construction of integrated circuits made it more effective to replace all the input
diodes in a DTL gate with a transistor, built with multiple emitters. The result is transistor-
transistor logic, which became the standard logic circuit in most applications for a number of
years.
As the state of the art improved, TTL integrated circuits were adapted slightly to handle a wider
range of requirements, but their basic functions remained the same. These devices comprise the
7400 family of digital ICs.
These are basically gate circuits consisting of several transistors, resistors and diodes that have
been formed on a small piece of silicon and enclosed in a plastic package.
Normally, more than one gate will be formed on the same piece of silicon and enclosed in the
same package with the supply and the input and output connections for each gate brought out to
external connecting pins. The complete unit is referred to as an integrated circuit (IC).
These circuits are much smaller, require the minimum of connections, and are faster and more
reliable than equivalent circuits constructed from separate components.
The usual package form is rectangular with the connecting pins aligned along the two longer
sides and is referred to as a DUAL-IN-LINE (DIL) package. For gate circuits, packages with
either 14 or 16 connecting pins are used and they are therefore referred to as 14-pin DIL or 16-
pin DIL packages.
The following figure illustrates the DIL packaging and the pin numbering system, pin 1 being
indicated by a circular indent at the end containing a notch.
TTL Logic Gates and Voltage Levels
There are a series of TTL integrated circuits (IC's), the identification numbers starting with the
numerals 74 and they are therefore referred to as the 74 series.
e.g.
7400 Quad 2-input NAND gate (Four 2-input NAND gates in the IC)
7402 Quad 2-input NOR gate (Four 2-input NOR gates in the IC)
7408 Quad 2-input AND gate (Four 2-input AND gates in the IC)
7432 Quad 2-input OR gate (Four 2-input OR gates in the IC)
7404 Hex Inverter (Six Inverter or NOT gates in the IC)
The following shows the gate pin-out connections for these IC's.
This series of logic gates use positive logic, a supply voltage of +5V and specified values for the
voltages corresponding to the logic levels 0 & 1 and for the other characteristics of logic gates.
There are several variations on the standard 74 series of TTL devices:
STTL Schottky TTL
LSTTL Low power Schottky TTL
ALSTTL Advanced Low Power Schottky TTL
FAST High speed Low Power TTL
These have slight differences in respect of some of the characteristics compared with the
standard TTL and will be considered in a further course on the topic.
The voltage values specified for the two logic levels are common for all TTL series devices and
are as follows:
Inputs: Logic 0: < 0.8V
Logic 1: > 2.0V
Outputs: Logic 0: <0.4V
Logic 1: >2.4V
These values represent the voltages that are recognized accurately as being at the respective level
0 or 1 at the input to or the output from a device. Intermediate voltages 0.8V - 2.0V at the input
or 0.4V - 2.4V at the output may be inaccurately identified.
The input voltage value at which a change in the output state is triggered is referred to as the
THRESHOLD LEVEL. For the TTL family, this value is around 1.4V.
The above figure shows the typical TTL NAND gate input/output transfer characteristic and
indicates the voltage areas outside the stated specification for these devices. With the input
voltage low, the output is high and exceeds 2.4V. At the threshold voltage, between 0.8V & 2V,
the output state changes to its low level, this being less than 0.4V.
For input falling voltage change from high value to zero, the characteristic is basically the same
as for rising voltages.
Emitter-Coupled Logic (ECL)
Also known as Current Mode Logic (CML), ECL gates are specifically designed to operate at
extremely high speeds, by avoiding the "lag" inherent when transistors are allowed to become
saturated. Because of this, however, these gates demand substantial amounts of electrical current
to operate correctly.
CMOS (Complementary Metal Oxide Semiconductor) Logic
One factor is common to all of the logic families we have listed above: they use significant
amounts of electrical power. Many applications, especially portable, battery-powered ones,
require that the use of power be absolutely minimized. To accomplish this, the CMOS
(Complementary Metal-Oxide-Semiconductor) logic family was developed. This family uses
enhancement-mode MOSFETs as its transistors, and is so designed that it requires almost no
current to operate.
CMOS gates are, however, severely limited in their speed of operation. Nevertheless, they are
highly useful and effective in a wide range of battery-powered applications.
Most logic families share a common characteristic: their inputs require a certain amount of
current in order to operate correctly. CMOS gates work a bit differently, but still represent a
capacitance that must be charged or discharged when the input changes state. The current
required to drive any input must come from the output supplying the logic signal. Therefore, we
need to know how much current an input requires, and how much current an output can reliably
supply, in order to determine how many inputs may be connected to a single output.
CMOS gates consist of field effect transistor circuits, these being formed on a piece of silicon
and enclosed in a 14-pin or 16-pin DIL plastic package as for TTL devices. Combinations of P-
channel (PMOS) and N-channel (NMOS) transistors are used and hence the name
Complementary MOS (CMOS).
CMOS gates are voltage operated devices (TTL being current operated) and, due to the use of
complementary MOS transistors, their power supply consumption is very low.
Typical power consumption: CMOS = 10nW and TTL = 10mW

Thus, TTL devices consume of the order of 1000 times more power.
Due to their voltage operation, the current capability of the output circuit of CMOS gates is less
than that for TTL gates in respect of both delivering current ("sourcing") and receiving current
("sinking").
The figure below illustrates the direction of current flow in the output circuit of a gate when
"sourcing" and "sinking" current.
Although the current required by a CMOS input is much lower than that for a TTL input, the
capacitance of CMOS devices is higher than for TTL devices. Hence their speed of operation is
less than that for TTL gates.
CMOS Logic Gates ICs
In the standard series of CMOS integrated circuits, the identification numbers of all ICs start
with the numeral 4 and normally having 4 digits. They are therefore referred to as the 4000
series, for example:
4001 Quad 2-input NOR gate (Four 2-input NOR gates in the IC)
4002 Dual 4-input NOR gate (Two 4-input NOR gates in the IC)
4011 Quad 2-input NAND gate (Four 2-input NAND gates in the IC)
4071 Quad 2-input OR gate (Four 2-input OR gates in the IC)
4049 Hex inverter (Six Inverter or NOT gates in the IC)
This series of logic gates uses positive logic, and can operate on a supply voltage within the
range 3V to 15V.
CMOS Voltage Levels
The voltage levels specified for the two logic levels are common to all 4000 series CMOS
devices. For a +5V supply, these voltages are as follows:
Inputs: Logic 0: 1.5V max
Logic 1: 3.5V min
Outputs: Logic 0: 0.05V max
Logic 1: 4.95V min
The input values represent the voltages that will be recognized accurately as being at the
respective level (0 or 1) at the input to a CMOS device. Intermediate voltages between 1.5V and
3.5V may be inaccurately identified.
The output values represent the level 0 and level 1 voltages that will be present at the output of a
CMOS 4000 series device that is operating within its normal specification.
The input threshold voltage for a CMOS 4000 series gate is typically around half of the supply
voltage, or 2.5V for a gate powered from a +5V supply.
CMOS Noise Margin
Consider the situation where the output of one CMOS 4000 series gate drives the input of
another. If the driving gate is operating within its specification and the supply voltage is +5V,
then:
Logic 1 output will exceed the minimum required logic 1 input voltage by at least 1.45V (4.95V
- 3.5V).
A logic 0 output will be below the maximum allowable logic 0 input voltage by at least 1.45V
(1.5V - 0.05V).
The noise margin of 4000 series CMOS is therefore at least 1.45V in either state, as shown
below
This means that the amount of electrical noise at the output of the driving gate would have to
exceed 1.45V in amplitude, before there would be any risk of a driven gate misinterpreting the
logic level at its input.
So the noise margin of standard CMOS running from a +5V supply is more than three times that
for standard TTL (0.4V).
This relatively high noise immunity makes the use of CMOS gates preferable in conditions
where a large amount of electrical noise is present.
CMOS Fan-Out
Because CMOS gates are voltage operated devices, a CMOS input requires very little current
(0.3µA maximum). This makes the fan-out of CMOS logic extremely high. In fact, more than 50
CMOS inputs can, theoretically, be driven from a single CMOS output.
However, in practical logic circuits where operating speed is important, the high input
capacitance of CMOS gates is a more limiting factor than the fan-out. The more inputs that are
connected to a single output, the longer will be the time taken for the gate output to change state
when one of its own inputs changes. If this propagation delay time becomes too long, the circuit
may no longer operate correctly.
Interfacing TTL and CMOS Gates
It is sometimes possible to interface directly between TTL and CMOS gates, but the limitations
of each logic family have to be taken into account when doing so.
For instance, a standard TTL gate may drive a CMOS gate if the logic 1 output voltage from the
TTL gate is increased. This can be achieved by using a pull-up resistor, as shown below
However, the circuit will only operate correctly if the operating speed is low enough to allow for
the propagation delay through the CMOS gate, and through any others that follow it.
A 4000 series CMOS gate cannot provide enough output current to drive a standard TTL input.
However, there are variations of the CMOS range that can be directly connected to TTL.
CMOS Gate Variations
Two important variations on the standard 4000 series of CMOS devices have been introduced.
These are:
74HC High speed CMOS devices with CMOS-compatible inputs and TTL/CMOS compatible
outputs
74HCT High speed CMOS devices with TTL-compatible inputs and TTL/CMOS compatible
outputs
These overcome the speed limitations of 4000 series CMOS. The 74HCT series is ideal for
interfacing with TTL outputs, while the 74HC series provides the high noise immunity that is a
characteristic of CMOS 4000 series gates.
Open Collector Gates

Some TTL ICs have no internal collector load resistor provided for the output transistor of the
gates. A separate external load resistor is required as shown below. These gates are referred to as
open collector gates.
This arrangement enables more than one gate to feed a single output, this output being a logical
function of the inputs.
The figure below shows two open collector buffers with a common output, with the truth table.
With either input at logic level 0, and hence the corresponding buffer output at level 0, the
combined output is at level 0. The combined output is at logic level 1 only with both inputs at
level 1. The circuit performs the AND function and is referred to as the wired-AND function.
The figure below shows two open collector Inverter gates with a common output with the truth
table.
With either input at logic level 1, and hence the corresponding inverter output at level 0, the
combined output is at logic level 0. The combined output is at logic level 1 only with both inputs
at level 0 - that is, when both inverter outputs are at level 1. The circuit performs the NOR
function and is referred to as the wired-NOR function.
Multiple input TTL gates are also available with open collector outputs. These are suitable for
similarly connected circuits. The circuits will give an output at logic level 1 only with all the
connected gate outputs at logic level 1.
Direct connection of the outputs of TTL gates having integral internal collector resistors for the
output stages will not result in a logical output being obtained. The gates will take an excessive
current from the supply, dependent on the input settings, but this will not normally damage the
gates due to the limiting effect of the internal resistor.
The outputs of CMOS gates should never be connected together directly.
Standard Load
The amount of current required to drive one standard input, is known as a standard load on any
output.
Buffers
Are circuits designed to be able to drive more inputs than usual input current, and some gates,
known as buffers.
Fan-in
Fan-in is a term that defines the maximum number of digital inputs that a single logic gate can
accept. Most transistor-transistor logic (TTL) gates have one or two inputs, although some have
more than two. A typical logic gate has a fan-in of 1 or 2.
Fan-out
Fan-out is a term that defines the maximum number of digital inputs that the output of a single
logic gate can feed. Most transistor-transistor logic (TTL) gates can feed up to 10 other digital
gates or devices. Thus, a typical TTL gate has a fan-out of 10.

Applied II Note

Uploaded by

Copyright:

Available Formats

Applied II Note

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Applied II Note

Uploaded by

Copyright:

Available Formats

A.

A Science and Technology University School of Electrical Engineering and Computing

(i) Positive feedback

(ii) Negative feedback

Principle of Feedback Amplifiers

is called positive feedback

is called negative feedback

(a) Negative Feedback

Obviously, A´ < A because | 1 + βA | > 1.

(b) Positive Feedback

Advantages of Negative Feedback

(b) The feedback network is being driven by the output voltage of 10 V.

The new increased input voltage is given by

Taking logs of both sides, we have loge A´ = loge A – loge (1 + βA)

If βA » 1, then the above expression becomes

Feedback over Several Stages

Differentiating the above two expressions, we get

(ii) When open-loop gain changes by 10%, then A2 = 50 + 0.1 × 50 = 55

Percentage change in closed-loop gain is

Now, dB gain = 20 log10 A

(a) Af = A/(1 + βA) = 63/(1 + 6.3) = 6.63 or 18.72 dB

f2 ´ = f0 (1 + βA) = 20(1 + 0.02 × 200) = 100 Hz

Forms of Negative Feedback

(a) Voltage-series Feedback

Characteristics Type of Feedback

Shunt-derived Series-fed Voltage Feedback

Current-series Feedback Amplifier

It can be proved that

Voltage-shunt Negative Feedback Amplifier

Current-shunt Negative Feedback Amplifier

The four differential amplifier configurations are following:

Dual Input, Balanced Output Differential Amplifier

Applying KVL to the base emitter loop of the transistor Q1

Generally, because is the internal resistance of input signal.

The voltage VCEQ can be obtained from equation (Eqn 2).

Dual Input, Balanced Output Difference Amplifier

Applying KVL in two loops 1 & 2

Substituting current relations,

Solving these two equations, ie1 and ie2 can be calculated.

The output voltage VO is given by

Differential Input Resistance:

The factor of 2 arises because re' of each transistor is in series.

The ac emitter resistance

Therefore, substituting the known values in voltage gain equation, we obtain

Inverting & Non - inverting Inputs

Common mode Gain and common Mode rejection ratio

Substituting in output voltage equation

Date sheet always specify CMRR in decibels CMRR = 20 log CMRR.

Dual Input, Unbalanced Output Differential Amplifier:

Differential amplifier with swamping resistors

From the equation, can be obtained as

The new voltage gain is given by

The input resistance is given by

The output resistance with or without is the same i.e.

Thus, ICQ = 0.988 mA

Constant Current Bias

is the diode voltage. Thus,

If are so chosen that

The voltage at the base of transistor QB is

Where I2 = 1.2 IZ (min)