Product Order Technical Tools & Support &

Folder Now Documents Software Community

SN74LVC2GU04-Q1
SCES902 – AUGUST 2019

SN74LVC2GU04-Q1 Dual Unbuffered Inverter

1 Features 2 Applications
1• AEC-Q100 Qualified for Automotive Applications: • AV Receivers
– Device Temperature Grade 1: –40°C to • Blu-ray Players and Home Theaters
+125°C, TA • DVD Recorders and Players
• Supports 5-V VCC Operation • Desktop or Notebook PCs
• Inputs Accept Voltages to 5.5 V • Digital Radio or Internet Radio Players
• Max tpd of 3.7 ns at 3.3 V • Digital Video Cameras (DVC)
• Low Power Consumption, 10-µA Max ICC • Embedded PCs
• ±24-mA Output Drive at 3.3 V • GPS: Personal Navigation Devices
• Typical VOLP (Output Ground Bounce) • Mobile Internet Devices
<0.8 V at VCC = 3.3 V, TA = 25°C • Network Projector Front-Ends
• Typical VOHV (Output VOH Undershoot) • Portable Media Players
>2 V at VCC = 3.3 V, TA = 25°C
• Pro Audio Mixers
• Can Be Used as a Down Translator to Translate
• Smoke Detectors
Inputs From a Max of 5.5 V Down
to the VCC Level • Solid-State Drive (SSD): Enterprise
• Unbuffered Outputs • High-Definition (HDTV)
• Tablets: Enterprise
• Audio Docks: Portable
• DLP Front Projection Systems
• DVR and DVS
• Digital Picture Frame (DPF)
• Digital Still Cameras

3 Description
This dual inverter is designed for 1.65-V to 5.5-V VCC
operation.
The SN74LVC2GU04-Q1 device contains two
inverters with unbuffered outputs and performs the
Boolean function Y = A.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE
SN74LVC2GU04QDRYRQ1 SON (6) 1.45 mm × 1.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Logic Diagram (Positive Logic)

1 6
1A 1Y

3 4
2A 2Y

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74LVC2GU04-Q1
SCES902 – AUGUST 2019 www.ti.com

Table of Contents
1 Features .................................................................. 1 8.2 Functional Block Diagram ......................................... 8
2 Applications ........................................................... 1 8.3 Feature Description................................................... 8
3 Description ............................................................. 1 8.4 Device Functional Modes.......................................... 9
4 Revision History..................................................... 2 9 Application and Implementation ........................ 10
9.1 Application Information............................................ 10
5 Pin Configuration and Functions ......................... 3
9.2 Typical Application ................................................. 10
6 Specifications......................................................... 3
6.1 Absolute Maximum Ratings ..................................... 3 10 Power Supply Recommendations ..................... 11
6.2 ESD Ratings.............................................................. 3 11 Layout................................................................... 12
6.3 Recommended Operating Conditions ...................... 4 11.1 Layout Guidelines ................................................. 12
6.4 Thermal Information .................................................. 4 11.2 Layout Example .................................................... 12
6.5 Electrical Characteristics........................................... 5 12 Device and Documentation Support ................. 13
6.6 Switching Characteristics .......................................... 6 12.1 Documentation Support ....................................... 13
6.7 Switching Characteristics .......................................... 6 12.2 Receiving Notification of Documentation Updates 13
6.8 Operating Characteristics.......................................... 6 12.3 Community Resources.......................................... 13
6.9 Typical Characteristic................................................ 6 12.4 Trademarks ........................................................... 13
7 Parameter Measurement Information .................. 7 12.5 Electrostatic Discharge Caution ............................ 13
12.6 Glossary ................................................................ 13
8 Detailed Description .............................................. 8
8.1 Overview ................................................................... 8 13 Mechanical, Packaging, and Orderable
Information ........................................................... 13

4 Revision History
DATE REVISION NOTES
August 2019 * Initial release.

2 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: SN74LVC2GU04-Q1

 SN74LVC2GU04-Q1
www.ti.com SCES902 – AUGUST 2019

5 Pin Configuration and Functions

DRY Package
6-Pin SON
Top View

1A 1 6 1Y

GND 2 5 VCC

2A 3 4 2Y

Pin Functions
PIN
I/O DESCRIPTION
NAME DRY Package (1)
1A 1 I Input
1Y 6 O Output
2A 3 I Input
2Y 4 O Output
VCC 5 — Positive Supply
GND 2 — Ground

(1) See Package drawing at the end of the data sheet for dimensions

6 Specifications
6.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range –0.5 6.5 V
VI Input voltage range (2) –0.5 6.5 V
(2) (3)
VO Voltage range applied to any output in the high or low state –0.5 VCC + 0.5 V
IIK Input clamp current VI < 0 –50 mA
IOK Output clamp current VO < 0 –50 mA
IO Continuous output current ±50 mA
Continuous current through VCC or GND ±100 mA
TA Operating free-air temperature –40 125 °C
Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.

6.2 ESD Ratings

MAX UNIT
Human-body model (HBM), per AEC Q100-002 (1)
±2000
HBM ESD Classification Level
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per AEC Q100-011
±1000
CDM ESD Classification Level

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 3

Product Folder Links: SN74LVC2GU04-Q1
SN74LVC2GU04-Q1
SCES902 – AUGUST 2019 www.ti.com

6.3 Recommended Operating Conditions (1)

MIN MAX UNIT
VCC Supply voltage 1.65 5.5 V
VIH High-level input voltage IO = –100 µA 0.75 × VCC V
VIL Low-level input voltage IO = 100 µA 0.25 × VCC V
VI Input voltage 0 5.5 V
VO Output voltage 0 VCC V
VCC = 1.65 V –4
VCC = 2.3 V –8
IOH High-level output current –16 mA
VCC = 3 V
–24
VCC = 4.5 V –32
VCC = 1.65 V 4
VCC = 2.3 V 8
IOL Low-level output current 16 mA
VCC = 3 V
24
VCC = 4.5 V 32

(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.4 Thermal Information

DRY
THERMAL METRIC (1) UNIT
(6 PINS)
RθJA Junction-to-ambient thermal resistance 233.4 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 144.6 °C/W
RθJB Junction-to-board thermal resistance 119.9 °C/W
ψJT Junction-to-top characterization parameter 15.8 °C/W
ψJB Junction-to-board characterization parameter 119.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermal metrics application
report.

4 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: SN74LVC2GU04-Q1

 SN74LVC2GU04-Q1
www.ti.com SCES902 – AUGUST 2019

6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
–40°C to 85°C –40°C to 125°C
PARAMETER TEST CONDITIONS VCC UNIT
MIN TYP (1) MAX MIN TYP (1) MAX
IOH = –100 µA 1.65 V to 5.5 V VCC – 0.1 VCC – 0.1
IOH = –4 mA 1.65 V 1.2 1.2
IOH = –8 mA 2.3 V 1.9 1.9
VOH VIL = 0 V V
IOH = –16 mA 2.4 2.4
3V
IOH = –24 mA 2.3 2.3
IOH = –32 mA 4.5 V 3.8 3.8
IOL = 100 µA 1.65 V to 5.5 V 0.1 0.1
IOL = 4 mA 1.65 V 0.45 0.45
IOL = 8 mA 2.3 V 0.3 0.3
VOL VIH = VCC V
IOL = 16 mA 0.4 0.4
3V
IOL = 24 mA 0.55 0.55
IOL = 32 mA 4.5 V 0.55 0.55
II A inputs VI = 5.5 V or GND 0 to 5.5 V ±5 ±5 µA
ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 10 µA
CI VI = VCC or GND 3.3 V 7 pF

(1) All typical values are at VCC = 3.3 V, TA = 25°C.

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 5

Product Folder Links: SN74LVC2GU04-Q1
SN74LVC2GU04-Q1
SCES902 – AUGUST 2019 www.ti.com

6.6 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see )
–40°C to 85°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 1.2 5.5 1 4 1.1 3.7 1 3 ns

6.7 Switching Characteristics

over recommended operating free-air temperature range (unless otherwise noted) (see )
–40°C to 125°C
FROM TO VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER UNIT
(INPUT) (OUTPUT) ± 0.15 V ± 0.2 V ± 0.3 V ± 0.5 V
MIN MAX MIN MAX MIN MAX MIN MAX
tpd A Y 1.2 6.3 1 4.5 1.1 4.2 1 3.5 ns

6.8 Operating Characteristics

TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V
PARAMETER TEST CONDITIONS UNIT
TYP TYP TYP TYP
Cpd Power dissipation capacitance f = 10 MHz 7 7 8 23 pF

6.9 Typical Characteristic

5

tpd(MAX)
4

3
tpd(ns)

tpd(MIN)
1

0
1 2 3 4 5 6
VCC (V)
Figure 1. tpd vs VCC

6 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: SN74LVC2GU04-Q1

 SN74LVC2GU04-Q1
www.ti.com SCES902 – AUGUST 2019

7 Parameter Measurement Information

VLOAD
RL S1 Open
From Output TEST S1
Under Test GND
tPLH/tPHL Open
CL
(see Note A) RL tPLZ/tPZL VLOAD
tPHZ/tPZH GND

LOAD CIRCUIT

INPUTS
VCC VM VLOAD CL RL VD
VI tr/tf
1.8 V ± 0.15 V VCC £2 ns VCC/2 2 × VCC 30 pF 1 kW 0.15 V
2.5 V ± 0.2 V VCC £2 ns VCC/2 2 × VCC 30 pF 500 W 0.15 V
3.3 V ± 0.3 V 3V £2.5 ns 1.5 V 6V 50 pF 500 W 0.3 V
5 V ± 0.5 V VCC £2.5 ns VCC/2 2 × VCC 50 pF 500 W 0.3 V

VI
Timing Input VM
0V
tW

VI tsu th
VI
Input VM VM Data Input VM VM
0V 0V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PULSE DURATION SETUP AND HOLD TIMES

VI VI
VM VM Output
Input VM VM
Control
0V 0V
tPLH tPHL tPZL tPLZ
VOH Output VLOAD/2
VM VM Waveform 1
Output VM
S1 at VLOAD VOL + VD
VOL VOL
(see Note B)
tPHL tPLH tPZH tPHZ
VOH Output VOH
Waveform 2 VOH – VD
Output VM VM VM
VOL S1 at GND
(see Note B) »0 V
VOLTAGE WAVEFORMS VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES ENABLE AND DISABLE TIMES
INVERTING AND NONINVERTING OUTPUTS LOW- AND HIGH-LEVEL ENABLING

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.

Figure 2. Load Circuit and Voltage Waveforms

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 7

Product Folder Links: SN74LVC2GU04-Q1
SN74LVC2GU04-Q1
SCES902 – AUGUST 2019 www.ti.com

8 Detailed Description

8.1 Overview
The SN74LVC1GU04-Q1 device contains two inverters with unbuffered outputs with a maximum sink current of
32 mA.

8.2 Functional Block Diagram

Logic Diagram (Positive Logic)

1 6
1A 1Y

3 4
2A 2Y

8.3 Feature Description

8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The high-drive capability of this device
creates fast edges into light loads, so routing and load conditions must be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be
followed at all times.

8.3.2 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst-case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using Ohm's law (R = V ÷ I).
Signals that are applied to the inputs need to have fast edge rates, as shown by Δt/Δv in the Recommended
Operating Conditions, to avoid excessive current consumption and oscillations. If a slow or noisy input signal is
required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard
CMOS input.

8.3.3 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as shown in Figure 3.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.

8 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: SN74LVC2GU04-Q1

 SN74LVC2GU04-Q1
www.ti.com SCES902 – AUGUST 2019

Feature Description (continued)

VCC
Device

Input Logic Output

-IIK -IOK

GND

Figure 3. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.4 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum
input voltage value specified in the Recommended Operating Conditions.

8.3.5 Unbuffered Logic

A standard CMOS logic function typically consists of at least three stages: the input inverter, the logic function,
and the output inverter. Some devices have multiple stages at the input or output for various reasons. An
unbuffered CMOS logic function eliminates the extra input and output stages; the device only contains the
required logic function which is directly driven from the inputs and directly drives the outputs.
The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes
in the oscillator circuit due to having lower total gain than a buffered equivalent. To learn more about how to use
an unbuffered inverter in an oscillator circuit, see Use of the CMOS Unbuffered Inverter in Oscillator Circuits.

8.4 Device Functional Modes

Table 1. Function Table (Each

Inverter)
INPUT OUTPUT
A Y
H L
L H

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 9

Product Folder Links: SN74LVC2GU04-Q1
SN74LVC2GU04-Q1
SCES902 – AUGUST 2019 www.ti.com

9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

The unbuffered inverter is commonly used in oscillator circuits because it is less sensitive to parameter changes
in the oscillator circuit due to having lower total gain than a buffered equivalent. An example application circuit is
shown in Figure 4. To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use
of the CMOS Unbuffered Inverter in Oscillator Circuits application report.

9.2 Typical Application

Copyright © 2017, Texas Instruments Incorporated

Figure 4. Typical Application Diagram

9.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The high drive also creates fast edges into light loads, so
routing and load conditions should be considered to prevent ringing.

9.2.2 Detailed Design Procedure

To learn more about how to use an unbuffered inverter in an oscillator circuit, refer to the Use of the CMOS
Unbuffered Inverter in Oscillator Circuits application report.
1. Recommended Input Conditions
– Specified high and low levels. See (VIH and VIL) in Recommended Operating Conditions.
– Inputs are overvoltage tolerant allowing them to go as high as (VI max) in Recommended Operating
Conditions at any valid VCC.
2. Absolute Maximum Output Conditions
– Load currents must not exceed (IO max) per output and must not exceed (Continuous current through VCC
or GND) total current for the part. These limits are located in Absolute Maximum Ratings.
– Outputs must not be pulled above the voltage rated in the Absolute Maximum Ratings.

10 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: SN74LVC2GU04-Q1

 SN74LVC2GU04-Q1
www.ti.com SCES902 – AUGUST 2019

Typical Application (continued)

9.2.3 Application Curve
1600
Icc 1.8V
1400 Icc 2.5V
Icc 3.3V
1200 Icc 5V

1000

Icc - µA
800

600

400

200

0
0 20 40 60 80
Frequency - MHz D001

Figure 5. ICC vs Frequency

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions table.
The VCC pin must have a good bypass capacitor to prevent power disturbance. A 0.1-µF capacitor is
recommended, and it is ok to parallel multiple bypass caps to reject different frequencies of noise. 0.1-µF and 1-
µF capacitors are commonly used in parallel. The bypass capacitor must be installed as close to the power pin
as possible for best results.

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 11

Product Folder Links: SN74LVC2GU04-Q1
SN74LVC2GU04-Q1
SCES902 – AUGUST 2019 www.ti.com

11 Layout

11.1 Layout Guidelines

Even low data rate digital signals can contain high-frequency signal components due to fast edge rates. When a
printed-circuit board (PCB) trace turns a corner at a 90° angle, a reflection can occur. A reflection occurs
primarily because of the change of width of the trace. At the apex of the turn, the trace width increases to 1.414
times the width. This increase upsets the transmission-line characteristics, especially the distributed capacitance
and self–inductance of the trace which results in the reflection. Not all PCB traces can be straight and therefore
some traces must turn corners.
An example layout is given in Figure 6 for the DRY (SON) package. This example layout includes a 0402 (metric)
capacitor and uses the measurements found in the example board layout appended to this end of this datasheet.
A via of diameter 0.1 mm (3.973 mil) is placed directly in the center of the device. This via can be used to trace
out the center pin connection through another board layer, or it can be left out of the layout

11.2 Layout Example

Bypass capacitor
placed close to
the device
GND VCC
0402

0.1 F
VCC

1Y 2Y
4
6

1A 2A
3
1

Avoid 90° GND

corners for
signal lines Recommend GND pour for
improved signal isolation,
noise reduction,
GND and thermal dissipation

Figure 6. Layout example for DRY package

12 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated

Product Folder Links: SN74LVC2GU04-Q1

 SN74LVC2GU04-Q1
www.ti.com SCES902 – AUGUST 2019

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation
For related documentation see the following:
•
•
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.

12.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.4 Trademarks
E2E is a trademark of Texas Instruments.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2019, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: SN74LVC2GU04-Q1
 PACKAGE OPTION ADDENDUM

www.ti.com 13-Sep-2019

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

1P2GU04QDRYRQ1 PREVIEW SON DRY 6 5000 TBD Call TI Call TI -40 to 125

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you
permission to use these resources only for development of an application that uses the TI products described in the resource. Other
reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third
party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims,
damages, costs, losses, and liabilities arising out of your use of these resources.
TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on
ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable
warranties or warranty disclaimers for TI products.

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2019, Texas Instruments Incorporated