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45 views38 pagesVLSI Testing Fundamentals Part4
Semiconductor Testing Fundamentals document
Uploaded by
Parthiban SelvarajCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF or read online on Scribd
/ 38
Test Program Development Issues
Test Program Development Issues
Objectives:
This section explains:
4+ The various types of test programs
+ Issues to consider before developing a test program
¢ Considerations for developing the program flow
+ Power up/ power down sequencing
+ Binning
+ Test summary reports
What is the Primary Purpose of the Test Program?
Engineering
The initial test program is often an engineering tool used to verify the functionality of the device and maybe to
gather information about it. The program should be structured to allow easy modification of voltages, currents
and timings. It may also have routines to allow quick debugging and may contain some characterization
routines,
Characterization
‘The characterization program is developed to determine the operational limits of the device. Itis often an
extension of the engineering test program. The characterization program should take advantage of routines
that are included with the tester operating software. Standard routines may include shmoo plots, level search
and timing search routines.
Production
‘The main purpose of the production test program is to separate the bad devices from the good. The program.
may be used for wafer sort, final test or QA test (quality assurance). It should execute as fast as possible. The
flexibility of the engineering program is traded for the faster test time of the production program.
‘The Fundamentals of Digital Semiconductor Testing, na q=
leat Uh, Test Program Development Issues
Other Considerations
Hardware Limitations
‘Once the device specification has been carefully reviewed and a detailed test timing diagram has been
developed, make certain the test hardware is capable of meeting the test requirements. Take into account the
test rate (maximum frequency), as well as voltage and current requirements for inputs, outputs and VDD. Do
not forget wafer probers, device handlers and other external equipment that may be required.
Throughput
Estimate the device test time on the target test system. Is the test time satisfactory? Ifthe device goes into high
volume production will the test throughput be adequate? If not, an alternate test system may be a better
choice.
System Availability
Will the target test system be available when needed. Will the support equipment that interfaces to the target
tester be available when needed?
Test Costs vs. DUT Cost
‘The cost of testing the device must be considered when selecting the target test system, it may not be cost
effective to test a low cost device on a very expense test system.
Initializing the Program
The opening menu allows the operator to select the test options to be used during testing. Some of the
standard options are: Wafer Sort, Final Test, QA Test, Characterization, temperature selection, and possibly the
selection of various versions ot options of the device. Additional information may also be collected, for
‘example: Lot Number, Operator ID, Test system number. The opening menu may also provide the operator
with instructions for setting up the test hardware.
Verifying the Test Setup
A loadboard test and a quick diagnostic must always be executed before testing devices. The program should
be designed so that testing can not begin until the loadboard and diagnostic tests pass. The ability to rerun the
Joadboard test at any given time is also useful.
n2 ‘The Fundamentals of Digital Semiconductor Testing Test Program Development Issues
Power-on Sequencing
Care must be taken when powering up the device. CMOS devices may latch up if any voltage exceeds VDD or
ground by more than 0.5V. Latch up can cause excessive currents to flow within the device and may result in
the destruction of the device under test. A safe procedure for powering up the device is to first apply zero volts,
to all power and input pins (make sure the pin electronic drivers are turned on for the inputs). Power up the
‘VDD supply, then program the VIL/VIH supplies. Power up any external circuitry or loads last. See Figure 11—
L
Power On Sequence
Power up VDD
Figure 11-1
‘The Fundamentals of Digital Semiconductor Testing, 13 i ‘D> (Test Program Development Issues
Te
Power-off Sequencing
‘After the binning information has been completed, the device and the test system must be prepared for
power-down. The device must be powered down in sequence—first any output loading or external hardware
must be disconnected. The inputs may then be powered down and last the VDD supply is shut off (set to OV
then disconnected). The test system drivers should also be shut off at the end of test. See Figure 11-2.
Power Off Sequence
Figure 11-2
4 ‘The Fundamentals of Digital Semiconductor Testing Test Program Development Issues Je<| m= Wm
Test Program Development Review
‘What are the requirements for an engineering test program?
‘What is the purpose of the production test program and how does it differ from the engineering
Program?
‘What test system routines are likely to be used within a characterization program?
‘There are many issuies which should be considered before test program development begins, name at
least three:
Why is a loadboard test important?
Ii the power-up or power-down sequence is performed incorrectly, what may occur?
During production testing, what action is normally taken when a failure occurs?
a) Testing stops
b) The test summary is updated
©) A fail bin is selected
4) Allof the above
©) None of the above
‘The Fundamentals of Digital Semiconductor Testing us Soft|% =
Fest\me? le Test Program Development Issues
16 ‘The Fundamentals of Digital Semiconductor Testing Creating a Test Program
Creating a Test Program
Objectives:
‘This section explains:
¢ How to begin test program development.
¢ Loadboard tests and hardware diagnostics
+ How to debug a new test program
Developing the Test Plan from the Device Specification
Before you begin to develop a test program the entire device specification should be reviewed in detail. As you
review the specification make a list of all the individual tests and include the exact conditions for each test.
Make certain you understand all specifications, including a detailed understanding of the device timing. Be
sure you have the current information—last minute changes to the specification (or device pin out) can ruin
the best made plans. If possible, meet with the designer to clear up any uncertainties that you may still have.
The following information may provide some helpful hints.
Take Notes!
While reviewing device specifications itis helpful to write down your ideas and concerns, and to make note of
items which may need special consideration. Get a notebook or file folder to help organize all of the
information available.
Power and Ground
Review the voltage and current requirements for the device under test. High current devices may require
hardware with dedicated power and ground planes. Device pins that require high VDD voltages may need to
bbe isolated from the tester driver and comparator circuitry.
Some test systems provide a driven or buffered ground, while others have only a hard ground; some test
systems have both. The type of ground used for any given device should be taken into consideration in the
early stages of program planning. Some test systems provide sense lines to monitor power and ground. If this
option is available, proper connections must be made on the test hardware to insure accurate voltages at the
DUT Using capacitors or other mean to reduce power supply noise caused by the DUT (decoupling the
Supplies) must also be considered,
Special Considerations
While reviewing the device specification make note of any conditions that will require special considerations.
Open drain outputs, for example, will require some type of pull-up. A device with a high IDD current may
require extra VDD or Ground paths. Some devices may require a high voltage signal to put the device into a
special test mode or to program an EEPROM.
‘The Fundamentals of Digital Semiconductor Testing a +], em
Test| 3 (Creating a Test Program
Notes and Exceptions
Exceptions or special notes may be associated with a particular parameter—be sure to read the details. It may
be stated that the parameter is guaranteed by design and does not require testing. Other parameters may need
toberelaxed during testing due to fixture noise. Some device specifications may define the amount by which a
given parameter may be relaxed. Additional information may also be given which applies to specific tests.
Functional Test Timing
When developing a functional test all of the timing defined in the test specification should be carefully
reviewed, then a test timing diagram should be developed for use within the test program. Consideration
must be given to the speed, accuracy and number of resources available for the target test system. It is also
useful to review the tester specification to insure that you understand the capabilities and limitations for the
target test system.
Itmay not be possible to exercise all ofthe various input timing edges and signal formats or to test all of the
AC parameters at one time. Develop a basic timing strategy that will work well fora gross functional test.
‘Once the basic timing is developed you can then begin to add complexity to your timing diagram.
‘The frst step in developing the test timing is to define the frequency (test rate) and placement of the clock and
control signals. Next, determine the active edges of the clock or control signals, when input signals are read
(latched), when output signals are gated out. Look closely at the delay time parameters for output signals.
Make certain that outputs have sufficient time to propagate out before the end of the test cycle. Spend as much
time as necessary to fully understand the device timing. This is one of the most important steps in test program
development!
If the test vectors are being developed from simulation data, review the timing used during simulation. The
test program will need to duplicate the simulation timing, The simulation timing should reflect the device
specification timing and must also be compatible with the performance of the test system.
Designing the Test Hardware
If time allows, design and build only the test hardware for hand testing the device. In the event that extensive
hardware changes are required during the initial device/ program debug, it will be unnecessary to alter the
probe card and interface hardware if they are not yet built.
Always attempt to minimize the complexity of the test hardware by keeping the number of external
‘components and wiring to a minimum. Remember, hardware has a way of self-destructing when used in a
production environment. Its up to the test engineer to use as much of the internal tester circuitry as possible
to accomplish the task of testing the device.
Review the notes you have been collecting—does the device require special hardware considerations? If s0
now is the time to work out those details.
Writing the Test Program
Begin by entering the device pin to tester mapping. This should include the device pin, signal name, function
(input, output, 1/0, power) and the tester pin associated with each signal.
22 ‘The Fundamentals of Digital Semiconductor Testing. Creating a Test Program
Once the definition of each individual pin has been entered, pin groups can be defined. Pin groups are created
based on similar characteristics, timings, voltages, currents etc. Once entered, be sure to check your work, this
information will be used again and again throughout the development of the test program.
Develop the Opens and Shorts and Gross IDD current tests next, then the Gross Functional test. At this point
‘you have enough to get started. If time allows, add the input leakage test.
Loadboard Tests
Develop a complete loadboard test before you begin testing. The loadboard test must include a leakage test of
all pins, a test of VDD and ground pins, and all external relays, resistors or other extemal components. A quick
tester diagnostic must also be included as part of the loadboard test: See Figure 12-1
Loadboard Test Flow Diagram
Start
[Leakage Test alt
(allrelays open)
Figure 12-4
‘The Fundamentals of Digital Semiconductor Testing, 123 me
Stlmo? Uy Creating a Test Program
Tester Diagnostics
tis important to include a quick tester diagnostic as part of the loadboard test. A basic diagnostic can consist
of forcing the input reference low supply to 0.8V and the input reference high supply to 2.0V, then test all pins
with the DC measurement system.
A fast functional test of all pins is also very useful. The driver and comparator circuitry for each pin can be tied
together to perform a self-test as an easy way to functionally verify that all pins are working correctly.
Running the Program the First Time
Hardware Verification
‘Once the test hardware is built and the loadboard test is written, the test hardware can be verified. Make
certain that the complete loadboard test is working correctly and that the test system passed the hardware
diagnostic. Do not attempt to verify the device test program until the hardware and test system are fully
functional.
Opens and shorts
After the loadboard and test system have been verified, turn on the datalogger and run the opens and shorts
test with an open socket. Make certain that all pins fail the opens conditions. Next, insert the device into the
test socket and again run the opens and shorts test, but stop the program immediately after the opens and
shorts test. Review the datalog measurements to make sure the readings are well within the pass/fail limits. If
necessary adjust the limits as needed.
Gross Current Tests
Run the program again and this time stop immediately after the gross current test and datalog the measured
value of the gross current test. Ifthe positive supply (VDD) is measured the current must be positive. Does the
reading make sense? Example: If the device specification for IDD is 5mA and the measured value is 4mA.
something is wrong,
‘The significance of this test, at this time, is to signal some type of gross problem. If the measured current
appears incorrect, remove the device from the test socket and run the test again. The empty socket reading
should be 0.0mA; if it isnot, investigate and solve the problem.
Verifying the Functional Test Setup
Before functionally testing the device, loop on the test pattern and, using an oscilloscope, observe each tester
channel. Are the timing and voltages correct? Check VDD and ground—do they look correct? Be sure to look
at every signal (including the output strobe, if possible). If pull-up resistors or current loads are required, make
sure they are connected and working correctly.
Basic Functionality
Running the gross functional test is when the fun really begins. Turn on the functional datalogger, press the
start button, sit back and watch the results. What happened? If nothing failed there is probably trouble.
4 ‘The Fundamentals of Digital Semiconductor Testing Soft] & =
Creating a Test Program t] > &
Remember that the lack ofa failure does not guarantee that the testis being performed correctly. Remove the
device from the test socket and run the test again. Did it fail? Review the failures and make sure that
everything that should fail did fail. If the test still does not fail, review the test program—something is clearly
‘wrong,
‘Chances are that the test failed the first time you ran it. If so, review the datalog to look for clues—are all the
failures somehow the same, e.g. only logic 1 failures or only logic 0 failures? Possibly a certain bus is the only
failure. See if any of the test pattern is working. Does the pattern fail at the very beginning? Maybe the vector
pattern has an initialization problem or the output strobe is wrong. Ifthe functional testis made up of multiple
patterns, run all of the patterns to collect as much data as possible. Datalog the results to disk or paper because
‘you will need to spend time off line to analyze the failures.
Leakage Tests
Run the leakage test, datalog the results and make sure the readings are correct. Ifthe functional test failed and.
the leakage test failed, investigate the leakage test. Solving the leakage failure may improve the functional test
results
A Brief Discussion on Test Vectors
‘Test vector patterns combined with timing values and signal formats are the heart of the test program. Vector
patterns are often developed by the design engineer during functional simulation of the device. They must
then be converted to test vector format for use in the test program. If this is the case and the test vectors fail the
functional test, be sure to collect as much information as possible (datalogs) and review the failures with the
design engineer. Give the design engineer a copy of the Simulation for Test guidelines, found in chapter 10.
Explain exactly what the program is doing and be sure the timing used during simulation is the same as the
timing used in the test program.
‘The Fundamentals of Digital Semiconductor Testing, 25 4
126
=
stl x Creating a Test Program
Creating a Test Program—Review
‘What is the very first test that should be run when debugging a new test program?
a) The opens and shorts test
b) The loadboard test
©) The gross IDD test
4) The gross functional test
©) None of the above
What is the purpose of the Gross ID current test?
‘What steps should be taken to verify the functional test setup before testing the first device?
‘When executing functional tests for the very fist time, what should be done if the test result is a pass?
) Go out for beer and pizza
b) Remove the device from the socket and run the test again
©) Test another device
4) None of the above
If the functional test fails and the input leakage test also fails, which test should be debugged first?
a) Functional
'b) Input leakage
The Fundamentals of Digital Semiconductor Testing, Troubleshooting
Troubleshooting
Objectives
Upon completion of this section you will understand:
‘+ How to find where problems occur
‘+ How to look for clues in the test results and isolate the problem
4+ The proper sequence for debugging,
‘+ What test system utilities are available
‘+ The function of the various system utilities
‘+ How to use tester tools for debugging
Introduction
‘The Verifying DC Parameters section has information on trouble-shooting each specific DC test. But it does not
give an overall approach to finding a test problem, especially on a production floor where “down time" is very
expensive. When you consider all the possibilities for a testing problem, it can be difficult to choose a starting,
point. To simplify the problem, begin by narrowing the possibilities to four main suspects. When a failure
‘occurs during test, the cause may be:
‘¢ The Device Under Test
‘+ The Interface Hardware (loadboard, test socket, pogo pin)
‘¢ The Test System
* The Test Program
‘While trouble-shooting, the exact cause of the failure may be identified, or if three of the four suspects are
climinated, then the last remaining possibility must be the cause; either way the problem will be found.
Although there are many approaches to trouble-shooting, the first step is to perform the test with the datalog
utility enabled to allow the exact measured value to be observed and evaluated. Consider the test method in
use when the testis performed. Also, compare a failing measurement with a passing value. Determine if the
‘measured result is a limit (marginal) failure or a catastrophic failure.
If the failure appears to be catastrophic, try to determine the cause. First, consider the test method. Then notice
if the measured result was produced by the PMU clamp circuitry. Or the measured result may be the
‘maximum value of a PMU measurement range. The measured results will contain clues to the riddle—it is up
to you to use the clues to solve it.
Once the results have been analyzed you should have an idea of what to do next. Itis generally best to start by
doing the easiest thing first that will result in gaining useful information. Keep in mind there will be many
things to try, but first do the easiest thing that will give useful information. In many cases removing the device
from the test socket will provide valuable information. Generally this is the easiest thing to do, but be aware
that it will not always yield valuable information.
‘The Fundamentals of Digital Semiconductor Testing Bt =
YE, Troubleshooting
Where to Begin
Your starting point will be influenced by several factors. Among those will be:
+ what test is failing?
‘+ what is the history of the test program and device?
‘+ What is known about the problem at that point in time?
First, find out what's failing, enable the datalog utility and look closely at the test results, Determine which test
is failing—is ita DC fail, an AC fail or a functional fail? Notice the number of failures—is only one test failing,
possibly one pin failing?
Look for basic clues. Ifthe problem is not apparent, proceed methodically and remember to solve one problem at a
time.
Verify the Test Hardware
Run the loadboard test if the program has one (the program should have one). Continue only if the test
hardware is performing to specification. It may also be helpful to remove and reinstall the loadboard.
Test a Standard Device
Get a known good device and test it and note the differences in the measured results. Determine ifthe failing
product has been successfully tested on this test system before.
Try to Verify the Basics
Make sure that both the test program and the failing device are the correct revisions. Make sure that the device
is placed in the test socket correctly. Make certain that any data required by the test program is entered
correctly.
Once you have determined:
‘+ the diagnostics are passing
+ thestandard device fails
‘the program is the correct revision
‘+ the devices are the correct revision
pick one test and find out why itis failing. Start by getting an oscilloscope and a DVM. Pause on the failing test
and verify that VDD and the input levels are correct. Verify that all timings are correct. Be sure to look at every
device pin with the oscilloscope. Look for noise or levels that appear to be incorrect.
Use Relaxed Values
Relax the test parameters to make it easier for the device to pass. Relax VIL/VIH/VOL/VOH and test the
device again. Relax the timing parameters. Test the device again and see if the results change.
132 The Fundamentals of Digital Semiconductor Testing Troubleshooting
Try Another Test System
I possible, test the device on a different test system. Ifthe results are the same, itis not a test system problem.
If the device passes, contact the test maintenance department and explain the problem seen on the first test
system.
Make Certain Opens and Shorts is Passing
The device will not function correctly if the opens and shorts testis failing. Ifa number of tests are failing, get
the opens and short test to work first. Once you have the opens and shorts test passing, look into any input
leakage failures.
Is it a Tester Problem?
If another test system is not available for use and all of the above suggestions have failed to provide a solution,
itis time to contact the test maintenance department and ask to have a complete tester diagnostic run. Do this
only after you have tried all of the items above.
Collect and Review the Datalog Results
A good way to start the investigation is to datalog the test results to a printer or file so they can be studied.
Don't waste expensive tester time viewing results on the video display if you can do it off-line. Datalog both
‘pass and fail measurements for al tests.
Analyze the Results of All the Tests
Look carefully at the results of all tests, both passing and failing. There will often be helpful clues in the
datalog information. Notice if the device is drawing the correct amount of ID current. Also, check to see if the
input leakage tests are failing. See if the VOL /VOH voltages look correct. If the failure is a DC measurement, is
ita limit failure or a catastrophic failure?
Has this Failure Ever Passed Before?
Verify that the failing test has worked in the past. Are there datalogs showing the results of a successful test? If
so, compare the results ofall tests.
Limit Your Debug Time
It isa good idea to limit the number of hours spent debugging one problem. This is an individual choice, but a
good rule of thumb is do not spend more than two or three hours working on the test system on a single problem. If you
‘work more that several hours on one problem, stop and take a break, discuss the issue with a colleague.
Double Check All Your Work
If failures occur when the test program is initially being debugged, collect as much data as possible and then
go back to your desk and review all of your work. Itis often helpful to have a colleague assist in reviewing,
your work-discussing the problem with another engineer may help you find a solution more quickly.
‘The Fundamentals of Digital Semiconductor Testing 133 Example: ITL/IIH Test Failures
Let's say that the input leakage test (IIL/IIH) is failing. This test forces voltage and measures current, therefore
the failure will be due to excessive current flow. It is possible that the device under test may be defective and
the inputs are simply consuming too much current. Itis also possible that there may be a problem with the
interface hardware, the test system or the test program.
The first step is to perform the test with the datalog utility enabled. This will allow the exact measured value to
bbe observed and evaluated. Does the failure appear to be a limit failure or is it a catastrophic failure?
Step 1 - Eliminate the DUT
Since the testis failing due to excessive current it makes sense to remove the device under test from the test
socket and repeat the test with an open socket, After the testis repeated, evaluate the test results by examining
the datalogged measurement. Ifthe current is now zero the test will pass, indicating that the device under test
is most likely defective.
If however, the datalogged measurement indicates that current is still flowing when the testis performed with
an open socket, then the problem is most likely the interface hardware or the test system.
Step 2 - Eliminate the Interface Hardware
If current still flows with no device in the socket, the next step will be to remove the interface hardware. The
interface hardware consists of whatever is between the pin electronics and the DUT. This will include the
loadboard and socket when performing hand test. The probe card is included at wafer sort and the interface to
the handler is included if an automatic handler is in use.
‘Once the interface hardware is removed, the test should be repeated and again the measured results observed.
If the datalog indicates zero current flow then the interface hardware most likely has a problem. If the datalog
indicates that current is still flowing then the test system hardware may have a problem.
Step 3 - Eliminate the Test System Hardware
If current still flows with the interface hardware removed, the test system is the likely suspect. If possible, try
the test program on a different test system. If no other test system is available, then itis probably time to run
the test system diagnostics or call the maintenance department for help. Ifthe test system has a problem then
the diagnostics should identify the hardware failure.
Step 4 - Eliminate the Test Program
So you have heard that software can't break, right? What is the point of reloading the test program? There are
several reasons why you may want to do this:
1. The test program and test vector data is stored in memory inside of the test system. Itis possible for
the test information to become corrupt during testing due to electrical power noise, a loose electrical
‘connection, or some other unforeseen problem. Once the data is corrupt, the problem can only be cor-
rected by reloading the test software.
2. Some test programs may present a series of questions that must be answered when the program is ini-
tially loaded. These questions may include selections for the type of test to be performed such as
‘Wafer Sort, Package Test, or Auto-handler Test. Each option may require unique tester-to-device pin
14 ‘The Fundamentals of Digital Semiconductor Testing, Test
connections, The program may request information regarding the type of device package such as a 64
pin package or an 84 pin package. The program may also request information regarding device
options that may be available, such as on board ROM or RAM. When you reload the test program
‘make certain that all of your answers are correct.
‘When reloading the test program make certain that you are using the correct test program name and the
correct revision. It is easy to enter the program name as L17297B when the correct program is L17279B.
Troubleshooting
Debug Tools
Scope Tool
‘Most test systems have some method of looping on a functional test vector pattern and providing a means of
creating a sync marker at a selected vector memory location. The test pattern can be started and stopped at any
point within the vector set and failures can be ignored. The oscilloscope can be used to verify the proper timing,
and voltage levels when verifying a new test program or for investigating test problems. Itis absolutely
essential to become proficient at using this debug technique.
Shmoo Plot
‘Shmoo plots are useful for debugging test problems and for finding the pass/fail limits of device operation.
‘Shmoo plots can be executed from the tester keyboard or from within the test program. This tool is very useful
in developing device characterization programs and collecting data for both DC and functional tests.
Search
Search performs either a binary or linear search for both DC and Functional tests. This tool provides a means to
take a quick look at input and output thresholds, or it can be used to provide accurate measurements of device
‘timings. Itis also very useful in developing device characterization programs.
Manipulating Tester Resources
‘Tester resource settings can be read and modified directly from the workstation keyboard. Power supplies,
input references, comparator values, timings and functional data can all be manipulated. To debug a test
problem, pause on the failing test and modify the appropriate parameters. The “Execute Button” can be used
{o verify the results of the modification. An oscilloscope can be used to verify pass/fail results. Become
familiar with all ofthe tester tools—they will greatly enhance your ability to debug and resolve problems
quickly.
Viewing Test Vectors
Each test system offers a way of viewing the vector patterns stored in memory. These utilities are essential for
debugging test vector problems. They are also useful when a partial vector file listing is needed. Test vectors
can be modified from the keyboard and the results tested.
‘The Fundamentals of Digital Semiconductor Testing 135 Debug and Troubleshooting Review
How do you begin to debug a failure?
fall the devices being tested appear to have the same failure you should:
a) Discuss the problem with a colleague
b) Geta known good (standard) device and test it
©) Call maintenance
4) None of the above
Ifevery test fails, what test should you debug first?
If the VIL/VIH functional test fails and all other tests pass what is the most likely problem?
‘When debugging a test problem is it important to understand the entire test program flow.
a) Yes
b) No
Explain why you selected yes/no in the previous question:
If the functional test is failing what could be changed in an attempt to make it pass?
a) Relax the input levels
b) Relax the output levels
©) Relax the timing
4) Allof the above
‘The Fundamentals of Digital Semiconductor Testing 10.
nu.
2
Troubleshooting
‘What is the scope tool used for?
‘The search utility will generally provide two methods of performing a search. What are they?
‘Shmoo plots provide valuable information but they may require considerable time to execute.
a) True
b) False
Learning to manipulate the test hardware will greatly increase your productivity when developing or
debugging test programs.
a) True
b) False
“Most test systems provide a means of modifying test vector data stored in vector memory directly from
the keyboard.
a) True
b) False
‘The Fundamentals of Digital Semiconductor Testing 137 Soft}
Test!
138
|
me
> Gy Troubleshooting
‘The Fundamentals of Digital Semiconductor Testing, Qualifying and Documenting the Test Program
Qualifying and Documenting the Test Program
Objectives
This section explains:
+ How to qualify a test program
+ How to create a test documentation package
Qualification
Sample Device Requirements
Itis essential to serialize and save sample devices once test program generation is complete. If possible the test
engineer should keep several samples separate from the production samples. Complete datalogs (with serial
numbers) should also be kept for each sample device. The following items should also be noted on the datalog:
test program revision, test system used and date tested. In the event that test problems arise, this information
will be extremely valuable.
Checking the Margins
Margins refers to the amount by which a parameter can be varied before a failure occurs. Once the test
program has been completed the margins should be verified. Use system utilities such as VLS and Shmoo
when possible. Some test systems offer a utility designed to vary all parameters +/~a certain percentage. If a
parameter is very close to failing, it will probably become a production yield issue. The idea is to identify the
problem and resolve it before production testing begins. All voltages, currents and timings should be varied.
Save this information for later reference.
Shmoo the Test Vector Patterns
If possible, Shmoo plot each test pattern to look for holes in the plots or other irregularities. Plot VDD vs. VIL/
VIE and VDD vs. output delays. Save this information for later reference.
Verify Binning and Summary
The binning and summary routines must be verified. A failure of each test type must be generated, then verify
that the failure results in the proper binning, Keep track of failures, take a test summary and make sure the
summary is correct.
‘Temperature Testing
‘Test the device over its specified temperature range. If it performs well, extend the temperature range by 10
percent and repeat the tes. Its best to find out early ifany potential problems exist. Record and save this
information for later reference.
‘The Fundamentals of Digital Semiconductor Testing, Ma stl 8 a Qualifying and Documenting the Test Program
Verify testing on handlers and probers
If the device is to be tested at wafer test or with an auto-handler, be sure to set up the extemal hardware and
verify correct operation.
Documenting the Test Program
Documentation
Once the program is completed a documentation package must be prepared. It is best to keep the information
onganized—a three ring binder works well for this. Begin by summarizing all of the test development activity.
Make certain to note any deviations from the test specification and reference any supportive documentation
such as Shmoo plots, datalogs, memos, et. Include the test time and detail any special requirements such as
‘external hardware, non-standard auto-handling, etc. All correspondence between the test engineer, design
‘engineer, product engineer, the customer, et. should also be included.
Program Listings
Include a listing of the program source code exactly as the program was initially released. It is also useful to
save a compiled listing. A tape or diskette copy is the most convenient but a paper copy can be viewed
anywhere.
Program Flow Chart
Include a program flow chart of all tests and show binning results of each test.
Datalogs
Include complete serialized datalogs showing the results of al tests. Also datalog an open socket and show the
results ofall tests. Review the open socket results to make sure each test fails. Check leakage and current
readings too.
Test Specification
Include a copy of the test specification used for program development.
Hardware Documentation
‘Complete and thorough hardware documentation is essential. Include both drawings and a written
description of all test hardware. This documentation must include enough information to build additional sets
of hardware without the need to see the original hardware.
Standard Devices
A minimum of five standard devices must be included in the documentation package. These devices must be
serialized and datalogged.
42 ‘The Fundamentals of Digital Semiconductor Testing, Sof
Qualifying and Documenting the Test Program Jos;
Sst
Backups and Archives
‘The test program must be saved on magnetic tape or diskette or other means of backup. Make several copies of
the final software, one for the documentation package and one for your own files. Itis also a good idea to save
a copy ofall files associated with the development of the program. Keep all simulation files, test cases, etc. This
information can be compressed and saved on tape or diskette. Be sure to clearly mark each tape—the data on
the tape must be easily identifiable.
‘The Fundamentals of Digital Semiconductor Testing, 143 a
sth Ue Qualifying and Documenting the Test Program
Qualifying and Documenting the Test Program Review
L
3.
ut
Why is it essential to save sample devices?
‘To what does the term margins refer?
Ifa test vector pattern is working correctly, a Shmoo plot of the VDD vs. VIL will show no “holes.”
a) True
b) False
List at least four items which must be included in a test program documentation package:
The Fundamentals of Digital Semiconductor Testing S
e
CMOS Device Latch-up
CMOS Device Latch—-up
-Advanced Topic-
by Vernon Rubright
Objectives:
‘This section explains:
‘¢ The cause of latch-up in CMOS devices
+ The effects of latch-up
‘+ Ways to prevent latch-up
‘+ How to test devices for latch-up
What is Latch-up?
‘Complementary MOS (CMOS) evolved as a result of circuit design innovation using the combination of
‘opposite polarity MOSFETs (P- and N-channel). This introduced the use of p- or n-wells to isolate the
‘transistor types. These wells along with the desired MOS transistors form a (parasitic) four-layer silicon device
(NPNP) commonly known as a Silicon Controlled Rectifier. Figure 15-1 illustrates how this structure is formed
and shows the SCR as two lateral bipolar transistors in a regenerative configuration with the collector of one
feeding the base of the other: The emitter of the PNP is the anode and the emitter of the NPN is the cathode.
‘The bases function as complimentary gates.
‘The electrical characteristics of the SCR are shown in Figure 15-2. With a positive voltage applied to the anode,
the device blocks the flow of current until the forward breakover voltage (VBO) is reached. At this point the
device switches into a high conduction state and the voltage across the device drops to about 1V. In the high
conduction state, current flow is limited only by the external circuit impedance and supply voltage. At
voltages below the breakover voltage, the device can be switched into the high conduction mode with a small
gate current. Once the SCR is in the high conduction latch-up state, it can only be switched off by reducing the
anode current below the holding current (IF).
‘The Fundamentals of Digital Semiconductor Testing, 151 a
tn? Uy CMOS Device Latch-up
Parasitic SCR in CMOS Device
Figure 15-1
Since the gates of the SCR are connected to the substrate and isolation well, current flow in these areas can
cause the SCR to enter the high conduction state. The most common sources of these currents are:
1. Input or output voltage swings that extend beyond the power rails (VDD/GND) and cause current to
flow.
2. Improper sequencing of multiple VDD supplies.
3. _ Internal IPR voltage drops in the power rails resulting from large output drive currents.
152 The Fundamentals of Digital Semiconductor Testing, ©
Gnd
‘When this device begins
to conduct, itis almost a
‘short circuit from VDD to
‘ground.
Figure 15-2
Latch-up can be prevented by controlling the electrical parameters of the parasitic SCR to guarantee the high
‘conduction state can never be entered while the device is operating within the absolute ratings. Parasitic SCR
parameters are therefore just like any other electrical parameter and must be thoroughly characterized to
verify the fabrication design goals.
Latch-up Testing
‘The philosophy behind the Latch-up test is one of attempting to force the parasitic SCR into the high
conduction state. This will occur if the VBO voltage is reached or enough gate current is supplied through the
substrate or isolation wells to cause the SCR to trigger. VBO triggering is tested by applying elevated voltages
to VDD and all input pins. Gate triggering is tested by forcing currents into and out of all input and output
pins. The magnitude of these voltages and currents is derived from the fabrication specifications. Review the
test methodology with the circuit design engineer and /or process engineer to establish test conditions that will
verify the design goals.
‘The Fundamentals of Digital Semiconductor Testing 153 om
> (, CMos Device Latch-up
‘Parameter Definition ‘Typical value
VDDwax | Maximum operating VDD 5.25V
VDDOVR | Maximum elevated VDD. 7.0V for a5.0V design
‘VIHOVR | Maximum elevated positive input voltage VDD +05V
VILOVR | Maximum elevated negative input voltage GND-05v
ETE “Maximum input positive current (Maximum current that can flow
into an input or output without causing Latch-up) >20mA
pon ‘Maximum negative input current (Maximum current that can flow
‘ut of an input or output without causing Latch-up) >20mA,
IDDQ ‘Maximum quiescent IDD current Spec. Static IDD_
DDI Measured quiescent IDD current
= ‘Maximum delta in IDD current after trigger condition VIH/LOVR
or TRIGIH/L applied <5.0 % of IDD1
Test Patterns
1. Precondition device to a known state (Same as static IDD).
2. Ripple all inputs high and low in complement field.
3. Toggle all outputs high and low (Same as VOH/VOL).
4. Place high Z outputs in the high impedance state (Same as 107).
‘Since current is limited only by the external circuit, if the SCR triggers, the VDD power supply must limit
current flow to a safe level (approximately 300mA). If the VDD supply can not be programmed to limit the
current a resistor should be placed in series with the supply. Large power supply bypass capacitors (> 20jF)
should also be removed during latch-up testing.
‘Testing starts with the program outputting a message identifying the following as elevated voltage tests for
\VBO triggering, VDDyax is then applied with the input levels set to the power rails (VIH = VDDyax, VIL =
GND). Test pattern 1. that preconditions the device to a known state is then executed. The DC measurement
system is then used to measure the amount of current flowing into the VDD pin(s). This value is compared to
the IDDQ limit and also stored in a program variable (IDD1). If the measured value is greater than IDDQ the
program outputs a message indicating the device failed the initial quiescent ID current along with the value
of VDD and the measured current. The device is then powered down and testing terminated.
If the measurement is less than IDDQ the test continues by increasing VDD to VDDOVR and then setting the
input levels VIH = VIHOVR and VIL = VILOVR. Test pattern 2 is then executed to individually toggle each
input pin high and low while the remaining pins are in the opposite state. The input levels then VDD are
returned to the original values and test pattern 1. is executed again. The DC measurement system is used to
measure IDD and the resulting value compared to a dual limit that requires the measurement to be
than (IDD1 -IDDT) and less than (IDD1 + IDDT). If the measured value is outside of these limits the program
outputs a message indicating the device has latched up (failed). Ifthe measured value is within these limits the
program outputs a message indicating the circuit did not latch up (passed). The program then outputs the
value of VDD, VDDOVR and IDD. The device is then powered down in preparation for the next test.
154 ‘The Fundamentals of Digital Semiconductor Testing, CMOS Device Latch-up
Itis important to point out that VDD is never reduced below VDDyax between the first and second IDD
‘measurements (Do not power down between the first and second IDD measurements.) Ifthe test system being,
‘used can not functionally drive the voltage levels required for the inputs, the DC measurement system should
be used to individually toggle each input while the remaining inputs are functionally driven to the maximum
capability of the tester.
‘Testing continues by outputting a message that identifies the following as trigger current tests for the input
pins. VDDj4ax is then applied with the input levels set to the power rails (VIH = VDDyqax, VIL = GND). Test
pattern 1. is executed and the DC measurement system used to measure the current flowing into the VDD
pin(s). This value is compared to the IDDQ limit and also stored in a program variable (IDD1). If the measured
value is greater than IDDQ the program outputs a message indicating the device failed the initial quiescent
IDD current along with the value of VDD and the measured current. The device is then powered down and
testing terminated.
If the measurement is less than IDDQ the test continues by forcing current (TRIGIH / TRIGIL), using the DC
measurement system, into or out of one of the input pins, The current is then removed and test pattern 1.
executed. The DC measurement system is then used to measure IDD and the resulting value compared toa
ual limit that requires the measurement to be greater than (IDD1 - IDDT) and less than (IDD1 + IDDT). If the
measured value is outside of these limits the program outputs a message indicating the device has latched up
(failed). If the measured value is within these limits the program outputs a message indicating the device did
not latch up (passed). The program then outputs the pin name /number, VDD, IDD and (TRIGIH / TRIGIL)
values. The device is then powered down in preparation for the next test. Starting from the point of applying
‘VDD tax this sequence is repeated for both Values of input current TRIGIH, TRIGIL and all input pins.
‘The High Z output pin test begins by outputting a message to identify the following tests as High Z outputs.
‘The testing procedure is identical to the input pin tests with pattern 4. replacing pattern 1. Pattern 4.
preconditions the Hiigh Z pins to the High Z state and when executed must terminate with the High Z pin(s)
being driven by the tester. Make sure the pin being tested is in the High Z.state and the same ending address is
‘used for preconditioning before and after the test current is applied.
Output pin testing is very similar to the High Z tests and begins by outputting a message that identifies the
following tests as output pins. The major difference in this testis that each pin must be tested in two states and
‘only one test current is forced for each state. The outputs are first tested one at a time in the low state by using,
the appropriate vector addresses in pattern 3. The procedure is the same as was used in the Input and High Z
tests, but only the TRIGIL test current is applied. The procedure is then repeated with the output pins
reconditioned to the high state and TRIGIH test current applied.
‘Once the tests have been verified, special features can be added to the test program like allowing the operator
to enter the test parameters, automatically varying the test parameters, or separating the two test types under
‘operator control.
Test Procedure Summary
1. Apply maximum operating voltage conditions.
Precondition device to known state.
‘Measure and store quiescent IDD current, IDD1.
Compare quiescent current to IDDQ limit.
(Output VDD and IDD values and abort test if current greater than IDDQ.
Apply test voltages or currents that could trigger SCR.
Remove trigger conditions and return to maximum operating conditions without powering down.
yoageer
‘The Fundamentals of Digital Semiconductor Testing, 165 oe
> (a CMOS Device Latch-up
8. Precondition device to known state.
9. Measure quiescent IDD current.
10. Power down.
11, Compare quiescent current to first measurement IDD1 + IDDT limit.
12. Output Pass/Fail result and value of VDD, IDD, and trigger parameter (VIHOVR, VILOVR, TRIGIH,
TRIGIL).
Applying Test Stimulus
It is important to point out that Latch-up is prevented only if the absolute maximum ratings are not exceeded.
Since these ratings specify that the input levels must never exceed the power rails (e.g. VDD+ 10% to GND -
10%), care must be taken to properly sequence VDD and the input stimulus. 1/O pins must also be initialized
to prevent high output currents due to contention between the device and tester. Devices with multiple VDD
pins may require VDD to be applied in a given sequence. Check with the circuit designer to establish the
proper sequence. The following sequence is recommended for applying and removing stimulus for all CMOS
tests:
Power Up Sequence
Initialize tester to drive all input pins to OV. Initialize tester I/O pins to the non drive mode with the
‘output loads set to OV.
2. Apply test voltage to the VDD pins in the proper sequence.
3. Set input test voltages VIL / VIE
4. Set output load reference test voltage.
5. Set output compare test voltages VOL/VOH.
Power Down Sequence
Initialize tester I/O pins to the non drive mode.
Set output load reference to OV.
Set input voltages VIL/VIH to OV.
Remove voltage from the VDD pins in the proper sequence.
1546 ‘The Fundamentals of Digital Semiconductor Testing Principles of Scan Testing
Principles of Scan Testing
-Advanced Topic-
by Vernon Rubright
Objectives:
‘This section explains:
.
.
‘The purpose of scan testing
‘The benefits of scan testing
Device types which benefit from scan testing
Scan test circuitry
Equipment required for scan testing
What is Scan Testing?
Scan testing is a way of decreasing the test development time and test time for certain types of devices. It
depends on designing special test circuits into the devices (called Scan design). Scan design is a structured
design methodology that greatly reduces the complexity of functional test generation. The philosophy is one of
“divide and conquer” and can best be described with reference to the general model for a clocked
(synchronous) logic circuit shown in Figure 16-1.
‘The Fundamentals of Digital Semiconductor Testing 161 |. Principles of Scan Testing
Synchronous Logic Circuit
Feedback makes testing difficult
Secondary State Variables (feedback signals)
sgral Primat
" |———__—> butputts)
Primary — —
Input(s) — | fue}
= a
Combinational Logic _|— — In}
Syste
Sock Memory
Elements
Figure 16-1
In this model, the major elements of the circuit are identified as a combinational logic section together with a
bank of memory elements M1, M2, ... Mn under control of a system clock. Inputs to the combinational logic
consist of the device inputs (Primary Inputs) and the fed back secondary-state variables from the memory
elements. The device outputs (Primary Outputs) are therefore a function of the present state of the device
inputs together with the current states of the memory elements.
‘The future state of the memory elements also depends on both the primary inputs and the current recorded
state of the memory elements themselves. Itis this dependency of the future state on the present state that
causes all the probiems in test generation. The device inputs are the only inputs the test has direct control of
and likewise the device outputs are the only outputs the test can directly observe. The problem is which
section can be tested first since neither section is directly controllable or observable and the sections are
mutually dependent on each other for correct operation.
The scan design methodology provides a solution to this problem by reducing the complexity of the circuit.
Scan designs are based on the principle of providing the following test facilities:
1. All memory elements can be tested in isolation from the rest of the circuit.
2. The future state of the secondary-state variables can be set to any value independent of their present
162 The Fundamentals of Digital Semiconductor Testing Principles of Scan Testing
values
3. The outputs of the combinational logic that drive into the memory elements can be observed directly.
Scan design is implemented by establishing a scan path through the memory elements as shown in Figure 16~
2. Effectively, each memory element is now preceded by a2 way switch (multiplexer) under the control of a
‘common Scan Select signal. When Scan Select is off, the multiplexers connect the outputs from the
combinational logic to the input sides of the memory elements, ie. the circuit functions in its normal mode.
‘When Scan Select ison, the memory elements are reconfigured into an isolated serial-in, serial-out shift
register.
Scan Enabled Synchronous
Logic Circuit
Secondary State Variables (feedback signals)
Primary
Input(s) ——
eS
Combinational Logic
‘Scan Select
Scan Data In
System Clock
Multiplexer
Figure 16-2
‘The serial data input is called Scan Data In and the serial data output is called Scan Data Out. In the scan mode
the memory elements can be preset to any particular set of values simply by placing the values in sequence on.
the Scan Data In input and clocking the shift register with the System Clock. The testing strategy now
becomes:
1. Select the scan-path mode, i.e. memory elements reconfigured into a shift register. Test the status and
operation of each memory element using the Scan Data In, Scan Data Out and System Clock facilities.
Suitable tests for a scan-path register are as follows:
‘The Fundamentals of Digital Semiconductor Testing, 163 % (Principles of Scan Testing
a. FLUSH TEST- In this test all memory elements are initialized to logic 0 and a single logic 1
is clocked through from the Scan Data In input to the Scan Data Out output using the scan
path (system) clock. The procedure can be repeated with a single logic 0 flushed through a
background of logic 1s. This sequence checks the ability of each memory element to assume
both logic states.
b. SHIFT TEST - In this test, the data sequence 00110011. is shifted through the register. This
sequence exercises each memory element through all combinations of present state and
future state.
2. Determine a set of tests for the combinational logic, assuming
a. total control of all inputs (primary and from the memory elements);
b. direct observation of all outputs (primary and to the memory elements).
3. Apply each test in the following way:
‘a. Select scar-path mode. Load the memory elements with test input values and establish addi-
‘tional test input values on the primary inputs.
b, Select normal mode. The steady-state output response of the combinational logic can now be
clocked into the memory elements.
. Return to scan-path mode and clock out the contents of the memory elements. Compare these
values, plus the values directly observable on the primary outputs, with the expected
response.
The philosophy of the scan design can now be seen more clearly. Rather than test the circuit as a single entity,
the addition of the scan path allows each major segment to be tested separately and in a procedural manner.
‘Standard tests can be defined for the memory elements (Step 1. above). The only test-generation problem is to
‘generate tests for the combinational segment. This problem has been well researched and a variety of logic or
fault simulators can be used.
LSSD Technique
A number of circuit design techniques have been developed to implement the scan methodology with Level
Sensitive Scan Design (LSSD), developed by IBM Corp. receiving the most attention. LSSD is specifically
aimed at reducing the dependency of system operation on AC parameters such as clock edge rise or fall times,
which are difficult to simulate in the design environment and difficult to monitor in a manufacturing
environment.
‘The technique provides direct control of two clocks. One clock controls the acceptance of data into the memory
elements while the second clock controls their outputs. With direct clock control the timing of the circuit can be
controlled to avoid potential race conditions resulting from the primary or secondary inputs propagating
through the combinational circuits.
Scan Test Equipment
The total number of memory elements in a VLSI circuit can result ina very long scan path shift register (scan
chain). Memory elements are often divided into multiple scan chains to simplify and speed up testing. Since
scan test patterns are serial representations of the circuit states, it is not uncommon for these patterns to be
millions of vectors long. Standard functional test pattern memory is designed to supply high speed parallel
(pin wide) data and is not cost effective for scan testing.
164 ‘The Fundamentals of Digital Semiconductor Testing Soft] & =
Sof
Principles of Scan Testing Teal &
‘Test equipment designed for scan testing has two functional test pattern memories. One is for parallel (pin
wide) data and another is for serial (scan) data. Each tester channel (pin) can be programmed to use the
parallel or serial test pattem. The serial memory is generally two bits wide (serial data in and out) and can be
configured into multiple depth/ width ratios under program control.
‘The Fundamentals of Digital Semiconductor Testing, 165 Soft|
Test!
166
=
3 a Principies of Scan Testing
‘The Fundamentals of Digital Semiconductor Testing AC Testing,
Assembly
Verification
Bi-directional Pin
Binning
Clamps
‘Comparators
DC Testing,
Device
‘Characterization
Device Specification
DPS
Drivers
DUT
Dynamic Loads
a |
Glossary
Glossary
AC testing guarantees that the device meets all of the timing specifications. AC
testing is performed by setting up the appropriate timing values (edge
placements) and signal formats as defined in the device AC specifications and
then executing a functional test sequence.
Assembly verification is primarily to verify that the devices survived the
assembly process and that they were assembled correctly. The tests performed
during assembly verification are similar to that of package testing and may be a
subset of package testing.
A device pin that functions as an input, an output and is also capable of turning,
off (going to a high impedance state).
‘A means of categorizing or sorting the tested devices into their appropriate
groupings, either hardware bins or software bins.
Hardware which limits the amount of voltage or current that is supplied by the
test system during a test. Clamps are used to protect the test operator, the test
hardware and the DUT.
The circuitry located on the pin electronics card which senses the logic 0 and logic
levels from the DUT. The comparators are used during functional testing.
When a voltage or current is measured during the test and the pass/fail results
are based upon the measured value. The PMU is designed to perform DC tests.
Device Characterization is the process of determining the operating
extremes of devices.
‘The device specification defines the exact performance conditions of the device.
‘The specification includes voltages, currents, timings and a description of the
device functions.
Device Power Supplies are used to supply voltage and current directly to the
DUT. The power pin (VDD or DCC) of the DUT will usually be connected to a
DPS.
‘The circuitry on the pin electronics card which supplies the logic 0 and logic 1
levels to the DUT. A pin is said to be driven ifthe test system driver applies a
voltage toit.
‘The semiconductor device being tested is often referred to as the DUT (Device
Under Test). It is also sometimes referred to as a UUT (Unit Under Test).
A term used to indicate that the DUT is actively changing states, dynamic tests are
associated with executing functional test vectors.
‘The circuitry located on the pin electronics card which acts as a load and can be
programmed to supply positive and negative currents. The dynamic loads can be
used to supply IOL and IOH currents for loading DUT outputs. Dynamic loads
are also referred to as programmable current loads.
‘The Fundamentals of Digital Semiconductor Testing Glossary-1 Forcing
Functional Testing
Gross Testing
Ground
Hot Switching
icc
IDDQ
0H
Incoming Inspection
Input Pin
10 Conflicts
Glossary-2
Failure Analysis isthe process of determining why a device has failed.
Formatted vector data (logic 1s and 0s) combined with timing and signal format
information.
The force line is the current carrying line of a four wire system such as a power
supply. The four wires of a four wire system are the High Force, High Sense, Low
Force and Low Sense. In test systems the Device Power Supply and the Precision
Measurement Unit are four wire systems.
The term force, as in forcing voltage or forcing current, is often used to describe
certain activities during testing, Force is used to describe the act of applying a
certain value of voltage or current by the test system. Apply can be substituted for
the word force.
When the device is actively performing logical functions. Input data is supplied to
the DUT and output data is read from the DUT. The functional comparator