FAN6754A — Highly Integrated Green-Mode PWM Controller

April 2012

FAN6754A
Highly Integrated Green- Mode PWM Controller
Brownout and VLimit Adjustment by HV Pin

Features Description
 High-Voltage Startup The highly integrated FAN6754A PWM controller
provides several features to enhance the performance
 AC Input Brownout Protection with Hysteresis of flyback converters. To minimize standby power
 Monitor HV to Adjust VLimit consumption, a proprietary green-mode function
provides off-time modulation to continuously decrease
 Low Operating Current: 1.5mA the switching frequency under light-load conditions.
 Linearly Decreasing PWM Frequency to 22KHz Under zero-load and very light-load conditions,
 Frequency Hopping to Reduce EMI Emission FAN6754A saves PWM pulses by entering deep burst
mode. This burst mode function enables the power
 Fixed PWM Frequency: 65KHz supply to meet international power conservation
 Peak-Current-Mode Control requirements.
 Cycle-by-Cycle Current Limiting FAN6754A integrates a frequency-hopping function
internally to reduce EMI emission of a power supply with
 Leading-Edge Blanking (LEB) minimum line filters. Built-in synchronized slope
 Internal Open-Loop Protection compensation is accomplished by proprietary HV
monitor to adjust VLimit for constant output power limit
 GATE Output Maximum Voltage Clamp: 13V over universal AC input range. The gate output is
 VDD Under-Voltage Lockout (UVLO) clamped at 13V to protect the external MOSFET from
over-voltage damage.
 VDD Over-Voltage Protection (OVP)
Other protection functions include AC input brownout
 Programmable Over-Temperature Protection (OTP) protection with hysteresis, SENSE pin short-circuit
 Internal Latch Circuit (OVP, OTP) protection, and VDD over-voltage protection. For over-
temperature protection, an external NTC thermistor can
 Open-Loop Protection (OLP); Restart for MR, Latch
be applied to sense the external switcher’s temperature.
for ML
When VDD OVP or OTP are activated, an internal latch
 SENSE Short-Circuit Protection (SSCP) circuit is used to latch-off the controller. The latch mode
 Built-in 8ms Soft-Start Function is reset when the VDD supply is removed.
FAN6754A is available in an 8-pin SOP package.
Applications
General-purpose switch-mode power supplies and Related Resources
flyback power converters, including:
 Evaluation Board: FEBFAN6754AMR_CP450v1
 Power Adapters

Ordering Information

Operating
Part Number Package Packing Method
Temperature Range
FAN6754AMRMY
-40 to +105°C 8-Pin, Small Outline Package (SOP) Tape & Reel
FAN6754AMLMY

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Application Diagram

Figure 1. Typical Application

Internal Block Diagram

HV NC
4 3

OVP SSCP
Line Voltage Latch Re-Start
OTP
Sample Circuit Protection Protection
OLP for ML OLP for MR

Brownout Protection Soft

Driver
8 GATE
HV VLimit Adjustment
Startup

OSC S Q
SSCP
Internal
VDD 7 SSCP Delay
BIAS R 0.05V
UVLO
SSCP
Soft-Start Comparator
Comparator
17V/10V Green Soft-Start
Circuit
Mode Blanking
6 SENSE
Current Limit
Comparator
VLimit
Debounce OVP
PWM
VDD-OVP Comparator

5V
Slope
IRT Compensation
3R
RT 5 2 FB
tD-OTP1
Counter OTP R
OLP OLP
1.05V Delay

tD-OTP2
Counter OLP 4.6V
Comparator
0.7V

1
GND

Figure 2. Functional Block Diagram

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 2
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Marking Information

F - Fairchild Logo
Z - Plant Code
ZXYTT ZXYTT X - 1-Digit Year Code
6754MR 6754ML Y - 1-Digit Week Code
ATPM ATPM TT - 2-Digit Die Run Code
T - Package Type (M=SOP)
P - Y: Package (Green)
M - Manufacture Flow Code

Figure 3. Top Mark

Pin Configuration

SOP-8

GND 1 8 GATE

FB 2 7 VDD

NC 3 6 SENSE

HV 4 5 RT

Figure 4. Pin Configuration (Top View)

Pin Definitions
Pin # Name Description
Ground. This pin is used for the ground potential of all the pins. A 0.1µF decoupling capacitor
1 GND
placed between VDD and GND is recommended.
Feedback. The output voltage feedback information from the external compensation circuit is fed
into this pin. The PWM duty cycle is determined by this pin and the current-sense signal from Pin
2 FB
6. FAN6754A performs open-loop protection (OLP); if the FB voltage is higher than a threshold
voltage (around 4.6V) for more than 56ms, the controller latches off the PWM.
3 NC No Connection
High-Voltage Startup. This pin is connected to the line input via a 1N4007 and 200kΩ resistor to
achieve brownout and high/low line compensation. Once the voltage on the HV pin is lower than
4 HV
the brownout voltage, PWM output turns off. High/low line compensation dominates the cycle-by-
cycle current limiting to achieve constant output power limiting with universal input.
Over-Temperature Protection. An external NTC thermistor is connected from this pin to GND.
The impedance of the NTC decreases at high temperatures. Once the voltage on the RT pin
5 RT drops below the threshold voltage, the controller latches off the PWM. If RT pin is not connected
to NTC resistor for Over-Temperature Protection, a 100KΩ series one resistor is recommended
to ground to prevent from noise interference. This pin is limited by an internal clamping circuit.
Current Sense. This pin is used to sense the MOSFET current for the current-mode PWM and
6 SENSE
current limiting.
Supply Voltage. IC operating current and MOSFET driving current are supplied using this pin.
7 VDD This pin is connected to an external bulk capacitor of typically 47µF. The threshold voltages for
turn-on and turn-off are 17V and 10V, respectively. The operating current is lower than 2mA.
Gate Drive Output. The totem-pole output driver for the power MOSFET. It is internally clamped
8 GATE
below 13V.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 3
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.

Symbol Parameter Min. Max. Unit

(1,2)
VVDD DC Supply Voltage 30 V
VFB FB Pin Input Voltage -0.3 7.0 V
VSENSE SENSE Pin Input Voltage -0.3 7.0 V
VRT RT Pin Input Voltage -0.3 7.0 V
VHV HV Pin Input Voltage 500 V
PD Power Dissipation (TA＜50°C) 400 mW
ΘJA Thermal Resistance (Junction-to-Air) 150 °C/W
TJ Operating Junction Temperature -40 +125 °C
TSTG Storage Temperature Range -55 +150 °C
TL Lead Temperature (Wave Soldering or IR, 10 Seconds) +260 °C
Human Body Model;
4500
Electrostatic Discharge Capability, JESD22-A114
ESD V
All Pins Except HV Pin Charged Device Model;
1500
JESD22-C101
Notes:
1. All voltage values, except differential voltages, are given with respect to the network ground terminal.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
3. ESD with HV pin: CDM=1000V and HBM=500V.

Recommended Operating Conditions

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.

Symbol Parameter Min. Typ. Max. Unit

TA Operating Ambient Temperature -40 +105 °C
RHV HV Startup Resistor 150 200 250 kΩ

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 4
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics
VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

VDD Section
VOP Continuously Operating Voltage 24 V
VDD-ON Start Threshold Voltage 16 17 18 V
VDD-OFF Minimum Operating Voltage 9 10 11 V
VDD-OLP IDD-OLP Off Voltage 5.5 6.5 7.5 V
Threshold Voltage on VDD Pin for
VDD-LH 3.5 4.0 4.5 V
Latch-Off Release Voltage
Threshold Voltage on VDD Pin for
VDD-OFF VDD-OFF VDD-OFF
VDD-AC Disable AC Recovery to Avoid V
+2.8 +3.3 +3.8
Startup Failed
IDD-ST Startup Current VDD-ON – 0.16V 30 µA
Operating Supply Current, VDD=20V, FB=3V Gate
IDD-OP1 1.5 2.0 mA
PWM Operation Open
Operating Supply Current,
IDD-OP2 VDD=20V, FB=3V 1.0 1.5 mA
Gate Stop
Operating Current at PWM-Off
ILH Phase Under Latch-Off VDD=5V 30 60 90 µA
Conduction
Internal Sink Current Under Latch-
IDD-OLP VDD-OLP+0.1V 170 200 230 µA
Off Conduction
VDD-OVP VDD Over-Voltage Protection 24 25 26 V
VDD Over-Voltage Protection
tD-VDDOVP 75 165 255 µs
Debounce Time
HV Section

VAC=90V(VDC=120V),
IHV Supply Current from HV Pin 2.0 3.5 5.0 mA
VDD=0V

HV=700V, VDD=VDD-
IHV-LC Leakage Current after Startup 1 20 µA
OFF+1V

DC Source Series
VAC-OFF Brownout Threshold R=200kΩ to HV Pin 92 102 112 V
See Equation 1
DC Source Series
VAC-ON Brownin Threshold R=200kΩ to HV Pin 104 114 124 V
See Equation 2
DC Source Series
ΔVAC VAC-ON - VAC-OFF 6 12 18 V
R=200kΩ to HV Pin
FB > VFB-N 220
tS-CYCLE Line Voltage Sample Cycle µs
FB < VFB-G 650
tH-TIME Line Voltage Hold Period 20 µs
FB > VFB-N 65 75 85 ms
tD-AC-OFF PWM Turn-off Debounce Time
FB < VFB-G 180 235 290 ms

Continued on page the following page…

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 5
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Figure 5. Brownout Circuit

VIN-ON
VIN-OFF
VIN

Gate
Gate start
Brownout debounce time Gate stop

Figure 6. Brownout Behavior

Figure 7. VDD-AC and AC Recovery

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 6
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
VDD=15V and TA=25°C unless otherwise noted.

Symbol Parameter Conditions Min. Typ. Max. Units

Oscillator Section
Center Frequency 61 65 69
fOSC Frequency in Normal Mode KHz
Hopping Range ±3.7 ±4.2 ±4.7
FB > VFB-N 3.9 4.4 4.9 ms
tHOP Hopping Period
FB=VFB-G 10.2 11.5 12.8 ms
fOSC-G Green-Mode Frequency 19 22 25 KHz
fDV Frequency Variation vs. VDD Deviation VDD=11V to 22V 5 %

fDT Frequency Variation vs. Temperature Deviation TA=-40 to +105°C 5 %

Feedback Input Section

AV Input Voltage to Current-Sense Attenuation 1/4.5 1/4.0 1/3.5 V/V
ZFB Input Impedance 14 16 18 kΩ
VFB-OPEN Output High Voltage FB Pin Open 4.8 5.0 5.2 V
VFB-OLP FB Open-Loop Trigger Level 4.3 4.6 4.9 V
tD-OLP Delay Time of FB Pin Open-Loop Protection 50 56 62 ms
Pin, FB Voltage
2.6 2.8 3.0 V
VFB-N Green-Mode Entry FB Voltage (FB =VFB-N)
Hopping Range ±3.7 ±4.2 ±4.7 kHz
Pin, FB Voltage
2.1 2.3 2.5 V
VFB-G Green-Mode Ending FB Voltage (FB =VFB-G)
Hopping Range ±1.27 ±1.45 ±1.62 kHz
VFB-ZDCR FB Threshold Voltage for Zero-Duty Recovery 1.9 2.1 2.3 V
VFB-ZDC FB Threshold Voltage for Zero-Duty 1.8 2.0 2.2 V

Continued on the following page…

PWM Frequency

fOSC

fOSC-G

VFB-ZDC VFB-ZDCR VFB-G VFB-N VFB

Figure 8. VFB vs. PWM Frequency

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 7
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Electrical Characteristics (Continued)
VDD=15V and TA=25°C unless otherwise noted.
Symbol Parameter Conditions Min. Typ. Max. Unit
s
Current-Sense Section
tPD Delay to Output 100 250 ns
tLEB Leading-Edge Blanking Time 230 280 330 ns
VDC=122V, Series R=200kΩ
VLimit-L Current Limit at Low Line (VAC=86V) 0.43 0.46 0.49 V
to HV
VDC=366V, Series R=200kΩ
VLimit-H Current Limit at High Line (VAC=259V) 0.36 0.39 0.42 V
to HV
VSSCP Threshold Voltage for SENSE Short-Circuit Protection 0.03 0.05 0.07 V
tON-SSCP On Time for VSSCP Checking 4.0 4.4 4.8 µs
tD-SSCP Delay for SENSE Short-Circuit Protection VSENSE<0.05V 60 120 180 µs
tSS Soft-Start Time Startup Time 7 8 9 ms
GATE Section
DCYMAX Maximum Duty Cycle 86 89 92 %
VGATE-L Gate Low Voltage VDD=15V, IO=50mA 1.5 V
VGATE-H Gate High Voltage VDD=12V, IO=50mA 8 V
(4)
IGATE-SINK Gate Sink Current VDD=15V 300 mA
IGATE-
Gate Source Current(4) VDD=15V, GATE=6V 250 mA
SOURCE

tr Gate Rising Time VDD=15V, CL=1nF 100 ns

tf Gate Falling Time VDD=15V, CL=1nF 50 ns
VGATE-
Gate Output Clamping Voltage VDD=22V 9 13 17 V
CLAMP

RT Section
IRT Output Current from RT Pin 92 100 108 µA
0.7V ＜ VRT ＜ 1.05V, after
VRTTH1 1.000 1.035 1.070
Over-Temperature Protection Threshold 12ms Latch Off
V
Voltage VRT ＜ 0.7V, After 100µs
VRTTH2 0.65 0.70 0.75
Latch Off
VRTTH2 ＜ VRT ＜ VRTTH1
14 16 18
FB > VFB-N
tD-OTP1 ms
VRTTH2 ＜ VRT ＜ VRTTH1
Over-Temperature Latch-Off Debounce 40 51 62
FB < VFB-G
VRT< VRTTH2, FB > VFB-N 110 185 260
tD-OTP2 µs
VRT< VRTTH2, FB < VFB-G 320 605 890
Note:
4. Guaranteed by design.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 8
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics

Figure 10. Operation Supply Current (IDD-OP1)

Figure 9. Startup Current (IDD-ST) vs. Temperature
vs. Temperature

Figure 11. Start Threshold Voltage (VDD-ON) Figure 12. Minimum Operating Voltage (VDD-OFF)
vs. Temperature vs. Temperature

Figure 13. Supply Current Drawn from HV Pin (IHV) Figure 14. HV Pin Leakage Current After Startup
vs. Temperature (IHV-LC) vs. Temperature

Figure 15. Frequency in Normal Mode (fOSC) Figure 16. Maximum Duty Cycle (DCYMAX)
vs. Temperature vs. Temperature

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 9
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Typical Performance Characteristics (Continued)

Figure 17. FB Open-Loop Trigger Level (VFB-OLP) Figure 18. Delay Time of FB Pin Open-Loop
vs. Temperature Protection (tD-OLP) vs. Temperature

Figure 19. VDD Over-Voltage Protection (VDD-OVP) Figure 20. Output Current from RT Pin (IRT)
vs. Temperature vs. Temperature

Figure 21. Over-Temperature Protection Threshold Figure 22. Over-Temperature Protection Threshold
Voltage (VRTTH1) vs. Temperature Voltage (VRTTH2) vs. Temperature

Figure 23. Brownin (VAC-ON) vs. Temperature Figure 24. Brownout (VAC-OFF) vs. Temperature

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 10
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Functional Description
Startup Current Gate Output / Soft Driving
For startup, the HV pin is connected to the line input The BiCMOS output stage is a fast totem-pole gate
through an external diode and resistor; RHV, (1N4007 / driver. Cross conduction has been avoided to minimize
200KΩ recommended). Peak startup current drawn from heat dissipation, increase efficiency, and enhance
the HV pin is (VAC× 2 ) / RHV and charges the hold-up reliability. The output driver is clamped by an internal
capacitor through the diode and resistor. When the VDD 13V Zener diode to protect power MOSFET transistors
capacitor level reaches VDD-ON, the startup current against undesirable gate over voltage. A soft driving
switches off. At this moment, the VDD capacitor only waveform is implemented to minimize EMI.
supplies the FAN6754A to keep the VDD until the
auxiliary winding of the main transformer provides the Soft-Start
operating current. For many applications, it is necessary to minimize the
inrush current at startup. The built-in 8ms soft-start
Operating Current circuit significantly reduces the startup current spike and
Operating current is around 1.5mA. The low operating output voltage overshoot.
current enables better efficiency and reduces the
requirement of VDD hold-up capacitance. Slope Compensation
The sensed voltage across the current-sense resistor is
Green-Mode Operation used for peak-current-mode control and cycle-by-cycle
The proprietary green-mode function provides off-time current limiting. Built-in slope compensation improves
modulation to reduce the switching frequency in light- stability and prevents sub-harmonic oscillation.
load and no-load conditions. VFB, which is derived from FAN6754A inserts a synchronized, positive-going, ramp
the voltage feedback loop, is taken as the reference. at every switching cycle.
Once VFB is lower than the threshold voltage (VFB-N), the
switching frequency is continuously decreased to the Constant Output Power Limit
minimum green-mode frequency of around 22KHz. When the SENSE voltage across sense resistor RSENSE
reaches the threshold voltage, around 0.46V for low-line
Current Sensing / PWM Current Limiting condition, the output GATE drive is turned off after a
Peak-current-mode control is utilized to regulate output small delay, tPD. This delay introduces an additional
voltage and provide pulse-by-pulse current limiting. The current proportional to tPD • VIN / LP. Since the delay is
switch current is detected by a sense resistor into the nearly constant regardless of the input voltage VIN,
SENSE pin. The PWM duty cycle is determined by this higher input voltage results in a larger additional current
current-sense signal and VFB, the feedback voltage. and the output power limit is higher than under low input
When the voltage on the SENSE pin reaches around line voltage. To compensate this variation for a wide AC
VCOMP = (VFB–0.6)/4, the switch cycle is terminated input range, a power-limiter is controlled by the HV pin
immediately. VCOMP is internally clamped to a variable to solve the unequal power-limit problem. The power
voltage around 0.46V for low-line output power limit. limiter is fed to the inverting input of the current limiting
comparator. This results in a lower current limit at high-
line inputs than at low-line inputs.
Leading-Edge Blanking (LEB)
Each time the power MOSFET is switched on, a turn-on Brownout and Constant Power Limited by
spike occurs on the sense-resistor. To avoid premature
termination of the switching pulse, a leading-edge the HV Pin
blanking time is built in. During this blanking period, the Unlike previous PWM controllers, FAN6754A’s HV pin
current-limit comparator is disabled and cannot switch can detect the AC line voltage brownout function and
off the gate driver. adjust the current limit. Using a fast diode and startup
resistor to sample the AC line voltage, the peak value
Under-Voltage Lockout (UVLO) refreshes and is stored in a register at each sampling
cycle. When internal update time is met, this peak value
The turn-on and turn-off thresholds are fixed internally at is used for brownout and current-limit level judgment.
17V and 10V, respectively. During startup, the hold-up Equation 1 and 2 calculate the level of brownin or
capacitor must be charged to 17V through the startup brownout converted to RMS value. For power saving,
resistor to enable the IC. The hold-up capacitor FAN6754A enlarges the sampling cycle to lower the
continues to supply VDD until the energy can be power loss from HV sampling at light-load condition.
delivered from auxiliary winding of the main transformer.
VDD must not drop below 10V during startup. This UVLO (RHV +1.6) (1)
VAC- ON (RMS) = ( 0.9V × )/ 2
hysteresis window ensures that hold-up capacitor is 1.6
adequate to supply VDD during startup. VAC - OFF (RMS) = ( 0.81V ×
(RHV +1.6)
)/ 2 (2)
1.6
where RHV is in kΩ.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 11
 FAN6754A — Highly Integrated Green-Mode PWM Controller
The HV pin can perform current limit to shrink the Thermal Protection
tolerance of Over-Current Protection (OCP) under full
An NTC thermistor, RNTC, in series with resistor RA, can
range of AC voltage, to linearly current limit curve, as
be connected from the RT pin to ground. A constant
shown in Figure 25. FAN6754A also shrinks the Vlimit
current, IRT, is output from the RT pin. The voltage on
level by half to lower the I2RSENSE loss to increase the
the RT pin can be expressed as VRT=IRT • (RNTC + RPTC),
heavy-load efficiency.
where IRT is 100µA. At high ambient temperature, RNTC
is smaller, such that VRT decreases. When VRT is less
0.47 than 1.035V (VRTTH1), the PWM turns off after 16ms
0.46 (tD-OTP1). If VRT is less than 0.7V (VRTTH2), the PWM turns
0.45 off after 185µs (tD-OTP2). If the RT pin is not connected to
0.44 NTC resistor for over-temperature protection,
Vlimit (V)

0.43 connecting a series one 100KΩ resistor to ground to

0.42 prevent from noise interference is recommended. This
0.41 pin is limited by an internal clamping circuit.
0.4
0.39
Limited Power Control
0.38
100 120 140 160 180 200 220 240 260 280 300 320 340 360 380 The FB voltage increases every time the output of the
DC Voltage on HV Pin (V) power supply is shorted or overloaded. If the FB voltage
remains higher than a built-in threshold for longer than
tD-OLP, PWM output is turned off. As PWM output is
Figure 25. Linearly Current Limit Curve turned off, VDD begins decreasing.
When VDD goes below the turn-off threshold (10V) the
VDD Over-Voltage Protection (OVP) controller is totally shut down and VDD is continuously
VDD over-voltage protection prevents damage due to discharged to VDD-OLP (6.5V) by IDD-OLP to lower the
abnormal conditions. If the VDD voltage is over the over- average input power. This is called two-level UVLO. VDD
voltage protection voltage (VDD-OVP) and lasts for tD- is cycled again. This protection feature continues as
VDDOVP, the PWM pulses are disabled until VDD drops
long as the overloading condition persists. This prevents
below the UVLO, then starts again. Over-voltage the power supply from overheating due to overloading
conditions are usually caused by open feedback loops. conditions.

Noise Immunity
Sense-Pin Short-Circuit Protection
Noise on the current sense or control signal may cause
The FAN6754A provides safety protection for Limited significant pulse-width jitter, particularly in continuous-
Power Source (LPS) tests. When the sense resistor is conduction mode. Slope compensation helps alleviate
shorted by soldering during production, the pulse-by- this problem. Good placement and layout practices
pulse current limiting loses efficiency for the purpose of should be followed. Avoiding long PCB traces and
providing over-power protection for the unit. The unit component leads, locating compensation and filter
may be damaged when the loading is larger than the components near the FAN6754A, and increasing the
maximum load. To protect against a short circuit across power MOS gate resistance improve performance.
the current-sense resistor, the controller is designed to
immediately shut down if a continuously low voltage
(around 0.05V/120µs) on the SENSE pin is detected.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 12
 FAN6754A — Highly Integrated Green-Mode PWM Controller
Physical Dimensions

5.00
4.80 A
0.65
3.81
8 5
B

6.20 1.75
5.80 4.00 5.60
3.80

PIN ONE 1 4
INDICATOR
1.27
(0.33) 1.27
0.25 M C B A
LAND PATTERN RECOMMENDATION

0.25 SEE DETAIL A

0.10
0.25
1.75 MAX C
0.19
0.51 0.10 C

0.33 OPTION A - BEVEL EDGE

0.50 x 45°
0.25
R0.10 GAGE PLANE

R0.10 0.36
OPTION B - NO BEVEL EDGE

NOTES: UNLESS OTHERWISE SPECIFIED

8°
0° A) THIS PACKAGE CONFORMS TO JEDEC
MS-012, VARIATION AA, ISSUE C,
0.90 SEATING PLANE B) ALL DIMENSIONS ARE IN MILLIMETERS.

0.406 (1.04) C) DIMENSIONS DO NOT INCLUDE MOLD

FLASH OR BURRS.
DETAIL A D) LANDPATTERN STANDARD: SOIC127P600X175-8M.
SCALE: 2:1 E) DRAWING FILENAME: M08AREV13

Figure 26. 8-Pin Small Outline Package (SOP) Package

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.

© 2011 Fairchild Semiconductor Corporation www.fairchildsemi.com

FAN6754A • Rev. 1.0.3 13
 FAN6754A— Highly Integrated Green-Mode PWM Controller

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FAN6754A • Rev. 1.0.3 14
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