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UNIT I COMBINATIONAL LOGIC

Combinational Circuits – Karnaugh Map − Analysis and Design Procedures – Binary Adder – Subtractor –
Decimal Adder − Magnitude Comparator – Decoder – Encoder – Multiplexers − Demultiplexers

COMBINATIONAL CIRCUITS:

Combinational circuit is a circuit in which we combine the different gates in the circuit, for example
encoder, decoder, multiplexer and demultiplexer. Some of the characteristics of combinational
circuits are following −
 The output of combinational circuit at any instant of time, depends only on the levels present
at input terminals.
 The combinational circuit do not use any memory. The previous state of input does not have
any effect on the present state of the circuit.
 A combinational circuit can have an n number of inputs and m number of outputs.

BLOCK DIAGRAM

BINARY ADDER:

 The Add micro-operation requires registers that can hold the data and the digital components
that can perform the arithmetic addition.
 A Binary Adder is a digital circuit that performs the arithmetic sum of two binary numbers
provided with any length.
 A Binary Adder is constructed using full-adder circuits connected in series, with the output
carry from one full-adder connected to the input carry of the next full-adder.

HALF ADDER:

Half adder is a combinational logic circuit with two inputs and two outputs. The half adder circuit is
designed to add two single bit binary number A and B. It is the basic building block for addition of
two single bit numbers. This circuit has two outputs carry and sum.
BLOCK DIAGRAM:
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TRUTH TABLE:

CIRCUIT DIAGRAM:

FULL ADDER:

Full adder is developed to overcome the drawback of Half Adder circuit. It can add two one-bit
numbers A and B, and carry c. The full adder is a three input and two output combinational circuit.
Block diagram

Truth Table
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Circuit Diagram

The following block diagram shows the interconnections of four full-adder circuits to provide a 4-bit
binary adder.

o The augend bits (A) and the addend bits (B) are designated by subscript numbers from right
to left, with subscript '0' denoting the low-order bit.
o The carry inputs starts from C0 to C3 connected in a chain through the full-adders. C4 is the
resultant output carry generated by the last full-adder circuit.
o The output carry from each full-adder is connected to the input carry of the next-high-order
full-adder.
o The sum outputs (S0 to S3) generates the required arithmetic sum of augend and addend bits.
o The n data bits for the A and B inputs come from different source registers. For instance, data
bits for A input comes from source register R1 and data bits for B input comes from source
register R2.
o The arithmetic sum of the data inputs of A and B can be transferred to a third register or to
one of the source registers (R1 or R2).
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HALF SUBTRACTORS:

Half subtractor is a combination circuit with two inputs and two outputs (difference and borrow). It
produces the difference between the two binary bits at the input and also produces an output
(Borrow) to indicate if a 1 has been borrowed. In the subtraction (A-B), A is called as Minuend bit
and B is called as Subtrahend bit.
Truth Table:

Circuit Diagram:

Full Subtractors:

The disadvantage of a half subtractor is overcome by full subtractor. The full subtractor is a
combinational circuit with three inputs A,B,C and two output D and C'. A is the 'minuend', B is
'subtrahend', C is the 'borrow' produced by the previous stage, D is the difference output and C' is the
borrow output.
Truth Table
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Circuit Diagram

N-Bit Parallel Subtractor:

The subtraction can be carried out by taking the 1's or 2's complement of the number to be
subtracted. For example we can perform the subtraction (A-B) by adding either 1's or 2's complement
of B to A. That means we can use a binary adder to perform the binary subtraction.
4 Bit Parallel Subtractor:
The number to be subtracted (B) is first passed through inverters to obtain its 1's complement. The 4-
bit adder then adds A and 2's complement of B to produce the subtraction. S 3 S2 S1 S0 represents the
result of binary subtraction (A-B) and carry output C out represents the polarity of the result. If A > B
then Cout = 0 and the result of binary form (A-B) then Cout = 1 and the result is in the 2's
complement form.
Block diagram:
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DECIMAL OR BCD ADDER

The BCD-Adder is used in the computers and the calculators that perform arithmetic operation
directly in the decimal number system. The BCD-Adder accepts the binary-coded form of decimal
numbers. The Decimal-Adder requires a minimum of nine inputs and five outputs.

In the above
diagram,

1. We take a 4-bit Binary-Adder, which takes addend and augend bits as an input with an input
carry 'Carry in'.
2. The Binary-Adder produces five outputs, i.e., Z8, Z4, Z2, Z1, and an output carry K.
3. With the help of the output carry K and Z8, Z4, Z2, Z1 outputs, the logical circuit is designed
to identify the Cout
4. The Z8, Z4, Z2, and Z1 outputs of the binary adder are passed into the 2 nd 4-bit binary adder
as an Augend.
5. The addend bit of the 2nd 4-bit binary adder is designed in such a way that the 1st and the
4th bit of the addend number are 0 and the 2nd and the 3rd bit are the same as Cout. When the
value of Cout is 0, the addend number will be 0000, which produce the same result as the 1 st 4-
bit binary number. But when the value of the C out is 1, the addend bit will be 0110, i.e., 6,
which adds with the augent to get the valid BCD number.
Example: 1001+1000

1. First, add both the numbers using a 4-bit binary adder and pass the input carry to 0.
2. The binary adder produced the result 0001 and carried output 'K' 1.
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3. Then, find the Cout value to identify that the produced BCD is invalid or valid using the
expression
Cout=K+Z8.Z4+Z8.Z2.
K=1
Z8 = 0

Z4 =0
Z2 =0
Cout =1+0*0+0*0
Cout =1+0+0
Cout = 1

4. The value of Cout is 1, which expresses that the produced BCD code is invalid. Then, add the
output of the 1st 4-bit binary adder with 0110.
= 0001+0110
= 0111
5. The BCD is represented by the carry output as:
BCD=Cout Z8 Z4 Z2 Z1=1 0 1 1 1

DECODER

The combinational circuit that change the binary information into 2N output lines is known
as Decoders. The binary information is passed in the form of N input lines. The output lines define
the 2N-bit code for the binary information. In simple words, the Decoder performs the reverse
operation of the Encoder. At a time, only one input line is activated for simplicity. The produced 2 N-
bit output code is equivalent to the binary information.

There are various types of decoders which are as follows:

2 to 4 line decoder:

In the 2 to 4 line decoder, there is a total of three inputs, i.e., A 0, and A1 and E and four outputs, i.e.,
Y0, Y1, Y2, and Y3. For each combination of inputs, when the enable 'E' is set to 1, one of these four
outputs will be 1. The block diagram and the truth table of the 2 to 4 line decoder are given below.
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Block Diagram:

Truth Table:

The logical expression of the term Y0, Y0, Y2, and Y3 is as follows:

Y3=E.A1.A0
Y2=E.A1.A0'
Y1=E.A1'.A0
Y0=E.A1'.A0'

Logical circuit of the above expressions is given below:

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3 to 8 line decoder:

The 3 to 8 line decoder is also known as Binary to Octal Decoder. In a 3 to 8 line decoder, there is a
total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2.
This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E' is set to 1, one of
these four outputs will be 1. The block diagram and the truth table of the 3 to 8 line encoder are
given below.

Block Diagram:

Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
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Y0=A0'.A1'.A2'
Y1=A0.A1'.A2'
Y2=A0'.A1.A2'
Y3=A0.A1.A2'
Y4=A0'.A1'.A2
Y5=A0.A1'.A2
Y6=A0'.A1.A2
Y7=A0.A1.A2

Logical circuit of the above expressions is given below:

4 to 16 line Decoder

In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y 0, Y1, Y2,……, Y16 and four inputs,
i.e., A0, A1, A2, and A3. The 3 to 16 line decoder can be constructed using either 2 to 4 decoder or 3
to 8 decoder. There is the following formula used to find the required number of lower-order
decoders.

Required number of lower order decoders=m2/m1

m1 = 8
m2 = 16

Required number of 3 to 8 decoders= =2

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Block Diagram:

Truth Table:

The logical expression of the term A0, A1, A2,…, A15 are as follows:
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Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3

Logical circuit of the above expressions is given below:

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ENCODERS

The combinational circuits that change the binary information into N output lines are known
as Encoders. The binary information is passed in the form of 2N input lines. The output lines define
the N-bit code for the binary information. In simple words, the Encoder performs the reverse
operation of the Decoder. At a time, only one input line is activated for simplicity. The produced N-
bit output code is equivalent to the binary information.

There are various types of encoders which are as follows:

4 to 2 line Encoder:

In 4 to 2 line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and two outputs, i.e.,
A0 and A1. In 4-input lines, one input-line is set to true at a time to get the respective binary code in
the output side. Below are the block diagram and the truth table of the 4 to 2 line encoder.

Block Diagram:

Truth Table:
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The logical expression of the term A0 and A1 is as follows:

A1=Y3+Y2
A0=Y3+Y1

Logical circuit of the above expressions is given below:

8 to 3 line Encoder:

The 8 to 3 line Encoder is also known as Octal to Binary Encoder. In 8 to 3 line encoder, there is a
total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 and three outputs, i.e., A0, A1, and A2. In
8-input lines, one input-line is set to true at a time to get the respective binary code in the output side.
Below are the block diagram and the truth table of the 8 to 3 line encoder.

Block Diagram:
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Truth Table:

The logical expression of the term A0, A1, and A2 are as follows:
A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1

Logical circuit of the above expressions is given below:

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Decimal to BCD Encoder:

The Octal to Binary Encoder is also known as 10 to 4 line Encoder. In 10 to 4 line encoder, there are
total of ten inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, and Y9 and four outputs, i.e., A0, A1, A2,
and A3. In 10-input lines, one input-line is set to true at a time to get the respective BCD code in the
output side. The block diagram and the truth table of the decimal to BCD encoder are given below.

Block Diagram:

Truth Table:

The logical expression of the term A0, A1, A2, and A3 is as follows:

A3 = Y9 + Y8
A2 = Y7 + Y6 + Y5 +Y4
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A1 = Y7 + Y6 + Y3 +Y2
A0 = Y9 + Y7 +Y5 +Y3 + Y1

Logical circuit of the above expressions is given below:

Priority Encoder:

4 to 2 line Priority Encoder:

In this priority encoder, there are total of 4 inputs, i.e., Y0, Y1, Y2, and Y3, and two outputs, i.e.,
A0 and A1. The Y3 has high and Y0 has low priority inputs. When more than one input is '1' at the
same time, the output will be the (binary) code corresponding to the higher priority input. Below is
the truth table of the 4 to 2 line priority encoder.

Truth Table:

The logical expression of the term A0 and A1 can be found using K-map as:
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A1=Y3+Y2
A0=Y3+Y2'.Y1

Logical circuit of the above expressions is given below:

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Uses of Encoders:

1. These systems are very easy to use in all digital systems.

2. Encoders are used to convert a decimal number into the binary number. The objective is to
perform a binary operation such as addition, subtraction, multiplication, etc
3.
Next →← Prev

Multiplexer
A multiplexer is a combinational circuit that has 2 n input lines and a single output line. Simply,
the multiplexer is a multi-input and single-output combinational circuit. The binary information
is received from the input lines and directed to the output line. On the basis of the values of the
selection lines, one of these data inputs will be connected to the output.
Unlike encoder and decoder, there are n selection lines and 2n input lines. So, there is a total of
2N possible combinations of inputs. A multiplexer is also treated as Mux.
There are various types of the multiplexer which are as follows:

2×1 Multiplexer:
In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line, i.e., S0 and
single outputs, i.e., Y. On the basis of the combination of inputs which are present at the
selection line S0, one of these 2 inputs will be connected to the output. The block diagram and

the truth table of the 2×1 multiplex given below.

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1

Logical circuit of the above expression is given below:

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4×1 Multiplexer:

In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2 selection lines,
i.e., S0 and S1 and single output, i.e., Y. On the basis of the combination of inputs that are present
at the selection lines S0 and S1, one of these 4 inputs are connected to the output. The block
diagram and the truth table of the 4×1 multiplexer are given below.

Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3

Logical circuit of the above expression is given below:

8 to 1 Multiplexer

In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5, A6, and A7, 3
selection lines, i.e., S0, S1and S2 and single output, i.e., Y. On the basis of the combination of
inputs that are present at the selection lines S0, S1, and S2, one of these 8 inputs are connected to
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the output. The block diagram and the truth table of the 8×1 multiplexer are given below.

Block Diagram:

Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.S2 .A6+

S0.S1.S3.A7

Logical circuit of the above expression is given below:

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8 ×1 multiplexer using 4×1 and 2×1 multiplexer

We can implement the 8×1 multiplexer using a lower order multiplexer. To implement the 8×1
multiplexer, we need two 4×1 multiplexers and one 2×1 multiplexer. The 4×1 multiplexer has 2
selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1 selection line.

For getting 8 data inputs, we need two 4×1 multiplexers. The 4×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of 8×1
multiplexer using 4×1 and 2×1 multiplexer is given below.
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16 to 1 Multiplexer

In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A 0, A1, …, A16, 4 selection lines, i.e.,
S0, S1, S2, and S3 and single output, i.e., Y. On the basis of the combination of inputs that are
present at the selection lines S0, S1, and S2, one of these 16 inputs will be connected to the output.
The block diagram and the truth table of the 16×1

Block Diagram:

Truth Table:
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The logical expression of the term Y is as follows:

Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+A5.S0 '.S1

.S2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+Y10.S0.S1'.S2.S3 '+A11.S0.S
1'.S2.S3+A12 S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3'+A15.S0.S1.S2'.S3

Logical circuit of the above expression is given below:

16×1 multiplexer using 8×1 and 2×1 multiplexer

We can implement the 16×1 multiplexer using a lower order multiplexer. To implement the 8×1
multiplexer, we need two 8×1 multiplexers and one 2×1 multiplexer. The 8×1 multiplexer has 3
selection lines, 4 inputs, and 1 output. The 2×1 multiplexer has only 1 selection line.
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For getting 16 data inputs, we need two 8 ×1 multiplexers. The 8×1 multiplexer produces one
output. So, in order to get the final output, we need a 2×1 multiplexer. The block diagram of
16×1 multiplexer using 8×1 and 2×1 multiplexer is given below.

De-multiplexer

A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines. Simply,
the multiplexer is a single-input and multi-output combinational circuit. The information is
received from the single input lines and directed to the output line. On the basis of the values of
the selection lines, the input will be connected to one of these outputs. De-multiplexer is opposite
to the multiplexer.
Unlike encoder and decoder, there are n selection lines and 2n outputs. So, there is a total of
2n possible combinations of inputs. De-multiplexer is also treated as De-mux.
There are various types of De-multiplexer which are as follows:

1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1 selection lines, i.e., S0,
and single input, i.e., A. On the basis of the selection value, the input will be connected to one of
the outputs. The block diagram and the truth table of the 1×2 multiplexer are given below.
Block Diagram:
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Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A
Logical circuit of the above expressions is given below:

1×4 De-multiplexer:

In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection lines, i.e.,
S0 and S1 and single input, i.e., A. On the basis of the combination of inputs which are present at the
selection lines S0 and S1, the input be connected to one of the outputs. The block diagram and the
truth table of the 1×4 multiplexer are given below.

Block Diagram:

Truth Table:
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The logical expression of the term Y is as follows:

Y0=S1' S0' A
y1=S1' S0 A
y2=S1 S0' A
y3=S1 S0 A

Logical circuit of the above expressions is given below:

1×8 De-multiplexer

In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7, 3
selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S0, S1 and S2, the input will be connected to one of these
outputs. The block diagram and the truth table of the 1×8 de-multiplexer are given below.

Block Diagram:
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Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2 A
Y5=S0.S1'.S2 A
Y6=S0'.S1.S2 A
Y7=S0.S1.S3.A

Logical circuit of the above expressions is given below:

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1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer

We can implement the 1×8 de-multiplexer using a lower order de-multiplexer. To implement the 1×8
de-multiplexer, we need two 1×4 de-multiplexer and one 1×2 de-multiplexer. The 1×4 multiplexer
has 2 selection lines, 4 outputs, and 1 input. The 1×2 de-multiplexer has only 1 selection line.

For getting 8 data outputs, we need two 1×4 de-multiplexer. The 1×2 de-multiplexer produces two
outputs. So, in order to get the final output, we have to pass the outputs of 1×2 de-multiplexer as an
input of both the 1×4 de-multiplexer. The block diagram of 1×8 de-multiplexer using 1×4 and 1×2
de-multiplexer is given below.
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1 x 16 De-multiplexer

In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y0, Y1, …, Y16, 4 selection lines, i.e., S0,
S1, S2, and S3 and single input, i.e., A. On the basis of the combination of inputs which are present at
the selection lines S0, S1, and S2, the input will be connected to one of these outputs. The block
diagram and the truth table of the 1×16 de-multiplexer are given below.

Block Diagram:
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Truth Table:

The logical expression of the term Y is as follows:

Y0=A.S0'.S1'.S2'.S3'
Y1=A.S0'.S1'.S2'.S3
Y2=A.S0'.S1'.S2.S3'
Y3=A.S0'.S1'.S2.S3
Y4=A.S0'.S1.S2'.S3'
Y5=A.S0'.S1.S2'.S3
Y6=A.S0'.S1.S2.S3'
Y7=A.S0'.S1.S2.S3
Y8=A.S0.S1'.S2'.S3'
Y9=A.S0.S1'.S2'.S3
Y10=A.S0.S1'.S2.S3'
Y11=A.S0.S1'.S2.S3
Y12=A.S0.S1.S2'.S3'
Y13=A.S0.S1.S2'.S3
Y14=A.S0.S1.S2.S3'
Y15=A.S0.S1.S2'.S3

Logical circuit of the above expressions is given below:

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1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer

We can implement the 1×16 de-multiplexer using a lower order de-multiplexer. To implement the
1×16 de-multiplexer, we need two 1×8 de-multiplexer and one 1×2 de-multiplexer. The 1×8
multiplexer has 3 selection lines, 1 input, and 8 outputs. The 1×2 de-multiplexer has only 1 selection
line.

For getting 16 data outputs, we need two 1×8 de-multiplexer. The 1×8 de-multiplexer produces eight
outputs. So, in order to get the final output, we need a 1×2 de-multiplexer to produce two outputs
from a single input. Then we pass these outputs into both the de-multiplexer as an input. The block
diagram of 1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer is given below.
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Magnitude Comparator in Digital Logic

 Difficulty Level : Easy
A magnitude digital Comparator is a combinational circuit that compares two digital or binary
numbers in order to find out whether one binary number is equal, less than, or greater than the
other binary number. We logically design a circuit for which we will have two inputs one for A
and the other for B and have three output terminals, one for A > B condition, one for A = B
condition, and one for A < B condition.

1- Bit Magnitude Comparator:

A comparator used to compare two bits is called a single-bit comparator. It consists of two inputs
each for two single-bit numbers and three outputs to generate less than, equal to, and greater than
between two binary numbers.
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The truth table for a 1-bit comparator is given below:

From the above truth table logical expressions for each output can be expressed as follows:
A>B: AB'
A<B: A'B
A=B: A'B' + AB
From the above expressions we can derive the following formula:

By using these Boolean expressions, we can implement a logic circuit for this comparator as given

below:
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2- Bit Magnitude Comparator:

A comparator used to compare two binary numbers each of two bits is called a 2-bit Magnitude
comparator. It consists of four inputs and three outputs to generate less than, equal to, and greater
than between two binary numbers.
The truth table for a 2-bit comparator is given below:

From the above truth table K-map for each output can be drawn as follows:
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From the above K-maps logical expressions for each output can be expressed as follows:
A>B:A1B19 + A0B19B09 + A1A0B09
A=B: A19A09B19B09 + A19A0B19B0 + A1A0B1B0 + A1A09B1B09
: A19B19 (A09B09 + A0B0) + A1B1 (A0B0 + A09B09)
: (A0B0 + A09B09) (A1B1 + A19B19)
: (A0 Ex-Nor B0) (A1 Ex-Nor B1)
A<B:A19B1 + A09B1B0 + A19A09B0
By using these Boolean expressions, we can implement a logic circuit for this comparator as given
below:
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4-Bit Magnitude Comparator:

A comparator used to compare two binary numbers each of four bits is called a 4 -bit magnitude
comparator. It consists of eight inputs each for two four-bit numbers and three outputs to generate
less than, equal to, and greater than between two binary numbers.
In a 4-bit comparator the condition of A>B can be possible in the following four cases:

1. If A3 = 1 and B3 = 0
2. If A3 = B3 and A2 = 1 and B2 = 0
3. If A3 = B3, A2 = B2 and A1 = 1 and B1 = 0
4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 1 and B0 = 0
Similarly the condition for A<B can be possible in the following four cases:
1. If A3 = 0 and B3 = 1
2. If A3 = B3 and A2 = 0 and B2 = 1
3. If A3 = B3, A2 = B2 and A1 = 0 and B1 = 1
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4. If A3 = B3, A2 = B2, A1 = B1 and A0 = 0 and B0 = 1

The condition of A=B is possible only when all the individual bits of one number exactly coincide
with corresponding bits of another number.
From the above statements logical expressions for each output can be expressed as follows:
AA, 831331 r: (A3 EioNor 33)A2132′ a (A3 Ex-Nor 133) (A2 Ex-Nor 132)A131′ a (A3 Ex-Nor
33) (A2 ENor132) (Al Ex-Nor 31)A01301
,13: A3903 a (A3 Ex-Nor 33)A211:12 a (A3 Ex-Nor 83) (A2 Ex-Nor 132)Ar131 a (A3 Ex-Nor 33)
(A2 Ex-Nor32) (Al Ex-Nor 131)A0N30
A=B: (A3 Ex-Nor B3) (A2 Ex-Nor 82) (Al Ex-Nor BI) (AO Ex-Nor BO)
By using these Boolean expressions, we can implement a logic circuit for this comparator as given
below:

NOTE:

For n- the bit comparator then, the number of combinations for which
 A = B is 2n

 A > B or A < B is (22n – 2n)/2

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Cascading Comparator:

A comparator performing the comparison operation to more than four bits by cascading two or
more 4-bit comparators is called a cascading comparator. When two comparators are to be
cascaded, the outputs of the lower-order comparator are connected to corresponding inputs of the
higher-order comparator.

Applications of Comparators:

1. Comparators are used in central processing units (CPUs) and microcontrollers (MCUs).
2. These are used in control applications in which the binary numbers representing physical
variables such as temperature, position, etc. are compared with a reference value.
3. Comparators are also used as process controllers and for Servo motor control.
4. Used in password verification and biometric applications.

KARNAUGH MAP (K-MAP)

Karnaugh Map usually abbreviated as K-map is a systematic approach used for simplifying Boolean
expressions or logic functions. It is majorly used method for minimizing the Boolean expressions. K
map is basically known to be a different method for the representation of truth table.
The Karnaugh map (K map) according to the variables involved can be either 1, 2, 3 or 4
variables. The number of cells for K-maps in case of different variables will be identified by:

where n is the total number of variables.

So, in case of one variable K-map, n will be equal to 1, thus the number of cells in 1 variable K-map
will be 2. Similarly, for two variable K-map, n will be 2, hence a number of cells, in this case, will be
4. Also, for 3 variable K-map, the number of cells will be 8 and for n equals to 4, the number of cells
will be 16.
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Rules to draw Karnaugh Map

We know that K-map is used for simplification of Boolean expressions. However, some rules are
associated whenever a K-map is plotted. The rules are given below:

 In K-map while adding binary terms according to the variables assigned, no 2 variables of
adjacent columns can be changed simultaneously.
Have a look at the example of 3 variable K-map shown below:

Here, as we can see that in the third column 11 is represented while in 4th column 10 is shown. This
is so because as we have written 01 in the 2nd column. And if we write 10 in the 3rd column then
simultaneously 2 variables will get changed. As 0 changes to 1 and 1 changes to 0 simultaneously.
This is the reason why m2 is assigned at the rightmost column of the 1st row and m3 is placed before
m2. In a similar way, m6 is present after m7.
 When a minterm K-map is designed then, in this condition, 1 is assigned at all those cells for
which the output is 1, while 0 is provided at those cells where output is 0. But sometimes for
simplicity, these 09s is omitted and the cells are kept vacant in the case when 0 is required to
be filled.
The condition is reversed at the time of designing a maxterm K-map. Here 1 is assigned to the cell in
case of 0 at the output and 0 is assigned in case of 1 at the output.

 While assigning the don9t care conditions to the cells of the K-map, 8X9 or 8d9 is placed at the
respective cell.
 At the time of grouping of bits inside the K-map, the highest priority is provided to a group of
16, further the priority decreases with 8, 4 and 2 bits9 pair.
 The rule of adjacency is highly followed while pairing the bits inside the Karnaugh map. This is
the reason; diagonal pairing is not performed in K-map.
Let us move further and understand the 3 and 4 variables K-map by some examples.
Karnaugh Map for 3 Variables
Suppose that we have to simplify a 3 variable Boolean expression using K map.

We know that the number of cells of the K-map is dependent on the number of variables. So, for 3
variable K map, the number of cells will be 23 i.e., 8.
Let us reduce the function given below using K-map

F (A, B, C) = Σm (0, 1, 2, 4, 7)
The figure below represents the K-map for 3 variables having 8 cells.
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As we have already discussed earlier the reason behind the assigning of variables to the Karnaugh
map. So, let us now proceed towards filling of bits to the minterm K-map.

The figure below shows the assigning of bits to the K-map:

Here, we can clearly see that for minterm K-map, 1 is assigned at m0, m1, m2, m4, m7, as given in the
function.
So, firstly here we will check the priority, as we can see that neither 16, 8 nor 4 19s is present in order
to perform the grouping. So, we will check for grouping of 2 bits.

The figure below represents the grouping of bits for the above function:
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Here, we can see that two 1, present at the 1st row of column 00 and 01 are forming pair. Similarly,
two 19s of the first column and rows 0, 1 are forming a pair. Also, the two corners, 1 at the first
row is forming a group of 1.
However, still, a single 1 is left that is unable to participate in a grouping as no other 1 is present at
its adjacent position. So, this 1 is considered to be as a group of single 1. As represented in the figure
given above.

Let us now see how the above function is realized using K-map.
So, the function for all 4 implicants will be:

So, combinely the realized Boolean expression will be given as:

Let us take another example to have a better understanding of the same.

F (A, B, C) = Σm (1, 3, 6, 7)
Let9s have a look at the figure below that represents the placement of bits inside the K-map:

The grouping of the bits is shown in the figure below:

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Here also, neither a group of 8 nor of 4 is forming. Thus 3 implicants can be formed by grouping as
shown in the figure above.

Thus the function will be:

But a noteworthy point is that here redundancy of bit is generating. This is so because the two 19s
present at BC position is already grouped individually with their adjacent bit. The pairing of two
different bits which are separately paired comes under redundancy theorem.

So, in this case, the implicant BC will be ignored. And the realized Boolean expression will be:

Let us now proceed to understand how 4 variable K-map gets realized.

Karnaugh map for 4 variables
In case of realizing 4 variable K-map, the number of cells will be 24 i.e., 16. At the time of assigning
variable to the 4 Χ 4 K-map, again the thing that is to be kept in mind is no two variables can be
changed simultaneously.
As we have done by swapping the variables of 3rd and 4th column in the 3 variable K-map.
The figure below represents a Karnaugh map for 4 variables:

Suppose the function to be realized is given as:

F (A, B, C, D) = Σm (0, 2, 3, 7, 11, 13, 14, 15)

The figure below represents the bit assigning to the 4 variable K-map:
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Here it is clear from the above figure that 1 is placed at m0, m2, m3, m7, m11, m13, m14, m15.
Now, after the bits get assigned, the grouping is performed. So, again the grouping is done according
to their priority.

As we can see that no combination of 8 bits is present in a way to form a group. However, then a
group of 4 19s is formed. Similarly, the two 19s at the corners of the 1st row are grouped
together. The figure here shows the grouping of bits for the 4 variable functions:

So, the above K-map can be realized as:

Hence the combined realized Boolean expression for the above K-map will be
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Don9t Care Condition in Karnaugh Map

Till now we have discussed the conditions where the desired output is generated according to some
input conditions. But there exist some cases in which the output remains unspecified because of
invalid input conditions.

These outputs are denoted as 8d9 or Χ in the K-map and are known as don’t care condition.
Basically whenever these don9t care terms are represented in the K-map then these are utilized in the
realization of Boolean expression if required. Otherwise, these are ignored.
Let us now take an example of a function with 4 variables with don9t care condition.
Suppose the function be:
F (A, B, C, D) = Σm (1, 3, 7, 11, 15) + Σd (0, 2, 4)
So, for the above function the designed K-map is shown below:

Here as we can see clearly that at cell position, m0, m2, m4 8d9 are placed representing the don9t
care condition. However, we have already discussed that in the case of SOP realization these 8d9
can be considered at the time of grouping.
Thus the grouping inside the K-map can be done in a way shown below:

Here, by making use of don9t care terms, 2 groups of 4 can be formed. Or we can say 2 quads are
formed.

So, the realized function is given as