TLC556, TLC556Y

DUAL LinCMOS TIMERS

SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

D Very Low Power Consumption . . . 2 mW D, J, OR N PACKAGE

Typ at VDD = 5 V (TOP VIEW)
D Capable of Operation in Astable Mode
D CMOS Output Capable of Swinging Rail to
1 DISCH
1 THRES
1 14 VDD
2 DISCH
2 13
Rail
1 CONT 2 THRES
D High Output-Current Capability 1 RESET
3
4
12
11 2 CONT
Sink 100 mA Typ 1 OUT 2 RESET
5 10
Source 10 mA Typ 1 TRIG 2 OUT
6 9
D Output Fully Compatible With CMOS, TTL, GND 7 8 2 TRIG
and MOS
D Low Supply Current Reduces Spikes FK PACKAGE
During Output Transitions (TOP VIEW)
D Single-Supply Operation From 2 V to 15 V

1 THRES
D

1 DISCH

2 DISCH
Functionally interchangeable With the

V DD
NE556; Has Same Pinout

NC
description
3 2 1 20 19
1 CONT 4 18 2 THRES
The TLC556 series are monolithic timing circuits
NC 5 17 NC
fabricated using the TI LinCMOS process, which
1 RESET 6 16 2 CONT
provides full compatibility with CMOS, TTL, and
NC 7 15 NC
MOS logic and operates at frequencies up to
1 OUT 8 14 2 RESET
2 MHz. Accurate time delays and oscillations are 9 10 11 12 13
possible with smaller, less-expensive timing

2 OUT
1 TRIG

NC
2 TRIG
GND
capacitors than the NE556 because of the high
input impedance. Power consumption is low
across the full range of power supply voltages.
Like the NE556, the TLC556 has a trigger level NC–No internal connection
approximately one-third of the supply voltage and
a threshold level approximately two-thirds of the supply voltage. These levels can be altered by use of the control
voltage terminal. When the trigger input falls below the trigger level, the flip-flop is set and the output goes high.
If the trigger input is above the trigger level and the threshold input is above the threshold level, the flip-flop is
reset and the output is low. The reset input can override all other inputs and can be used to initiate a new timing
cycle. If the reset input is low, the flip-flop is reset and the output is low. Whenever the output is low, a
low-impedance path is provided between the discharge terminal and ground.
While the CMOS output is capable of sinking over 100 mA and sourcing over 10 mA, the TLC556 exhibits greatly
reduced supply-current spikes during output transitions. This minimizes the need for the large decoupling
capacitors required by the NE556.
These devices have internal electrostatic-discharge (ESD) protection circuits that prevent catastrophic failures
at voltages up to 2000 V as tested under MIL-STD-883C, Method 3015. However, care should be exercised in
handling these devices, as exposure to ESD may result in degradation of the device parametric performance.
All unused inputs should be tied to an appropriate logic level to prevent false triggering.
The TLC556C is characterized for operation from 0°C to 70°C. The TLC556I is characterized for operation from
– 40°C to 85°C. The TLC556M is characterized for operation over the full military temperature range of – 55°C
to 125°C.

LinCMOS is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date. Copyright  1997, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

AVAILABLE OPTIONS
PACKAGE
TA VDD CHIP FORM
SMALL OUTLINE CHIP CARRIER CERAMIC DIP PLASTIC DIP
RANGE RANGE (Y)
(D) (FK) (J) (N)
O°C 2V
to to TLC556CD TLC556CN TLC556Y
70°C 18 V
– 4O°C 3V
to to TLC556lD TLC556IN
85°C 18 V
– 55°C 5V
to to TLC556MD TLC556MFK TLC556MJ TLC556MN
125°C 18 V
The D package is available taped and reeled. Add the suffix R to the device type (e.g., TLC556CDR).

FUNCTION TABLE
RESET TRIGGER THRESHOLD DISCHARGE
OUTPUT
VOLTAGE† VOLTAGE† VOLTAGE† SWITCH
< MIN Irrelevant Irrelevant L On
> MAX < MIN Irrelevant H Off
>MAX >MAX >MAX L On
> MAX > MAX < MIN As previously established
† For conditions shown as MIN or MAX, use the appropriate value specified under electrical characteristics.

functional block diagram (each timer)

CONT
VDD RESET
3
14 4

R
2 R1
THRES 5
R 1 OUT
S
R

6
TRIG
R
1
DISCH
7
GND

RESET can override TRIG and THRES.

TRIG can override THRES.
Pin numbers shown are for the D, J, or N packages.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

TLC556Y chip information

These chips, properly assembled, display characteristics similar to the TLC556 (see electrical table). Thermal
compression or ultrasonic bonding may be used on the doped aluminum bonding pads. Chips may be mounted
with conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 TYPICAL

BONDING PADS: 4 × 4 MINIMUM
TJ max = 150°C
61 TOLERANCES ARE ± 10%
ALL DIMENSIONS ARE IN MILS
NO BACKSIDE METALLIZATION
PIN (7) INTERNALLY CONNECTED
TO BACKSIDE OF CHIP

97

FUNCTIONAL BLOCK DIAGRAM (EACH TIMER)

CONT
VDD RESET
(3)
(14) (4)

R
(2) R1
THRESH (5)
R 1 OUT
S
R

(6)
TRIG
R
(1)
DISCH
(7)
GND

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

absolute maximum ratings over operating free-air temperature (unless otherwise noted)
TLC556C TLC556I TLC556M UNIT
Supply voltage, VDD (see Note 1) 18 18 18 V
Input voltage range, VI – 0.3 to VDD – 0.3 to VDD – 0.3 to VDD V
Sink current, discharge or output 150 150 150 mA
Source current, output 15 15 15 mA
Continuous total power dissipation See Dissipation Rating Table
Operating free-air temperature range 0 to 70 – 40 to 85 – 55 to 125 °C
Storage temperature range – 65 to 150 – 65 to 150 – 65 to 150 °C
Case temperature for 60 seconds FK package 260
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J package 300 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds D or N package 260 260
NOTE 1: All voltage values are with respect to network ground terminal.

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING FACTOR TA = 70°C TA = 85°C TA = 125°C
PACKAGE
POWER RATING ABOVE TA = 25°C POWER RATING POWER RATING POWER RATING
D 950 mW 7.6 mW/°C 608 mW 494 mW N/A
FK 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
J 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
N 1150 mW 9.2 mW/°C 736 mW 598 mW N/A

recommended operating conditions

MIN MAX UNIT
Supply voltage, VDD 2 15 V
TLC556C 0 70
Operating free-air temperature range, TA TLC556I – 40 85 °C
TLC556M – 55 125

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 2 V for TLC556C, VDD = 3 V for
TLC556I
TEST TLC556C TLC556I
PARAMETER TA† UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX
25°C 0.95 1.33 1.65 1.6 2 2.4
VIT Input threshold voltage V
Full range 0.85 1.75 1.5 2.5
25°C 10 10
Threshold current pA
MAX 75 150
25°C 0.4 0.67 0.95 0.71 1 1.29
V(t i )
(trigger) Trigger voltage V
Full range 0.3 1.05 0.61 1.39
25°C 10 10
I(trigger)
(t i ) Trigger current pA
MAX 75 150
25°C 0.4 1.1 1.5 0.4 1.1 1.5
V((reset)
t) Reset voltage V
Full range 0.3 1.8 0.3 1.8
25°C 10 10
I(reset)
( t) Reset current pA
MAX 75 150
Control voltage (open circuit) as
MAX 66.7% 66.7%
a percentage of supply voltage
Discharge
g switch on-state volt- 25°C 0.04 0.2 0.03 0.2
IOL = 1 mA V
age Full range 0.25 0.375
Discharge
g switch off-state cur- 25°C 0.1 0.1
nA
rent MAX 0.5 120
25°C 1.5 1.9 1.5 1.9
VOH High level output voltage
High-level 300 µA
IOH = –300 V
Full range 1.5 2.5
25°C 0.07 0.3 0.07 0.3
VOL Low level output voltage
Low-level IOL = 1 mA V
Full range 0.35 0.4
25°C 130 500 130 500
IDD Supply current See Note 2 µA
Full range 800 1000
† Full range is 0°C to 70°C for TLC556C and – 40°C to 85°C for TLC556I.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 5 V

TEST TLC556C TLC556I TLC556M
PARAMETER
CONDITIONS TA† UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX

Input threshold 25°C 2.8 3.3 3.8 2.8 3.3 3.8 2.8 3.3 3.8
VIT V
voltage Full range 2.7 3.9 2.7 3.9 2.7 3.9
25°C 10 10 10
Threshold current pA
MAX 75 150 5000
25°C 1.36 1.66 1.96 1.36 1.66 1.96 1.36 1.66 1.96
V((trigger)) Trigger voltage V
Full range 1.26 2.06 1.26 2.06 1.26 2.06
25°C 10 10 10
I((trigger)
i ) Trigger current pA
MAX 75 150 5000
25°C 0.4 1.1 1.5 0.4 1.1 1.5 0.4 1.1 1.5
V((reset)) Reset voltage V
Full range 0.3 1.8 0.3 1.8 0.3 1.8
25°C 10 10 10
I((reset)) Reset current pA
MAX 75 150 5000
Control voltage (open
circuit) as a
MAX 66.7% 66.7% 66.7%
percentage of supply
voltage

Discharge
g switch 25°C 0.15 0.5 0.15 0.5 0.15 0.5
O = 10 mA
IOL V
on-state voltage Full range 0.6 0.6 0.6

Dischargeg switch 25°C 0.1 0.1 0.1

nA
off-state current MAX 0.5 2 120

High-level
g output 25°C 4.1 4.8 4.1 4.8 4.1 4.8
VO
OH O = –1
IOH 1 mA V
voltage Full range 4.1 4.1 4.1
25°C 0.21 0.4 0.21 0.4 0.21 0.4
IOL
O = 8 mA
Full range 0.5 0.5 0.6

Low-level output 25°C 0.13 0.3 0.13 0.3 0.13 0.3

VO
OL O = 5 mA
IOL V
voltage Full range 0.4 0.4 0.45
25°C 0.08 0.3 0.08 0.3 0.08 0.3
O = 3.2
IOL 3 2 mA
Full range 0.35 0.35 0.4
25°C 340 700 340 700 340 700
IDD Supply current See Note 2 µA
Full range 1000 1200 1400
† Full range is 0°C to 70°C for TLC556C, – 40°C to 85°C for TLC556I, and – 55°C to 125°C for TLC556M.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or to TRIG.

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics at specified free-air temperature, VDD = 15 V

TEST TLC556C TLC556I TLC556M
PARAMETER TA† UNIT
CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX
25°C 9.45 10 10.55 9.45 10 10.55 9.45 10 10.55
VIT Input threshold voltage V
Full range 9.35 10.65 9.35 10.65 9.35 10.65
25°C 10 10 10
Threshold current pA
MAX 75 150 5000
25°C 4.65 5 5.35 4.65 5 5.35 4.65 5 5.35
V(t
(trigger)
i ) Trigger voltage V
Full range 4.55 5.45 4.55 5.45 4.55 5.45
25°C 10 10 10
I(trigger)
(t i ) Trigger current pA
MAX 75 150 5000
25°C 0.4 1.1 1.5 0.4 1.1 1.5 0.4 1.1 1.5
V((reset)
t) Reset voltage V
Full range 0.3 1.8 0.3 1.8 0.3 1.8
25°C 10 10 10
I(reset)
( t) Reset current pA
MAX 75 150 5000
Control voltage (open
circuit) as a percent- MAX 66.7% 66.7% 66.7%
age of supply voltage

Discharge
g switch on- 25°C 0.8 1.7 0.8 1.7 0.8 1.7
IOL = 100 mA V
state voltage Full range 1.8 1.8 1.8

Discharge
g switch off- 25°C 0.1 0.1 0.1
nA
state current MAX 0.5 2 120
25°C 12.5 14.2 12.5 14.2 12.5 14.2
IOH = –10
10 mA
Full range 12.5 12.5 12.5

High-level
g output 25°C 13.5 14.6 13.5 14.6 13.5 14.6
VOH IOH = –5
5 mA V
voltage Full range 13.5 13.5 13.5
25°C 14.2 14.9 14.2 14.9 14.2 14.9
IOH = –1
1 mA
Full range 14.2 14.2 14.2
25°C 1.28 3.2 1.28 3.2 1.28 3.2
IOL = 100 mA
Full range 3.6 3.7 3.8

Low-level output 25°C 0.63 1 0.63 1 0.63 1

VOL IOL = 50 mA V
voltage Full range 1.3 1.4 1.5
25°C 0.12 0.3 0.12 0.3 0.12 0.3
IOL = 10 mA
Full range 0.4 0.4 0.45
25°C 0.72 1.2 0.72 1.2 0.72 1.2
IDD Supply current See Note 2 mA
Full range 1.6 1.8 2
† Full range is 0°C to 70°C for TLC556C, – 40°C to 85°C for TLC556I, and – 55°C to 125°C for TLC556M.
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

electrical characteristics, VDD = 5 V, TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIT Input threshold voltage 2.8 3.3 3.8 V
Threshold current 10 pA
V(trigger) Trigger voltage 1.36 1.66 1.96 V
I(trigger) Trigger current 10 pA
V(reset) Reset voltage 0.4 1.1 1.5 V
I(reset) Reset current 10 pA
Discharge switch on-state voltage IOL = 10 mA 0.15 0.5 V
Discharge switch off-state current 0.1 nA
VOH High-level output voltage IOH = – 1 mA 4.1 4.8 V
IOL = 8 mA 0.21 0.4
VOL Low-level output voltage IOL = 5 mA 0.13 0.3 V
IOL = 2.1 mA 0.08 0.3
IDD Supply current See Note 2 3.40 700 µA
NOTE 2: These values apply for the expected operating configurations in which THRES is connected directly to DISCH or TRIG.

operating characteristics, VDD = 5 V, TA = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Initial error of timing interval † VDD = 5 V to 15 V, RA = RB = 1 kΩ to 100 kΩ 1% 3%
Supply voltage sensitivity of timing interval CT = 0.1 µF, See Note 3 0.1 0.5 %/V
tr Output pulse rise time 20 75
RL = 10 MΩ,
MΩ CL = 10 pF ns
tf Output pulse fall time 15 60
RA = 470 Ω, RB = 200 Ω,
fmax Maximum frequency in astable mode 1.2 2.1 MHz
CT = 200 pF, See Note 3
† Timing interval error is defined as the difference between the measured value and the average value of a random sample from each process
run.
NOTE 3: RA, RB, and CT are as defined in Figure 3.

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

TYPICAL CHARACTERISTICS

PROPAGATION DELAY TIMES (TO DISCHARGE

OUTPUT FROM TRIGGER AND THRESHOLD
SHORTED TOGETHER)
DISCHARGE SWITCH ON-STATE RESISTANCE vs
vs SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
100 600

t PHL , t PLH – Propagation Delay Times – ns

70 IO(on) ≥ 1 mA
VDD = 2 V, IO = 1 mA CL ≈ 0
Discharge Switch On-State Resistance – Ω

500 TA = 25°C
40

VDD = 5 V, IO = 10 mA
20 400

VDD = 15 V, IO = 100 mA
10 300
7

200 tPHL
4
tPLH‡
100
2

1 0
–75 –50 –25 0 25 50 75 100 125 0 2 4 6 8 10 12 14 16 18 20
TA – Free-Air Temperature – °C VDD – Supply Voltage – V
‡ The effects of the load resistance on these values must be
Figure 1
taken into account separately.

Figure 2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

APPLICATION INFORMATION

0.1 µF tL
tH
RA VDD
0.1 µF
tPHL
CONT VDD
RESET RL
2/3 VDD
TLC556
DISCH
Output
OUT
RB 1/3 VDD
THRES CL
TRIG
GND
CT GND
tPLH

CIRCUIT TRIGGER AND THRESHOLD VOLTAGE WAVEFORM

Figure 3. Astable Operation

Connecting the trigger input to the threshold input, as shown in Figure 3, causes the timer to run as a
multivibrator. The capacitor CT charges through RA and RB to the threshold voltage level (approximately 0.67
VDD) and then discharges through RB only to the value of the trigger voltage level (approximately 0.33 VDD).
The output is high during the charging cycle (tH) and low during the discharge cycle (tL). The duty cycle is
controlled by the values of RA, and RB, and CT, as shown in the equations below.
tH [ CT (RA ) RB) In 2 (In 2 + 0.693)
t L [ C T R B In 2
Period + t H ) t L [ C T (R A ) 2R B) In 2

Output driver duty cycle + [ 1 *

tL RB
tH ) tL R A ) 2R B

Output waveform duty cycle + tH t)H tL [ R )RB2R

A B
The 0.1-µF capacitor at CONT in Figure 3 decreases the period by about 10%.
The formulas shown above do not allow for any propagation delay from the trigger and threshold inputs to the
discharge output. These delay times add directly to the period and create differences between calculated and
actual values that increase with frequency. In addition, the discharge output resistance ron adds to RB to provide

ƪ ǒ Ǔƫ
another source of error in the calculation when RB is very low or ron is very high.
The equations below provide better agreement with measured values.

+ CT (RA ) RB) In * exp * tPLH ) tPHL

C T (R B ) r on)

ƪ ǒ Ǔƫ
tH 3

+ CT (RB ) ron) In * exp * tPHL ) tPLH

C T (R A ) R B)
tL 3

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 TLC556, TLC556Y
DUAL LinCMOS TIMERS
SLFS047B – FEBRUARY 1984 – REVISED SEPTEMBER 1997

APPLICATION INFORMATION

The preceding equations and those given earlier are similar in that a time constant is multiplied by the logarithm
of a number or function. The limit values of the logarithmic terms must be between In 2 at low frequencies and
In 3 at extremely high frequencies. For a duty cycle close to 50%, an appropriate constant for the logarithmic
t t
)
terms can be substituted with good results. Duty cycles less than 50% H will require that H < 1 and
t t t
H L L
possibly RA ≤ ron. These conditions can be difficult to obtain.
In monostable applications, the trip point of the trigger input can be set by a voltage applied to CONT. An input
voltage between 10% and 80% of the supply voltage from a resistor divider with at least 500-µA bias provides
good results.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-89503022A ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 89503022A
TLC556MFKB
5962-8950302CA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8950302CA Samples
& Green TLC556MJB
TLC556CD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC556C Samples

TLC556CDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM 0 to 70 TLC556C Samples

TLC556CDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC556C Samples

TLC556CDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC556C Samples

TLC556CN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type TLC556CN Samples

TLC556ID ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC556I Samples

TLC556IDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC556I Samples

TLC556IDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC556I Samples

TLC556IDRG4 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 85 TLC556I Samples

TLC556IN ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type TLC556IN Samples

TLC556MD ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 TLC556M Samples

TLC556MDG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM TLC556M Samples

TLC556MDR ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 TLC556M Samples

TLC556MFKB ACTIVE LCCC FK 20 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962- Samples
& Green 89503022A
TLC556MFKB
TLC556MJ ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 TLC556MJ Samples
& Green
TLC556MJB ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8950302CA Samples
& Green TLC556MJB

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2022

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TLC556, TLC556M :

• Catalog : TLC556
• Military : TLC556M

NOTE: Qualified Version Definitions:

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Jun-2022

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC556CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLC556IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLC556CDR SOIC D 14 2500 340.5 336.1 32.0
TLC556IDR SOIC D 14 2500 350.0 350.0 43.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 5-Jan-2022

TUBE

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
5962-89503022A FK LCCC 20 1 506.98 12.06 2030 NA
TLC556CD D SOIC 14 50 505.46 6.76 3810 4
TLC556CD D SOIC 14 50 507 8 3940 4.32
TLC556CDG4 D SOIC 14 50 507 8 3940 4.32
TLC556CDG4 D SOIC 14 50 505.46 6.76 3810 4
TLC556CN N PDIP 14 25 506 13.97 11230 4.32
TLC556ID D SOIC 14 50 505.46 6.76 3810 4
TLC556IDG4 D SOIC 14 50 505.46 6.76 3810 4
TLC556IN N PDIP 14 25 506 13.97 11230 4.32
TLC556MD D SOIC 14 50 505.46 6.76 3810 4
TLC556MDG4 D SOIC 14 50 505.46 6.76 3810 4
TLC556MFKB FK LCCC 20 1 506.98 12.06 2030 NA

Pack Materials-Page 3
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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