ECE318:CMOS VLSI Design

Unit 2
Fabrication of MOSFET and Scaling
Fabrication process flow
Create n-well region
➢ Creation of the n-well regions for pMOS transistors, by impurity
implantation into the substrate.
➢ Then, a thick oxide is grown in the regions surrounding the
Grow Oxide layer
nMOS and pMOS active regions.
➢ The thin gate oxide is subsequently grown on the surface
through thermal oxidation. Create or deposit
➢ These steps are followed by the creation of n+ and p+ regions poly silicon layer

(source, drain, and channel stop implants)

➢ final metallization (creation of metal interconnects). Implant source, drain
regions, substrate
contact

Create contact,
deposit and pattern
metal layer
Process steps required for patterning of silicon dioxide

Si-Substrate

SiO2

Si-Substrate

Photoresist

SiO2

Si-Substrate

U V Rays

Glass mask

SiO2 Exposed photoresist become soluble

Si-Substrate
Fabrication of nMOS transistor
➢ Oxidation of Silicon Substrate (Fig.b)
➢ Field oxide is selectively etched to expose the silicon surface on
which the MOS transistor will be created (Fig.c)
➢ On top of the thin oxide layer, a layer of polysilicon
(polycrystalline silicon) is deposited (Fig.d)
➢ Polysilicon is used both as gate electrode material for MOS
transistors and also as an interconnect medium in silicon
integrated circuits.
➢ Undoped polysilicon has relatively high resistivity.
➢ The-resistivity of polysilicon can be reduced, however, by doping
it with impurity atoms.

Fig. Process flow for the fabrication of

an n-type MOSFET on p-type silicon.
Fabrication of nMOS transistor(Contd.)
➢ Polysilicon is also etched away, which exposes
the bare silicon surface on which the source and
drain junctions are to be formed
➢ The entire silicon surface is then with a high
concentration of impurities, either through
diffusion or ion implantation (in this case with
donor atoms to produce n-type doping) (Fig. h)
➢ The impurity doping also penetrates the
polysilicon on the surface, reducing its resistivity
➢ Once the source and drain regions are
completed, the entire surface is again covered
with an insulating layer of silicon dioxide (f)
➢ The insulating oxide layer is then patterned in
order to provide contact windows for the drain
and source junctions (Fig.j).
➢ The surface is covered with evaporated
aluminum which will form the interconnects
Fabrication of nMOS transistor(Contd.)
➢ Metal layer is patterned and etched, completing the
interconnection of the MOS transistors on the surface.
Device Isolation Techniques
The MOS transistors that comprise an integrated circuit must be
electrically isolated from each other during fabrication.
➢ Isolation is required to prevent unwanted conduction paths
between the devices, to avoid creation of inversion layers outside
the channel regions of transistors, and to reduce leakage
currents.
➢ To achieve a sufficient level of electrical isolation between
neighboring transistors on a chip surface, the devices are typically
created in dedicated regions called active areas
➢ Active area is surrounded by a relatively thick oxide barrier called
the field oxide.
➢ One possible technique to create isolated active areas on silicon
surface is first to grow a thick field oxide over the entire surface
of the chip, and then to selectively etch the oxide in certain
regions, to define the active areas. This fabrication technique,
called etched field-oxide isolation
 Device Isolation Techniques
Etched field-oxide isolation technique
➢ Here, the field oxide is selectively etched away to expose the silicon
surface on which the MOS transistor will be created.
➢ Although the technique is relatively straightforward, it also has some
drawbacks.
➢ The most significant disadvantage is that the thickness of the field
oxide leads to rather large oxide steps at the boundaries between
active areas and isolation Fabrication (field) regions.
➢ When polysilicon and metal layers are deposited over such boundaries
in of MOSFETs subsequent process steps, the sheer height difference
at the boundary can cause cracking of deposited layers, leading to chip
failure.
➢ The local oxidation of silicon (LOCOS) technique is based on the principle
of selectively growing the field oxide in certain regions, instead of
selectively etching away the active areas after oxide growth.
➢ Selective oxide growth is achieved by shielding the active areas with
silicon nitride (Si3N4) during oxidation, which effectively inhibits oxide Fig. Basic steps of the LOCOS process to
growth. create oxide isolation around active areas
CMOS n-Well Process
• The n-well CMOS process starts with a moderately doped (with impurity
concentration typically less than 1015 cm-3) p-type silicon substrate.
• Then, an initial oxide layer is grown on the entire surface.
• The first lithographic mask defines the n-well region. Donor atoms, usually
phosphorus, are implanted through this window in the oxide.
• Once the n-well is created, the active areas of the nMOS and pMOS
transistors can be defined.
• The polysilicon layer is deposited using chemical vapor deposition (CVD)
and patterned by dry (plasma) etching.
MCQ
Q1. Which layer is used for power and signal lines?
a) metal
b) polysilicon
c) n-diffusion
d) p-diffusion
CMOS n-Well Process
➢ The created polysilicon lines will function as the gate
electrodes of the nMOS and the pMOS transistors
and their interconnects.
➢ Using a set of two masks, the n+ and p+ regions are
implanted into the substrate and into the n-well,
respectively
➢ Metal (aluminum) is deposited over the entire chip
surface using metal evaporation, and the metal lines
are patterned through etching.
➢ Since the wafer surface is non-planar, the quality and
the integrity of the metal lines created in this step are
very critical and are ultimately essential for circuit
reliability
 CMOS n-Well Process
➢ The composite layout and the resulting cross-sectional
view of the chip, showing one nMOS and one pMOS
transistor (in the n-well), and the polysilicon and metal
interconnections.
➢ The final step is to deposit the passivation layer (for
protection) over the chip, except over wire-bonding
pad areas.
Layout Design Rules
The design rules are usually described in two ways:
(i) Micron rules, in which the layout constraints such as minimum feature sizes and minimum
allowable feature separations are stated in terms of absolute dimensions in micrometers, or,
(ii) Lambda rules, which specify the layout constraints in terms of a single parameter (X) and thus
allow linear, proportional scaling of all geometrical constraints.
Lambda-based layout design rules devised for
the MOSIS (MOS Implementation System)
MCQ’s
Q1. Design rules does not specify __________
a) linewidths
b) separations
c) extensions
d) colours

Q2. The width of n-diffusion and p-diffusion layer should be?

a) 3λ
b) 2λ
c) λ
d) 4λ

Q3. What should be the spacing between two diffusion layers?

a) 4λ
b) λ
c) 3λ
d) 2λ
MCQ’s
Q4. Minimum n-well width should be ____________ micro meter.
a) 2
b) 3
c) 4
d) 6
Typical design flow for the production
of a mask layout
Design rules which determine the dimensions of a minimum-size
transistor
For the minimum diffusion contact size (which is necessary for
source and drain connections) and the minimum separation
from diffusion contact to both active area edges.

Width of the polysilicon line over the active area (which is the
gate of the transistor) is typically taken as the minimum poly
width (Fig. 2.14).

Minimum overall length of the active area:

(minimum polysilicon width) + 2 x (minimum poly-to-contact
spacing) + 2 x (minimum contact size) + 2 x (minimum spacing
from contact to active area edge).
Design rules which determine the separation between the
nMOS and the pMOS transistor of the CMOS inverter.

➢ Polysilicon gates of the nMOS and the pMOS transistors are

usually aligned, so that the gate connections can be made
with a single polysilicon line of least possible length.
➢ Reason for avoiding long polysilicon connections (as a general
layout practice) is the fact that the large parasitic resistance
and the parasitic capacitance of polysilicon lines may result in
significant RC delays;
Complete mask layout of the CMOS inverter
➢ Layout design rules dictate a set of limitations for the mask
geometry
➢ Full-custom layout design process still allows a large
number of variations in terms of device sizing, the
placement of individual devices, and the routing of
interconnections between the devices
➢ A simple circuit consisting of only two transistors.
➢ Depending on the dominant design criteria and design
constraints (minimization of overall silicon area,
minimization of delay times, placement of input/output
pins, etc.), one can choose a certain mask layout design
over other alternatives.
MOSFET Scaling and Small-Geometry Effects
• The design of high-density chips in MOS VLSI (Very Large Scale Integration) technology requires that
the packing density of MOSFETs used in the circuits is as high as possible and, consequently, that the
sizes of the transistors are as small as possible.
• The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to as scaling.
• It is expected that the operational characteristics of the MOS transistor will change with the reduction
of its dimensions.
• There are two basic types of size-reduction strategies: full scaling (also called constant-field scaling)
and constant voltage scaling.
• Scaling of MOS transistors is concerned with systematic reduction of overall dimensions of the devices
as allowed by the available technology, while preserving the geometric ratios found in the larger
devices.
• To describe device scaling, a constant scaling factor S >1 is required
• A new generation of manufacturing technology replaces the previous one about every two or three
years, and the down-scaling factor S of the minimum feature size from one generation to the next is
about 1.2 to 1.5.
Table: Reduction of the
minimum feature size
Full Scaling (Constant-Field Scaling)
• Scaling of a typical MOSFET by a scaling factor of S.
• This scaling option attempts to preserve the magnitude of internal
electric fields in the MOSFET, while the dimensions are scaled
down by a factor of S.
• To achieve this goal, all potentials must be scaled down
proportionally, by the same scaling factor.
• this potential scaling also affects the threshold voltage VT0
• Finally, the Poisson equation describing the relationship between
charge densities and electric fields dictates that the charge
densities must be increased by a factor of S in order to maintain
the field conditions.

Table : lists the scaling factors for all significant dimensions,

potentials, and doping densities of the MOS transistor
 Full scaling effect on the current-voltage characteristics of the
MOS transistor
➢ The gate oxide capacitance per unit area, on the other hand, is changed as follows:
𝝐𝒐𝒙 𝝐
𝑪′𝒐𝒙 = =S 𝒐𝒙=S 𝑪𝒐𝒙
𝒕′𝒐𝒙 𝒕𝒐𝒙
➢ The aspect ratio WIL of the MOSFET will remain unchanged under scaling. Consequently, the
transconductance parameter kn will also be scaled by a factor of S.
➢ Since all terminal voltages are scaled down by the factor S as well, the linear-mode drain current of
the scaled MOSFET can now be found as:
𝑲𝒏 𝑰𝑫 (𝒍𝒊𝒏)
𝑰′𝑫 𝒍𝒊𝒏 = 𝑲′𝒏 [2 𝑽𝒈𝒔 − 𝑽𝑻 𝑽𝒅𝒔 −𝑽𝒅𝒔 𝟐 ]= [2 𝑽𝒈𝒔 − 𝑽𝑻 𝑽𝒅𝒔 −𝑽𝒅𝒔 𝟐 ]=
𝑺 𝑺
➢ Instantaneous power dissipated by the device (before scaling) can be found as:
𝑷
𝑷′ = 𝑰′𝑫 𝑽′𝑫𝑺=
𝑺𝟐

Table: Effects of full scaling upon

key device characteristics
MCQ
Q1. The saturation current is scaled by the factor of:
a) 1
b) 1/α2
c) 1/β
d) 1/α
Q2. The power dissipation per gate is scaled as:
a) 1
b) 1/ β.α2
c) α2/β
d) 1/ β2
 Constant-Voltage Scaling
• While the full scaling strategy dictates that the power supply voltage and all terminal voltages be
scaled down proportionally with the device dimensions, the scaling of voltages may not be very
practical in many cases.
• In particular, the peripheral and interface circuitry may require certain voltage levels for all input
and output voltages, which in turn would necessitate multiple power supply voltages and
complicated levelshifter arrangements.
• For these reasons, constant-voltage scaling is usually preferred over full scaling.
• In constant-voltage scaling, all dimensions of the MOSFET are reduced by a factor of S, as in full
scaling.
• The power supply voltage and the terminal voltages, on the other hand, remain unchanged.
• The doping densities must be increased by a factor of S2 in order to preserve the charge-field
relations.
𝑰′𝑫 𝒍𝒊𝒏 = 𝑲′𝒏 [2 𝑽𝒈𝒔 − 𝑽𝑻 𝑽𝒅𝒔 −𝑽𝒅𝒔 𝟐 ]=S 𝑰𝑫 𝒍𝒊𝒏
𝑷′ = 𝑰′𝑫 𝑽′𝑫𝑺 =S.𝑷

Table: Constant-voltage scaling of MOSFET

dimensions, potentials, and doping densities.
Constant-Voltage Scaling
• Power density (power dissipation per unit area) is found to increase by a factor of S3 after
constant-voltage scaling, with possible adverse effects on device reliability.
• constant-voltage scaling may be preferred over full (constant-field) scaling in many practical cases
because of the external voltage-level constraints.
• It must be recognized, however, that constant-voltage scaling increases the drain current density
and the power density by a factor of S3.
• This large increase in current and power densities may eventually cause serious reliability
problems for the scaled transistor, such as electromigration, hot-carrier degradation, oxide
breakdown, and electrical over-stress.

Table: Effects of constant-voltage scaling

upon key device characteristics.
Short Channel Effect: Non-Ideal Effect
The deviation of MOSFET characteristics from ideal condition is known
as non-ideal effect.
• Subthreshold Conduction: For Vgs<VT a small subthreshold current
flows.
• Channel Length Modulation: In saturation, the depletion region at
drain terminal shift towards source reducing effect channel length.
𝐿
• 𝐼′𝐷 = 𝐼
𝐿−∆𝐿 𝐷
Subthreshold Performance
Why Polysilicon?
• The threshold voltage (and consequently the drain to source on-current) is determined by the
work function difference between the gate material and channel material.
• When metal was used as gate material, gate voltages were large (in the order of 3V to 5V), the
threshold voltage (resulting from the work function difference between a metal gate and silicon
channel) could still be overcome by the applied gate voltage (i.e. |Vg - Vt| > 0).
• As transistor sizes were scaled down, the applied signal voltages were also brought down (to
avoid gate oxide breakdown, hot-electron reduction, power consumption reduction, etc).
• A transistor with a high threshold voltage would become non-operational under these new
conditions. Thus, poly-crystalline silicon (polysilicon) became the modern gate material because it
is the same chemical composition as the silicon channel beneath the gate oxide.
• In inversion, the work-function difference is close to zero, making the threshold voltage lower and
ensuring the transistor can be turned on.
• Polysilicon is also more stable for temperature variations.
• In place of polysilicon we can also use high work function metals like Ni, Co, Ti and Pt etc.
Why high-K dielectric insulating material in place of SiO2?
The requirements of a new oxide to replace
SiO2 are as follows:
➢ The metal oxide must have a permittivity
higher than Si, industry targets values
nearly between 15 to 20.
➢ Aiming towards less leakage of current, the
material should allow less leakage current.
➢ Density of defects must be less
➢ The oxide is in constant contact with Si and
hence must be thermodynamically stable
with it.
➢ High breakdown field and low loss factor .

Drawback: High-K degrade mobility due high

threshold voltage.
Energy band and energy bond
• Energy Band diagram: It gives information about valence band, conduction band and band gap
which important to categorise semiconductor and their performances.
• Bond Energy: Bond energy is directly related to the melting temperature of solids.
• For different types of bonds, the melting temperature scales with the bond energy. Both ionic
(e.g. NaCl, MgO) and covalent bonds (e.g. Si, C) have high bond energies and consequently high
melting temperature.
What are low Level and high level of
Injection?
➢ low injection, means that the excess carrier concentration is much smaller than the thermal-
equilibrium majority carrier concentration. For the p-type semiconductor, then, low injection
implies that δn<p0
➢ Under low injection, hole concentration is just the acceptor impurity concentration
➢ High level injection, when excess electron become comparable or more than majority holes.
Video link: NMOS Characteristics
https://www.youtube.com/watch?v=13-oG0gVvvE
https://www.youtube.com/watch?v=H5Obyg8uE6g
Query??