International Journal of Innovative Technology and Exploring Engineering (IJITEE)

ISSN: 2278-3075 (Online), Volume-9 Issue-4, February 2020

Design and Implementation of Full Adder using

Different XOR Gates
D. Durga Prasad, M. Dileep , Ch. Rama Krishna

Abstract: A Full Adder is a logical circuit that servers a great Driving capability for outputs without glitches, different
part in the design of application particular integrated circuits. It loads, interconnection quality and layout regularity also
is the basic component found in VLSI and DSP applications. The should be looked after. A range of nano meter devices are
applications of Full adder in VLSI include ALU design, Address faced by the problem of short channel effects and other hot
generation in processors, Multipliers and so on. Power
carrier effects. To maintain correct speed, the threshold
consumption is one of the most significant parameters of full
adder. Therefore, reducing power consumption in full adder is voltage is scaled down, which leads to increase in standby
very important. In this paper, Design XOR gate using currents, also effect the static power is one of the main
Transmission gate logic (TGL), Pass transistor logic (PTL) and contributor to total power.
Static Complementary metal oxide semiconductor logic (CMOS).
Also design Full Adder circuit using different XOR gate designs. II. REVIEW OF XOR GATE
These circuits are designed and implemented, simulated using
Mentor Graphics Tool. After getting simulation results, compare Mostly, By using XOR, AND, OR gates full adders are
the different XOR gate designs based full adders in terms of designed. While designing full adder, the major consumer of
power consumption and delay. Using the comparative analysis power is XOR gate. Consequently, The power consumption
for the designed Full Adders, an effective adder design can be will be decreased in full adder, by designing the
chosen based on the performance criteria as required by the XNOR/XOR gates in optimum way. Mainly, the
designer. applications of digital circuits design are done by
Keywords: Full Adder, TGL, PTL, Mentor Graphics Tool. implementing XOR/XNOR gates. Also several other circuits
are proposed with this implementation of XNOR/XOR
I. INTRODUCTION gates. By using Pass Transistor logic, Transmission gate
logic and CMOS logic XOR gate was designed.
There are different type of arithmetic operations as follow,
Addition, Multiplication, Subtraction, Division and Address III. XOR GATE USING CMOS LOGIC
Calculation. In VLSI systems most commonly used
operation is Addition. Full Adder is designed using binary CMOS devices will have two important characteristics as
adders and improving the performance of full adder by 1-bit mentioned below, they are high noisy immunity and low
is a significant role in VLSI. By using the various types of static power. One of transistor pair will be always in off
full adders we can design different technologies and logical condition, While switching between off and on states,
designs, and an important goal of these technologies is to significant power will be drawn by series combination
reduce power consumption and also to increase speed. The momentarily. Where CMOS circuits will not produce that
adder performance can be improved by two methods and much waste heat likewise other logics, for example
one of the methods is as follow. The two methods are transistor-transistor logic (logic) or, N-type metal-oxide-
System level viewpoint method and Circuit style viewpoint semiconductor logic (NMOS), these will have a certain
method. In first method, System level viewpoint, in this amount of standing current when they are not changing their
longest signal path is determined in ripple adders also state. In chip, high density logic functions are allowed by
decrease the trail to scale back the full signal path delay. CMOS. Due to this reason, CMOS were highly used in
Where, the carry out bit of highly significant bit is implementing VLSI (very large scale integration) chips.
calculated there will be a longest path. Coming to next The real architecture of particular field-effect transistors is
method Circuit style viewpoint method, high performance referenced by the phrase "metal-oxide-semiconductor", with
full adder is designed by using semiconductor level design an electrode of metal gate at the leading position of oxide
skills. To prevent decrease in signal magnitude, we require insulator, and it is the turn on top of the semiconductor.
an optimized design, which also consume less power, Previously aluminium material was used, but now we are
provide small delays even at little voltage supply maintain using polysilicon material. In CMOS process, remaining
consistency in critical paths while moving headed for metal gates are come back with high-k dielectric material,
smaller designs such as in nanometre range. during the time, which was announced by Intel for the 45-
nanometre nodes and which are smaller in sizes.
Many of the complex logics are involved with OR and AND
Revised Manuscript Received on February 28, 2020.
* Correspondence Author logic gates require wielding the ways among gates that
D.Durga Prasad*, Assistant Professor, Department of ECE, Vishnu represents the logic. Both the two transistors will have low
Institute of Technology, Vit, Bhimavaram, Andhra Pradesh, India resistance when, path dwells of those transistors are in
M.Dileep , Assistant Professor, Department of ECE, Vishnu Institute of series, It also to the corresponding supply voltage,
Technology, Vit, Bhimavaram, Andhra Pradesh, India
Ch.Rama Krishna, Assistant Professor, Department of ECE, Vishnu modelling an AND. Either one of both transistors will have
Institute of Technology, Vit, Bhimavaram, Andhra Pradesh, India low resistance when they are in parallel and corresponding
supply voltage is modelling an OR. The below figure.
© The Authors. Published by Blue Eyes Intelligence Engineering and
Sciences Publication (BEIESP). This is an open access article under the
CC-BY-NC-ND license http://creativecommons.org/licenses/by-nc-nd/4.0/

Retrieval Number: C8891019320/2020©BEIESP Published By:

DOI: 10.35940/ijitee.C8891.029420 Blue Eyes Intelligence Engineering
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Journal Website: www.ijitee.org & Sciences Publication
 Design and Implementation of Full Adder using Different XOR Gates

1 shows XOR Gate using CMOS Logic. C.XOR USING PASS TRANSISTOR LOGIC
Pass transistor logic (PTL): During the designing of
integrated circuits we use pass transistor logic to describe
many logic families. The number of transistors count to
make different type of logic is reduced, by deleting the
redundant transistors. Instead of switches we use transistors
to pass logic levels between nodes of a circuit, because they
are directly connected to supply voltages. Active devices
count is get decreased.
At each stage the difference between of high voltage logic
level and low voltage logic levels is reduced, it is the main
drawback. Each transistor when in series connection it is
less saturated, when compared to its input. An usually
constructed gate may require to renovate the signal voltage
to full value, when many devices are connected in series in a
logic path.
To the one of the given power supply rails output is
Fig.1. XOR Gate using CMOS Logic connected, so that in sequential chain logic voltage levels
B. XOR GATE USING TRANSMISSION GATE does not decrease which is in contrast to the conventional
LOGIC CMOS logic switch transistors. To ensure adequate
performance simulation of circuits may be required.
The signal level from input to output will be selectively
On depending upon given input signal Vin, the periodic
passes or blocked by an electronic element, which can be
clock signal drives the pass transistors and this pass
defined as an analog switch or transmission gate. pMOS and
transistor acts as an access switch to either charge down or
nMOS transistors are there in this solid state switch. Both
charge up the parasitic capacitance Cx.
the transistors are made on or off based on the biasing in a
There are two possible operations logic “1” is transferred
complementary manner of a control gates. With almost any
clock signal is active and then charging up the capacitance
voltage potential it can be blocked by a control signal or
Cx to high level logic and the logic “0” is transfered to
conduct in both directions, which is similar to relay. It is a
charge down the Cx capacitance to low logic level. On
switch based upon CMOS, in which nMOS passes a good
depending upon Vx voltage, in any of case, the depletion
output 0 but weak 1, and pMOS passes good output of 1 but
load output of NMOS inverter assumes a low-logic or high-
weak 0. These two transistors, pMOS and nMOS work
logic level. The below figure.3 shows XOR Gate based on
parallelly. According to the basis, by using two field effect
Pass transistor Logic.
transistors we used to construct the transmission gate and
substrate is not connected source terminal internally, which
are in contrast with field effect transistors. The terminals of
transistors, i.e,. drain and source are contacted together
because, a p and n-channels MOSFETS are contacted in
shunt connection. To form control terminal we use inverter
(NOT gate) to connect their gate terminals. Here unlike the
FET the source connection is not connected with the
substrate terminal. To avoid the signal flow affect the
parasitic diode is always reversely biased and to the
respective supply potential we used to connect the substrate
potential. To the positive supply potential substrate of p-
channel MOSFET is connected. The n-chanel MOSFET is
connected to the negative supply potential. The below Fig.3.XOR Gate based on Pass transistor logic
figure.2 shows the XOR Gate based on Transmission Gate
Logic. III. RESULTS AND DISCUSSION
In Mentor Graphics Tool we implemented and resembled all
the circuits and observed the output waveforms of each
circuit.
A.IMPLEMENTATION OF XOR GATE
In fig.4 the simulation schematic of XOR Gate based on
Pass transistor logic is shown and in fig.5 simulation
waveform is shown.

Fig.2. XOR Gate using Transmission Gate Logic

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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075 (Online), Volume-9 Issue-4, February 2020

Fig.4. Simulation schematic of XOR gate based on Pass Fig.7. Simulation waveform diagram of XOR Gate based
Transistor logic on the Transmission gate logic
In Fig.8 the simulation schematic diagram of XOR Gate
using CMOS logic is shown and simulation waveform
diagram is shown in Fig.9.

Fig.5. Simulation waveform of XOR Gate based Pass

Transistor Logic
In the below Fig.6 the simulation schematic of
XOR Gate based on the transmission gate logic is shown
and in Fig.7 simulation waveform is shown. Fig.8: Simulation schematic of XOR using CMOS

Fig.6.Simulation schematic diagram of XOR Gate based

on transmission gate logic.

Fig.9. Simulation waveform of XOR using CMOS

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 Design and Implementation of Full Adder using Different XOR Gates

The below Table-I shows the differences between different

XOR Gate designs in terms of power dissipation and delay.
Table-I: POWER DISSIPATION AND DELAY
COMPARISON OF XOR GATES
XOR GATE
Power Dissipation
Design Delay

Pass Transistor Logic 132.5630 nWatts 239.64 ps

Transmission Gate Logic 301.7342 nWatts 49.971 ns

Fig.12. Simulation waveform of Full Adder based on
Transmission Gate logic

CMOS Logic 13.9140 mWatts 50.158 ns

B.IMPLEMENTATION OF FULL ADDER

In below fig.10 the simulation schematic of full adder is
shown.

Fig.13. Simulation waveform of Full Adder based Pass

Transistor Logic
The below Table-II shows the comparison between Full
Adder designs in terms of delay and power dissipation.
Table-II: POWER DISSIPATION AND DELAY
COMPARISON OF FULL ADDER
FULL ADDER
Power Dissipation Delay
Fig.10. Simulation schematic of full adder Design

The simulation waveform of full adder based on Pass Transistor Logic 916.9071 nWatts 49.823 ns
CMOS logic, Transmission gate logic & Pass Transistor
logic is shown in Fig.11, Fig.12, Fig.13 respectively.
Transmission Gate Logic 1.4584 uWatts 49.835 ns

CMOS Logic 1.5880 uWatts 49.910 ns

IV.CONCLUSION
Various types of full adder circuits with various logic styles
have been implemented. By comparing all the techniques,
the Pass Transistor logic based full adder consists of a very
less number of transistors, because of a less number of
transistors results in less switching activity and area, So
Pass Transistor logic based full adder capitulate less power
dissipation and delay when compare with other logic styles
Fig.11. Simulation waveform of Full Adder based on based full adder.
CMOS logic

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 International Journal of Innovative Technology and Exploring Engineering (IJITEE)
ISSN: 2278-3075 (Online), Volume-9 Issue-4, February 2020

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AUTHORS PROFILE
D.Durga, Prasad was born in A.P, India, Completed
M.Tech in VLSI System Design (VLSISD) at
Swarnandhra college of Engineering, Seetharampuram
in the year of 2015 and B.Tech from Vishnu Institute of
Technology in the year of 2013 in Electronics
&Communication engineering. Presently working as an
Assistant Professor in Vishnu Institute of Technology,
Bhimavaram ,A.P, India. His research interests in VLSI Design and
Communication Systems.

M.Dileep, was born in A.P, India completed M.Tech

from University Of Pune, B.Tech from Vasavi Engg
College, Tadepalligudem. Presently working as
Associate professor in Vishnu Institute of Technology,
Bhimavaram, His research interest in VLSI Design and
communication systems

Ch. Rama, Krishna was born in A.P, India. He

completed his M.Tech in JNTUK in 2008 and he has
totally 18 years experience. Presently He is working as
Associate professor in Vishnu Institute of Technology,
Bhimavaram. His interesred research areas are Low
power VLSI, analog circuits and Antennas.

Retrieval Number: C8891019320/2020©BEIESP Published By:

DOI: 10.35940/ijitee.C8891.029420 Blue Eyes Intelligence Engineering
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Journal Website: www.ijitee.org & Sciences Publication