Allegro®

Constraint Manager with Design Entry HDL

Tutorial
Product Version 15.2
June 2004
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 Allegro Constraint Manager with Design Entry HDL Tutorial

Contents
1
Introduction to the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Nature of Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Estimated Completion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Purpose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Prerequisites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Advantages of Using Constraint Manager with Design Entry HDL . . . . . . . . . . . . . . . . . 11
Using the Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Tutorial Database . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Understanding the Tutorial Database Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
What’s Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2
Setting Routing Constraints on Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Nature of Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Estimated Completion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Starting Design Entry HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Starting Constraint Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Setting the Maximum and Minimum Propagation Delay for a Net . . . . . . . . . . . . . . . . . . 20
Accessing the Min and Max Propagation Delays Worksheet . . . . . . . . . . . . . . . . . . . 20
Navigating to a Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Setting Values for Propagation Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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Viewing the Constraint on the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Setting the Propagation Delay Relative to Another Net . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Setting Differential Pair Constraints on a Pair of Nets . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Creating a Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Setting Constraints on a Differential Pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Viewing Nets in Canonical and Physical Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
What’s Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3
Setting Timing and Signal Integrity Constraints on Nets. . . . . 45
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Nature of Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Estimated Completion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Setting Timing Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Controlling the Settle and Switch Time of a Signal . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Setting Signal Integrity Constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Setting the Electrical Properties of a Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Setting Reflection Constraints for a Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
What’s Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4
Working with Electrical Constraint Sets . . . . . . . . . . . . . . . . . . . . . . . . 57
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Nature of Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Estimated Completion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Creating an ECSet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

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Assigning an ECSet to a Net . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Overriding Default Values of Constraints in an ECSet . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Viewing an ECSet on the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
What’s Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

5
Working with Xnets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Nature of Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Estimated Completion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Creating an Xnet in Design Entry HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Creating a Model-Defined Diff-Pair in Design Entry HDL . . . . . . . . . . . . . . . . . . . . . . . . 74
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Viewing an Xnet in Constraint Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Generating an Electrical Constraint on an Xnet in SigXplorer . . . . . . . . . . . . . . . . . . . . . 77
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Applying an ECSet on an Xnet to Other Xnets in Constraint Manager . . . . . . . . . . . . . . 81
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

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What’s Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

6
Performing ECOs in Design Entry HDL/Constraint Manager 87
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Nature of Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Estimated Completion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Adding a Net in the Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Modifying a Constraint in Design Entry HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Modifying a Constraint in Constraint Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Deleting a Constraint in Constraint Manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Renaming a Net in Design Entry HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
What’s Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

7
Synchronizing Constraints Between Schematic and Board 105
Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Nature of Chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Estimated Completion Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Exporting Constraints from Design Entry HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

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Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Starting PCB Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Viewing and Adding Constraints in PCB Editor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Importing Constraints in Design Entry HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Viewing Constraints in Design Entry HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Task Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Steps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Two Modes of Synchronizing Constraints between the Board and the Schematic . . . . 113
Overwriting Constraints on the Board with Constraints on the Schematic . . . . . . . . 114
Importing Constraints Changed on the Board in the Schematic . . . . . . . . . . . . . . . 119
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
What’s Next . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Recommended Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122

A
Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

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1
Introduction to the Tutorial

Objectives
■ State the purpose of the Allegro Constraint Manager with Design Entry HDL tutorial.
■ Define the audience for the Allegro Constraint Manager with Design Entry HDL tutorial.
■ Identify the prerequisites for using the Allegro Constraint Manager with Design Entry
HDL tutorial.
■ Identify the advantages of using Allegro Constraint Manager with Design Entry HDL.
■ Identify the tools required to run the tutorial.
■ Copy the design used in the tutorial to your machine.
■ List the important directories and files in the design.

Nature of Chapter
Conceptual

Estimated Completion Time

30 minutes

Purpose
The Allegro Constraint Manager with Design Entry HDL Tutorial describes the different types
of electrical constraints that you can capture in Constraint Manager. You learn to capture
them in Constraint Manager and keep them synchronized in Design Entry HDL. The tutorial
also highlights the tight integration between Constraint Manager, Design Entry HDL, and PCB

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Editor. You set constraints while creating the schematic in Design Entry HDL and then
propagate them to the board in PCB Editor through Constraint Manager.

A constraint is a user-defined restriction applied to an object when it is routed and placed on

the board. An electrical constraint (EC) restricts the electrical behavior of an object on the
printed circuit board. For example, you can specify that a net can have a maximum
propagation delay of 2 ns for a circuit to function properly.

The tutorial focuses on the following procedures:

■ Capturing ECs in Constraint Manager.
■ Performing Engineering Change Orders (ECOs) in Design Entry HDL and Constraint
Manager.
■ Propagating ECs back and forth between Design Entry HDL and PCB Editor.

Audience
This tutorial is designed for first-time users of Constraint Manager from Design Entry HDL. If
you are a schematic designer, you might want to capture ECs while implementing the logic of
your design. Constraint Manager, when connected to Design Entry HDL, helps you capture
these constraints and ensures that the properties in Design Entry HDL are synchronized with
their corresponding electrical constraints in Constraint Manager, and conversely.

Prerequisites
It is assumed that you are familiar with Design Entry HDL and PCB Editor but not with
Constraint Manager. The scope of this tutorial does not include details of various modes and
properties in Design Entry HDL or PCB Editor but will cover Constraint Manager procedures
in detail.
Note: To learn about Design Entry HDL or PCB Editor, see the Allegro Design Entry HDL
User Guide and the Allegro PCB and Package User Guide: Getting Started with
Physical Design in CDSDoc.

Tip
To quickly understand the main features of the Design Entry HDL Constraint
Manager flow for Cadence PCB tools, click here. You can also access the demos by
selecting Help > Learning Design Entry HDL> Demos in Design Entry HDL.

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Advantages of Using Constraint Manager with Design

Entry HDL
Until release14.2 , you used the Attributes dialog box in Design Entry HDL to set restrictions
in the form of properties on objects. A property was captured as a name-value pair. This
required that you know the syntax of properties, which in many cases was quite cumbersome.
No syntax checking was done while the property was being added and a property with
incorrect syntax was not added on to an object. As a result, multiple rounds were sometimes
required to add one property.

Constraint Manager is a spreadsheet-based application with a very easy-to-use interface for

entering constraints, which are equivalent to Design Entry HDL properties. It checks the
syntax of a constraint while it is being added, thus simplifying your task.

Another advantage of using Constraint Manager is that it allows you to create generic
constraints that you can apply to many nets at the same time. At a later point in time, if your
design requirements change, you can edit the generic rule. The updated rule will
automatically get applied to the nets that refer to it.

Using the Tutorial

To use the Allegro Constraint Manager with Design Entry HDL tutorial, you need the following
tools and Tutorial Database:
■ Allegro Project Manager
■ Design Entry HDL
■ Constraint Manager
■ Signal Explorer
■ PCB Editor

Important
The Allegro PCB Design HDL 610 suite contains all these tools.

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Tutorial Database

Windows NT

Unzip the project.zip file located at <your_inst_dir>/doc/conCM_tut/

tutorial_examples, and extract it to an empty directory, say design. This directory will
serve as the database directory for this tutorial.

UNIX

Uncompress and untar the project.tar file located at <your_inst_dir>/doc/

conCM_tut/tutorial_examples, and extract the information to an empty directory, say
design. This directory will serve as the database directory for this tutorial.

Setting the CONCEPT_INST_DIR Variable

Ensure that the CONCEPT_INST_DIR variable is set to point to the directory where you install
PCB tools.

Understanding the Tutorial Database Structure

The design database consists of the following directories and files:

Directory/File Purpose
worklib This is the project directory that contains all the schematics in the design.
ps0 is the top-level schematic.
lib This directory contains all the libraries that have been used in creating the
design.
part_tables This directory contains the part table files for components instantiated in
the design.
temp This directory contains the temporary files that are created when you run
various tools.
cds.lib This file defines the libraries that tools read to identify the libraries they
can use. This file maps user library names to physical directory paths.
project.cpm This is the Design Entry HDL project file.

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Summary
The Allegro Constraint Manager with Design Entry HDL Tutorial should be used by schematic
designers who want to capture high-speed constraints while implementing the logic of the
design. Constraint Manager lets you set constraints in a convenient, faster and error-free
manner.

To run the tutorial, you need to unzip the design files and copy them to your machine. The
design files contain the schematics and files required to run the procedures explained in this
tutorial.

What’s Next
In the next chapter, Setting Routing Constraints on Nets, you will use Constraint Manager with
Design Entry HDL for setting routing constraints. You will set the propagation delay constraint
for a net, create pin-pairs, differential pairs and matched groups, and set constraints on them.
You will also learn to view nets in canonical and physical formats in Constraint Manager.

Recommended Reading
For more information about the Constraint Manager tool, see the Constraint Manager
Design Guide. For information about how high-speed constraints are handled in the PCB
flow, see PCB Design Flows.

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2
Setting Routing Constraints on Nets

Objectives
To learn how to set routing constraints on nets in your design using Constraint Manager and
view the constraints in Design Entry HDL.

At the end of the lesson, you will be able to

■ Set the minimum and maximum delay for a net.
■ Navigate to a net.
■ Create a pin-pair.
■ Create a matched group.
■ Set the delay for a net relative to another net.
■ Create a differential pair.
■ Set constraints on a differential pair.
■ View a constraint in Design Entry HDL.
■ View nets in physical and canonical format.

Nature of Chapter
Skill ( includes concepts and practice)

Estimated Completion Time

1.5 hours

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Starting Design Entry HDL

Task Overview
You will start Project Manager and open the project.cpm file in it. Then you will start Design
Entry HDL and view the schematic in it.

Steps
1. In Unix, launch Project Manager by typing the following command in the command
window:
projmgr

-Or-
On Windows, launch Project Manager from Programs > Allegro SPB 15.2 > Project
Manager.
The Project Manager Product Choices window is displayed.
Note: If you have set the default suite previously, the Design Entry HDL window opens
automatically and you can skip step 2.
2. Select Allegro PCB Design HDL 610.
The Allegro PCB Design HDL 610: Allegro Project Manager window appears.
3. Open the project.cpm project file.
4. Click the Design Entry icon.

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The Design Entry HDL window opens showing the schematic for project.cpm as
follows:

Starting Constraint Manager

Task Overview
You will start Constraint Manager from Design Entry HDL and capture constraints on some
nets in the schematic.

Steps
1. From Design Entry HDL, choose Tools > Constraints > Edit.

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The Constraint Manager dialog box appears to prompt you that using Constraint
Manager with Design Entry HDL is compatible only with Allegro PCB Editor and Allegro
SI version 15.2.

2. Click the Don’t show me the message again checkbox.

3. Click OK.
The Constraint Manager dialog box closes. Design Entry HDL prompts you to expand the
design to obtain connectivity information for Constraint Manager.
4. Click Yes.

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After the design is expanded, the Constraint Manager window is displayed over the
Design Entry HDL window as shown below:

Use this workbook of Constraint Manager

to create generic constraint rules
for multiple nets.

Use this workbook of Constraint Manager

to add constraints on individual nets
and buses.

Note: The title bar of the Constraint Manager window shows that Constraint Manager is
connected to Allegro Design Entry HDL. This implies that all the constraints captured in
it will be reflected in Design Entry HDL.

For details on the Constraint Manager user interface, refer chapter “Introducing Constraint
Manager” of the Constraint Manager Design Guide.
Note: Now try this interactive exercise, Starting Constraint Manager.

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Setting the Maximum and Minimum Propagation Delay for

a Net
While designing the schematic for your design, you might have several design constraints
such as length and impedance on the critical nets in the design. These constraints might have
been given to you by the Signal Integrity engineer. These translate to the length of critical nets
and therefore to the propagation delay of the signals passing through them.

Accessing the Min and Max Propagation Delays Worksheet

Task Overview

You will now set the minimum and maximum Propagation Delay for the net HLDA. This
constraint is present in the Routing worksheet in the Net workbook.

Steps
1. In the Net workbook, click Routing.

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The routing worksheet appears. All the nets and the buses in the ps0 design are listed
in the worksheet in the right pane.

Buses and nets in the design.

Tabs for various routing constraints.

Note: You can see that the nets are listed in their physical format. This is the default
format of display in Constraint Manager if your design is packaged. If your design is not
packaged, the nets are displayed in the canonical format. Switching between the two
formats is covered later in this chapter.
2. Double-click Routing to expand the workbook.
Notice the Wiring, Impedance, Min/Max Propagation Delays, Total Etch Length,
Differential Pair and Relative Propagation Delay tabs in this workbook.
3. Click Min/Max Propagation Delays to open the respective worksheet.
4. Size the worksheet to occupy the full window.

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Navigating to a Net
When Constraint Manager is launched from Design Entry HDL, you can click an object in
Design Entry HDL and it will become highlighted in Constraint Manager. The converse is also
true.

Task Overview

You will locate net HLDA in Design Entry HDL and highlight it, and it will get selected in
Constraint Manager automatically.

Steps
1. In Design Entry HDL, choose Tools > Global Find.
The Global Find dialog box appears.
2. Enter the net name as HLDA. Make sure that the Net checkbox is selected.
3. Click Find.
The instance of the net HLDA is displayed in the Results area of the Global Find dialog
box.
4. Click @project_lib.ps0(sch_1):page1_hlda.

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The net gets selected in the Design Entry HDL window as follows:

5. Click Close in the Global Find dialog box.

The Global Find dialog box closes.
6. Click the net HLDA in the Design Entry HDL window.
7. Click the Constraint Manager window.
The net HLDA is selected.
Note: Now try this interactive exercise, Navigating to a Net.

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Setting Values for Propagation Delay

Depending on the requirement, the Signal Integrity engineer might give you the maximum
and minimum allowed length of critical nets. You can accordingly set the maximum and
minimum propagation delays of those nets.

It is possible that for a certain critical net, you might have to set the constraint on all its driver
and receiver ends or specific pin pairs. In the following section, we will learn how to set the
constraint for the entire net and also for a specific driver-receiver pair.

Task Overview

We will be setting the maximum and minimum values for propagation delay on net HLDA.
First, we will set the delay between all the drivers and receivers of net HLDA. Then, for a
specific driver and receiver pair, we will set a different value for the propagation delay.

Steps
1. For net HLDA, do the following:

a. In the Prop Delay column, type the Min value as 0.9.

Note: The unit for the minimum propagation delay is set to ns, which is the default unit.
This means that the signal on the net HLDA must have a propagation delay of at least
0.9 ns before it reaches any destination.

Important
Note that in the Pin Pairs column, All Drivers/All Receivers gets selected
automatically. This means that the propagation delay has been set between all the
drivers and receivers of the signal on net HLDA.

a. In the Prop Delay column, type the Max value as 1.1.

Note: The unit for maximum propagation delay is set to ns, which is the default unit.

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This means that the signal on the net HLDA must reach any destination within 1.1 ns
after it is available on the net HLDA.

2. Click net HLDA and choose Objects > Create > PinPair from the Constraint Manager
menu or right-click net HLDA and choose Create > Pin Pair from the popup menu.
The Create Pin Pairs of HLDA for propagation delay dialog box appears. It contains two
columns. The First Pins and Second Pins columns list the pins for net HLDA.
3. In the First Pins column, click J1.25(In).

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4. In the Second Pins column, click U2.3(Out).

5. Click OK.
The pin-pair J1.25:U2.3 is formed and is visible under the net HLDA in the Constraint
Manager window.
Note: The values in the Min and Max columns for the pin-pair are inherited from the
existing constraint on net HLDA.
6. Change the value in the Min column from 0.9 ns to 0.8 ns.
7. Change the value in the Max column from 1.1 ns to 1.0 ns.

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The worksheet appears as shown below:

Changed Min Prop Delay and

Max Prop Delay for the pin-pair.

8. Choose File > Save to save the constraints in the Constraint Manager database.
Note: Now try this interactive exercise, Creating a Pin Pair.

Viewing the Constraint on the Schematic

The constraint that you have added in Constraint Manager is added as an electrical constraint
property in the occurrence property file of the design. For example, the Min/Max
propagation delay constraint maps to the PROPAGATION_DELAY electrical constraint
property. For all mappings between constraints and properties, refer Appendix B, “Property
Mapping” of the Constraint Manager User Guide.

The constraint will not be automatically visible in Design Entry HDL. To view the constraint on
the schematic, make the corresponding electrical constraint property visible using the
Attributes dialog box in Design Entry HDL.
Note: You can also propagate the electrical constraint property from the occurrence edit
mode to the hierarchy mode.

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Task Overview

The Min/Max propagation delay constraint maps to the PROPAGATION_DELAY electrical

constraint property. You will now make the PROPAGATION_DELAY property visible in Design
Entry HDL and view its value in the occurrence edit mode. Then you will propagate the
PROPAGATION_DELAY property to the canvas.

Steps
1. Click the Design Entry HDL window.
2. Choose Tools > Occurrence Edit to switch to the occurrence edit mode in Design Entry
HDL.
3. Choose Text > Attributes.
4. Click net HLDA.
The Attributes dialog box appears. You can see the PROPAGATION_DELAY property.
Its two values (one for all drivers and all receivers in the format AD:AR:min:max and the
second for a specific driver-receiver pair) are concatenated and the visibility is set to
None in the Attributes dialog box.
5. In the Visible drop-down list next to the PROPAGATION_DELAY property, set the
visibility of the PROPAGATION_DELAY property to Both as shown below.

Select Both to display the property

name and value on the schematic.

Note: You can select Name or Value to make only the property name or the property

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value visible.
6. Click OK.
The Attributes dialog box closes.
7. Zoom into the portion of the schematic where the net HLDA is placed.
The PROPAGATION_DELAY property appears as follows:

8. Choose Tools > Constraints > Update Schematic.

Design Entry HDL prompts you to save the schematic.
9. Click Yes.
Constraint Manager propagates the property to the canvas.

Tip
You can switch to the hierarchy mode and view the PROPAGATION_DELAY property
on the net. However, if you switch to the hierarchy mode while Constraint Manager
is running, Constraint Manager exits.
Note: Now try this interactive exercise, Creating and Viewing a Constraint in Design Entry
HDL.

Setting the Propagation Delay Relative to Another Net

You can set the propagation delay of a net or pin-pair relative to the propagation delay of
another net. All these nets/pin-pairs can then be grouped together to form a matched group.
The group is characterized by a target pin-pair/net, a delta value, and a tolerance value. For
details on matched groups, refer section “Working with Match Groups” of the Constraint
Manager Design Guide.

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Task Overview
We will set the propagation delay for the target net D<0> and create a matched group for it.
Then, we will add nets D<14> and D<15> to the matched group and set their propagation
delay relative to net D<0>.

Steps
We will carry out the following steps:
1. Setting the Minimum and Maximum Propagation Delay for the Target Net
2. Creating a Matched Group
3. Adding nets D<14> and D<15> to the match group
4. Setting relative propagation delay values for the nets D<14> and D<15>

Setting the Minimum and Maximum Propagation Delay for the Target Net
1. Click the Constraint Manager window.
2. Click the icon next to bus D in the Min/Max Propagation Delays worksheet.
The bits in bus D are shown.
3. For bit D<0>, in the Min column, type the value as 1.0.
4. For bit D<0>, in the Max column, type the value as 1.2.

Creating a Matched Group

1. Click Relative Propagation Delay in the Routing constraint.
The Relative Propagation Delay worksheet appears in the right pane.
2. Click the icon next to bus D in the worksheet.
The bits in bus D are shown.
3. Click bit D<0> and choose Objects > Create > Match Group from the Constraint
Manager menu or right-click bit D<0> and choose Create > Match Group from the
popup menu.
The Create Match Group dialog box appears. It contains the bit D<0> in the Selections
field indicating that this net is a member of the matched group.

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Tip
You can also create an empty match group at the design-level using the menu option
Objects > Create > Match Group first and add all the members of the group later.
4. Enter the name of the match group as MY_GROUP in the Match Group field as follows:

5. Click OK.
The Create Match Group dialog box closes.

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6. Scroll up the list of nets to see the entry MY_GROUP under the ps0 design in the
worksheet as follows:

D<0> inherits the constraints in MY_GROUP.

Note: The net D<0> appears under MY_GROUP indicating that it is a member of the
group.
Note: Now try this interactive exercise, Creating a Matched Group.

Adding Nets to a Matched Group

1. Right-click MY_GROUP.
The popup menu appears.
2. Choose Membership > Match Group.

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The Match Group Membership for MY_GROUP dialog box appears with net D<0> as a
member as follows:

3. In the All Nets column, scroll down and click D<14>.

4. Click to move the selected net D<14> to the Members column.
5. Repeat steps 3 and 4 for net D<15>.
Now, the 3 nets D<0>, D<14> and D<15> are members of the match group MY_GROUP.
6. Click OK.

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The Match Group Membership for MY_GROUP dialog box closes and nets D<0>, D<14>
and D<15> appear under MY_GROUP in the Constraint Manager worksheet as follows:

D<0>, D<14>, and D<15> inherit

the constraints in MY_GROUP.

Setting Relative Propagation Delay Values for Nets

1. For net D<0>, perform the following steps:

a. In the Scope column, select Global from the drop-down box.

This matches all pin-pairs in the match group.
In the Pin Pairs column, All Drivers/All Receivers gets selected.

b. In the Delta:Tolerance field, the value is automatically set to 0 ns:5%.

The delta value zero for net D<0> makes Constraint Manager select this net as the
target net. The minimum and maximum propagation delay values for nets D<14>
and D<15> are set relative to that of net D<0>.
The default unit for delta is ns and for tolerance is percentage. You can specify
tolerance in ns also.
2. For net D<14>, perform the following steps:

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a. In the Scope column, select Global.

b. In the Pin Pairs column, All Drivers/All Receivers gets selected automatically.
Select Longest Pin Pair from the drop-down box.
A constraint when set on the longest pin-pair of a net is most stringent. If the
constraint is met by the longest pin-pair, it is ensured that the constraint will be met
by all other pin-pairs of the net also.

c. In the Delta:Tolerance field, specify the value as 0.3 ns:5%.

This means that the travel time for the signal on net D<14> must be 0.3 ns more than
that for the signal on net D<0> within a tolerance of +/- 5%.
3. For net D<15>, perform the following steps:

a. In the Scope column, select Global.

In the Pin Pairs column, All Drivers/All Receivers gets selected.

b. In the Delta:Tolerance field, specify the value as -0.03 ns:0.06 ns.

This means that the travel time for the signal on net D<15> must be 0.03ns less than
that for the signal on net D<0> within a tolerance of +/- 0.06ns.
The worksheet appears as follows:

4. Choose File > Save to save the constraints in the Constraint Manager database.
Note: The Relative Propagation Delay constraint maps to the
RELATIVE_PROPAGATION_DELAY property in Design Entry HDL.

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Setting Differential Pair Constraints on a Pair of Nets

You can create a Differential Pair for nets and set constraints on them so that the Auto Router
routes them accordingly.

Creating a Differential Pair

Task Overview

You will now create a differential pair constituting nets CLK1+ and CLK1-.

Steps
1. Click the Constraint Manager window.
2. In the Routing workbook, click Differential Pair.
The Differential Pair worksheet appears on the right side of the Constraint Manager
window.
3. Select nets CLK1+ and CLK1-.
4. Choose Objects > Create > Differential Pair from the Constraint Manager menu or
right-click and choose Create > Differential Pair from the popup menu.
5. The Create Differential Pair dialog box appears.
It contains nets CLK1+ and CLK1- in the Selections column indicating that these nets
are members of the differential pair. The name of the differential pair appears
automatically as CLK1 in the Diff Pair Name field.
Note: If the nets forming a differential pair are of the form A+ and A-, the name of the
differential pair is set to A. For other pairs of nets, the name of the differential pair is of
the form DPn.
6. Click Create.

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The Create Differential Pair dialog box appears as follows:

7. Click Close.
The Create Differential Pair dialog box closes.
8. Scroll up the list of nets in the worksheet to see the entry for differential pair CLK1 with
CLK1+ and CLK1- as its members as follows:

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9. Choose File > Save to save the constraints in the Constraint Manager database.
The Differential Pair constraint gets mapped to the DIFFERENTIAL_PAIR property in
Design Entry HDL.
10. Click the Design Entry HDL window.
11. Make the DIFFERENTIAL_PAIR property visible for nets CLK1+ and CLK1- as
explained earlier.
12. Choose Tools > Constraints > Update Schematic.
The newly added constraints are visible on the schematic in hierarchy mode also.
Note: Now try this interactive exercise, Creating a Differential Pair.

Setting Constraints on a Differential Pair

Task Overview

You will set constraints on the differential pair CLK1. These constraints will get inherited by
the member nets CLK1+ and CLK1- automatically.
Note: Differential pair constraints present in the Differential Pair worksheet can be applied
to only differential pairs and not to individual members of the differential pair.

Important
The constraints added on differential pairs in Constraint Manager are saved only in
the Constraint Manager database. They are not propagated to Design Entry HDL,
hence you cannot view them on the schematic.

Steps
1. Click the Constraint Manager window and perform the following steps for differential pair
CLK1.
2. In the Uncoupled Length column-

a. Select the value of Gather Control as Ignore.

The value of Gather Control determines whether to Ignore or to Include the
uncoupled length that occurs before the etch gathers at the pins.

b. Set the value of Max as 200.

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This sets the maximum amount of uncoupled length to 200 mil, where mil is the
default unit.
3. In the Phase Tolerance column-

a. Set the value of Tolerance as 0.2 ns.

This matches the travel time for each signal of the differential pair to within the
specified Tolerance.
4. In the Line Spacing column-

a. Set the value of Min as 6 mil.

This sets the minimum etch to etch spacing for the differential pair to 6 mil. If this
value is not set, the default net spacing rule is used.
5. In the Coupling column-

a. Set the value of Primary Gap as 8 mil.

This sets the optimal distance between the pair of nets in the differential pair to 8 mil.

b. Set the value of Primary Width as 6 mil.

This sets the line width for the differential pair to 6 mil.

c. Set the value of Neck Gap as 4 mil.

This sets the allowed distance between the two nets of the differential pair if the etch
needs to neck-down to get through the pins.

d. Set the value of Neck Width as 6 mil.

This sets the allowed line width for the differential pair if the etch needs to neck-down
to get through the pins.

e. Set the value of (+) Tolerance as 2 mil.

This sets the positive tolerance when the optimal Primary Gap cannot be met.

f. Set the value of (-) Tolerance as 2 mil

This sets the negative tolerance when the optimal Primary Gap cannot be met.
6. Choose File > Save to save the constraint in the Constraint Manager database.

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Viewing Nets in Canonical and Physical Format

If you start Constraint Manager from Design Entry HDL before packaging the design, the net
names are displayed in Constraint Manager in the canonical (logical) format by default. For
example, the bus D<15..0> appears as follows:

The entry @project_lib.ps0(sch_1):d means that the bus D<15..0> is on the

schematic view of the cell ps0. The cell ps0 is located in the project_lib library in the
project. The 16 bits of the bus are displayed as follows:
@project_lib.ps0(sch_1):d(0)
@project_lib.ps0(sch_1):d(1)
@project_lib.ps0(sch_1):d(2)
.
.
.
@project_lib.ps0(sch_1):d(15)

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After you package the design, the nets are displayed in Constraint Manager in their physical
(packaged) net names. Continuing the same example, bus D<15..0> appears as follows:

Note: After your design is packaged, you can view the nets in their canonical format as well.
To switch between the two formats-
1. From the Constraint Manager menu, choose View > Options.

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The View Options dialog box appears as follows:

Choose between Physical

and Logical net names.

a. Toggle between the Physical and Logical settings to see the effect. Select
Physical before closing the dialog box.

Tip
You can add constraints on nets before you have packaged your design. These
constraints are retained after you package the design.

Summary
You learned to create driver-receiver pin pairs and differential pairs for nets and set some
DRC-based constraints on them. You also learned to cross-probe between Design Entry HDL
and Constraint Manager and view nets in canonical or physical format in Constraint Manager.

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What’s Next
In the next chapter, Setting Timing and Signal Integrity Constraints on Nets, you will set some
timing and signal integrity constraints on critical nets. These are constraints that you would
get after simulating the design. You will also view these constraints on the schematic.

Recommended Reading
For more information about how pin-pair and differential pair constraints are handled in
Design Entry HDL, see the Allegro Design Entry HDL User Guide.

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Setting Timing and Signal Integrity
Constraints on Nets

Objectives
To learn how to set timing and signal integrity constraints on nets in your design using
Constraint Manager and view those constraints on the schematic in Design Entry HDL.

At the end of the lesson, you will be able to

■ Set the switch and settle time for a signal.
■ Control the electrical properties of a signal.
■ Set the maximum overshoot of a signal.
■ Set the noise margin for a signal.

Nature of Chapter
Skill ( includes concepts and practice)

Estimated Completion Time

30 minutes

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Setting Timing Constraints

You will now learn how to set the following timing constraints on nets in your design:
■ Settle time
■ Switch time

Controlling the Settle and Switch Time of a Signal

Task Overview

You will navigate to the RESETL net and add the settle and switch time constraints on it. Then,
you will save the constraints and view the corresponding properties on the schematic.

Steps
1. Accessing the Switch and Settle Delay Worksheet
2. Navigating to a Net
3. Setting Values for Min First Switch and Max Final Settle
4. Viewing the Constraint on the Schematic

Accessing the Switch and Settle Delay Worksheet

1. In the Net folder of the worksheet selector, click Timing.

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The timing worksheet appears. All the nets and the buses in the ps0 design are listed in
the worksheet in the right pane.

Tabs for various timing constraints.

2. Double-click Timing to expand the workbook.

Notice the Switch/Settle Delays and Setup/Hold tabs in this workbook.
3. Click Switch/Settle Delays.
4. Size the worksheet to occupy the full window.

Navigating to a Net

Task Overview

You will highlight net RESETL in Design Entry HDL and it will get selected in Constraint
Manager.

Steps
1. In Design Entry HDL, choose Tools > Global Find.
The Global Find dialog box appears.

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2. Enter the net name as RESETL. Make sure that the Net checkbox is selected.
3. Click Find.
The instances of net RESETL are displayed in the Results area of the Global Find dialog
box.
4. Click @project_lib.ps0(sch_1):page1_resetl.
The net gets selected in the Design Entry HDL window as follows:

Click this instance

of net RESETL.

5. Click Close in the Global Find dialog box.

The Global Find dialog box closes.
6. Click the RESETL net in the Design Entry HDL window.
7. Click the Constraint Manager window.
The net RESETL is selected.

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Setting Values for Min First Switch and Max Final Settle

Steps
1. In the Min First Switch column, set the Min value as 0.25:0.26 in the row selected
for net RESETL.
This sets the value for rising edge of signal on net RESETL as 0.25 ns and falling edge
as 0.26 ns. The default unit for min first switch is ns.
2. In the Max Final Settle column, set the Max value as 3.25:3.25 in the row selected
for net RESETL.
This sets the value for maximum final settle delay for the rising edge and the falling edge
of net RESETL as 3.25 ns. The default unit for max final settle is ns.
The Constraint Manager worksheet now appears as follows:

Constraint Min First Switch Constraint Max Final Settle

for net RESETL. for net RESETL.

3. Choose File > Save to save the constraints in the Constraint Manager database.

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Viewing the Constraint on the Schematic

The Min First Switch constraint gets mapped to the MIN_FIRST_SWITCH property in
Design Entry HDL and the Max Final Settle constraint gets mapped to the
MAX_FINAL_SETTLE property.

Task Overview

You will now make the MIN_FIRST_SWITCH and MAX_FINAL_SETTLE properties on net
RESETL visible in Design Entry HDL and view their values in the expanded mode.

Steps
1. Click the Design Entry HDL window.
2. Choose Text > Attributes.
3. Click the net RESETL.
The Attributes dialog box appears. You can see the MIN_FIRST_SWITCH and
MAX_FINAL_SETTLE properties with visibility set to None in the Attributes dialog box.
4. In the Visible drop-down list next to the MIN_FIRST_SWITCH property, select the
visibility of the MIN_FIRST_SWITCH property as Both.

5. Repeat step 4 for the MAX_FINAL_SETTLE property.

6. Click OK.
The Attributes dialog box closes.
7. You might switch to the occurrence edit mode and view the properties.
You are prompted to save the changes.

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a. Click Yes.
The constraints appear as shown below:

Setting Signal Integrity Constraints

You will now learn how to set the following constraints on nets in your design:
■ Electrical Properties
■ Reflection constraints, maximum Overshoot and Noise Margin

Setting the Electrical Properties of a Signal

Task Overview

You will set the electrical properties constraints for net CLK. Then, you will save the
constraints and view the corresponding properties on the schematic.

Steps
1. Click the Constraint Manager window.
2. In the Net folder of the worksheet selector, click Signal Integrity.

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The signal integrity worksheet appears. All the nets and the buses in the ps0 design are
listed in the worksheet in the right pane.

Tabs for various signal integrity constraints.

3. Double-click Signal Integrity to expand the workbook.

Notice the Electrical Properties, Reflection, Edge Distortions, Estimated XTalk,
Simulated XTalk and SSN tabs in this workbook.
4. Click Electrical Properties.
5. Scroll down to net CLK in the Signal Integrity worksheet.
6. Set the value as 66 in the Frequency column in the row selected for net CLK. The unit
for frequency is set to MHz.
The value of Period is set automatically when you enter the frequency of the signal. The
default unit is ns.
7. The default value of Duty Cycle is 50%. Set the value as 60%.
8. The default value of Jitter is 0. Set the value as 20. The default unit for jitter is ps.
9. The default value of Cycle to Measure is 1. Set the value as 2.

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The Constraint Manager worksheet now appears as follows:

Electrical properties
for net CLK.

10. Choose File > Save to save the constraints in the Constraint Manager database.
The frequency, period, jitter, duty cycle and cycle to measure constraints get mapped to
the PULSE_PARAM property in Design Entry HDL.
11. Click the Design Entry HDL window.
12. Choose Tools > Global Navigate.
13. Switch to the Constraint Manager window. Size it such that the Design Entry HDL
window is also visible in the background.
14. Right-click net CLK.
The popup menu appears.
15. Choose Select.
The entry for CLK appears as
@project_lib.ps0(sch_1):page3_i1@project_lib.\4_bit_counter\(sch_1):page1_
clk in the Results field of the Global Navigate dialog box.

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16. Click the entry

@project_lib.ps0(sch_1):page3_i1@project_lib.\4_bit_counter\(sch_1):page1_
clk.
The instance of the net on page 1 of the 4_BIT_COUNTER design gets highlighted in the
Design Entry HDL window.
17. Close the Global Navigate dialog box.
18. Make the PULSE_PARAM property visible on the schematic.
19. Propagate the PULSE_PARAM property to the canvas.
The property PULSE_PARAM appears as follows:

Setting Reflection Constraints for a Signal

Task Overview

You will set the Reflection constraints for net CLK. Then, you will save the constraints and view
the corresponding properties on the schematic.

Steps
1. In the Constraint Manager window, click Reflection.

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The Reflection worksheet appears as follows:

2. Size the worksheet to occupy the full window.

3. Scroll down the Signal Integrity worksheet to net CLK.
4. Set the Overshoot as
a. Set the value as 5100:-610 in the Max column. The default unit for max overshoot
is mV.
This sets the value of maximum overshoot for the rising edge of net CLK to 5100mV
and value of maximum overshoot for the falling edge of net CLK to 610mV.
The value for High Actual is set at the time of analysis in Allegro SI/PCB Editor. You
cannot set it in Constraint Manager connected with Design Entry HDL.
The value for Low Actual is set at the time of analysis in Allegro SI/PCB Editor. You
cannot set it in Constraint Manager connected with Design Entry HDL.
The value for Margin is set at the time of analysis in Allegro SI/PCB Editor. You
cannot set it in Constraint Manager connected with Design Entry HDL.
5. Set the Noise Margin as

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a. Set the value as 100:100 in the Min column. The default unit for min noise margin
is mV.
This sets the value of the minimum noise margin for the rising and falling edges of
net CLK to 100 mV.
The value for High Actual is set at the time of analysis in Allegro SI/PCB Editor. You
cannot set it in Constraint Manager connected with Design Entry HDL.
The value for Low Actual is set at the time of analysis in Allegro SI/PCB Editor. You
cannot set it in Constraint Manager connected with Design Entry HDL.
The value for Margin is set at the time of analysis in Allegro SI/PCB Editor. You
cannot set it in Constraint Manager connected with Design Entry HDL.
6. Choose File > Save to save the constraints in the Constraint Manager database.
The maximum overshoot constraint in Constraint Manager maps to the
MAX_OVERSHOOT property in Design Entry HDL and minimum noise margin maps to
MIN_NOISE_MARGIN.
7. Click the Design Entry HDL window.
8. Make the MAX_OVERSHOOT and MIN_NOISE_MARGIN properties visible in Design Entry
HDL.

Summary
You learned to set some simulation-based constraints on nets in Constraint Manager. You
also learned the correspondence between those constraints and properties in Design Entry
HDL, and made the properties visible on the canvas.

What’s Next
In the next chapter, Working with Electrical Constraint Sets, you will learn to group constraints
into an electrical constraint set (ECSet) and apply them to several critical nets at the same
time. You will also see how an ECSet appears in Design Entry HDL and how to change some
constraints that are part of an ECSet.

Recommended Reading
For information about all the timing and signal integrity constraints that you can set in
Constraint Manager, see the Constraint Manager Design Guide.

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4
Working with Electrical Constraint Sets

Objectives
To learn how to create an Electrical Constraint Set (ECSet) and apply it to nets and buses in
your design using Constraint Manager.

At the end of the lesson, you will be able to

■ Decide when to use an ECSet.
■ Create an ECSet.
■ Assign an ECSet to a net.
■ Override values of constraints in an ECSet.
■ View an ECSet in Design Entry HDL.

Nature of Chapter
Skill ( includes concepts and practice)

Estimated Completion Time

40 minutes

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Overview
You can identify the critical nets in your design and then identify constraints that are
applicable to all of them. You can then define those constraints together in an ECSet and
apply to each of the critical sets. Thus, an ECSet can be used to define a generic set of rules
applicable to a number of nets. If your design requirement changes at a later point in time,
you can edit your constraint; all the nets referencing the ECSet shall inherit the changed
ECSet automatically. Thus, using ECSets is a very efficient way of capturing constraints.

Another use of ECSets is in the case of design reuse. If you are reusing a design that has
ECSets defined for its critical nets, you can import the ECSets into your new design; this
saves a lot of rework.

You can also use ECSets for setting pin-pair constraints on the bits of a large bus. This is a
faster and easier way of doing so. You can set the pin-pair constraints on one bit of the bus
and create an ECSet from them in Signal Explorer. Then, make the bits of the bus reference
this ECSet. Constraint Manager will automatically create the corresponding pin-pairs for the
bits and make them visible in Constraint Manager connected to PCB Editor.

The main advantages of an ECSet are:

■ One ECSet can be applied to many nets simultaneously.
■ You can capture any or all electrical constraints in one ECSet.
■ A change in a constraint in an ECSet is automatically inherited by the objects that
reference the ECSet.
■ You can override the constraints defined in an ECSet.

We will take the example of the DATA bus and set certain constraints on a bit of the bus in
Signal Explorer. Consequently, an ECSet will be formed in Constraint Manager. We will then
make few other bits of the bus reference this ECSet. We will also override the default values
of constraints for some bits of the DATA bus.

Creating an ECSet

Task Overview
You will capture the following constraints on bit DATA<1> of bus DATA in Signal Explorer:
■ Max overshoot

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■ Min noise margin

■ Min first switch
■ Max final settle
■ Impedance

An ECSet with the above constraints will be formed in Constraint Manager.

Steps
1. Click the Constraint Manager window.
2. Click Reflection in the Signal Integrity workbook.
3. In the Signal Integrity worksheet, click the icon next to net DATA to view the bits of
the bus.
4. Click bit DATA<1> and choose Tools > SigXplorer from the Constraint Manager menu
or right-click net DATA<1> and choose SigXplorer from the popup menu.
The Sigxp Product Choices dialog box appears.

5. Double-click Expert.

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The Allegro PCB SI window appears.

Tip
If the values for overshoot/undershoot and other constraints are not known, you can
simulate and add terminations using the Model Browser. You can then do a tradeoff
between the termination values and the simulated values of overshoots and
undershoots. For details on using the various Signal Explorer features, refer PCB
Studio Signal Explorer User Guide.
6. Choose Set > Constraints.
The Set Topology Constraints window appears.
7. Click the Signal Integrity tab.
8. In the Reflection section,

a. Set the value of High State for Overshoot as 5000.

b. Set the value of Low State for Overshoot as -600.

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c. Set the value of High State for Min Noise Margin as 20.

d. Set the value of Low State for Min Noise Margin as 22.

1.Click for Signal

Integrity constraints.
2.Set High State and
Low State values
for Reflection.

3.Set High State and

Low State values
for Min Noise Margin.

4.Click Apply.

9. Click Apply.
10. Click the Switch-Settle tab.
11. In the Pins section, click ALL DRVRS/RCVRS.
12. In the Rule Editing section,

a. Set the value of Rise in Min First Switch Delays as 2 ns.

b. Set the value of Fall in Min First Switch Delays as 3 ns.

c. Set the value of Rise in Max Final Settle Delays as 5 ns.

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d. Set the value of Fall in Max Final Settle Delays as 6 ns.

1.Click for Switch-

Settle constraints.

2.Click
ALL DRVRS/RCVRS

3.Set Min First

Switch Delays for
rising and
falling edges.

4.Set Max Final

Settle Delays for
rising and
falling edges.
5.Click Add.
6.Click Apply.

13. Click Add.

The constraint that you have created is added in the Existing Rules section.
14. Click Apply.
15. Click the Impedance tab.
16. In the Pins/Tees section, click ALL/ALL.
17. In the Rule Editing section,

a. Set the value of Target as 70 Ohm.

b. Set the value of Tolerance to 2.

18. Click Add.

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The impedance constraint that you have created is added in the Existing Rules section.

1.Click for
Impedance
constraints.

2.Click ALL/ALL.

3.Set Target.

4.Set Tolerance
in Ohms.
5.Click Add.

19. Click OK.

The Set Topology Constraints window closes.
20. Choose File > Update Constraint Manager.
This creates a new ECSet DATA<1> in Constraint Manager for the electrical constraints
that you have set on bit DATA<1> in Signal Explorer.
You are prompted to make net DATA<1> reference the newly created ECSet DATA<1>.

21. Click Yes.

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The ECSet DATA<1> is attached to net DATA<1>.

22. Click All Constraints in the Electrical Constraint Set folder.
You can see the ECSet DATA<1> listed under the design ps0. This means that you can
apply this ECSet to all nets in the design.
23. Scroll right and view all the constraints in the ECSet.

24. View the ECSet referenced by net DATA<1> and the constraints on net DATA<1> in the
Signal Integrity, Timing and Routing worksheets. For example, the Signal Integrity
constraints appear as follows:

Note: Now try this interactive exercise, Creating an ECSet.

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Assigning an ECSet to a Net

Task Overview
You will assign the ECSet DATA<1> to bits DATA<15>, DATA<14>, DATA<13>, and
DATA<12> of bus DATA so that the constraints in DATA<1> are applied to them.

Steps
1. In the Net folder, open the Signal Integrity worksheet for Reflection constraints.
2. Click bit DATA<15> of bus DATA and choose Objects > Electrical CSet References
from the Constraint Manager menu or right-click DATA<15> to bring up the popup menu
and choose Electrical CSet References.
The Electrical CSet References dialog box appears.
3. Select DATA<1> in the Current References field as follows:

4. Click OK.
The Electrical CSet References dialog box closes.

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5. In the Constraint Manager window, view the reflection constraints on bit DATA<15> of
bus DATA.

Note: The Max Overshoot and Min Noise Margin constraints are applied with the
same values as on bit DATA<1>.
6. View the inherited Switch/Settle Delays and Impedance constraints on bit DATA<15>
in the Constraint Manager worksheet.
7. Repeat steps 2 to 7 for bits DATA<14>, DATA<13>, and DATA<12> of bus DATA.

Tip
You can also select multiple nets at the same time by keeping the Ctrl (Control in
the Unix platform) key pressed and clicking the nets in the Constraint Manager
window. Then you can open the Electrical CSet References dialog box and assign
the ECSet to all of them at the same time.
8. Choose File > Save to save the constraints in the Constraint Manager database.

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Overriding Default Values of Constraints in an ECSet

Once you have inherited the constraints from an ECSet with their default values, you can
override the values of some of the constraints for a net if your design has such a requirement.

Task Overview
We will change the values of Impedance and Min First Switch constraint for bit DATA<15> of
bus DATA.

Steps
1. Open the worksheet for Impedance from the Net folder.
2. In the Target field for bit DATA<15> of bus DATA, change the inherited value of 70 Ohm
to 74 Ohm.
The worksheet appears as follows:

3. Go to the worksheet for Switch/Settle Delays.

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4. In the Min First Switch column, change the value of Min from 2:3 ns to 0.5:0.6 ns
for bit DATA<15> of bus DATA.
The worksheet appears as follows:

5. Choose File > Save to save the constraints in the Constraint Manager database.

Viewing an ECSet on the Schematic

An ECSet in Constraint Manager maps to the ELECTRICAL_CONSTRAINT_SET property in
Design Entry HDL. Like other properties, this is also a read-only property in Design Entry
HDL when Constraint Manager is running simultaneously.

Task Overview
You will view the properties on bit DATA<15> of bus DATA in Design Entry HDL.

Steps
1. Switch to the Design Entry HDL window.

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2. Locate bus DATA in the design.

3. Choose Text > Attributes.
4. Click bus DATA.
The Attributes dialog box appears.
5. Select the Show Index option.
Index 1 appears for the bus.
6. Increase the index to 15.
You can see the IMPEDANCE_RULE, MIN_FIRST_SWITCH and
ELECTRICAL_CONSTRAINT_SET properties.

Important
The IMPEDANCE_RULE and MIN_FIRST_SWITCH properties appear separately
because they have values different from the constraints in the ECSet A<1>.

7. Click Cancel.
The Attributes dialog box closes.

Summary
You learned to set constraints on a net in Signal Explorer to form an ECSet. You also learned
to make a net reference an ECSet, and then override some constraints in the ECSet.

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What’s Next
In the next chapter, Working with Xnets, you will create an Xnet in Design Entry HDL, view it
in Constraint Manager, generate electrical constraints on the Xnet in SigXplorer, and apply
the constraints to other Xnets in Constraint Manager

Recommended Reading
For more information about electrical constraint sets, see the Allegro Design Entry HDL
User Guide and the Constraint Manager Design Guide.

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Working with Xnets

Objectives
To learn how to create an extended net (Xnet) in Design Entry HDL, view it in Constraint
Manager, generate electrical constraints on the Xnet in SigXplorer, and apply the constraint
rules to other Xnets in Constraint Manager.

At the end of the lesson, you will be able to:

■ Create an Xnet.
■ Create a model-defined diff-pair.
■ View an Xnet in Constraint Manager.
■ Generate an electrical constraint on the Xnet in SigXplorer.
■ Apply an ECSet on one Xnet to other Xnets in Constraint Manager.

Nature of Chapter
Skill (includes concepts and practice)

Estimated Completion Time

20 minutes

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Overview
When the path of a net traverses a discrete device (resistor, inductor, or capacitor), each net
segment is represented by an individual net entity in the board database. Constraint
Manager, however, interprets these net segments as a contiguous extended net (Xnet). Xnet
creation is based on the presence of the SIGNAL_MODEL property on the discrete
components. This means that to qualify as an Xnet, the discrete component separating the
net into segments must have a valid signal model assigned to it. Design Entry HDL 15.2
includes Signal Integrity analysis features that support creation of Xnets and model-defined
diff-pairs through assignment of valid signal models to various devices.

You assign a signal model to components in Design Entry HDL using the Model Assignment
window. The Model Assignment window provides an easy way of assigning signal models to
multiple components and pins in Design Entry HDL.

When you launch Constraint Manager, it reads the signal models assigned to various
components including discretes. Constraint Manager interprets the net separated by the
discrete with a valid signal model as an Xnet. You can create electrical constraints on the Xnet
in Constraint Manager as well as in SigXplorer. You can also apply these constraints to other
Xnets in Constraint Manager.

We will take the example of the net NET1 divided by a discrete R6. We will assign a valid
signal model to the discrete device R6 and to an IC device U19 to create a model-defined diff-
pair. We will then view the Xnet and model-defined diff-pair in Constraint Manager. Later, we
will launch SigXplorer on the Xnet and set electrical constraints on it in SigXplorer.
Consequently, an ECSet will be formed in Constraint Manager. We will then make another
Xnet reference this ECSet.

Creating an Xnet in Design Entry HDL

Task Overview
You will create an Xnet by assigning a signal model to the discrete R6.

Steps
1. In Design Entry HDL, navigate to page 4 (PS0.SCH.1.4) by clicking the Next Page/
Symbol icon.
2. Zoom in appropriately to display the schematic drawing clearly.

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3. Choose Tools > Model Assignment.

4. On the schematic, right-click the resistor instances R6.
5. From the pop-up menu, select Highlight.
6. Restore the Model Assignment window.
The entry for R6 is selected in the second pane of the Model Assignment window.

7. Click the Auto Generate button.

8. Click the Apply button.
An appropriate signal model is assigned to R6. The net NET1 will now be interpreted as
an Xnet by Constraint Manager.

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Creating a Model-Defined Diff-Pair in Design Entry HDL

Task Overview
You will set up path to the device model library, ps0.dml and assign a model DS90C031TM to
the component U19 to create a model-defined diff-pair.

Steps
1. Zoom in appropriately to display the schematic drawing clearly.
2. On the schematic, right-click the component instances U19.
3. From the pop-up menu, select Highlight.
4. Restore the Model Assignment window.
The entry for U19 is selected in the second pane of the Model Assignment window
5. Click the Setup button.
6. Select the entry for PS0.dml file.
7. Click the Set as Working library icon.

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8. Click OK.
9. Navigate to the entry for U19 by first selecting 74ALS192 in the first pane and then
selecting U19 in the second pane.
10. Right-click and select Assign SI Model from the pop-up menu.
The SI Model Assignment window is displayed.

11. Browse to the signal model DS90C031TM in the SI Model column.

12. Click the Assign button.
13. Click the Apply button.
14. Click the Close button to close the Model Assignment window.
15. Zoom in again to display the schematic drawing clearly.
Notice that the signal models you just assigned are visible on schematic canvas. The
nets ABCNET1 and ABCNET2 will now be interpreted as a model-defined diff-pair by
Constraint Manager.

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Viewing an Xnet in Constraint Manager

Task Overview
You will view the Xnet and model-defined diff-pair you created in the previous exercise in
Constraint Manager.

Steps
1. In Design Entry HDL, choose Tools > Constraints > Edit.
2. Click Yes when prompted to expand the design.
Allegro Constraint Manager (connected to Allegro Design Entry HDL) is displayed.
3. Click the plus sign (+) next to Routing in the Net folder on the left pane.
4. Click Relative Propagation Delay under Routing.
The contents of the Relative Propagation Delay worksheet are displayed on the right
pane.
5. Move the mouse pointer over the entry for NET1 in the worksheet.
A tooltip appears indicating that the selected net is an Xnet.

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6. Similarly, move the mouse pointer over the entry for DP_ABCNET. Notice the tooltip
which indicates that the selected object is a diff-pair.
Note: Constraint Manager reads the nets ABCNET1 and ABCNET2 as a diff-pair and
adds a DP_ prefix to the diff-pair name.

Generating an Electrical Constraint on an Xnet in

SigXplorer

Task Overview
You will generate an electrical constraint on the Xnet you created in a previous exercise in
SigXplorer.

Steps
1. Right-click the entry for the Xnet, NET1 in the Relative Propagation Delay worksheet in
Constraint Manager.
2. Select SigXplorer from the pop-up menu.

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SigXplorer launches displaying the topology of the Xnet, NET1.

3. To generate constraint rules on the Xnet NET1, choose Set > Constraints from the
main menu of SigXplorer.
4. Select the Rel Prop Delay tab in the Set Topology Constraints window.
5. Click New.
Notice that when you click New, the Rule Name field populates with the base name of
the topology and a suffix M1. Here, it is named as NET1_M1 after the Xnet, NET1. If you
add a second rule, the suffix will automatically increment by 1.
6. Click the entry for U18.12 in the Pins/Tees section.
The From field is populated with the appropriate value in the Rule Editing section.
7. Click the entry for U21.5 in the Pins/Tees section.
The To field is populated with the appropriate value in the Rule Editing section.

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8. Type 6 in the Tolerance field.

9. Click the Add button.
The relative propagation delay constraint that you have created is added in the Existing
Rules section.

10. Click OK.

11. Choose File > Update Constraint Manager.
This creates a new ECSet NET1 in Constraint Manager for the electrical constraints that
you have set on the Xnet NET1 in SigXplorer. You are prompted to make the Xnet NET1
reference the newly created ECSet NET1.
12. Click Yes.

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The Electrical CSet Apply Information message box confirm that the ECSet NET1 is
attached to the Xnet NET1.

13. In the Relative Propagation Delay worksheet, notice that the ECSet has been applied to
Xnet, NET1. Notice that the pin-pair constraint you defined has been applied to NET1.

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You generated an electrical constraint on an Xnet in SigXplorer and applied it to the Xnet in
Constraint Manager.

Applying an ECSet on an Xnet to Other Xnets in

Constraint Manager

Task Overview
You will apply the ECSet NET1 to other Xnet NET 3 in Constraint Manager.

Steps
1. Right-click the entry for the Xnet, NET3 in the Relative Propagation Delay worksheet In
Constraint Manager.
2. Select Electrical CSet References from the pop-up menu.
The Electrical CSet References dialog box is displayed.
3. Select NET1 from the drop-down list.
4. Click OK.

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The ECSet Apply Information message box confirms the application of the ECSet to
NET3.

5. Click Close.

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The ECSet is applied and appears in blue color in the Referenced Electrical CSet column
indicating that the ECSet is applied correctly.

6. Now perform steps 1 through 4 above on a net, BHEL.

The ECSet Apply Information message box informs that the ECSet could not be applied
correctly. The ECSet name appears in red color in the Referenced Electrical CSet
column indicating that an error occurred while applying the ECSet to the Xnet. Also, the

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first cell in the Referenced Electrical CSet column shows a solid red-color bar indicating
the error.

You applied an ECSet generated on one Xnet to another Xnet in Constraint Manager.
Note: Now try this interactive exercise, on creating Xnets and model-defined diff-pairs,
generating ECSets on Xnets in SigXplorer, and applying the ECSets to other Xnets in
Constraint Manager.

Summary
You learned to create an Xnet in Design Entry HDL, view it in Constraint Manager, generate
electrical constraints on the Xnet in SigXplorer, and apply the constraints to other Xnets in
Constraint Manager.

What’s Next
In the next chapter, Performing ECOs in Design Entry HDL/Constraint Manager, you will
make changes to constraints existing on the schematic. You will make changes both in
Constraint Manager and Design Entry HDL. The two tools are synchronized when you save
the changes.

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Recommended Reading
For more information about Xnet creation, see the Working with Signal Integrity Analysis
Features chapter of the Allegro Design Entry HDL User Guide and the Constraint
Manager Design Guide.

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Performing ECOs in Design Entry HDL/
Constraint Manager

Objectives
To learn how to perform Engineering Change Orders (ECOs) in schematic objects and
constraints on objects while keeping the constraints and the corresponding electrical
properties synchronized.

At the end of the lesson, you will be able to

■ Capture a constraint on an unpackaged net.
■ Modify a constraint in Constraint Manager.
■ Modify a constraint in Design Entry HDL.
■ Delete a constraint in Constraint Manager.
■ Rename a net in Design Entry HDL and retain its constraints.

Nature of Chapter
Skill ( includes concepts and practice)

Estimated Completion Time

40 minutes

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Overview
You can make changes in constraints and their corresponding electrical properties after you
have added them once and have exited the corresponding tools. Design Entry HDL and
Constraint Manager are synchronized when the electrical constraints and schematic are
saved in Constraint Manager and Design Entry HDL.

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Adding a Net in the Schematic

You can capture a constraint on an unpackaged object in a schematic. At a later point in time,
when you package the design, the constraint is retained in the schematic.

Task Overview
You will add a net MY_NET between pin Q0 of BINARY CTR F393 and pin I11 of 20R8. Then
you will add the impedance constraint on it. Lastly, you will package your design and view the
constraint in Constraint Manager.

Steps
1. Click the Design Entry HDL window.
2. If you are in occurrence edit mode, choose Tools > Occurrence Edit to switch to
expanded mode.
3. Choose Tools > Unexpand Design to switch to the hierarchy mode.
The Constraint Manager window closes.

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4. Zoom into the portion of the schematic where BINARY CTR F393 and 20R8 lie. These
components are present on page 1 of the ps0 design.

Connect pin Q0 of
BINARY CTR F393
and pin I11 of 20RB.

5. Choose Wire > Route and click once on pin Q0 of BINARY CTR F393 and again on pin
I11 of 20R8.

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6. Choose Wire > Signal Name.

The Signal Name dialog box appears.
7. Enter the name MY_NET in the Signal Names field and click the net that you have just
added.
8. Close the Signal Name dialog box.
9. Choose File > Save to save the newly added net in the schematic database.
10. Choose Tools > Expand Design to switch to the expanded mode.
11. Choose Tools > Constraints > Edit.
12. Open the Impedance worksheet.
You can see the net MY_NET in the canonical format and all the other nets in physical
format. This is because the design has not been packaged after the addition of the net
MY_NET.

13. Set the Target value as 55 Ohm and Tolerance value as 3%.
14. Choose File > Save.
15. Switch to the Design Entry HDL window and make the IMPEDANCE_RULE property
visible.

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16. Choose File > Save to save the newly added constraints.
17. Choose File > Export Physical.
The Export Physical dialog box appears.
18. Click OK.
The Progress window appears.
19. Once the packaging is done, switch to the Constraint Manager window.
You can now see the net MY_NET in the physical format along with the impedance
constraint on it shown below:

Modifying a Constraint in Design Entry HDL

You can modify the value of an electrical constraint by editing the value of the corresponding
property in the Attributes dialog box in Design Entry HDL.

Important
You have to exit from Constraint Manager to edit properties in the schematic. If
Constraint Manager is running simultaneously with Design Entry HDL, the Values
column appears greyed in the Attributes dialog box in Design Entry HDL.

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Task Overview
You will modify the value of the MAX_FINAL_SETTLE property for net RESETL in Design
Entry HDL and view it in Constraint Manager.

Steps
1. Click the Design Entry HDL window.
2. Choose Text > Attributes and click net RESETL.
The Attributes dialog box appears as follows with the Schematic Value column greyed
for all properties.

3. Click Cancel.
The Attributes dialog box closes.
4. Click the Constraint Manager window.
5. Choose File > Exit.
The Constraint Manager window closes.
6. Click the Design Entry HDL window.
7. Choose Text > Attributes and click net RESETL.

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The Attributes dialog box appears with the Schematic Value column editable for
properties.

8. For the MAX_FINAL_SETTLE property, change the existing schematic value to

AD:AR:3.210 ns:3.280 ns.
9. Click OK.
10. Choose File > Save to save the modified value of the property.
11. Choose Tools > Constraints > Edit.
The Constraint Manager window appears.
12. Open the Switch/Settle Delays worksheet.

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You can see the updated value of the Max Final Settle constraint in the worksheet as
follows:

Modifying a Constraint in Constraint Manager

You can modify the value of an electrical constraint in Constraint Manager and view the
corresponding property on the schematic in Design Entry HDL.

Task Overview
You will modify the value of the Min First Switch constraint for net RESETL in Constraint
Manager and view it in Design Entry HDL.

Steps
1. Open the Switch/Settle Delays worksheet in Constraint Manager.
2. Scroll down to the constraints for net RESETL.
3. In the Min First Switch column, change the existing value of Min to 0.2500:0.2800.
4. Choose File > Save to save the new value of the constraint.

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5. Click the Design Entry HDL window.

6. Choose Text > Attributes and click net RESETL.
The Attributes dialog box appears with the updated value for MIN_FIRST_SWITCH
property in the Net Value column as follows:

7. Click Cancel.
The Attributes dialog box closes.
8. Choose Tools > Constraints > Update Schematic.
The changes in constraints are propagated to the hierarchy mode.

Tip
You can switch to the hierarchy mode and view the changed MIN_FIRST_SWITCH
property in the Attributes dialog box. However, if you switch to hierarchy mode while
Constraint Manager is running, Constraint Manager exits.

Deleting a Constraint in Constraint Manager

You can delete an electrical constraint in Constraint Manager; the corresponding electrical
property gets deleted from the schematic.

Task Overview
You will delete the Electrical Properties constraint for net CLK in Constraint Manager and view
the change on the schematic.

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Steps
1. Open the Electrical Properties worksheet in Constraint Manager.
2. Scroll down to the constraints for net CLK.
3. Delete the existing value for Frequency.
The values for constraints Period, Duty Cycle and Jitter get deleted automatically.
4. Choose File > Save.
5. Click the Design Entry HDL window and ensure that you are not in occurrence edit mode.
6. Open page 1 of the 4_BIT_COUNTER design.
7. Choose Text > Attributes and click net CLK.
The Attributes dialog box appears as follows:

Note: See that the PULSE_PARAM property has not been deleted from the design yet.
8. Click Cancel.
9. Choose Tools > Constraints > Update Schematic.
Constraint Manager updates the design and the property gets deleted from the
schematic as well.
10. Open the Attributes dialog box again.

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It appears as follows:

Note: You can see that the value of PULSE_PARAM has got deleted but the property
name still exists in the Attributes dialog box. You can use this to add the PULSE_PARAM
property in Design Entry HDL if required at a later point in time.
11. Click Cancel.

Renaming a Net in Design Entry HDL

You can rename a net that has constraints on it in Design Entry HDL; the constraints are
retained.

Task Overview
You will assign a new name to net ROMOEL in Design Entry HDL and view the net with the
changed name in Constraint Manager. The net ROMOEL has the Max Overshoot constraint on
it.

Steps
1. Open page 1 of the ps0 design.
2. Locate net ROMOEL in the design.

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The net ROMOEL appears at the following two places in the design:

Two instances
of net
ROMOEL.

3. Choose Tools > Unexpand Design to switch to the hierarchy mode in Design Entry
HDL.
Constraint Manager window gets closed automatically as the connectivity information is
no longer available.
4. Choose Text > Attributes and click one instance of net ROMOEL.
The Attributes dialog box appears.

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5. Change the value of property SIG_NAME from ROMOEL to ROMOEL_NEW as follows:

6. Click OK.
The Attributes dialog box closes.
7. Repeat steps 4 to 6 for the second instance of net ROMOEL.
8. Choose File > Save.
9. Choose Tools > Expand Design to expand the design.
10. Choose Tools > Constraints > Edit.
The Constraint Manager window opens.
11. Open the Reflection worksheet in the Constraint Manager window.

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You can see the newly added net @project_lib.ps0(sch_1):romoel_new as well as

net ROMOEL as follows:

Nets ROMOEL_NEW
and ROMOEL

12. Choose Audit > Obsolete Objects from the Constraint Manager menu.

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The Audit Obsolete Objects dialog box appears as follows:

Net ROMOEL is obsolete now ROMOEL_NEW is the new net name

13. Select ROMOEL in the Obsolete Objects column.

14. Click Delete.
The Constraint Manager message box appears and prompts you to confirm deletion of
the obsolete net ROMOEL.

15. Click Yes.

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The Constraint Manager message box appears indicating that obsolete objects do not
exist in the design any more.

16. Click OK.

The obsolete entry for the net ROMOEL is removed from the Constraint Manager
worksheet.
17. Choose File > Save.
18. Choose File > Exit.

Summary
You have now seen the tight integration between Design Entry HDL and Constraint Manager.
You learned to make changes to constraints in Constraint Manager and Design Entry HDL
separately and saw that the two tools get synchronized when you save the changes.

What’s Next
In the next chapter, Synchronizing Constraints Between Schematic and Board, you will learn
to propagate constraints on the schematic to the board. You will also learn to propagate the
constraints on the board back to the schematic so that the board and the schematic are
synchronized.

Recommended Reading
For more information about the integration between Design Entry HDL and Constraint
Manager, see the Allegro Design Entry HDL User Guide.

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Synchronizing Constraints Between
Schematic and Board

Objectives
To learn how to synchronize electrical constraints captured on the schematic with those
captured on the board and conversely.

At the end of the lesson, you will be able to

■ Propagate electrical constraints on schematic to the corresponding board.
■ Propagate electrical constraints on a board to the corresponding schematic.
■ Overwrite electrical constraints in the schematic onto those on the board and conversely.
■ Propagate only changed electrical constraints from the schematic to the board and
conversely.

Nature of Chapter
Skill ( includes concepts and practice)

Estimated Completion Time

1 hour 10 minutes

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Exporting Constraints from Design Entry HDL

Once you have created your schematic and have added all the constraints relevant during
logic implementation, you can transfer the logic to an PCB Editor board. When you create the
board, the electrical constraints are also transferred to objects on the board.

Task Overview
You will package your design and create a board file for your design. The board file will contain
all the constraints that you have added in the schematic.

Steps
1. Click the Design Entry HDL window.
2. Choose File > Export Physical.
The Export Physical dialog box appears.
3. Make sure that the Package Design option is selected.

Important
You must package the design when you add new constraints in your design so that
they are propagated to the corresponding board.
4. Select the Update PCB Editor Board (Netrev) option.
The Input Board File option contains start.brd. This is the input template file for the
board that will be created for your design.
5. Enter my_board.brd as the Output Board File.

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The Export Physical dialog box appears as follows:

Selected to propagate constraints to PCB Editor.

Selected to create new board.

Template board file

New board file

6. Click OK.
The Export Physical dialog box closes and the Progress window appears. Once the
packaging is done and the board is created, the Design Sync message box appears.
7. Click No.
The Design Sync message box closes.

Starting PCB Editor

Steps
1. Click the Project Manager window.
2. Click the Layout icon.

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The PCB Editor window opens with the myboard.brd board file.

Viewing and Adding Constraints in PCB Editor

The Constraint Manager tool is integrated with Design Entry HDL as well as with PCB Editor.
The layout engineer can view the constraints captured on the schematic in PCB Editor by
invoking Constraint Manager from it. In addition to viewing the constraints captured on
schematic, the layout engineer can also
■ capture constraints relevant to placement and routing of objects on the board
■ update the constraints that you captured in the schematic in case you find that the
constraints are not very well in line with the way nets are routed on the board
■ analyze the values of various constraints
■ export the results of the analysis, which can then be viewed by the schematic engineer
in Constraint Manager connected to Design Entry HDL to see if there are any violations
in the constraints set by him.

Task Overview
You will invoke Constraint Manager from PCB Editor and then view the constraints on net
RESETL, edit the Min First Switch constraint on net RESETL, and add the Max Xtalk
constraint on it. You will also analyze the constraints and export the results.

Steps
1. Click the PCB Editor window.
2. Choose Setup > Electrical Constraint Spreadsheet from the PCB Editor menu.
The Constraint Manager window is displayed in front of the PCB Editor window.
Note: The title bar of the Constraint Manager window shows that Constraint Manager is
connected to PCB Editor and all the constraints captured in it would be reflected in PCB
Editor.
3. In the Net workbook, double-click Timing and then Switch/Settle Delays.
The constraints that you had captured on nets in Constraint Manager connected to
Design Entry HDL were propagated to the PCB Editor database when you packaged the
design and created the board using Export Physical.

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4. Scroll down to view the Min First Switch and Max Final Settle constraints on net RESETL.
The constraints appear in the Constraint Manager window as follows:

Constraint Min First Switch Constraint Max Final Settle

for net RESETL. for net RESETL.

5. Similarly, view the other constraints on net RESETL.

6. Switch to the Switch/Settle Delays worksheet again and scroll down to net RESETL.
7. Change the value of Min in the Min First Switch column to 0.2500:0.2900.

Important
You may want to change the values of constraints captured in Design Entry HDL in
PCB Editor after doing an analysis on the nets on the board. For detailed information
on how to perform analysis in Constraint Manager connected to PCB Editor, refer
the Constraint Manager Tutorial.
8. Double-click Signal Integrity in the left window pane and click Estimated Xtalk.
9. Scroll down to net RESETL.
10. Enter the value for Max in the XTalk column as 30:30.

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The Signal Integrity worksheet appears as shown below:

Constraint Max XTalk for net RESETL.

11. Click the PCB Editor window.

12. Choose File > Save.
PCB Editor prompts you to overwrite the my_board.brd file.
13. Click Yes.
PCB Editor saves the changes in its database.
14. Choose Analyze > Analyze.
Constraint Manager checks if there are any violations to the constraints and sets colors
to reflect the same. For further details on how to analyze the constraints, refer
Constraint Manager Tutorial ( back-end).
15. Choose File > Export > Analysis results.
The Export Actuals dialog box appears with file name as my_board.acf.
16. Click Save.

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Importing Constraints in Design Entry HDL

The constraints that you have added on the board need to be propagated to the schematic.
This is required to keep the logic in the schematic and the physical design synchronized with
each other. The propagation of physical design information to the schematic can be done
through the import process in Design Entry HDL.

Task Overview
You will invoke the Import Physical dialog box from Design Entry HDL and import the physical
design information from the my_board.brd file to your schematic design.

Steps
1. Click the Design Entry HDL window.
2. Choose File > Import Physical.
The Import Physical dialog box appears.
3. Select the Generate Feedback Files option.
Note: The PCB Editor Board File field contains the board file name my_board.brd.
This is the file from which the electrical constraints will be read.
4. Make sure that the Backannotate Schematic option is selected.
5. Click OK.
The Import Physical dialog box closes and the Progress window appears. Once the
import process is complete, the Design Sync message box appears.
6. Click No.
The Design Sync message box closes.

Viewing Constraints in Design Entry HDL

Since Constraint Manager is integrated with Design Entry HDL and PCB Editor both, the
constraints that you add/modify in PCB Editor can be made visible in Design Entry HDL also.

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Task Overview
You will view the following constraints on net RESETL in Design Entry HDL:
■ Max XTalk that you had added in PCB Editor
■ Min First Switch whose value you had changed in PCB Editor

Steps
1. Choose Tools > Expand Design.
The design takes some time to expand.
2. Go to page 1 of ps0 design and locate net RESETL.
3. Choose Text > Attributes and click net RESETL.
The Attributes dialog box appears.

Select Both to make

Constraints on net RESETL. MAX_XTALK visible.

4. Make the MAX_XTALK property visible on the schematic.

5. Choose Tools > Constraints > Update Schematic.
Design Entry HDL prompts you to save the schematic before updating it with the new
constraints.
6. Click Yes.

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Note: It takes some time for Design Entry HDL to save the design and update it.
7. Zoom into the portion of the design where net RESETL is and view the constraints on it.
They appear as follows:

Two Modes of Synchronizing Constraints between the

Board and the Schematic
It is quite possible that after you have created the board corresponding to your schematic
along with all the constraints, you change certain constraints either on the schematic or on
the board. The schematic and the board then do not remain synchronized.

You can propagate the changes in the following two modes:

■ Overwrite current constraints
When you are propagating changes from the schematic to the board, Design Sync
overwrites all existing electrical constraint information in the board file with the electrical
constraint information currently present in the schematic.
Similarly, when you are propagating changes from the board to the schematic, Design
Sync overwrites all existing electrical constraint information in the schematic with the
electrical constraint information currently present in the board file.
■ Propagate changed constraints only
When you are propagating changes from the schematic to the board, Design Sync will
overwrite only those electrical constraints in the board file that have changed in the
schematic since the last time the constraints were propagated.
Similarly, when you are propagating changes from the board to the schematic, Design
Sync will overwrite only those electrical constraints in the schematic that have changed
in the board file since the last time the constraints were propagated.

We will be learning the two modes in the following 2 sections.

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Overwriting Constraints on the Board with Constraints on the Schematic

Task Overview

You will add the Min First Switch constraint on net CLK from Constraint Manager connected
to PCB Editor. Then, you will change the following constraints on net CLK from Constraint
Manager connected to Design Entry HDL:
❑ Delete Min Noise Margin
❑ Change the value of Max Overshoot
❑ Add Max XTalk

Finally, you will overwrite the changes made in constraints in the schematic onto the
constraints on the board.

Steps
1. Click the Constraint Manager connected to PCB Editor window.
2. Open the Switch/Settle Delays worksheet and for net CLK, enter Min as 0.24:0.24
in the Min First Switch column.
3. Click the PCB Editor window.
4. Choose File > Save.
PCB Editor prompts you to overwrite the my_board.brd file.
5. Click Yes.
PCB Editor saves the changes in its database.
6. Choose File > Exit and close the PCB Editor window.
The Constraint Manager connected to PCB Editor window also closes.
7. Click the Constraint Manager connected to Design Entry HDL window.
8. Choose File > Import > Analysis results.
The Import Actuals dialog box appears.
9. Click file name my_board.
10. Click Open.

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The results of the analysis done in Constraint Manager connected to PCB Editor are
loaded.
11. Open the Reflection constraint worksheet and for net CLK, do the following:

a. Change the value of Max Overshoot to 5200:-600.

b. Delete the value of Min Noise Margin.

12. Open the Estimated XTalk worksheet and for net CLK, set Max as 26:25 in the XTalk
column.
13. Choose File > Save.
14. Click the Design Entry HDL window.
15. Choose File > Save.
16. Choose File > Export Physical.
The Export Physical dialog box appears.

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17. In the Electrical constraints section, select the Overwrite current constraints option
as follows:

Select to overwrite the

constraints on the board
with those on the
schematic.

With this option selected, Design Sync overwrites all existing electrical constraint
information in the Output Board File with the electrical constraint information available
in the schematic.
18. Click OK.
19. After the export process is complete, invoke PCB Editor from Project Manager.
20. Choose Setup > Electrical Constraint Spreadsheet.
The Constraint Manager window appears.
21. Open the Reflection worksheet.

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It appears as follows:

Updated value of constraint

Max Overshoot for net CLK.

Note: You can see that the value of Max Overshoot has been overwritten (previously
5100:-610 on the board) and the Min Noise Margin constraint has been deleted.
22. Open the Estimated XTalk worksheet.

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For net CLK, the value of Max XTalk appears as follows:

23. Open the Switch/Settle Delays worksheet.

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For net CLK, the constraint Min First Switch (that you had previously added on the
board) has been deleted from the board since it did not exist on the schematic.

Importing Constraints Changed on the Board in the Schematic

Task Overview

You will change the following constraints on net RESETL from Constraint Manager connected
to PCB Editor:
❑ Change the value of Min First Switch
❑ Delete Max Final Settle
❑ Add Max Overshoot

Finally, you will import these changes made in constraints in the board onto the constraints
on the schematic.

Steps
1. Click the Constraint Manager connected to PCB Editor window.

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2. Open the Switch/Settle Delays worksheet.

3. For net RESETL, in the Min First Switch column, change the value of Min to
0.2500:0.2600.
4. For net RESETL, in the Max Final Settle column, delete the value of Max.
5. Open the Reflection worksheet.
6. For net RESETL, in the Overshoot column, enter the value of Max as 5200:-600.
7. Click the PCB Editor window.
8. Choose File > Save.
PCB Editor prompts you to overwrite the my_board.brd file.
9. Click Yes.
PCB Editor saves the changes in its database.
10. Click the Design Entry HDL window.
11. Choose File > Import Physical.
The Import Physical dialog box appears.
12. In the Electrical constraints section, select the Import Changes only option as
follows:

Overwrite only those

constraints on the schematic
that have changed.

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With this option selected, Design Sync imports only those electrical constraints that have
changed in the PCB Editor Board File since the last import and overwrites these
constraints on the schematic.
13. Click OK.
The Import Physical dialog box closes and the Progress window appears. Once the
import process is complete, the Design Sync message box appears.
14. Click No.
The Design Sync message box closes.
15. Choose Tools > Constraints > Update Schematic.
16. Choose Text > Attributes and click net RESETL.
The Attributes dialog box appears as follows:

Note: You can see the updated value of MIN_FIRST_SWITCH property, the new
constraint MAX_OVERSHOOT and only the placeholder for MAX_FINAL_SETTLE property.
17. Click Cancel.
Note: Now try this interactive exercise, Synchronizing the Design and the Board.

Summary
You looked at two modes of propagating electrical constraints from the schematic to the board
and conversely — propagating all the constraints or propagating only changed constraints.
This ensures that constraints in Design Entry HDL and PCB Editor are synchronized.

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What’s Next
This is the last chapter in the Design Entry HDL and Constraint Manager Tutorial. In the
Glossary, you will find the definitions of various terms used in this tutorial.

Recommended Reading
For more information about the two modes of synchronizing electrical constraints between a
schematic and a board, see chapter “Working with Electrical Constraints” of the Allegro
Design Entry HDL User Guide.

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A
Glossary

Overshoot

Overshoot is the maximum voltage swing above the input voltage. It specifies the acceptable
voltage limits of logic families.

Noise Margin

Noise margin is the voltage difference between the maximum voltage dip and the active high
threshold or between the maximum voltage dip and the active low threshold.

Jitter

Jitter is the deviation in pulse width of a clock cycle, keeping the clock cycle same.

Sensitive Edge

Sensitive edge signals are those that drive receivers by their edge thresholds. A typical
example of a sensitive edge signal is a clock signal.

First Incident Switch

First incident switching is the switching voltage of sufficient amplitude at the initial rise of a
signal which is sufficient to drive receivers.

Propagation Delay

Propagation delay is the summation of all calculated transmission line delays along the
shortest path between two points. The default unit for propagation delay is ns.

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Glossary

Settle Time

Settle time is the time required for a ringing signal to stabilize to within a specified range of
the final value.

Minimum First Switch Time

Specifies the maximum transmission line wire delay plus distortions differing from the nominal
driver rise-or-fall time seen in the receiver rise-or-fall.

Duty Cycle

The portion of the time the pulse stimuli is held in the high state as a fraction of the entire
pulse period. A value of 0.5 represents equal high and low portions of the cycle period.

Simultaneous Switching Noise

When a number of drivers switch simultaneously in a digital system, a sudden change in

current occurs through the power and ground connections to the die. Because of the parasitic
inductance that exists in this path, any current change produces a temporary fluctuation in
the power and ground voltages as seen by the die. This is typically referred to as
Simultaneous Switching Noise (SSN), or Ground Bounce. Simultaneous switching noise can
cause noise at the output of non-switching drivers. This noise will then propagate to loads on
the net and potentially cause false switching.

Impedance

Impedance is the ratio of input voltage to input current for a transmission line (Z0 = V/I). When
a source sends a signal down a line, this is the impedance it must drive. The Source will not
see a change in its loading Impedance until 2*TD, where TD is the delay of the line.

Reflection

A reflection on a transmission line is an echo. A portion of the signal power (voltage and
current) transmitted down the line goes into the load, and a portion is reflected. Reflections
are prevented if the load and the line have the same impedance.

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Glossary

Setup Time

The time for which a digital signal A must be stable and unchanging prior to another digital
signal of interest B.

Setup time is most often associated with activity of digital signals immediately before a clock
event when these signals must be stable and ready as necessary inputs to clocked circuits,
especially latches.

Hold Time

The time for which a digital signal A must be stable and unchanging following the change of
another digital signal of interest B.

This parameter is very important with synchronous state machines employing feedback logic
that can change as a result of the clock.

Clock Skew

Clock skew is the difference in arrival time between clock and data at a logic gate.

Differential Pair

A differential pair represents a pair of nets or Xnets that will be routed in a way that the signals
passing through them are opposite in sign with respect to the same reference. This ensures
that any electromagnetic noise in the circuit is cancelled out.

Pin-Pair

A pin-pair represents a pair of logically connected pins, often a driver-receiver connection.

Pin-pairs may not be directly connected but they must be on the same net or Xnet. A pin-pair
for a net connecting component 1 and component 2 is represented as follows:
reference designator of component 1.pin number : reference designator of component
2.pin number

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Glossary

For example in the following figure, a pin-pair for net CLK2 is:

Pin 2 of crystal and pin 4 of F109

form a pin-pair for net CLK2.

You can specify a pin-pair explicitly, or it can be derived based on the length of the physical
net between the pins forming the pin-pair. The length of the net is determined when the board
for the schematic is placed and routed in PCB Editor. Accordingly, the pin-pairs are
categorized as follows:
■ longest/shortest pin-pair
Out of all the possible pairs of pins that a net connects, the longest pin-pair is the one
between whose pins the length of the connecting net is maximum. Similarly, the shortest
pin-pair is the one between whose pins the length of the connecting net is minimum.
■ longest/shortest driver-receiver
Out of all the pairs of pins for a net where one pin outputs the signal (driver) on the net
and the other takes input (receiver), the longest driver-receiver is the one between whose
pins the length of the connecting net is maximum. Similarly, the shortest driver-receiver
is the one between whose pins the length of the connecting net is minimum.

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Glossary

■ all driver-receiver pin-pairs

This refers to all possible pairs of pins for a net such that one pin outputs the signal
(driver) on the net and the other takes input (receiver).

Electrical Constraint Set

An electrical constraint set (ECSet) is a collection of constraints and their default values. An
ECSet reflects a particular design requirement. You can capture any or all electrical
constraints in an ECSet.

ECSets reside in the Electrical Constraint Set object folder. You can create ECSets for signal
integrity, timing, and routing constraints.

Primary Gap

Indicates the ideal edge-to-edge spacing between the pair of nets in the differential pair that
should be maintained for the entire length of the pair.

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Glossary

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Index
A constraints 38
creation 36
adding a net in the schematic 89 definition 125
adding constraints in PCB Editor 108 duty cycle 52, 124
adding nets to a matched group 32
Allegro PCB Design HDL 610 suite 11
analysis 109 E
ECOs(Engineering Change Orders) 88
C ECSet
creation in Signal Explorer 58
canonical format 21, 40 using 58
clock skew 125 ECSet (electrical constraint set) 58
constraint electrical constraint property
delete 96 modify 92
duty cycle 52, 124 visibility 27
frequency 52 electrical constraint set (ECSet) 58, 127
impedance 124 Engineering Change Orders(ECOs) 88
jitter 52, 123 exporting constraints from Design Entry
modify HDL 106
Constraint Manager 95
Design Entry HDL 92
settle time 124 F
setup time 125
synchronize 113 first incident switch 123
visibility 27 frequency 52
constraint on renamed net 98
constraint on unpackaged schematic 89
constraints on board 108 G
creating a differential pair 36
creating a matched group 30 global find 22
creating ECSet in Signal Explorer 58
critical net 24
H
D hierarchy mode 96
hold time 125
database
install 11
NT 12 I
UNIX 12
deleting a constraint in Constraint impedance 20, 62, 124
Manager 96 importing constraints in PCB Editor 111
Design Expert 11 install the database 11
Design Studio 11
differential pair

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J procedures
adding a net in the schematic 89
jitter 52, 123 adding constraints in PCB Editor 108
adding nets to a matched group 32
creating a differential pair 36
L creating a matched group 30
deleting a constraint in Constraint
locate a net 22 Manager 96
exporting constraints from Design Entry
HDL 106
M importing constraints in PCB Editor 111
modifying a constraint in Constraint
matched group 29 Manager 95
minimum first switch time 49, 124 modifying a constraint in Design Entry
modes of constraints synchronization 113 HDL 92
modify constraint 92 renaming a net in Design Entry HDL 98
modifying a constraint in Constraint setting constraints on a differential
Manager 95 pair 38
modifying a constraint in Design Entry setting electrical properties 51
HDL 92 setting propagation delay relative to a
net 29
setting the propagation delay 20
N starting Constraint Manager 17
viewing a constraint on the
navigate 22 schematic 27
net product suite 11
canonical format 21, 40 propagate changed constraints 113
physical format 21, 40 propagation delay 20
noise margin 123 definition 123
pin pair 24
relative to a net 29
O
obsolete object 101 R
overshoot 55, 60, 123
overwrite constraints 113 reflection 54, 124
renaming a net in Design Entry HDL 98

P S
packaged design 21, 40
PCB Editor sensitive edge 123
add constraints 108 setting constraints on a differential pair 38
synchronize constraints 114 setting electrical properties 51
physical format 21, 40 setting frequency 52
pin pair setting propagation delay relative to a
creation 25 net 29
definition 125 setting the propagation delay 20
propagation delay 24 settle time 46, 124
primary gap 39, 127 setup time 125
Signal Explorer

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add constraints 58
synchronize constraints with Constraint
Manager 63
simultaneous switching noise (SSN) 124
starting Constraint Manager 17
synchronize constraints
modes 113
PCB Editor 114
Signal Explorer 63
synchronizing board and schematic 111

V
viewing a constraint on the schematic 27

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