AT91SAM9G45-EKES

....................................................................................................................

User Guide

6481B–ATARM–27-Nov-09
Section 1
Introduction .................................................................................................................1-1
1.1 Scope ................................................................................................................................. 1-1
1.2 Applicable Documents ....................................................................................................... 1-2

Section 2
Kit Contents ................................................................................................................2-1
2.1 Deliverables ....................................................................................................................... 2-1
2.2 Evaluation Board Specifications......................................................................................... 2-2
2.3 Electrostatic Warning ......................................................................................................... 2-2

Section 3
Power Up ....................................................................................................................3-1
3.1 Power Up the Board........................................................................................................... 3-1
3.2 Battery................................................................................................................................ 3-1
3.3 DevStart ............................................................................................................................. 3-1
3.4 Recovery Procedure .......................................................................................................... 3-1
3.5 Sample Code and Technical Support ................................................................................ 3-2

Section 4
Board Description .......................................................................................................4-1
4.1 Equipment on the Board .................................................................................................... 4-1
4.1.1 Interfaces ............................................................................................................. 4-1
4.1.2 Board Interface Connection ................................................................................. 4-2
4.1.3 Push Button Switches .......................................................................................... 4-2
4.1.4 Display LCD and LEDs ........................................................................................ 4-3
4.2 Hardware Layout and Configuration .................................................................................. 4-3
4.2.1 Processor............................................................................................................. 4-3
4.2.2 Clock Circuitry...................................................................................................... 4-3
4.2.3 Reset Circuitry ..................................................................................................... 4-4
4.2.4 Memory ................................................................................................................ 4-4
4.2.5 Power Supplies .................................................................................................... 4-7
4.2.6 Debug Interface ................................................................................................... 4-9
4.2.7 Audio Stereo Interface ....................................................................................... 4-14
4.2.8 TV-Out Extension .............................................................................................. 4-16
4.2.9 Software Controlled LEDs ................................................................................. 4-16
4.2.10 Serial Peripheral Interface Controller (SPI) ....................................................... 4-17
4.2.11 Two Wire Interface (TWI)................................................................................... 4-18
4.2.12 SD/MMC Interface ............................................................................................. 4-18
4.2.13 TFT LCD with Touch Panel ............................................................................... 4-20
4.2.14 Push Buttons ..................................................................................................... 4-22

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 4.2.15 Expansion Slot ................................................................................................... 4-22

Section 5
Configuration ..............................................................................................................5-1
5.1 JTAG/ICE Configuration..................................................................................................... 5-1
5.2 ETHERNET Configuration ................................................................................................. 5-1
5.3 Jumpers Configuration ....................................................................................................... 5-2
5.4 Miscellaneous Configuration Items .................................................................................... 5-3
5.5 PIO Configuration............................................................................................................... 5-3
5.5.1 Peripheral Signals Multiplexing on I/O Lines ....................................................... 5-3
5.5.2 Multiplexing on PIO Controller A (PIOA).............................................................. 5-4
5.5.3 Multiplexing on PIO Controller B (PIOB).............................................................. 5-5
5.5.4 Multiplexing on PIO Controller C (PIOC) ............................................................. 5-6
5.5.5 Multiplexing on PIO Controller D (PIOD) ............................................................. 5-7
5.5.6 Multiplexing on PIO Controller E (PIOE).............................................................. 5-8

Section 6
Connectors .................................................................................................................6-1
6.1 Power Supply ..................................................................................................................... 6-1
6.2 RS232 Connector with RTS/CTS Handshake Support ...................................................... 6-1
6.3 DBGU................................................................................................................................. 6-2
6.4 Ethernet.............................................................................................................................. 6-3
6.5 USB Host ........................................................................................................................... 6-3
6.6 USB Host/Device ............................................................................................................... 6-4
6.7 JTAG Debugging Connector .............................................................................................. 6-4
6.8 SD/MMC- MCI0.................................................................................................................. 6-6
6.9 SD/MMC- MCI1.................................................................................................................. 6-7
6.10 AC97 .................................................................................................................................. 6-7
6.11 Image Sensor - ISI ............................................................................................................. 6-8
6.12 Video .................................................................................................................................. 6-9
6.13 Display Devices.................................................................................................................. 6-9
6.13.1 LG TFT LCD LG/PHILIPS.................................................................................... 6-9
6.14 Large LCD Extension ....................................................................................................... 6-10

Section 7
Schematics .................................................................................................................7-1
7.1 Schematics......................................................................................................................... 7-1

Section 8
Revision History..........................................................................................................8-1
8.1 Revision History ................................................................................................................. 8-1

1-ii AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Section 1
Introduction

1.1 Scope
This User Guide introduces the SAM9G45 Evaluation Kit (SAM9G45-EKES) and describes its develop-
ment and debugging capabilities.

Figure 1-1. Board Photo

The Atmel® SAM9G45-EKES is a fully-featured evaluation platform for the Atmel SAM9G45-based
microcontroller. The evaluation kit allows users to extensively evaluate, prototype and create application-
specific designs.
The SAM9G45-EKES includes many hardware peripherals such as:
„ Two high speed USB hosts and one high speed device port
„ An Ethernet 10/100 interface
„ Two high speed multimedia card interfaces
„ An LCD TFT display (480*RGB*272)
„ A composite video output

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Introduction

„ A camera interface
„ Several communication peripherals such as:
– Universal Synchronous/Asynchronous Receiver Transmitter (USART)
– Serial Synchronous Controller (SSC)
– Two-Wire Interface (TWI)
The external memory block is made of 3 memory types:
„ DDR2-SDRAM
„ NAND Flash
„ NOR Flash

1.2 Applicable Documents

Table 1-1. Applicable Documents

Reference Title Comments
This document describes the SAM9G45, which is
part of the Atmel's Smart ARM® Microcontrollers.
6438A SAM9G45 Preliminary Datasheet It is available from
http://www.atmel.com/dyn/products/product_card.
asp?part_id=4596
It is available from
Errata on AT91SAM9G45
6485A http://www.atmel.com/dyn/products/product_card.
Engineering Sample Devices
asp?part_id=4596

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 Section 2
Kit Contents

2.1 Deliverables
The Atmel SAM9G45-EKES toolkit includes:
„ Board
– The SAM9G45-EKES board
„ Power supply
– Universal input AC/DC power supply with US, Europe and UK plug adapters
– One 3V Lithium Battery type CR1225
„ Cables
– One micro A/B-type USB cable
– One serial RS232 cable
„ A Welcome Letter

Figure 2-1. Unpacked SAM9G45-EKES

Unpack and inspect this kit carefully. Contact your local Atmel distributor, should you have issues con-
cerning the contents of the kit.

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Kit Contents

2.2 Evaluation Board Specifications

Table 2-1. SAM9G45-EKES Specifications

Characteristics Specifications
Clock speed 400 MHz PCK, 133 MHz MCK
Ports Ethernet, USB, RS232, DBGU
Board supply voltage 5 VDC from connector

Temperature
- operating -10° to +50° C
- storage -40° to +85° C
Relative humidity 0 to 90% (non condensing)
Dimensions 180 mm x 160 mm
RoHS status Compliant

2.3 Electrostatic Warning

The SAM9G45-EKES evaluation board is shipped in a protective anti-static package. The board must
not be subjected to high electrostatic potentials. We strongly recommend using a grounding strap or sim-
ilar ESD protective device when handling the board in hostile ESD environments (offices with synthetic
carpet, for example...). Avoid touching the component pins or any other metallic element on the board.

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 Section 3
Power up

3.1 Power Up the Board

Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right
power plug adapter corresponding to that of your country, and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the
screen and enjoy the demo.

3.2 Battery
The SAM9G45-EKES ships with a 3V coin battery.
This battery is not required for the board to start up.
The coin battery is provided for user convenience in case the user would like to exercise the date and
time backup function of the SAM9G45 series devices when the board is switched off.

3.3 DevStart
The on-board NAND Flash contains a “SAM9G45-EKES DevStart”.
It is stored in the “SAM9G45-EKES DevStart” folder on the USB Flash disk available when the
SAM9G45-EKES is connected to a host computer.
Click the file “welcome.html” in this folder to launch SAM9G45-EKES DevStart.
SAM9G45-EKES DevStart guides you through installation processes of IAR™ EWARM, Keil MDK and
GNU toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and
how to program it into the SAM9G45-EKES. Optionally, if you have a SAM-ICE™, instructions are also
given about how to debug the code.
We recommend that you backup the “SAM9G45-EKES DevStart” folder on your computer before
launching it.

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Power up

3.4 Recovery Procedure

The DevStart ends by giving step-by-step instructions on how to recover the SAM9G45-EKES to the
state as it was when shipped by Atmel.
Follow the instructions if you deleted the contents of the embedded Flash or the NAND Flash and want
to recover from this situation.

3.5 Sample Code and Technical Support

After boot up, you can run some sample code or your own application on the development kit. You can
download sample code and get technical support from Atmel website
http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4597

Figure 3-1. Atmel Website for SAM9G45 Series

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 Section 4
Board Description

4.1 Equipment on the Board

Figure 4-1. Board Architecture

Main Memory Multimedia cards LCD TFT Vidéo Audio User I/O

PARALLEL Data
FLASH Flash
LCD TFT Micro
DDR2 LCD TFT Joystick
480*272
DDR2 SDRAM 480*272 & P.B
SDRAM Line In
NAND 8 bits 4 bits
NPCS0

FLASH interface interface Touch

Touch Line Out
SD/MMC SD/MMC Screen
Screen
NCS0
NCS1

NCS3

Composite Led
CD

video Codec

MCI1 SPI0 MCI0

EBI0 EBI1 / 1.8v MCI1 SPI0 MCI0
EBI0 EBI1 / 1.8v
AC97
Multimedia Cards Interface LCD Interface AC97 PWM
External Memory Multimédia Cards Interface LCD Interface PWM
External Memory

System Controller
AT91SAM9G45
AT91SAM9M10 PIO
System Controller
PIO

Image Sensor ETHERNET USB DEBUG

Image Sensor ETHERNET
10/100 MAC USART USB DEBUG
Interface TWI USART
Interface TWI 10/100 MAC
Host A Host B Device DBGU JTAG/ICE
Host A Host B Device

Serial
Power / Eeprom RS232 oooooooo
Shdn
PHY RMII oooooooo
oooooooo
oooooooo
oooooooo
oooooooo

VCC 5V ISI Ethernet RMII/MII RS232 USB Hub USB DBGU JTAG/ICE PIO
High / Full Hub / Device

4.1.1 Interfaces
The board is equipped with a SAM9G45-CU chip (324-ball TFBGA package) together with the following
interfaces or peripherals:
„ DDR2/LPDDR memory interface is connected to 128 MB DDR2-SDRAM memory
„ External Bus Interface (EBI) is connected to three kinds of memory devices (DDR2-SDRAM, NAND
Flash and NOR Flash (not populated))

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Board Description

„ One TWI serial memory

„ One USB Host/Device multiplexed port interface
„ One USB Host port interface
„ One RS232 serial communication port
„ One DBGU serial communication port
„ One JTAG/ICE debug interface
„ One Ethernet 100-base TX with three status LEDs
„ One AC97 Audio DAC with headphone line out, line in and mono/stereo micro inputs
„ One TV interface (composite video output)
„ One 4.3" TFT LCD Module with touch screen and back light
„ One ISI connector (camera interface)
„ One Power red LED and two general-purpose green LEDs
„ Two user input push buttons
„ One joystick with 4-direction control and selector
„ One Wakeup input push button
„ One reset input push button
„ One DataFlash®/SD/SDIO/MMC plus card slot (4/8 bit interface)
„ One SD/SDIO/MMC card slot (4-bit interface)
„ One Lithium Coin Cell Battery Retainer for 12 mm cell size (memory backup usage)

4.1.2 Board Interface Connection

„ Ethernet using RJ45 connector (J15)
„ USB Host, support USB host using a type A connector (J12)
„ USB Host/Device, support USB host/device using a type micro AB connector (J14)
„ UART1 (Rx, Tx, Rts, Cts) connected to a 9-way male D-type RS232 connector (J11)
„ DBGU (Rx and Tx only) connected to a 9-way male D-type RS232 connector (J10)
„ JTAG, 20 pin IDC connector (J13)
„ SD/MMCplus connector (J5)
„ SD/MMC connector (J6)
„ Headphone (J7), line-in (J8) and microphone headset (J9)
„ Speaker output (JP15)
„ Image sensor connector (J17)
„ TFT LCD display (J16), with TouchScreen (J19) and BackLigth (J21)
„ Test points; various test points are located throughout the board
„ Main power supply (J2)

4.1.3 Push Button Switches

„ Reset, board reset (BP1)
„ Wake up, push button to bring processor out of low power mode (BP2)
„ Right and left click, user push button switches (BP4 and BP5)
„ Joystick (BP3)

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 Board Description

4.1.4 Display LCD and LEDs

„ Display, 480xRGBx272 pixels LCD module display connected to the PIO port E (LCD1)
„ One surface-mounted power red LED, user interface (D8)
„ Two surface-mounted green LEDs, user interface (D6 and D7)
„ Three surface-mounted LEDs indicate Ethernet status (D9, D10, D11)

Figure 4-2. Board Layout Commented

HOST
HOST DEVICE
DBGU RS232 USB USB JTAG ETHERNET POWER

J14
1 J2
2 20 TP1
J13
J12

k
J10 J11 Q2 1 19 k D9
J15
1 2 3 4 k D10

D8
k D11
C163
C177
1
D2
WAKE-UP

RR46
JP10 C182

C164
C172
C173 BUTTON

R33
TP4 MN18 MN17 C174

C176
MN6 MN7 R109

MN1
C171

C178
R185

R32

D3
MN20 C165 L2

JP9
Y4
RESET
R67

C136 JP5 R23 R92 R112

JP1

JP3
JP2
R93 C175
LINE BUTTON

MN2
MN15 C54

R103
C137

JP8
Y5 R94 R95 C181

R26
J8

R27

D5
L4
C122
R68

MN10 Y1

C29
C35

R28
INPUT MN11 C180 R108

RR44
R25

R107
C118 C128 R58

C19
R71 C36 C27

R102

R101
R100
R104
C129

JP4

R9 R3 R7
L5 Q1

JP16
C150 MN4
C130

L7
RR11

RR9

C151 2 8
MICROPHONE J9 Y3 MN5 L3
1
J1 MN14
7
RR19 RR25

R72 BP2 BP1

INPUT C131 TP6 L6
RR21

MN9 MN8 JP11

JP12
RR13

JP14 1
MN16

RR17
C146

C144

29
JP15

C52 J17
RR23
C48

C121 30
JP6 Y2 2

JP7
JP13

R10
R11
HEADPHONES C113 C112
J7
C193

HEADER J3
BACKUP
MN13

k
k
L22

C196 BATTERY

D6
D7
L24 C200

R121
VIDEO J20 C220
1

MN23

R142
OUTPUT R119 «RIGHT»
C221 BP4
L21
TP5 R143 USER BUTTON
C199

L18
Y7

R125
C192 BP5
BP3 «LEFT»
USER Y6
RR34 USER BUTTON
TP3
JOYSTICK RR36 RR35
TP2

2 20 2 40
J18 J23
1 19 1 39

J6
J5 SD/MMC 1
SD/MMC 0 SLOT
SLOT

LCD DISPLAY LCD EXTENSION ISI/CAMERA

CONNECTORS CONNECTOR

The major components of the SAM9G45-EKES board are shown in Figure 4-1.

4.2 Hardware Layout and Configuration

4.2.1 Processor
The board features the Atmel SAM9G45-CU 324-ball TFBGA package. This chip runs at a nominal fre-
quency of 400 MHz for the core and 133 MHz for the system bus.
For more information, refer to the last SAM9G45 datasheet available from http://www.atmel.com/

4.2.2 Clock Circuitry

The SAM9G45-EKES includes six clock sources:

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Board Description

„ Two are alternatives for the SAM9G45 main clock,

„ One crystal and one crystal oscillator are used for the Ethernet MII/RMII chip,
„ One crystal is used for the AC97 codec chip, and
„ One crystal or one crystal oscillator is used for the TV encoder.

Table 4-1. Main Components Associated with the Clock Systems

Quantity Description Component assignment
1 Crystal for Internal Clock, 12 MHz Y1
1 Crystal for RTC Clock, 32.768 kHz Y2
1 Oscillator for Ethernet Clock RMII, 50 MHz Y4
1 Crystal for Ethernet Clock MII, 25 MHz Y5
1 Crystal for AC91 Codec Clock, 24.576 MHz Y3
Crystal for TV Encoder Clock, 13 MHz, or Y7
1
Oscillator for TV Encoder, 13 MHz Y6

4.2.3 Reset Circuitry

The reset sources are:
„ Power on reset
„ Push button reset
„ JTAG reset from an in-circuit emulator interface.

4.2.4 Memory

4.2.4.1 External Memories

The SAM9G45 features a DDR2/LPDDR memory interface and an External Bus Interface (EBI) to permit
interfacing to a wide range of external memories and to almost any kind of parallel peripheral.
The SAM9G45-EKES board is equipped with DDR2/LPDDR devices featuring 128 MB of DDR2-
SDRAM memory (Micron MT47H64M8B6-3 16Meg*8*4).
The External Bus Interface (EBI) is connected to three kinds of memory devices:
„ One Parallel Flash AT49SV322DT (not populated by default)
„ Two DDR2-SDRAM MT47H64M8B6-3
„ One NAND Flash MT29F2G16ABD (not populated by default) or MT29F2G08ABD (single footprint)
The chip select NCS0, NCS1 and CS3 are used for NOR Flash, DDR2-SDRAM and NAND Flash mem-
ories, respectively. Furthermore, a dedicated jumper can disconnect each of these NCS0, NCS1, and
NCS3 signals, making them available for other functions.

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 Figure 4-3.

AT91SAM9G45-EKES User Guide

DDR_D[0..15]

DDR_A[0..13]
EBI0 - DDR2

MN6 MN7
DDR_A0 H8 C8 DDR_D0 DDR_A0 H8 C8 DDR_D8
DDR_A1 H3 A0 DDR2 SDRAM DQ0 C2 DDR_D1 DDR_A1 H3 A0 DDR2 SDRAM DQ0 C2 DDR_D9
DDR_A2 H7 A1 DQ1 D7 DDR_D2 DDR_A2 H7 A1 DQ1 D7 DDR_D10
DDR_A3 J2 A2 MT47H64M8CF - 3 DQ2 D3 DDR_D3 DDR_A3 J2 A2 MT47H64M8CF - 3 DQ2 D3 DDR_D11
DDR_A4 J8 A3 DQ3 D1 DDR_D4 DDR_A4 J8 A3 DQ3 D1 DDR_D12
DDR_A5 J3 A4 DQ4 D9 DDR_D5 DDR_A5 J3 A4 DQ4 D9 DDR_D13
DDR_A6 J7 A5 DQ5 B1 DDR_D6 DDR_A6 J7 A5 DQ5 B1 DDR_D14
DDR_A7 K2 A6 DQ6 B9 DDR_D7 DDR_A7 K2 A6 DQ6 B9 DDR_D15
DDR_A8 K8 A7 DQ7 DDR_A8 K8 A7 DQ7
DDR_A9 K3 A8 B7 DDR_A9 K3 A8 B7
A9 DQS DDR_DQS0 A9 DQS DDR_DQS1
DDR_A10 H2 A8 DDR_A10 H2 A8
DDR_A11 K7 A10 DQS DDR_A11 K7 A10 DQS
DDR_A12 L2 A11 B3 DDR_A12 L2 A11 B3
A12 RDQS/DM DDR_DQM0 A12 RDQS/DM DDR_DQM1
DDR_A13 L8 A2 DDR_A13 L8 A2
A13 RDQS/NU 1V8 A13 RDQS/NU 1V8
BA0 G2 A1 C55 100nF BA0 G2 A1 C56 100nF
DDR_BA0 BA0 VDD BA0 VDD
BA1 G3 E9 C57 100nF BA1 G3 E9 C58 100nF
DDR_BA1 BA1 VDD BA1 VDD
H9 C59 100nF H9 C60 100nF
VDD L1 VDD L1
VDD C61 100nF VDD C62 100nF
F9 F9
ODT E1 ODT E1
VDDL C63 100nF VDDL C64 100nF
CKE F2 A9 C65 100nF CKE F2 A9 C66 100nF
DDR_CKE CKE VDDQ CKE VDDQ
C1 C67 100nF C1 C68 100nF
CK E8 VDDQ C3 CK E8 VDDQ C3
DDR_CLK CK VDDQ C69 100nF CK VDDQ C70 100nF
NCK F8 C7 C71 100nF NCK F8 C7 C72 100nF
DDR_NCLK CK VDDQ CK VDDQ
C9 C73 100nF C9 C74 100nF
VDDQ VDDQ
CS G8 E2 DDR_VREF CS G8 E2 DDR_VREF
DDR_CS CS VREF CS VREF
CAS G7 A3 C75 CAS G7 A3 C76
DDR_CAS CAS VSS CAS VSS
RAS F7 E3 100nF RAS F7 E3 100nF
DDR_RAS RAS VSS RAS VSS
J1 J1
NW E F3 VSS K9 NW E F3 VSS K9
DDR_W E WE VSS WE VSS
A7 A7
VSSQ B2 VSSQ B2
G1 VSSQ B8 G1 VSSQ B8
L3 RFU1 VSSQ D2 L3 RFU1 VSSQ D2
L7 RFU2 VSSQ D8 L7 RFU2 VSSQ D8
RFU3 VSSQ RFU3 VSSQ
E7 E7
VSSDL VSSDL
Board Description

4-5
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 4-6
6481B–ATARM–27-Nov-09
Board Description

H_D[0..15]

H_A[1..21]

R_D[0..15]

R_A[2..15]
Figure 4-4.

MN8 MN9 MN10

EBI1_DDR_A2 H8 C8 EBI1_DDR_D0 EBI1_DDR_A2 H8 C8 EBI1_DDR_D8 EBI1_FLASH_A1 E1 E2 EBI1_FLASH_D0
EBI1_DDR_A3 H3 A0 DDR2 SDRAM DQ0 C2 EBI1_DDR_D1 EBI1_DDR_A3 H3 A0 DDR2 SDRAM DQ0 C2 EBI1_DDR_D9 EBI1_FLASH_A2 D1 A0 I/00 H2 EBI1_FLASH_D1
EBI1_DDR_A4 H7 A1 DQ1 D7 EBI1_DDR_D2 EBI1_DDR_A4 H7 A1 DQ1 D7 EBI1_DDR_D10 EBI1_FLASH_A3 C1 A1 F L ASH I/O1 E3 EBI1_FLASH_D2
EBI1_DDR_A5 J2 A2 MT47H64M8CF - 3 DQ2 D3 EBI1_DDR_D3 EBI1_DDR_A5 J2 A2 MT47H64M8CF - 3 DQ2 D3 EBI1_DDR_D11 EBI1_FLASH_A4 A1 A2 I/O2 H3 EBI1_FLASH_D3
EBI1_DDR_A6 J8 A3 DQ3 D1 EBI1_DDR_D4 EBI1_DDR_A6 J8 A3 DQ3 D1 EBI1_DDR_D12 EBI1_FLASH_A5 B1 A3 AT49SV322DT I/O3 H4 EBI1_FLASH_D4
EBI1_DDR_A7 J3 A4 DQ4 D9 EBI1_DDR_D5 EBI1_DDR_A7 J3 A4 DQ4 D9 EBI1_DDR_D13 EBI1_FLASH_A6 D2 A4 I/O4 E4 EBI1_FLASH_D5
EBI1_DDR_A8 J7 A5 DQ5 B1 EBI1_DDR_D6 EBI1_DDR_A8 J7 A5 DQ5 B1 EBI1_DDR_D14 EBI1_FLASH_A7 C2 A5 I/O5 H5 EBI1_FLASH_D6
EBI1_DDR_A9 K2 A6 DQ6 B9 EBI1_DDR_D7 EBI1_DDR_A9 K2 A6 DQ6 B9 EBI1_DDR_D15 EBI1_FLASH_A8 A2 A6 I/O6 E5 EBI1_FLASH_D7
EBI1_DDR_A10 K8 A7 DQ7 EBI1_DDR_A10 K8 A7 DQ7 EBI1_FLASH_A9 B5 A7 I/O7 F2 EBI1_FLASH_D8
EBI1_DDR_A11 K3 A8 B7 EBI1_DDR_A11 K3 A8 B7 EBI1_FLASH_A10 A5 A8 I/O8 G2 EBI1_FLASH_D9
A9 DQS DQS0_EBI1 A9 DQS DQS1_EBI1 A9 I/O9
EBI1_DDR_A12 (SDA10) H2 A8 EBI1_DDR_A12 (SDA10) H2 A8 EBI1_FLASH_A11 C5 F3 EBI1_FLASH_D10
EBI1_DDR_A13 K7 A10 DQS EBI1_DDR_A13 K7 A10 DQS EBI1_FLASH_A12 D5 A10 I/O10 G3 EBI1_FLASH_D11
EBI1_DDR_A14 L2 A11 B3 EBI1_DDR_A14 L2 A11 B3 EBI1_FLASH_A13 B6 A11 I/O11 F4 EBI1_FLASH_D12
A12 RDQS/DM DQM0_EBI1 A12 RDQS/DM DQM1_EBI1 A12 I/O12
EBI1_DDR_A15 L8 A2 EBI1_DDR_A15 L8 A2 EBI1_FLASH_A14 A6 G5 EBI1_FLASH_D13
A13 RDQS/NU 1V8 A13 RDQS/NU 1V8 EBI1_FLASH_A15 C6 A13 I/O13 F5 EBI1_FLASH_D14
BA0_EBI1 G2 A1 BA0_EBI1 G2 A1 EBI1_FLASH_A16 D6 A14 I/O14 G6 EBI1_FLASH_D15
BA0_EBI1 BA0 VDD C80 100nF BA0 VDD C81 100nF A15 I/O15
BA1_EBI1 G3 E9 C82 100nF BA1_EBI1 G3 E9 C83 100nF EBI1_FLASH_A17 E6
BA1_EBI1 BA1 VDD BA1 VDD A16
H9 C84 100nF H9 C85 100nF EBI1_FLASH_A18 B2
VDD L1 VDD L1 EBI1_FLASH_A19 C3 A17 A3
VDD C86 100nF VDD C87 100nF A18 RDY/ BUSY
F9 F9 EBI1_FLASH_A20 D4
ODT E1 ODT E1 EBI1_FLASH_A21 D3 A19
VDDL C88 100nF VDDL C89 100nF A20 C4
CKE_EBI1 F2 A9 CKE_EBI1 F2 A9 NC1 F6
CKE_EBI1 CKE VDDQ C90 100nF CKE VDDQ C91 100nF NC
C1 C92 100nF C1 C93 100nF R39 100K
CLK_EBI1 E8 VDDQ C3 CLK_EBI1 E8 VDDQ C3 B4
CLK_EBI1 CK VDDQ C94 100nF CK VDDQ C95 100nF 1V8 RESET 1V8
EBI1 - DDR2 + Flash

NCLK_EBI1 F8 C7 C96 100nF NCLK_EBI1 F8 C7 C97 100nF A4

NCLK_EBI1 CK VDDQ CK VDDQ EBI1_NW E/NW R0/CFW E WE
C9 C98 100nF C9 C99 100nF G4
VDDQ VDDQ B3 VCC C100
1V8 VPP
CS_EBI1 G8 E2 VREF1 CS_EBI1 G8 E2 VREF1 F1 H1 100nF
CS_EBI1 CS VREF CS VREF CE GND
G1 H6
EBI1_NRD/CFOE OE GND
1S
CAS_EBI1 G7 A3 C101 CAS_EBI1 G7 A3 C102 CBGA
CAS_EBI1 CAS VSS CAS VSS
RAS_EBI1 F7 E3 100nF RAS_EBI1 F7 E3 100nF DNP
RAS_EBI1 RAS VSS RAS VSS
J1 J1
W E_EBI1 F3 VSS K9 W E_EBI1 F3 VSS K9
W E_EBI1 WE VSS WE VSS
A7 A7
VSSQ B2 VSSQ B2 JP9
VSSQ VSSQ R40 470K
G1 B8 G1 B8 1V8
RFU1 VSSQ RFU1 VSSQ EBI1_NCS0
L3 D2 L3 D2
L7 RFU2 VSSQ D8 L7 RFU2 VSSQ D8
RFU3 VSSQ RFU3 VSSQ
E7 E7
VSSDL VSSDL

VREF1
DDR_VREF

EBI1_NAND_FSH_D[0..15]

MN11
PC5 (NANDCLE) D5 H4 EBI1_NAND_FSH_D0
(NANDALE) C4 CLE I/O0 J4 EBI1_NAND_FSH_D1
PC4 ALE NAND F L ASH I/O1
EBI1_NANDOE R42 0R RE D4 K4 EBI1_NAND_FSH_D2
JP10 0R WE C7 RE MT29F 2G08ABD I/O2 K5 EBI1_NAND_FSH_D3
EBI1_NANDW E R43
(NCS3) CE C6 WE I/O3 K6 EBI1_NAND_FSH_D4
PC14 CE I/O4
1V8 R46 470K J7 EBI1_NAND_FSH_D5
(RDY/BSY) 0R RB C8 I/O5 K7 EBI1_NAND_FSH_D6
PC8 R44
1K R/B I/O6 J8 EBI1_NAND_FSH_D7
R45
WP C3 I/O7 H3 EBI1_NAND_FSH_D8
1V8 WP N.C26
R41 470K J3 EBI1_NAND_FSH_D9
G5 N.C27 H5 EBI1_NAND_FSH_D10
LOCK N.C28 J5 EBI1_NAND_FSH_D11 Optional 16bits DATA BUS
R47 N.C29 H6 EBI1_NAND_FSH_D12 With AT29F2G16ABD Micron
DNP A1 N.C30 G6 EBI1_NAND_FSH_D13
A2 N.C1 N.C31 H7 EBI1_NAND_FSH_D14
A9 N.C2 N.C32 G7 EBI1_NAND_FSH_D15
A10 N.C3 N.C33
B1 N.C4
B9 N.C5 L9
B10 N.C6 N.C34 L10
D6 N.C7 N.C35 M1
D7 N.C8 N.C36 M2
D8 N.C9 N.C37 M9
E3 N.C10 N.C38 M10
E4 N.C11 N.C39
E5 N.C12 1V8
E6 N.C13 D3
N.C14 VCC C103 100nF
E7 G4 C104 100nF
E8 N.C15 VCC H8
N.C16 VCC C105 100nF
F3 J6 C106 100nF
F4 N.C17 VCC
F5 N.C18
F6 N.C19
F8 N.C20 C5
G3 N.C21 VSS F7
G8 N.C22 VSS K3
L1 N.C23 VSS K8
L2 N.C24 VSS
N.C25 VF BGA- 63
MT29F2G08ABDHC:D

AT91SAM9G45-EKES User Guide

 Board Description

4.2.5 Power Supplies

The SAM9G45 Board contains four regulated power supplies:
„ 3.3 VDC Supply
„ 1.8 VDC Supply
„ 1.0 VDC Core Supply
„ 1.0 VDC Core UTMI Supply, PLL
The outputs of these regulated power supplies1 are distributed as necessary to each part of the circuit
board.
„ The 3.3 VDC Supply is generated by an LTC1765-3.3 chip. It accepts VIN 5 VCC power and outputs a
regulated +3.3 V to most other circuits in the SAM9G45-VB.
„ The 1.8 VDC Supply (VDDIOM0, VDDIOM1) is generated by an LT1765-1.8. It is powered by VIN
5 VCC power and outputs a regulated +1.8V.
„ The 1.0 VDC Core Supply (VDDCORE) is generated by a TPS60500 IC. It is powered by the VIN
5 VCC power.
„ The 1.0 VDC Core Supply (VDDUTMIC, VDDPLLUTMI and VDDPLLA) is generated by a CMOS
voltage regulator R1100D series. It is powered by the output of the 3.3 VDC Supply.

Note: 1. Corresponding test points (TP1 to TP4, GND) are used with jumpers (JP1.1 to JP7) to
permit probing of these voltages.

AT91SAM9G45-EKES User Guide 4-7

6481B–ATARM–27-Nov-09
 4-8
6481B–ATARM–27-Nov-09
Board Description

3V3 J1-1
C1 1 2
D1 VDDUTMII
180nF L1
1 2
VDDANA
10uH 150mA
Figure 4-5.

J2 3V3 R1

2
5V MN1 L2 BAT20J 1R
1 3 6 C3
2 C2 4 VIN1 SW 1 5 100nF
2.2uF VIN2 SW 2 2.2uH C4 C5

BOOST
D2 11 12 10uF 4.7uF

3
SHDN LT1765-3.3 FB
5V
R2 7
100K 10 NC1 D3 L3
2.1 MM SOCKET 15 NC2
STPS2L30A VDDOSC

SYNC
GND1
GND2
GND3
GND4
GND5
VC
NC3 10uH 150mA
R3

1
8
9

14
17
16
13
C6 1R
2.2nF C7
100nF
C8
4.7uF

1 3
JP1
2

VDDIOP0
FORCE 1 3
POWER JP2
C9
2

ON D4 VDDIOP1
180nF 1 3
JP4
1 2 JP3
2

5V 1V8 VDDIOP2

2
MN2 L4 BAT20J
Q1 VDDISI
3 6 1V VDDUTMIC J1-2
C10 4 VIN1 SW 1 5 MN3 3 4
2
1

VIN2 SW 2 VDDUTMIC
1 6 2.2uF 2.2uH C12

BOOST
11 12 10uF
C11 SHDN LT1765-1.8 FB C13 C14
VDD
OUT

15pF 7 2.2uF 2.2uF

GND

R4 2 5 10 NC1 D5
SHDN NC2
15 R1100D101C
3

STPS2L30A

SYNC
GND1
GND2
GND3
GND4
GND5
VC
5V NC3
10K

1
8
9

14
17
16
13
3 4 C15 L5 J1-4
2.2nF 7 8 VDDPLLUTMI
10uH 150mA
Si1563EDH R7
1R
C20
100nF
C21
4.7uF
R5
10K C16 C17
1uF 1uF L6
VDDPLLA
10uH 150mA
Power Supply and Management Power Block

8 6 3 4
R9
3V3 1V 1R
C1M C1P C2M C2P
C23
5 7 100nF
VIN VOUT C24
C18 C19 R6 4.7uF
2.2uF 10pF 68K
TPS60500
10
FB C22
22uF
1 2 R8 1V
EN GND PG 220K J1-3
MN4 5 6 VDDCORE
9

1V8

1 3
JP5
2

VDDIOM0
1 3
JP6
2

VDDIOM1

J3 3V3

1 3
JP7
C25
2

100nF

VDDBU VDDBU

AT91SAM9G45-EKES User Guide

 Board Description

4.2.6 Debug Interface

4.2.6.1 JTAG/ICE
Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a stan-
dard USB-to-JTAG in-circuit emulator.

Figure 4-6. JTAG Interface

3V3

RR42
100K

5
6
7
8
3V3 J13 3V3

2 1

4
3
2
1
4 3 R84 DNP NTRST NTRST
6 5 TDI TDI
8 7 TMS TMS
10 9 TCK TCK
12 11 R85 0R RTCK RTCK
14 13 TDO TDO
16 15 R86 0R NRST NRST
18 17
20 19
R87
DNP

ICE INTERFACE

4.2.6.2 DBGU Com Port

This UART is connected to the DB-9 male socket through an RS-232 Transceiver (TXD and RXD only).

Figure 4-7. DBGU Com Port

3V3 MN18
16 1
C153 VCC C1+ C156
SERIAL DEBUG PORT 100nF 100nF
15 3V3
MALE RIGHT ANGLE GND 3
C155 2 C1- 4
100nF V+ C2+ C158
1 100nF
6 C160 R80 R82
2 100nF 6 5 100K 100K
7 V- C2-
3 14 11
8 T PB13
4
9 7 10
5 T

13 12
R PB12
11

10

R83 0R
8 9
R
J10
ADM3202ARNZ

AT91SAM9G45-EKES User Guide 4-9

6481B–ATARM–27-Nov-09
Board Description

4.2.6.3 User Serial Com Port

The USART1 is used as a user serial com port. This USART1 is buffered with an RS-232 Transceiver
(TXD, RXD and handshake CTS/RTS control) and connected to the DB-9 male socket. Software must
assign the appropriate PIO pins (PB5 = RXD1, PB4 = TXD1, PD16 = RTS1, PD17 = CTS1) to enable the
UART1 function.

Figure 4-8. User Serial Com Port

MN17 3V3
1 16
3V3 C152 C1+ VCC C154 RS232 COM PORT
100nF 100nF
15
3 GND MALE RIGHT ANGLE
4 C1- 2 C157
C159 C2+ V+ 100nF
R79 R81 100nF 1
100K 100K C161 6
5 6 100nF 2
C2- V- 7
11 14 3
PB4 T 8
4
10 7 9
PD16 T 5

12 13
PB5 R

10

11
9 8
PD17 R
J11
ADM3202ARNZ

Refer to the SAM9G45 datasheet for more information about the SAM9G45 USARTs.

4.2.6.4 USB Port

The SAM9G45-EKES features USB communication ports:
„ Two Host Ports: Full speed OHCI and High speed EHCI
„ One Device Port: High speed.
USB Host Port0 is directly connected to the first UTMI transceiver. The second Host Port (Port1) is mul-
tiplexed with the USB device High speed and connected to the second UTMI port.
„ One USB high/full speed type standard A connector
„ One USB interface Host/Device Micro AB connector
Refer to the SAM9G45 datasheet for detailed programming information.

4-10 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Board Description

Figure 4-9. USB Port

J12
292303-1 USB HOST INTERFACE
1 2
HDMA
4 3
HDPA
C162
100nF
5 6

5V

L15 MN20
8 1 (ENA)
OUTA ENA PD1
BLM21PG221SN1x
C164 7 2 (FLGA)
33 uF IN FLGA PD2
C163
16V 100nF
6 3 (FLGB)
GNG FLGB PD4
L16
5 4 (ENB)
OUTB ENB PD3
BLM21PG221SN1x
C165 SP2526A-2
33 uF
16V

R88 47K 3V3

(VBUS)
PB19
R89
C166 68K
10pF R90
ZX62-AB-5P 47K
7

1
VBUS
2
DHS

DM HDMB
3
DP HDPB
ID 4 (IDUSB)
PD28
GND 5

6
J14
USB HOST/DEVICE INTERFACE

C167
100nF

4.2.6.5 Ethernet 10/100 (EMAC) Port

The port is compatible with IEEE® Standard 802.3.
The SAM9G45-EKES is equipped with a Davicom DM9161AEP 10/100 Mbps Fast Ethernet Physical
Layer TX/FX Single Chip Transceiver. It contains the entire physical layer functions of 100BASE-TX as
defined by IEEE 802.3u, including the Physical Coding Sublayer (PCS), Physical Medium attachment
(PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder
(ENC/DEC), and Twisted Pair Media Access Unit (TPMAU).
The Ethernet interface integrates an RJ45 connector with an embedded transformer, and three status
LEDs.
The Ethernet interface provides two selectable modes, MII or RMII (Reduced MII), for 100Base-Tx or
10Base-Tx. The MII and RMII interfaces are capable of both 10Mb/s and 100Mb/s data rates as
described in the IEEE 802.3u standard. The signals used by MII and RMII interfaces are described in the
table below.

AT91SAM9G45-EKES User Guide 4-11

6481B–ATARM–27-Nov-09
Board Description

Table 4-2. Pin Mapping for Normal MII and Reduced MII
Pin Name Normal MII Mode Reduced MII Mode
SAM9G45 DM9161 SAM9G45 DM9161
ETX0-ETX1 ETX[0:1] transmit data TXD [0:1] ETX[0:1] TXD [0:1]
ETX2-ETX3 ETX[2:3] transmit data TXD [2:3] NC NC
ETXEN ETXEN: transmit enable TXEN ETXEN: transmit enable TXEN
ETXER ETXER: transmit error TXER/TXD[4] NC NC
ETXCK/REFCK ETXCK: transmit clock TXCLK REFCK: reference clock REF_CLK
ERX0-ERX1 ERX[0:1]: receive data RXD [0:1] ERX[0:1]: receive data RXD [0:1]
ERX2-ERX3 ERX[2:3]: receive data RXD [2:3] NC NC
RXER/RXD[4]/
ERXER ERXER: receive error ERXER: receive error RPTR/NODE
RPTR/NODE
ECRSDV: carrier sense /
ERXDV ERXDV: receive valid data RXDV CRS DV
data valid
ERXCK ERXCK: receive clock RXCLK NC NC
ECOL ECOL: collision detect COL NC NC
ECRS: carrier sense /
ECRS CRS (PHYAD[2:4] NC NC
data valid
EMDC: management data
EMDC EMDC: management data clock MDC MDC
clock
EMDIO: management data EMDIO: management data
EMDIO MDIO MDIO
input / output input / output
RESET# XT1 RESET# XT1
NRST NRST: microcontroller reset NRST: microcontroller reset
(25 MHz) (REF_CLK 50MHz)

4-12 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 3V3

AT91SAM9G45-EKES User Guide

R91 10K

Y4
1 4
C168
EO DDV
50 MHz 100nF
2 3
C169 C170
SSV TUO

ufacturer's datasheet.
CFPS-39IB 50.0MHZ 18pF 18pF
Y5 C171
4 3 100nF
GND_ETH
R92 R93 DNP 1 2
0R
Figure 4-10. Ethernet Port

25MHz

MN22
(TX_CLK) R94 0R 42 43 R96 R97
PA17 REF_CLK/XT2 XT1 49R9 49R9
(TXD3) R98 DNP 17 1% 1%
15
16

PA7 TXD3
(TXD2) R99 DNP 18 J15
PA6 TXD2
(TXD1) 19 7 1
PA11 TXD1 TX+
+DT +XT 1
(TXD0) 20
PA10 TXD0
(TX_EN) 21 4
PA14 TX_EN
TC
R95 DNP 22
TX_CLK/ISOLATE 8 2
TX-
-DT -XT 2
(RXD3) R100 DNP 26
PA9 RXD3/PHYAD3
(RXD2) R101 DNP 27 AVDDT
PA8 RXD2/PHYAD2
(RXD1) 28
PA13 RXD1/PHYAD1
(RXD0) 29 3 3
PA12 RXD0/PHYAD0 RX+
+DR +XR 3

(RX_CLK) R102 DNP 34 5

PA28 RX_CLK/10BTSER
TC
(RX_DV) 37
PA15 RX_DV/TESTMODE 4 6
RX-
-DR -XR 6
(TX_ER) R103 DNP 16
PA27 TX_ER/TXD4 AVDDT
(RX_ER) 38 L17
PA16 RX_ER/RXD4/RPTR 742792093 R105 R106 C173
(COL) R104 DNP 36 1 C172 100nF 49R9 49R9 100nF
PA30 COL/RMII AVDDR
57 57
(CRS) R107 DNP 35 1% 1% 7
57
PA29 CRS/PHYAD4
CN 4
R108 1.5K 2 C174 100nF C175 C176
3V3 AVDDR
(MDC) 24 10uF 10uF
PA18 MDC
5
(MDIO) 25 DM9161AEP AVDDT 10V 10V GND_ETH
PA19 MDIO
Fn1
C178 100nF
(MDINTR) 32 9 C177 8
57
PD15 MDINTR AVDDT
7
100nF
39 5
DISMDIX AGND
8
6
3V3 AGND 46 J00-0061NL

8
7
6
5
8
7
6
5
8
7
6
5
JP16 AGND 3V3 GND_ETH
R185 0R
C179 100nF 41 47 GND_ETH
3V3 DVDD BGRESG RJ45 ETHERNET CONNECTOR
8
7
6
5

C180 100nF 30 R109

DVDD RR46 3V3
6.8K

1
2
3
4
1
2
3
4
1
2
3
4
C181 100nF 23 1% 10K 1K
DVDD 48 YELLOW R110 FULL DUPLEX
15 BGRES 31 D9
1
2
3
4

RR43 RR44 RR45 33 DGND LEDMODE 11 1K

10K 10K 10K 44 DGND LED0/OP0 12 GREEN R111 SPEED 100
DGND LED1/OP1 13 D10
R112 0R 10 LED2/OP2 14 1K
PW RDW N CABLESTS/LINKSTS GREEN R113 LINK&ACT
40 45 D11
NRST RESET N.C

3V3

C182
10uF
10V

R114 0R R115 0R

GND_ETH
Board Description

4-13
For more information about the Ethernet controller device, refer to the Davicom DM9161 controller man-

6481B–ATARM–27-Nov-09
Board Description

4.2.7 Audio Stereo Interface

The SAM9G45-EKES includes an AD1981B AC97 SoundMAX® CODEC for digital sound input and out-
put. This interface includes audio jacks for MIC input (J9), Line audio input (J8), Headphone line output
(J7) and a 2-point speaker output connector (JP15).
It is compliant with AC97 Component Specification V2.2.

4-14 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 CLOCK SELECTION - PIN STRAPING TABLE C112100uF 6V3 3.5 PHONEJACK STEREO

+
L8 3 J7 5
RA=1K RB=1K CODEC ID CLK FREQ 742792093

OUT OUT PRIMARY 24.576 MHz Local XTAL

+
OUT IN SECONDARY 12.288 MHz Ext. BITCLK L9 2 HEADPHONE
IN OUT PRIMARY 48.000 MHz Ext. BITCLK (Into XTAL-IN) 742792093 LINE-OUT
IN IN PRIMARY 14.318 MHz Ext. BITCLK (Into XTAL-IN) C113100uF 6V3

(see table) AVDD_AC97 R56 R57 C114 C115

C117 1K 1K 470pF 470pF 1 4
100nF

AT91SAM9G45-EKES User Guide

R58 DNP
RA
C118
RB C116 10uF
100nF 10V AGND_AC97
R59 DNP

AGND_AC97 C119 R61 22K R62 22K

(EXT_CLK) R60 DNP 1uF
PE31
C124 C121
C120 22pF 100nF 3V3 10uF

48
47
46
45
44
43
42
41
40
39
38
37
MN15 10V
AVDD_AC97

manufacturer's datasheet.
NC

ID1
ID0
Y3 C122 C125

EAPD
10uF 100nF

SPDIF
24.576MHz

AVSS3
AVSS2
6 C126 100nF

AVDD3
AVDD2
AGND_AC97

10V MN16
AVDD_AC97 JP14 DNP VDD

HP_OUT_L

HP_OUT_R
MONO_OUT
C123 22pF 4 -IN
1 36 1 3 Vo1 5
2 DVDD1 LINE_OUT_R 35 3 +IN
3 XTL_IN LINE_OUT_L 34 C127 100nF

2
4 XTL_OUT AVDD4 33
DVSS1 AVSS4 SPEAKER OUTPUT
(AC97TX) 5 32 C128 270pF JP15
PD7 SDATA_OUT AFILT4
(AC97CK) 6 AD1981B 31 C129 270pF DNP
PD9 BIT_CLK AFILT3
7 30 C130 270pF
(AC97RX) 8 DVSS2 AFILT2 29
Figure 4-11. Audio Stereo Interface

PD6 SDATA_IN AFILT1 C131 270pF

9 28 VREFOUT Av=1 8
DVDD2 VREFOUT VDD/2
(AC97FS) 10 27 C132 100nF 2 Bypass Vo2
PD8 SYNC VREF
11 26
NRST RESET AVSS1
12 25 C134 C133 100nF
NC1 AVDD1 1uF C135
100nF 1 Shutdown
Bias
GND
AGND_AC97 SSM2211
7

PHONE_IN
AUX_L
AUX_R
JS1
JS0
CD_L
CD_GND_REF
CD_ R
MIC1
MIC2
LINE_IN_L
LINE_IN_R

13
14
15
16
17
18
19
20
21
22
23
24
AGND_AC97

R63 2.2K
C136 R64 4.7K 3.5 PHONEJACK STEREO
1uF L10 3 J8 5
R65 2.2K 742792093

C137 R66 4.7K

1uF L11 2 LINE-IN
742792093

AGND_AC97 R67 R68 C138 C139

4.7K 4.7K 470pF 470pF 1 4

OPTIONAL VOICE
FILTER COMPONENTS AGND_AC97

C140 100nF R69 100R 3.5 PHONEJACK STEREO

L12 3 J9 5
742792093
5V AVDD_AC97
L13 C141 100nF R70 100R
L14 2 MONO / STEREO
10uH 150mA 742792093 MICROPHONE INPUT
C144 C145 C146
10uF 47uF C142 C143 R71 R72
10V 100nF 6V3 10nF 10nF 3.9K 3.9K C147 C148
470pF 470pF 1 4
R73 0R
C149
AGND_AC97 470pF
AGND_AC97

R74
OPTIONAL MIC BIASING FROM VREFOUT AVDD_AC97 0R

VREFOUT R75 DNP R76 470R AGND_AC97

R77 DNP R78 470R

C150 C151
10uF 10uF
10V 10V

AGND_AC97
Board Description

4-15
For more information about the AC97 codec device, refer to the Analog Devices AD1981B controller

6481B–ATARM–27-Nov-09
Board Description

4.2.8 TV-Out Extension

The Chrontel™ CH7024 chip provides an interface between the SAM9G45 LCD Controller and a TV set
by converting LCD signals to TV signals.
The CH7024 is a TV encoder device which encodes the video signals and generates synchronization
signals for NTSC and PAL standards. Supported TV output formats are NTSC-M, NTSC-J, NTSC-433,
PAL-B/D/G/A/I, PAL-M, PAL-N and PAL-60. The CH7024 provides video output support for CVBS or S-
video.

Figure 4-12. TV-Out Extension Port

PE[0..30]

PE30 (B7)
PE29 (B6)
PE28 (B5)
PE27 (B4)
PE26 (B3)
PE25 (B2)
PE24 (B1)
PE23 (B0)
PE22 (G7)
PE21 (G6) 3V3
PE20 (G5)
PE19 (G4) L18
PE18 (G3) 742792093
PE17 (G2) MN23
PE16 (G1) 1V8
PE15 (G0) PE23 42 38
PE14 (R7) PE24 43 D0 VDDIO 16 L19
PE13 (R6) PE25 44 D1 DVDD 742792093
PE12 (R5) PE26 45 D2 C190 C191 C192 C193
PE11 (R4) PE27 46 D3 100nF 100nF 10uF 10uF
PE10 (R3) PE28 47 D4 10V 10V
PE9 (R2) PE29 48 D5 18
PE8 (R1) PE30 1 D6 DGND
PE7 (R0) PE15 2 D7
PE6 (LCDDEN) PE16 3 D8 32 L20
PE5 (LCDDOTCK) PE17 4 D9 AVDD_PLL C194 742792093
PE4 (HSYNC) PE18 5 D10 100nF
PE3 (VSYNC) PE19 6 D11 31
PE2 (LCDCC) PE20 7 D12 AGND_PLL 3V3
PE1 (LCDMOD) PE21 8 D13
PE0 (LCDPW R) PE22 9 D14 33 L21
PE7 10 D15 AVDD C195 742792093
PE8 11 D16 100nF C196
PE9 12 D17 36 10uF
PE10 13 D18 AGND 10V
PE11 14 D19
PE12 15 D20 25 L22
PE13 17 D21 AVDD_DAC C197 742792093
PE14 19 D22 100nF
D23 29 3V3
PE3 39 AGND_DAC
PE4 40 V C198
PE5 41 H 30 R116 33pF
PE6 20 XCLK ISET
1.2K 1% J20
DE 28 L24 3
R117 4.7K CVBS 1.8uH
3V3

3
C200 D13
R118 4.7K 27 R119 R120 C199 270pF 1 2

1
(TW DO) 21 Y 100pF
PA20 75R 75R
(TW CK0) 22 SPD BAT54SLT1G
PA21 SPC R121
26
23 C/CVBS
NRST RESET 75R
XI/FIN

3V3 24 37 Composite Video Output

NC P-OUT
XO

R122 DNP
CH7024B-DF-TR
34

35

Y6
1 OE TP5
VDD 4
R125
13 MHz 0R
2 VSS OUT 3 R124 DNP
Y7
SG-8002JC-13.0000M-PCB 4 3
DNP C205
DNP 1 2

C207 13MHz C206

10pF 10pF

The frequency accuracy must be +-20ppm or higher.

4.2.9 Software Controlled LEDs

Three users LED are provided for general use. The LEDs are connected to PIO port lines, allowing their
control through either GPIO or PWM control.
„ LEDs D6 to D8 are software controlled by PIO pins.
„ LEDs D9 to D11 indicate Ethernet traffic and link status. These are automatically managed by on-chip
microcontroller hardware. See Section 7.1 ”Schematics” .

4-16 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Board Description

Table 4-3. Discrete LEDs

LED Description Comment
D6 Green LED User software controlled
D7 Green LED User software controlled
D8 Red LED User software controlled
D9 Yellow LED Indicates transmission or reception via Ethernet
D10 Green LED Indicates speed 100
D11 Green LED Is lit when a good link test has been detected

Figure 4-13. Software Controlled LEDs

USER INTERFACE 3V3
D6 R10 470R
PD0
3V3 GREEN
D7 R11 470R
PD31
GREEN

R12
470R

PB15
PB16
D8
RED R15
470K

BP3
3 1 4 UP
PB14 LEFT 2 5 RIGHT
PB18 PUSH 3 6 DOWN

1 PD30 JOYSTICK
Q2 PB17
IRLML2402
2 C215 C216 C217 C218 C219
R141
10nF 10nF 10nF 100R 10nF 10nF
POWER LED PB[14..18]

4.2.10 Serial Peripheral Interface Controller (SPI)

The SAM9G45 provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to
interface with the on-board serial EEPROM.

Figure 4-14. SPI

3V3

DNP R53
Test point 470K
1 3 3V3
JP11
MN14
2

(SPI0_MISO) 8 6
PB0 SO VCC
(SPI0_MOSI) 1 C110
PB1 SI
(SPI0_SPCK) JP12 2 100nF
PB2 SCK
(SPI0_NPCS0) 4 7
PB3 CS GND

3 5
NRST RESET WP
AT45D321D
R55 W RITE PROTECT
SERIAL DATAFLASH DNP NORMALLY OPEN

AT91SAM9G45-EKES User Guide 4-17

6481B–ATARM–27-Nov-09
Board Description

4.2.11 Two Wire Interface (TWI)

The SAM9G45 has a full speed (400 kHz) master/slave I2C Serial Controller. The controller is fully com-
patible with the industry standard I2C and SMBus Interfaces. This port is used to interface with the on-
board Serial DataFlash, ISI and TV encoder interface.

Figure 4-15. TWI

3V3

R54

10K
MN13
(TW CK0) 6 1
PA21 SCL A0
(TW DO) 5 2
PA20 SDA A1 3
8 A3 JP13
3V3 VCC
C111
100nF 4 7
GND WP
AT24C512BN-SH25-B

SERIAL EEPROM

4.2.12 SD/MMC Interface

The SAM9G45-EKES has two high-speed 8-bit multimedia interfaces MMC/MMCPlus v4.1. The first
interface is used as an 8-bit interface (MCI1), connected to a CE-ATA connector footprint and an 8-bit
SD/MMC card slot. The second interface is used as a 4-bit interface (MCI0), connected to a 4-bit
SD/MMC card slot.
The users must provide their own compatible cards for use with these connectors.
Please note that the power is connected to VCC, which is 3.3 volts.

4-18 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 AT91SAM9G45-EKES User Guide
Figure 4-16. SD/MMC0-MMC1

3V3

3V3
8
7
6
5
8
7
6
5
8
7
6
5

RR34 RR35 RR36

8
7
6
5
68K 10K
R51 RR41 R52 68K
10K 68K 10K
1
2
3
4
1
2
3
4
1
2
3
4

(MCI1_W P)

1
2
3
4
PD29
(MCI0_CD) PD11 (MCI1_CD)
PD10
PA[0..5] PA[22..31]
J6 12 J5 16
PA3 (MCI0_DA1) R186 27R C109100nF 8 11 PA24 (MCI1_DA1) R192 27R 8 15
PA2 (MCI0_DA0) R187 27R 7 10 PA23 (MCI1_DA0) R193 27R 7 14
3V3 6 6
PA0 (MCI0_CK) R188 27R 5 PA31 (MCI1_CK) R194 27R 5
4 3V3 4
3 3 13
PA1 (MCI0_CDA) R189 27R 2 PA22 (MCI1_CDA) R195 27R 2 12
PA5 (MCI0_DA3) R190 27R 1 PA26 (MCI1_DA3) R196 27R 1 11
PA4 (MCI0_DA2) R191 27R 9 PA25 (MCI1_DA2) R197 27R 9 10

FPS009 C108 7SDMM-B0-2211

100nF
PA27 (MCI1_DA4) R198 27R
PA28 (MCI1_DA5) R199 27R
PA29 (MCI1_DA6) R200 27R
PA30 (MCI1_DA7) R201 27R

SD/MMC CARD INTERFACE - MCI0 SD/MMCPlus CARD INTERFACE - MCI1

Board Description

4-19
6481B–ATARM–27-Nov-09
Board Description

4.2.13 TFT LCD with Touch Panel

The SAM9G45 features an LCD controller. A 4.3" 480x272 Portrait Mode LCD provides the SAM9G45-
EKES with a low power LCD display, back light unit and a touch panel, similar to that used on commer-
cial PDAs.
The TFT LCD component is an LG®/PHILIPS®, model number LB043WQ1.
Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24-
bit data signals (8bitxRGB by default) or 16-bit data signals (5+6+5bitxRGB in option). This allows the
user to develop graphical user interfaces for a wide variety of end applications.
Warning: never connect/disconnect the LCD display from the board while the power supply is on. Doing
so may damage both units and is not covered by warranty.
The back light voltage is generated from a TPS61161 boost converter. It is powered directly by the VIN
5 VCC power (the control for the back light voltages is separated from the main board voltages due to
the specific voltage requirements of the LCD panel).

4-20 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 (pinxx = display pin number )

J24 3V3
pin45
1 pin44
2 pin43 VLED+
3 pin42 VLED-
4 pin41
5 pin40 YpLCD
6

AT91SAM9G45-EKES User Guide

pin39 XpLCD R180
Z7 7 pin38 YmLCD 10K
8 pin37 XmLCD
9 pin36
10 pin35
11 pin34 (LCDDEN) PE6
12 pin33
13 PE[0..30] {3,12}
pin32
14 pin31 R50 27R (LCDPWR) PE0
15 pin30 LCDDOTCK PE30 (B7)
16 pin29 PE29 (B6)
17
Figure 4-17. TFT LCD

pin28 1 RR48A 8 BLUE7 PE28 (B5)

4.3" 480x272 18 pin27 2 RR48B 7 BLUE6 PE27 (B4)
19 pin26 3 RR48C 6 BLUE5 R136 PE26 (B3)
TFT LCD DISPLAY 20 pin25 4 RR48D 5 BLUE4 4.7K PE25 (B2)
21 pin24 1 RR49A 8 BLUE3 PE24 (B1)
22 pin23 2 RR49B 7 BLUE2 R179 0R PE25 PE23 (B0)
23 pin22 3 RR49C 6 BLUE1 R178 0R PE24 PE22 (G7)
24 pin21 4 RR49D 5 BLUE0 R177 0R PE23 PE21 (G6)
25 pin20 1 RR50A 8 GREEN7 PE20 (G5)
26 pin19 2 RR50B 7 GREEN6 PE19 (G4)
PIN 45 27 pin18 3 RR50C 6 GREEN5 PE18 (G3)

LG PHILIPS
28 pin17 4 RR50D 5 GREEN4 PE17 (G2)
29 pin16 1 RR51A 8 GREEN3 PE16 (G1)
30 pin15 2 RR51B 7 GREEN2 PE15 (G0)
31 pin14 3 RR51C 6 GREEN1 R176 0R PE16 PE14 (R7)

on
32 pin13 4 RR51D 5 GREEN0 R175 0R PE15 PE13 (R6)

Conductors
TOP SIDE
33 pin12 1 RR52A 8 RED7 PE12 (R5)
34 pin11 2 RR52B 7 RED6 PE11 (R4)
PIN 1 35 pin10 3 RR52C 6 RED5 PE10 (R3)
36 pin9 4 RR52D 5 RED4 PE9 (R2)
37 pin8 1 RR53A 8 RED3 PE8 (R1)
38 pin7 2 RR53B 7 RED2 R174 0R PE9 PE7 (R0)
39 R48 is placed near processor
pin6 3 RR53C 6 RED1 R173 0R PE8 PE6 (LCDDEN)
40 pin5 4 RR53D 5 RED0 R172 0R PE7 PE5 (LCDDOTCK)
LB043WQ1 41 {12} LCDDOTCK
pin4 3V3 R48 33R PE4
42 pin3 C188 C189 PE3
43 pin2 100nF 10uF PE2 (LCDCC)
44 pin1 10V PE1
45 PE0 (LCDPWR)
XF2M45151A

R171 DNP PE24

BLUE7 R170 0R PE30

R169 DNP PE23

BLUE6 R168 0R PE29

R167 DNP PE22

BLUE5 R166 0R PE28

R165 DNP PE21

BLUE4 R164 0R PE27

R163 DNP PE20

BLUE3 R162 0R PE26
D12
STPS0540Z L23 5V R161 DNP PE18
VLED+ GREEN7 R160 0R PE22
22uH
C202 C201 R159 DNP PE17
1uF 2.2uF C208 C209 GREEN6 R158 0R PE21

4
MN25 TPS61161DRVT DNP DNP
6 R157 DNP PE16
VIN

SW
GREEN5 R156 0R PE20
YpLCD R130 0R (AD2Yp) PD22 {3,12}
5 (LCDCC) PE2 XmLCD R131 0R (AD1Xm) PD21 {3,12} R155 DNP PE15
VLED- 1 CTRL YmLCD R132 0R (AD3Ym) GREEN4 R154 0R PE19
FB PD23 {3,12}
2 XpLCD R133 0R (AD0Xp) PD20 {3,12}
R123 COMP R137 R153 DNP PE14

GND
THP
10R C203 10K GREEN3 R152 0R PE18
220nF

3
7
C210 R151 DNP PE13
220K C211 GREEN2 R150 0R PE17
DNP
20mA MAX 9 LEDs Back Light R149 DNP PE12
RED7 R148 0R PE14

This Resistor R147 DNP PE11

RED6 R146 0R PE13
is intentionally mounted
in place of C210 R145 DNP PE10
RED5 R144 0R PE12

R184 DNP PE9

RED4 R183 0R PE11

R182 DNP PE8

RED3 R181 0R PE10
Board Description

4-21
6481B–ATARM–27-Nov-09
Board Description

4.2.14 Push Buttons

The SAM9G45-EKES is equipped with two system push buttons, two user push buttons and one joy-
stick. The push buttons consist of momentary push button switches mounted directly to the board. When
any switch is depressed, a low (zero) appears at the associated input pin.
„ System push buttons:
– Reset, perform system reset
– Wakeup, perform system wake up
„ User push button:
– Right click
– Left click
„ Joystick:
– One touch, 5-way switching,
– Normally open momentary contacts,
– Push down to select in any position.

Figure 4-18. Push Buttons

3V3
VDDBU

R13 R14
100K 1K
BP1

NRST NRST

BP2

WAKE UP WAKE UP

BP4

RIGHT CLICK C220

PB7
R142
100R
10nF
BP5

LEFT CLICK C221

PB6
R143
100R
10nF

4.2.15 Expansion Slot

„ GPIO1 & GPIO2, LCD signals (PIO E) are routed to the connectors extension J23
„ All I/Os of the SAM9G45 Image Sensor Interface are routed to connectors J17
„ Touch screen signals and analog I/O are connected to J18
This allows the developer to extend the features of the board by adding external hardware components
or boards.

4-22 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Board Description

Figure 4-19. Expansion Slot

CONNECTOR EXTENTION FOR LARGE LCD
J23 TSM-120-01-L-DV
PE8 1 2 PE7
PE10 3 4 PE9
PE12 5 6 PE11
PE14 7 8 PE13
PE16 9 10 PE15
PE18 11 12 PE17
PE20 13 14 PE19
PE22 15 16 PE21
PE24 17 18 PE23
PE26 19 20 PE25
PE28 21 22 PE27
PE30 23 24 PE29
PE4 25 26 PE3
PE5 27 28
29 30
PE6 31 32 PE2
PE0 33 34 PE1
PD14 (GPIO1) 35 36 (GPIO2)
PD15
37 38
3V3 39 40

DNP
J18

PD21 (AD1Xm) 1 2 (AD0Xp)

PD20
PD23 (AD3Ym) 3 4 (AD2Yp)
PD22
5 6
PD25 7 8 PD24
PD27 9 10
R128 R129 PD26
PD19 11 12
PD18
DNP 13 14 DNP
15 16 5V
17 18
3V3 19 20 3V3
DNP
TSM-110-01-L-DV

IMAGE SENSOR CONNECTOR

3V3

C186 C187 C184

100nF 10uF 100nF
10V

J17
1 2
VDDISI 3 4
(CTRL1) 5 6 (CTRL2)
PD12 PD13
PA21 7 8 PA20
9 10 PB31
11 12 PB29
13 14 PB30
15 16 PB28
17 18 PB20
PB21 19 20 PB22
PB23 21 22 PB24
PB25 23 24 PB26
PB27 25 26 PB8
PB9 27 28 PB10
PB11 29 30

AT91SAM9G45-EKES User Guide 4-23

6481B–ATARM–27-Nov-09
 Section 5
Configuration

5.1 JTAG/ICE Configuration

Table 5-1. JTAG/ICE Configuration
Designation Default Setting Feature
R84 Not populated Disables the ICE NTRST input
R85 Soldered Enables the ICE RTCK return. R87 must be opened
R86 Soldered Enables the ICE NRST input
R87 Not populated Disables TCK <-> RTCK local loop

5.2 ETHERNET Configuration

RMII is the factory default mode.
To evaluate the MII mode, the user has to unsolder R92 and solder R93, R98 to R104, R107.
Two types of jumpers are used on the SAM9G45-EKES board:
„ 2-pin jumpers with two possible settings:
– Fitted: the circuit is closed, and
– Not fitted: the circuit is open
„ 3-pin jumpers with two possible positions, for which settings are presented in the following tables.

AT91SAM9G45-EKES User Guide 5-1

6481B–ATARM–27-Nov-09
Configuration

5.3 Jumpers Configuration

Table 5-2. Jumpers Configuration
Default
Designation Setting Feature
Closed J1-1 1-2 VDDUTMII 3V3
J1 Closed J1-2 3-4 VDDUTIMC 1V
(combined
jumper array) Closed J1-3 5-6 VDDCORE 1V
Closed J1-4 7-8 VDDPLLUTMI 1V
1-2 VDDIOP0 3V3
JP1 1-2 JP1
2-3 External power to VDDIOP0 3V3 nominal
1-2 VDDIOP1 3V3
JP2 1-2 JP2
2-3 External power to VDDIOP1 3V3 nominal
1-2 VDDIOP2 3V3
JP3 1-2 JP3
2-3 External power to VDDIOP2 3V3 nominal
Forces power on.
JP4 Opened To use the software shutdown control, JP4 must be opened.
3V battery backup must be present and JP7 jumper set in position 1-2
1-2 VDDIOM0 1V8
JP5 1-2 JP5
2-3 External power to VDDIOM0 1V8 nominal
1-2 VDDIOM1 1V8
JP6 1-2 JP6
2-3 External power to VDDIOM1 1V8 nominal
1-2 VDDBU Lithium 3V Battery
JP7 1-2 JP7
2-3 VDDBU 3.3V from regulator
BMS Enables Boot on the internal ROM; closed selects the boot from the external device connected
JP8 Opened
to NCS0
JP9 Closed Enables chip select access, Boot on the NCS0 (MN10 Flash)
JP10 Closed Enables chip select access, Boot on the NCS3 (MN12 NAND Flash)
JP11 Test point JP11.1: SO JP11.2: SI JP11.3: SCK
JP12 Closed Enables chip select access, Boot on the SPIO_NPCS0 (Serial Data Flash MN14)
JP13 Opened Set address A0 low (MN13 Serial EEPROM), enable Boot access.
JP14 JP14.1 = Line_Out_L JP14.3 = Line_Out_R
JP15 Used to connect a Loudspeaker
JP16 Closed DISMDIX (MN22)

5-2 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Configuration

5.4 Miscellaneous Configuration Items

N.P = not populated
P = populated

Table 5-3. Miscellaneous Configuration

Default
Designation Setting Feature
R20 N.P JTAGSEL
R21 P Connect TSADVREF to VDDANA (may be used for specific filtering)
R22 P Connect GNDANA to GND (may be used for specific filtering)
R24 P Force TST pin to GND (chip is set in non-test mode = normal operation mode)
Write protect NAND Flash (mount a 0-ohm resistor to write-protect the NAND
R47 N.P
Flash device)
Write protect serial Data Flash (mount a 0-ohm resistor to write-protect the serial
R55 N.P
Flash device)
R58, R59 N.P Clock selection Audio AC97 (see mapping table in Section 7.1 ”Schematics” )
R60 N.P External clock Audio AC97 (mount a 0-ohm resistor to connect it)
R75, R77 N.P Change bias from VREFOUT (see Section 7.1 ”Schematics” )
R69, R70 Voice filter components
R84,R85 ICE interface reset and clocking schemes (see Section 5.1 ”JTAG/ICE
R86,R87 Configuration” )
R92, R93,
R94, R95,
R98, R99
R100, R101 Ethernet interface, MII mode (see Section 5.2 ”ETHERNET Configuration” )
R102,R103
R104,R107
R112
Y6, R122,
N.P External 13 MHz oscillator (option) for the on-board video composite encoder
R124
TP1 GND Test point
TP2 GND Test point
TP3 GND Test point
TP4 GND Test point

5.5 PIO Configuration

5.5.1 Peripheral Signals Multiplexing on I/O Lines

The AT91SAMG45 product features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multi-
plex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be
assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs
define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers.

AT91SAM9G45-EKES User Guide 5-3

6481B–ATARM–27-Nov-09
Configuration

5.5.2 Multiplexing on PIO Controller A (PIOA)

"R.Select" = connection selectable via an on-board resistor (default not populated)

Table 5-4. PIO Multiplexing Port A

I/O Peripheral A Peripheral B Function and Comments Power
PA0 MCI0_CK TCLK3 MMCI0 Clock VDDIOP0
PA1 MCI0_CDA TIOA3 MMCI0 Command VDDIOP0
PA2 MCI0_DA0 TIOB3 MMCI0 Data0 VDDIOP0
PA3 MCI0_DA1 TCKL4 MMCI0 Data1 VDDIOP0
PA4 MCI0_DA2 TIOA4 MMCI0 Data2 VDDIOP0
PA5 MCI0_DA3 TIOB4 MMCI0 Data3 VDDIOP0
PA6 MCI0_DA4 ETX2 Ethernet MII VDDIOP0
PA7 MCI0_DA5 ETX3 Ethernet MII VDDIOP0
PA8 MCI0_DA6 ERX2 Ethernet MII VDDIOP0
PA9 MCI0_DA7 ERX3 Ethernet MII VDDIOP0
PA10 ETX0 Ethernet RMII Transmit data 0 VDDIOP0
PA11 ETX1 Ethernet RMII Transmit data 1 VDDIOP0
PA12 ERX0 Ethernet RMII Receive data 0 VDDIOP0
PA13 ERX1 Ethernet RMII Receive data 1 VDDIOP0
PA14 ETXEN Ethernet RMII Transmit enable VDDIOP0
PA15 ERXDV Ethernet RMII Receive data valid VDDIOP0
PA16 ERXER Ethernet RMII Receive Error VDDIOP0
PA17 ETXCK Ethernet RMII Transmit Clock VDDIOP0
PA18 EMDC Ethernet RMII Manag.Data Clock VDDIOP0
PA19 EMDIO Ethernet RMII Manag.Data In/Out VDDIOP0
PA20 TWD0 Two Wire Interface Data VDDIOP0
PA21 TWCK0 Two Wire Interface Clock VDDIOP0
PA22 MCI1_CDA SCK3 MMCI1 Command VDDIOP0
PA23 MCI1_DA0 RTS3 MMCI1 Data0 VDDIOP0
PA24 MCI1_DA1 CTS3 MMCI1 Data1 VDDIOP0
PA25 MCI1_DA2 PWM3 MMCI1 Data2 VDDIOP0
PA26 MCI1_DA3 TIOB2 MMCI1 Data3 VDDIOP0
PA27 MCI1_DA4 ETXER R.Select MMCI1 Data4 Ethernet MII VDDIOP0
PA28 MCI1_DA5 ERXCK R.Select MMCI1 Data5 Ethernet MII VDDIOP0
PA29 MCI1_DA6 ECRS R.Select MMCI1 Data6 Ethernet MII VDDIOP0
PA30 MCI1_DA7 ECOL R.Select MMCI1 Data7 Ethernet MII VDDIOP0
PA31 MCI1_CK PCK0 MMCI1_clock VDDIOP0

5-4 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Configuration

5.5.3 Multiplexing on PIO Controller B (PIOB)

Table 5-5. PIO Multiplexing Port B

I/O Peripheral A Peripheral B Function and Comments Power
PB0 SPI0_MISO SPI Slave Out AT45DB642 VDDIOP0
PB1 SPI0_MOSI SPI Slave In AT45DB642 VDDIOP0
PB2 SPI0_SPCK SPI Serial Clock AT45DB642 VDDIOP0
PB3 SPI0_NPCS0 SPI Chip Select AT45DB642 VDDIOP0
PB4 TXD1 USART1 Transmit Data VDDIOP0
PB5 RXD1 USART1 Receive Data VDDIOP0
PB6 TXD2 User Push Button Right click VDDIOP0
PB7 RXD2 User Push Button Left click VDDIOP0
PB8 TXD3 ISI_D8 Image Sensor Data 8 VDDIOP2
PB9 RXD3 ISI_D9 Image Sensor Data 9 VDDIOP2
PB10 TWD1 ISI_D10 Image Sensor Data 10 VDDIOP2
PB11 TWCK1 ISI_D11 Image Sensor Data 11 VDDIOP2
PB12 DRXD DBGU Receive Data VDDIOP0
PB13 DTXD DBGU Transmit Data VDDIOP0
PB14 SPI1_MISO Joystick Left VDDIOP0
PB15 SPI1_MOSI CTS0 Joystick Right VDDIOP0
PB16 SPI1_SPCK SCK0 Joystick Up VDDIOP0
PB17 SPI1_NPCS0 RTS0 Joystick Down VDDIOP0
PB18 RXD0 SPI0_NPCS1 Joystick Push VDDIOP0
PB19 TXD0 SPI0_NPCS2 UsbVbus VDDIOP0
PB20 ISI_D0 Image Sensor Data 0 VDDIOP2
PB21 ISI_D1 Image Sensor Data 1 VDDIOP2
PB22 ISI_D2 Image Sensor Data 2 VDDIOP2
PB23 ISI_D3 Image Sensor Data 3 VDDIOP2
PB24 ISI_D4 Image Sensor Data 4 VDDIOP2
PB25 ISI_D5 Image Sensor Data 5 VDDIOP2
PB26 ISI_D6 Image Sensor Data 6 VDDIOP2
PB27 ISI_D7 Image Sensor Data 7 VDDIOP2
PB28 ISI_PCK Image Sensor Data Clock VDDIOP2
PB29 ISI_VSYNC Image Sensor Vertical Synchro VDDIOP2
PB30 ISI_HSYNC Image Sensor Horizontal Synchro VDDIOP2
PB31 ISI_MCK PCK1 Image Sensor Reference Clock VDDIOP2

AT91SAM9G45-EKES User Guide 5-5

6481B–ATARM–27-Nov-09
Configuration

5.5.4 Multiplexing on PIO Controller C (PIOC)

Table 5-6. PIO Multiplexing Port C

I/O Peripheral A Peripheral B Function and Comments Power
PC0 DQM2 VDDIOM1
PC1 DQM3 VDDIOM1
PC2 A19 Add19 Flash AT49SV322 VDDIOM1
PC3 A20 Add20 Flash AT49SV322 VDDIOM1
PC4 A21/NANDALE ALE Flash AT49SV322 VDDIOM1
PC5 A22/NANDCLE CLE Flash AT49SV322 VDDIOM1
PC6 A23 VDDIOM1
PC7 A24 VDDIOM1
PC8 CFCE1 Ready/Busy NAND Flash VDDIOM1
PC9 CFCE2 RTS2 VDDIOM1
PC10 NCS4/CFCS0 TCLK2 VDDIOM1
PC11 NCS5/CFCS1 CTS2 VDDIOM1
PC12 A25/CFRNW VDDIOM1
PC13 NCS2 VDDIOM1
PC14 NCS3/NANDCS Chip select NAND Flash VDDIOM1
PC15 NWAIT VDDIOM1
PC16 D16 VDDIOM1
PC17 D17 VDDIOM1
PC18 D18 VDDIOM1
PC19 D19 VDDIOM1
PC20 D20 VDDIOM1
PC21 D21 VDDIOM1
PC22 D22 VDDIOM1
PC23 D23 VDDIOM1
PC24 D24 VDDIOM1
PC25 D25 VDDIOM1
PC26 D26 VDDIOM1
PC27 D27 VDDIOM1
PC28 D28 VDDIOM1
PC29 D29 VDDIOM1
PC30 D30 VDDIOM1
PC31 D31 VDDIOM1

5-6 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Configuration

5.5.5 Multiplexing on PIO Controller D (PIOD)

Table 5-7. PIO Multiplexing Port D

I/O Peripheral A Peripheral B Function and Comments Power
PD0 TK0 PWM3 Command LED2 VDDIOP0
PD1 TF0 Output ENA USB Host VDDIOP0
PD2 TD0 Input FLGA USB Host VDDIOP0
PD3 RD0 Output ENB USB Host VDDIOP0
PD4 RK0 Input FLGB USB Host VDDIOP0
PD5 RF0 Int. Ethernet 10/100 MDINTR VDDIOP0
PD6 AC97RX AC97 Receive Signal VDDIOP0
PD7 AC97TX TIOA5 AC97 Transmit Signal VDDIOP0
PD8 AC97FS TIOB5 AC97 Frame Sync Signal VDDIOP0
PD9 AC97CK TCLK5 AC97 Clock Signal VDDIOP0
PD10 TD1 Card Detect MMCI0 MCI0_CD VDDIOP0
PD11 RD1 Card Detect MMCI1 MCI1_CD VDDIOP0
PD12 TK1 PCK0 CTRL1 Image Sensor Interface VDDIOP0
PD13 RK1 CTRL2 Image Sensor Interface VDDIOP0
PD14 TF1 GPIO1 Large LCD (connector) VDDIOP0
PD15 RF1 GPIO2 Large LCD (connector) VDDIOP0
PD16 RTS1 USART1 Request to Send VDDIOP0
PD17 CTS1 USART1 Clear To Send VDDIOP0
PD18 SPI1_NPCS2 IRQ VDDIOP0
PD19 SPI1_NPCS3 FIQ VDDIOP0
PD20 TIOA0 TSAD0 Touch screen X_Right VDDANA
PD21 TIOA1 TSAD1 Touch screen X_Left VDDANA
PD22 TIOA2 TSAD2 Touch screen Y_Up VDDANA
PD23 TCLK0 TSAD3 Touch screen Y_Down VDDANA
PD24 SPI0_NPCS1 PWM0 GPAD4 General purpose A/D4 VDDANA
PD25 SPI0_NPCS2 PWM1 GPAD5 General purpose A/D5 VDDANA
PD26 PCK0 PWM2 GPAD6 General purpose A/D6 VDDIOP0
PD27 PCK1 SPI0_NPCS3 GPAD7 General purpose A/D7 VDDIOP0
PD28 TSADTRG SPI1_NPCS1 USB Plug-ID IDUSB VDDIOP0
PD29 TCLK1 SCK1 MCI1_WP VDDIOP0
PD30 TIOB0 SCK2 Command Power Led VDDIOP0
PD31 TIOB1 PWM1 Command LED1 VDDIOP0

AT91SAM9G45-EKES User Guide 5-7

6481B–ATARM–27-Nov-09
Configuration

5.5.6 Multiplexing on PIO Controller E (PIOE)

Table 5-8. PIO Multiplexing Port E

I/O Peripheral A Peripheral B Function and Comments Power
PE0 LCDPWR PCK0 LCD Panel Pow.Enab.Ctrl VDDIOP1
PE1 LCDMOD LCD Modulation Signal VDDIOP1
PE2 LCDCC LCD Contrast Control VDDIOP1
PE3 LCDVSYNC LCD Vertical Synch. VDDIOP1
PE4 LCDHSYNC LCD Horizontal Synch. VDDIOP1
PE5 LCDDOTCK LCD Dot Clock VDDIOP1
PE6 LCDDEN LCD Data Enable VDDIOP1
PE7 LCDD0 LCDD2 LCD-Red0 VDDIOP1
PE8 LCDD1 LCDD3 LCD-Red1 VDDIOP1
PE9 LCDD2 LCDD4 LCD-Red2 VDDIOP1
PE10 LCDD3 LCDD5 LCD-Red3 VDDIOP1
PE11 LCDD4 LCDD6 LCD-Red4 VDDIOP1
PE12 LCDD5 LCDD7 LCD-Red5 VDDIOP1
PE13 LCDD6 LCDD10 LCD-Red6 VDDIOP1
PE14 LCDD7 LCDD11 LCD-Red7 VDDIOP1
PE15 LCDD8 LCDD12 LCD-Green0 VDDIOP1
PE16 LCDD9 LCDD13 LCD-Green1 VDDIOP1
PE17 LCDD10 LCDD14 LCD-Green2 VDDIOP1
PE18 LCDD11 LCDD15 LCD-Green3 VDDIOP1
PE19 LCDD12 LCDD18 LCD-Green4 VDDIOP1
PE20 LCDD13 LCDD19 LCD-Green5 VDDIOP1
PE21 LCDD14 LCDD20 LCD-Green6 VDDIOP1
PE22 LCDD15 LCDD21 LCD-Green7 VDDIOP1
PE23 LCDD16 LCDD22 LCD-Blue0 VDDIOP1
PE24 LCDD17 LCDD23 LCD-Blue1 VDDIOP1
PE25 LCDD18 LCD-Blue2 VDDIOP1
PE26 LCDD19 LCD-Blue3 VDDIOP1
PE27 LCDD20 LCD-Blue4 VDDIOP1
PE28 LCDD21 LCD-Blue5 VDDIOP1
PE29 LCDD22 LCD-Blue6 VDDIOP1
PE30 LCDD23 LCD-Blue7 VDDIOP1
PE31 PWM2 PCK1 AC97 External Clock VDDIOP1

5-8 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Section 6
Connectors

6.1 Power Supply

The AT91SAMG45-EKES evaluation board can be powered from a DC 5V power supply via the external
power supply jack (J2) shown in Figure 10 1. The positive pole must be on J2 center pin.

Figure 6-1. Power Supply Connector J2

Table 6-1. Power Supply Connector J2 Signal Description

Pin Mnemonic Signal description
1 Center +5 VCC
2 Gnd

6.2 RS232 Connector with RTS/CTS Handshake Support

Connector J11 is the COM1 connector.

Figure 6-2. RS232 COM1 Connector J11

AT91SAM9G45-EKES User Guide 6-1

6481B–ATARM–27-Nov-09
Connectors

Table 6-2. Serial COM1 Connector J11 Signal Descriptions

Pin Mnemonic Signal description
1, 4, 6, 9 NC NO CONNECTION
2 TXD TRANSMITTED DATA RS232 serial data output signal
3 RXD RECEIVED DATA RS232 serial data input signal
5 GND GROUND
7 RTS READY TO SEND Active-positive RS232 input signal
8 CTS CLEAR TO SEND Active-positive RS232 output signal

6.3 DBGU
Connector J10 is the DBGU connector.

Figure 6-3. RS232 DBGU Connector J10

Table 6-3. RS232 DBGU Connector J10 Signal Descriptions

Pin Mnemonic Signal description
1, 4, 6, 7, 8, 9 NC NO CONNECTION
2 TXD TRANSMITTED DATA RS232 serial data output signal
3 RXD RECEIVED DATA RS232 serial data input signal
5 GND GROUND

6-2 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Connectors

6.4 Ethernet
Connector J15 is the RJ-45 Ethernet Connector.

Figure 6-4. Ethernet RJ45 Connector J15

Table 6-4. Ethernet RJ45 Connector J15 Signal Descriptions

Pin Mnemonic Pin Mnemonic
1 TxData+ DIFFERENTIAL OUTPUT PLUS 2 Txdata- DIFFERENTIAL OUTPUT MINUS
3 RxData+ DIFFERENTIAL INPUT PLUS 4 Shield
5 Shield 6 RxData- DIFFERENTIAL INPUT MINUS
7 Shield 8 Shield

6.5 USB Host

Connector J12 is the USB Host connector.

Figure 6-5. USB Host type A connector J12

Table 6-5. USB Host Type A Connector J12 Signal Descriptions

Pin Mnemonic Signal description
1 Vbus 5v power
2 DM Data minus
3 DP Data plus
4 Gnd Ground
5 Shield Shield

AT91SAM9G45-EKES User Guide 6-3

6481B–ATARM–27-Nov-09
Connectors

6.6 USB Host/Device

Connector J14 is the USB Host/Device connector.

Figure 6-6. USB Host/Device Micro AB connector J14

Table 6-6. USB Host/Device MicroAB Connector J14 Signal Descriptions

Pin Mnemonic Signal description
1 Vbus 5v power
2 DM Data minus
3 DP Data plus
4 ID On the Go Identification
5 Gnd Ground

6.7 JTAG Debugging Connector

Connector J13 is the JTAG/ICE connector.
A SAM-ICE connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm
male) that mates with IDC sockets mounted on a ribbon cable.

Figure 6-7. JTAG/ICE Connector J13

6-4 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Connectors

Table 6-7. JTAG/ICE Connector J13 Signal Descriptions

Pin Mnemonic Description
This is the target reference voltage. It is used to check if the target
has power, to create the logic-level reference for the input
1 VTref. 3.3V power comparators, and to control the output logic levels to the target. It is
normally fed from VDD on the target board and must not have a
series resistor.
This pin is not connected in SAM-ICE. It is reserved for compatibility
2 Vsupply. 3.3V power with other equipment. Connect to VDD or leave open in target
system.
JTAG Reset. Output from SAM-ICE to the Reset signal on the target
nTRST TARGET RESET - Active-low output JTAG port. Typically connected to nTRST on the target CPU. This pin
3
signal that resets the target is normally pulled HIGH on the target to avoid unintentional resets
when there is no connection.
4 GND Common ground
JTAG data input of target CPU. It is recommended that this pin is
TDI TEST DATA INPUT - Serial data output line,
5 pulled to a defined state on the target board. Typically connected to
sampled on the rising edge of the TCK signal.
TDI on target CPU.
6 GND Common ground
JTAG mode set input of target CPU. This pin should be pulled up on
the target. Typically connected to TMS on target CPU. Output signal
7 TMS TEST MODE SELECT
that sequences the target's JTAG state machine, sampled on the
rising edge of the TCK signal.
8 GND Common ground
TCK TEST CLOCK - Output timing signal, for JTAG clock signal to target CPU. It is recommended that this pin is
9 synchronizing test logic and control register pulled to a defined state on the target board. Typically connected to
access. TCK on target CPU.
10 GND Common ground
Some targets must synchronize the JTAG inputs to internal clocks. To
assist in meeting this requirement, a returned and retimed TCK can
RTCK - Input Return test clock signal from the be used to dynamically control the TCK rate. SAM-ICE supports
11
target. adaptive clocking which waits for TCK changes to be echoed
correctly before making further changes. Connect to RTCK if
available, otherwise to GND
12 GND Common ground
TDO JTAG TEST DATA OUTPUT - Serial data JTAG data output from target CPU. Typically connected to TDO on
13
input from the target. target CPU.
14 GND Common ground
15 nSRST RESET Active-low reset signal. Target CPU reset signal
16 GND Common ground
17 RFU This pin is not connected in SAM-ICE.
18 GND Common ground
19 RFU This pin is not connected in SAM-ICE
20 GND Common ground

AT91SAM9G45-EKES User Guide 6-5

6481B–ATARM–27-Nov-09
Connectors

6.8 SD/MMC- MCI0

Connector J6 is the SD/MMC connector.

Figure 6-8. SD/MMC0 Connector J6

Table 6-8. SD/MMC0 Connector J6 Signal Descriptions

Pin Mnemonic Pin Mnemonic
1 RSV/DAT3 2 CDA
3 GND 4 VCC
5 CLK 6 GND
7 DAT0 8 DAT1
9 DAT2 10 Card Detect
11 GND 12

6-6 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Connectors

6.9 SD/MMC- MCI1

Connector J5 is the SD/MMC connector.

Figure 6-9. SD/MMC1 Connector J5

Table 6-9. SD/MMC1 Connector J5 Signal Descriptions

Pin Mnemonic Pin Mnemonic
1 RSV/DAT3 2 CMD
3 GND 4 VCC
5 CLK 6
7 DAT0 8 DAT1
9 DAT2 10 DAT3
11 DAT4 12 DAT5
13 DAT6 14 DAT7

6.10 AC97
„ Connector J7 is the Headphone connector.
„ Connector J8 is the Line In connector.
„ Connector J9 is the Line In connector.
„ Connector JP15 is the Speaker Output connector

Figure 6-10. Audio Connector J7, J8, J9

Table 6-10. J7, J8, J9 Signal Description

Pin Mnemonic
Central pin Signal

AT91SAM9G45-EKES User Guide 6-7

6481B–ATARM–27-Nov-09
Connectors

Table 6-11. Speaker JP15 Signal Descriptions

Pin Mnemonic
1 Speaker bridge output A
2 Speaker bridge output B

6.11 Image Sensor - ISI

Connector J17 is the ISI connector.

Figure 6-11. ISI Connector J17

Table 6-12. ISI Connector J17 Signal Descriptions

Pin Mnemonic Pin Mnemonic
1 VCC 3v3 2 Gnd
3 VCC 3v3 4 Gnd
5 Ctrl1 6 Ctrl2
7 SCL 8 SDA
9 Gnd 10 ISI_MCK
11 Gnd 12 ISI_VSYNC
13 Gnd 14 ISI_HSYNC
15 Gnd 16 ISI_PCK
17 Gnd 18 ISI_Data0
19 ISI_Data1 20 ISI_Data2
21 ISI_Data3 22 ISI_Data4
23 ISI_Data5 24 ISI_Data6
25 ISI_Data7 26 ISI_Data8
27 ISI_Data9 28 ISI_Data10
29 ISI_Data11 30 Gnd

6-8 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Connectors

6.12 Video
Connector J20 is the Video connector

Figure 6-12. Video Connector J20

Table 6-13. Video Connector J20 Signal Description

Pin Mnemonic Signal description
1 Center Composite video signal output

6.13 Display Devices

6.13.1 LG TFT LCD LG/PHILIPS

Connector J24 is the TFT-LCD connector.

Figure 6-13. TFT LCD Connector J24

Table 6-14. LG TFT LCD Connector J24 Signal Descriptions

Pin Mnemonic Pin Mnemonic
1 GND 2 GND
3 VDD 3V3 4 VDD 3V3
5 R0 6 R1
7 R2 8 R3
9 R4 10 R5

AT91SAM9G45-EKES User Guide 6-9

6481B–ATARM–27-Nov-09
Connectors

Table 6-14. LG TFT LCD Connector J24 Signal Descriptions

Pin Mnemonic Pin Mnemonic
11 R6 12 R7
13 G0 14 G1
15 G2 16 G3
17 G4 18 G5
19 G6 20 G7
21 B0 14 B1
23 B2 16 B3
25 B4 18 B5
27 B6 20 B7
29 GND 30 DCLK
31 DISPON 32 NO CONNECT
33 NO CONNECT 34 LCDEN
35 VDD PWR SEL 36 GND
37 X1 38 Y1
39 X2 40 Y2
41 GND 42 VLED-
43 VLED+ 44 NO CONNECT
45 NO CONNECT

6.14 Large LCD Extension

Connectors J23 and J18 are for an optional large LCD extension (not populated).

Table 6-15. Connector J23 Signal Description for a Large LCD Extension
Pin Mnemonic Pin Mnemonic
1 PE8 RED Data Signal 2 PE7 RED Data Signal (LSB)
3 PE10 RED Data Signal 4 PE9 RED Data Signal
5 PE12 RED Data Signal 6 PE11 RED Data Signal
7 PE14 RED Data Signal (MSB) 8 PE13 RED Data Signal
9 PE16 GREEN Data Signal 10 PE15 GREEN Data Signal (LSB
11 PE18 GREEN Data Signal 12 PE17 GREEN Data Signal
13 PE20 GREEN Data Signal 14 PE19 GREEN Data Signal
15 PE22 GREEN Data Signal (MSB) 16 PE21 GREEN Data Signal
17 PE24 BLUE Data Signal 18 PE23 BLUE Data Signal (LSB)
19 PE26 BLUE Data Signal 20 PE25 BLUE Data Signal
21 PE28 BLUE Data Signal 22 PE27 BLUE Data Signal
23 PE30 BLUE Data Signal (MSB) 24 PE29 BLUE Data Signal

6-10 AT91SAM9G45-EKES User Guide

6481B–ATARM–27-Nov-09
 Connectors

Table 6-15. Connector J23 Signal Description for a Large LCD Extension
Pin Mnemonic Pin Mnemonic
25 PE4 LCDHSYNC 26 PE3 LCDVSYNC
27 PE5 LCDDOTCK 28 GND (0V)
29 GND (0V) 30 NC
31 PE6 LCDDEN 32 PE2 LCDCC
33 PE0 DISPON 34 PE1 LCDMOD
35 PD14 GPIO1 36 PD15 GPIO2
37 GND (0V) 38 GND (0V)
39 VCC +3V3 power source 40 NC

Table 6-16. Connector J18 Signal Description for a Large LCD Extension
Pin Mnemonic Pin Mnemonic
1 XM AD1XM 2 XP AD0XP
3 YM AD3YM 4 YP AD2YP
5 GND (0V) 6 GND (0V)
7 PD25 PD25 8 PD24 PD24
9 PD27 PD27 10 PD26 PD26
11 PD19 PD19 12 PD18 PD18
13 GND (0V) 14 GND (0V)
15 GND (0V) 16 +5V
17 GND (0V) 18 GND (0V)
19 VCC +3V3 power source 20 VCC +3V3 power source

AT91SAM9G45-EKES User Guide 6-11

6481B–ATARM–27-Nov-09
 Section 7
Schematics

7.1 Schematics
This section contains the following schematics:
„ Top Level view, block architecture of the design
„ Power Supply
„ SAM Processor
„ Bus impedance adaptor
„ Main memory
„ EBI memory
„ MCI & TWI
„ Audio AC97
„ Serial interfaces
„ Ethernet
„ LCD
„ Video interfaces and LCD extension

AT91SAM9G45-EKES User Guide 7-1

6481B–ATARM–27-Nov-09
 8 7 6 5 4 3 2 1

5V
POWER SUPPLY 3V3

POWER 1V8

INTERFACE

128MB
USER'S

DDR2
EB0 DRR2 INTERFACE

EBI0
1V EB0 DRR2 INTERFACE
D PIO D

Sheet 2
Sheet 5
DBGU

RS232
RES.ARRAYS
COM1 EBI0_EBI1 ADAPTER

128MB
DDR2
EB1 DRR2 INTERFACE
HOST
EB1 DATA INTERFACE
USB

PIO
HOST ATMEL

EBI1
DEVICE
ARM9 Processor

FLASH
EB1 FASH INTERFACE
EB1 ADRESSE INTERFACE
ICE PIO A,...E SAM9M10 or SAM9G45
HE 10

INTERFACE (LFBGA324)

FLASH
NAND
EB1 BUS INTERFACE EB1 NANDFASH INTERFACE
C
Sheet 9 C

10/100 FAST
PIO Sheet 4
RJ 45

ETHERNET Sheet 6

Sheet 10

MMC SD
PIO A,...E CARD
HE 14

PIO

SDIO
READER
CONNECTOR

LCD INTERFACE
CARD

MMC SD
4.3" READER

SDIO
480x272
TFT
PIO

MIC
TOUCH SCREEN SERIAL
Sheet 3 EEPROM
AUDIO
ISI

IN
HE 15

B B
CAMERA
SERIAL

OUT
INTERFACE DATA
Sheet 8 FLASH
TV
RCA

INTERFACE Sheet 7
Sheet 11 12
PIO MUXING
PIOA USAGE PIOA USAGE PIOB USAGE PIOB USAGE PIOC USAGE PIOC USAGE PIOD PIOD PIOE PIOE
PA0 MCI0_CK PA16 RX_ER PB0 SPI0_MISO PB16 BP3_UP PC0 NOT USED PC16 NOT USED PD0 USER_LED_D6 PD16 RTS1 PE0 LCDPW R PE16 G1
PA1 MCI0_CDA PA17 TX_CLK PB1 SPI0_MOSI PB17 BP3_DOW N PC1 NOT USED PC17 NOT USED PD1 ENA PD17 CTS1 PE1 LCDMOD PE17 G2
PA2 MCI0_DA0 PA18 MDC PB2 SPI0_SPCK PB18 BP3_PUSH PC2 A19 PC18 NOT USED PD2 FLGA PD18 J18_12 PE2 LCDCC PE18 G3
PA3 MCI0_DA1 PA19 MDIO PB3 SPI0_NPCS0 PB19 VBUS PC3 A20 PC19 NOT USED PD3 ENB PD19 J18_11 PE3 VSYNC PE19 G4
PA4 (MCI0_DA2) PA20 TW DO PB4 TXD1 PB20 ISI_D0 PC4 NANDALE / A21 PC20 NOT USED PD4 FLGB PD20 AD0Xp PE4 HSYNC PE20 G5
PA5 (MCI0_DA3) PA21 TW CK0 PB5 RXD1 PB21 ISI_D1 PC5 NANDCLE PC21 NOT USED PD5 MDINTR PD21 AD1Xm PE5 LCDDOTCK PE21 G6
PA6 TXD2 PA22 MCI1_CDA PB6 BP5_LEFT PB22 ISI_D2 PC6 NOT USED PC22 NOT USED PD6 AC97RX PD22 AD2Yp PE6 LCDDEN PE22 G7
PA7 TXD3 PA23 MCI1_DA0 PB7 BP4_RIGHT PB23 ISI_D3 PC7 NOT USED PC23 NOT USED PD7 AC97TX PD23 AD3Ym PE7 R0 PE23 B0
PA8 RXD2 PA24 MCI1_DA1 PB8 ISI_D8 PB24 ISI_D4 PC8 RDY/BSY PC24 NOT USED PD8 AC97FS PD24 J18_8 PE8 R1 PE24 B1
PA9 RXD3 PA25 MCI1_DA2 PB9 ISI_D9 PB25 ISI_D5 PC9 NOT USED PC25 NOT USED PD9 AC97CK PD25 J18_7 PE9 R2 PE25 B2
PA10 TXD0 PA26 MCI1_DA3 PB10 ISI_D10 PB26 ISI_D6 PC10 NOT USED PC26 NOT USED PD10 MCI0_CD PD26 J18_10 PE10 R3 PE26 B3
PA11 TXD1 PA27 MCI1_DA4 / TX_ER PB11 ISI_D11 PB27 ISI_D7 PC11 NOT USED PC27 NOT USED PD11 (MCI1_CD) PD27 J18_9 PE11 R4 PE27 B4
PA12 RXD0 PA28 MCI1_DA5 / RX_CLK PB12 DRXD PB28 ISI_PCK PC12 NOT USED PC28 NOT USED PD12 CTRL1 PD28 IDUSB PE12 R5 PE28 B5
PA13 RXD1 PA29 MCI1_DA6 / CRS PB13 DTXD PB29 ISI_VSYNC PC13 NOT USED PC29 NOT USED PD13 CTRL2 PD29 (MCI1_W P) PE13 R6 PE29 B6
PA14 TX_EN PA30 MCI1_DA7 / COL PB14 BP3_LEFT PB30 ISI_HSYNC PC14 NCS3 PC30 NOT USED PD14 GPIO1 PD30 POW ER LED PE14 R7 PE30 B7
A PA15 RX_DV PA31 MCI1_CK PB15 BP3_RIGHT PB31 ISI_MCK PC15 NOT USED PC31 NOT USED PD15 GPIO2 PD31 USER_LED_D7 PE15 G0 PE31 EXT_CLK A

E LN 03-sep-09
D PP 22-jun-09
C PP 02-DEC-08
B PP 29-JUL-08
NOTE A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
REV MODIF. DES. DATE VER. DATE
"DNP" means the component is not populated by default AT91SAM9M10-EKES
AT91SAM9G45-EKES
SCALE
1/1 REV. SHEET
1
TOP LEVEL E 12
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

3V3 J1-1
C1 1 2 VDDUTMII {3}
D1
180nF L1
1 2 VDDANA {3}
10uH 150mA
J2 3V3 R1
L2 BAT20J

2
5V MN1 1R
1 3 6 C3

BOOST
2 C2 4 VIN1 SW 1 5 100nF
2.2uF VIN2 SW 2 2.2uH C4 C5
D2 11 12 10uF 4.7uF
SHDN FB
3

5V LT1765-3.3
R2 7
100K 10 NC1 D3 L3

SYNC

GND1
GND2
GND3
GND4
GND5
D
2.1 MM SOCKET 15 NC2 D
STPS2L30A

VC
NC3 VDDOSC {3}
10uH 150mA
R3

14

1
8
17
9
16

13
C6 1R
2.2nF C7
100nF
C8
4.7uF

1 3
JP1
VDDIOP0 {3}

2
FORCE 1 3
POWER JP2
C9 VDDIOP1 {3}
ON D4

2
180nF 1 3
JP4
1 2 JP3
VDDIOP2 {3,12}

2
5V 1V8
L4 BAT20J

2
MN2 VDDISI {3,12}
Q1
3 6 1V VDDUTMIC J1-2

BOOST
C10 4 VIN1 SW 1 5 MN3 3 4
VIN2 SW 2 VDDUTMIC {3}

1
1 6 2.2uF 2.2uH C12
11 12 10uF

VDD

OUT
C11 SHDN LT1765-1.8 FB C13 C14

GND
15pF 7 2.2uF 2.2uF
R4 10K 2 5 10 NC1 D5

SYNC

GND1
GND2
GND3
GND4
GND5
{3} SHDN NC2
C 15 STPS2L30A R1100D101C C

VC
NC3

3
5V

14

1
8
17
9
16

13
3 4 C15 L5 J1-4
2.2nF 7 8 VDDPLLUTMI {3}
10uH 150mA
Si1563EDH R7
1R
C20
100nF
C21
4.7uF
R5
10K C16 C17
1uF 1uF L6
VDDPLLA {3}
8 6 3 4 10uH 150mA
R9
3V3 1V 1R
C1M C1P C2M C2P
C23
5 7 100nF
VIN VOUT C24
C18 C19 R6 4.7uF
2.2uF 10pF 68K
TPS60500
10
FB C22
22uF
1 2 R8 1V
EN GND PG 220K J1-3
B B
MN4 5 6 VDDCORE {3}
R126 9
10K

1V8

1 3
JP5
USER INTERFACE VDDIOM0 {3}

2
3V3 1 3
D6 R10 470R JP6
3V3
PD0 {3} VDDIOM1 {3}

2
3V3 GREEN VDDBU
D7 R11 470R
PD31 {3}
GREEN R13 R14
100K 1K
R12 BP1 ADHESIVE FEET J3 3V3
470R
1 3
NRST NRST {3,7,8,9,10,12} Z1 Z2
JP7
PB15 BP2 C25
11.1 11.1

2
PB16 100nF
D8
RED R15 WAKE UP WAKE UP {3}
VDDBU VDDBU {3}
Z3 Z4 Z5
470K BP4
11.1 11.1 11.1
BP3
A
3 1 4 UP RIGHT CLICK C220
PB7 {3} A

PB14 LEFT 2 5 RIGHT R142

PB18 PUSH 3 6 DOWN
10nF
100R GND TEST POINT
E LN 03-sep-09
1 PD30 {3} JOYSTICK BP5 D PP 22-jun-09
Q2 PB17 TP1 TP2 TP3 TP4 C PP 02-DEC-08
IRLML2402
2 C215 C216 C217 C218 C219 LEFT CLICK C221
PB6 {3} B
A INIT EDIT
PP
PP
29-JUL-08
26-MAY-08 XXX XX-XXX-XX
R141 R143 REV MODIF. DES. DATE VER. DATE
10nF 10nF 10nF 100R 10nF 10nF 100R AT91SAM9M10-EKES
POWER LED {3} PB[14..18]
10nF
AT91SAM9G45-EKES
SCALE
1/1 REV. SHEET
2
POW ER SUPPLY E 12
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
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{7,10,12} PA[0..31] PB[0..31] {2,7,9,12} {8,11,12} PE[0..31]

MN5A MN5B MN5E
PA0 L1 T4 PB0 PE0 G4
PA1 M1 PA0/MCI0_CK/TCLK3 PB0/SPI0_MISO V2 PB1 PE1 F4 PE0/LCDPW R/PCK0
PA2 L5 PA1/MCI0_CDA/TIOA3 PB1/SPI0_MOSI V3 PB2 MN5C MN5D PE2 G5 PE1/LCDMOD
PA2/MCI0_DA0/TIOB3 PB2/SPI0_SPCK PD[0..31] {2,7,8,9,10,11,12} PE2/LCDCC
PA3 N1 U4 PB3 A8 R7 PD0 PE3 F5
PA3/MCI0_DA1/TCKL4 PB3/SPI0_NPCS0 {4,6} PC[2..5] PC0/DQM2 PD0/TK0/PW M3 PE3/LCDVSYNC
PA4 L6 R5 PB4 E9 T7 PD1 PE4 G7
PA5 M2 PA4/MCI0_DA2/TIOA4 PB4/TXD1 V4 PB5 PC2 B8 PC1/DQM3 PD1/TF0 L8 PD2 PE5 H5 PE4/LCDHSYNC
PA6 M3 PA5/MCI0_DA3/TIOB4 PB5/RXD1 T5 PB6 PC3 C8 PC2/A19 PD2/TD0 V6 PD3 PE6 G3 PE5/LCDDOTCK
PA7 M4 PA6/MCI0_DA4/ETX2 PB6/TXD2 U5 PB7 PC4 F9 PC3/A20 PD3/RD0 M8 PD4 PE7 H6 PE6/LCDDEN
PA8 L7 PA7/MCI0_DA5/ETX3 PB7/RXD2 T12 PB8 PC5 A7 PC4/A21/NANDALE PD4/RK0 V7 PD5 PE8 G6 PE7/LCDD0/LCDD2
PA9 N2 PA8/MCI0_DA6/ERX2 PB8/TXD3/ISI_D8 N11 PB9 D8 PC5/A22/NANDCLE PD5/RF0 N8 PD6 PE9 H7 PE8/LCDD1/LCDD3
PA10 M5 PA9/MCI0_DA7/ERX3 PB9/RXD3/ISI_D9 U13 PB10 A6 PC6/A23 PD6/AC97RX U7 PD7 PE10 H8 PE9/LCDD2/LCDD4
PA11 P1 PA10/ETX0 PB10/TW D1/ISI_D10 M11 PB11 PC8 E8 PC7/A24 PD7/AC97TX/TIOA5 P8 PD8 PE11 G8 PE10/LCDD3/LCDD5
D PA11/ETX1 PB11/TW CK1/ISI_D11 {6} PC8 PC8/CFCE1 PD8/AC97FS/TIOB5 PE11/LCDD4/LCDD6 D
PA12 N3 P6 PB12 C7 R8 PD9 PE12 J5
PA13 P2 PA12/ERX0 PB12/DRXD R6 PB13 B6 PC9/CFCE2/RTS2 PD9/97CK/TCLK5 U8 PD10 PE13 H4 PE12/LCDD5/LCDD7
PA14 M6 PA13/ERX1 PB13/DTXD M7 PB14 B7 PC10/NCS4/CFCS0/TCLK2 PD10/TD1 T8 PD11 PE14 J3 PE13/LCDD6/LCDD10
PA15 N4 PA14/ETXEN PB14/SPI1_MISO V5 PB15 A5 PC11/NCS5/CFCS1/CTS2 PD11/RD1 V8 PD12 PE15 J4 PE14/LCDD7/LCDD11
PA16 N5 PA15/ERXDV PB15/SPI1_MOSI/CTS0 T6 PB16 D7 PC12/A25/CFRNW PD12/TK1/PCK0 L9 PD13 PE16 J2 PE15/LCDD8/LCDD12
PA17 N6 PA16/ERXER PB16/SPI1_SPCK/SCK0 U6 PB17 PC14 F8 PC13/NCS2 PD13/RK1 U9 PD14 PE17 J6 PE16/LCDD9/LCDD13
PA17/ETXCK PB17/SPI1_NPCS0/RTS0 {6} PC14 PC14/NCS3/NANDCS PD14/TF1 PE17/LCDD10/LCDD14
PA18 R1 N7 PB18 C6 M9 PD15 PE18 J7
PA19 P3 PA18/EMDC PB18/RXD0/SPI0_NPCS1 P7 PB19 E7 PC15/NW AIT PD15/RF1 N9 PD16 PE19 J1 PE18/LCDD11/LCDD15
PA20 R2 PA19/EMDIO PB19/TXD0/SPI0_NPCS2 P12 PB20 B5 PC16/D16 PD16/RTS1 V9 PD17 PE20 J8 PE19/LCDD12/LCDD18
PA21 P4 PA20/TW D0 PB20/ISI_D0 T15 PB21 D6 PC17/D17 PD17/CTS1 R9 PD18 PE21 K1 PE20/LCDD13/LCDD19
PA22 T1 PA21/TW CK0 PB21/ISI_D1 R12 PB22 F7 PC18/D18 PD18/SPI1_NPCS2/IRQ T9 PD19 PE22 K4 PE21/LCDD14/LCDD20
PA23 P5 PA22/MCI1_CDA/SCK3 PB22/ISI_D2 T16 PB23 A4 PC19/D19 PD19/SPI0_NPCS3/FIQ D2 PD20 PE23 K2 PE22/LCDD15/LCDD21
PA24 R3 PA23/MCI1_DA0/RTS3 PB23/ISI_D3 N12 PB24 C5 PC20/D20 PD20/TIOA0 E1 PD21 PE24 K5 PE23/LCDD16/LCDD22
PA25 T2 PA24/MCI1_DA1/CTS3 PB24/ISI_D4 M12 PB25 B4 PC21/D21 PD21/TIOA1 F1 PD22 PE25 K6 PE24/LCDD17/LCDD23
PA26 T3 PA25/MCI1_DA2/PW M3 PB25/ISI_D5 U14 PB26 E6 PC22/D22 PD22/TIOA2 G2 PD23 PE26 K3 PE25/LCDD18
PA27 U1 PA26/MCI1_DA3/TIOB2 PB26/ISI_D6 M13 PB27 D5 PC23/D23 PD23/TCLK0 F2 PD24 PE27 K7 PE26/LCDD19
PA28 U3 PA27/MCI1_DA4/ETXER PB27/ISI_D7 N13 PB28 A3 PC24/D24 PD24/SPI0_NPCS1/PW M0 G1 PD25 PE28 K8 PE27/LCDD20
PA29 U2 PA28/MCI1_DA5/ERXCK PB28/ISI_D8 R13 PB29 C4 PC25/D25 PD25/SPI0_NPCS2/PW M1 H1 PD26 PE29 L3 PE28/LCDD21
PA30 R4 PA29/MCI1_DA6/ECRS PB29/ISI_VSYNC T13 PB30 A1 PC26/D26 PD26/PCK0/PW M2 H2 PD27 PE30 L2 PE29/LCDD22
PA31 V1 PA30/MCI1_DA7/ECOL PB30/ISI_HSYNC P13 PB31 A2 PC27/D27 PD27/PCK1/SPI0_NPCS3 P9 PD28 PE31 L4 PE30/LCDD23
PA31/MCI1_CK/PCK0 PB31/ISI_MCK/PCK1 B2 PC28/D28 PD28/TSADTRG/SPI1_NPCS1 L10 PD29 PE31/PW M2/PCK1
B3 PC29/D29 PD29/TCLK1/SCK1 T10 PD30
B1 PC30/D30 PD30/TIOB0/SCK2 L11 PD31
PC31/D31 PD31/TIOB1/PW M1
EBI1_D[0..15] {4}
MN5G MN5F
{4} EBI0_D[0..15]
A17 EBI1_D0 EBI1_A[1..18] {4}
EBI0_D0 R16 EBI1_D0 D15 EBI1_D1
EBI0_D1 R15 EBI0_DDR_D0 EBI1_D1 C15 EBI1_D2
EBI0_D2 T14 EBI0_DDR_D1 EBI1_D2 B16 EBI1_D3
C EBI0_D3 P15 EBI0_DDR_D2 EBI1_D3 B15 EBI1_D4 C
EBI0_D4 P16 EBI0_DDR_D3 EBI1_D4 D14 EBI1_D5
EBI0_DDR_D4 EBI1_D5 VDDBU {2}
EBI0_D5 P17 C14 EBI1_D6
EBI0_D6 R14 EBI0_DDR_D5 EBI1_D6 A15 EBI1_D7
EBI0_D7 P14 EBI0_DDR_D6 EBI1_D7 B14 EBI1_D8 MN5H
EBI0_D8 N15 EBI0_DDR_D7 EBI1_D8 D13 EBI1_D9 R16 39R T18 D4
EBI0_DDR_D8 EBI1_D9 HFSDPA VDDBU C26 100nF
EBI0_D9 N16 C13 EBI1_D10 R18 D3
EBI0_D10 P18 EBI0_DDR_D9 EBI1_D10 E13 EBI1_D11 R17 39R HFSDMA GNDBU
EBI0_DDR_D10 EBI1_D11 VDDPLLUTMI {2}
EBI0_D11 N17 B13 EBI1_D12 T17 V13 C27 100nF
EBI0_DDR_D11 EBI1_D12 {9} HDPA HHSDPA VDDPLLUTMI
EBI0_D12 N18 E12 EBI1_D13 R17 U18 C28 100nF
EBI0_DDR_D12 EBI1_D13 {9} HDMA HHSDMA VDDUTMIC
EBI0_D13 N14 D12 EBI1_D14 VDDUTMIC {2}
EBI0_D14 M15 EBI0_DDR_D13 EBI1_D14 C12 EBI1_D15 R18 39R V15 U17
EBI0_D15 M16 EBI0_DDR_D14 EBI1_D15 TP6 V16 DFSDP/HFSDPB GNDUTMI
EBI0_DDR_D15 DFSDM/HFSDMB VDDUTMII {2}
F13 EBI1_A0 EBI1_A0 R19 39R V17
{4} EBI0_A[0..13] EBI1_NBS0/A0 VDDUTMII
F14 EBI1_A1 TESTPOINT U15 C29 100nF
EBI1_NBS2/NW R2/A1 {9} HDPB DHSDP/HHSDPB
EBI0_A0 M17 F18 EBI1_A2 U16 VDDIOP0 {2}
EBI0_DDR_A0 EBI1_A2 {9} HDMB DHSDM/HHSDMB
EBI0_A1 L14 F15 EBI1_A3 K9 C30 100nF
EBI0_A2 M18 EBI0_DDR_A1 EBI1_A3 E14 EBI1_A4 U11 VDDIOP0 K10
EBI0_DDR_A2 EBI1_A4 {2} VDDOSC VDDOSC VDDIOP0 C31 100nF
EBI0_A3 L15 F17 EBI1_A5 U12 VDDIOP1 {2}
EBI0_A4 L16 EBI0_DDR_A3 EBI1_A5 F16 EBI1_A6 C32 GNDOSC H3
EBI0_DDR_A4 EBI1_A6 VDDIOP1 C33 100nF
EBI0_A5 L18 E17 EBI1_A7 100nF VDDIOP2 {2,12}
EBI0_A6 L17 EBI0_DDR_A5 EBI1_A7 E15 EBI1_A8 C34 V12 V14
EBI0_DDR_A6 EBI1_A8 XIN VDDIOP2 C35 100nF

1
EBI0_A7 K14 E16 EBI1_A9 18pF VDDCORE {2}
EBI0_A8 K15 EBI0_DDR_A7 EBI1_A9 D18 EBI1_A10 Y1 E18
EBI0_DDR_A8 EBI1_A10 VDDCORE C36 100nF
EBI0_A9 K16 D17 EBI1_A11 C38 12 MHz G12 C37
EBI0_DDR_A9 EBI1_A11 VDDCORE 100nF
EBI0_A10 K18 C18 EBI1_A12 18pF V11 G13 C39
EBI0_DDR_A10 EBI1_A12 XOUT VDDCORE 100nF

2
EBI0_A11 K17 B18 EBI1_A13 H11 C40
EBI0_DDR_A11 EBI1_A13 VDDCORE 100nF
EBI0_A12 J14 A18 EBI1_A14 C41 C1 VDDIOM0 {2}
EBI0_DDR_A12 EBI1_A14 XIN32

1
EBI0_A13 J15 B17 EBI1_A15 15pF K13 C42
EBI0_DDR_A13 EBI1_A15 VDDIOM0 100nF
B C10 EBI1_A16 Y2 L12 C43 B
EBI1_BA0/A16 VDDIOM0 100nF
B10 EBI1_A17 32.768 kHz L13 C44
EBI1_BA1/A17 VDDIOM0 100nF
G17 C17 EBI1_A18 C45 D1 M14 C46
{4} EBI0_BA0 EBI0_DDR_BA0 EBI1_A18 XOUT32 VDDIOM0 100nF

2
G16 15pF VDDIOM1 {2}
{4} EBI0_BA1 EBI0_DDR_BA1 B11 EBI1_DQM0 {4} D16 C47
EBI1_DQM0 VDDIOM1 100nF
D11 EBI1_DQM1 {4} F6 C48
EBI1_DQM1 VDDIOM1 100nF
J16 A11 EBI1_DQS0 {4} VDDBU R20 DNP E4 G10 C49
{4} EBI0_CKE EBI0_DDR_CKE EBI1_DQS0 JTAGSEL VDDIOM1 100nF
J18 E11 EBI1_DQS1 {4} NTRST N10 G11 C50
{4} EBI0_CLK EBI0_DDR_CLK EBI1_DQS1 {9} NTRST NTRST VDDIOM1 100nF
H18 TDI R10
{4} EBI0_NCLK EBI0_DDR_NCLK {9} TDI TDI
A12 EBI1_RAS {4} TMS P10 VDDPLLA {2}
EBI1_RAS {9} TMS TMS
H14 C11 EBI1_CAS {4} TCK U10 P11 C51 100nF
{4} EBI0_CS EBI0_DDR_CS EBI1_CAS {9} TCK TCK VDDPLLA
F12 EBI1_SDWE {4} RTCK R11
EBI1_SDW E {9} RTCK RTCK
H17 B9 EBI1_SDA10 {4} TDO V10
{4} EBI0_CAS EBI0_DDR_CAS EBI1_SDA10 {9} TDO TDO
J17 B12 EBI1_SDCKE {4} NRST M10 E2
{4} EBI0_RAS EBI0_DDR_RAS EBI1_SDCKE {2,7,8,9,10,12} NRST NRST TSADVREF
H15 A13 E3 0R R21

GNDCORE
GNDCORE
GNDCORE
GNDCORE
{4} EBI0_WE EBI0_DDR_W E EBI1_SDCK EBI1_SDCK {4} VDDANA VDDANA {2}

GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOM
GNDIOM
A14 F3

GNDIOP
GNDIOP
EBI1_NSDCK EBI1_NSDCK {4} {2} SHDN SHDN

WKUP

BMS

VBG

TST
A16 A10 C2 C52 C53
{5,6} DDR_VREF EBI0_DDR_VREF EBI1_NCS0 EBI1_NCS0 {6} GNDANA
F10 EBI1_NCS1/SDCS {4} 100nF 100nF
EBI1_NCS1/SDCS

C3

T11

V18

E5

G9
H9
J9
J10
C16
H12
H13
J12
J13
K11
K12
H10
J11
G14 F11 EBI1_NRD/CFOE {6}
{4} EBI0_DQM0 EBI0_DDR_DQM0 EBI1_NRD/CFOE
H16 C9 EBI1_NWE/NWR0/CFWE {6}
{4} EBI0_DQM1 EBI0_DDR_DQM1 EBI1_NW E/NW R0/CFW E D9 R22
EBI1_NBS1/NW R1/CFIOR {2} WAKE UP
A9 0R
G18 EBI1_NBS3/NW R3/CFIOW
{4} EBI0_DQS0 EBI0_DDR_DQS0
G15 D10 EBI1_NANDOE {6}
{4} EBI0_DQS1 EBI0_DDR_DQS1 EBI1_NANDOE 3V3
E10 EBI1_NANDWE {6} R24
EBI1_NANDW E
10K
A A

R25
SUP1 4.7K E LN 03-sep-09
D PP 22-jun-09

10pF

6.8K
C PP 02-DEC-08
B PP 29-JUL-08
BOOT MODE SELECT JP8 A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX

C54

R23
Opened = Internal ROM BOOT REV MODIF. DES. DATE VER. DATE
Closed = NCS0 AT91SAM9M10-EKES
AT91SAM9G45-EKES
SCALE
1/1 REV. SHEET
3
DNP
SG-BGA-CA89405MF SAM9 chip E 12
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
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EBI Bus Impedance Adaptor EBI1_D0 4 RR1D 5 EBI1_DDR_D0

EBI1_DDR_D[0..15] {6}

{3} EBI1_D[0..15] EBI1_NAND_FSH_D[0..15] {6} EBI1_FLASH_A[1..21] {6}

EBI1_FLASH_A1
EBI1_D1 1 RR1A 8 EBI1_DDR_D1 EBI1_FLASH_A2
DDR_D[0..15] {5} EBI1_NAND_FSH_D0 EBI1_FLASH_A3
{3} EBI0_D[0..15]
EBI1_NAND_FSH_D1 EBI1_FLASH_A4
EBI0_D0 2 RR4B 7 DDR_D0 EBI1_D2 2 RR1B 7 EBI1_DDR_D2 EBI1_NAND_FSH_D2 EBI1_FLASH_A5
EBI1_NAND_FSH_D3 EBI1_FLASH_A6
EBI0_D1 4 RR2D 5 DDR_D1 EBI1_D0 1 RR9A 8 EBI1_FLASH_D0 EBI1_NAND_FSH_D4 EBI1_FLASH_A7
EBI1_D3 3 RR1C 6 EBI1_DDR_D3 EBI1_NAND_FSH_D5 EBI1_FLASH_A8

EBI1
EBI0_D2 2 RR2B 7 DDR_D2 2 RR9B 7 EBI1_NAND_FSH_D0 EBI1_NAND_FSH_D6 EBI1_FLASH_A9
EBI1_NAND_FSH_D7 EBI1_FLASH_A10
D EBI0_D3 1 RR4A 8 DDR_D3 EBI1_D1 1 RR11A 8 EBI1_FLASH_D1 EBI1_D4 2 RR3B 7 EBI1_DDR_D4 EBI1_NAND_FSH_D8 EBI1_FLASH_A11 D
EBI1_NAND_FSH_D9 EBI1_FLASH_A12

EBI0
EBI0_D4 3 RR4C 6 DDR_D4 2 RR11B 7 EBI1_NAND_FSH_D1 EBI1_NAND_FSH_D10 EBI1_FLASH_A13
EBI1_D5 1 RR3A 8 EBI1_DDR_D5 EBI1_NAND_FSH_D11 EBI1_FLASH_A14
EBI0_D5 4 RR4D 5 DDR_D5 EBI1_D2 4 RR11D 5 EBI1_FLASH_D2 EBI1_NAND_FSH_D12 EBI1_FLASH_A15
EBI1_NAND_FSH_D13 EBI1_FLASH_A16
EBI0_D6 1 RR2A 8 DDR_D6 3 RR11C 6 EBI1_NAND_FSH_D2 EBI1_D6 4 RR3D 5 EBI1_DDR_D6 EBI1_NAND_FSH_D14 EBI1_FLASH_A17
EBI1_NAND_FSH_D15 EBI1_FLASH_A18
EBI0_D7 3 RR2C 6 DDR_D7 EBI1_D3 3 RR9C 6 EBI1_FLASH_D3 EBI1_FLASH_A19
EBI1_D7 3 RR3C 6 EBI1_DDR_D7 EBI1_FLASH_A20
EBI0_D8 2 RR6B 7 DDR_D8 4 RR9D 5 EBI1_NAND_FSH_D3 EBI1_FLASH_A21

EBI0_D9 4 RR8D 5 DDR_D9 EBI1_D4 1 RR13A 8 EBI1_FLASH_D4

EBI1_D8 3 RR5C 6 EBI1_DDR_D8 EBI1_A1 2 RR30B 7
EBI0_D10 4 RR6D 5 DDR_D10 2 RR13B 7 EBI1_NAND_FSH_D4
3 RR30C 6 EBI1_FLASH_A1
EBI0_D11 2 RR8B 7 DDR_D11 EBI1_D5 3 RR13C 6 EBI1_FLASH_D5 EBI1_D9 1 RR7A 8 EBI1_DDR_D9
EBI1_A2 4 RR18D 5 EBI1_DDR_A2
EBI0_D12 1 RR8A 8 DDR_D12 4 RR13D 5 EBI1_NAND_FSH_D5 EBI1_DDR_A[2..15] {6}
EBI1_D10 2 RR5B 7 EBI1_DDR_D10 1 RR18A 8 EBI1_FLASH_A2
EBI0_D13 3 RR6C 6 DDR_D13 EBI1_D6 1 RR17A 8 EBI1_FLASH_D6
EBI1_A3 2 RR28B 7 EBI1_DDR_A3
EBI0_D14 1 RR6A 8 DDR_D14 2 RR17B 7 EBI1_NAND_FSH_D6 EBI1_D11 4 RR7D 5 EBI1_DDR_D11
3 RR28C 6 EBI1_FLASH_A3
EBI0_D15 3 RR8C 6 DDR_D15 EBI1_D7 3 RR17C 6 EBI1_FLASH_D7
EBI1_D12 1 RR5A 8 EBI1_DDR_D12 EBI1_A4 4 RR30D 5 EBI1_DDR_A4
DDR_A[0..13] {5} 4 RR17D 5 EBI1_NAND_FSH_D7
{3} EBI0_A[0..13]
1 RR15A 8 EBI1_FLASH_A4
EBI0_A0 1 RR10A 8 DDR_A0 EBI1_D13 3 RR7C 6 EBI1_DDR_D13
C EBI1_D8 4 RR19D 5 EBI1_FLASH_D8 EBI1_A5 2 RR18B 7 EBI1_DDR_A5 C
EBI0_A1 2 RR10B 7 DDR_A1
3 RR19C 6 EBI1_NAND_FSH_D8 EBI1_D14 2 RR7B 7 EBI1_DDR_D14 3 RR18C 6 EBI1_FLASH_A5
EBI0_A2 3 RR10C 6 DDR_A2
EBI1_D9 2 RR21B 7 EBI1_FLASH_D9 EBI1_A6 2 RR20B 7 EBI1_DDR_A6
EBI0_A3 3 RR12C 6 DDR_A3 EBI1_D15 4 RR5D 5 EBI1_DDR_D15
1 RR21A 8 EBI1_NAND_FSH_D9 1 RR20A 8 EBI1_FLASH_A6
EBI0_A4 4 RR10D 5 DDR_A4
EBI1_D10 3 RR25C 6 EBI1_FLASH_D10 EBI1_A7 1 RR22A 8 EBI1_DDR_A7
EBI0_A5 2 RR12B 7 DDR_A5
4 RR25D 5 EBI1_NAND_FSH_D10 2 RR22B 7 EBI1_FLASH_A7
EBI0_A6 1 RR12A 8 DDR_A6
EBI1_D11 2 RR23B 7 EBI1_FLASH_D11
EBI0_A7 4 RR14D 5 DDR_A7 CAUTION EBI1_A8 1 RR30A 8 EBI1_DDR_A8
1 RR23A 8 EBI1_NAND_FSH_D11
EBI0_A8 3 RR14C 6 DDR_A8 Pin assignemts at 4 RR28D 5 EBI1_FLASH_A8
EBI1_D12 1 RR25A 8 EBI1_FLASH_D12 PCB layout time
EBI0_A9 2 RR14B 7 DDR_A9 EBI1_A9 4 RR24D 5 EBI1_DDR_A9
2 RR25B 7 EBI1_NAND_FSH_D12
EBI0_A10 4 RR12D 5 DDR_A10 1 RR28A 8 EBI1_FLASH_A9
EBI1_D13 3 RR23C 6 EBI1_FLASH_D13
EBI0_A11 1 RR14A 8 DDR_A11 EBI1_A10 3 RR20C 6 EBI1_DDR_A10
4 RR23D 5 EBI1_NAND_FSH_D13
EBI0_A12 2 RR16B 7 DDR_A12 4 RR20D 5 EBI1_FLASH_A10
EBI1_D14 4 RR21D 5 EBI1_FLASH_D14
EBI0_A13 1 RR16A 8 DDR_A13 EBI1_A11 1 RR27A 8 EBI1_DDR_A11
3 RR21C 6 EBI1_NAND_FSH_D14
3 RR26C 6 EBI1_FLASH_D[0..15] {6} 2 RR27B 7 EBI1_FLASH_A11
EBI1_D15 2 RR19B 7 EBI1_FLASH_D15
B 4 RR26D 5 SDA10 3 RR22C 6 EBI1_DDR_A12 (SDA10) B
1 RR19A 8 EBI1_NAND_FSH_D15
EBI1_A12 4 RR22D 5 EBI1_FLASH_A12

EBI1_A13 4 RR27D 5 EBI1_DDR_A13

R26 27R R29 27R
{3} EBI0_CKE DDR_CKE {5} {3} EBI1_SDCKE CKE_EBI1 {6}
3 RR27C 6 EBI1_FLASH_A13
R27 27R R30 27R
{3} EBI0_CLK DDR_CLK {5} {3} EBI1_SDCK CLK_EBI1 {6}
EBI1_A14 3 RR15C 6 EBI1_DDR_A14
R28 27R R31 27R
{3} EBI0_NCLK DDR_NCLK {5} {3} EBI1_NSDCK NCLK_EBI1 {6}
2 RR24B 7 EBI1_FLASH_A14

EBI1_A15 4 RR15D 5 EBI1_DDR_A15

4 RR16D 5 DDR_BA0 {5} EBI1_A16 1 RR31A 8 BA0_EBI1 {6}
{3} EBI0_BA0
3 RR24C 6 EBI1_FLASH_A15
1 RR26A 8 DDR_BA1 {5} EBI1_A17 3 RR31C 6 BA1_EBI1 {6}
{3} EBI0_BA1
EBI1_A16 2 RR31B 7 EBI1_FLASH_A16
3 RR16C 6 DDR_W E {5} 2 RR33B 7 CS_EBI1 {6}
{3} EBI0_W E {3} EBI1_NCS1/SDCS
EBI1_A17 4 RR31D 5 EBI1_FLASH_A17
2 RR26B 7 DDR_CS {5} 1 RR33A 8 W E_EBI1 {6}
{3} EBI0_CS {3} EBI1_SDW E
{3} EBI1_A[1..18]
EBI1_A18 1 RR24A 8 EBI1_FLASH_A18

3 RR29C 6 DDR_RAS {5} 2 RR15B 7 RAS_EBI1 {6} (A19) 2 RR32B 7 EBI1_FLASH_A19

{3} EBI0_RAS {3} EBI1_RAS {3} PC2
4 RR29D 5 DDR_CAS {5} 3 RR33C 6 CAS_EBI1 {6} (A20) 3 RR32C 6 EBI1_FLASH_A20
{3} EBI0_CAS {3} EBI1_CAS {3} PC3
1 RR29A 8 DDR_DQM0 {5} 4 RR33D 5 DQM0_EBI1 {6} (A21) 4 RR32D 5 EBI1_FLASH_A21
{3} EBI0_DQM0 {3} EBI1_DQM0 {3,6} PC4
A A
2 RR29B 7 DDR_DQM1 {5} 1 RR32A 8 DQM1_EBI1 {6}
{3} EBI0_DQM1 {3} EBI1_DQM1

E LN 03-sep-09
R32 27R R34 27R D PP 22-jun-09
{3} EBI0_DQS0 DDR_DQS0 {5} {3} EBI1_DQS0 DQS0_EBI1 {6}
C PP 02-DEC-08
R33 27R R35 27R B PP 29-JUL-08
{3} EBI0_DQS1 DDR_DQS1 {5} {3} EBI1_DQS1 DQS1_EBI1 {6}
A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
REV MODIF. DES. DATE VER. DATE
SDA10 AT91SAM9M10-EKES
{3} EBI1_SDA10 SCALE
1/1 REV. SHEET
AT91SAM9G45-EKES
RES.ARRAYS-EBI0_EBI1 E 4
12
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8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

{4} DDR_D[0..15]
D D

{4} DDR_A[0..13]

MN6 MN7
DDR_A0 H8 C8 DDR_D0 DDR_A0 H8 C8 DDR_D8
DDR_A1 H3 A0 DDR2 SDRAM DQ0 C2 DDR_D1 DDR_A1 H3 A0 DDR2 SDRAM DQ0 C2 DDR_D9
DDR_A2 H7 A1 DQ1 D7 DDR_D2 DDR_A2 H7 A1 DQ1 D7 DDR_D10
DDR_A3 J2 A2 MT47H64M8CF-3 DQ2 D3 DDR_D3 DDR_A3 J2 A2 MT47H64M8CF-3 DQ2 D3 DDR_D11
DDR_A4 J8 A3 DQ3 D1 DDR_D4 DDR_A4 J8 A3 DQ3 D1 DDR_D12
DDR_A5 J3 A4 DQ4 D9 DDR_D5 DDR_A5 J3 A4 DQ4 D9 DDR_D13
DDR_A6 J7 A5 DQ5 B1 DDR_D6 DDR_A6 J7 A5 DQ5 B1 DDR_D14
DDR_A7 K2 A6 DQ6 B9 DDR_D7 DDR_A7 K2 A6 DQ6 B9 DDR_D15
DDR_A8 K8 A7 DQ7 DDR_A8 K8 A7 DQ7
DDR_A9 K3 A8 B7 DDR_A9 K3 A8 B7
A9 DQS DDR_DQS0 {4} A9 DQS DDR_DQS1 {4}
DDR_A10 H2 A8 DDR_A10 H2 A8
C DDR_A11 K7 A10 DQS DDR_A11 K7 A10 DQS C
DDR_A12 L2 A11 B3 DDR_A12 L2 A11 B3
A12 RDQS/DM DDR_DQM0 {4} A12 RDQS/DM DDR_DQM1 {4}
DDR_A13 L8 A2 DDR_A13 L8 A2
A13 RDQS/NU 1V8 A13 RDQS/NU 1V8
BA0 G2 A1 C55 100nF BA0 G2 A1 C56 100nF
{4} DDR_BA0 BA0 VDD BA0 VDD
BA1 G3 E9 C57 100nF BA1 G3 E9 C58 100nF
{4} DDR_BA1 BA1 VDD BA1 VDD
H9 C59 100nF H9 C60 100nF
VDD L1 VDD L1
VDD C61 100nF VDD C62 100nF
F9 F9
ODT E1 ODT E1
VDDL C63 100nF VDDL C64 100nF
CKE F2 A9 C65 100nF CKE F2 A9 C66 100nF
{4} DDR_CKE CKE VDDQ CKE VDDQ
C1 C67 100nF C1 C68 100nF
CK E8 VDDQ C3 CK E8 VDDQ C3
{4} DDR_CLK CK VDDQ C69 100nF CK VDDQ C70 100nF
NCK F8 C7 C71 100nF NCK F8 C7 C72 100nF
{4} DDR_NCLK CK VDDQ CK VDDQ
C9 C73 100nF C9 C74 100nF
VDDQ VDDQ
CS G8 E2 DDR_VREF CS G8 E2 DDR_VREF
{4} DDR_CS CS VREF CS VREF
CAS G7 A3 C75 CAS G7 A3 C76
{4} DDR_CAS CAS VSS CAS VSS
RAS F7 E3 100nF RAS F7 E3 100nF
{4} DDR_RAS RAS VSS RAS VSS
J1 J1
NW E F3 VSS K9 NW E F3 VSS K9
{4} DDR_W E WE VSS WE VSS
A7 A7
VSSQ B2 VSSQ B2
G1 VSSQ B8 G1 VSSQ B8
L3 RFU1 VSSQ D2 L3 RFU1 VSSQ D2
L7 RFU2 VSSQ D8 L7 RFU2 VSSQ D8
B RFU3 VSSQ RFU3 VSSQ B
E7 E7
VSSDL VSSDL

1V8
L7

10uH 150mA
R36 C77 R37
1R 100nF 1.5K

C78 DDR_VREF DDR_VREF {3,6}

4.7uF

C79 R38
100nF 1.5K
A A

E LN 03-sep-09
D PP 22-jun-09
C PP 02-DEC-08
B PP 29-JUL-08
A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
REV MODIF. DES. DATE VER. DATE
AT91SAM9M10-EKES SCALE
1/1 REV. SHEET
AT91SAM9G45-EKES
E 5
EBI0_DDR2
12
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8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

{4} EBI1_FLASH_D[0..15]

{4} EBI1_FLASH_A[1..21]

{4} EBI1_DDR_D[0..15]

{4} EBI1_DDR_A[2..15]
MN8 MN9 MN10
EBI1_DDR_A2 H8 C8 EBI1_DDR_D0 EBI1_DDR_A2 H8 C8 EBI1_DDR_D8 EBI1_FLASH_A1 E1 E2 EBI1_FLASH_D0
EBI1_DDR_A3 H3 A0 DDR2 SDRAM DQ0 C2 EBI1_DDR_D1 EBI1_DDR_A3 H3 A0 DDR2 SDRAM DQ0 C2 EBI1_DDR_D9 EBI1_FLASH_A2 D1 A0 I/00 H2 EBI1_FLASH_D1
EBI1_DDR_A4 H7 A1 DQ1 D7 EBI1_DDR_D2 EBI1_DDR_A4 H7 A1 DQ1 D7 EBI1_DDR_D10 EBI1_FLASH_A3 C1 A1 FLASH I/O1 E3 EBI1_FLASH_D2
EBI1_DDR_A5 J2 A2 MT47H64M8CF-3 DQ2 D3 EBI1_DDR_D3 EBI1_DDR_A5 J2 A2 MT47H64M8CF-3 DQ2 D3 EBI1_DDR_D11 EBI1_FLASH_A4 A1 A2 I/O2 H3 EBI1_FLASH_D3
D D
EBI1_DDR_A6 J8 A3 DQ3 D1 EBI1_DDR_D4 EBI1_DDR_A6 J8 A3 DQ3 D1 EBI1_DDR_D12 EBI1_FLASH_A5 B1 A3 AT49SV322DT I/O3 H4 EBI1_FLASH_D4
EBI1_DDR_A7 J3 A4 DQ4 D9 EBI1_DDR_D5 EBI1_DDR_A7 J3 A4 DQ4 D9 EBI1_DDR_D13 EBI1_FLASH_A6 D2 A4 I/O4 E4 EBI1_FLASH_D5
EBI1_DDR_A8 J7 A5 DQ5 B1 EBI1_DDR_D6 EBI1_DDR_A8 J7 A5 DQ5 B1 EBI1_DDR_D14 EBI1_FLASH_A7 C2 A5 I/O5 H5 EBI1_FLASH_D6
EBI1_DDR_A9 K2 A6 DQ6 B9 EBI1_DDR_D7 EBI1_DDR_A9 K2 A6 DQ6 B9 EBI1_DDR_D15 EBI1_FLASH_A8 A2 A6 I/O6 E5 EBI1_FLASH_D7
EBI1_DDR_A10 K8 A7 DQ7 EBI1_DDR_A10 K8 A7 DQ7 EBI1_FLASH_A9 B5 A7 I/O7 F2 EBI1_FLASH_D8
EBI1_DDR_A11 K3 A8 B7 EBI1_DDR_A11 K3 A8 B7 EBI1_FLASH_A10 A5 A8 I/O8 G2 EBI1_FLASH_D9
A9 DQS DQS0_EBI1 {4} A9 DQS DQS1_EBI1 {4} A9 I/O9
EBI1_DDR_A12 (SDA10) H2 A8 EBI1_DDR_A12 (SDA10) H2 A8 EBI1_FLASH_A11 C5 F3 EBI1_FLASH_D10
EBI1_DDR_A13 K7 A10 DQS EBI1_DDR_A13 K7 A10 DQS EBI1_FLASH_A12 D5 A10 I/O10 G3 EBI1_FLASH_D11
EBI1_DDR_A14 L2 A11 B3 EBI1_DDR_A14 L2 A11 B3 EBI1_FLASH_A13 B6 A11 I/O11 F4 EBI1_FLASH_D12
A12 RDQS/DM DQM0_EBI1 {4} A12 RDQS/DM DQM1_EBI1 {4} A12 I/O12
EBI1_DDR_A15 L8 A2 EBI1_DDR_A15 L8 A2 EBI1_FLASH_A14 A6 G5 EBI1_FLASH_D13
A13 RDQS/NU 1V8 A13 RDQS/NU 1V8 EBI1_FLASH_A15 C6 A13 I/O13 F5 EBI1_FLASH_D14
BA0_EBI1 G2 A1 BA0_EBI1 G2 A1 EBI1_FLASH_A16 D6 A14 I/O14 G6 EBI1_FLASH_D15
{4} BA0_EBI1 BA0 VDD C80 100nF BA0 VDD C81 100nF A15 I/O15
BA1_EBI1 G3 E9 C82 100nF BA1_EBI1 G3 E9 C83 100nF EBI1_FLASH_A17 E6
{4} BA1_EBI1 BA1 VDD BA1 VDD A16
H9 C84 100nF H9 C85 100nF EBI1_FLASH_A18 B2
VDD L1 VDD L1 EBI1_FLASH_A19 C3 A17 A3
VDD C86 100nF VDD C87 100nF A18 RDY/ BUSY
F9 F9 EBI1_FLASH_A20 D4
ODT E1 ODT E1 EBI1_FLASH_A21 D3 A19
VDDL C88 100nF VDDL C89 100nF A20 C4
CKE_EBI1 F2 A9 CKE_EBI1 F2 A9 NC1 F6
{4} CKE_EBI1 CKE VDDQ C90 100nF CKE VDDQ C91 100nF NC
C1 C92 100nF C1 C93 100nF R39 100K
CLK_EBI1 E8 VDDQ C3 CLK_EBI1 E8 VDDQ C3 B4
{4} CLK_EBI1 CK VDDQ C94 100nF CK VDDQ C95 100nF 1V8 RESET 1V8
NCLK_EBI1 F8 C7 C96 100nF NCLK_EBI1 F8 C7 C97 100nF A4
{4} NCLK_EBI1 CK VDDQ CK VDDQ {3} EBI1_NW E/NW R0/CFW E WE
C9 C98 100nF C9 C99 100nF G4
VDDQ VDDQ B3 VCC C100
1V8 VPP
CS_EBI1 (NCS1) G8 E2 VREF1 CS_EBI1 G8 E2 VREF1 F1 H1 100nF
{4} CS_EBI1 CS VREF CS VREF CE GND
G1 H6
{3} EBI1_NRD/CFOE OE GND
CAS_EBI1 G7 A3 C101 CAS_EBI1 G7 A3 C102 CBGA
{4} CAS_EBI1 CAS VSS CAS VSS
RAS_EBI1 F7 E3 100nF RAS_EBI1 F7 E3 100nF DNP
{4} RAS_EBI1 RAS VSS RAS VSS
C J1 J1 C
W E_EBI1 F3 VSS K9 W E_EBI1 F3 VSS K9
{4} W E_EBI1 WE VSS WE VSS
A7 A7
VSSQ B2 VSSQ B2 JP9
VSSQ VSSQ R40 470K
G1 B8 G1 B8 1V8
RFU1 VSSQ RFU1 VSSQ {3} EBI1_NCS0
L3 D2 L3 D2
L7 RFU2 VSSQ D8 L7 RFU2 VSSQ D8
RFU3 VSSQ RFU3 VSSQ
E7 E7
VSSDL VSSDL

VREF1
{3,5} DDR_VREF

{4} EBI1_NAND_FSH_D[0..15]

MN11
(NANDCLE) D5 H4 EBI1_NAND_FSH_D0
{3} PC5 CLE I/O0
(NANDALE) C4 J4 EBI1_NAND_FSH_D1
{3,4} PC4
0R RE D4 ALE NAND FLASH I/O1 K4 EBI1_NAND_FSH_D2
{3} EBI1_NANDOE R42
B JP10 0R WE C7 RE MT29F2G08ABD I/O2 K5 EBI1_NAND_FSH_D3 B
{3} EBI1_NANDW E R43
(NCS3) CE C6 WE I/O3 K6 EBI1_NAND_FSH_D4
{3} PC14 CE I/O4
1V8 R46 470K J7 EBI1_NAND_FSH_D5
(RDY/BSY) 0R RB C8 I/O5 K7 EBI1_NAND_FSH_D6
{3} PC8 R44
1K R/B I/O6 J8 EBI1_NAND_FSH_D7
R45
WP C3 I/O7 H3 EBI1_NAND_FSH_D8
1V8 WP N.C26
R41 470K J3 EBI1_NAND_FSH_D9
G5 N.C27 H5 EBI1_NAND_FSH_D10
LOCK N.C28 J5 EBI1_NAND_FSH_D11 Optional 16bits DATA BUS
R47 N.C29 H6 EBI1_NAND_FSH_D12 With AT29F2G16ABD Micron
DNP A1 N.C30 G6 EBI1_NAND_FSH_D13
A2 N.C1 N.C31 H7 EBI1_NAND_FSH_D14
A9 N.C2 N.C32 G7 EBI1_NAND_FSH_D15
A10 N.C3 N.C33
B1 N.C4
B9 N.C5 L9
B10 N.C6 N.C34 L10
D6 N.C7 N.C35 M1
D7 N.C8 N.C36 M2
D8 N.C9 N.C37 M9
E3 N.C10 N.C38 M10
E4 N.C11 N.C39
E5 N.C12 1V8
E6 N.C13 D3
N.C14 VCC C103 100nF
E7 G4 C104 100nF
E8 N.C15 VCC H8
N.C16 VCC C105 100nF
F3 J6 C106 100nF
F4 N.C17 VCC
F5 N.C18
A N.C19 A
F6
F8 N.C20 C5
G3 N.C21 VSS F7
G8 N.C22 VSS K3 E LN 03-sep-09
L1 N.C23 VSS K8 PP 22-jun-09
D
L2 N.C24 VSS C PP 02-DEC-08
N.C25 VFBGA-63 B PP 29-JUL-08
MT29F2G08ABDHC:D A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
REV MODIF. DES. DATE VER. DATE
AT91SAM9M10-EKES SCALE
1/1 REV. SHEET
AT91SAM9G45-EKES
E 6
EBI1_MEMORY
12
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8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

3V3

D 3V3 D

8
7
6
5

8
7
6
5

8
7
6
5
RR34 RR35 RR36

8
7
6
5
68K 10K
R51 RR41 R52 68K
10K 68K 10K

1
2
3
4

1
2
3
4

1
2
3
4
(MCI1_W P)
{3} PD29

1
2
3
4
(MCI0_CD) (MCI1_CD)
{3} PD10 {3} PD11
{3} PA[0..5] {3,10} PA[22..31]
J6 12 J5 16
PA3 (MCI0_DA1) R186 27R C109100nF 8 11 PA24 (MCI1_DA1) R192 27R 8 15
PA2 (MCI0_DA0) R187 27R 7 10 PA23 (MCI1_DA0) R193 27R 7 14
3V3 6 6
PA0 (MCI0_CK) R188 27R 5 PA31 (MCI1_CK) R194 27R 5
4 3V3 4
3 3 13
PA1 (MCI0_CDA) R189 27R 2 PA22 (MCI1_CDA) R195 27R 2 12
PA5 (MCI0_DA3) R190 27R 1 PA26 (MCI1_DA3) R196 27R 1 11
PA4 (MCI0_DA2) R191 27R 9 PA25 (MCI1_DA2) R197 27R 9 10

FPS009 C108 7SDMM-B0-2211

100nF
PA27 (MCI1_DA4) R198 27R
PA28 (MCI1_DA5) R199 27R
PA29 (MCI1_DA6) R200 27R
PA30 (MCI1_DA7) R201 27R

C C

SD/MMCPlus CARD INTERFACE - MCI1

SD/MMC CARD INTERFACE - MCI0

3V3

3V3

DNP R53
Test point 470K
R54 1 3 3V3
10K JP11
B MN14 B

2
MN13 (SPI0_MISO) 8 6
{3} PB0 SO VCC
(TW CK0) 6 1 (SPI0_MOSI) 1 C110
{3,12} PA21 SCL A0 {3} PB1 SI
(TW DO) 5 2 (SPI0_SPCK) JP12 2 100nF
{3,12} PA20 SDA A1 {3} PB2 SCK
3 (SPI0_NPCS0) 4 7
A3 {3} PB3 CS GND
3V3 8 JP13
VCC
C111 3 5
{2,3,8,9,10,12} NRST RESET WP
100nF 4 7
GND WP AT45D321D
AT24C512BN-SH25-B SERIAL DATAFLASH R55
DNP
W RITE PROTECT
NORMALLY OPEN
SERIAL EEPROM

A A

E LN 03-sep-09
D PP 22-jun-09
C PP 02-DEC-08
B PP 29-JUL-08
A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
REV MODIF. DES. DATE VER. DATE
AT91SAM9M10-EKES SCALE
1/1 REV. SHEET
AT91SAM9G45-EKES
E 7
MCI & TW I
12
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8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

CLOCK SELECTION - PIN STRAPING TABLE C112100uF 6V3 3.5 PHONEJACK STEREO
L8 3 J7

+
5
RA=1K RB=1K CODEC ID CLK FREQ 742792093

OUT OUT PRIMARY 24.576 MHz Local XTAL

OUT IN SECONDARY 12.288 MHz Ext. BITCLK L9 2 HEADPHONE

+
IN OUT PRIMARY 48.000 MHz Ext. BITCLK (Into XTAL-IN) 742792093 LINE-OUT
IN IN PRIMARY 14.318 MHz Ext. BITCLK (Into XTAL-IN) C113100uF 6V3

(see table) AVDD_AC97 R56 R57 C114 C115

C117 1K 1K 470pF 470pF 1 4
R58 DNP 100nF
D D
RA
C118
RB C116 10uF
100nF 10V AGND_AC97
R59 DNP

AGND_AC97 C119 R61 22K R62 22K

(EXT_CLK) R60 DNP 1uF
{3} PE31
C124 C121
C120 22pF 100nF 3V3 10uF

48
47
46
45
44
43
42
41
40
39
38
37

AGND_AC97
MN15 10V
AVDD_AC97

SPDIF
EAPD
ID1
ID0
AVSS3
AVDD3
NC
HP_OUT_R
AVSS2
HP_OUT_L
AVDD2
MONO_OUT
Y3 C122 C125
24.576MHz 10uF 100nF 6 C126 100nF
10V MN16
AVDD_AC97 JP14 DNP VDD
C123 22pF 4 -IN
1 36 1 3 Vo1 5
2 DVDD1 LINE_OUT_R 35 3 +IN
3 XTL_IN LINE_OUT_L 34
XTL_OUT AVDD4 C127 100nF

2
4 33 SPEAKER OUTPUT
(AC97TX) 5 DVSS1 AVSS4 32 JP15
{3} PD7 SDATA_OUT AFILT4 C128 270pF
(AC97CK) 6 AD1981B 31 C129 270pF DNP
{3} PD9 BIT_CLK AFILT3
7 30 C130 270pF
(AC97RX) 8 DVSS2 AFILT2 29
{3} PD6 SDATA_IN AFILT1 C131 270pF
9 28 VREFOUT Av=1
8
DVDD2 VREFOUT VDD/2
(AC97FS) 10 27 C132 100nF 2 Bypass Vo2
{3} PD8 SYNC VREF
11 26
{2,3,7,9,10,12} NRST RESET AVSS1
C 12 25 C134 C133 100nF C
NC1 AVDD1 1uF C135

CD_GND_REF
100nF 1 Shutdown
Bias

PHONE_IN

LINE_IN_R
LINE_IN_L
GND

AUX_R
AUX_L

CD_ R
AGND_AC97 SSM2211

CD_L

MIC1
MIC2
7

JS1
JS0
13
14
15
16
17
18
19
20
21
22
23
24
AGND_AC97

R63 2.2K
C136 R64 4.7K 3.5 PHONEJACK STEREO
1uF L10 3 J8 5
R65 2.2K 742792093

C137 R66 4.7K

1uF L11 2 LINE-IN
742792093

AGND_AC97 R67 R68 C138 C139

4.7K 4.7K 470pF 470pF 1 4

B OPTIONAL VOICE B
FILTER COMPONENTS AGND_AC97

C140 100nF R69 100R 3.5 PHONEJACK STEREO

L12 3 J9 5
742792093
5V AVDD_AC97
L13 C141 100nF R70 100R
L14 2 MONO / STEREO
10uH 150mA 742792093 MICROPHONE INPUT
C144 C145 C146
10uF 47uF C142 C143 R71 R72
10V 100nF 6V3 10nF 10nF 3.9K 3.9K C147 C148
470pF 470pF 1 4
R73 0R
C149
AGND_AC97 470pF
AGND_AC97

R74
OPTIONAL MIC BIASING FROM VREFOUT AVDD_AC97 0R

VREFOUT R75 DNP R76 470R AGND_AC97

WARNING R77 DNP R78 470R

A A

TO BIAS FROM VREFOUT C150 C151 E LN 03-sep-09

CHANGE R71 and R72 to 3k 5% 10uF 10uF D PP 22-jun-09
DO NOT INSTALL R76, R78, C150, C151 10V 10V C PP 02-DEC-08
B PP 29-JUL-08
VREFOUT MUST BE PROGRAMMED TO 3.7V A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
USING VREFH BIT (REG 76h) REV MODIF. DES. DATE VER. DATE
AGND_AC97 AT91SAM9M10-EKES
AT91SAM9G45-EKES
SCALE
1/1 REV. SHEET
8
AUDIO AC97 E 12
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

3V3 MN18 MN17 3V3

16 1 1 16
C153 VCC C1+ C156 3V3 C152 C1+ VCC C154 RS232 COM PORT
SERIAL DEBUG PORT 100nF 100nF 100nF 100nF
15 3V3 15
MALE RIGHT ANGLE GND 3 3 GND MALE RIGHT ANGLE
C155 2 C1- 4 4 C1- 2 C157
J10 100nF V+ C2+ C158 C159 C2+ V+ 100nF
1 100nF R79 R81 100nF 1
6 C160 R80 R82 100K 100K C161 6
D D
2 100nF 6 5 100K 100K 5 6 100nF 2
7 V- C2- C2- V- 7
3 14 11 PB13 {3} 11 14 3
T {3} PB4 T
8 8
4 4
9 7 10 10 7 9
T {3} PD16 T
5 5

13 12 PB12 {3} 12 13
R {3} PB5 R
11

10

10

11
R83 0R
8 9 9 8
R {3} PD17 R
J11
ADM3202ARNZ ADM3202ARNZ

C C

J12
292303-1 USB HOST INTERFACE
1 2 HDMA {3}
4 3 3V3
HDPA {3}
C162
100nF RR42
5 6 100K

5
6
7
8
3V3 J13 3V3

2 1

4
3
2
1
4 3 R84 DNP NTRST NTRST {3}
6 5 TDI TDI {3}
5V 8 7 TMS TMS {3}
10 9 TCK TCK {3}
12 11 R85 0R RTCK RTCK {3}
L15 MN20 14 13 TDO TDO {3}
8 1 (ENA) 16 15 R86 0R NRST
OUTA ENA PD1 {3} NRST {2,3,7,8,10,12}
BLM21PG221SN1x 18 17
C164 7 2 (FLGA) PD2 {3} 20 19
33 uF C163 IN FLGA R87
16V 100nF DNP
6 3 (FLGB) PD4 {3}
L16 GNG FLGB
B B
5 4 (ENB)
BLM21PG221SN1x OUTB ENB PD3 {3} ICE INTERFACE
C165 SP2526A-2
33 uF
16V

R88 47K 3V3

(VBUS) PB19 {3}
R89
C166 68K
10pF R90
ZX62-AB-5P 47K
7

1
VBUS
2
SHD

DM HDMB {3}
3 HDPB {3}
DP
ID
4 (IDUSB) PD28 {3}
GND
5

6
J14
USB HOST/DEVICE INTERFACE

C167
100nF
A A

E LN 03-sep-09
D PP 22-jun-09
C PP 02-DEC-08
B PP 29-JUL-08
A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
Take note of layout directive REV MODIF. DES. DATE VER. DATE
AT91SAM9M10-EKES
"High speed USB platform design.PDF"
AT91SAM9G45-EKES
SCALE
1/1 REV. SHEET
9
SERIAL INTERFACES E 12
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

D D
3V3

R91 10K

Y4
1 OE VDD
4
C168
50 MHz 100nF
2 VSS OUT 3
C169 C170
CFPS-39IB 50.0MHZ 18pF 18pF
Y5 C171
4 3 100nF
GND_ETH
R92 R93 DNP 1 2
0R
25MHz

MN22
(TX_CLK) R94 0R 42 43 R96 R97
{3} PA17 REF_CLK/XT2 XT1 49R9 49R9
(TXD3) R98 DNP 17 1% 1%

15

16
{3} PA7 TXD3
(TXD2) R99 DNP 18 J15
{3} PA6 TXD2
(TXD1) 19 7 1 TD+ TX+ 1
{3} PA11 TXD1 TX+
(TXD0) 20
{3} PA10 TXD0
(TX_EN) 21 4 CT
{3} PA14 TX_EN
R95 DNP 22
TX_CLK/ISOLATE 8 2 TD- TX- 2
C (RXD3) R100 DNP 26 TX- C
{3} PA9 RXD3/PHYAD3
(RXD2) R101 DNP 27 AVDDT
{3} PA8 RXD2/PHYAD2
(RXD1) 28
{3} PA13 RXD1/PHYAD1
(RXD0) 29 3 3 RD+ RX+ 3
{3} PA12 RXD0/PHYAD0 RX+
(RX_CLK) R102 DNP 34 5 CT
{3,7} PA28 RX_CLK/10BTSER
(RX_DV) 37
{3} PA15 RX_DV/TESTMODE 4 6 RD- RX- 6
(TX_ER) R103 DNP 16 RX-
{3,7} PA27 TX_ER/TXD4 AVDDT
(RX_ER) 38 L17
{3} PA16 RX_ER/RXD4/RPTR 742792093 R105 R106 C173
(COL) R104 DNP 36 1 C172 100nF 49R9 49R9 100nF 75 75
{3,7} PA30 COL/RMII AVDDR 75
(CRS) R107 DNP 35 1% 1% 7 NC 4
{3,7} PA29 CRS/PHYAD4 C174 100nF
3V3 R108 1.5K 2 C175 C176
(MDC) 24 AVDDR 10uF 10uF 5
{3} PA18 MDC AVDDT 10V 10V
(MDIO) 25 DM9161AEP GND_ETH 1nF
{3} PA19 MDIO C178 100nF 75
(MDINTR) 32 9 C177 8 7
{3} PD5 MDINTR AVDDT 100nF
39 5 8
DISMDIX AGND 6
3V3 AGND 46 J00-0061NL
AGND 3V3
8
7
6
5

8
7
6
5

8
7
6
5

JP16 R185 0R GND_ETH

C179 100nF 41 47 GND_ETH
3V3 DVDD BGRESG RJ45 ETHERNET CONNECTOR

8
7
6
5
C180 100nF 30 R109
DVDD RR46 3V3
6.8K
1
2
3
4

1
2
3
4

1
2
3
4

C181 100nF 23 1% 10K 1K

DVDD 48 YELLOW R110 FULL DUPLEX
15 BGRES 31 D9
DGND LEDMODE

1
2
3
4
B RR43 RR44 RR45 33 11 1K B
10K 10K 10K 44 DGND LED0/OP0 12 GREEN R111 SPEED 100
DGND LED1/OP1 13 D10
R112 0R 10 LED2/OP2 14 1K
PW RDW N CABLESTS/LINKSTS GREEN R113 LINK&ACT
40 45 D11
{2,3,7,8,9,12} NRST RESET N.C

3V3

C182
10uF
10V

R114 0R R115 0R

GND_ETH

A A

Take note of layout directive

E LN 03-sep-09
"DM9161-LG-V11-011401S.PDF" D PP 22-jun-09
C PP 02-DEC-08
B PP 29-JUL-08
A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
REV MODIF. DES. DATE VER. DATE
AT91SAM9M10-EKES
AT91SAM9G45-EKES
SCALE
1/1 REV. SHEET
10
RMII ETHERNET E 12
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

(pinxx = display pin number )

J24 3V3
pin45
1 pin44
2 pin43 VLED+
3 pin42 VLED-
4 pin41
5 pin40 YpLCD
D D
6 pin39 XpLCD R180
Z7 7 pin38 YmLCD 10K
8 pin37 XmLCD
9 pin36
10 pin35
11 pin34 (LCDDEN) PE6
12 pin33
13 PE[0..30] {3,12}
pin32
14 pin31 R50 27R (LCDPW R) PE0
15 pin30 LCDDOTCK PE30 (B7)
16 pin29 PE29 (B6)
17 1 8
4.3" 480x272 18
pin28
pin27 2
RR48A
RR48B 7
BLUE7
BLUE6
PE28
PE27
(B5)
(B4)
19
TFT LCD DISPLAY 20
pin26
pin25
3
4
RR48C
RR48D
6
5
BLUE5
BLUE4
R136
4.7K
PE26
PE25
(B3)
(B2)
21 pin24 1 RR49A 8 BLUE3 PE24 (B1)
22 pin23 2 RR49B 7 BLUE2 R179 0R PE25 PE23 (B0)
23 pin22 3 RR49C 6 BLUE1 R178 0R PE24 PE22 (G7)
24
LG PHILIPS

pin21 4 RR49D 5 BLUE0 R177 0R PE23 PE21 (G6)

25 pin20 1 RR50A 8 GREEN7 PE20 (G5)
26 pin19 2 RR50B 7 GREEN6 PE19 (G4)
PIN 45 27 pin18 3 RR50C 6 GREEN5 PE18 (G3)
28 pin17 4 RR50D 5 GREEN4 PE17 (G2)
29 pin16 1 RR51A 8 GREEN3 PE16 (G1)
Conductors

30
TOP SIDE

pin15 2 RR51B 7 GREEN2 PE15 (G0)

31 pin14 3 RR51C 6 GREEN1 R176 0R PE16 PE14 (R7)
32
on

pin13 4 RR51D 5 GREEN0 R175 0R PE15 PE13 (R6)

33 pin12 1 RR52A 8 RED7 PE12 (R5)
C 34 pin11 2 RR52B 7 RED6 PE11 (R4) C
PIN 1 35 pin10 3 RR52C 6 RED5 PE10 (R3)
36 pin9 4 RR52D 5 RED4 PE9 (R2)
37 pin8 1 RR53A 8 RED3 PE8 (R1)
38 2 7
39
pin7 RR53B RED2 R174 0R PE9 R48 is placed near processor PE7 (R0)
pin6 3 RR53C 6 RED1 R173 0R PE8 PE6 (LCDDEN)
40 pin5 4 RR53D 5 RED0 R172 0R PE7 PE5 (LCDDOTCK)
LB043W Q1 41 {12} LCDDOTCK
pin4 3V3 R48 33R PE4
42 pin3 C188 C189 PE3
43 pin2 100nF 10uF PE2 (LCDCC)
44 pin1 10V PE1
45 PE0 (LCDPW R)
XF2M45151A

R171 DNP PE24

BLUE7 R170 0R PE30

R169 DNP PE23

BLUE6 R168 0R PE29

R167 DNP PE22

BLUE5 R166 0R PE28
B R165 DNP PE21 B
BLUE4 R164 0R PE27

R163 DNP PE20

BLUE3 R162 0R PE26
D12
STPS0540Z L23 5V R161 DNP PE18
VLED+ GREEN7 R160 0R PE22
22uH
C202 C201 R159 DNP PE17
1uF 2.2uF C208 C209 GREEN6 R158 0R PE21
4

MN25 TPS61161DRVT DNP DNP

6 R157 DNP PE16
SW

VIN GREEN5 R156 0R PE20

YpLCD R130 0R (AD2Yp) PD22 {3,12}
5 (LCDCC) PE2 XmLCD R131 0R (AD1Xm) PD21 {3,12} R155 DNP PE15
VLED- 1 CTRL YmLCD R132 0R (AD3Ym) GREEN4 R154 0R PE19
FB PD23 {3,12}
2 XpLCD R133 0R (AD0Xp) PD20 {3,12}
GND

COMP
THP

R123 R137 R153 DNP PE14

10R C203 10K GREEN3 R152 0R PE18
220nF
3

C210 R151 DNP PE13

220K C211 GREEN2 R150 0R PE17
DNP
20mA MAX 9 LEDs Back Light R149 DNP PE12
RED7 R148 0R PE14

This Resistor R147 DNP PE11

RED6 R146 0R PE13
A
is intentionally mounted A

in place of C210 RED5

R145
R144
DNP
0R
PE10
PE12
E LN 03-sep-09
R184 DNP PE9 D PP 22-jun-09
RED4 R183 0R PE11 C PP 02-DEC-08
B PP 29-JUL-08
R182 DNP PE8 A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
RED3 R181 0R PE10 REV MODIF. DES. DATE VER. DATE
AT91SAM9M10-EKES SCALE
1/1 REV. SHEET
AT91SAM9G45-EKES
E 11
LCD & ISI & VIDEO INTERFACE
12
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 8 7 6 5 4 3 2 1

{3,11} PE[0..30] CONNECTOR EXTENTION FOR LARGE LCD

PE30 (B7) J23 TSM-120-01-L-DV
PE29 (B6) PE8 1 2 PE7
PE28 (B5) PE10 3 4 PE9
PE27 (B4) PE12 5 6 PE11
D PE26 (B3) PE14 7 8 PE13 D
PE25 (B2) PE16 9 10 PE15
PE24 (B1) PE18 11 12 PE17
PE23 (B0) PE20 13 14 PE19
PE22 (G7) PE22 15 16 PE21
PE21 (G6) 3V3 PE24 17 18 PE23
PE20 (G5) PE26 19 20 PE25
PE19 (G4) L18 PE28 21 22 PE27
PE18 (G3) 742792093 PE30 23 24 PE29
PE17 (G2) MN23 PE4 25 26 PE3
PE16 (G1) 1V8 {11} LCDDOTCK 27 28
PE15 (G0) PE23 42 38 29 30
PE14 (R7) PE24 43 D0 VDDIO 16 L19 PE6 31 32 PE2
PE13 (R6) PE25 44 D1 DVDD 742792093 PE0 33 34 PE1
PE12 (R5) PE26 45 D2 C190 C191 C192 C193 (GPIO1) 35 36 (GPIO2)
D3 {3} PD14 PD15 {3}
PE11 (R4) PE27 46 100nF 100nF 10uF 10uF 37 38
PE10 (R3) PE28 47 D4 10V 10V 39 40
D5 3V3
PE9 (R2) PE29 48 18
PE8 (R1) PE30 1 D6 DGND DNP
PE7 (R0) PE15 2 D7
D8 J18
PE6 (LCDDEN) PE16 3 32 L20
PE5 (LCDDOTCK) PE17 4 D9 AVDD_PLL C194 742792093 (AD1Xm) 1 2 (AD0Xp)
D10 {3,11} PD21 PD20 {3,11}
PE4 (HSYNC) PE18 5 100nF (AD3Ym) 3 4 (AD2Yp) PD22 {3,11}
D11 {3,11} PD23
PE3 (VSYNC) PE19 6 31 5 6
PE2 (LCDCC) PE20 7 D12 AGND_PLL 3V3 7 8
D13 {3} PD25 PD24 {3}
PE1 (LCDMOD) PE21 8 9 10 PD26 {3}
D14 {3} PD27 R128 R129
PE0 (LCDPW R) PE22 9 33 L21 11 12 PD18 {3}
D15 AVDD {3} PD19
PE7 10 C195 742792093 DNP 13 14 DNP
PE8 11 D16 100nF C196 15 16
D17 5V
C PE9 12 36 10uF 17 18 C
PE10 13 D18 AGND 10V 19 20
D19 3V3 3V3
PE11 14
PE12 15 D20 25 L22 DNP
PE13 17 D21 AVDD_DAC C197 742792093 TSM-110-01-L-DV
PE14 19 D22 100nF
D23 29 3V3
39 AGND_DAC
R49 is placed near processor PE3
V C198
PE4 40
PE5 41 H 30 R116 33pF
R49 33R PE6 20 XCLK ISET
1.2K 1% J20
DE 28 L24 3
R117 4.7K CVBS 1.8uH
3V3

3
C200 D13
R118 4.7K 27 R119 R120 C199 270pF 1 2
Y

1
(TW DO) 21 75R 75R 100pF
{3,7} PA20 SPD
(TW CK0) 22 BAT54SLT1G
{3,7} PA21 SPC R121
26
23 C/CVBS
{2,3,7,8,9,10} NRST RESET 75R
XI/FIN

3V3 24 37 Composite Video Output

NC P-OUT
XO

R122 DNP
CH7024B-DF-TR
34

35

Y6
1 OE TP5
VDD 4
13 MHz
R125
0R IMAGE SENSOR CONNECTOR
2 VSS 3V3
B OUT 3 R124 DNP
B
Y7
SG-8002JC-13.0000M-PCB 4 3
DNP C205
DNP 1 2 C186 C187 C184
100nF 10uF 100nF
C207 13MHz C206 10V
10pF 10pF

J17
{3} PB[8..11]
1 2
PB8 (ISI_D8) 3 4
{2,3} VDDISI
The frequency accuracy must be +-20ppm or higher. PB9 (ISI_D09) (CTRL1) 5 6 (CTRL2) PD13 {3}
{3} PD12
PB10 (ISI_D10) PA21 7 8 PA20
PB11 (ISI_D11) 9 10 PB31
11 12 PB29
13 14 PB30
15 16 PB28
{3} PB[20..31]
17 18 PB20
PB20 (ISI_D0) PB21 19 20 PB22
PB21 (ISI_D1) PB23 21 22 PB24
PB22 (ISI_D2) PB25 23 24 PB26
PB23 (ISI_D3) PB27 25 26 PB8
PB24 (ISI_D4) PB9 27 28 PB10
PB25 (ISI_D5) PB11 29 30
PB26 (ISI_D6)
PB27 (ISI_D7)
PB28 (ISI_PCK)
A PB29 (ISI_VSYNC) A
PB30 (ISI_HSYNC)
PB31 (ISI_MCK)

E LN 03-sep-09
D PP 22-jun-09
C PP 02-DEC-08
B PP 29-JUL-08
A INIT EDIT PP 26-MAY-08 XXX XX-XXX-XX
REV MODIF. DES. DATE VER. DATE
AT91SAM9M10-EKES SCALE
1/1 REV. SHEET
AT91SAM9G45-EKES
E 12
LCD & ISI & VIDEO INTERFACE
12
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8 7 6 5 4 3 2 1
 Section 8
Revision History

8.1 Revision History

Table 8-1.
Change Request
Document Comments Ref.
6481A First issue.
Figure 4-17, ” TFT LCD” updated.
6481B 6833
Section 7.1 ”Schematics” updated.

AT91SAM9G45-EKES User Guide 8-1

6481B–ATARM–27-Nov-09
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6481B–ATARM–27-Nov-09