TDA7575B

2 x 75W multifunction dual-bridge power amplifier

with integrated digital diagnostics

Features
■ Multipower bcd technology
■ MOSFET output power stage
■ DMOS power output
■ New high-efficiency (class AB) PowerSO36
(slug up) Flexiwatt27
■ Single-channel 1driving capability
■ High output power capability 2x28 W/4  @
14.4 V, 1 kHz, 10 % THD
■ Max. output power 2x75 W/2 1x150 W/1 
Description
■ Single-channel 1  driving capability The TDA7575B is a new MOSFET dual bridge
amplifier specially intended for car radio
■ 84 W undistorted power
applications. Thanks to the DMOS output stage
■ Full I2C bus driving with 4 address possibilities: the TDA7575B has a very low distortion allowing
– Standby a clear powerful sound.
– Play/mute Among the features, its superior efficiency
– Gain 12/26 dB performance coming from the internal exclusive
– Full digital diagnostic (AC and DC loads) structure, makes it the most suitable device to
■ Possibility to disable the I2C bus simplify the thermal management in high power
sets.The dissipated output power under average
■ Differential inputs listening condition is in fact reduced up to 50%
■ Full fault protection when compared to the level provided by
■ DC offset detection conventional class AB solutions.

■ Two independent short circuit protections This device is equipped with a full diagnostic array
that communicates the status of each speaker
■ Diagnostic on clipping detector with selectable
through the I2C bus. The TDA7575B has also the
threshold (2 % / 10 %)
possibility of driving loads down to 1 paralleling
■ Clipping detector as diagnostic pin when I2C the outputs into a single channel. It is also
bus is disabled possible to disable the I2C and control the
■ Standby/mute pins TDA7575B by means of the usual standby and
mute pins.
■ ESD protection

Table 1. Device summary

Order code Package Packing

TDA7575B Flexiwatt27 Tube

TDA7575BPD PowerSO36 (slug up) Tube
TDA7575BPDTR PowerSO36 (slug up) Tape and reel

September 2013 Doc ID 14103 Rev 3 1/32

www.st.com 1
Contents TDA7575B

Contents

1 Block and pins diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5 I2C bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.2 Start and stop conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.3 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5 1 W capability setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
5.6 I2C abilitation setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6 Software specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Examples of bytes sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7 Diagnostics functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

7.1 Turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
7.2 Permanent diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.3 Output DC offset detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.4 AC diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 Multiple faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6 Faults availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.7 I2C programming/reading sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2/32 Doc ID 14103 Rev 3

TDA7575B List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Address selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6. IB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 7. IB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 8. DB1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. DB2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. Double fault table for turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 11. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Doc ID 14103 Rev 3 3/32

List of figures TDA7575B

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Pins connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. Quiescent drain current vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 4. Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5. Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Output power vs. supply voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 7. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 8. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 9. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 10. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 11. Distortion vs. output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 12. Distortion vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 13. Distortion vs. output voltage (LD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 14. Cross talk vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 15. Cross talk vs. frequency (LD mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 16. CMRRR vs. frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 17. Output attenuation vs. supply voltage (vs. dependent muting) . . . . . . . . . . . . . . . . . . . . . . 13
Figure 18. Output attenuation vs. mute pin voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 19. Power dissipation vs. output power (4 - SINE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 20. Power dissipation vs. output power (2 - SINE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 21. Power dissipation vs. average output power (Audio program simulation, 4) . . . . . . . . . . 14
Figure 22. Power dissipation vs. average output power (Audio program simulation, 2) . . . . . . . . . . 14
Figure 23. ITU R-ARM frequency response, weighting filter for transient pop. . . . . . . . . . . . . . . . . . . 14
Figure 24. Application circuit (TDA7575B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 25. Application circuit (TDA7575BPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 26. Data validity on the I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 27. Timing diagram on the I2C bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 28. Timing acknowledge clock pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 29. Turn-on diagnostic: working principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. SVR and output behavior - case 1: without turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. SVR and output pin behavior - case 2: with turn-on diagnostic . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. Short circuit detection thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 33. Load detection thresholds - high gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 34. Load detection thresholds - high gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 35. Restart timing without diagnostic enable (permanent) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 36. Restart timing with diagnostic enable (permanent). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 37. Current detection high: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . 27
Figure 38. Current detection low: load impedance |Z| vs. output peak voltage . . . . . . . . . . . . . . . . . . 27
Figure 39. PowerSO36 (slug up) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . 29
Figure 40. Flexiwatt27 (vertical) mechanical data and package dimensions . . . . . . . . . . . . . . . . . . . . 30

4/32 Doc ID 14103 Rev 3

TDA7575B Block and pins diagrams

1 Block and pins diagrams

Figure 1. Block diagram

VS
ADDRESS
A B CLK DATA VCC CD_OUT

CLIP
I2CBUS
DETECTOR
IN1+
OUT1+
IN1-
OUT1-

SHORT CIRCUIT
PROTECTION
IN2+ OUT2+

IN2- OUT2-

SHORT CIRCUIT
PROTECTION I2C EN

SVR ST-BY/HE S_GND PW_GND TAB 1Ω MUTE

D01AU1269

Figure 2. Pins connection diagram (top view)

27 TAB
26 PWGND
OUT1+ 36 1 TAB
25 A
OUT1+ 35 2 IN1+ 24 OUT2+
VCC 34 3 IN1- 23 N.C.
VCC 33 4 MUTE 22 OUT2-
21 VCC
B 32 5 ST_BY
20 IN2+
PWGND 31 6 SGND
19 IN2-
PWGND 30 7 DATA 18 I2CEN
OUT1- 29 8 CK 17 1Ω

OUT1- 28 9 16 CD_OUT
N.C.
15 SVR
OUT2- 27 10 N.C.
14 CK
OUT2- 26 11 N.C. 13 DATA
PWGND 25 12 N.C. 12 SGND

PWGND 24 13 SVR 11 STT-BY

10 MUTE
A 23 14 CD-OUT
9 IN1-
VCC 22 15 1-OHM 8 IN1+
VCC 21 16 I2C-EN 7 VCC

OUT2+ 20 17 IN2- 6 OUT1-

5 N.C.
OUT2+ 19 18 IN2+
4 OUT1+
D01AU1270 3 B
2 PWGND
PowerSO36 (slug up)
1 TAB
D03IN1512

Flexiwatt27

Doc ID 14103 Rev 3 5/32

Electrical specifications TDA7575B

2 Electrical specifications

2.1 Absolute maximum ratings

Table 2. Absolute maximum ratings
Symbol Parameter Value Unit

Vop Operating supply voltage 18 V

VS DC supply voltage 28 V
Vpeak Peak supply voltage (for t = 50 ms) 50 V
VCK CK pin voltage 6 V
VDATA Data pin voltage 6 V
IO Output peak current (not repetitive t = 100 ms) 8 A
IO Output peak current (repetitive f > 10 Hz) 6 A
Ptot Power dissipation Tcase = 70 °C 86 W
Tstg, Tj Storage and junction temperature -55 to 150 °C

2.2 Thermal data

Table 3. Thermal data
Symbol Parameter PowerSO36 Flexiwatt 27 Unit

Rth j-case Thermal resistance junction-to-case Max 1 1 °C/W

2.3 Electrical characteristics

VS = 14.4 V; f = 1 kHz; RL = 4 ; Tamb= 25 °C unless otherwise specified.

Table 4. Electrical characteristics

Symbol Parameter Test condition Min. Typ. Max. Unit

Power amplifier

VS Supply voltage range - 8 - 18 V

Id Total quiescent drain current - 50 130 200 mA
(1)
Max. power 35 40 - W
THD = 10 % 25 28
- W
THD = 1 %; BTL mode 22
Po Output power
RL = 2 ; THD 10 % 45 50
RL = 2 ; THD 1 % 37 - W
RL = 2 ; Max. power(1) 70 75

6/32 Doc ID 14103 Rev 3

TDA7575B Electrical specifications

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Single channel configuration

(1  pin > 2.5 V); RL = 1 ;
Po Output power - W
THD 3 % 80 84
Max. power(1) 140 150
Po = 1-12 W; STD mode 0.03 0.1
HE mode; Po = 1-2 W - 0.03 0.1 %
HE mode; Po = 4-8 W 0.5
Po = 1-12 W, f = 10 kHz - 0.15 0.5 %
THD Total harmonic distortion
RL = 2; HE mode; Po = 3 W - 0.03 0.5 %
Single channel configuration
(1  pin > 2.5 V); RL = 1; - 0.02 0.1 %
Po = 4-30 W
CT Cross talk Rg = 600 Po = 1 W 60 75 - dB
RIN Input impedance - 60 100 130 k
GV1 Voltage gain 1 (default) - 25 26 27 dB
GV1 Voltage gain match 1 - -1 0 1 dB
GV2 Voltage gain 2 - 11 12 13 dB
GV2 Voltage gain match 2 - -1 0 1 dB
Rg = 600 ; Gv = 26 dB
EIN1 Output noise voltage gain 1 - 40 60 V
filter 20 to 22 kHz
Rg = 600 ; Gv = 12d B
EIN2 Output noise voltage gain 2 - 15 25 V
filter 20 to 22 kHz
f = 100 Hz to 10 kHz; Vr = 1 Vpk;
SVR Supply voltage rejection 50 60 - dB
Rg = 600 
BW Power bandwidth (-3 dB) 100 - - KHz
ASB Standby attenuation - 90 100 - dB
ISB Standby current consumption Vst-by = 0 V - 2 10 A
AM Mute attenuation - 80 90 dB
VOS Offset voltage Mute and play -45 0 45 mV
VAM Min. supply mute threshold - 7 7.5 8 V
CMRR Input CMRR VCM = 1 Vpk-pk; Rg = 0  56 60 dB
Maximum common mode input
VMC f = 1 kHz - - 1 Vrms
level
SR Slew rate - 1.5 4 - V/s
During mute on/off output offset
-10 - +10 mV
voltage ITU R-ARM weighted
VOS
During standby on/off output see Figure 23
-10 - +10 mV
offset voltage

Doc ID 14103 Rev 3 7/32

Electrical specifications TDA7575B

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

TON Turn on delay D2 (IB1) 0 to 1 - 15 40 ms

TOFF Turn off delay D2 (IB1) 1 to 0 - 15 40 ms
VOFF Standby pin for standby - 0 - 1.5 V
VSB Standby pin for standard bridge - 3.5 - 5 V
VHE Standby pin for high-efficiency - 7 - 18 V
Standby pin current 1.5 < Vst-by/HE < 18 V 7 160 200 A
IO
Standby pin current Vst-by < 1.5 V -10 0 10 A
Vm Mute pin voltage for mute mode - 0 - 1.5 V
Vm Mute pin voltage for play mode - 3.5 - 18 V
Im Mute pin current (standby) Vmute = 0 V, Vst-by < 1.5V -5 0 5 A
Im Mute pin current (operative) 0 V < Vmute < 18 V, Vst-by > 3.5 V - 65 100 A
VI2C I2C pin voltage for I2C disabled - 0 - 1.5 V
VI2C I2C pin voltage for I2C enabled - 2.5 - 18 V
I2C I2C pin current (standby) 0V < I2C EN < 18V, Vstby < 1.5V -5 0 5 A
I 2C
I2C pin current (operative) I2C EN <18V, Vst-by>3.5V 7 11 15 A
V1 1  pin voltage for 2ch mode - 0 - 1.5 V
V1 1  pin voltage for 1  mode - 2.5 - 18 V
I1 1  pin current (standby) 0 V < 1  <18 V, Vs-tby < 1.5 V -5 0 5 A
I1 1  pin current (operative) 1  < 18 V, Vst-by > 3.5 V 7 11 15 A
La Low logic level 0 - 1.5 V
A pin voltage
Ha High logic level 2.5 - 18 V
Ia A pin current (standby) 0V < A < 18V , Vstby < 1.5 V -5 0 5 A
Ia A pin current (operative) A<18V, Vst-by > 3.5V 7 11 15 A
Lb Low logic level 0 - 1.5 V
B pin voltage
Hb High logic level 2.5 - 18 V
Ib B pin current (standby) 0 V < B < 18 V, Vs-tby < 1.5 V -5 0 5 A
Ib B pin current (operative) B < 18 V, Vst-by > 3.5 V 7 11 15 A
TW Thermal warning - - 150 - °C
TPI Thermal protection intervention - - 170 - °C
ICDH Clip pin high leakage current CD off, 0 V < VCD < 5.5 V -15 0 15 A
ICDL Clip pin low sink current CD on; VCD < 300 mV 1 mA
D0 (IB1) = 0 0.8 1.3 2.5 %
CD Clip detect THD level
D0 (IB1) = 1 5 10 15 %

(*) Standby pin high enables I2C bus; Standby pin low puts the device in standby condition. (see “prog” for more details)

8/32 Doc ID 14103 Rev 3

TDA7575B Electrical specifications

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Turn-on diagnostics (Power amplifier mode)

Short to GND det. (below this
Power amplifier in standby
Pgnd limit, the output is considered in - - 1.2 V
condition
short circuit to GND)
Short to Vs det. (above this
Pvs limit, the output is considered in - Vs -0.9 - - V
short circuit to VS)
Normal operation
thresholds.(within these limits,
Pnop - 1.8 - Vs -1.5 V
the output is considered
without faults).
Lsc Shorted load det. - - - 0.5 
Lop Open load det. - 130 - - 
Lnop Normal load det. - 1.5 - 70 
Turn-on diagnostics (Line driver mode)
Short to GND det. (below this
Pgnd limit, the output is considered in - - 1.2 V
short circuit to GND)
Short to Vs det. (above this
Pvs limit, the Output is considered Vs -0.9 - - V
in Short Circuit to VS)
Normal operation Power amplifier in standby
thresholds.(within these limits,
Pnop 1.8 - Vs -1.5 V
the output is considered
without faults).
Lsc Shorted load det. - - 1.5 
Lop Open load det. 400 - - 
Lnop Normal load det. 4.5 - 200 
Permanent diagnostics (Power amplifier mode or line driver mode)
Short to GND det. (below this Power amplifier in Mute or Play
Pgnd limit, the output is considered in condition, one or more short - - 1.2 V
short circuit to GND) circuits protection activated
Short to Vs det. (above this
Vs -
Pvs limit, the Output is considered - - - V
0.9
in Short Circuit to VS)
Normal operation
thresholds.(Within these limits,
Pnop - 1.8 - Vs -1.5 V
the Output is considered
without faults).
Pow. amp. mode - - 0.5 
Lsc Shorted load det.
Line driver mode - - 1.5 

Doc ID 14103 Rev 3 9/32

Electrical specifications TDA7575B

Table 4. Electrical characteristics (continued)

Symbol Parameter Test condition Min. Typ. Max. Unit

Power amplifier in play condition

VO Offset detection ±1.5 ±2 ±2.5 V
AC input signals = 0
INLH Normal load current detection VO < (VS - 5)pk IB2 (D0) = 0 500 - - mA
INLL Normal load current detection VO < (VS - 5)pk IB2 (D0) = 1 250 - - mA
IOLH Open load current detection VO < (VS - 5)pk IB2 (D0) = 0 - - 250 mA
IOLL Open load current detection VO < (VS - 5)pk IB2 (D0) =1 - - 125 mA
2
I C bus interface
fSCL Clock frequency - - - 400 kHz
VIL Input low voltage - - - 1.5 V
VIH Input high voltage - 2.3 - - V
1. Saturated sqare wave output.

10/32 Doc ID 14103 Rev 3

TDA7575B Electrical characteristics curves

3 Electrical characteristics curves

Figure 3. Quiescent drain current vs. supply Figure 4. Output power vs. supply voltage
voltage

Id (mA) Po (W)
160 80
75
150 70 Po-max
140 Vi=0 65 RL=4 Ohm
NO LOADS 60 f=1 KHz
130 55
50
120 45 THD=10%
110 40
35
100 30
25
90 20 THD=1%
80 15
10
70 5
8 10 12 14 16 18 8 9 10 11 12 13 14 15 16 17 18
Vs (V) Vs (V)

Figure 5. Output power vs. supply voltage Figure 6. Output power vs. supply voltage

Po (W) Po (W)
130 130
120 120
Po-max Po-max
110 110
100 RL=2 Ohm 100 RL=2 Ohm
90 f=1 KHz 90 f=1 KHz
80 80
THD=10% THD=10%
70 70
60 60
50 50
40 THD=1% 40 THD=1%
30 30
20 20
10 10
0 0
8 9 10 11 12 13 14 15 16 17 18 8 9 10 11 12 13 14 15 16 17 18
Vs (V) Vs (V)

Figure 7. Distortion vs. output power Figure 8. Distortion vs. output power

THD (%) THD (%)

10 10
HI-EFF mode HI-EFF mode
Vs=14.4V Vs=14.4V
RL=4 Ohm RL=2 Ohm

1 1

f=10 KHz f=10 KHz

0.1 0.1

f=1 KHz f=1 KHz

0.01 0.01
0.1 1 10 100 0.1 1 10 100
Po (W)
Po (W)

Doc ID 14103 Rev 3 11/32

Electrical characteristics curves TDA7575B

Figure 9. Distortion vs. output power Figure 10. Distortion vs. output power

THD (%)
THD (%) 10
10
STD mode STD mode
Vs=14.4V Vs=14.4V
RL=4 Ohm 1 RL=2 Ohm
1
f=10 KHz
f=10 KHz
0.1 0.1

f=1 KHz f=1 KHz

0.01 0.01

0.001 0.001
0.1 1 10 100 0.1 1 10 100
Po (W) Po (W)

Figure 11. Distortion vs. output power Figure 12. Distortion vs. frequency

THD (%)
THD (%)
10 10
STD mode
Vs=14.4V Vs=14.4V
RL=1 Ohm STD mode
1
1Ω - 40W
1 2Ω - 24W
f=10 KHz 4Ω - 12W

0.1

0.1
f=1 KHz
0.01

0.01 0.001
0.1 1 10 100 10 100 1000 10000 100000
Po (W) f (Hz)

Figure 13. Distortion vs. output voltage Figure 14. Cross talk vs. frequency
(LD mode)

THD (%) CROSSTALK (dB)

10 -20
LD mode -30 STD mode
Vs=14.4V RL=2 Ohm
RL=100 Ohm -40 Rg=600 Ohm
1
-50
0.1 -60

f=10 KHz -70

0.01 -80
f=1 KHz -90
0.001 -100
0 1 2 3 4 5 6 7 8 9 10 11 12 10 100 1000 10000 100000
Vout f (Hz)

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TDA7575B Electrical characteristics curves

Figure 15. Cross talk vs. frequency Figure 16. CMRRR vs. frequency
(LD mode)

CROSSTALK (dB) CMRR (dB)

-20 -40
-30 LD mode
Vcm=1 Vpp
Vo=1 Vrms
-40 RL=100 Ohm
-50
-50
-60
-70
-60
-80
-90
-100 -70
10 100 1000 10000 100000 10 100 1000 10000 100000
f (Hz) f (Hz)

Figure 17. Output attenuation vs. supply Figure 18. Output attenuation vs. mute pin
voltage (vs. dependent muting) voltage

OUT ATTN (dB) OUT ATTN (dB)

20 20
0 dB=1 Vrms 0 dB=2 Vrms
0 0 RL=2 Ohm
RL=2 Ohm
-20
-20
-40
-40
-60
-60
-80
-80
-100

-120 -100
5 6 7 8 9 10 1 1.5 2 2.5 3 3.5 4
Vs (V) MUTE PIN V (V)

Figure 19. Power dissipation vs. output power Figure 20. Power dissipation vs. output power
(4 - SINE) (2 - SINE)

Ptot (W) Ptot (W)

35 60
Vs=14.4V Vs=14.4V
30 RL=2 x 4 Ohm 50 RL:=2 x 2 Ohm
f=1 KHz f=1 KHz
25
STD 40 STD
20
30
15
20
10
HI-EFF HI-EFF
5 10

0 0
0.1 1 10 100 0.1 1 10 100
Po (W) Po (W)

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Electrical characteristics curves TDA7575B

Figure 21. Power dissipation vs. average Figure 22. Power dissipation vs. average output
output power (Audio program power (Audio program simulation,
simulation, 4) 2)

Ptot (W) Ptot (W)

30
35
Vs=14 V Vs=14V
25 RL=2 x 4 30 RL=2 x 2 Ohm
GAUSSIAN NOISE GAUSSIAN NOISE STD

20 25
CLIP
CLIP
START START
20
15 HI-EFF
STD 15
10
10
5 HI-EFF 5

0 0
0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 10
Po (W) Po (W)

Figure 23. ITU R-ARM frequency response,

weighting filter for transient pop

Output attenuation (dB)

10

-10

-20

-30

-40

-50
10 100 1000 10000 100000
Hz AC00343

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TDA7575B Application circuits

4 Application circuits

Figure 24. Application circuit (TDA7575B)

I2C BUS VS CD_OUT

A B CLK DATA C7 C8 R1 47KΩ

0.1μF 2200μF V

VCC

25 3 14 13 7-21 16

C1 0.22μF
IN1+ 8
OUT1+
4
IN1- 9 6
OUT1-
C2 0.22μF

C3 0.22μF
OUT2+
IN2+ 20 24
22
OUT2-
IN2- 19
C4 0.22μF
I2C BUS
18
ENABLE
15 11 12 2-26 1 17 10

S_GND PW_GND TAB

C5 MUTE
10μF C6 R2 47KΩ
1μF
D05AU1615 ST-BY/HE 1Ω SETTING

Figure 25. Application circuit (TDA7575BPD)

I2C BUS VS CD_OUT

A B CLK DATA C7 C8 R1 47KΩ

0.1μF 2200μF V

VCC

23 32 8 7 21-2-33-34 14

C1 0.22μF
IN1+ 2
OUT1+
35-36
IN1- 3 28-29
OUT1-
C2 0.22μF

C3 0.22μF
OUT2+
IN2+ 18 19-20
26-29
OUT2-
IN2- 17
C4 0.22μF
I2C BUS
16
ENABLE
13 5 6 24-25-30-31 1 15 4

S_GND PW_GND TAB

C5 MUTE
10μF C6 R2 47KΩ
1μF
D05AU1616 ST-BY/HE 1Ω SETTING

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I2C bus interface TDA7575B

5 I2C bus interface

Data transmission from microprocessor to the TDA7575B and vice versa takes place
through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up
resistors to positive supply voltage must be connected).

5.1 Data validity

As shown by Figure 26, the data on the SDA line must be stable during the high period of
the clock.
The high and low state of the data line can only change when the clock signal on the SCL
line is low.

5.2 Start and stop conditions

As shown by Figure 27 a start condition is a high to low transition of the SDA line while SCL
is high.
The stop condItion Is A Low To High Transition of the SDA line while SCL is high.

5.3 Byte format

Every byte transferred to the SDA line must contain 8 bits. Each byte must be followed by an
acknowledge bit. The MSB is transferred first.

5.4 Acknowledge
The transmitter(*) puts a resistive HIGH level on the SDA line during the acknowledge clock
pulse (see Figure 28). The receiver(**) the acknowledges has to pull-down (LOW) the SDA
line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock
pulse.
(*) Transmitter
= master (P) when it writes an address to the TDA7575B
= slave (TDA7575B) when the µP reads a data byte from TDA7575B
(**) Receiver
= slave (TDA7575B) when the µP writes an address to the TDA7575B
= master (P) when it reads a data byte from TDA7575B

Figure 26. Data validity on the I2C bus

SDA

SCL

DATA LINE CHANGE

STABLE, DATA DATA
VALID ALLOWED D99AU1031

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TDA7575B I2C bus interface

Figure 27. Timing diagram on the I2C bus

SCL

I2CBUS

SDA

D99AU1032
START STOP

Figure 28. Timing acknowledge clock pulse

SCL 1 2 3 7 8 9

SDA
MSB
ACKNOWLEDGMENT
START D99AU1033 FROM RECEIVER

5.5 1  capability setting

It is possible to drive 1 load paralleling the outputs into a single channel.
In order to implement this feature, outputs are to be connected on the board as follows:
● OUT1+ (pin 35 and pin 36) shorted to OUT2+ (pin 19 and pin 20)
● OUT1- (pin 28 and pin 29) shorted to OUT2- (pin 26 and pin 27).
It is recommended to minimize the impedance on the board between OUT2 and the load in
order to minimize THD distortion. It is also recommended to control the maximum mismatch
impedance between VCC pins (pin 21/pin 22 respect to pin 33/pin 34) and between PWGND
pins (pin 24/pin 25 respect to pin 30/pin 31), mismatch that must not exceed a value of
20 m
With 1  feature settled the active input is IN2 (pin 17 and pin 18), therefore IN1 pins should
be let floating.
It is possible to set the load capability acting on 1  pin as follows:
1  pin (pin 15) < 1.5 V: two channels mode (for a minimum load of 2 )
1  pin (pin 15) > 2.5 V: one channel mode (for 1  load).
It is to remember that 1
Ohmfunction is a hardware selection.
Therefore it is recommended to leave 1pin floating or shorted to GND to set the two
channels mode configuration, or to short 1 pin to VCC to set the one channel (1)
configuration.

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I2C bus interface TDA7575B

5.6 I2C abilitation setting

It is possible to disable the I2C interface by acting on I2C pin (pin 16) and control the
TDA7575B by means of the usual standby and mute pins. In order to activate or deactivate
this feature, I2C pin must be set as follows:
● I2C pin (pin 16) < 1.5V: I2C bus interface deactivated
● I2C pin (pin 16) > 2.5V: I2C bus interface activated
It is also possible to let I2C pin floating to deactivate the I2C bus interface, or to short I2C pin
to VCC to activate it.
In particular:
● I2C enabled: I2C pin (pin 16) > 2.5 V
– STD mode: Vst-by (pin 5) > 3.5 V, IB2(D1)=0
– HE mode: Vst-by (pin 5) > 3.5 V, IB2(D1)=1
– Play mode: Vmute (pin 4) >3.5 V, IB1 (D2) = 1
The amplifier can always be switched off by putting Vst-by to 0V , but with I2C enabled it can
be turn on only through I2C (with Vst-by > 3.5 V).
● I2C disabled: I2C pin (pin 16) < 1.5 V
– STD mode: 3.5V < standby (pin 5) < 5
– HE mode: Vstby (pin 5) > 7 V
– Play mode: Vmute (pin 4) > 3.5 V
For both STD and HE mode the play/mute mode can be set acting on Vmute pin.
When I2C bus is disabled, when a fault is detected pin 14 (CD-OUT) is pulled down by the
internal logic circuitry. The faults detected are the short circuit to ground, to VCC and across
the load (after an aver current detection).

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TDA7575B Software specifications

6 Software specifications

All the functions of the TDA7575B are activated by I2C interface.

The bit 0 of the "Address Byte" defines if the next bytes are write instruction (from P to
TDA7575B) or read instruction (from TDA7575B to µP).

Table 5. Address selection

Bit Address

A6 1
A5 1
A4 0
A3 1
A2 0
A1 B
A0 A
R/W X

If R/W = 0, the P sends 2 "instruction bytes": IB1 and IB2.

Table 6. IB1
Bit Instruction decoding bit

D7 0
Diagnostic enable (D6 = 1)
D6
Diagnostic defeat (D6 = 0)
Offset detection enable (D5 = 1)
D5
Offset detection defeat (D5 = 0)
Gain = 26 dB (D4 = 0)
D4
Gain = 12 dB (D4 = 1)
D3 0
Mute (D2 = 0)
D2
Unmute (D2 = 1)
D1 0
CD 2% (D0 = 0)
D0
CD 10% (D0 = 1)

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Software specifications TDA7575B

Table 7. IB2
Bit Instruction decoding bit

D7 0
D6 0
D5 0
Standby on - Amplifier not working - (D4 = 0)
D4
Standby off - Amplifier working - (D4 = 1)
Power amplifier mode diagnostic (D3 = 0);
D3
Line driver mode diagnostic (D3 = 1)
Current detection diagnostic enabled (D2 = 1)
D2
Current detection diagnostic defeat (D2 = 0)
Power amplifier working in standard mode (D1 = 0)
D1
Power amplifier working in high efficiency mode (D1 = 1)
Current detection threshold high (D7 =0)
D0
Current detection threshold low (D7 =1)

If R/W = 1, the TDA7575B sends 2 "Diagnostics Bytes" to P: DB1 and DB2.

Table 8. DB1
Bit Instruction decoding bit
D7 Thermal warming (if Tchip  150°C, D7 = 1)
Diag. cycle not activated or not terminated (D6 = 0)
D6
Diag. cycle terminated (D6 = 1)
Channel 1 Channel LF
current detection IB2 (D0) = 0 current detection IB2 (D0) = 1
D5
Output peak current < 250 mA - Open load (D5 = 1) Output peak current < 125 mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0) Output peak current > 250 mA - Normal load (D5 = 0)
Channel 1
D4 Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
Channel 1
D3 Normal load (D3 = 0)
Short load (D3 = 1)
Channel 1
Turn-on diag.: No open load (D2 = 0)
D2 Open load detection (D2 = 1)
Offset diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
Channel 1
D1 No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
Channel 1
D0 No short to GND (D1 = 0)
Short to GND (D1 = 1)

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TDA7575B Software specifications

Table 9. DB2
Bit Instruction decoding bit

Offset detection not activated (D7 = 0)

D7
Offset detection activated (D7 = 1)
Current sensor not activated (D6 = 0)
D6
Current sensor activated (D6 = 1)
Channel LR Channel LR
Current detection IB2 (D0) = 0 Current detection IB2 (D0) = 1
D5
Output peak current < 250 mA - Open load (D5 = 1) Output peak current < TBD mA - Open load (D5 = 1)
Output peak current > 500 mA - Normal load (D5 = 0) Output peak current > TBD mA - Normal load (D5 = 0)
Channel 2
D4 Turn-on diagnostic (D4 = 0)
Permanent diagnostic (D4 = 1)
Channel 2
D3 Normal load (D3 = 0)
Short load (D3 = 1)
Channel 2
Turn-on diag.: No open load (D2 = 0)
D2 Open load detection (D2 = 1)
Permanent diag.: No output offset (D2 = 0)
Output offset detection (D2 = 1)
Channel 2
D1 No short to Vcc (D1 = 0)
Short to Vcc (D1 = 1)
Channel 2
D0 No short to GND (D1 = 0)
Short to GND (D1 = 1)

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Software specifications TDA7575B

6.1 Examples of bytes sequence

1 - Turn-on diagnostic - Write operation
Start Address byte with D0 = 0 ACK IB1 with D6 = 1 ACK IB2 ACK STOP

2 - Turn-on diagnostic - Read operation

Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK STOP

The delay from 1 to 2 can be selected by software, starting from T.B.D. ms

3a - Turn-on of the power amplifier with mute on, diagnostic defeat.

Start Address byte with D0 = 0 ACK IB1 ACK IB2 ACK STOP
X000XXXX XXX1XX1X

3b - Turn-off of the power amplifier

Start Address byte with D0 = 0 ACK IB1 ACK IB2 ACK STOP
X0XXXXXX XXX0XXXX

4 - Offset detection procedure enable

Start Address byte with D0 = 0 ACK IB1 ACK IB2 ACK STOP
XX1XX1XX XXX1XXXX

5 - Offset detection procedure stop and reading operation (the results are valid only for the
offset detection bits (D2 of the bytes DB1, DB2, DB3, DB4).
Start Address byte with D0 = 1 ACK DB1 ACK DB2 ACK STOP

● The purpose of this test is to check if a D.C. offset (2 V typ.) is present on the outputs,
produced by input capacitor with anomalous leakage current or humidity between pins.
● The delay from 4 to 5 can be selected by software, starting from T.B.D. ms

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TDA7575B Diagnostics functional description

7 Diagnostics functional description

7.1 Turn-on diagnostic

It is activated at the turn-on (stand-by out) under I2C bus request. Detectable output faults are:
– Short to GND
– Short TO Vs
– Short across the speaker
– Open speaker
To verify if any of the above misconnections are in place, a subsonic (inaudible) current
pulse (Figure 29) is internally generated, sent through the speaker(s) and sunk back. The
Turn On diagnostic status is internally stored until a successive diagnostic pulse is
requested (after a I2C reading).
If the "stand-by out" and "diag. enable" commands are both given through a single
programming step, the pulse takes place first (power stage still in stand-by mode, low,
outputs = high impedance).
Afterwards, when the Amplifier is biased, the PERMANENT diagnostic takes place. The
previous Turn On state is kept until a short appears at the outputs.

Figure 29. Turn-on diagnostic: working principle

Vs~5V I (mA)

Isource Isource

Isink
CH+
CH-

Isink
~100mS t (ms)
Measure time

Fig. Figure 30 and Figure 31 show SVR and OUTPUT waveforms at the turn-on (stand-by
out) with and without Turn-on diagnostic.

Figure 30. SVR and output behavior - case 1: without turn-on diagnostic

Vsvr
Out
Permanent diagnostic
acquisition time (100mS Typ)

Diagnostic Enable t
Bias (power amp turn-on)
(Permanent) FAULT
event Read Data

I2CB DATA Permanent Diagnostics data (output)

permitted time

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Diagnostics functional description TDA7575B

Figure 31. SVR and output pin behavior - case 2: with turn-on diagnostic

Vsvr
Out Turn-on diagnostic
Permanent diagnostic
acquisition time (100mS Typ)
acquisition time (100mS Typ)

t
Diagnostic Enable Turn-on Diagnostics data (output) FAULT
Diagnostic Enable
(Turn-on) permitted time
(Permanent) event

Bias (power amp turn-on) Read Data Permanent Diagnostics data (output)
I2CB DATA
permitted time permitted time

The information related to the outputs status is read and memorized at the end of the
current pulse top. The acquisition time is 100 ms (typ.). No audible noise is generated in the
process. As for short to GND / Vs the fault-detection thresholds remain unchanged from 26
dB to 12 dB gain setting. They are as follows:

Figure 32. Short circuit detection thresholds

S.C. to GND x Normal Operation x S.C. to Vs

0V 1.2V 1.8V VS-1.5V VS-0.9V VS

D02AU1341

Concerning short across the speaker / open speaker, the threshold varies from 26 dB to 12
dB gain setting, since different loads are expected (either normal speaker's impedance or
high impedance). The values in case of 26 dB gain are as follows:

Figure 33. Load detection thresholds - high gain setting

S.C. across Load x Normal Operation x Open Load

0V 0.5Ω 1.5Ω 70Ω 130Ω Infinite

D01AU1254

If the line-driver mode (Gv= 12 dB and line driver mode diagnostic = 1) is selected, the same
thresholds will change as follows:

Figure 34. Load detection thresholds - high gain setting

S.C. across Load x Normal Operation x Open Load

0Ω 1.5Ω 4.5Ω 200Ω 400Ω infinite

D01AU1252

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TDA7575B Diagnostics functional description

7.2 Permanent diagnostics

Detectable conventional faults are:
– Short to GND
– Short to Vs
– Short across the speaker
The following additional features are provided:
– Output offset detection
The TDA7575B has 2 operating statuses:
1. RESTART mode. The diagnostic is not enabled. Each audio channel operates
independently from each other. If any of the a.m. faults occurs, only the channel(s)
interested is shut down. A check of the output status is made every 1 ms (fig. 30).
Restart takes place when the overload is removed.
2. DIAGNOSTIC mode. It is enabled via I2C bus and self activates if an output overload
(such to cause the intervention of the short-circuit protection) occurs to the speakers
outputs. Once activated, the diagnostics procedure develops as follows (fig. 31):
– To avoid momentary re-circulation spikes from giving erroneous diagnostics, a
check of the output status is made after 1ms: if normal situation (no overloads) is
detected, the diagnostic is not performed and the channel returns back active.
– Instead, if an overload is detected during the check after 1 ms, then a diagnostic
cycle having a duration of about 100 ms is started.
– After a diagnostic cycle, the audio channel interested by the fault is switched to
RESTART mode. The relevant data are stored inside the device and can be read
by the microprocessor. When one cycle has terminated, the next one is activated
by an I2C reading. This is to ensure continuous diagnostics throughout the car-
radio operating time.
– To check the status of the device a sampling system is needed. The timing is
chosen at microprocessor level (over than half a second is recommended).

Figure 35. Restart timing without diagnostic enable (permanent)

each 1ms time, a sampling of the fault is done
Out
1-2mS 1mS 1mS 1mS 1mS

t
Overcurrent and short
circuit protection intervention Short circuit removed
(i.e. short circuit to GND)

Figure 36. Restart timing with diagnostic enable (permanent)

1mS 100mS 1mS 1mS

t
Overcurrent and short
circuit protection intervention Short circuit removed
(i.e. short circuit to GND)

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Diagnostics functional description TDA7575B

7.3 Output DC offset detection

Any DC output offset exceeding ± 2 V are signalled out. This inconvenient might occur as a
consequence of initially defective or aged and worn-out input capacitors feeding a DC
component to the inputs, so putting the speakers at risk of overheating.
This diagnostic has to be performed with low-level output AC signal (or Vin = 0).
The test is run with selectable time duration by microprocessor (from a "start" to a "stop"
command):
● Start = Last reading operation or setting IB1 - D5 - (OFFSET enable) to 1
● Stop = Actual reading operation
Excess offset is signalled out if persistent throughout the assigned testing time. This feature
is disabled if any overloads leading to activation of the short-circuit protection occurs in the
process.

7.4 AC diagnostic
It is targeted at detecting accidental disconnection of tweeters in 2-way speaker and, more
in general, presence of capacitively (AC) coupled loads.
This diagnostic is based on the notion that the overall speaker's impedance (woofer +
parallel tweeter) will tend to increase towards high frequencies if the tweeter gets
disconnected, because the remaining speaker (woofer) would be out of its operating range
(high impedance). The diagnostic decision is made according to peak output current
thresholds, and it is enabled by setting (IB2-D2) = 1. Two different detection levels are
available:
● HIgh current threshold IB2 (D7) = 0
– Iout > 500 mApk = normal status
– Iout < 250 mApk = open tweeter
● Low current threshold IB2 (D7) = 1
– Iout > 250 mApk = normal status
– Iout < 125 mApk = open tweeter
To correctly implement this feature, it is necessary to briefly provide a signal tone (with the
amplifier in "play") whose frequency and magnitude are such to determine an output current
higher than 500mApk with IB2(D7)=0 (higher than 250mApk with IB2(D7)=1) in normal
conditions and lower than 250 mApk with IB2(D7)=0 (lower than 125 mApk with IB2(D7)=1)
should the parallel tweeter be missing.
The test has to last for a minimum number of 3 sine cycles starting from the activation of the
AC diagnostic function IB2<D2>) up to the I2C reading of the results (measuring period). To
confirm presence of tweeter, it is necessary to find at least 3 current pulses over the above
threholds over all the measuring period, else an "open tweeter" message will be issued.
The frequency / magnitude setting of the test tone depends on the impedance
characteristics of each specific speaker being used, with or without the tweeter connected
(to be calculated case by case). High-frequency tones (> 10 kHz) or even ultrasonic signals
are recommended for their negligible acoustic impact and also to maximize the impedance
module's ratio between with tweeter-on and tweeter-off.

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TDA7575B Diagnostics functional description

Figure 37 shows the load impedance as a function of the peak output voltage and the
relevant diagnostic fields.
This feature is disabled if any overloads leading to activation of the short-circuit protection
occurs in the process.

Figure 37. Current detection high: load impedance |Z| vs. output peak voltage
Load |z| (Ohm)
50
Iout (peak) <250mA
Low current detection area
30
(Open load) Iout (peak) >500mA

20 D5 = 1 of the DBx byres

10
IB2(D0) = 0
High current detection area
5
(Normal load)
D5 = 0 of the DBx bytes
3

1
1 2 3 4 5 6 7 8
Vout (Peak)

Figure 38. Current detection low: load impedance |Z| vs. output peak voltage
Load |z| (Ohm)
50
Iout (peak) <125mA
Low current detection area
30
(Open load) Iout (peak) >250mA

20 D5 = 1 of the DBx byres

10
IB2(D0) = 1

High current detection area

5
(Normal load)
D5 = 0 of the DBx bytes
3

1
0.5 1 1.5 2 2.5 3 3.5 4
Vout (Peak)

7.5 Multiple faults

When more misconnections are simultaneously in place at the audio outputs, it is
guaranteed that at least one of them is initially read out. The others are notified after
successive cycles of I2C reading and faults removal, provided that the diagnostic is enabled.
This is true for both kinds of diagnostic (turn-on and permanent).
The table below shows all the couples of double-fault possible. It should be taken into
account that a short circuit with the 4  speaker unconnected is considered as double fault.

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Diagnostics functional description TDA7575B

Table 10. Double fault table for turn-on diagnostic

S. GND (sc) S. GND (sk) S. Vs S. Across L. Open L.
S. Vs + S.
S. GND (sc) S. GND S. GND S. GND S. GND
GND
S. GND (sk) / S. GND S. Vs S. GND Open L. (*)

S. Vs / / S. Vs S. Vs S. Vs

S. Across L. / / / S. Across L. N.A.

Open L. / / / / Open L. (*)

S. GND (so) / S. GND (sk) in the above table make a distinction according to which of the 2
outputs is shorted to ground (test-current source side= so, test-current sink side = sk). More
precisely, in both the channels SO = CH+, and SK = CH-.
In permanent diagnostic the table is the same, with only a difference concerning open load
(*), which is not among the recognizable faults. Should an open load be present during the
device's normal working, it would be detected at a subsequent turn-on diagnostic cycle (i.e.
at the successive car radio turn-on).

7.6 Faults availability

All the results coming from I2C bus, by read operations, are the consequence of
measurements inside a defined period of time. If the fault is stable throughout the whole
period, it will be sent out. This is true for DC diagnostic (turn-on and permanent), for offset
detector.
To guarantee always resident functions, every kind of diagnostic cycles (turn-on, permanent,
offset) will be reactivate after any I2C reading operation. So, when the micro reads the I2C, a
new cycle will be able to start, but the read data will come from the previous diag. cycle (i.e.
The device is in turn-on state, with a short to GND, then the short is removed and micro
reads I2C. The short to GND is still present in bytes, because it is the result of the previous
cycle. If another I2C reading operation occurs, the bytes do not show the short). In general
to observe a change in diagnostic bytes, two I2C reading operations are necessary.

7.7 I2C programming/reading sequences

A correct turn on/off sequence respectful of the diagnostic timings and producing no audible
noises could be as follows (after battery connection):
● Turn-on: (Standby OUT + DIAG enable) --- 500 ms (min) --- muting OUT
● Turn-off: Muting IN --- 20 ms --- (DIAG disable + standby IN)
Car radio installation: DIAG enable (write) --- 20 0ms --- I2C read (repeat until all faults
disappear).
– Offset test: device in play (no signal)
– Offset enable - 30 ms - I2C reading
(repeat I2C reading until high-offset message disappears).

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TDA7575B Package information

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

Figure 39. PowerSO36 (slug up) mechanical data and package dimensions
mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND
A 3.270 - 3.410 0.1287 - 0.1343 MECHANICAL DATA
A2 3.100 - 3.180 0.1220 - 0.1252
A4 0.800 - 1.000 0.0315 - 0.0394
A5 - 0.200 - - 0.0079 -
a1 0.030 - -0.040 0.0012 - -0.0016
b 0.220 - 0.380 0.0087 - 0.0150
c 0.230 - 0.320 0.0091 - 0.0126
D 15.800 - 16.000 0.6220 - 0.6299
D1 9.400 - 9.800 0.3701 - 0.3858
D2 - 1.000 - - 0.0394 -
E 13.900 - 14.500 0.5472 - 0.5709
E1 10.900 - 11.100 0.4291 - 0.4370
E2 - - 2.900 - - 0.1142
E3 5.800 - 6.200 0.2283 - 0.2441
E4 2.900 - 3.200 0.1142 - 0.1260
e - 0.650 - - 0.0256 -
e3 - 11.050 - - 0.4350 -
G 0 - 0.075 0 - 0.0031
H 15.500 - 15.900 0.6102 - 0.6260
h - - 1.100 - - 0.0433
L 0.800 - 1.100 0.0315 - 0.0433
N - - 10˚ - - 10˚
s - - 8˚ - - 8˚
PowerSO36 (SLUG UP)
(1) “D and E1” do not include mold flash or protusions.
Mold flash or protusions shall not exceed 0.15mm (0.006”).
(2) No intrusion allowed inwards the leads.

7183931 G

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Package information TDA7575B

Figure 40. Flexiwatt27 (vertical) mechanical data and package dimensions

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.45 4.50 4.65 0.175 0.177 0.183 OUTLINE AND
B 1.80 1.90 2.00 0.070 0.074 0.079 MECHANICAL DATA
C 1.40 0.055
D 0.75 0.90 1.05 0.029 0.035 0.041
E 0.37 0.39 0.42 0.014 0.015 0.016
F (1) 0.57 0.022
G 0.80 1.00 1.20 0.031 0.040 0.047
G1 25.75 26.00 26.25 1.014 1.023 1.033
H (2) 28.90 29.23 29.30 1.139 1.150 1.153
H1 17.00 0.669
H2 12.80 0.503
H3 0.80 0.031
L (2) 22.07 22.47 22.87 0.869 0.884 0.904
L1 18.57 18.97 19.37 0.731 0.747 0.762
L2 (2) 15.50 15.70 15.90 0.610 0.618 0.626
L3 7.70 7.85 7.95 0.303 0.309 0.313
L4 5 0.197
L5 3.5 0.138
M 3.70 4.00 4.30 0.145 0.157 0.169
M1 3.60 4.00 4.40 0.142 0.157 0.173
N 2.20 0.086
O 2 0.079
R 1.70 0.067
R1 0.5 0.02
R2 0.3 0.12
R3 1.25 0.049
R4 0.50 0.019
V 5˚ (Typ.)
V1 3˚ (Typ.) Flexiwatt27 (vertical)
V2 20˚ (Typ.)
V3 45˚ (Typ.)
(1): dam-bar protusion not included
(2): molding protusion included

V
C

B
V
H
H1
V3
H2 A
H3
O

R3

R4
L4

V1
R2
N
L2

R
L L1
V1
L3

V2

R2 D
R1

L5 R1 R1
Pin 1
E
G G1 F
FLEX27ME
M M1

7139011

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TDA7575B Revision history

9 Revision history

Table 11. Document revision history

Date Revision Changes

30-Oct-2007 1 Initial release.

Updated Figure 39: PowerSO36 (slug up) mechanical data and
17-Dec-2009 2
package dimensions on page 29.
17-Sep-2013 3 Updated Disclaimer.

Doc ID 14103 Rev 3 31/32

 TDA7575B

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