CD4510BMS, CD4516BMS

Data Sheet December 1992 File Number 3338

CMOS Presettable Up/Down Counters Features

CD4510BMS Presettable BCD Up/Down Counter and the • High Voltage Types (20V Rating)
CD4516BMS Presettable Binary Up/Down counter consist of • CD4510BMS - BCD Type
four synchronously clocked D-type flip-flops (with a gating
structure to provide T-type flip-flop capability) connected as • CD4516BMS - Binary Type
counters. These counters can be cleared by a high level on • Medium Speed Operation
the RESET line, and can be preset to any binary number - fCL = 8MHz Typ. at 10V
present on the jam inputs by a high level on the PRESET
ENABLE line. The CD4510BMS will count out of non-BCD • Synchronous Internal Carry Propagation
counter states in a maximum of two clock pulses in the up • Reset and Preset Capability
mode, and a maximum of four clock pulses in the down mode.
• 100% Tested for Quiescent Current at 20V
If the CARRY IN input is held low, the counter advances up or
down on each positive-going clock transition. Synchronous • 5V, 10V and 15V Parametric Ratings
cascading is accomplished by connecting all clock inputs in • Standardized Symmetrical Output Characteristics
parallel and connecting the CARRY OUT of a less significant
stage to the CARRY IN of a more significant stage. • Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
The CD4510BMS and CD4516BMS can be cascaded in the
• Noise Margin (Over Full Package/Temperature Range)
ripple mode by connecting the CARRY OUT to the clock of
the next stage. If the UP/DOWN input changes during a ter- - 1V at VDD = 5V
minal count, the CARRY OUT must be gated with the clock, - 2V at VDD = 10V
and the UP/DOWN input must change while the clock is - 2.5V at VDD = 15V
high. This method provides a clean clock signal to the sub-
• Meets All Requirements of JEDEC Tentative Standard
sequent counting stage. (See Figures 13, 14.)
No. 13B, “Standard Specifications for Description of
These devices are similar to types MC14510 and MC14516. ‘B’ Series CMOS Devices”
The CD4510BMS and CD4516BMS are supplied in these Applications
16-lead outline packages:
• Up/Down Difference Counting
Braze Seal DIP *H4W †H45
• Multistage Synchronous Counting
Frit Seal DIP *FBF †H1F
Ceramic Flatpack H6W • Multistage Ripple Counting
*CD4510B Only †CD4516B Only • Synchronous Frequency Dividers

Pinout Functional Diagram

CD4510BMS, CD4516BMS PRESET ENABLE
TOP VIEW
1

4 6
PRESET ENABLE 1 16 VDD P1 Q1
12 11
P2 Q2
Q4 2 15 CLOCK 13 14
P3 Q3
3 2
P4 3 14 Q3 P4 Q4
P1 4 13 P3

CARRY IN 5 12 P2

Q1 6 11 Q2 15
CLOCK
CARRY OUT 7 10 UP/DOWN 10
UP/DOWN
5 7
VSS 8 9 RESET CARRY IN CARRY OUT

9 VDD = 16
RESET VSS = 8

1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
 CD4510BMS, CD4516BMS

Absolute Maximum Ratings Reliability Information

DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . . -0.5V to +20V Thermal Resistance. . . . . . . . . . . . . . . . θja θjc
(Voltage Referenced to VSS Terminals) Ceramic DIP and FRIT Package . . . . 80oC/W 20oC/W
Input Voltage Range, All Inputs . . . . . . . . . . . . . -0.5V to VDD +0.5V Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . . . .±10mA Maximum Package Power Dissipation (PD) at +125oC
Operating Temperature Range . . . . . . . . . . . . . . . -55oC to +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . .500mW
Package Types D, F, K, H For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC Linearity at 12mW/oC to 200mW
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC Device Dissipation per Output Transistor. . . . . . . . . . . . . . . .100mW
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for For TA = Full Package Temperature Range (All Package Types)
10s Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+175oC

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1) SUBGROUPS TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC - 10 µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC - 10 µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
(Note 2)
Input Voltage High VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
(Note 2)
Input Voltage Low VIL VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC - 4 V
(Note 2) VOL < 1.5V
Input Voltage High VIH VDD = 15V, VOH > 13.5V, 1, 2, 3 +25oC, +125oC, -55oC 11 - V
(Note 2) VOL < 1.5V
NOTES: 1. All voltages referenced to device GND, 100% testing being im- 3. For accuracy, voltage is measured differentially to VDD. Limit is
plemented. 0.050V max.
2. Go/No Go test with limits applied to inputs.

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 CD4510BMS, CD4516BMS

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
GROUP A
PARAMETER SYMBOL CONDITIONS (NOTE 1, 2) SUBGROUPS TEMPERATURE MIN MAX UNITS
Propagation Delay TPHL1 VDD = 5V, VIN = VDD or GND 9 +25oC - 400 ns
Clock to Q Output TPLH1
10, 11 +125oC, -55oC - 540 ns
Propagation Delay TPHL2 VDD = 5V, VIN = VDD or GND 9 +25oC - 420 ns
Preset or Reset to Q TPLH2
10, 11 +125oC, -55oC - 567 ns
Propagation Delay TPHL3 VDD = 5V, VIN = VDD or GND 9 +25oC - 480 ns
Clock to Carry Out TPLH3
10, 11 +125oC, -55oC - 648 ns
Propagation Delay TPHL4 VDD = 5V, VIN = VDD or GND 9 +25oC - 250 ns
Carry In to Carry Out TPLH4
10, 11 +125oC, -55oC - 338 ns
Propagation Delay TPHL5 VDD = 5V, VIN = VDD or GND 9 +25oC - 640 ns
Preset or Reset to Carry TPLH5 (Note 3)
10, 11 +125oC, -55oC - 864 ns
Out
Transition Time TTHL VDD = 5V, VIN = VDD or GND 9 +25oC - 200 ns
TTLH
10, 11 +125oC, -55oC - 270 ns
Maximum Clock Input Fre- FCL VDD = 5V, VIN = VDD or GND 9 +25oC 2 - MHz
quency
10, 11 +125oC, -55oC 1.48 - MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. Reset to Carry Out (TPLH) only.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC - 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC - 10 µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC, - - 50 mV
55oC
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, - - 50 mV
55oC
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, - 4.95 - V
55oC
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, - 9.95 - V
55oC
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA

3
 CD4510BMS, CD4516BMS

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.15 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -1.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC - -4.2 mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - - 3 V
55oC
Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, - +7 - V
55oC
Propagation Delay TPHL1 VDD = 10V 1, 2, 3 +25oC - 200 ns
Clock to Q Output TPLH1
VDD = 15V 1, 2, 3 +25oC - 150 ns
Propagation Delay TPHL2 VDD = 10V 1, 2, 3 +25oC - 210 ns
Preset or Reset to Q TPLH2
VDD = 15V 1, 2, 3 +25oC - 160 ns
Propagation Delay TPHL3 VDD = 10V 1, 2, 3 +25oC - 240 ns
Clock to Carry Out TPLH3
VDD = 15V 1, 2, 3 +25oC - 180 ns
Propagation Delay TPHL4 VDD = 10V 1, 2, 3 +25oC - 120 ns
Carry In to Carry Out TPLH4
VDD = 15V 1, 2, 3 +25oC - 100 ns
Propagation Delay Preset TPHL5 VDD = 10V 1, 2, 3, 4 +25oC - 320 ns
or Reset to Carry Out TPLH5
VDD = 15V 1, 2, 3, 4 +25oC - 250 ns
Transition Time TTLH VDD = 10V 1, 2, 3 +25oC - 100 ns
TTHL
VDD = 15V 1, 2, 3 +25oC - 80 ns
Maximum Clock Input Fre- FCL VDD = 10V 1, 2 +25oC 4 - MHz
quency
VDD = 15V 1, 2 +25oC 5.5 - MHz
Minimum Hold Time TH VDD = 5V 1, 2, 3 +25oC - 70 ns
Preset Enable to JN
VDD = 10V 1, 2, 3 +25oC - 40 ns
VDD = 15V 1, 2, 3 +25oC - 40 ns
Minimum Data Setup Time TS VDD = 5V 1, 2, 3 +25oC - 25 ns
Preset Enable to JN
VDD = 10V 1, 2, 3 +25oC - 10 ns
VDD = 15V 1, 2, 3 +25oC - 10 ns
Minimum Data Hold Time TH VDD = 5V 1, 2, 3 +25oC - 60 ns
Clock to Carry In
VDD = 10V 1, 2, 3 +25oC - 30 ns
VDD = 15V 1, 2, 3 +25oC - 30 ns
Minimum Clock Hold Time TH VDD = 5V 1, 2, 3 +25oC - 30 ns
Clock to Up/Down
VDD = 10V 1, 2, 3 +25oC - 30 ns
VDD = 15V 1, 2, 3 +25oC - 30 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial
design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. Reset to Carry Out (TPLH) only.

4
 CD4510BMS, CD4516BMS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS

LIMITS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC - ±1 V
Delta
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V
Delta
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH > VOL < V
VDD/2 VDD/2
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x ns
TPLH +25oC
Limit
NOTES: 1. All voltages referenced to device GND. 3. See Table 2 for +25oC limit.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC

PARAMETER SYMBOL DELTA LIMIT

Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading

TABLE 6. APPLICABLE SUBGROUPS

MIL-STD-883
CONFORMANCE GROUP METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.

TABLE 7. TOTAL DOSE IRRADIATION

TEST READ AND RECORD

MIL-STD-883
CONFORMANCE GROUPS METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4

5
 CD4510BMS, CD4516BMS

TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

OSCILLATOR
FUNCTION OPEN GROUND VDD 9V ± -0.5V 50kHz 25kHz
CD4510BMS
Static Burn-In 1 2, 6, 7, 11, 14 1, 3-5, 8-10, 12, 13, 16
(Note 1) 15
Static Burn-In 2 2, 6, 7, 11, 14 8 1, 3-5, 9, 10, 12, 13,
(Note 1) 15, 16
Dynamic Burn- - 1, 3, 4, 8, 9, 12, 13 10, 16 2, 6, 7, 11, 14 15 5
In (Note 1)
Irradiation 2, 6, 7, 11, 14 8 1, 3-5, 9, 10, 12, 13,
(Note 2) 15, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
VDD = 10V ± 0.5V

Logic Diagrams

P1* Q1 P2* Q2 P3* Q3 P4* Q4

4 6 12 11 13 14 3 2
9
RESET*

1
PRESET*
ENABLE

15 P P P P
CLOCK*
PE Q PE Q PE Q PE Q
7
CARRY OUT C C C C

T Q T Q T Q T Q

Q1 Q2 Q2 Q3 Q3 Q4 Q4

5
CARRY IN*

10 U/D
UP/DOWN*
U/D

Q1
VDD U/D U/D Q3 U/D Q3 U/D U/D U/D Q3 Q2 Q3
Q4 Q2 Q4 Q2 Q2 Q4 Q2 U/D Q3 Q4

* ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION
NETWORK
VSS

FIGURE 1. CD4510BMS

6
 CD4510BMS, CD4516BMS

Logic Diagrams (Continued)

P1* Q1 P2* Q2 P3* Q3 P4* Q4

4 6 12 11 13 14 3 2
9
RESET*

1
PRESET*
ENABLE

15 P P P P
CLOCK*
PE Q PE Q PE Q PE Q
7
CARRY OUT C C C C

T Q T Q T Q T Q

Q1 Q2 Q2 Q3 Q3 Q4 Q4

5
CARRY IN*

10 U/D
UP/DOWN*
U/D

Q1
VDD U/D Q3 U/D Q3 U/D U/D U/D Q3 Q2
Q2 Q4 Q2 Q4 Q2 Q2 Q2 U/D Q3

* ALL INPUTS ARE PROTECTED

BY CMOS PROTECTION
NETWORK
VSS

FIGURE 2. CD4516BMS

TRUTH TABLE

CL CI U/D PE R ACTION

X 1 X 0 0 NO COUNT

0 1 0 0 COUNT UP

0 0 0 0 COUNT DOWN

X X X 1 0 PRESET

X X X X 1 RESET

X = DON’T CARE

7
 CD4510BMS, CD4516BMS

Typical Performance Characteristics

AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

OUTPUT LOW (SINK) CURRENT (IOL) (mA)

30 15.0
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
GATE-TO-SOURCE VOLTAGE (VGS) = 15V
25 12.5

20 10.0

10V
15 7.5
10V

10 5.0

5 2.5
5V 5V

0 5 10 15 0 5 10 15
DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

FIGURE 3. TYPICAL OUTPUT LOW (SINK) CURRENT FIGURE 4. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE (VDS) (V) DRAIN-TO-SOURCE VOLTAGE (VDS) (V)

-15 -10 -5 0 -15 -10 -5 0
0 0
AMBIENT TEMPERATURE (TA) = +25oC AMBIENT TEMPERATURE (TA) = +25oC
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)

GATE-TO-SOURCE VOLTAGE (VGS) = -5V -5 GATE-TO-SOURCE VOLTAGE (VGS) = -5V

-10 -5

-15

-10V -10V
-20 -10

-25

-15V -15V
-30 -15

FIGURE 5. TYPICAL OUTPUT HIGH (SOURCE) CURRENT FIGURE 6. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS CHARACTERISTICS

AMBIENT TEMPERATURE (TA) = +25oC

PROPAGATION DELAY TIME (tPLH, tPHL) (ns)

AMBIENT TEMPERATURE (TA) = +25oC

250
TRANSITION TIME (tTLH) (ns)

200 200 SUPPLY VOLTAGE (VDD) = 5V

SUPPLY VOLTAGE (VDD) = 5V

150 150

10V
100 100
10V 15V

15V
50 50

0
0 20 40 60 80 100 0 20 40 60 80 100
LOAD CAPACITANCE (CL) (pF) LOAD CAPACITANCE (CL) (pF)

FIGURE 7. TYPICAL TRANSITION TIME vs LOAD FIGURE 8. TYPICAL PROPAGATION DELAY TIME vs LOAD
CAPACITANCE CAPACITANCE FOR CLOCK-TO-Q OUTPUTS

8
 CD4510BMS, CD4516BMS

Typical Performance Characteristics (Continued)

104 AMBIENT TEMPERATURE (TA)

AMBIENT TEMPERATURE (TA) = +25oC

POWER DISSIPATION PER GATE (PD) (µW)

8 = +25oC
MAXIMUM CLOCK INPUT FREQUENCY

LOAD CAPACITANCE (CL) = 50pF 6

15 4 tr, tf = 20ns
2
SUPPLY VOLTS (VDD) = 15V
103
(fCL MAX) (MHz)

8 10V
6 10V
10 4
5V
2

102
8
5 6
4
CL = 50pF
2
CL = 15pF
10
0 5 10 15 20 2 4 68 2 4 68 2 4 68 2 4 68 2 4 68
01 1 10 102 103 104
SUPPLY VOLTAGE (VDD)
INPUT FREQUENCY (fCL) (kHz)

FIGURE 9. TYPICAL MAXIMUM CLOCK INPUT FREQUENCY vs FIGURE 10. TYPICAL DYNAMIC POWER DISSIPATION vs
SUPPLY VOLTAGE FREQUENCY

Test Circuit and Waveform

100µF ID 500µF
1 16
PULSE
2 15
GENERATOR
3 14 20ns 20ns
VDD
4 13 90%
CL 50%
CL 5 12
10%
VSS
6 11 VARIABLE
WIDTH
CL 7 10
CL
8 9 CL

FIGURE 11. POWER DISSIPATION TEST CIRCUIT AND INPUT WAVEFORM

Acquisition System

SAMPLE
AMPLI- AND
FIER HOLD
10 BIT PARALLEL
16 CHANNEL
ANALOG MULTIPLEXER START A/D DATA
DATA CD4067 CONVERTER OUTPUTS
CLOCK
INPUTS
CONVERSION
LOGIC
END
SELECT
INPUTS
NOTE:
Q1 Q4 This acquisition system can be operated in the random access mode by
PRESET jamming in the channel number at the present inputs, or in the sequential
INPUTS CD4516BMS mode by clocking the CD4516BMS.

CLOCK PRESET ENABLE

FIGURE 12. TYPICAL 16 CHANNEL, 10 BIT DATA ACQUISITION SYSTEM

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 CD4510BMS, CD4516BMS

Timing Diagrams

CLOCK

CARRY IN
UP/DOWN
RESET

PE
P1
P2
P3
P4
Q1
Q2
Q3
Q4
CARRY OUT
COUNT 0 1 2 3 4 5 6 7 8 9 8 7 6 5 4 3 2 1 0 0 9 6 7 0

FIGURE 13. CD4510BMS

CLOCK

CARRY IN
UP/DOWN

RESET
PE
P1 VDD
P2 VSS
P3
P4
Q1
Q2
Q3
Q4
CARRY OUT
COUNT 5 6 7 8 9 10 11 12 13 14 15 9 8 7 6 5 4 3 2 1 0 0 15 0

FIGURE 14. CD4516BMS

10
 CD4510BMS, CD4516BMS

PARALLEL CLOCKING
UP/DOWN
PRESET
ENABLE

UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4

CI CD4510/16BMS CO CI CD4510/16BMS CO CI CD4510/16BMS CO

*

R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4

CLOCK

RESET

* CARRY OUT lines at the 2nd, 3rd, etc., stages may have a negative-going glitch pulse resulting from differential delays of different CD4010/16BMS
IC’S. These negative going glitches do not affect proper CD4029BMS operation. However, if the CARRY OUT signals are used to trigger other edge-
sensitive logic devices, such as FF’S or counters, the CARRY OUT signals should be gated with the clock signal using a 2-input OR gate such as
CD4071BMS.

RIPPLE CLOCKING
UP/DOWN
PRESET
ENABLE

UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4 UP/D PE J1 J2 J3 J4

CI CD4510/16BMS CO CI CD4510/16BMS CO CI CD4510/16BMS CO

R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4 R CL Q1 Q2 Q3 Q4

CLOCK 1/4 CD4071B

RESET

Ripple Clocking Mode: The up/down control can be changed at any count. The only restriction on changing the up/down control is that the
clock input to the first counting stage must be high. For cascading counters operating in a fixed up-count or down-count mode, the OR gates
are not required between stages, and CO is connected directly to the CL input of the next stage with CI grounded.

FIGURE 15. CASCADING COUNTER PACKAGES

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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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