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Short Channel Effects

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16 views

Short Channel Effects

short channel effects notes are there

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Pushkar
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Fig : Gate induced drain leakage 8. Body bias effect: Body effect refers to the change in the threshold voltage of the device when there is a difference between substrate(body) and source voltages. Body bias is usually the lowest voltage in the chip. However, if we were to connect Vbuilt to a voltage lower than VSS (Source voltage), there is an increased flow of carriers between these source-bulk junctions thereby increasing the width of the depletion region. This in turns increases the minimum gate voltage needed to achieve channel inversion. 9. Velocity saturation: As there exists drain’s depletion region over the channel region due to the presence of Vos the electric field saturates the mobility of electrons at the pinch off point thereby creating saturation of current before the device could enter into the saturation region. Vos < Vest Due to the existence of saturation prior to the Voss the saturation of the device is extended and the drain current is small Ip Long-channel dev | Shor-channet device Mobility Degradation retest N\ ce ‘Oocme Fae secre tat a ‘Conan ‘en Fig 7: Velocity saturation curve USEFUL FORMULAS > Formulas 1. Resistance R= pl/a 2. Conductivity o=nep 3. Capacitance Fig : Back to back connection of NPN transistor in CMOS 6. Sub -threshold conduction: ‘As Vos [s increased and the channel is occupied by depletion region of drain leading to increase in electric field and thus the presence of channel before threshold is attained by the device itis called as subthreshold conduction. Thus the conduction occurs when Ves Vr ecargad Bowe Fig : subthreshold conduction 7. Gate induced drain leakage: GIDL occurs when the gate partially overlaps source and drain and when Vos is high and Ves is at low potential. The gate drain overlap region is present due to band to band tunnelling effect as the depletion region of drain keeps increasing in a manner that at some point of Vos the electrons from valence band tunnel towards the oxide’s conduction band known as band to band tunnelling effect. This tunnelling effect leads to leakage current at drain which is induced by the gate thus gate induced drain leakage. pase ‘As the technology node shrinks, Cross-sectional area of the metal interconnects also shrinks and the current density increases to a great extent in the lower node. Electro migration has been a problem since the 90 nm technology node or even earlier but it gets worse in lower technology node 28nm or lower node. Depending on the current density, the subject metal ion started drifting in the opposite direction of the electric field. If the current density is high, the interconnect may get affected by EM instantly or sometimes the effect may come after months/years of operation depending on current density. So the reliability of ASIC will depend upon this EM effect. Mean Time To Failure (MTTF) is an indication of the life span of an integrated circuit. MTTF is calculated using Black’s equation as below. A Ea MITE = Fy exp) Where A = Cross-Section area J = Current density N= Scaling factor (normally set to 2) Ea = Activation energy oltzmann’s constant T= Temperature in Kelvin Hillock Causing Short Void Causing Open lectromigration in metal wire 5. Latchup: The internal structure of CMOS has back to back connected PNP and NPN transistors as feedback ina positive loop. This back to back connection of PIMOS and NMOS leads to a low impedance path from supply to ground that allows heavy current flow in the path which could damage the device. This low impedance path can be over - come by decreasing the R (resistance) or by creating guard rings or by forming shallow isolation trench between PMOS and NMOS. UNIT 6 SHORT CHANNEL DEVICE > Short channel device: ¥_ Adevice is said to be short channel if it has following properties: 1. Adevice is called a short channel if its channel length is <1pm. 2. Ifthe channel length is in the order of depletion region width at source and drain junction it isa short channel device. 3. Ifthe channel length is in the order of junction depth. ¥_ Reasons for Short channel effect: 1. High electric fiek ‘As the channel length is less, the electric field between source and drain is high. 2. Vevariations: The source and drain is already depleted and has to be considered as their junction depth is the same channel length. So Ves for channel formation gets reduced as the depletion region of source and drain helps is pre - existence of channel before applying Vos. ¥_ Short channel effects: 1. Channel length modulation: When Vos > Ves ~ Vs the pinch off moves towards source from drain due to this the depletion Width of drain keeps increasing in a manner that the whole channel is occupied by the dep width of the drain. ‘Thus the effective channel decreases and is known as channel length modulation. fo 2/L; Lis channel length eat) m He Lae © 7 Was Veo} -(L+4-Vpgl Drain Current Drain Voltage channel length modulation graph 2. Hot carrier effects: Hot carriers are the high kinetic energy carriers. ‘As the short channel devices have Ves increasing there by high electric field is generated which leads electrons to flow from source to drain with high kinetic energy these carriers due to high electric field has tendency to break the bond and move to oxide layer from semiconductor channel leading to increase in electron concentration in oxide layer thus we see existence of charge leading to lc not equal to OA. This non - zero le makes the device input impedance to decrease, The electrons that have to reach the gate get trapped in oxide forming a negative charge in the oxide layer thus increasing Vr so Ves has to be increased to nullify this hot carrier effect. 3. Drain Induced barrier lowering: ‘As the channel length is small and Vos is kept increasing thus the depletion region of the drain is increased and thus the electric field increases. This depletion region causes an electric field around the source due to the charges present in the drain. These charges reduce the junction of source thus known as drain induced barrier lowering as the drain charges are the cause of the reduction in source junction. Due to presence of charges in the channel region there happens to see the reduction in Vr. This effect where the channel region is completely getting occupied by depletion regions and resulting in high electric fields is called the Punch through effect. i ee ee] Qs depleted Qs depleted by source by drain Delta doping We get to see this effect in lower technology nodes as the channel length reduces the interconnect spacing decreasing. ‘When high current density passes through a metal interconnect, the momentum of current carrying electrons may get transferred to metal ions during collision between them. Due to momentum transfer, the metal ions get drifted in the direction of motion of electrons. Such drift, ‘of metal ions from its original position is called electro migration. This means that when a metal needs to carry a higher density of charges than its capacity we get to see crests and troughs in the metal known as hillocks and voids which means short and open respectively. ‘When high density of carriers are passed in the metal the atoms get staggered leading to short known as hillacks. When the hillocks are formed due to a staggering amount of atoms the other region will be depleted of charges as it has less density of charges leading to open holes known as voids. Current density J is defined as the current following per unit cross-section area. J=YA ‘Where 1 is the current and Ais the cross-section of the area of interconnect. and for PMOS it is 4.3V as we need complete discharge of the voltage we consider NMOS as strong 0. STRONG 1: When NMOS and PMOS are given with some voltage let’s say SV and VDD with SV and Vt 0.7V the final voltage at the output due to charging capacity of the capacitor is found to be SV for PMOS and for NMOS it is 0.7V as we need input voltage to be reached as the output voltage so we consider PMOS as strong 1. Input g = 4 0-e-+e-strong 0 gai 1-2-r0-degraded 1 Input =. Output 0-+-+>-degraded 0 183 strong 1 Yoo Yoo (8) Low-to-high (©) High-to-1ow Fig: Strong 1 and strong 0 VIC of cmos: vad § sub pMos Va G = Gate Terminal S = Source Terminal D = Drain Terminal Sub = Subst ‘Schematic d ygram of CMOS Inverter Fig: CMOS circuit, V Advantages of CMOS: 2. High noise margin due to full voltage swing. 2. High input impedance due to Ie = 0. 3. Low output impedance, in steady state there always exists a path with finite resistance between output and either Voo or GND, making it less sensitive to noise and disturbances. 4, Ratio less property as the logic of the CMOS does not depend on the W/L ratio of P and N MosFeT. 5. Zero static power dissipation as no direct exists between ground and supply rail under steady state condition. ¥_ The analysis of the gate is done respect to the different design metrics as listed below: 1) Cost, expressed by the complexity and area. 2) Integrity and robustness, expressed by the static (or steady-state) behaviour. 3) Performance, determined by the dynamic (or transient) response 4) —_ Energy efficiency, set by the energy and power consumption. ¥ Logic: Positive logic = 1: positive potential "Negative logic = 0: negative potential When Vi. = 1 and equal to Veo the NMOS transistor is ON while the PMOS is OFF. When Vin = 0 and equal to Vss the PMOS transistor is ON while the NMOS is OFF. Y_ Structure of CMOS logic: 1. Consists of Pull down and Pulll up networks. 2. Pull down network has NMOS and Pull up network has PMOS. 3 AND : NMOS is connected in series; PMOS is connected in parallel. ‘OR: NMOS is connected in parallel; PMOS is connected in series. 4, Output is a complement of input. 5. Same inputs are given to both NMOS and PMOS. 6 For N inputs 2N transistors are needed. 7. Pull up transistor is the dual of a pull down transistor. Strong and Strong 1 STRONG 0: When NMOS and PMOS are given with some voltage let’s say SV and VDD with SV and Vt 0.7V the final voltage at the output due to discharging capacity of the capacitor is found to be OV for NMOS

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