NEC »PD7823x Advanced, 8-Bit . Real-Time Control Microcomputers NEC Electronics Inc. With A/D and D/A Converters “an 28 wat January 1990 Description Cl Extensive timer/counter functions ‘The 4P078293, wPD78294, and -PD78P238 are high- performance, 8-bit, single-chip microcomputers. They contain extended addressing capabilities for up to 1M byte of external memory. The devices also integrate sophisti- cated analog and digital peripherals as well as two low- power standby modes that make them ideal forlow-power/ battery backup applications. ‘The 4PD7823x family focuses on embedded control with features like hardware multiply and divide, two levels of interrupt response, four banks of main registers for mult tasking, and macroservice for processor-independent peripheral and memory DMA. Augmenting this high- performance core are advanced components like high precision A/D and DIA converters, two independent serial interfaces, several counter/imers, PWM outputs. as well as a real-time outputport. Onboard memory includes upto ‘1K bytes of RAM and 32K bytes of mask ROM or OTP ROM. The macroservice routine allows data to be transferred between any combination of memory and peripherals inde- pendent of the current program execution. The four banks of processor registers allow simplified context switching to be performed. Both features combined with powerful on- chip peripherals make this part ideal for a wide variety of ‘embedded control applications. Features 1 Complete single-chip microcomputer —8-bit ALU. — 16K ROM — 640 bytes RAM Both 1-bit and 8-bit logic U Instruction prefetch queue Hardware multiply and divide J Memory expansion — 8085 bus-compatible 64K program address space — IM data address space 0 Large /O capacity: up to 64 1/0 port lines 0 TWo 12-bit PWM outputs 0 Eight-input 8-bit A/D converters CL Two-output 8-bit DIA converters — One 16-bit imer/counter/event counter — Three 8-bit imer/counter/event counter (0 Four timer-controlied PWM channels (2 Two 4-bit real-time output ports D Extensive interrupt handler — Vectored interrupt handling — Programmable priority — Macroservice mode Two independent serial ports 1D Software pullup options D Retresh output for pseudostatic RAM On-chip clock generator — 12-MHz maximum CPU clock frequency = 0.33-ns instruction cycle J CMOS silicon gate technology 2 5-voll power supply Ordering Information Number ROW Package: wP078209G0-088 ROMs ‘0-pinplasic OFF HPO78233L a4-pnPLOC #PO782336-586 ‘t-pnplasic FP P078234G0-989 W6KMasKROM —_60-pinplasticOFP wPO7Ez34. ‘4-pn PLCC PO782346-586 ‘34 pin plastic QF PD78P208GC-280 S2KOTPROM _—_—80-pinplastioOFP. BPO7aP238L a4-pn PLoS PD76P258G-5686 ‘4pin plastic GFPNEC »PD7823x Pin Identification Symbol Farcon Symbot Foren Pas PO, Spon Pay PSrRahe VO REST Upper aatess fe PigPr PUR PURI VOpER VPunewanmoddeiedaupus Pla: Piyhhy Ag OUpuponiEnendedadessnittie PPh open PeuR VOpeT6tReadsobe ont Pan rodcothorneslabeinerainet —PeaiWA TO port ite tobe oat P2\-P2q/NTPO-INTPT Inputport2/Extemal nteuptinputtimer PogiWAT WO port 6/Waitinput ol _—_______—__ P6;/REFRO. WO port6/Refresh output Paginr2ic nat ponaEderlitornpt PIpPTyANG ANT woutponTADeonvenernpi Se pat asT8 ares tobe op P2s/INTPAASCK Input port2/External interruptinput! RESET Extemalresetinput nomerronowseraicock” "GE ——~C*C*«CR em aceon cnn Pains ptpenvenerainterstined x Exoral yar real cockpit PeyS\_—_ pain arses Wher "iD converter refrenoevotage Pago _____‘VOpuaSeralrecave rot ‘Nera hers DRconvert relrencevotages Pam WOpon/Sealrerentouit ra = PoC VO porta /Seral cockinpwoua Se ,is0rs80 TOper9iSeelospuSeiabsO eats pose pone supp rogecion PaxPHy TOUTES —_VOponsiTmercupa gg Ramerrtun:nomalyroond PlaPhyADG AD, ——_VOponaLoneradiressbyeideabie yo Nosoneaton»PD7823x NEC Pin Configurations 80-Pin Plastic QFP ofa Prgane sof pryana sabi Prana 7B eran 45 PagAdo 2B Payany “1B Pegade snwSca Cf sna awe ‘ony Cf uauay ssa ony Cf sow Cf zany easty awa oanw'ea vauwea ocaw*ea Cf sauna vosmmanniea sauna wa owta q ow'ea co te ee SNGSMRSRARFISSRRE BS TOUT oo ROeeaee sere le geereer ed E»PD7823x NE Cc -Pin PLCC (Plastic Leaded Chip Carrier) 4 rronut o Pagans Cf 13 mB rans Prganis Cl 16 mB rows PPyIANIT mB peguos we > B peenos ate mp regnoe ran 2 B rennor xe o f rome ae Brean weer ts B means ts B peyate P2yINTPO. elbitrecera PagiINTPY oP peas oa & B reyme cea 2B rome P2s/INTPAIASCK ml aleean ce sD reams Paris sD ea “ : & D reat Payno & B pega ae & B regioNEC »PD7823x 94-Pin Plastic QFP PEFR»PD7823x NEC Pin Functions P09-P0;. Port 0 is an 8-bit,tristate output port with direct, transistor drive capabilty. Port 0 can also be configured as two 4-bit, real-time (timer-controlied) output ports. Pig-P17. Port 1 is an 8-bit input/output port with the pro- grammable pullup option, Port 1 has direct LED drive capability. PWMO-PWMH. These are pulse-width modulated outputs for de motor control P2p-P27. Port 2 is an 8-bit input port with the programma- bie pullup option except for P29 and P2y NMI. Non-maskable interrupt input. INTPO-INTPS. External interrupt inputs. INTPO, INTP1, and INTP3 are timer capture trigger inputs. Cl. External clock input to the timer. ASCK. Asynchronous serial clock input. Sl. Serial data input for three-wire serial l/O mode. P39-P9>. Port 3is an 8-bittristate 1/0 port withthe pro- ‘grammable pullup option. XD. Receive serial data input. ‘TxD. Transmit serial data output ‘SEK, Serial shift clock output. ‘SO. Serial data output for three-wire serial /O mode. ‘SBO. 1/0 bus for the clocked serial interface. T00-T03. Timer flip-flop outputs. Pag-P47. Port 4 is an 8-bit, bidirectional tristate port with the programmable pullup option. Port 4 has direct LED. drive capability ‘ADo-AD7. Multiploxed address/data bus used with exter- nal memory or expanded I/O. P5p-P5;. Port § is an 8-bit, bidirectional tristate port with, the programmable pullup option. Port 5 has direct LED drive capability Ag-Ars. Upper-order address bus used with external memory or expanded 1/O. P6q-P6s. Pins Péy-P63 of port 6 are outputs. |-order address bus used with external P64-P67. Pins P6,-P6; of port 6 are tristate I/Os with the programmable pullup option. FD. Read strobe output used by external memory (or data registers) to place data on the 1/0 bus during a read operation. WR. write strobe output used by external memory (or data registers) to latch data from the /O bus during a write ‘operation. WATT. Wait signal input REFRG. Retresh pulse output used by external pseudo- static memory. 79-P7;. Port is an 8-bit input port. ‘ANIO-ANIT. Analog voltage inputs to A/D converter. 'ANO1, ANO2. Analog voltage outputs from D/A converters. ASTB. Address strobe output used by external circuitry to latch the low-order 8 address bits during the first part of a read or write cycle. RESET. A low level on this external reset input sets allre- disters to their specified reset values. This pin, together With P2o/NMI, sets the wPD78P234 in the PROM program- ming mode. MODE. Control signal input that selects external memory or internal ROM as the program memory. When MODE is tow, .PD78234 is set in ROMless mode and external memory is accessed. X1, X2, For frequency control of the internal clock oscil- lator, a crystal is connected to X1 and X2. If the clock is supplied by an external source, the clock signal is con- nected fo Xt and the inverted clock signal is connected to x2. ‘AVpert- A/D converter reference voltage, AVpera, AVaers- D/A converter reference voltage. ‘ANpp: A/D converter supply voltage. ‘Ags. AID converter ground.NEC »PD7823x ».PD7823x Block Diagram tus ort SFR AddressData Bus ete! P2q/NMI —"1 Programmable fl mat Apdst Pey-Pegi a} camel, KDI — Tan ao, mTPORTTPS ‘Dg AD! rao — OF] moar payin =| a reste —+| new —=| Gaara | P32i80K 76/0 Ps Pa4iT00 Pas iro rex rs0se0 +] tesa re Frimercount| webu) g wnrpo >} Tineroner ‘Grane ar) pagintPaset —a| inertooner ‘Grama? (5 8s) Payitoa aie Bus Tinorcoontr ‘Channa! Cate) TealTine utp Pon (aoe x2) Fea ANON? Macrosenice ‘Avaers | ‘Coane ‘ito 2 converter | nee —>| (26.07) NPS | Avper2 +] conwenwe aera Pum <—| Modine ea aa [> resi [> Pe ERG Le asta Tra Dam ‘Momo xeBj0s) Py jo ooo oo Oo 8 P29 Pa Pq Po ey Py Pe 7 PB Pq Fig meep»PD7823x NEC FUNCTIONAL DESCRIPTION Timing ‘The maximum clock frequency is 12 MHz. The clock is de- rived from an external crystal or an external oscillator. The internal processor clock is two-phase and the machine states are executed at a rate of 6 MHz. The shortest in- structions require two states (333 ns). The CPU contains a ‘one-byte instruction prefetch. This allows a subsequent instruction to be fetched during the execution of an instruc tion that does not reference memory. Memory Map ‘The uPD7823x has 1M byte of address space. This address space Is partitioned into 64K bytes of program Figure 1. Memory Map memory starting at address OOOOH. (See figure 1.) The remainder of the 1M bytes can be accessed as data mem- ory space. External memory is supported by 1/0 port 4, an 8-bit multi- plexed address/data bus. The memory mapping register Controls the size of extemal memory as well as the number of added wait states. The upper address byte is derived from port 5, and the extended address nibble is derived from port 6. ‘The uPD78234 has on-chip mask ROM occupying the space from 00000H to 03FFFH. When the ROM is used land no other program or data space is required, ports 4,5, and 6 are available as additional I/O ports. ooo ‘000 | inert veaer conarn | Mes Table Ava ‘on-chip ROM P0404 | cau Tie Rea eSA Bos on (att be extral 2080 | progam wea rnanery corer InpPorazse, 00008 CcaLLF my nea ai ‘wo Progam Aca ree corre crore ‘oFcaDH co nchip RAM *T once 40 yes fa orerri orcor _| roan Seca Fpcan OFEEOH crreen | "Ren orceru | _Peoaten “00008 Exar Merry (@xonses assess nea) reerNEC »PD7823x General-Purpose Registers ‘The general-purpose registers are mapped into specific addresses in data memory. They are made up of four banks, each bank consisting of eight 8-bit or four 16-bit registers. The register bank used is specified by a CPU instruction. This can be checked by reading RBSO and RBS1 in the program status word (PSW).The general- purpose register configuration is shown in figure 2. Figure2. Register Mapping recon [Regie tank Foren Foret Procestng Processing [nA | ox] TIPO) AR | oFere ° aya fmae| [arnec | orcran ene so [mae] [earae | orercn wrest courier coral Geo Cone ‘Sera lock vx tou | cone rast fe teaxee asi} Taso 6NEC nPD7823x Timer/Counters ‘The 4PD7823x has four timer/counters: one 16-bit and three 8-bit. The 16-bit timer/counter (figure 9) has the basic functionality of an interval timer, a programmable ‘square-wave output, and a pulse width measurer. These functions can provide a digital delayed one-shot output, a pulse width modulated output, and a cycle measurer. Figure 9. 16-Bit Timer/Counter ‘The first two 8-bit timer/counters can provide the basic funetions of an interval timer and a pulse width measurer. Timer/counter 1 can also be used as a timer for output tigger generation for the real-time output port. Timer/ ‘counter 2 can also provide an external event counter, a ‘one-shot timer, @ programmable square-wave output, a pulse-width modulated output, and a cycle measurer. ‘Timer/counter 3 can operate as an intemal timer or as @ counter to generate clocks for a baud rate generator. See figures 10, 11, and 12. Tier Ovpit a fu} conan a Sera irae Soroae fe Me Roger Senval ) esas] ess0 east | el zee em] [Bree] aor Jeon] ave T + oF F Ene regaava o—fosston| 4» anes | l | reser | wages ote | foux'® | ero) ra Coe Tae Capi Regi a Reger cen 7»PD7823x Figure 10. 8-Bit Timer/Counter 1 NEC Fornal Bia 3 Fa ‘| : . Eneral mort ae Move Rgitora. [ e501] E500 Seon [ain] ow [ame trator ] eres 7 eer intro ——o] Eeeeperaion | [rei Givo ue Colncidance ) | wre10 maar C ‘axes — PC mer aK 258 —ey 1 t veriow (akrae —| ae tea | saeco tia t tage = J teuete —| L T care ‘ome wrens aaa algo Proscar i Tom, Mode Regitur [Pasi2 | PASH | PASTO ces [ovr | oneal omen ‘ ce I*{ ¢ Tremal Bo 5 18NEC »PD7823x Figure 11. &-BItTimer/Counter 2 a tT See. |o[ meer |e cen a aoe eel eee pedeen | |a| [em [sirer] [Saco] ave [enroa] ave ] T (wrwoy yt F F reece om — 3 once ———— : a Proscar ‘cz | ovre | owe ‘Mode Register 323 21 | PRSZO eee are [Fase [nszz [prises ° fen aera 5 Interrupts: ‘There are 20 interrupt request sources; each source is allo- cated a location in the vector table, (See table 2.) There is ‘one software interrupt request and one of the remaining 19 interrupts is non-maskable. The software interrupt and the ‘non-maskable interrupt are unconditionally received even. in the DI state. These two interrupts possess the maximum, priority. The maskable interrupt requests are subject to mask control by the setting of the interrupt mask flag. ‘There are defautt priorities associated with each maskable rrupt and these can be assigned to either of two pro- ‘grammable priority levels. Interrupts may be serviced by the vectored interrupt method where a branch to a desired service programis executed. Interrupts may also be handled by the macroservice function where a preassigned proc: ‘ess is performed without program intervention. 19»PD7823x NE Cc Figure 12. 8-Bit Timer/Counter 3 sen.te0 omen enuaser—] oo, |_| wm cone aren | Bo feux!s12 —+| Clow at [ ae ‘®Bu Tener 3 7 Set iwiece ‘oe — | ia ‘to — cette nas [nse [ens | pre ce —_ rie Table 2. Interrupt Sources and Vector Addresses interupt vector feqent ete ecrnarice “hoi oy Prony Interupt Raqunet Generation Source ose Adress Sotware None BaKnartonerecaen = O08 Non-maskable None —_NMI(pininputedge detection) _ - =a 02H Maskable o INTPO (pin input edge detection) _ Yes 0006H “a INTP4 (pin input edge detection) ~ a Yes 0008H 2___ INTP2(pninputedge detection) Yes Q00AH 3 NTP np edge cect Yes e00cH 4 NToOD Two- CRO corre sralgerarann) Yeo ora INTENT (TMO-CR1coneence si gnerston Yeo 0016 © INTCIO(TMI-cROconeitne snl error Yeo 018 TINT MCR eoeldene sgn error es o0van @~ WNTCRI THE. GRE corde se gonuaon) Yes 00108 2 INTPA(pninpwtodpecetetenyINTCAO(TNG- CREO orcdencesgalgeeraton) Yes ———_—‘OO0EH 10 TPS (gn pet gp cetecton NAD end comersion Yeo 10H " INTG20 (TM2-CAZ0 coincidence signal generation) Yes oo12H 12 INTSERgeeraton ct ayocvonos serial reas ood ora a “3 INTSA (end of asynchronous serial intertace reception) Yes 022 4 NTS edotanyretvonoue sone varies) Yes east 15 INT endl socked ora tric ranean Yoo 0264NE Cc pPD7823x Macroservice Figure 13. Macroservice Control Word Map ‘The macroservice function can be programmed to transfer data from a special function register to memory or from arenes [ Cerntectar |) memory oa speci! uncon repele. TWansfr even re ereoos [ae Ro tHggerod by inerupt requests and take place without so ee ware intervention. There are 17 interrupt requests where creoca | nose Roper] | SET macroserdcing can be executed The macroserice fur erence es en ton s contoled by the mactosenice mode reir and west ‘the macroservice channel pointer. The macroservice OFEDAN | Mode Register mo rege asigns Bi acogorving mo and the crconi | eamitone || yg macroservice channel pointer indicates the address of the OFEDBH | Mode Register mre! memory location pointers. The location of each register facant le chat rom ands Corresponding interrupts shown i fire 13 cron Sar roy enihonl orcoe [tert] | OnPon® Tho rersh signals used wih a psoudostatic RAM, The ere refresh cycle can be set to one of four intervals ranging OFEDSH an et INTPSANTAD from 2.6 to 21.3 4s. The refresh is timed to follow a read or OFED2H | Mode Register vio oporaion 8 thee lan terrence, com [oon [eer | cn oreo | — ar ar Standby Modes crcors|[ ca] Halt and sop functions reduce systam pawer consump- rece | tee tion. In the halt mode, the CPU stops and the system clock OFECOH | Channel Pointer continues to run. A release of the halt mode is initiated — wrceo gh urmasted toro tequest an ils ces ASE sre [moa input. In the stop mode, the CPU and system clock are oreCBH anne Foner wntezs both stopped, reducing the power consumption even OFECAH | Mode Register farther. Te stop mode fs rlessed by an NMI input or See leone RESET input. OFECSH | Mode Registor ware orecn | “caer Par wa orecn [aan ap reco [cette ware oreoa | ~ar apo ‘OFECSH | Channel Pointer wns orece [arg 21»PD7823x ELECTRICAL SPECIFICATIONS: NEC Absolute Maximum Ratings tan 25 ter Symbol Conatons ating at Power up waages| Veo sto +70 v oo Ales oo + 08 v es ~0510+05 v inputvatage Ms Oster +05 v Oupavotage Vo ~0510¥o0 +05 ¥ Lowel spied te ‘Oreoupatin 6 mA Alouette! 00 mA Figheveoueacirer oH Ore ovpuin __ Alloutput pins total 50 mA ‘Donen retrone rer ~DSI0AVe9 103 v inouvetone DiAconvrorrtronce Alnere “0 10Voo 108 v (mpet vantage AVREFS: 0510Vp9 + 0.3 v (Operating temporature Tort - ~H010 +85, Stevagetonporatvre Ts10 esto +150 < Operating Frequency Capacitance Oscillation Frequency, ta Yoo. Tas +2500: Vo = Vas face soe ~aote +SEE 10 ae seh inpacapactance G20 pF = Wena not Ouiputcapactance Co 20 oF inpwioapacepactrce Go 20 _ oF 22.NE Cc »PD7823x DC Characteristics Tye =40 to +85°C;Voo = +5V 10%: Vos = Ags = OV. Hor ‘Symbot Conditions: Min WP Max nt Towiovelinpavotage Vu. ° v Highdovelingutvotiage Vein Excoptpinsinote 1 22 v Vio PinsinNotet 080 v Lowieveloutputvoiage You tou = 20mA v Vou lou = 8 0mAlpinsin Note2) v Highovetoutputvotage lon==1.0mA Von-19) v (004A Ypp-05) v Sma pinsinNote3) 20 v inputeakage current oV=Vi= Yoo 210 vA (Outputieakage curent i= Yoo 310 HA ‘Aver curt Operating modo, fx = 12M 15, 50 mA po power supply current (Operating moda, gx = 12MH2 0 mA HALT mode, x= 122 7 20 mA Data retention volage STOP mode 25 55 v Data retention currant ‘STOPmode “Vooon=25V 2 aA Vooon = 5¥=10% s 50 HA Pulupresisor A waov 6 « 2% ka. Notes: (1) X1, X2, RESET, P29/NM P2yINTPO, P2p/NTPI, P2,/INTP2ICI, (2) Pins Plo-Py, Plg-PariADy-ADy and PSp-PBriAg-Ais, P2yIINTPS, P2g/INTPSIASCK, P2giINTPS, P27/Sl, PS2iSCK (9) Ping PUy-POy Paq/S0880, and EA pins, Figure 14. Voltage Thresholds for Timing Measurements = maar oasyv»PD7823x NE Cc Read/Write Operation Tan MO to +85°C3 pp = +5 210% Vag = OV: fe = 12MHE; Cy = 100 pF. Soe fies 15 16, and 17 Tem ‘Symbol Conditions Min Max Unit Xinpulcoek oyoetine ‘ox a 250 08 ‘Adress setuptme 1 ASTB 1 ‘ast 52 1 ‘Adcressnodtime from ASTB # (Noto 1) era A= SAMO = 800 25 18 ‘AdcrosstoFD 1 dlaytve oan 123 ne ‘Address oattine rom RD | fea W 18 ‘Aseress to datainputtine ‘on 228 8 STB Hodatainputine ‘oem, 181 1 FD ‘iodatainputtine ‘oa 38 8 {STB 10D | delaytime ‘osta 2 ne Dataholstime tom t aw = 1s FD toasdress active tne ‘ora 724 ns FAD 1 oASTB delayime ‘ost 124 7 FD lowiovetwicth tw 126 3 ‘ASTBhigh level with twsne EA rs ‘Adcresst0WA 3 dolayime tonw 29 rs STB todataoutpattine Tost00 aa ns WR | todataoutputtime towoo 60, ns ASTB | 1OWA ! dolayime ‘osm 2 7 ese Retresh mode 128 1 Datasotptine io WAT ‘eoown 146 18 DatasetuptimetoWR | (Note) eoowe eiresh made 2 rs Datahoi time om WA t ‘two 2 8 Wr WoASTB I detayiee ‘owst 2 1 WRiow-ovelwidth ww 196 os twa Roiresh mode a rs ‘Adress toWATT 1 iputtive ‘oat 15 8 {ASTB 1 @WATT 1 inputtie ‘osrw a ne WT potstime from + ‘wrx 8 WaT eonpimeioxtt ‘eux 8 Notes: (1) The hold tme Incudes the fre during which Vow and Voy are retained under the folowing load conditions: C= 100 oF and R=2ke. 24NEC pPD7823x Figure 18. Read Operation Timing 25uPD7823x Ni i Cc Figure 16. Write Operation Timing aw,NEC ».PD7823x Serial Port Operation Tae lo 185°: Vop = #5V # 10% Vos MIC = WO PF Seo gues 1810, ort 20. em Conatvons Min Max unt Seraicockoysotme Tipu _ Exeral cock ‘9 os Cutout Internal cock 13 vs rere cock 53 ve Serial clock jowtevel width ~ wskt Input__External clock 420, ns Cutout _nteralcaen 6 6 Interna toc 64 25 Py Sora dock hghvievelwish Tae inpia External cock 420 8 ‘ups _inernaloek16 6 8 eral loc 25 “ ‘$1, $80setup time to SCK 1 tess. 1590 ns ‘SI, SB0hold time trom SK t {uss _ 400 ns S0/S00Apuelay me tromSEK + ‘osesi ‘GMOS posh pur outpat ° 300 rs es we eral mode) ‘oss ‘Open-drain ouput ° ey 18 (sehmode) r= k2 ‘SbOnigh holdtme rom SEK eee SBimade + om ‘8010, setup ine SCRE ‘sak sel mede + tox ‘S80 low-level with ‘wast 4 tox ‘Se0Highevetwith wae + tox xD setup ne oS + ‘eres © 8 xD ls neater SORT ‘hs © ne ‘SOK | to TxD delay time: {osKTx. 210 ns Figure 18, Clock-Synchronized Serial interface Timing; Three-Line 1/0 Mode omuom 27»PD7823x Ni Fi Cc Figure 19. Clock-Synchronized Serial interface Timing; SBI Mode Bus Release Signal Transfer Timing ‘Command Signal Transfer Timing sok | tss8sK os rin Figure 20. Asynctronoue Mode Tning son = X a ‘amaNEC uPD7823x A/D Converter Operation Jun Ot TBS Voge BV 0%: Veg = Nig = OV. vem Synbo! Conaone uta Rasoon 3 or Full-scale error ~ oa 08 ‘AVper = 40V10Vo9 - 08. * Quantization enor _ ~ Z 212 ts8. Conversion time ~ Too 88 Stoyx=125ns 360 = tom 12565 tore = 25008 ~~ 200 tovx Saneingtine ‘ome Ones yx 15s 7 ical Tens Sts 06 @ - ‘ox srasinpatage wan ~o aa rputinpedeee fan ~ ‘a0 wa ‘natog etree volags Wher oa eo ‘ner eurent Ainge Operating mode hg Tene is 50 na STOPmode 0218 mA D/A Converter Operation Tan Oto “85; Nery = Voo = #SV 210%: Nees tm Synbol wpe ton 3 Bi Aeottwacraaey Thera =v a ‘Nera =Voo-0¥ Conic 2M 300° ‘pera =075¥00 se AVnee ~ 9:25 op; toed cations 30, 3008 Setting time Undefined ~ 0 1 Arlopretrencs eae Vamnera O80 ‘ov ‘Analog reference voltage VavRer3 _ o 0.25 Yoo. v Fetrarcepowernplcurerd Are ° Sma Reference power input current Alpers: -5.0 o mA ‘Output resistance Ro _ 24 KaNEC »PD7823x Interrupt Timing Operation Figure 21. Interrupt Input Timing we Synbol Condos Win Wax Unit Taare ‘wn oes gh evlwih ‘wee TO INTPO:INTPSiowievlwah Sw 2 tox INTPOANTPS Wg evlwith wr ov RESET low-level with west, 10 s FEEEThighwotwioh nen swan sw: Woceigeten@ SCS ae Data Retention Characteristics Tan 4010 +85. em ‘Symbol ‘Conditions Min on Max nit Datarotonionvaliage Vooon _ STOPmose 25. 55 v Dataretertoncurent ‘oooa __Yoooa=2.5V 2 6 ry V0 5 2 vA Voprisotime eo. 200 as Ypptatume feo 200 Ms Vopretersion tne vo. ° me (@° STOP mode setup) ‘STOPreleasesignalinputime —_ToREL ° me Oscilatonstabizatonwaittine warn __Crystalosciator », ms Coramicresonator 6 ne Lomlovelinputvatage Vi Speotiedpins Not 1) ° ‘Avon Highievelinputvotage Yt (09¥o008 Voor v Notes: (1) RESET, Pay NM, PeyINTPO, P2gINTPS, P2y/INTPZICI, Pay INTP2, P2gINTPAIASCK, P2,/NTPS, P2y/3,PSp!SCK, PQ/SO! $80, and EA i. (2) Soe igure,NEC Figure 23. Data Retention Characteristics Set sTOP Mode Yoo na (essa ny ing ‘ogo nou nw (Rose oy ing ‘age nos 3pPD7823x Timing Dependent on tcvx tom Symbol ‘Calculation Formula WinMex MH Unit Xiinpaldockeycle re tent Min e 3 ‘Aséress sotuptineto ASTE | ‘ast ten 90) Min 52 rs ‘Address | delay tno ‘oan ~ Bovx=35 Min 128 re, ‘Ader Host ime rom FO & an ‘evxl2-90 Min i re ‘Adesso datainputine ‘ox (@+2n teva 100 Max 228 8 {ASTB 1 odalainputtine ‘osro (+2n)toyx= 65 Max 181 rs BD H odetainputtone - ‘ono (2 2mitoyx=65 Max 9 8 ‘STB ORD | delaytine ‘ost tox=30 Min 2 m8 BD 1 toxcaressactvotme ‘ona Pore 40 Min 124 8 FAD 11oAST doaytine ‘orer. Bor 40 Mn 124 vs Biow-ovel width wen. (22m tovx=40 Mn 128 8 ASTBRGHevelwiah ~ ws tox 00 Min 52 ts ‘Addcosst0WA + delay tine toaw Bown Mo 129 rs {STB | todaiaouputine ‘ost09 torn 60 ~ Max we rs {AST 1 toWR | dolaytne ‘osmws ton=90 Min a 8 ‘ose 2on-35 Min 128 ne (rireshmece) Data cotuptine WRT ‘soowm (@+2moyx- 10 Min 148 18 Data sotuptimoto WA + 's00Wr tovx-60 Mr 2 ne (cereshmede) WA WASTB | deayime ‘owsr tone 40 Nie 2 “ne Whitowivelwiath ‘wwe (e2M tere 50 196 8 ‘wm (2r2n)tcyx-50| Min 14 8 (Corsrmode) ‘Address toWATT | input tine ‘oar Bioyx— 100 Max 146 a ‘STB H0WAIT 1 inputtine ‘ost erx80 Max ma 7s Notes: (1) indicates the numberof wat stats. 32Ni Cc »PD7823x Figure 24. Recommended Oscillator Circuit External Clock Operation Tams Symi Gove tn War Unt « = Tipaineton wa 3 wee Xipahghiiwah ws 2 ep & | won Xinpareeire ten oa ea e “arpattine oe Kiwanis one em coma teqoaney f= 2 sou] Figure 26. External Glock Timing Figure 25. Recommended External Clock Circuit ok xt P0702 x Gok tequaney thx «410 12M»PD7823x pPD78P238 PROGRAMMING In the 78P238, the mask ROM of 78234 is replaced by a ‘one-time programmable ROM (OTP ROM). The ROM is 32K x 8 bits and can be programmed using a general- purpose PROM writer with a wPD27C256A programming mode, ‘The PA-78P238GC/Gu/L are the socket adaptors used for configuring the .PD78P238 tofita standard PROM socket. Refer to tables 3 through 6 and figures 27 and 28 for spe- cial information applicable to PROM programming. NEC Table 3. Pin Functions During EPROM Programming Pin Function 05-Po, ‘evar inputpinstor PROM wrtelventy ‘operations ‘Ae ___Inputpinfor PROM write verity operation P2\iINTPO___Ag___Inputpinfor PROM write very operaton P5p-P5e/Awy-Aue Asg-Ate _Inputpinsfor PROM wrtoivery _ operations Pap:P&7/ADo-AD) Dp-Dy __Oalapins or PROMweteverty operations P65/WA cE ‘Strobe data into the PROM. Fec35 68 Erwan rntome PROM ee ee Troe ctrangentioon BERET FEET prow ropanrg odes Tne baonseee tosh cA Ver ‘High voltage applied to this pin for sete Vee Ves _Ground 2 Table 4._ Summary of Operation Modes fr PROM Programming ie va REST GeO te Vo OD; poman Tas ri a 4 Teay ey oa Pegrenieiy es tL a easy veya ote r nl m easy rey tin Readout +25v L L ao +5 +5V Data output Owpuldiabe BV 7 c n av ev ote Winer #125 Vis applied Vp and +6 V9 Yoo bath GE end TE cannot be soto low vel) smutaroosy 34NEC p»PD7823x Table. DC Programming Characteristics Tan 25 =5°C, Vip = 125 =05V applied to NMI PIN, Vos ~ OV. Parameter Symbol Symbol™ ‘Condition vin Max—_—Unit Fiieveliopavotege Vin Ven 24 Voor 103 Lowievelinputvotage Me Ye ~03 08 v Inpulleskage curont wr Var __0= = ope 10 HA High evel ouput votage Vou Vow 24 vo Yous You Yoo=07 v Lowievetauputvorage You You 048 v Ouputteakage current ho 10 vA Nulpinbighwotageinncurent te 0 vA Voor power votoge Voor Veo __Programmemenywitemode 678 80 625 v Programmemoryreedmade 45 _——~50 55 v Vpppowervotage Ve Vor Programmenonywitemode 122 —125—~—~—«128 v Pregram memory read mode Vor = Voor v Vooepowercurent Too icc _ Program memory wite mode 5 30 mA Program memory readmode 5 30 mA CE = Vi. Vi~ Vow Vprpowercurent lee ibe Programmemorywtemode 3 20 mA cE= Vy, 08 = Vin a Proprammemoryread mode 1 109 vA * Coresponding symbols othe wPO27C256R Table 6. AC Programming Characteristics Ta 25 15, Vp «125 205V appiedto NMI DIN. og = OV. Yop = 6 #025 V. pp = 125 =03¥. Parameter ‘Symbol Symbol™ Condition MnP Max unit Receassatyptine oEE sac us. 2 a DatatoOE : delay tine ‘e000 ‘oes 2 1s Inputdata setup tine to CE! ‘s106 be 2 a ‘Aasressholdtime rom 1 ‘yca wa 2 us Input ata hoi tine tori 1 ‘Hoo ‘ov 2 1 Ouipurdataratine OE ‘wooo tor ° 90 8 Vopsetuptine oe ‘svc ‘ves 1 m8 VopesetuptimetoGE | ‘voc. wos 1 me iar pds wih tans ‘ew ~ 098 e008 ‘Asana rogram pulse with tz Yorw 285 7875 me wi nigh wokageingu coin te ‘eee 2 ra (sen) Adesso data cuit tme ‘on00 ‘woe 200 = EE Hodataoutputtme ‘0000, tee OE 200 n= GE Hodstacutpattime "p00 toe a m3 Datanold tine tom OE 1 ‘coo. er. © ns Datano ime rom adress ‘too. ton ne © Corresponding symboW8 ofthe uPD27CZ56A»PD7823x NEC Figure 27. PROM Write Mode Timing (2) Vp must nat eowed 8 V, inating oversbot some taan aw fete ype tooo pt en ea i a ooo te + oe = | }-—_———_ [soe _, [yer ‘soo atk eo a | oP tsvPC_ voor voor =). vm 4 z fs ses | HE , ‘poop bol vw = “ = ()- Ypop must be appl beta appvne Ver. Kaho be removed her eeingV pp. Figure 28. PROM Read Mode Timing mtu aeNEC »PD7823x PROM Write Procedure (a) 2) @) (4) © © ” @ @) Connect the RESET pin to a low level and apply +12.5 Vo the NMI pin. Apply +6 Vo the Voo pin and + 12.5 V to the Vpp pin. Provide the initial address. Provide write data. Provide 1-ms program pulse (active low) to the CE pin. This bitis now verified with a pulse (active low) to the GE pin. ifthe data has been written, proceedtto step 8; If not, repeat steps 4 to 6. If the data cannot be cor- rectly written afler 25 attempts, go to step 7. Classify as defective and stop write operation. Provide write data and supply program pulse (for additional writing) for 3 ms times the number of repeats performed between stops 4 106. Increment the address. (10) Repeat steps 4 to 9 until the end address. PROM Read Procedure (1). Fixthe RESET pin to a low level and apply +12.5 V0, the NMI pin. (2) Apply +5 Vito the Vpp and Vpo pins. (8). Inputthe address of the data to be readto pins Ag-Ara, (4) Read mode is entered with a pulse (active low) on both the CE and OE pins. (8) Data is output to the Dp to Dy pins. 37»PD7823x INSTRUCTION SET {All microcomputers in the 4PD7823x family have a t-byte instruction lookahead butter. This allows the first byte of the next opcode in program memory tobe fetched while the current opcode is being executed. This pipeline architec- ture allows instruction fetch and excute cycles to overlap. ‘An instruction can be fetched from program memory while data is being read from or written to RAM or an 1/O port. ‘The advantage of the pipeline is that one instruction canbe ‘executed while another is being fetched, virtually halving the time required for these two operations and thereby reducing overall program execution time. Operands and Operations Refer to tables 7 and 8 for the meanings of symbols in the ‘operand and operations columns of the Instruction Set, table. Table 7. Operands (cont) ‘Symbol 2p Spedialtuncton registerpal: {GR00-CRO2, TMO, IFO, MK, PRO, SMO ‘Tam Memory address indirectly addressed Register direct mode:(DE} (HL), [DE+) (HL +] {DE-.HL-1 Base mode[DE byte), {HL yee] [SP-+ byte Indexed mode: word, wore), word{DE} word HU) ‘mem! Memory address addressed by meansctindrect addressing group 1: (DE) (HL address: 40H.-7EH immediate dataoriabel {6-bi data: 16-btInmedia ‘Specify operands in accordance with the rules of operand sore a representation; for details, refer to the assembler specifi- senmeciate ate orabel cations. If two or more description methods are avaliable, bt_S-idaa:8-btirmedat detacrlabel select one. The symbols +, -. #. 1 $,/,[ and & aren Nomberol shite 6-btinmediate dala (0-7) keywords and must be used in conjunction with each bn” Regjterbank ROO-RED instruction. ‘When describing immediate data as alabel, use oneofthe Table 8._Registers and Flags following modifiers: +,~, #,!,$,/,[].and& Symbo'srand Symbol Weaning rpcanbe describedinboth thefunctionnameandabsolute 4 Seer name e epae 7 Table 7. Operands 5 Bregister_—_ ‘Symbol Meaning c Cregister, - + __Avneenent ° Drogistr TAulodeerement _ € Eregater # —_Immedatedata H Hregister _ ! Absolute address - u Lregister S__Relatveaderess _ RO-R7 __Rogisters0107 (absolute nares) 7 Brinversion ax ogi pai(AX) 1-bacoumullor (1 rectassossng ae epi pa(8C) = Sibbank oe esi par(OE) 7 Regier it Register pa.) Function name:X.,,B,E,0,L,H Absolutename: ROtOA7 str pars 0109 (absoluenarres) rel Po Program counter ster group 10.8 pO REEEEE Eroprestconte Ee fH Registergroup 6.8 ee jaaanane "e Recister pair Function name: AX, 8C, OE, MU. Pow [Absolute name: APOIO APS ow ‘St Specialunctionregistor: rr 0, P2-P7, POH, POL, RTPC, CR10, CR11,CAZ0, CR2,CR22, (CR20, PMO, PM3, PNS,PM6,PMC3,PUO.CACD-CAG2.Toc, 2_Zeofag ‘TMI-TM3, TCO, TMC1, PRMO, PRMI, ADM, ADCR, CSI, RBST-ABSO_Regiterbankasectiags ‘SBIC, SIO, ASIM,ASIS, iB, TxS, BRGC, STBC (Gedicatedin. struction only), MM, PW, REM, IFOL,IFOH, MKOL,MKOH,PRoL, ‘© _lmterruptenabiefag 0 ROH, ‘SMOL, ISMOH, INTMO,INTWH, IST STBC___ Standby contolregicor 38NEC »PD7823x Table 8. Registers and Flags (cont) ‘Symbol__ Meaning oO ‘Memory contents indicated by addess or register conionts ny vo \decimal umber Xun. Higher bits and lowor bis o 16-bitregistorpai Clocks ‘The clock field specifies the number of clocks required under the conditions defined by the four column headings a follows: IROM Program ininternal ROMis executed. IRAM Programin external ROMis executed andinternal RAMis accessed. SFR Programinexternal ROMis executed and special {unetion register is accessed. EMEM Program in external ROMis executedand external memoryis accessed. Ina shift/rotate instruction, nin the clock field indicates the ‘number of bits by which data is shifted. ‘The hyphen () indicates a range of values; for example 10-13 means 10, 11, 12, or 13. ‘The virgule symbol (/) means either/or; for example, a/b means either a or b. ‘The number of clocks when execution is branched by a conditional branch instruction is shown after the symbol (/) ‘The number of clocks for instruction having the saddr or saddrp operand and when an SFRis accessed with FFOOH to FFFFH described as saddr or sadatp is shown after the symbol (). Bytes and Clocks ‘The number of bytes and clocks for instructions with amem, ‘or &mem operand depends on the particular instruction land the memory addressing mode (register indirect, base, cr indexed). Table 9 is applicable when the program in internal ROM is executed (ROM clock column of the In- struction Set table). Table 10 is applicable when the pro- gram in external ROM is executed (IRAM, SFR, and EMEM clock columns). Flags ‘The symbols in the flag field have the following meanings. Blank No change 0 Cleared too 1 Settot x Setor cleared depending on the result Value previously saved is restored Operation Codes ‘Table 11 defines the symbols used in the operation code field Registers and Register Pairs. The rr, and rp operands, are spectfiedin the opcode by one or more bits as shown in, figure 29. For example, 001 as bits RA\R (or ReRsRa) specifies register A. In the first and second operands are registers or register pairs; the higher 4 bits of the register specification byte define the first operand and the lower 4 bits define the sec- ‘ond operand. For example, in the MOV A,L instruction (transfer L register contents to register A), the second byte of the opcode is obtained from figure 29 as shown below. Instruction Opcode, Bytes 1 and 2 Movrr 00100100 0 RePisRy 0 R2RiRo MOVAL 00100100 00010110 Memory Addressing Modes, The 3-bit mem code and the S5-bit mod code are selected from figure 30 according tothe description of mem in the operand field (table 7). AMO instruction with register indirect mode specified for mem is a special 1-byte instruction. When base mode or indexed mode is specified for mem, the 8-bit or 16-bit offset data corresponding to byte and word, respectively, is added from the third byte onward, ‘The opcode for an &mem or &mem! operand is modified by inserting a O1H code as the first byte preceding the first- byte code listed in the Instruction Set table. Subsequent bytes are as shown in the table. Figure 29. Opcodes for Registers (r, r1, rp) r A p Ro Fo|ms| [Px Po "9 Pa a fe 0 0 0 |po} x Po Ps oo 1 lala aca miitc 0 0 | aro| ax eee rate 0 1 | rer] ac naeontoal adic 10 | nee | oF peroneal re|lic) +s [pes] He so fale saa lel 39»PD7823x Ni FE Cc Figure 30. Opcodes for Memory Addressing Modes (mem, mod) Wer [1 orse]o oso ]o tote i Index Moco om \ jeri} O28 ose efaiea eran ieee tava oot | tte | tse | woot oro | ey | pasty | wore ty ora] oe wo seo | pa vor] ow Table 9. Bytes and Clocks for instructions With “mem” and “&mem” Operands; internal ROM (IROM) Regist Indirect Indexed Mode Base Mode Mode [DE+] woratal t+) woral3] [DE] (08) [DE+ byte) wore(DE] Instruction [MLsbyte] —_ [SP+byt0) wordt} Bytes ve 3 3 4 aa aa 4 4 5 Cock Mov ry 38 en oe on Cycles enon 1053 cer tous xCH qas oa 308 a6 1048 3371 war 1348) a7 ‘ADD, ADDS. wore ane one 1049) oe SUB, SUBC, a oT eon 2 0114 nn 12.45 XOR.CMP When intemal RAM is accessed with an Istucton having @ mem — When the extemal memory (cluding the SFR area) is accessed, the operand. the numberof bytes is the number belore the symbol (). umber atbytes i the number after the symbol (). 40NEC »PD7823x Table 10. Bytes and Clocks for instructions With “mem” and “&mem" Operands; External ROM (RAM, SFR, EMEM) Register indirect Indexed Mode Base Mode Mode (DE+) ‘word[A] THL+) ‘word[B] rae [DE+ byte] word{DE] Instruction (yt (HL+ byte) _ISP+ byte) wordHL] Bytes mom a 3 3 4 ‘&mom isu 4 4 5 Glock MOV ‘Amen cr 1119 114 146 Cycles: ran ‘Ammen “ee ett 146 187 1719 “amom,A XCH ‘Amen 148 12/16 137 148 16120 ‘Abmom ae 18/19 16/20 172 19/28 ‘ADD.ADDC, _A.mem sons 118 12/14 19115 157 sua, SUC, ; 18/20 rey ‘Aamom 161846 157 16118 18120 XOR,CMP * When (0E}, HU}, [DE] [HL], [DE] or HL-Jisspectiedas the mem ‘operand of a MOV instruction, tho instruction is used as a deciceted ‘ye ype. When the operandis &mem theinstructon i 2-bte. Table 11. Opcode Symbols ‘Symbot Meaning Bn Immediate data corresponding obit Na Immediate data corresponding ton Data -bitimmediato data cortespondingiobye LowitignByte _16-bitmmadiate data coresponding to word Sudo Lower blot data 6 tastes creeping tosacae ‘Sirofteet __Lowor6-biofiset data of 16-bladaressotspecial functionregistr (st) Lowitigh Ofset_16-bitofsot data conesponding to wordinindexed oressing Lowhigh Addr _16-btimmediate data coresponding to adr 16 iss ‘Signed? complemen data (6bis)incscating lative adcress dstancobotweontrstadcross of next insituction andbranch destination adress ae Lower 1 bits fimmediate data comespanding addr @ Lower Sits ofimmediate data cowespondingto (acess) aNEC »PD7823x Instruction Set ____Coeks Fina Operation Code (Bia 7-0) Mnemonic Operand Operation Bye IRON TRAN SFA EWEM ZAC CY” Byme 1 tu BS 2: Date Transfor Mov Abie roby 22 6 Tort 1 AAR Oa Tecan wore act = bye 3 38 8 8 dott 1010 Sacer Data wiaope ew Ope 28 oe oore 101d ter 2 2 6 oe 0010 01900 _ 0 Fe RsRe 0 Ro Ro Ar Aer 12 1101 0 RaRiPo Asatte The (adh 2 a4 8 core 0000 sacarotoe week (eae) =A 2 6 8 dere 0010 Sacre Tact acer (ea) = (ay > 78 cori 1000 Sextet - Sacro ier eer ze e D001 0000 _ Stroffeet wa wea 28 doo1 0010 Sroet Ken Ae nem Ta 612 614 G18 e168 vote 1 1 mem 00 ° Admem: Ae (amen) 25 4 HIT 149 11-19 “+00 a1 0 0 ° 7 _ [DE]. [HL [DE-=}, [OE] [HL+] or Lis desorbed as mem, these insructiona ar used as dedcatod {byte codes. he register nares desorbed a8 &nem, the nsrucions are used as dedicated 2byt6 codes: 42NEC pPD7823x Instruction Set (cont) Moemonic_ Operand Operation —__Clocks _FI898__ Operation Code (Bits 7-0) Byles iROM IRAM SFR EMEM ZACCY ByteaBItnruBs BK Data Transfer (cont) MOV moma (mom) A 4 612 614 G16 816 70101 0 mm ooo 1mm 0000. Low Ofteet High Orset ‘amomA ‘aeeri6 ‘Aslagerié (mem) =A ‘A (isseri6y ‘A+ (aiaaart6) 26 818 87 Te T9 79000 0001 101 0 mm oo00 0001 000 mad 1 mem 0000 Low Ofset High Ofteot . oo 6 ooo0 1001 Vert o000 Low Addie igh Ade 3 ano 8 2000 0007 ooo 1007 tt1t 0000 tow aad igh Ader "ager6,A “aia, PSW.ebyte PSWA (laaariey = A (ise) = 8 PEW bye PoWeA . ov 7 oo00 1001 tiit O00n Low Adie gh Ader 5 60 20 oo00 00 ooo0 10 Vat coon 1 1 Low Ads igh Ado o 107 11440 Ona "APSW Ae Psw»PD7823x Instruction Set (cont) Clocks NEC F898 Operation Code (Bits 7-0) Nremonie Operands Operation Bywe ROM TRAM SFR ENE ZACCY —ByweBtthruBs 8-0 Data Transfer (cont) xcH Ar Ane . 710) 1 RRA rer 28 oot) o10r “ORGASAa 0 Rai Ro ‘Amen Ae (mom) 24 948 12416 1620 ooo mod “0 mem 0100 Low Oteet ___ High Ofset amen A (amor) 35 ie ete 1828 oo00 0004 oOo mes 0 mem 0100 Lom Otset High ortset ‘Asaddr Ae (ead) 2 4 6 ooo 0001 Saderotet ‘Ast Rest 3 B10 8 0000 0001 0010 0001 _____Strottset cadena (ead) > (6006) 3 6M v0 oo1t 1001 Seaeratat Secer-ofet 16-BH Data Tranafor NOW m.Fwerd word rr) O48 ‘secdrp.#word—_(saddkp) © word 4 48 2 12 18 oo ~~ _ Hon Be ‘sp. word op + wd «8 2 oooo 101d Secret LowBye Hah Ove a Dew 74 6 oo10 0100 O Per O 1 PPO "AK = (e868) 2 60 8 oo001 1100 Saasofsot saderp Aandi) AK 2 8 2 oo0tNEC nPD7823x Instruction Set (cont) Clocks _Fi8G*_ Operation Code (Bits 7-0) Mnemonic Operand Operation Bytes IROM IRAM SFR EMEM ZACCY BytenB1thruBs 6-Bit Date Tranater (cont) __ MOWAXst Ake stp “10 1 oot 0008 sto sip A ° 2 ooo Ximemt Keron os 2 68 oo “AXamomt ‘AK © (Bont) W719 O° on ut imemiAK (mem) « AK on on O° ut “EmemiAK (Ameri) » AX wie eB on or ut ACY © Av byte 2 6 xxx t070 1000 7 ae saaar bye ——(sa0.GY « (eadeh + one wen xxx 0110 1000 Saar-foat Date seone~=~«RCY + ahve ° 1 wx x 000 O00 o110 1000 Strofeet Date uw Oversee 3. 7 xxx 1000 1000 _ O Ree Aa 0 Rei Ro ‘Asada ACY © A+ sade) os 6 7 8 xxx 1001 1000 Sasdi-afst Aste AGY Ars 7 10 xxx 0000 000 soo1 tooo Z Stat ‘seadrsacsr ——_(sadce,CY * (sede + (cad 28 on xxx O1t1 1000 Sadéroftset Sadératioot 45NEC yPD7823x Instruction Set (cont) —__Gioeks____ FG Operation Code (7-0) Meamonie Opernd __Opaaion Bytes ROM TRAM SFR EMEM ZACCY "oye Brive 1:81 Operation (cont) ~ 7 200 Amam ere Aviram) a en We oT Ia ODO mee oO mn 1000 Lov Ost High toot Kamen AGY=A+ (bron) 3s 01s ise ww we Xxx 0000 0008 ce Omen 1000 Low fet oh tae woe Aebre Reve Avner 2728 Tre doTe 1004 ; a Caan aca vope ~~ yew bite 1000 +o ‘Sadcr-ottset aia Gidofe «eG = ae ope OY 78 wee x pooe oot otro 1008 Brome Date 7 wererernoy ze? Tee dbeT 1o08 0 Re As Rq 0 R2Ry Ro ase eopererrer 2m ee HOO} 1008 ar ae Weve Aveesey > we 00 000K oor soot erate cease — aan Ve ates teess) «SCC Tae odit 1008 ou Saddr-oftset Sado ‘Aram AN cAnmerer eae TE BT ee OOO med omen 1004 Tow Oat igh oft Asmem, ACY & A+ (&mem) + CY 38 1015 1418 a 1620x x x 0000 0001 00 ree omen 7008 rT. on roeNEC »PD7823x Instruction Set (cont) Cocks F808 Operation code (887.0) Memosle_Operind Operation Byes ROM WAM SFR EWEN ZacCY "Byes Brtwuas BM Operation (cont) _ SUB Awtyte ACY = A-bye 22 8 xxx toto 1010 te weaatore eee adie) = SCeC T TO FOTe Sasa - ata Stoner ebro 7 www eo O00 000 ort. tote Sate ata a worer 737 yee dooo tote __ © Re Rs Ry 0 RRs Ro aoa Kev = Ace pos 8 7 6 wee dOGT F010 Suaatot aw Kore Aer > 7 ee we O DOT Teortere ~ (eadar),CY « (sadcr) — (sade) 3 39 oon xx x OT ~ sacat Sedat ‘Amon 24 819 11S WOT OAT x x x mod Tore ow Ost Hoh feet Kinen ROY = Alemany 3 Wows W410 wm we xxx 0000 00074 oe) ‘SUBC Avbye AGY © Anbyte-CY 22 6 xx ‘Sedarebye——(eadaCY (sade)-bpe-CY 87 xxx ‘shore ROY & str—bye cy cr) 4 xxx a7»PD7823x NE Cc Instruction Set (cont) __Slecke_F1ag*__ Operation Code (Bits 7-0) Mnemonic Operand Operation Bytes iROM IRAM SFR _EMEM ZACCY Byles Bt thru Bs ‘Bit Operation (cont) We oy 28 7 wee a000 101 _ _ © Res Ra 0 Re Ri Re soar ACY Aone) =C¥ agen eal elueee ees a det g(e rOFOR REL ONE Seddrotiot 7 10 xxx 0000 0001 voor toi Ast ROY A-ah_c¥ sedéreaddr ——_(6a080.CV + (sader)—(eaay «ST xxx ott or ‘Amor AGY © A-imom)—CY 4618 1S OT AT x x x 000 mod men 1 011 Low Oot Hoh Otset 38 1015 418 eH 62x xx 0000 00OF 000 nd O mem tT Ott Low Ost High Ofet IND Avovo Aw Anbrle 22 6 x Toro 1100 Date a 1100 ‘Seaaooot Data intro a= snr . 8 4 x o000 0001 ito 1100 Stotvet ate tera 23 7 x Teo0 1100 @ AaReRe 0 Rai Ao ‘Asedar Ae AN a8) 2 0 6 7 8 « toot 1100 Sacerofteet ‘Aste Ae AAG a7 0 x e000 o00t Soot i100 Stator ‘acer sadar (ad + (ead aad 3988 x oti Sedsrefisot ‘Sadcrfsot Aamem sader-#ope——_(eader) + (sacar) Abyo 3s 7 8 Ht x onNEC ».PD7823x Instruction Set (cont) ____ Cocke _Fiaosperatton Cove (te) Mnemonic operand Operation yen ROM TAM SFR _EMEM ZacCY "Bye Brinn Os ‘8-Bit Operation (cont) a0 Amer ae AN) ta ee is BT eT OO ee Omen 1100 Low Ofee a High Oteot Kimon AF AN Gey 33 tw ee em AX COON 000 mod 2 men 1100 oo ‘agnor on Awe Re AVbie 22 6 x Toro tito _ =e waderwoAe (ede) «(sad Vote > 8 0410 4490 Sat rea : Owa sir, #oyte str e strVbye: 4 9 14 x oo000 0o07 Drie tie Sate Oa 7 Tear 2 ye ee 1118 © RRs Ry 0 Rei Ro Rear «AWA a Seasraret re weaver 2? xe eet oot tite __ sata irae eats = wadanvends) ~~ SC~ a Fatt sacs Aen eave mee Wis eT Ge OO med o mm ttre Low Otte oo Aamem: Ae AViamem) 35 1015 1418 160 16-20 x oo00 ooo 200 me own tthe Low Ota igh oft 49NEC »PD7823x Instruction Set (cont) —__Clockt_F1898__ Operation Code (Bits 7-0) Mnemonic Operand Operation Byes IRON TRAM SFR_EWEN ZACCY — Byten BtthrUBS Bt Operation cont) XORAwoyto Ae AMbyte 2 2. 6 x o 1tot Daa ‘Sader one (Sader) « (saccrybyie 2 35 9 x otro at04 sedeeotiset Data warone Caw ave 77 rm 7 ooo0 ooo o1to ston Sreteer Data 1 rer 2 3 7 ® 1000 1107 0 ReAsRq_ 0 Re Rs Ro “Kener he Av eed ee re Saasarat “net Ae AMst) 3 7 10 x oo00 00071 root tier a Tadaraossr ada = eawywieaaey =~ eats 1404 “Sado offset Sader tea ‘Amem Re Reem) 24 B13 15 WO? 1847 x O00 mo o mm 1 ow Oteet : High Ofet Kamen Ae Aviamen) 3s We 1 wo ox 9900 OOF 000 md “O mem 1101 tow Oftsat High Otsat MP Atoyte A-byte 2 2 6 “Vee toro ditt oma i ‘saddr.#byie (sa0dr) —byte 3 35 9 1 xxx OvtO 444d Secret Data “shtbyo ofr—byte a7 py xxx 0000 0001 orto 494 —____Stratiset oweNi Fi Cc p»PD7823x Instruction Set (cont) Clocks Fl0g8_ Operation Code (Bits 7-0) Mnemonic _Operand Operation Bytes IROM RAM SFR EMEM ZACCY Bytes B1 thru Bs {Bit Operation (cont) — — cures or 37 xe xt000 1141 0 ReAigRe 0 Res Ro ‘Asad ‘A=(ea5) 2 a5 6 7 8 «xxt001 1117 = Sadcroitset Ast Anstr 3 7 10 xxx 0000 0001 sadcrsaddr (sade) (ead) 3 a7 9 exe ‘Amen A-(mom) 24 81S 1618 WHT ISI7 KX xX ‘Amer ‘A-(émem) 35 1015 1418 16 1620 x x x High orto 16-Bit Operation ADDW AX Fword AKGY © AX word a 6 9 xxx 0010 11014 Low Byte __ High Bye aK RXOY © AKT 2 6 8 xxx 1000 1000 O00 thro aX saserp "AK.GY = AX = (sascrp) 2 7m 8 xxx OooT 1104 ‘Saddrofeot aap KEY © AX stp 318 18 xxx 0000 o SUBW AK eword AKCY © AX- word 2 4 8 xe x00 AKI AKGY © AX=Ip 2 6 8 xe x10 ° “Aksaddep AXCY © AX (sadaip) 2 om 8 19 x x00 ‘Sassroteet ‘1p»PD7823x Instruction Set (cont) NEC __Clocka_ ‘Operation Code (Bits 7-0) Mnemonic _Operend Operation Byles iROM TRAM SFA EMEM ZACCY Byles Br thruBs 16-Bit Operation (cont) = Suaw —AKsp AKGY « AX= sip 28 16 xxx 0000 0001 oor vite Sroteet GuPW Awad AK word > 38 ze x OOtO TtaT tow te Hoheve axe aX 2 8 7 xxx d000 1441 oe00 1mmO Kees AK (000) 2 00 8 Tax ooo) 4144 _ Sacco ep mr 3 18 xxx 0000 0001 ooo 4 - Sroet ‘Mutipiication Division mur ewe 2 2% oooo 0408 _ 00.0.0 1 RaRiRo pvuw or ‘axtquotent (remainder) = 2 7" 76 0000 010 7 ee 0001 1 Rah Ay Inerement/ Decrement - =e ea TEs eee dar (enh) + Gad + 228 6 7 xx @o10 0410 seats oe Ter _ 123 Ee 1400 1 ReRRy er (ood = Gada—* Fe aaay ex Oo1e Ota Suadrotect Now Deptt “1 3 3 - 0100 OTFiP oeow es) 133 ooo 1 Pe ‘ShitiRotate _ FOR en (Orne tater iw) 2 orm Sein yoott 0000 : _ pnuenes. "0-7 1 NaNs_NoR2 Ri Fo ' roe (Gira nines wd 2 ara Sein x o011 0001 Stes. n-8" Gatiiacianirane rans 52.Ni Fi Cc »PD7823x Instruction Set (cont) Clocks Moemonle_Operand Operation Bytes iROM_IRAM SFR_EMEM ‘Shift/Rotate (cont) ORC «a (Yao Oita nim) 2 Gen SHIH animes, ROG tn (CemanWiimieig) 2 342m S420 animes, 0-0-7 SHR rn (Ht Otma etm 2 342n BHR anes, n=0-7| an (a mronOtmrm im) «2 S42N HRA amiimes.n=0-7 SHRW pn (Y= moms Orms~ «2 9080 Stan ‘Boy xntines, 90-7 SW pa (Chait 0.Pyee «2 SHEN HSN ‘eq xntines, =0-7 ORS Asow(memijzg.(memiing 2 28 2 4 = Aga (emt.g = (mera ‘Smemt Aspe tkremtisa(imemtirg 3 28 2S? © ooo Ago. (&memt}s.o © (amemt}7-4 $ oie4 1 1th FOL emt Aor (nomtiraimenzg 2 2 27 35 3 ° o104 Ago emir = (mera ; Amero “amemi ee ° ooo Ag (morta © (amamtis.o © o1074 1 11mNEC »PD7823x Instruction Set (cont) ___Slocks __Fi89®__ Operation Code (Bits 7-0) Mnemonic Operand Operation Byte IROM IRAM SFR EMEM ZACCY Bytes Bt thru BS ‘BCD Adjustment ‘ADIBA Decimalacjustaccumulatorator 1 3 3 xxx 0000 1110 addon ‘ADUBS Decimaladjustaccumulatorafier -t 3 3 xxx oooo 1t1tt dation ‘Bit Manipulation Movi Gy.saddrbin CY « (sada) 3 67 89 8 W x 0000 1000 00 0 0 0 By8; By Sadér-fiset CY.strbit CY « str aan ° x 0000 1000 0.000 1 82816 ‘Strotiset CYA CY eAbt 2 5 7 x 0000 0011 0000 1 868 cyxet CY «Xt 2 5 7 x 0000 0011 00.0 0 0 B&B ‘Strotiset CYPSWbt | CY“ PSW.bt 2 5 7 x 0000 0010 00.00 0 BBB ‘seccrbRCY ——(eaddrbit) « CY 3 en 12 4 4 ooo0 1000 0001 0 BBB ‘Saddroftset ‘SrbI.GY ‘irbit = CY 3 (2 “ ooo0 1000 00 01 1 8:8 Bp Strofaet AbICY ‘Abit = CY 2 8 Ww 0000 004 0001 1 88:8 LOY Dit = CY, 2 8 oooo ooNt 00.0 1 0 B2ByBo ‘Steotiset PSWDLCY PWD= CY 2 7 8 xx oo00 0010 00 0 1 0 8,8; 8 ANDI Cyadarbn CY «= CYA(saddrbit) 3s 7 8 x 0000 1000 001 0 0 8:B;8 Sedacatcat