TP 1 Computer Systems II - Yonder Arellano
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ScribdTranslationsTP 1 Computer Systems II - Yonder Arellano
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ScribdTranslationsUNIVERSIDAD ABIERTA INTERAMERICANA FACULTY
OF INFORMATION TECHNOLOGY
Subject: Computer Systems II
First and Last name: Yonder Arellano
DNI: 95646039
Course: 1A
PRACTICAL WORK N° 1
LOGIC CIRCUITS - PROCESSOR MODEL
1) Construct the operation table of a circuit that recognizes only the combination 011 and draw the
corresponding circuit.
2) Construct the operation table of a 2-output circuit that recognizes only combinations 010 and 011
(one output to recognize each combination). Construct the corresponding circuit. Verify that the
circuit complies with the table for 010 and 110
3) Indicate the operation table of a circuit that recognizes each of the possible combinations of 3 bits.
Construct the corresponding circuit. Verify compliance with the table for 010 and 110. What is this
circuit called and how is it used in memory and PCU?
It is called a decoder and we use it for bus redirection.
4) Construct the operation table of a circuit with a single output, which is worth 1 if any of the
following two combinations (010 or 011) are activated at the inputs. Construct the corresponding
circuit. Verify compliance with the table for entries 010 and 110.
5) Given the table of an X-OR construct a circuit with AND and OR that complies with this table.
6) Construct the operation table of a circuit that in its 4 inputs receives any two 2-bit numbers, and
that the binary combination that appears in its 4 outputs corresponds to the product of those two
numbers present in its inputs. Build the circuit and verify for 11 x 10
7) Construct an ALU to add or subtract two 4-bit numbers and generate the flags after each operation.
Then test the circuit with the following operations with integers, and determine the value of the
flags in circuits, after having done the math on paper: (- 7) + (- 3) ; (- 7) - (- 3) .
8) Explain circuitously how the flag C is not inverted in addition and is inverted in subtraction.
9) Explain in circuits that if the output that gives the value of the flag V is 1, it corresponds to the fact
that two naturals representing integers of equal sign are added together and the result is a natural
representing an integer of opposite sign.
10) Draw a "D latch" flip flop with its three gates. Then analyze each of the following two sequences
I. a) with Ck=0 is retaining a zero. b) with Ck=1 is prepared to store a one. c) with Ck=0 ended up
keeping a zero.
The value of D does not change to 1 when CK=1 therefore Q remains with value 0.
II. a) with Ck= 0 is storing a zero. b) with Ck=1 is prepared to store a 1. c) ends by keeping a one.
What do you suppose happened in the first sequence?
The value of D changes to 1 when CK=1 so Q remains with value 1.
11) For the instants of point 10) draw the time diagrams of Ck, D and Q.
12) Explain why when Ck = 1 the circuit behaves as a wire between Q and D and does not retain
13) Given on the blackboard the following variation of Ck and D determine over time how Q will vary
14) Given a register with 2 flip flops M-E that when Ck = 0 stores 10 and receives from outside
11. Draw the complete register with its 4 flip flops (2 Masters - 2 Slaves), indicating which
ones retain, which ones copy and the 1/0 value of the wires. Idem assuming that Ck = 1 and
then Ck = 0 receiving from outside 00.
15) Using 3 blank processor model sheets, describe the ordering and execution of an instruction
with operation code 1111, which is located at address 1010 and orders to jump to 0111 in case
flag Z=1. Determine the value of the associated data and on each sheet indicate the
information movements and which control lines must be activated to allow such movements.
Indicate values in buses, UAL and registers, complete in the registers that change, the values
of Masters and Slaves, both for the zero value of the Clock, as well as for the value one.