DEM Midsem

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BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI

M.S Software Engineering (SAP Labs, Bangalore)


First Semester 2021-2022 - Mid Term examination (Open Book)
SESAP ZC261: Digital Electronics and Microprocessors
Date: 31st October 2021 No. of Pages:
Weightage: 30% Time: 2 hours

1. Solve the following


a. Find the 8’s complement of (647)8
b. Perform 90210 - 89910 using complements
c. Represent +9 and -9 in signed 8-bit representation (2s complement for
negative numbers)

2. For the given Boolean function F(a,b,c,d) = b’d’ + bd’ + bc + ad’ + c’d’
a. Express F in canonical form. (sum of min terms and product of max terms).
b. Identify prime and essential prime implicants
c. Give minimized two level AND-OR implementation
d. Give minimized two level NOR-NOR implementation

3. Identify the following for the given sequential circuit


a) Flip Flop Input equations
b) State transition table
c) State diagram
d) Explain in words what the circuit does
e) Classify as Mealy or Moore

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4. Draw the sequential circuit for the below state table with JK flip flops.
What can you say about this circuit and its self-correcting ability?
QA QB QA(t+1) QB(t+1) JA KA JB KB
0 0 0 1
0 1 1 0
1 0 0 0
1 1 0 0

5. You are given a 3-bit Synchronous counter with Asynchronous Clear capability.
(Counter works on positive edge of clock)
a. How will you construct a Mod-5 counter from the 3-bit counter?
b. Show timing diagram for 8 clock cycles for all 3 outputs of the counter.
c. If 1MHz clock is given as input clock, what is the frequency and duty cycle
of the 3 output bits.

6. For the given MUX implementation, do the following


a. Find the Boolean function’s sum of min terms expression for the given
MUX implementation
b. Implement the sum of minters with a 4:1 MUX with W and X given as
inputs to S1 and S0 selection lines
c. Show the decoder implementation of the same Boolean function with a 4:16
Decoder.

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7. Design a 9s complement circuit for a valid BCD.
Ex - If input is 1000, 9s complement of it would be 0001 (9-8 =1)

Given to you is a Binary Adder, that can either add B3B2B1B0 with A3A2A1A0.
You are also given XOR gates and other minimal gates if required.
You don’t have to draw the internals of Binary Adder – you can assume it is given
to you and can be used as a black box.

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