Analysis and Effect of Switching Frequency and

Voltage Levels on Total Harmonic Distortion

in Multilevel Inverters Fed BLDC Drive

A. Puma Chandra Rao Y.P.Obulesh Ch. Sai Babu

EEE Department,Prasad V. Potluri EEE Department,Lakireddy Bali EEE Department, lawaharlal Nehru
Siddhartha Institute of Technology, Reddy College of Engineering, Technological University Kakinada,
Vijayawada,Andhra Pradesh,India Mylavaram,Andhra Pradesh,India Kakinada,Andhra Pradesh,India
E-mail: alapati.purna@yahoo.com E-mail: ypobulesh@yahoo.co.in E-mail: chs_eee@yahoo.co.in

Abstract-Multilevel converter technology has emerged as Multilevel inverters include an array of power semiconductors
a very important alternative in the area of high-power and capacitor voltage sources, the output of which generate
medium-voltage energy control. Several topologies for voltages with stepped waveforms. The commutation of the
multilevel inverters have been proposed over the years, the switches permits the addition of the capacitor voltages,
most popular cascaded H-bridge apart from other which reach high voltage at the output, while the power
multilevel inverters is the capability of utilizing different dc semiconductors must withstand only reduced voltages
voltages on the individual H-bridge cells which results in [1],[2],[3]. Figure 1 shows a schematic diagram of one
splitting the power conversion amongst higher-voltage phase leg of inverters with different numbers of levels, for
lower-frequency and lower-voltage higher-frequency which the action of the power semiconductors is represented
inverters. Considering the cascaded inverter to be one unit, by an ideal switch with several positions. A two-level
it can be seen that a higher number of voltage levels are inverter generates an output voltage with two values (levels)
available for a given number of semiconductor devices. In with respect to the negative terminal of the capacitor Figure
this paper multilevel converter with different voltage levels are l(a), while the three-level inverter generates three voltages,
considered and simulation results are presented in terms of and so on.
total harmonic distortion (THD). Finally generalized The term multilevel starts with the three-level inverter
expression for highest order harmonic based on switching introduced by Nabae et al. By increasing the number of
frequency and number of levels is derived and fed to BLDC levels in the inverter, the output voltages have more steps
drive. generating a staircase waveform, which has a reduced
Keywords: Cascaded H-Bridge (CHB) Multilevel Inverter
harmonic distortion [4], [5]. However, a high number of
levels increases the control complexity and introduces
(MLI), Total Harmonic Distortion (THD), Pulse Width
voltage imbalance problems. Three different topologies
Modulation (PWM),Switching Frequency.
have been proposed for multilevel inverters: diode-clamped
or neutral point clamped, flying capacitors clamped and
I. INTRODUCTION cascaded multi cell with separate dc sources. In addition,
several modulation and control strategies have been developed
In High performance applications reliability and low
or adopted for multilevel inverters including the following:
maintenance are essential in the aerospace industries and
multilevel sinusoidal pulse width modulation (SPWM).
computer peripheral this force for the development of
brushless d.c. motors. Now large numbers of brushless d.c.
motors are used,mostly in size up to a few hundred watts. The
II vt Jl
small ratings machine is increasingly made with all the
power electronics circuits and control integrated at one end VeT 1 _ V tJ'-"
of the motor, so that they can be directly retrofitted as a
alternate for a conventional d.c. motor. Higher specific ,'£1,,-" +" Ur 1"' : 'Jl
. jv
J
a
U tVll
outputs can be achieved because all the heat dissipating area
is on the stator, cooling is much better than in a
conventional motor. The rotor inertia can also be less than
(&)
. .

(b)
. . 0Va v�Ll (c)
. . o

that of a conventional machine,which means that the torque

FIG. 1: ONE PHASE LEG OF AN INVERTER WITH (A) Two LEVELS,
to inertia ratio is higher and,giving a higher acceleration. (B) THREE LEVELS, AND (C) N-LEVELS
978-1-4673-4603-0/12/$31.00 © 2012 IEEE
66 Proceedings of7'h International Conference on Intelligent Systems and Control (ISCO 2013)

A multilevel converter has several advantages over a Disadvantages

conventional two-level converter that uses high switching
frequency pulse width modulation (PWM) [6 ],[7],[8]. The Separate dc sources are required for each of the H-bridges.
attractive features of a multilevel converter are,(a) Staircase This will limit its application to products that already have
waveform quality: Multilevel converters not only can generate multiple SDCSs readily available.
the output voltages with very low distortion, but also can
reduce the dv/dt stresses; therefore electromagnetic

t .-----+------t
� --------�--�
compatibility (EMC) problems can be reduced. (b) Comrnon­ SDCS
Va((m- I J,2/
mode (CM) voltage: Multilevel converters produce smaller
CM voltage; therefore, the stress in the bearings of a motor
connected to a multilevel motor drive can be reduced. (c) Input
current: Multilevel converters can draw input current with
low distortion. (d) Switching frequency: Multilevel converters SDCS
Va({m-1J,2-1/
can operate at both fundamental switching frequency and
high switching frequency PWM. It should be noted that
lower switching frequency usually means lower switching
loss and higher efficiency. There are different approaches for

tr--+----+
the selection of switching techniques for the multilevel
inverters. Finally a five level CHB inverter with level shifted Va2
SDCS
carrier is applied for BLDC drive and simulation results are
presented.

II. CASCADED H-BRIDGE MULTILEVEL INVERTER

n --------
Va1 t�-- �--
---- � SDCS

The N-Ievel cascaded H-bridge, multilevel inverter comprises

Vz(N-l) series connected single phase H-bridges per phase, for
which each H-bridge has its own isolated dc source. Three FIG. 2: SINGLE-PHASE STRUCTURE OF A MULTILEVEL
output voltages are possible, ±Vs, and zero, giving a total CASCADED H-BRlDGE INVERTER
number of states of 3V,(N-l) ,where N is odd. Figure 2 shows
one phase of a n-level cascaded H-bridge inverter. A. Full H-Bridge-Three Level Inverter
The cascaded H-bridge multilevel inverter is based on Figure 3 shows the Full H-Bridge Configuration. By using
mUltiple two level inverter outputs (each H-bridge),with the single H-Bridge we can get 2 and 3 voltage levels. The
output of each phase shifted. Despite four diodes and number output voltage levels of cascaded Full H-Bridge
switches, it achieves the greatest number of output voltage inverter are given by 2n+1 and voltage step of each level is
levels for the fewest switches. given by Vdc/n. Where n is number of H-bridges inverter
Its main limitation lies in its need for isolated power sources for connected in cascaded. The switching table is given in
each level and for each phase,although for VA compensation, Table 1 and 2.
capacitors replace the dc supplies, and the necessary capacitor
energy is only to replace losses due to inverter losses. Its
modular structure of identical H-bridges is a positive feature. 52..J
• The number of levels in the line-to-Iine voltage
wavefonn will be k = 2N -1. Vout
Vdc
• while the number of levels in the line to load neutral of
a star (wye) load will be p = 2k- 1. 5�
• The number of capacitors or isolated supplies required
per phase is Ncap = Vz(N - 1).
hases
• The number of possible switch states is nstates = N p . FIG. 3: FuLL H-BRIDGE INVERTER
• The number of switches in each leg is Sn = 2(N - 1).
TABLE 1: SWITCHING TABLE FOR FULL H-BRlDGE INVERTER

Advantages Switches Turn ON Voltage Level

1. The number of possible output voltage levels is more SI, S2 Vdc/2
than twice the number of dc sources (m = 2s + 1). S3, S4 -Vdc/2
2. The series of H-bridges makes for modularized layout
and packaging. This will enable the manufacturing Table 2 shows the Switching table for Full H-Bridge for
process to be done more quickly and cheaply. three level inverter.
Analysis and Effect ofSwitching Frequency and Voltage Levels... 67

TABLE 2: SWITCHING TABLE FOR FULL H BRIDGE Figure 5 Shows the seven level multilevel inverter and
THREE LEVEL INVERTER Table 4 shows the switching states of the seven level CHB
Switches Turn ON Voltage Level inverter.
SI, S2 Vdc/2
TABLE 4: SWITCHING TABLE FOR FuLL H-BRIDGE
S3,S4 -Vdc/2 OF SEVEN LEVEL INVERTER
S2,S4 °
Switches Turn ON Voltage Level

SI, S2, S6, S8, SI0, SI2 Vdc13

B. Five Level CHB Inverter
SI, S2, S6, S8, S10, S12 2Vdc/3
Figure 4 Shows the five level multilevel inverter and Table
III shows the switching states of the 5 level inverter. Here SI, S2, S5, S6, S9, S10 Vdc
even though we have eight switches at any switching state
S2, S4, S6, S8, S10, S12 °
only two switches are on/off at a voltage level of Vdc/2, so
switching losses are reduced. In three level inverter dv/dt is S3, S4, S6, S8 SIO, SI2 -Vdc/3
Vdc, but in five level inverter dv/dt is Vdc/2. As dv/dt
S3, S4, S6, S8, S10, S12 -2Vdc/3
reduces the stress on switches reduces and EMI reduces.
S3, S4, S7, S8, SII, SI2 -Vdc

III. SIMULAnON RESULTS

The simulation is carried out in Matlab/Simulink software

and results are presented. The simulation parameters are
Vindc = 100 v,Switching frequency is 3050 Hz.

A. Three Level H Bridge Inverter with Sinusoidal

PWM
FIG. 4: FIVE LEVEL CHB INVERTER Figure 6 shows the Simulink Model of three level H bridge
inverter with sinusoidal PWM technique. Figure 7 shows the
TABLE 3: SWITCHING TABLE FOR FULL H-BRIDGE
output voltage waveform of the single phase three level H
OF FIVE LEVEL INVERTER
bridge inverter with sinusoidal PWM technique. From
Switches Turn ON Voltage Level Figure 7 it is observe the dv/dt of three level H bridge inverter
SI, S2, S6, S8 Vdc/2 with sinusoidal PWM is 100 V. The FFT analyses of output
voltage wave form is shown in Figure 8. From this figure it is
SI, S2, S5, S6 Vdc
observed that the dominant harmonic is shifted to high
S2, S4, S6, S8 °
frequency zone and its frequency is 5950 and 6250 Hz.
S3, S4, S6, S8 -Vdcl2
S3, S4, S7, S8 -Vdc

C. Seven Level CHB Inverter

FIG. 6: SIMULINK MODEL OF THREE LEVEL H BRIDGE

INVERTER WITH SINUSOIDAL PWM
FIG. 5: SEVEN LEVEL CHB INVERTER
68 Proceedings of7'h International Conference on Intelligent Systems and Control (ISCO 2013)

FIG. 10: OUTPUT VOLTAGE WAVEFORM OF FIVE

LEVEL CHB INVERTER
FIG. 7: OUTPUT VOLTAGE WAVEFORM OF THREE LEVELS H-BRIDGE
INVERTER WITH SINUSOIDAL PWM Figure 10 shows the output voltage waveform of five level
CHB inverter with phase shifted carrier sinusoidal PWM.
From Figure 10 it is observed that the dv/dt of five level
Fundamental (50Hz) = 100.1 • THD= 52.05%
CHB inverter is 50 V. The FFT analyses of output voltage
20 ------------ �-------- wave form is shown in Figure 11. From this figure it is
observed that the dominant harmonic is shifted to further
. .
--_. --_ .. --_. . . . . . -_ .. --_. ---�. --_. --- high frequency zone and its frequency is 11950 and 12450 Hz

Fundamental (50Hz) = 200 ,THO= 26.92%

:!l' 5 12

2000 4000 6000

Frequency (Hz)

FIG. 8: SPECTRUM ANALYSIS OF OUTPUT VOLTAGE OF THREE LEVEL

H-BRIDGE INVERTER WITH SINUSOIDAL PWM

B. CHB Five Level Inverter with Sinusoidal PWM 18000

Frequency (Hz)
Figure 9 shows the Simulink Model of five level CHB inverter
FIG. 11: SPECTRUM ANALYSIS OF OUTPUT VOLTAGE
with phase shifted carrier sinusoidal PWM technique. OF FIVE LEVEL CHB INVERTER

C. CHB Seven Level Inverter with Sinusoidal PWM

�
. . -
0
. -'

� -���.
�
. =
.o'!ncI<lrdoz- ��
__ ... _

FIG. 9: SlMULlNK MODEL OF FIVE LEVEL CHB INVERTER WITH FIG. 12: SlMULlNK MODEL OF SEVEN LEVEL CHB INVERTER
PHASE SHIFTED CARRIER SINUSOIDAL PWM WITH PHASE SHIFTED CARRIER SINUSOIDAL PWM
Analysis and Effect ofSwitching Frequency and Voltage Levels... 69

TABLE 5: EFFECT OF VOLTAGE LEVELS AND SWITCHING

FREQUENCY ON DOMINANT HARMONIC
Switching Dominant
No. ofLevels Frequency in Harmonic
HZ Frequency
Three level H bridge 3050 5950 and 6250
inverter with Sinusoidal
PWM
CHB Five level 3050 11950 and 12450
inverter with Sinusoidal
PWM

FIG. 13: OUTPUT VOLTAGE WAVEFORM OF SEVEN LEVEL CHB CHB Seven level 3050 17950 and 18650
INVERTER WITH SINUSOIDAL PWM inverter with Sinusoidal
PWM
Figure 12 shows the Simulink Model of seven level CHB
inverter with phase shifted carrier sinusoidal PWM decreases the switching losses. So if we want to use
technique. The seven level CHB inverter with phase shifted multilevel inverter in place of three level inverter, first we
carrier sinusoidal PWM output voltage waveform is shown need to find a dominant frequency for the given switching
in Figure 13. From Figure 13 it is found that the dv/dt of seven frequency in three level inverter. Substitute this dominant
level inverter is 33.33 V. The FFT analyses of output voltage frequency and number of levels in equation 1 and find the
wave form is shown in Figure 14. From this figure it is switching frequency of the multilevel inverter. For example
observed that the dominant harmonic is shifted to further high the dominant frequency of three level inverter is 5950 Hz
frequency zone and its frequency is 17950 and 18650 Hz. for a switching frequency of 3050 Hz. If we are using a
seven level inverter to get the same dominant frequency the
switching frequency of multilevel inverter is 1050 Hz. The
Fundamental (50Hz) = 300.5, THD= 18.04%
results are shown in Figure 15 and Figure 16.
,, ,, ,,
---.--------,---------,------- ,
--------,-----------------
,, ,, ,,
,, ,, ,,
, , ,
------,--------,---------,------- , ,
-------------------------
400 ,----�-�-�-_,__-��-�-�-__,__�
, ,, ,,
,
, ,
------,--------,---------,-------
, ,
,, ,
,
------,-------------------------- 300
, , ,, , ,, ,, ,,
______ £ ________ J __________________ '- _ ______ • ________ .J_________,________
,, ,, ,, ,, ,, ,, ,, 200
,, ,
, ,
, ,,, ,,, ,,, ,,,
, , ,
______ , ________ J _________,_________'-. ______ • ________.J _________,________
,, ,, ,, ,, ,, ,, ,,
,, ,, ,, ,, ,, ,, ,, 100
, , , , ,
-----_._-------"--------_._--------'-- -----_._--------'--------_._----
, ,
. . . . . . .
,, ,,

-100
Frequency (Hz)

FIG. 14: SPECTRUM ANALYSIS OF OUTPUT VOLTAGE OF SEVEN -200

LEVEL CHB INVERTER WITH PHASE SHIFTED CARRIER

-300
SINUSOIDAL PWM

From the Table 5 it is observed that by fixing the switching

FIG. 15: OUTPUT VOLTAGE WAVEFORM OF SEVEN LEVEL CHB
frequency and when we increase the nwnber of levels the INVERTER WHEN THE SWITCHING FREQUENCY IS 1050 Hz
dominant harmonic frequency will increase.
The generalized expression for dominant harmonic is, Fundamental (50Hz) = 100.1 ,THD= 52.05%

F dominan = Fswitching X (levels-I) ± (levels) x Ffundmental ... (1)

20

The above expression is valid for inverters whose level is

------------ . -------

greater than or equal to 3. For example for a five level

inverter,
------------,-------

Fdominant= 3050 x (5- 1) ± (5) x 50

------ . . . . . .. . � . . .

= 11950 and 12450 Hz

We are getting dominant frequency same as in Table V i.e. 800J 10000 12000
11950 and 12450. From this it is clear that by fixing the Frequency (Hz)

dominant harmonic as we increase the number of voltage FIG. 16: Spectrum Analysis of Output Voltage of Seven Level
levels, switching frequency will decreases, which in turn eHB when the Switching Frequency is 1050 Hz
70 Proceedings of7'h international Conference on intelligent Systems and Control (iSCO 20i3)

D. 5 Level CHB MLI Fed BLDC Motor The stator back-emf for each phase is shown in Figure 20
and behaves similar to the stator currents.

Time (sec)

FIG. 20: THREE PHASE STATOR BACK-EMFS

FIG. 17: SIMULATION OF THE 5-LEVEL CHB MLI FED BLDC MOTOR

The proposed control strategy for the 5 level Cascaded H­

Bridge (CHB) multilevel inverter fed BLDC motor with .

level shifted PWM modulation technique has developed = '.

.
. ..
.
..
.
..
.
..
.
..

....
..
..
.
.

. .
.. .. ..

. .... .
..
..
..
.
..
.
..
.
. .
.
.
..

.'
. . .
..
.
..

.
using Matlab/Simulink and results are presented. Figure 17 0 .. --... .... ....
, . .
. . . . . . _ _ ...... ....... _ _ . . . _ _
.. .. .. .. ..
...c ... ..... ....
.
.. .... ... . .....
. .. . .
.... .... ....
..
.... .... ....
. .. .. .
.... ..... ..... .
..
.....
..

.,... .. . . -,.
·100 " " ,
.. . .. .. ;
shows the block diagram of the Level Shifted Carrier PWM
200 · ·· ·· .. , .. . . .. .. .. .. .. ..
-
Tmi.(Sec)
five level CHB MLI fed BLDC Motor. The behavior of the
generated electromagnetic torque is also of vital importance. FIG. 21: FIVE LEVEL OUTPUT VOLTAGES

Figure 18 and Figure 19 shows the generated torque and

output speed of the level shifted carrier PWM five level Figure 21 shows the five level three phase output voltage of
CHB inverter fed BLDC motor. the CHB level shifted PWM Inverter

V. CONCLUSION

This paper has given a brief summary of different types of

multilevel inverters and their circuit topologies for BLDC
application. Today, more number of and more commercial
products are based on the multilevel inverter structure. This
paper covers the fundamental principle of different
multilevel inverters which has been introduced systematically.
The intention was simply to provide ground work to readers
interested in looking back on the evolution of multilevel
inverter technologies. In this paper, we had simulated
FIG. 18: ELECTRO MAGNETIC TORQUE OF 5-LEVEL multilevel converters with different voltage levels and
CHB INVERTER FED BLDC MOTOR simulation results of voltage output and THD are presented
and applied to the BLDC motor. A generalized expression
for highest order harmonic based on switching frequency
and number of levels is derived and Matlab/Simulink
models are developed.

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