Chapter 6.

Converter Circuits

• Where do the boost,

6.1. Circuit manipulations buck-boost, and other
converters originate?
6.2. A short list of • How can we obtain a
converters converter having given
desired properties?
6.3. Transformer isolation
• What converters are
6.4. Converter evaluation possible?

and design • How can we obtain

transformer isolation in a
6.5. Summary of key converter?
points • For a given application,
which converter is best?
 6.1. Circuit Manipulations

L
1
+

2
Vg + C R V
–

Begin with buck converter: derived in Chapter 1 from first principles

• Switch changes dc component, low-pass filter removes
switching harmonics
• Conversion ratio is M = D
 6.1.1. Inversion of source and load

Interchange power input and output ports of a converter

Buck converter example
V2 = DV1
Port 1 Port 2
L
1

+ +
2
+ V1 V2
–
– –

Power flow
 Inversion of source and load

Interchange power source and load:

Port 1 Port 2
L
1

+ +
2
V1 V2 +
–
– –

Power flow

V2 = DV1 1
V1 = V2
D
 Realization of switches
as in Chapter 4

Port 1 Port 2
• Reversal of power L
flow requires new
realization of + +
switches
V1 V2 +
–
• Transistor conducts
when switch is in – –
position 2
• Interchange of D Power flow
and D’

V1 = 1 V2 Inversion of buck converter yields boost converter

D'
 6.1.2. Cascade connection of converters

Converter 1 + Converter 2 +

Vg + V1 V
– V1 V = M (D)
= M 1(D) V1 2
Vg – –

V1 = M 1 (D)Vg
V = M(D) = M (D)M (D)
Vg 1 2
V = M 2 (D)V1
 Example: buck cascaded by boost

L1 L2 2
1
+ +

2 1
Vg + C1 V1 C2 R V
–

– –
{
{
Buck converter Boost converter

V1
=D
Vg
V = D
Vg 1 – D
V = 1
V1 1 – D
 Buck cascaded by boost:
simplification of internal filter

Remove capacitor C1
L1 L2 2
1
+

2 1
Vg + C2 R V
–

Combine inductors L1 and L2

1 L iL 2
+

2 1 Noninverting
Vg + V
– buck-boost
converter
–
 Noninverting buck-boost converter

1 L iL 2
+

2 1
Vg + V
–

subinterval 1 subinterval 2

+ +
iL

Vg + V Vg + V
– –
iL
– –
 Reversal of output voltage polarity

subinterval 1 subinterval 2
+ +
iL

Vg + V Vg + V
noninverting – –
buck-boost iL
– –

+ iL +
iL

inverting Vg + V Vg + V
– –
buck-boost
– –
 Reduction of number of switches:
inverting buck-boost

Subinterval 1 Subinterval 2
+ iL +
iL

Vg + V Vg + V
– –

– –

One side of inductor always connected to ground

— hence, only one SPDT switch needed:

1 2 +

iL V =– D
Vg + V Vg 1–D
–

–
 Discussion: cascade connections

• Properties of buck-boost converter follow from its derivation

as buck cascaded by boost
Equivalent circuit model: buck 1:D transformer cascaded by boost
D’:1 transformer
Pulsating input current of buck converter
Pulsating output current of boost converter
• Other cascade connections are possible
Cuk converter: boost cascaded by buck
 6.1.3. Rotation of three-terminal cell

e - t er mi na l
Treat inductor and re ce
Th

ll
SPDT switch as three- A a 1 b B
terminal cell: +

2
Vg + v
– c
C
–

Three-terminal cell can be connected between source and load in three

nontrivial distinct ways:
a-A b-B c-C buck converter
a-C b-A c-B boost converter
a-A b-C c-B buck-boost converter
 Rotation of a dual three-terminal network

A capacitor and SPDT e - t er m i n a l

re c

Th
switch as a three-

el l
1
terminal cell: A a b B +

2
Vg + v
–
c
C –

Three-terminal cell can be connected between source and load in three

nontrivial distinct ways:
a-A b-B c-C buck converter with L-C input filter
a-C b-A c-B boost converter with L-C output filter
a-A b-C c-B Cuk converter
 6.1.4. Differential connection of load
to obtain bipolar output voltage

dc source load

Converter 1 +

V1 Differential load
V1 = M(D) Vg + voltage is
–
V
V = V1 – V2
–
Vg + D
– The outputs V1 and V2
may both be positive,
Converter 2 but the differential
+ output voltage V can be
V2 positive or negative.
V2 = M(D') Vg
–

D'
 Differential connection using two buck converters

Buck converter 1

}
1

+ Converter #1 transistor
2 driven with duty cycle D
V1
+
– Converter #2 transistor
V driven with duty cycle
+
– complement D’
Vg
–
Differential load voltage
2 is
1
+ V = DVg – D'V g
V2
Simplify:
–
V = (2D – 1)Vg
{
Buck converter 2
 Conversion ratio M(D),
differentially-connected buck converters

V = (2D – 1)Vg
M(D)
1

0
0.5 1 D

–1
 6.2. A short list of converters

An infinite number of converters are possible, which contain switches

embedded in a network of inductors and capacitors
Two simple classes of converters are listed here:
• Single-input single-output converters containing a single
inductor. The switching period is divided into two subintervals.
This class contains eight converters.
• Single-input single-output converters containing two inductors.
The switching period is divided into two subintervals. Several of
the more interesting members of this class are listed.
 Single-input single-output converters
containing one inductor

• Use switches to connect inductor between source and load, in one

manner during first subinterval and in another during second subinterval
• There are a limited number of ways to do this, so all possible
combinations can be found
• After elimination of degenerate and redundant cases, eight converters
are found:
dc-dc converters
buck boost buck-boost noninverting buck-boost
dc-ac converters
bridge Watkins-Johnson
ac-dc converters
current-fed bridge inverse of Watkins-Johnson
 Converters producing a unipolar output voltage

1. Buck M(D) = D
M(D)
1 1
+

2
Vg + V 0.5
–

– 0
0 0.5 1 D

M(D) = 1 M(D)
2. Boost 1–D
2 4

+ 3

1 2
Vg + V
– 1

0
– 0 0.5 1 D
 Converters producing a unipolar output voltage

0 0.5 1 D
3. Buck-boost M(D) = – D 0
1–D
–1
1 2 +
–2

Vg + V –3
–
–4
– M(D)

4. Noninverting buck-boost M(D) = D

1–D M(D)
1 2 4
+ 3

2 1 2
Vg + V
– 1

– 0
0 0.5 1 D
 Converters producing a bipolar output voltage
suitable as dc-ac inverters

5. Bridge M(D) = 2D – 1
M(D)
1
1 2
Vg +
– + V – 0
2 1 0.5 1 D

–1

6. Watkins-Johnson M(D) = 2D – 1 M(D)

D
1 1
2 1
+ or + 0

–1
0.5 1 D
Vg + V Vg + V
– – 2 –2

–3
1 2 – –
 Converters producing a bipolar output voltage
suitable as ac-dc rectifiers

M(D)
7. Current-fed bridge M(D) = 1
2D – 1 2

1
0.5 1 D
0
1 2
+ –1
Vg + V –
–
2 1 –2

8. Inverse of Watkins-Johnson M(D) = D

2D – 1 M(D)
1 2
1 2
+ or
+ 1
0.5 1 D
Vg + 0
– V Vg + V
– 2 –1

2 1 – – –2
 Several members of the class of two-inductor converters

´ M(D) = – D 0 0.5 1 D
1. Cuk 1–D 0

–1
+
–2
1 2 –3
Vg + V
–
–4

– M(D)

M(D) = D
2. SEPIC 1–D M(D)
4
2 +
3

Vg +
– 1 V 2

1
– 0
0 0.5 1 D
 Several members of the class of two-inductor converters

3. Inverse of SEPIC M(D) = D M(D)

1–D
1 4

+ 3

2
Vg + 2 V
– 1

0
– 0 0.5 1 D

4. Buck 2 M(D) = D 2
M(D)
1
1
+
2
+ 2
Vg – V 0.5

1
–
0
0 0.5 1 D
 6.3. Transformer isolation

Objectives:
• Isolation of input and output ground connections, to meet
safety requirements
• Reduction of transformer size by incorporating high
frequency isolation transformer inside converter
• Minimization of current and voltage stresses when a
large step-up or step-down conversion ratio is needed
—use transformer turns ratio
• Obtain multiple output voltages via multiple transformer
secondary windings and multiple converter secondary
circuits
 A simple transformer model

Multiple winding transformer Equivalent circuit model

i1(t) i2(t) i1(t) i1'(t) n1 : n2 i2(t)

n1 : n 2
+ + + iM(t) +
v1(t) LM v2(t)
v1(t) v2(t)
– –
– –
i3(t)
i3(t)
v1(t) v2(t) v3(t) +
+
n 1 = n 2 = n 3 = ...
v3(t)
v3(t) 0 = n 1i 1' (t) + n 2i 2(t) + n 3i 3(t) + ...
–
– : n3
: n3
Ideal
transformer
 The magnetizing inductance LM

• Models magnetization of Transformer core B-H characteristic

transformer core material
B(t) | v1(t) dt
saturation
• Appears effectively in parallel with
windings
• If all secondary windings are
slope | LM
disconnected, then primary winding
behaves as an inductor, equal to the
magnetizing inductance H(t) | i M (t)

• At dc: magnetizing inductance tends

to short-circuit. Transformers cannot
pass dc voltages
• Transformer saturates when
magnetizing current iM is too large
 Volt-second balance in LM

The magnetizing inductance is a real inductor,

obeying i1(t) i1'(t) n1 : n2 i2(t)
di M (t)
v1(t) = L M + iM(t) +
dt
integrate: v1(t) LM v2(t)
t
i M (t) – i M (0) = 1 v1(o)do – –
LM 0
i3(t)
Magnetizing current is determined by integral of +
the applied winding voltage. The magnetizing
current and the winding currents are independent v3(t)
quantities. Volt-second balance applies: in
–
steady-state, iM(Ts) = iM(0), and hence : n3
Ts Ideal
0= 1 v1(t)dt transformer
Ts 0
 Transformer reset

• “Transformer reset” is the mechanism by which magnetizing

inductance volt-second balance is obtained
• The need to reset the transformer volt-seconds to zero by the end of
each switching period adds considerable complexity to converters
• To understand operation of transformer-isolated converters:
• replace transformer by equivalent circuit model containing
magnetizing inductance
• analyze converter as usual, treating magnetizing inductance as
any other inductor
• apply volt-second balance to all converter inductors, including
magnetizing inductance
 6.3.1. Full-bridge and half-bridge
isolated buck converters

Full-bridge isolated buck converter

Q1 Q3
D1 D3 D5
i1(t) iD5(t) L i(t)
1 : n
+ +
+
Vg +
– vT(t) vs(t) C R v
–
– –
: n
D2 D4 D6
Q2 Q4
 Full-bridge, with transformer equivalent circuit

Q1 Q3
D1 D3 D5
i1(t) i1'(t) iD5(t) i(t) L
1 : n
+ +
+ iM(t)

Vg +
– vT(t) LM vs(t) C R v
–
– –
: n iD6(t)
D2 D4 D6
Q2 Q4 Ideal
Transformer model
 Full-bridge: waveforms

iM(t)

• During first switching period:

Vg
LM
– Vg transistors Q1 and Q4 conduct
LM
vT(t)
for time DTs , applying volt-
Vg
seconds Vg DTs to primary
0 0
–Vg winding

i(t)
• During next switching period:
I 6i transistors Q2 and Q3 conduct
for time DTs , applying volt-
vs(t)
nVg nVg seconds –Vg DTs to primary
0 0
winding
iD5(t) i • Transformer volt-second
0.5 i 0.5 i
balance is obtained over two
0 t
0 DTs Ts Ts+DTs 2Ts switching periods
conducting Q1 D5 Q2 D5
devices: Q4 D6 Q3 D6
• Effect of nonidealities?
D5 D6
 Effect of nonidealities
on transformer volt-second balance

Volt-seconds applied to primary winding during first switching period:

(Vg – (Q1 and Q4 forward voltage drops))( Q1 and Q4 conduction time)

Volt-seconds applied to primary winding during next switching period:

– (Vg – (Q2 and Q3 forward voltage drops))( Q2 and Q3 conduction time)

These volt-seconds never add to exactly zero.

Net volt-seconds are applied to primary winding
Magnetizing current slowly increases in magnitude
Saturation can be prevented by placing a capacitor in series with
primary, or by use of current programmed mode (Chapter 12)
 Operation of secondary-side diodes

D5 L
: n iD5(t) i(t)
+ +
• During second (D′)
subinterval, both
vs(t) C R v
secondary-side diodes
conduct
– – • Output filter inductor
: n current divides
D6
approximately equally
vs(t)
nVg nVg between diodes
0 0 • Secondary amp-turns add
iD5(t) to approximately zero
i
0.5 i 0.5 i
• Essentially no net
0 t
magnetization of
0 DTs Ts Ts+DTs 2Ts
transformer core by
conducting Q1 D5 Q2 D5
devices: Q4 D6 Q3 D6
secondary winding currents
D5 D6
 Volt-second balance on output filter inductor

D5 L
: n iD5(t) i(t) i(t)
+ + I 6i

vs(t) C R v vs(t)
nVg nVg

– – 0 0
: n
D6 iD5(t) i
0.5 i 0.5 i
0 t
0 DTs Ts Ts+DTs 2Ts

conducting Q1 D5 Q2 D5
V = vs devices: Q4 D6 Q3 D6
D5 D6
V = nDVg

M(D) = nD buck converter with turns ratio

 Half-bridge isolated buck converter

Q1
D1 D3
i1(t) iD3(t) L i(t)
Ca 1 : n
+ +
+
Vg +
– vT(t) vs(t) C R v
–
– –
Cb : n
D2 D4
Q2

• Replace transistors Q3 and Q4 with large capacitors

• Voltage at capacitor centerpoint is 0.5Vg
• vs(t) is reduced by a factor of two
• M = 0.5 nD
 6.3.2. Forward converter

D2 L
n1 : n 2 : n 3
+

D3 C R V

Vg +
– –
Q1
D1

• Buck-derived transformer-isolated converter

• Single-transistor and two-transistor versions
• Maximum duty cycle is limited
• Transformer is reset while transistor is off
 Forward converter
with transformer equivalent circuit

D2 L
n1 : n 2 : n 3
+
iM i1' +
+ – +

LM v1 v2 v3 D3 vD3 C R V

Vg + – + –
– i3 – –
i1 i2
Q1 +
D1
vQ1
–
 Forward converter: waveforms

v1
Vg

0 • Magnetizing current, in
conjunction with diode D1,
n
– n 1 Vg operates in discontinuous
2
iM conduction mode
• Output filter inductor, in
conjunction with diode D3,
Vg n 1 Vg
LM –n
2 LM 0
may operate in either
CCM or DCM
vD3
n3
n 1 Vg

0 0
DTs D2Ts D 3T s t
Ts
Conducting Q1 D1 D3
devices: D2 D3
 Subinterval 1: transistor conducts

n1 : n2 : n3 D2 on L

+ +
iM i1'
+ – +

LM v1 v2 v3 vD3 C R V

Vg + – + –
– i3 – –
i1 i2

D1 off
Q1 on
 Subinterval 2: transformer reset

n1 : n 2 : n 3 L

+ +
iM i1'
+ – +

LM v1 v2 v3 D3 on vD3 C R V

Vg + – + –
– i3 – –
i1
i2 = iM n1 /n2
Q1 off
D1 on
 Subinterval 3

n1 : n2 : n3 L

iM + +
i1'
+ – +
=0
LM v1 v2 v3 D3 on vD3 C R V

Vg + – + –
– i3 – –
i1 i2
Q1 off D1 off
Magnetizing inductance volt-second balance

v1
Vg

n1
– n Vg
2
iM

Vg n 1 Vg
LM –n
2 LM 0

v1 = D Vg + D2 – Vg n 1 /n 2 + D3 0 = 0
 Transformer reset

From magnetizing current volt-second balance:

v1 = D Vg + D2 – Vg n 1 /n 2 + D3 0 = 0

Solve for D2:

n2
D2 = n D
1
D3 cannot be negative. But D3 = 1 – D – D2. Hence
D3 = 1 – D – D2 * 0
n2
D3 = 1 – D 1 + *0
n1
Solve for D
1 for n1 = n2:
D) n2 D) 1
1+ 2
n1
 What happens when D > 0.5

iM(t)
magnetizing current
waveforms, D < 0.5
for n1 = n2

DTs D2Ts D3Ts t

iM(t)
D > 0.5

DTs D2Ts 2Ts t

 Conversion ratio M(D)

D2 L
: n3
+

D3 C R V

vD3
n3
n 1 Vg

n3
vD3 = V = n DVg
1
0 0
DTs D2Ts D 3T s t
Ts
Conducting Q1 D1 D3
devices: D2 D3
 Maximum duty cycle vs. transistor voltage stress

Maximum duty cycle limited to

D) 1
n2
1+
n1

which can be increased by increasing the turns ratio n2 / n1. But this
increases the peak transistor voltage:
n1
max vQ1 = Vg 1 + n
2

For n1 = n2

D) 1 and max(vQ1) = 2Vg

2
 The two-transistor forward converter

Q1
D3 L
D1
+
1:n

Vg +
– D4 C R V

D2
Q2

V = nDVg D) 1 max(vQ1) = max(vQ2) = Vg

2
6.3.3. Push-pull isolated buck converter

Q1
D1 L
1 : n i(t)
– + +
iD1(t)
Vg vT(t)
+
vs(t) C R V
+
–

–
vT(t)
+ – –

D2
Q2

V = nDVg 0≤D≤1
 Waveforms: push-pull

iM(t)
• Used with low-voltage inputs
Vg – Vg
LM
• Secondary-side circuit identical
LM
vT(t)
to full bridge
Vg
0 0 • As in full bridge, transformer
–Vg
volt-second balance is obtained
i(t)
over two switching periods
I 6i
• Effect of nonidealities on
vs(t)
transformer volt-second
nVg nVg balance?
0 0
• Current programmed control
iD1(t) i
0.5 i
can be used to mitigate
0.5 i
0 t transformer saturation
0 DTs Ts Ts+DTs 2Ts problems. Duty cycle control
Conducting Q1 D1 Q2 D1 not recommended.
devices: D1 D2 D2 D2
 6.3.4. Flyback converter

Q1 D1
buck-boost converter:
–

Vg + L V
–

Q1 D1
construct inductor
winding using two –
1:1
parallel wires:
Vg + V
– L

+
 Derivation of flyback converter, cont.

Q1 D1
Isolate inductor
–
windings: the flyback 1:1
converter
Vg + LM V
–

Flyback converter +
having a 1:n turns 1:n D1
ratio and positive LM C V
output: Vg +
–
Q1 –
 The “flyback transformer”

Transformer model
G A two-winding inductor
ig +
i + 1:n D1 iC G Symbol is same as
LM vL C R v
transformer, but function
differs significantly from
Vg + – ideal transformer
– –
G Energy is stored in
magnetizing inductance
Q1
G Magnetizing inductance is
relatively small

G Current does not simultaneously flow in primary and secondary windings

G Instantaneous winding voltages follow turns ratio
G Instantaneous (and rms) winding currents do not follow turns ratio
G Model as (small) magnetizing inductance in parallel with ideal transformer
 Subinterval 1

Transformer model

ig +
i + 1:n iC vL = V g
LM vL C R v iC = – v
Vg + R
–
– ig = i
–

CCM: small ripple

approximation leads to
Q1 on, D1 off vL = V g
iC = – V
R
ig = I
 Subinterval 2

Transformer model i/n

ig +
+
i 1:n iC vL = – nv
=0 –
+ vL v/n C R v i C = ni – v
Vg
–
R
+ ig = 0
–
–

CCM: small ripple

approximation leads to

Q1 off, D1 on vL = – V n
i C = nI – V
R
ig = 0
 CCM Flyback waveforms and solution

vL
Vg
Volt-second balance:
vL = D Vg + D' – V
n =0
–V/n
Conversion ratio is
I/n – V/R
M(D) = V = n D
iC
Vg D'
Charge balance:
i C = D – V + D' nI – V = 0
–V/R R R
Dc component of magnetizing
ig
current is
I
I = nV
D'R
0
Dc component of source current is
DTs D'Ts t I g = i g = D I + D' 0
Ts
Conducting
devices: Q1 D1
 Equivalent circuit model: CCM Flyback

vL = D Vg + D' – V
n =0 +
Ig I

i C = D – V + D' nI – V = 0 Vg + DI + DV D'V + D'I V

R R – – g n – n R

I g = i g = D I + D' 0 –

1:D D' : n
I +
Ig

Vg + R V
–

–
 Discussion: Flyback converter

G Widely used in low power and/or high voltage applications

G Low parts count
G Multiple outputs are easily obtained, with minimum additional parts
G Cross regulation is inferior to buck-derived isolated converters
G Often operated in discontinuous conduction mode
G DCM analysis: DCM buck-boost with turns ratio
 6.3.5. Boost-derived isolated converters

• A wide variety of boost-derived isolated dc-dc converters can be

derived, by inversion of source and load of buck-derived isolated
converters:
• full-bridge and half-bridge isolated boost converters
• inverse of forward converter: the “reverse” converter
• push-pull boost-derived converter
Of these, the full-bridge and push-pull boost-derived isolated
converters are the most popular, and are briefly discussed here.
 Full-bridge transformer-isolated
boost-derived converter

i(t) L

+ vL(t) –
D1
1 : n io(t)
Q1 Q3 +
+
Vg +
– vT(t) C R v
–
–
: n
Q2 Q4 D2

• Circuit topologies are equivalent to those of nonisolated boost

converter
• With 1:1 turns ratio, inductor current i(t) and output current io(t)
waveforms are identical to nonisolated boost converter
 Transformer reset mechanism

V/n
vT (t)
• As in full-bridge buck
0 0
topology, transformer volt-
– V/n second balance is obtained
vL(t) Vg Vg over two switching periods.
• During first switching
Vg –V/n Vg –V/n period: transistors Q1 and
i(t) Q4 conduct for time DTs ,
I
applying volt-seconds VDTs
to secondary winding.
io(t) I/n I/n • During next switching
period: transistors Q2 and
Q3 conduct for time DTs ,
0 0
DTs D'Ts DTs D'Ts t applying volt-seconds
Ts Ts –VDTs to secondary
Conducting Q1 Q1 Q1 Q2
devices: Q2 Q4 Q2 Q3 winding.
Q3 D1 Q3 D2
Q4 Q4
 Conversion ratio M(D)

vL(t) Vg Vg

Application of volt-second
balance to inductor voltage
Vg –V/n Vg –V/n
waveform:
i(t)
I vL = D Vg + D' Vg – V
n =0

Solve for M(D):

DTs D'Ts DTs D'Ts t
Ts Ts M(D) = V = n
Conducting Q1
Q2
Q1
Q4
Q1
Q2
Q2
Q3
Vg D'
devices:
Q3 D1 Q3 D2
Q4 Q4 —boost with turns ratio n
 Push-pull boost-derived converter

Q1
D1
1 : n
– io(t) +
Vg vT(t)
i(t) L
+
C R V
+
–

+ vL(t) – –
vT(t)
+ –

D2
Q2

M(D) = V = n
Vg D'
Push-pull converter based on Watkins-Johnson converter

Q1
D1
1 : n
+
Vg
C R V
+
–

D2
Q2
 6.3.6. Isolated versions of the SEPIC and Cuk converter

+
L1 C1 D1
Basic nonisolated
SEPIC Vg + C2 R v
– L2
Q1
–

L1 C1 D1
1:n
Isolated SEPIC i1 ip is +

Vg + C2 R v
–
Q1
–
 Isolated SEPIC

ip(t) i1

L1 C1 ip D1
1:n
i1 is +
i2
– i2
Vg + LM C2 R v
– = L2 (i1 + i2) / n
Q1 is(t)
–
Ideal 0
Transformer
model i1(t)
I1

M(D) = V = nD
Vg D' i2(t)
I2

DTs D'Ts t
Conducting Ts
devices: Q1 D1
 Inverse SEPIC

1
Nonisolated inverse +
SEPIC
Vg + 2 V
–

C1 L2
1:n
Isolated inverse +
SEPIC
D1 C2 R v
Vg +
–
Q1
–
 Obtaining isolation in the Cuk converter

L1 L2
Nonisolated Cuk –
converter C1
Vg + Q1 D1 C2 R v
–

L1 L2
Split capacitor C1 –
into series C1a C1b
capacitors C1a Q1
Vg + D1 C2 R v
and C1b –

+
 Isolated Cuk converter

L1 L2

Insert transformer +
C1a C1b
between capacitors Q1
C1a and C1b Vg + D1 C2 R v
–

M(D) = V = nD –
Vg D' 1:n

Discussion
• Capacitors C1a and C1b ensure that no dc voltage is applied to transformer
primary or secondary windings
• Transformer functions in conventional manner, with small magnetizing
current and negligible energy storage within the magnetizing inductance
 6.4. Converter evaluation and design

For a given application, which converter topology is best?

There is no ultimate converter, perfectly suited for all possible
applications
Trade studies
• Rough designs of several converter topologies to meet the
given specifications
• An unbiased quantitative comparison of worst-case transistor
currents and voltages, transformer size, etc.
Comparison via switch stress, switch utilization, and semiconductor
cost
Spreadsheet design
 6.4.1. Switch stress and switch utilization

• Largest single cost in a converter is usually the cost of the active

semiconductor devices
• Conduction and switching losses associated with the active
semiconductor devices often dominate the other sources of loss

This suggests evaluating candidate converter approaches by

comparing the voltage and current stresses imposed on the active
semiconductor devices.
Minimization of total switch stresses leads to reduced loss, and to
minimization of the total silicon area required to realize the power
devices of the converter.
 Total active switch stress S

In a converter having k active semiconductor devices, the total active

switch stress S is defined as
k
S= Y
j=1
V jI j
where
Vj is the peak voltage applied to switch j,
Ij is the rms current applied to switch j (peak current is also
sometimes used).
In a good design, the total active switch stress is minimized.
 Active switch utilization U

It is desired to minimize the total active switch stress, while

maximizing the output power Pload.
The active switch utilization U is defined as
Pload
U=
S
The active switch utilization is the converter output power obtained per
unit of active switch stress. It is a converter figure-of-merit, which
measures how well a converter utilizes its semiconductor devices.
Active switch utilization is less than 1 in transformer-isolated
converters, and is a quantity to be maximized.
Converters having low switch utilizations require extra active silicon
area, and operate with relatively low efficiency.
Active switch utilization is a function of converter operating point.
 CCM flyback example: Determination of S

During subinterval 2, the

+
transistor blocks voltage VQ1,pk 1:n D1
equal to Vg plus the reflected
load voltage: LM C V
Vg +
Vg –
V
VQ1,pk = Vg + n = Q1 –
D'
Transistor current coincides
with ig(t). RMS value is
ig
Pload
I Q1,rms = I D = I
Vg D
Switch stress S is
0
S = VQ1,pk I Q1,rms = Vg + V
n I D DTs D'Ts t
Ts
Conducting
devices: Q1 D1
 CCM flyback example: Determination of U

1:D D' : n
Express load power Pload in I +
Ig
terms of V and I:
Vg + R V
–
Pload = D'V nI
–
Previously-derived
CCM flyback model
expression for S:
S = VQ1,pk I Q1,rms = Vg + V
n I D
Hence switch utilization U is
Pload
U= = D' D
S
 Flyback example: switch utilization U(D)

0.4
For given V, Vg, Pload, the max U = 0.385 at D = 1/3
designer can arbitrarily
choose D. The turns ratio n
must then be chosen 0.3
according to
n= V D'
Vg D U 0.2

Single operating point

design: choose D = 1/3.
0.1
small D leads to large
transistor current
large D leads to large 0
transistor voltage 0 0.2 0.4 0.6 0.8 1

D
 Comparison of switch utilizations
of some common converters

Table 6.1. Active switch utilizations of some common dc-dc converters, single operating point.
Converter U(D) max U(D) max U(D)
occurs at D =
Buck D 1 1
Boost D' ∞ 0
D
Buck-boost, flyback, nonisolated SEPIC, isolated D' D 2 = 0.385 1
SEPIC, nonisolated Cuk, isolated Cuk 3 3 3
Forward, n1 = n2 1 D 1 = 0.353 1
2 2
2 2
Other isolated buck-derived converters (full- D 1 = 0.353 1
bridge, half-bridge, push-pull) 2 2 2 2
Isolated boost-derived converters (full bridge, D' 1 0
push-pull) 2 1+D 2
 Switch utilization : Discussion

G Increasing the range of operating points leads to reduced switch utilization

G Buck converter
can operate with high switch utilization (U approaching 1) when D is
close to 1
G Boost converter
can operate with high switch utilization (U approaching ∞) when D is
close to 1
G Transformer isolation leads to reduced switch utilization
G Buck-derived transformer-isolated converters
U ≤ 0.353
should be designed to operate with D as large as other considerations
allow
transformer turns ratio can be chosen to optimize design
 Switch utilization: Discussion

G Nonisolated and isolated versions of buck-boost, SEPIC, and Cuk

converters
U ≤ 0.385
Single-operating-point optimum occurs at D = 1/3
Nonisolated converters have lower switch utilizations than buck or
boost
Isolation can be obtained without penalizing switch utilization
 Active semiconductor cost vs. switch utilization

semiconductor device cost

per rated kVA
semiconductor cost =
per kW output power voltage current converter
derating derating switch
factor factor utilization

(semiconductor device cost per rated kVA) = cost of device, divided by

product of rated blocking voltage and rms current, in $/kVA. Typical
values are less than $1/kVA
(voltage derating factor) and (current derating factor) are required to obtain
reliable operation. Typical derating factors are 0.5 - 0.75
Typical cost of active semiconductor devices in an isolated dc-dc
converter: $1 - $10 per kW of output power.
6.4.2. Converter design using computer spreadsheet

Given ranges of Vg and Pload , as well as desired value of V and other

quantities such as switching frequency, ripple, etc., there are two
basic engineering design tasks:
• Compare converter topologies and select the best for the given
specifications
• Optimize the design of a given converter
A computer spreadsheet is a very useful tool for this job. The results
of the steady-state converter analyses of Chapters 1-6 can be
entered, and detailed design investigations can be quickly performed:
• Evaluation of worst-case stresses over a range of operating
points
• Evaluation of design tradeoffs
 Spreadsheet design example

Specifications • Input voltage: rectified 230 Vrms

Maximum input voltage Vg 390 V ±20%
Minimum input voltage Vg 260 V
• Regulated output of 15 V
Output voltage V 15 V
Maximum load power Pload 200 W • Rated load power 200 W
Minimum load power Pload 20 W
• Must operate at 10% load
Switching frequency fs 100 kHz
Maximum output ripple ∆v 0.1 V • Select switching frequency of
100 kHz
• Output voltage ripple ≤ 0.1V

Compare single-transistor forward and flyback converters in this application

Specifications are entered at top of spreadsheet
 Forward converter design, CCM

D2 L
n1 : n2 : n3
+

D3 C R V

Vg +
– –
Q1
D1

Design variables
Reset winding turns ratio n2 /n1 1 • Design for CCM at full load;
Turns ratio n3 /n1 0.125 may operate in DCM at
light load
Inductor current ripple ∆i 2A ref to sec
 Flyback converter design, CCM

+
1:n D1

LM C V
Vg +
–
Q1 –

Design variables
• Design for CCM at full load;
Turns ratio n2 /n1 0.125 may operate in DCM at
Inductor current ripple ∆i 3 A ref to sec light load
 Enter results of converter analysis into spreadsheet
(Forward converter example)

Maximum duty cycle occurs at minimum Vg and maximum Pload.

Converter then operates in CCM, with
n1 V
D=
n 3 Vg
Inductor current ripple is
D'VT s
6i =
2L
Solve for L:
D'VT s
L=
26i
∆i is a design variable. For a given ∆i, the equation above can be used
to determine L. To ensure CCM operation at full load, ∆i should be
less than the full-load output current. C can be found in a similar
manner.
 Forward converter example, continued

Check for DCM at light load. The solution of the buck converter
operating in DCM is
n3 2
V= Vg
n1 4K
1+ 2
D
with K = 2 L / R Ts, and R = V 2 / Pload
These equations apply equally well to the forward converter, provided
that all quantities are referred to the transformer secondary side.
Solve for D:
D= 2 K n1 V
2 D=
2n 3Vg in DCM n 3 Vg in CCM
–1 –1
n 1V
at a given operating point, the actual duty cycle is the small of the
values calculated by the CCM and DCM equations above. Minimum D
occurs at minimum Pload and maximum Vg.
 More regarding forward converter example

Worst-case component stresses can now be evaluated.

Peak transistor voltage is
n1
max vQ1 = Vg 1 + n
2

RMS transistor current is

2
n3 2
6i n3
I Q1,rms = D I + 5 DI
n1 3 n1
(this neglects transformer magnetizing current)

Other component stresses can be found in a similar manner.

Magnetics design is left for a later chapter.
Results: forward and flyback converter spreadsheets

Forward converter design, CCM Flyback converter design, CCM

Design variables Design variables
Reset winding turns ratio n2/n1 1 Turns ratio n2/n1 0.125
Turns ratio n3/n1 0.125 Inductor current ripple ∆i 3 A ref to sec
Inductor current ripple ∆i 2 A ref to sec
Results Results
Maximum duty cycle D 0.462 Maximum duty cycle D 0.316
Minimum D, at full load 0.308 Minimum D, at full load 0.235
Minimum D, at minimum load 0.251 Minimum D, at minimum load 0.179
Worst-case stresses Worst-case stresses
Peak transistor voltage vQ1 780 V Peak transistor voltage vQ1 510 V
Rms transistor current iQ1 1.13 A Rms transistor current iQ1 1.38 A
Transistor utilization U 0.226 Transistor utilization U 0.284
Peak diode voltage vD2 49 V Peak diode voltage vD1 64 V
Rms diode current iD2 9.1 A Rms diode current iD1 16.3 A
Peak diode voltage vD3 49 V Peak diode current iD1 22.2 A
Rms diode current iD3 11.1 A
Rms output capacitor current iC 1.15 A Rms output capacitor current iC 9.1 A
 Discussion: transistor voltage

Flyback converter
Ideal peak transistor voltage: 510V
Actual peak voltage will be higher, due to ringing causes by
transformer leakage inductance
An 800V or 1000V MOSFET would have an adequate design margin
Forward converter
Ideal peak transistor voltage: 780V, 53% greater than flyback
Few MOSFETs having voltage rating of over 1000 V are available
—when ringing due to transformer leakage inductance is accounted
for, this design will have an inadequate design margin
Fix: use two-transistor forward converter, or change reset winding
turns ratio
A conclusion: reset mechanism of flyback is superior to forward
 Discussion: rms transistor current

Forward
1.13A worst-case
transistor utilization 0.226
Flyback
1.38A worst case, 22% higher than forward
transistor utilization 0.284
CCM flyback exhibits higher peak and rms currents. Currents in DCM
flyback are even higher
Discussion: secondary-side diode and capacitor stresses

Forward
peak diode voltage 49V
rms diode current 9.1A / 11.1A
rms capacitor current 1.15A
Flyback
peak diode voltage 64V
rms diode current 16.3A
peak diode current 22.2A
rms capacitor current 9.1A
Secondary-side currents, especially capacitor currents, limit the
practical application of the flyback converter to situations where the load
current is not too great.
 Summary of key points

1. The boost converter can be viewed as an inverse buck converter, while

the buck-boost and Cuk converters arise from cascade connections of
buck and boost converters. The properties of these converters are
consistent with their origins. Ac outputs can be obtained by differential
connection of the load. An infinite number of converters are possible,
and several are listed in this chapter.

2. For understanding the operation of most converters containing

transformers, the transformer can be modeled as a magnetizing
inductance in parallel with an ideal transformer. The magnetizing
inductance must obey all of the usual rules for inductors, including the
principle of volt-second balance.
 Summary of key points

3. The steady-state behavior of transformer-isolated converters

may be understood by first replacing the transformer with the
magnetizing-inductance-plus-ideal-transformer equivalent
circuit. The techniques developed in the previous chapters can
then be applied, including use of inductor volt-second balance
and capacitor charge balance to find dc currents and voltages,
use of equivalent circuits to model losses and efficiency, and
analysis of the discontinuous conduction mode.

4. In the full-bridge, half-bridge, and push-pull isolated versions of

the buck and/or boost converters, the transformer frequency is
twice the output ripple frequency. The transformer is reset while
it transfers energy: the applied voltage polarity alternates on
successive switching periods.
 Summary of key points

5. In the conventional forward converter, the transformer is reset while the

transistor is off. The transformer magnetizing inductance operates in the
discontinuous conduction mode, and the maximum duty cycle is limited.
6. The flyback converter is based on the buck-boost converter. The flyback
transformer is actually a two-winding inductor, which stores and transfers
energy.
7. The transformer turns ratio is an extra degree-of-freedom which the
designer can choose to optimize the converter design. Use of a computer
spreadsheet is an effective way to determine how the choice of turns ratio
affects the component voltage and current stresses.
8. Total active switch stress, and active switch utilization, are two simplified
figures-of-merit which can be used to compare the various converter
circuits.