LINEAR AND DIGITAL IC APPLICATIONS

Unit – 3

Verilog Hardware Description Language

 HDL INTRODUCTION

• A Hardware Description Language (HDL) is a specialized computer

language used to describe the structure and behavior of
electronic circuits, and most commonly, digital logic circuits.
• Both Verilog and VHDL (Very High Speed Integrated Circuits HDL)
are Hardware Description Languages (HDL).
• These languages help to describe hardware of digital system such
as microprocessors, and flip-flops.
• Therefore, these languages are different from regular
programming languages.
• VHDL is an older language whereas Verilog is the latest language.

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 History

• The Verilog HDL language was first developed by Gateway Design

Automation1 in 1983 as a hardware modeling language.
• Because of the popularity of their simulator product, Verilog HDL gained
acceptance as a usable and practical language by a number of designers.
• The language was placed in the public domain in 1990.
• Open Verilog International (OVI) was formed to promote Verilog.
• In 1992,OVI decided to pursue standardization of Verilog HDL as an IEEE
standard.
• This effort was successful and the language became an IEEE standard in
1995.
• The complete standard is described In the Verilog Hardware Description
Language Reference Manual.
• The standard is called IEEE Std 1364-1995.
• Contains Language elements, compiler directives, constants, value set,
expressions, data types & modelling methods.

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Delays:

`timescale 1ns/100ps defines time unit/ time precision i.e., means that all the delays that
follow (like# 5.1234) are interpreted to be in nanoseconds and any fractions will be rounded
to the nearest picosecond (5123ps).

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 Language Elements
Describes the basic elements of Verilog HDL.
It introduces the
– Identifiers
– Comments
– Numbers
– Compiler directives
– System tasks
– System functions
 It introduces the two data types in the language.

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Identifiers:

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 Value set
• Verilog supports four values and eight strengths to model the
functionality of real hardware

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 Value set contd.,
• In addition to logic values, strength levels are often used to resolve
conflicts between drivers of different strengths in digital circuits
• Values 0 and 1can have strength levels as listed below:

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 Value set contd.,

• If 2 signals of unequal strengths are driven on a wire, the stronger

signal prevails
Ex: 2 signals of strength strong1 and weak0 contend, result is resolved as
a strong1
• If 2 signals of equal strengths are driven on a wire, the result is
unknown
Ex: 2 signals of strength strong1 and strong0 conflict, result is X.

strength levels are particularly useful for accurate modelling of

signal contention, MOS services, dynamic Mos and other low-level
devices.

• Only trireg nets can have storage strengths large, medium, small

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 Constants
Verilog constants are literals, Genvars parameters, Localparams and
specparams.

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 False (0), true (1).
In case comparison x,z with no
interpretation result never be unknown
(x).
In logical comparisons, if the operands
contain x or z then result is unknown (x).
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If condition expression is true 1----- exp 1
If condition expression is false 0----- exp 2
If condition expression is x or z, then the result is
bitwise operation( 0 with 0 gives 0
1 with 1 gives 1, rest are x)

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 Data Type

ii. Nets are declared primarily with the keyword wire.

iii. Nets are one bit values by default unless they are declared explicitly as
vectors.
iv. Wire and net are often used interchangeably.
v. Net is not a keyword but represents a class of data types such as wire,
wand, wor, tri, triand, trior, trireg, etc.
vi. The wire declaration is used most frequently.

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 DATA TYPES

• Register retains value until another value is placed onto them.

• In Verilog, the term register merely means a variable that can hold a value.
• Unlike a net, register does not need a driver.
• Verilog registers do not need a clock as hardware registers.
• Values of registers can be changed anytime in a simulation by assigning a
new value to the register
• Commonly declared by the keywords reg.

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 Modelling Methods
• Representation of particular theorem/ phenomenon using diagram,
flowchart, equations or a physical object to represent it, making it
easier to understand.
• Verilog is a computer programming environment which is used to
simulate complex digital or logic circuits.
• Modelling in Verilog can be done in different ways
As an interconnection of gates – Gate level modelling
As an interconnection of transistors – switch level modelling
As an interconnection of sub-circuits – structural modelling
Using logical equation – Dataflow style of modelling
Using behaviour of the system –Behavioural modelling
Mixture of above styles – mixed modelling

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 A basic Verilog program

module module_name (port_list);

input declarations;
output declarations;
parameter declarations;

initial statements;
always statements;
gate instantiations;
UDP instantiations;
endmodule;

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 Gate–Level Modelling
• Verilog has predefined inbuilt gate primitives.
• It is the lowest level of abstraction.
• Design logic using basic gates.
• All logic gates can be implemented using these gates.
1. Basic gates (And/Or, Buf/Not)
2. Bufif/Notif gates
3. Pull gates
4. Gate delays

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 And/Or gates

• One scalar o/p and multiple scalar i/p’s.

• Output of a gate is evaluated as soon as one of the input changes.
• The primitives (Gates)available in Verilog are:
and
or
xor
nand
nor
xnor

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And/Or gates Truth Table

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 Syntax

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Example:
module gate_eg (o1,o2,i1,i2,i3,i4);
input i1,i2,i3,i4;
output o1,o2;

and and_gate(o1,i1,i2);
xor xor_gate(o2,i3,i4);

endmodule

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Example continued:
module gate_eg (o1,o2,o3,o4, i1,i2,i3,i4,i5,i6,i7,i8);
input i1,i2,i3,i4, i5,i6,i7,i8;
output o1,o2,o3,o4;
or(o1,i1,i2);
nand(o2,i3,i4);
nor(o3,i5,i6);
xor(o4,i7,i8);
end module

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 Buf/Not gates

• These gates have one scalar input and one or

more scalar outputs.

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Example:
module gate_eg (o1,o2, i1,i2);
input i1,i2;
output o1,o2;

buf buf_gate (o1,i1);

not not_gate (o2,i2);

end module

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 Bufif/Notif Gates
• These gates have a additional control signal.
• They propagate if the control signal is given otherwise the output will
be in high impedance state.
• Bufif1, bufif0, notif1, notif0

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Bufif/Notif Gates Truth Table

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Example:
module gate_eg (o1,o2, 03,04,i1,i2,i3,i4,control);
input i1,i2, i3,i4,control;
output o1,o2,o3,o4;

bufif1 buf_gate1 (o1,i1,control);

notif1 not_gate1 (o2,i2,control);

bufif0 buf_gate2 (o3,i3,control);

notif0 not_gate2 (o4,i4,control);

end module

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switch level modelling
nmos, rnmos – ctrl=1 ,
pmos, rpmos – ctrl=1
switch Off--- O/p is Z(high impedance b/n i/p and o/p for resistive switches )

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 Gate Delays
• In Verilog we can introduce gate delays in the logic circuits.
• 3 types of delays from input to output of gates.

1. Rise delay:
This delay comes into picture when the output of the gate transit from
another value to logic 1.

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2. Fall delay
When gate output transit to logic 0 from another value.

3. Turn-off delay
 When gate output transit to Z from any other logic value.
 If the gate output transit to don’t care then minimum of three delays is
considered.

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 Insert delay value to code

Example:
module D (out,a,b,c);
input a,b,c;
output out;
Wire e;
and #(5) a1 (e,a,b);
//or#(4,5) o1(out,e,c);
or #(4,5,6) o1 (out,e,c);

endmodule

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 Structural modelling

• Represent digital logic model with gates

• Connect together with wires
Advantages:
• Directly affect the digital logic
• Lower level modelling.
Disadvantages:
• Hard to understand
• Easy to miss wires
• Very cumbresome

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 Half subtractor
Example:
module half_sub D (borrow, difference, a, b);
input a,b;
output borrow, difference;
Wire w1;

xor x1 (difference, a, b);

not n1 (w1,a);
and a1 (borrow, w1,b);

endmodule

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 Example circuit

Example:
module circuit_eg (f,a,b,c,d);
input a,b,c,d;
output f;
Wire w1,w2,w3;

and a1 (w1, a, b);

or o1 (w3,c,d);
xor x1 (w2, w1,w3);
and a2 (f, w2,w3);

endmodule

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 Data flow modelling
• Gate level modelling can be used in terms of low level abstraction.
• When it comes to higher level of abstraction data flow modelling is
used.
• Data flow modelling provides a powerful way to implement a design
using logic equations.
• Continuous assignment is there on data flow modelling.
• Continuous assignment is used to drive a value onto an net. A
continuous assignment replaces gates in the description of the circuit
and describes the circuit at a higher level of abstraction.
• A continuous assignment statement starts with the keyword assign.
Characteristics of continuous assignment:
 The LHS must always be net type.
 RHS can be reg or net type.
 Continuous statements are always active.
 Delay values can be specified for assignments in terms of time units.

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Example1 : assign out = in1 & in2; // continuous assign. Out is net.
in1&in2 are reg.
Example 2: assign {c_out, sum [3:0]} = a[3:0]+ b[3:0]+ c_in;
/* LHS is concatenation of scalar
net and vector net*/
IMPLICIT CONTINUOUS ASSIGNMENT
• Continuous assignment can be placed on a net when it is declared.
• There can be one implicit declaration assignment per net because a net is
declared only once.
Example:
// Regular continuous assignment
Wire out;
Assign out = in1 & in2;
// implict continuous assignment
Wire out = in1 & in2;
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 Delays
• Delay values control time between the change in a RHS operand and when
the new value is assigned to LHS.
• 3 ways of specifying delays in continuous assignment statements.
1. Regular assignment delay
 The delay is specified after the keyword assign.
 Any change in values of in1 or in2 will result in a delay of 10 time units
before recompilation of the expression in1 & in2, result will be
assigned to out.
// Delay in a continuous assign
Assign #10 out = in1 & in2 ;

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2. Implicit continuous assignment delay
Specify both delay and an assignment on the net.
// implicit continuous assignment delay
Wire #10 out = in1 & in2;

3. Net declaration delay:

A delay can be specified on a net when it is declared without putting a
continuous assignment on the net.
// net delays
Wire #10 out;
Assign out = in1 & in2;

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 Examples

4-BIT FULL ADDER, USING DATA FLOW OPERATORS

// define a 4- bit full addrer by using data flow statements
Module fulladd4 (sum, c_out, a, b, c_in);
// I/O Port declarations
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
// specify the function of a full adder
assign { c_out, sum} = a + b + c_in;
endmodule
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 Behavioural modelling

• Verilog supports 2 structured procedure statements always and initial.

• All behavioural statements are written inside these blocks.
• These blocks run in parallel i.e. concurrent in nature.
• Their activity starts at 0 simulation time.
• Blocks cannot be nested.
initial Statement:
 Once execution only.
 Execution starts at 0 simulation time.
 Stops when last statement is executed.
 Parallel execution in case of multiple initial blocks.
 Multiple statements inside an initial block needs to be grouped with begin
and end statements.

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 Example
module stimulus;
reg x, y, a, b, m;
initial
m=1’bo; //single assignment statement
initial
begin
#5 a= 1’b1;
#30 b = 1’b0;
end
initial
begin
#10 x = 1’b0;
#35 y 1’b1;
end
Initial
#50 $finish;
endmodule

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 always statement
• Repeats continuously throughout the duration of simulation time (loop).
• Like initial block it is also concurrent in nature and starts at 0 simulation time.
• Parallel execution in case of multiple always blocks.
• A deadlock condition will be created if an always construct has no control for
simulation time (Sensitivity list has to be given)
Example:
module clock_gen;
reg clock;
Initial // initial clock at 0 time
clock = 1’bo;
always // toggle clock every half-cycle (time period = 10)
#10 clock = ~ clock;
initial
#1000 $finish
endmodule
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 Procedural assignment
 Updates the values of reg, integer, real, or time variables.
 The value placed on variable will remain unchanged until another
procedural assignment updates the variable with a different value.
 These are unlike continuous statements.
 2 types of procedural statements:
– Blocking assignments
– Non- blocking assignments.
Blocking assignments:
 Represents with sign ‘=‘, statements executed sequentially as they are
specified in a sequential block.
 One statement blocks other until it is executed.
 Delay values will be added.
 Can be used in both procedural and continuous assignments.

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 Example
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioural statements must be inside an initial or always block
initial
begin
x=0; y=1, z=1; //scalar assignments
count=0; //assignment to integer variables
reg_a = 16’b0; reg_b = reg_a; //initialise vectors
#15 reg_a [2] = 1’b1; //bit select assignment with delay
#10 reg_b [15:13]= {x, y, z} //assign result of concatenation
count= count+1; //assignment to an integer -increment
end

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 Non-blocking assignments
• Represented with “<=“, statements executed concurrently.
• RHS evaluated first, subsequently the specified assignments are scheduled.
• Non-Blocking assignments can’t be used in an continuous assignment statement or in a
net declaration.
• Order of an execution of distinct non-blocking assignments to a given variable shall be
preserved
Example:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
initial
begin
x=0; y=1, z=1;
count=0;
reg_a = 16’b0; reg_b= reg_a;
reg_a[2] <= #15 1’b1;
reg_b[15:13] <= #10 {x,y,z};
count <= count+1;
end Verilog Hardware Description Language 89
 Delays in procedural assignment
Delay based timing control in an expression specifies the time duration between
when the statement is encountered and when it is executed.
– Regular delay
– Intra-assignment delay
Regular delay
If delay is specified then at that time the entire statement is executed and assigned
to the LHS.
This is the delay before the RHS is evaluated and assigned to the LHS
Entire operation will be delayed.
Example:
inital
begin
x = 0;
#10 y =1; //delay execution of y=1 by 10 units
#y x = x + 1; //delay control with identifier . Take value of y
end

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 Intra assignment delay
• The RHS of the equation is evaluated at current time but the value is
assigned to LHS after the delay time
• Can be applied to both blocking and non-blocking assignment.
Example:
initial
begin
x= 0, z=0;
y = #5 x + z; // x+z evaluated 1st then after 5 time units assigned to y
end
Block statements:
SEQUENCE BLOCK PARALLEL BLOCK
Begin-end used to group multiple statements. Fork-join used to group multiple statements.
Statements executed in mentioned order. Statements executed concurrently.
Delay is treated relative to simulation time Delay is treated relative to simulation time of
and previous statement. entering the block.
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 Sequential block example Parallel Block example
initial initial
begin begin
x=1’b0; x=1’b0;
y=1’b1; y=1’b1;
z={x, y}; z={x, y};
w={y, x}; w={y, x};
end end
2_example : sequential blocks with 2_Example: sequential blocks with
delay delay
reg x, y; reg x, y;
reg [1 : 0] z, w; reg [1 : 0] z, w;
initial initial
begin begin
x = 1’b0; // 0 time units x = 1’b0; // 0 time units
#5 y = 1’b1; // 5 time units #5 y = 1’b1; // 5 time units
#10 z = {x, y}; // 15 time units #10 z = {x, y}; // 10 time units
#20 w = {y, x}; // 35 time units #20 w = {y, x}; // 20 time units
end end Language
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 Conditional statements
• Keywords like if and else are used.
• Decision maker statements.
• Multiple statements inside an if-else statement is enclosed by begin-end
block
• Nested if-else-if statements also come in conditional statements.
SYNTAX:
TYPE_1: if (<expression>) true_statement ;

TYPE_2: if (<expression>) true_statement ; else false_statement;

TYPE_3: if (<expression1>) true_statement1;

else if (<expression2>) true_statement2;
else if (<expression3>) true_statement3;
else default_statement
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 Multiway branching – case statement

• Sometimes if_else_if statements become very difficult to use.

• Keywords: case, endcase and default.
• Multiple statements can be contained by begin-end block
Syntax:
Case {expression}
alternative1: statement1;
alternative2: statement2;
alternative3: statement3;
---
---
default: default_statement;
endcase

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 Looping constructs

 4 types of looping statements in Verilog:

– For loop
– While loop
– Repeat loop
– Forever loop
 Looping statements appear only inside an initial or always block.
 Loops may contain delay expressions

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 While loop:
 Keyword: while
 Executed until while expression is false.
 Multiple statements are grouped in begin-end
 Non-synthesizable in nature.
EXAMPLE:
Q:Increment count from 0 10 127 exit at count 128, display count variable
integer count;
initial
begin
count= 0;
while (count< 128); //Executes loop till count is 127. exit at 128
begin
$display (“count = %d”, count);
count = count + 1
end
end
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 For loop

• Generally for loop consists of 3 parts:

1. Initialize
2. terminating statement &
3. increment/decrement
• For loop provides a more compact loop structure than while loop.
Syntax:
integer count;
initial
for (count=0, count<128, count = count+1)
$display (“count= %d”, count);

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 REPEAT
• keyword: repeat
• It iterates for a fixed number of time
• No expression is required
• Repeat loop must contain a number.
Syntax:
initial
begin
count = 0;
repeat(128)
begin
$display (“count= %d”, count);
count = count + 1
end
end
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 Forever loop

• Keyword: forever
• It executes forever until $finish or disable statement is encountered
• It does not require any expression
SYNTAX:
initial
begin
clock = 1’b0;
forever #10 clock = ~clock; //clock with period of 10 units
end

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 4x1 MUX
module mux4_to_1 (out, io, i1, i2, i3, s1, s0);
output out; //port declarations
input io, i1, i2, i3, ; //input port declaration
input s1, s0; //output port declaration
reg out;
always @ (s1, s0, i0 , i1, i2, i3 )
begin
case ((s1, s0))
2’b00 : out = i0;
2’b01 : out = i1;
2’b10 : out = i2;
2’b11 : out = i3;
default: out = 1’bx;
endcase
end
endmodule

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 4-bit counter

module counter (q, clock, clear);

output [3:0] q;
Input clock, clear;
reg [3:0] q;
always @ (posedge clear or negedge clock)
begin
if (clear)
q = 4’d0;
else
q = (q+1) % 16;
end
endmodule

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