REN Isl6236 DST 20061106

DATASHEET
ISL6236 FN6373
High-Efficiency, Quad-Output, Main Power Supply Controllers for Notebook Rev 6.00
Computers April 29, 2010
The ISL6236 dual step-down, switch-mode power-supply Features

(SMPS) controller generates logic-supply voltages in
battery-powered systems. The ISL6236 include two • Wide Input Voltage Range 5.5V to 25V
pulse-width modulation (PWM) controllers, 5V/3.3V and • Dual Fixed 1.05V/3.3V and 1.5V/5.0V Outputs or
1.5V/1.05V. The output of SMPS1 can also be adjusted from Adjustable 0.7V to 5.5V (SMPS1) and 0V to 2.5V
0.7V to 5.5V. The SMPS2 output can be adjusted from 0V to (SMPS2), ±1.5% Accuracy
2.5V by setting REFIN2 voltage. An optional external charge • Secondary Feedback Input (Maintains Charge Pump
pump can be monitored through SECFB. This device features Voltage)
a linear regulator providing 3.3V/5V, or adjustable from 0.7V to
4.5V output via LDOREFIN. The linear regulator provides up • 1.7ms Digital Soft-Start and Independent Shutdown
to 100mA output current with automatic linear-regulator • Fixed 3.3V/5.0V, or Adjustable Output 0.7V to 4.5V,
bootstrapping to the BYP input. When in switchover, the LDO ±1.5% (LDO): 200mA
output can source up to 200mA. The ISL6236 includes
• 3.3V Reference Voltage ±2.0%: 5mA
on-board power-up sequencing, the power-good (POK)
outputs, digital soft-start, and internal soft-stop output • 2.0V Reference Voltage ±1.0%: 50µA
discharge that prevents negative voltages on shutdown. • Constant ON-time Control with 100ns Load-Step
A constant ON-time PWM control scheme operates without Response
sense resistors and provides 100ns response to load • Frequency Selectable
transients while maintaining a relatively constant switching
• rDS(ON) Current Sensing
frequency. The unique ultrasonic pulse-skipping mode
maintains the switching frequency above 25kHz, which • Programmable Current Limit with Foldback Capability
eliminates noise in audio applications. Other features include • Selectable PWM, Skip or Ultrasonic Mode
pulse skipping, which maximizes efficiency in light-load
applications, and fixed-frequency PWM mode, which reduces • BOOT Voltage Monitor with Automatic Refresh
RF interference in sensitive applications. • Independent POK1 and POK2 Comparators
Ordering Information • Soft-Start with Pre-Biased Output and Soft-Stop
PART TEMP. • Independent ENABLE
NUMBER PART RANGE PACKAGE PKG.
(Note) MARKING (°C) (Pb-Free) DWG. # • High Efficiency - up to 97%
ISL6236IRZA ISL6236 IRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B • Very High Light Load Efficiency (Skip Mode)
ISL6236IRZA-T* ISL6236 IRZ -40 to +100 32 Ld 5x5 QFN L32.5x5B • 5mW Quiescent Power Dissipation
(Tape and
Reel) • Thermal Shutdown
*Please refer to TB347 for details on reel specifications. • Extremely Low Component Count
NOTES: • Pb-Free (RoHS Compliant)
1. These Intersil Pb-free plastic packaged products employ special
Pb-free material sets, molding compounds/die attach materials, Applications
and 100% matte tin plate plus anneal (e3 termination finish, which
is RoHS compliant and compatible with both SnPb and Pb-free • Notebook and Sub-Notebook Computers
soldering operations). Intersil Pb-free products are MSL classified
at Pb-free peak reflow temperatures that meet or exceed the Pb- • PDAs and Mobile Communication Devices
free requirements of IPC/JEDEC J STD-020.
• 3-Cell and 4-Cell Li+ Battery-Powered Devices
2. For Moisture Sensitivity Level (MSL), please see device
information page for ISL6236. For more information on • DDR1, DDR2 and DDR3 Power Supplies
MSL please see techbrief TB363.
• Graphic Cards
• Game Consoles
• Telecommunications
FN6373 Rev 6.00 Page 1 of 36

April 29, 2010
ISL6236
Pinout
ISL6236
(32 LD 5x5 QFN)
TOP VIEW
PHASE2
UGATE2
REFIN2
POK2
OUT2
ILIM2
SKIP
EN2
32 31 30 29 28 27 26 25
REF 1 24 BOOT2
TON 2 23 LGATE2
VCC 3 22 PGND
EN LDO 4 21 GND
VREF3 5 20 SECFB
VIN 6 19 PVCC
LDO 7 18 LGATE1
LDOREFIN 8 17 BOOT1
9 10 11 12 13 14 15 16
OUT1
ILIM1
BYP
FB1
POK1
EN1
UGATE1
PHASE1
FN6373 Rev 6.00 Page 2 of 36

April 29, 2010
ISL6236
Absolute Voltage Ratings Thermal Information

VIN, EN LDO to GND. . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +27V Thermal Resistance (Typical) JA (°C/W) JC (°CW)
BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V 32 Ld QFN (Notes 3, 4) . . . . . . . . . . . . 32 3.0
BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Operating Temperature Range . . . . . . . . . . . . . . . .-40°C to +100°C
VCC, EN, SKIP, TON, PVCC, POK to GND . . . . . . . . . -0.3V to +6V Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
LDO, FB1, REFIN2, LDOREFIN to GND . . . -0.3V to (VCC + 0.3V) Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C
OUT, SECFB, VREF3, REF to GND . . . . . . . . -0.3V to (VCC + 0.3V Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
UGATE to PHASE . . . . . . . . . . . . . . . . . . . . -0.3V to (PVCC + 0.3V) http://www.intersil.com/pbfree/Pb-FreeReflow.asp
ILIM to GND . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VCC + 0.3V)
LGATE, BYP to GND . . . . . . . . . . . . . . . . . . -0.3V to (PVCC + 0.3V)
PGND to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +0.3V
LDO, REF, VREF3 Short Circuit to GND . . . . . . . . . . . . Continuous
VCC Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1s
LDO Current (Internal Regulator) Continuous . . . . . . . . . . . . 100mA
LDO Current (Switched Over to OUT1) Continuous . . . . . . +200mA
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
3. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
4. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications No load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V, EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V,
VEN_LDO = 5V, TA = -40°C to +100°C, unless otherwise noted. Typical values are at TA = +25°C. Boldface
limits apply over the operating temperature range, -40°C to +85°C.
MIN MAX
PARAMETER CONDITIONS (Note 6) TYP (Note 6) UNITS
MAIN SMPS CONTROLLERS
VIN Input Voltage Range LDO in regulation 5.5 25 V
VIN = LDO, VOUT1 <4.43V 4.5 5.5 V
3.3V Output Voltage in Fixed Mode VIN = 5.5V to 25V, REFIN2 > (VCC - 1V), SKIP = 5V 3.285 3.330 3.375 V
1.05V Output Voltage in Fixed Mode VIN = 5.5V to 25V, 3.0 < REFIN2 < (VCC - 1.1V), 1.038 1.05 1.062 V
SKIP = 5V
1.5V Output Voltage in Fixed Mode VIN = 5.5V to 25V, FB1 = VCC, SKIP = 5V 1.482 1.500 1.518 V
5V Output Voltage in Fixed Mode VIN = 5.5V to 25V, FB1 = GND, SKIP = 5V 4.975 5.050 5.125 V
FB1 in Output Adjustable Mode (Note 7) VIN = 5.5V to 25V 0.693 0.700 0.707 V
REFIN2 in Output Adjustable Mode VIN = 5.5V to 25V 0.7 2.50 V
SECFB Voltage VIN = 5.5V to 25V 1.920 2.00 2.080 V
SMPS1 Output Voltage Adjust Range SMPS1 0.70 5.50 V
SMPS2 Output Voltage Adjust Range SMPS2 0.50 2.50 V
SMPS2 Output Voltage Accuracy REFIN2 = 0.7V to 2.5V, SKIP = VCC -1.0 1.0 %
(Referred for REFIN2)
DC Load Regulation Either SMPS, SKIP = VCC, 0A to 5A -0.1 %
Either SMPS, SKIP = REF, 0A to 5A -1.7 %
Either SMPS, SKIP = GND, 0A to 5A -1.5 %
Line Regulation Either SMPS, 6V < VIN < 24V 0.005 %/V
Current-Limit Current Source Temperature = +25°C 4.75 5 5.25 µA
ILIM Adjustment Range 0.2 2 V
Current-Limit Threshold (Positive, Default) ILIM = VCC, GND - PHASE 93 100 107 mV
(No temperature compensation)
FN6373 Rev 6.00 Page 3 of 36

April 29, 2010
ISL6236
limits apply over the operating temperature range, -40°C to +85°C. (Continued)
MIN MAX
Current-Limit Threshold GND - PHASE VILIM = 0.5V 40 50 60 mV
(Positive, Adjustable)
VILIM = 1V 93 100 107 mV
VILIM = 2V 185 200 215 mV
Zero-Current Threshold SKIP = GND, REF, or OPEN, GND - PHASE 3 mV
Current-Limit Threshold (Negative, Default) SKIP = VCC, GND - PHASE -120 mV
Soft-Start Ramp Time Zero to full limit 1.7 ms
Operating Frequency (VtON = GND), SKIP = VCC SMPS 1 400 kHz
SMPS 2 500 kHz
(VtON = REF or OPEN), SMPS 1 400 kHz
SKIP = VCC
SMPS 2 300 kHz
(VtON = VCC), SKIP = VCC SMPS 1 200 kHz
SMPS 2 300 kHz
ON-Time Pulse Width VtON = GND (400kHz/500kHz) VOUT1 = 5.00V 0.895 1.052 1.209 µs
VOUT2 = 3.33V 0.475 0.555 0.635 µs
VtON = REF or OPEN VOUT1 = 5.05V 0.895 1.052 1.209 µs
(400kHz/300kHz)
VOUT2 = 3.33V 0.833 0.925 1.017 µs
VtON = VCC (200kHz/300kHz) VOUT1 = 5.05V 1.895 2.105 2.315 µs
VOUT2 = 3.33V 0.833 0.925 1.017 µs
Minimum OFF-Time TA = -40°C to +100°C 200 300 425 ns
TA = -40°C to +85°C 200 300 410 ns
Maximum Duty Cycle VtON = GND VOUT1 = 5.05V 88 %
VOUT2 = 3.33V 85 %
VtON = REF or OPEN VOUT1 = 5.05V 88 %
VOUT2 = 3.33V 91 %
VtON = VCC VOUT1 = 5.05V 94 %
VOUT2 = 3.33V 91 %
Ultrasonic SKIP Operating Frequency SKIP = REF or OPEN 25 37 kHz
INTERNAL REGULATOR AND REFERENCE

LDO Output Voltage BYP = GND, 5.5V < VIN < 25V, LDOREFIN < 0.3V, 4.925 5.000 5.075 V
0 < ILDO < 100mA
LDO Output Voltage BYP = GND, 5.5V < VIN < 25V, LDOREFIN > (VCC -1V), 3.250 3.300 3.350 V
0 < ILDO < 100mA
LDO Output in Adjustable Mode VIN = 5.5V to 25V, VLDO = 2 x VLDOREFIN 0.7 4.5 V
LDO Output Accuracy in Adjustable Mode VIN = 5.5V to 25V, VLDOREFIN = 0.35V to 0.5V ±2.5 %
VIN = 5.5V to 25V, VLDOREFIN = 0.5V to 2.25V ±1.5 %
LDOREFIN Input Range VLDO = 2 x VLDOREFIN 0.35 2.25 V
LDO Output Current BYP = GND, VIN = 5.5V to 25V (Note 5) 100 mA
LDO Output Current During Switchover BYP = 5V, VIN = 5.5V to 25V, LDOREFIN < 0.3V 200 mA
LDO Output Current During Switchover BYP = 3.3V, VIN = 5.5V to 25V, LDOREFIN > (VCC - 1V) 100 mA
to 3.3V
LDO Short-Circuit Current LDO = GND, BYP = GND 200 400 mA
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April 29, 2010
ISL6236
MIN MAX
Undervoltage-Lockout Fault Threshold Rising edge of PVCC 4.35 4.5 V
Falling edge of PVCC 3.9 4.05
LDO 5V Bootstrap Switch Threshold to BYP Rising edge at BYP regulation point 4.53 4.68 4.83 V
LDOREFIN = GND
LDO 3.3V Bootstrap Switch Threshold to Rising edge at BYP regulation point 3.0 3.1 3.2 V
BYP LDOREFIN = VCC
LDO 5V Bootstrap Switch Equivalent LDO to BYP, BYP = 5V, LDOREFIN > (VCC -1V) (Note 5) 0.7 1.5 
Resistance
LDO 3.3V Bootstrap Switch Equivalent LDO to BYP, BYP = 3.3V, LDOREFIN < 0.3V (Note 5) 1.5 3.0 
Resistance
VREF3 Output Voltage No external load, VCC > 4.5V 3.235 3.300 3.365 V
No external load, VCC < 4.0V 3.220 3.300 3.380 V
VREF3 Load Regulation 0 < ILOAD < 5mA 10 mV
VREF3 Current Limit VREF3 = GND 10 17 mA
REF Output Voltage No external load 1.980 2.000 2.020 V
REF Load Regulation 0 < ILOAD < 50µA 10 mV
REF Sink Current REF in regulation 10 µA
VIN Operating Supply Current Both SMPSs on, FB1 = SKIP = GND, REFIN2 = VCC 25 50 µA
VOUT1 = BYP = 5.3V, VOUT2 = 3.5V
VIN Standby Supply Current VIN = 5.5V to 25V, both SMPSs off, EN LDO = VCC 180 250 µA
VIN Shutdown Supply Current VIN = 4.5V to 25V, EN1 = EN2 = EN LDO = 0V 20 30 µA
Quiescent Power Consumption Both SMPSs on, FB1 = SKIP = GND, REFIN2 = VCC, 5 7 mW
VOUT1 = BYP = 5.3V, VOUT2 = 3.5V
FAULT DETECTION
Overvoltage Trip Threshold FB1 with respect to nominal regulation point +8 +11 +14 %
REFIN2 with respect to nominal regulation point +12 +16 +20 %
Overvoltage Fault Propagation Delay FB1 or REFIN2 delay with 50mV overdrive 10 µs
POK Threshold FB1 or REFIN2 with respect to nominal output, falling -12 -9 -6 %
edge, typical hysteresis = 1%
POK Propagation Delay Falling edge, 50mV overdrive 10 µs
POK Output Low Voltage ISINK = 4mA 0.2 V
POK Leakage Current High state, forced to 5.5V 1 µA
Thermal-Shutdown Threshold +150 °C
Out-Of-Bound Threshold FB1 or REFIN2 with respect to nominal output voltage 5 %
Output Undervoltage Shutdown Threshold FB1 or REFIN2 with respect to nominal output voltage 65 70 75 %
Output Undervoltage Shutdown Blanking From EN signal 10 20 30 ms
Time
INPUTS AND OUTPUTS
FB1 Input Voltage Low level 0.3 V
High level VCC - 1.0 V
REFIN2 Input Voltage OUT2 Dynamic Range, VOUT2 = VREFIN2 0.5 2.50 V
Fixed OUT2 = 1.05V 3.0 VCC - 1.1 V
Fixed OUT2 = 3.3V VCC - 1.0 V
FN6373 Rev 6.00 Page 5 of 36

April 29, 2010
ISL6236
MIN MAX
LDOREFIN Input Voltage Fixed LDO = 5V 0.30 V
LDO Dynamic Range, VLDO = 2 x VLDOREFIN 0.35 2.25 V
Fixed LDO = 3.3V VCC - 1.0 V
SKIP Input Voltage Low level (SKIP) 0.8 V
Float level (ULTRASONIC SKIP) 1.7 2.3 V
High level (PWM) 2.4 V
TON Input Voltage Low level 0.8 V
Float level 1.7 2.3 V
High level 2.4 V
EN1, EN2 Input Voltage Clear fault level/SMPS off level 0.8 V
Delay start level 1.7 2.3 V
SMPS on level 2.4 V
EN LDO Input Voltage Rising edge 1.2 1.6 2.0 V
Falling edge 0.94 1.00 1.06 V
Input Leakage Current VtON = 0V or 5V -1 +1 µA
VEN = VEN LDO = 0V or 5V -0.1 +0.1 µA
VSKIP = 0V or 5V -1 +1 µA
VFB1 = VSECFB = 0V or 5V -0.2 +0.2 µA
VREFIN = 0V or 2.5V -0.2 +0.2 µA
VLDOREFIN = 0V or 2.75V -0.2 +0.2 µA
INTERNAL BOOT DIODE
VD Forward Voltage PVCC - VBOOT, IF = 10mA 0.65 0.8 V
IBOOT LEAKAGE Leakage Current VBOOT = 30V, PHASE = 25V, PVCC = 5V 500 nA
MOSFET DRIVERS
UGATE Gate-Driver Sink/Source Current UGATE1, UGATE2 forced to 2V 2 A
LGATE Gate-Driver Source Current LGATE1 (source), LGATE2 (source), forced to 2V 1.7 A
LGATE Gate-Driver Sink Current LGATE1 (sink), LGATE2 (sink), forced to 2V 3.3 A
UGATE Gate-Driver ON-Resistance BST - PHASE forced to 5V (Note 5) 1.5 4.0 
LGATE Gate-Driver ON-Resistance LGATE, high state (pull-up) (Note 5) 2.2 5.0 
LGATE, low state (pull-down) (Note 5) 0.6 1.5 
Dead Time LGATE Rising 15 20 35 ns
UGATE Rising 20 30 50 ns
OUT1, OUT2 Discharge ON-Resistance 25 40 
NOTES:
5. Limits established by characterization and are not production tested.
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Does not apply in PFM mode (see further details on page 26).
FN6373 Rev 6.00 Page 6 of 36

April 29, 2010
ISL6236
Pin Descriptions
PIN
NUMBER NAME FUNCTION
1 REF 2V Reference Output. Bypass to GND with a 0.1µF (min) capacitor. REF can source up to 50µA for external loads.
Loading REF degrades FB and output accuracy according to the REF load-regulation error.
2 TON Frequency Select Input. Connect to GND for 400kHz/500kHz operation. Connect to REF (or leave OPEN) for
400kHz/300kHz operation. Connect to VCC for 200kHz/300kHz operation (5V/3.3V SMPS switching frequencies,
respectively.)
3 VCC Analog Supply Voltage Input for PWM Core. Bypass to GND with a 1µF ceramic capacitor.
4 EN LDO LDO Enable Input. The LDO is enabled if EN LDO is within logic high level and disabled if EN LDO is less than the logic
low level.
5 VREF3 3.3V Reference Output. VREF3 can source up to 5mA for external loads. Bypass to GND with a 0.01µF capacitor if
loaded. Leave open if there is no load.
6 VIN Power-Supply Input. VIN is used for the constant-on-time PWM on-time one-shot circuits. VIN is also used to power the
linear regulators. The linear regulators are powered by SMPS1 if OUT1 is set greater than 4.78V and BYP is tied to
OUT1. Connect VIN to the battery input and bypass with a 1µF capacitor.
7 LDO Linear-Regulator Output. LDO can provide a total of 100mA external loads. The LDO regulate at 5V If LDOREFIN is
connected to GND. When the LDO is set at 5V and BYP is within 5V switchover threshold, the internal regulator shuts
down and the LDO output pin connects to BYP through a 0.7 switch. The LDO regulate at 3.3V if LDOREFIN is
connected to VCC. When the LDO is set at 3.3V and BYP is within 3.3V switchover threshold, the internal regulator
shuts down and the LDO output pin connects to BYP through a 1.5 switch. Bypass LDO output with a minimum of
4.7µF ceramic.
8 LDOREFIN LDO Reference Input. Connect LDOREFIN to GND for fixed 5V operation. Connect LDOREFIN to VCC for fixed 3.3V
operation. LDOREFIN can be used to program LDO output voltage from 0.7V to 4.5V. LDO output is two times the
voltage of LDOREFIN. There is no switchover in adjustable mode.
9 BYP BYP is the switchover source voltage for the LDO when LDOREFIN connected to GND or VCC. Connect BYP to 5V if
LDOREFIN is tied to GND. Connect BYP to 3.3V if LDOREFIN is tied to VCC.
10 OUT1 SMPS1 Output Voltage-Sense Input. Connect to the SMPS1 output. OUT1 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS1 feedback input in fixed-voltage mode.
11 FB1 SMPS1 Feedback Input. Connect FB1 to GND for fixed 5V operation. Connect FB1 to VCC for fixed 1.5V operation
Connect FB1 to a resistive voltage-divider from OUT1 to GND to adjust the output from 0.7V to 5.5V.
12 ILIM1 SMPS1 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM1 over a
0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM1. Connect ILIM1 to REF for a fixed 200mV
threshold. The logic current limit threshold is default to 100mV value if ILIM1 is higher than VCC - 1V.
13 POK1 SMPS1 Power-Good Open-Drain Output. POK1 is low when the SMPS1 output voltage is more than 10% below the
normal regulation point or during soft-start. POK1 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK1 is low in shutdown.
14 EN1 SMPS1 Enable Input. The SMPS1 is enabled if EN1 is greater than the logic high level and disabled if EN1 is less than
the logic low level. If EN1 is connected to REF, the SMPS1 starts after the SMPS2 reaches regulation (delay start). Drive
EN1 below 0.8V to clear fault level and reset the fault latches.
15 UGATE1 High-Side MOSFET Floating Gate-Driver Output for SMPS1. UGATE1 swings between PHASE1 and BOOT1.
16 PHASE1 Inductor Connection for SMPS1. PHASE1 is the internal lower supply rail for the UGATE1 high-side gate driver.
PHASE1 is the current-sense input for the SMPS1.
17 BOOT1 Boost Flying Capacitor Connection for SMPS1. Connect to an external capacitor according to the typical application
circuits (Figures 66, 67 and 68). See “MOSFET Gate Drivers (UGATE, LGATE)” on page 27.
18 LGATE1 SMPS1 Synchronous-Rectifier Gate-Drive Output. LGATE1 swings between GND and PVCC.
19 PVCC PVCC is the supply voltage for the low-side MOSFET driver LGATE. Connect a 5V power source to the PVCC pin and
bypass with a 1µF MLCC ceramic capacitor. Refer to Figure 69 - A switch connects PVCC to VCC with 10when in
normal operation and is disconnected when in shutdown mode. An external 10 resistor from PVCC to VCC is
prohibited as it will create a leakage path from VIN to GND in shutdown mode.
20 SECFB The SECFB is used to monitor the optional external 14V charge pump. Connect a resistive voltage-divider from 14V
charge pump output to GND to detect the output. If SECFB drops below the threshold voltage, LGATE1 turns on for
300ns. This will refresh the external charge pump driven by LGATE1 without over-discharging the output voltage.
FN6373 Rev 6.00 Page 7 of 36

April 29, 2010
ISL6236
Pin Descriptions (Continued)

PIN
NUMBER NAME FUNCTION
21 GND Analog Ground for both SMPS and LDO. Connect externally to the underside of the exposed pad.
22 PGND Power Ground for SMPS controller. Connect PGND externally to the underside of the exposed pad.
23 LGATE2 SMPS2 Synchronous-Rectifier Gate-Drive Output. LGATE2 swings between GND and PVCC.
24 BOOT2 Boost Flying Capacitor Connection for SMPS2. Connect to an external capacitor according to the typical application
circuits (Figures 66, 67 and 68). See “MOSFET Gate Drivers (UGATE, LGATE)” on page 27.
25 PHASE2 Inductor Connection for SMPS2. PHASE2 is the internal lower supply rail for the UGATE2 high-side gate driver.
PHASE2 is the current-sense input for the SMPS2.
26 UGATE2 High-Side MOSFET Floating Gate-Driver Output for SMPS2. UGATE1 swings between PHASE2 and BOOT2.
27 EN2 SMPS2 Enable Input. The SMPS2 is enabled if EN2 is greater than the logic high level and disabled if EN2 is less than
the logic low level. If EN2 is connected to REF, the SMPS2 starts after the SMPS1 reaches regulation (delay start). Drive
EN2 below 0.8V to clear fault level and reset the fault latches.
28 POK2 SMP2 Power-Good Open-Drain Output. POK2 is low when the SMPS2 output voltage is more than 10% below the
normal regulation point or during soft-start. POK2 is high impedance when the output is in regulation and the soft-start
circuit has terminated. POK2 is low in shutdown.
29 SKIP Low-Noise Mode Control. Connect SKIP to GND for normal Idle-Mode (pulse-skipping) operation or to VCC for PWM
mode (fixed frequency). Connect to REF or leave floating for ultrasonic skip mode operation.
30 OUT2 SMPS2 Output Voltage-Sense Input. Connect to the SMPS2 output. OUT2 is an input to the Constant on-time-PWM
on-time one-shot circuit. It also serves as the SMPS2 feedback input in fixed-voltage mode.
31 ILIM2 SMPS2 Current-Limit Adjustment. The GND-PHASE1 current-limit threshold is 1/10th the voltage seen at ILIM2 over a
0.2V to 2V range. There is an internal 5µA current source from VCC to ILIM2. Connect ILIM2 to REF for a fixed 200mV.
The logic current limit threshold is default to 100mV value if ILIM2 is higher than VCC - 1V.
32 REFIN2 Output voltage control for SMPS2. Connect REFIN2 to VCC for fixed 3.3V. Connect REFIN2 to VREF3 for fixed 1.05V.
REFIN2 can be used to program SMPS2 output voltage from 0.5V to 2.50V. SMPS2 output voltage is 0V if
REFIN2 <0.5V.
Typical Performance Curves Circuit of Figures 66, 67 and 68, no load on LDO, OUT1, OUT2, VREF3, and REF, VIN = 12V,
EN2 = EN1 = VCC, VBYP = 5V, PVCC = 5V, VEN LDO = 5V, TA = -40°C to +100°C, unless
otherwise noted. Typical values are at TA = +25°C.
7VIN SKIP MODE 12VIN ULTRA SKIP MODE

7VIN PWM MODE 25VIN SKIP MODE
7VIN PWM MODE 25VIN SKIP MODE
7VIN ULTRA SKIP MODE 25VIN PWM MODE
7VIN ULTRA SKIP MODE 25VIN PWM MODE
12VIN PWM MODE
12VIN PWM MODE
100 100
90 90
80 80
70 70
EFFICIENCY (%)
EFFICIENCY (%)
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
OUTPUT LOAD (A) OUTPUT LOAD (A)
FIGURE 1. VOUT2 = 1.05V EFFICIENCY vs LOAD (300kHz) FIGURE 2. VOUT1 = 1.5V EFFICIENCY vs LOAD (200kHz)
FN6373 Rev 6.00 Page 8 of 36

April 29, 2010
ISL6236
otherwise noted. Typical values are at TA = +25°C. (Continued)
7VIN SKIP MODE 12VIN ULTRA SKIP MODE 7VIN SKIP MODE 12VIN ULTRA SKIP MODE
7VIN PWM MODE 25VIN SKIP MODE 7VIN PWM MODE 25VIN SKIP MODE
7VIN ULTRA SKIP MODE 25VIN PWM MODE 7VIN ULTRA SKIP MODE 25VIN PWM MODE
12VIN PWM MODE 12VIN PWM MODE
100 100
90 90
80 80
70 70
EFFICIENCY (%)
EFFICIENCY (%)
60 60
50 50
40 40
30 30
20 20
10 10
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
FIGURE 3. VOUT2 = 3.3V EFFICIENCY vs LOAD (500kHz) FIGURE 4. VOUT1 = 5V EFFICIENCY vs LOAD (400kHz)
1.070 1.540
1.068 1.535
1.066
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.530
1.064
1.062 1.525
1.060 1.520
1.058 1.515
1.056
1.510
1.054
1.052 1.505
1.050 1.500
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
FIGURE 5. VOUT2 = 1.05V REGULATION vs LOAD (300kHz) FIGURE 6. VOUT1 = 1.5V REGULATION vs LOAD (200kHz)
3.38 5.16
3.37 5.14
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
5.12
3.36
5.10
3.35
5.08
3.34
5.06
3.33
5.04
3.32 5.02
3.31 5.00
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
FIGURE 7. VOUT2 = 3.3V REGULATION vs LOAD (500kHz) FIGURE 8. VOUT1 = 5V REGULATION vs LOAD (400kHz)
FN6373 Rev 6.00 Page 9 of 36

April 29, 2010
ISL6236
2.5 2.5
POWER DISSIPATION (W)

2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0.0 0.0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
FIGURE 9. VOUT2 = 1.05V POWER DISSIPATION vs LOAD FIGURE 10. VOUT1 = 1.5V POWER DISSIPATION vs LOAD
(300kHz) (200kHz)
3.5 3.5
3.0 3.0
2.5 2.5
2.0 2.0
1.5 1.5
1.0 1.0
0.5 0.5
0.0 0.0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
FIGURE 11. VOUT2 = 3.3V POWER DISSIPATION vs LOAD FIGURE 12. VOUT1 = 5V POWER DISSIPATION vs LOAD
(500kHz) (400kHz)
1.064 1.068
NO LOAD PWM
1.062 1.066
1.064
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
1.060
1.062 NO LOAD PWM
1.058
1.060
1.056 1.058
1.054 MID LOAD PWM 1.056

1.054
1.052 MID LOAD PWM
MAX LOAD PWM 1.052
1.050 MAX LOAD PWM
1.050
1.048 1.048
5 7 9 11 13 15 17 19 21 23 25 5 7 9 11 13 15 17 19 21 23 25
INPUT VOLTAGE (V) INPUT VOLTAGE (V)
FIGURE 13. VOUT2 = 1.05V OUTPUT VOLTAGE REGULATION FIGURE 14. VOUT2 = 1.05V OUTPUT VOLTAGE REGULATION
vs VIN (PWM MODE) vs VIN (SKIP MODE)
FN6373 Rev 6.00 Page 10 of 36

April 29, 2010
ISL6236
1.518 1.530
1.516 1.525
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)

NO LOAD PWM
1.514 NO LOAD PWM
1.520
1.512 MID LOAD PWM
MID LOAD PWM 1.515
1.510
MAX LOAD PWM 1.510
1.508 MAX LOAD PWM
1.506 1.505
1.504 1.500
5 7 9 11 13 15 17 19 21 23 25 5 7 9 11 13 15 17 19 21 23 25
3.340 3.38
3.37
3.335 NO LOAD PWM
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
3.36
NO LOAD PWM
3.330
3.35
3.325 3.34 MAX LOAD PWM
3.33
3.320
3.32
MID LOAD PWM
3.315
3.31 MID LOAD PWM
MAX LOAD PWM
3.310 3.30
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
5.065
NO LOAD PWM 5.14
5.060
5.12
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
MAX LOAD PWM 5.10

5.055 NO LOAD PWM
MID LOAD PWM
5.08
5.050 MID LOAD PWM
5.06
5.045
5.04
MAX LOAD PWM
5.040 5.02
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
FIGURE 19. VOUT1 = 5V OUTPUT VOLTAGE REGULATION vs FIGURE 20. VOUT1 = 5V OUTPUT VOLTAGE REGULATION vs
VIN (PWM MODE) VIN (SKIP MODE)
FN6373 Rev 6.00 Page 11 of 36

April 29, 2010
ISL6236
300 50
45
250
40
FREQUENCY (kHz)
35
200
RIPPLE (mV)
PWM 30
150 25 PWM
ULTRA-SKIP
20
100
ULTRA-SKIP 15
10
50
5 SKIP
SKIP
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
FIGURE 21. VOUT2 = 1.05V FREQUENCY vs LOAD FIGURE 22. VOUT2 = 1.05V RIPPLE vs LOAD
250 50
PWM 45
200 40
PWM
FREQUENCY (kHz)
35
RIPPLE (mV)
150 30
25
100 20 ULTRA-SKIP SKIP
ULTRA-SKIP
15
50 10
SKIP 5
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
600 14
PWM PWM
500 12
FREQUENCY (kHz)
10
400
RIPPLE (mV)
8 ULTRA-SKIP
300 SKIP
6
200
ULTRA-SKIP 4
100 2
SKIP
0 0
0.001 0.010 0.100 1.000 10.000 0.001 0.010 0.100 1.000 10.000
FN6373 Rev 6.00 Page 12 of 36

April 29, 2010
ISL6236
450 40
PWM
400 35
350 30
FREQUENCY (kHz)
PWM ULTRA-SKIP
300
RIPPLE (mV)
25
250
20
200 SKIP
15
150
100 ULTRA-SKIP 10
50 5
SKIP
0 0
0.001 1.000 10.000 0.001 0.010 0.100 1.000 10.000
FIGURE 27. VOUT1 = 5V FREQUENCY vs LOAD FIGURE 28. VOUT1 = 5V RIPPLE vs LOAD
5.04 3.35
5.02
BYP = 0V 3.30
5.00
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
4.98 3.25
BYP = 0V
4.96
3.20
4.94
4.92 3.15
4.90 BYP = 3.3V

3.10
4.88 BYP = 5V
3.05
4.86
4.84 3.00
0 50 100 150 200 0 50 100 150 200
OUTPUT LOAD (mA) OUTPUT LOAD (mA)
FIGURE 29. LDO OUTPUT 5V vs LOAD FIGURE 30. LDO OUTPUT 3.3V vs LOAD
3.5 15.5
3.0
15.0
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
2.5
14.5
2.0
14.0
1.5
13.5
1.0
0.5 13.0
0 12.5
0 2 4 6 8 10 0 2 4 5 8 10
OUTPUT LOAD (mA) OUTPUT LOAD (mA)
FIGURE 31. VREF3 vs LOAD FIGURE 32. CHARGE PUMP vs LOAD (PWM)
FN6373 Rev 6.00 Page 13 of 36

April 29, 2010
ISL6236
50 1400
45 1200
INPUT CURRENT (mA)
INPUT CURRENT (µA)

1000
40
800
35
600
30
400
25
200
20 0.0
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
FIGURE 33. PWM NO LOAD INPUT CURRENT vs VIN FIGURE 34. SKIP NO LOAD INPUT CURRENT vs VIN
(EN = EN2 = EN LDO = VCC) (EN1 = EN2 = EN LDO = VCC)
177.5 26.5
177.0 26.0
176.5 25.5
INPUT CURRENT (µA)
INPUT CURRENT (µA)
176.0 25.0
175.5 24.5
175.0 24.0
174.5 23.5
174.0 23.0
173.5 22.5
173.0 22.0
7 9 11 13 15 17 19 21 23 25 7 9 11 13 15 17 19 21 23 25
FIGURE 35. STANDBY INPUT CURRENT vs VIN FIGURE 36. SHUTDOWN INPUT CURRENT vs VIN
(EN = EN2 = 0, EN LDO = VCC) (EN = EN2 = EN LDO = 0)
VREF3 500mV/DIV
EN1 5V/DIV
VOUT1 2V/DIV
LDO 1V/DIV
CP 5V/DIV
REF 1V/DIV IL1 2A/DIV
POK1 2V/DIV
FIGURE 37. REF, VREF3, LDO = 5V, CP, NO LOAD FIGURE 38. START-UP VOUT1 = 5V (NO LOAD, SKIP MODE)
FN6373 Rev 6.00 Page 14 of 36

April 29, 2010
ISL6236
EN1 5V/DIV EN1 5V/DIV
VOUT1 2V/DIV VOUT1 2V/DIV
IL1 2A/DIV IL1 5A/DIV
POK1 2V/DIV POK1 2V/DIV
FIGURE 39. START-UP VOUT1 = 5V (NO LOAD, PWM MODE) FIGURE 40. START-UP VOUT1 = 5V (FULL LOAD, PWM MODE)
IL2 2A/DIV
IL2 2A/DIV
FIGURE 41. START-UP VOUT2 = 3.3V (NO LOAD, SKIP MODE) FIGURE 42. START-UP VOUT1 = 3.3V (NO LOAD, PWM MODE)
EN2 5V/DIV
EN2 5V/DIV
VOUT2 2V/DIV
IL2 5A/DIV POK2 5V/DIV
FIGURE 43. START-UP VOUT1 = 3.3V (FULL LOAD, FIGURE 44. DELAYED START-UP (VOUT1 = 5V, VOUT2 = 3.3V,
PWM MODE) EN1 = REF)
FN6373 Rev 6.00 Page 15 of 36

April 29, 2010
ISL6236
EN1 5V/DIV
EN1 5V/DIV VOUT2 2V/DIV
POK1 5V/DIV VOUT1 2V/DIV
POK2 5V/DIV POK1 OR POK2 5V/DIV
FIGURE 45. DELAYED START-UP (VOUT1 = 5V, VOUT2 = 3.3V, FIGURE 46. SHUTDOWN (VOUT1 = 5V, VOUT2 = 3.3V,
EN2 = REF) EN2 = REF)
LGATE1 5V/DIV LGATE1 5V/DIV
VOUT1 RIPPLE 50mV/DIV
VOUT2 RIPPLE 50mV/DIV VOUT2 RIPPLE 50mV/DIV
FIGURE 47. LOAD TRANSIENT VOUT1 = 5V FIGURE 48. LOAD TRANSIENT VOUT1 = 5V (SKIP)
IL2 5A/DIV
IL2 5A/DIV VOUT2 RIPPLE 50mV/DIV
FIGURE 49. LOAD TRANSIENT VOUT1 = 3.3V (PWM) FIGURE 50. LOAD TRANSIENT VOUT1 = 3.3V (SKIP)
FN6373 Rev 6.00 Page 16 of 36

April 29, 2010
ISL6236
VOUT RIPPLE 20mV/DIV
VOUT RIPPLE 20mV/DIV

LDO 1V/DIV
VOUT2 0.5V/DIV
REFIN2 0.5V/DIV LDOREFIN 0.5V/DIV
LDO RIPPLE 50mV/DIV VOUT2 RIPPLE 50mV/DIV
FIGURE 51. VOUT2 TRACKING TO REFIN2 FIGURE 52. LDO TRACKING TO LDOREFIN
VOUT1 0.5V/DIV VOUT1 0.5V/DIV
IL1 2A/DIV
IL1 2A/DIV
FIGURE 53. START-UP VOUT1 = 1.5V (NO LOAD, SKIP MODE) FIGURE 54. START-UP VOUT1 = 1.5V (NO LOAD, PWM MODE)

VOUT1 0.5V/DIV
VOUT2 0.5V/DIV
FIGURE 55. START-UP VOUT1 = 1.5V (FULL LOAD, FIGURE 56. START-UP VOUT2 = 1.05V (NO LOAD,
PWM MODE) SKIP MODE)
FN6373 Rev 6.00 Page 17 of 36

April 29, 2010
ISL6236
EN2 5V/DIV
EN2 5V/DIV VOUT2 0.5V/DIV
VOUT2 0.5V/DIV
IL2 2A/DIV
IL2 2A/DIV
FIGURE 57. START-UP VOUT1 = 1.05V (NO LOAD, FIGURE 58. START-UP VOUT1 = 1.05V (FULL LOAD,
PWM MODE) PWM MODE)
EN2 5V/DIV VOUT1 2V/DIV
EN1 500mV/DIV
VOUT2 0.5V/DIV
VOUT1 2V/DIV VOUT2 500mV/DIV
FIGURE 59. DELAYED START-UP (VOUT1 = 1.5V, FIGURE 60. DELAYED START-UP (VOUT1 = 1.5V,
VOUT2 = 1.05V, EN1 = REF) VOUT2 = 1.05V, EN2 = REF)
LGATE1 5V/DIV
EN1 5V/DIV

VOUT2 2V/DIV
VOUT1 2V/DIV
IL1 5A/DIV
POK1 OR POK2 5V/DIV

FIGURE 61. SHUTDOWN (VOUT1 = 1.5V, VOUT2 = 1.05V, FIGURE 62. LOAD TRANSIENT VOUT1 = 1.5V (PWM)
EN2 = REF)
FN6373 Rev 6.00 Page 18 of 36

April 29, 2010
ISL6236

VOUT2 RIPPLE 20mV/DIV VOUT2 RIPPLE 20mV/DIV
FIGURE 63. LOAD TRANSIENT VOUT1 = 1.5V (SKIP) FIGURE 64. LOAD TRANSIENT VOUT1 = 1.05V (PWM)
LGATE2 5V/DIV
IL2 5A/DIV
FIGURE 65. LOAD TRANSIENT VOUT1 = 1.05V (SKIP)
Typical Application Circuits provides a pin-selectable switching frequency, allowing

operation for 200kHz/300kHz, 400kHz/300kHz, or
The typical application circuits (Figures 66, 67 and 68)
400kHz/500kHz on the SMPSs.
generate the 5V/7A, 3.3V/11A, 1.25V/5A, dynamic voltage/10A,
1.5V/5A, 1.05V/5A and external 14V charge pump main Light-load efficiency is enhanced by automatic Idle-Mode
supplies in a notebook computer. The ISL6236 is also equipped operation, a variable-frequency pulse-skipping mode that
with a secondary feedback, SECFB, used to monitor the output reduces transition and gate-charge losses. Each step-down,
of the 14V charge pump. In an event when the 14V drops power-switching circuit consists of 2 N-channel MOSFETs, a
below its threshold voltage, SECFB comparator will turn on rectifier, and an LC output filter. The output voltage is the
LGATE1 for 300ns. This will refresh an external 14V charge average AC voltage at the switching node, which is
pump without overcharging the output voltage. The input supply regulated by changing the duty cycle of the MOSFET
range is 5.5V to 25V. switches. The gate-drive signal to the N-channel high-side
MOSFET must exceed the battery voltage, and is provided
Detailed Description
by a flying-capacitor boost circuit that uses a 100nF
The ISL6236 dual-buck, BiCMOS, switch-mode capacitor connected to BOOT.
power-supply controller generates logic supply voltages for
notebook computers. The ISL6236 is designed primarily for Both SMPS1 and SMPS2 PWM controllers consist of a
battery-powered applications where high efficiency and triple-mode feedback network and multiplexer, a multi-input
low-quiescent supply current are critical. The ISL6236 PWM comparator, high-side and low-side gate drivers and
FN6373 Rev 6.00 Page 19 of 36

April 29, 2010
ISL6236
logic. In addition, SMPS2 can also use REFIN2 to track its measured by the VIN input and proportional to the output
output from 0.5V to 2.50V. The ISL6236 contains fault-protection voltage. This algorithm results in a nearly constant switching
circuits that monitor the main PWM outputs for undervoltage and frequency despite the lack of a fixed-frequency clock
overvoltage conditions. A power-on sequence block controls the generator. The benefit of a constant switching frequency is that
power-up timing of the main PWMs and monitors the outputs for the frequency can be selected to avoid noise-sensitive
undervoltage faults. The ISL6236 includes an adjustable low frequency regions:
drop-out linear regulator. The bias generator blocks include the K  V OUT + I LOAD  r DS  ON   LOWERQ  
t ON = ---------------------------------------------------------------------------------------------------------- (EQ. 1)
linear regulator, 3.3V precision reference, 2V precision V IN
reference and automatic bootstrap switchover circuit.
See Table 2 for approximate K- factors. Switching frequency
The synchronous-switch gate drivers are directly powered from
increases as a function of load current due to the increasing
PVCC, while the high-side switch gate drivers are indirectly
drop across the synchronous rectifier, which causes a faster
powered from PVCC through an external capacitor and an
inductor-current discharge ramp. ON-times translate only
internal Schottky diode boost circuit.
roughly to switching frequencies. The ON-times established in
An automatic bootstrap circuit turns off the LDO linear the “Electrical Specifications” table starting on page 3 are
regulator and powers the device from BYP if LDOREFIN is set influenced by switching delays in the external high-side power
to GND or VCC. See Table 1. MOSFET. Also, the dead-time effect increases the effective
TABLE 1. LDO OUTPUT VOLTAGE TABLE
ON-time, reducing the switching frequency. It occurs only in
PWM mode (SKIP = VCC) and during dynamic output voltage
LDO VOLTAGE CONDITIONS COMMENT transitions when the inductor current reverses at light or
VOLTAGE at BYP LDOREFIN < 0.3V, Internal LDO is negative load currents. With reversed inductor current, the
BYP > 4.63V disabled. inductor's EMF causes PHASE to go high earlier than normal,
VOLTAGE at BYP LDOREFIN > VCC - 1V, Internal LDO is extending the ON-time by a period equal to the UGATE-rising
BYP > 3V disabled. dead time.
5V LDOREFIN < 0.3V, Internal LDO is TABLE 2. APPROXIMATE K-FACTOR ERRORS
BYP < 4.63V active.
SWITCHING APPROXIMATE
3.3V LDOREFIN > VCC - 1V, Internal LDO is FREQUENCY K-FACTOR K-FACTOR
BYP < 3V active. SMPS (kHz) (µs) ERROR (%)
2 x LDOREFIN 0.35V < LDOREFIN < 2.25V Internal LDO is (tON = GND, REF, 400 2.5 ±10
active. or OPEN), VOUT1
(tON = GND), 500 2.0 ±10

FREE-RUNNING, CONSTANT ON-TIME PWM VOUT2
CONTROLLER WITH INPUT FEED-FORWARD (tON = VCC), 200 5.0 ±10
The constant on-time PWM control architecture is a VOUT1
pseudo-fixed-frequency, constant ON-time, current-mode type (tON = VCC, REF, 300 3.3 ±10
with voltage feed-forward. The constant ON-time PWM control or OPEN), VOUT2
architecture relies on the output ripple voltage to provide the
PWM ramp signal; thus the output filter capacitor's ESR acts For loads above the critical conduction point, the actual
as a current-feedback resistor. The high-side switch ON-time is switching frequency is:
determined by a one-shot whose period is inversely
V OUT + V DROP1
proportional to input voltage and directly proportional to output f = ------------------------------------------------------- (EQ. 2)
t ON  V IN + V DROP2 
voltage. Another one-shot sets a minimum OFF-time (300ns
typ). The ON-time one-shot triggers when the following
where:
conditions are met: the error comparator's output is high, the
synchronous rectifier current is below the current-limit • VDROP1 is the sum of the parasitic voltage drops in the
threshold, and the minimum off time one-shot has timed out. inductor discharge path, including synchronous rectifier,
The controller utilize the valley point of the output ripple to inductor, and PC board resistances
regulate and determine the OFF-time. • VDROP2 is the sum of the parasitic voltage drops in the
ON-TIME ONE-SHOT (tON) charging path, including high-side switch, inductor, and PC
board resistances
Each PWM core includes a one-shot that sets the high-side
switch ON-time for each controller. Each fast, low-jitter, • tON is the ON-time calculated by the ISL6236
adjustable one-shot includes circuitry that varies the ON-time
in response to battery and output voltage. The high-side switch
ON-time is inversely proportional to the battery voltage as
FN6373 Rev 6.00 Page 20 of 36

April 29, 2010
ISL6236
VIN: 5.5V TO 25V
5V
C5
1µF
C8
1µF
PVCC VCC LDO NC
VIN LDOREFIN GND

C10 C1
10µF BOOT1 BOOT2 10
10µF
Q3a Q1
SI4816BDY UGATE1 UGATE2 IRF7821
OUT1 – PCI-e C9 C4 OUT2-GFX
L1: 3.3µH L2: 2.2µH TRACK REFIN2/10A
1.25V/5A 0.1µF 0.22µF
PHASE1 PHASE2
Q3b Q2
C11 LGATE1 LGATE2 C2
330µF IRF7832
2 x 330µF
9m 4m
6.3V OUT1 PGND 6.3V
VCC
R1 OUT2
EN1
7.87k
5V BYP VCC 2 BITS
ISL6236 EN2
DAC
REFIN2: DYNAMIC 0 TO 2.5V
FB1 REFIN2 TIED TO VREF3 = 1.05V
FB1 TIED TO GND = 5V
FB1 TIED TO VCC = 1.5V REFIN2 TIED TO VCC = 3.3V + -
AGND REFIN2 + DROOP
R2 R3 R5
200k 200k +
10k
ILIM1 ILIM2
C3 VCC VCC
OPEN
SKIP VREF3
C7 R4 R6
GND EN LDO 0.1µF
REF 200k 200k
VCC SECFB POK1
VCC TON POK2

PAD
FREQUENCY-DEPENDENT COMPONENTS
1.25V/1.05V SMPS tON = VCC

SWITCHING
FREQUENCY 200kHz/300kHz
L1 3.3µH
L2 2.7µH
C2 2 x 330µF
C11 330µF
FIGURE 66. ISL6236 TYPICAL DYNAMIC GFX APPLICATION CIRCUIT
FN6373 Rev 6.00 Page 21 of 36

April 29, 2010
ISL6236
VIN: 5.5V TO 25V
5V
C5
1µF
LDOREFIN TIED TO GND = 5V
C8 LDOREFIN TIED TO VCC = 3.3V
1µF
LDO
PVCC VCC LDO
VCC C6
VIN LDOREFIN 4.7µF
F
C10 C1
10µF SI4816BDY BOOT1 BOOT2 10
10µF
Q3a
UGATE2 Q1a
UGATE1
OUT1 C9 C4 OUT2
L1: 3.3µH L2: 2.2µF 1.05V/5A
1.5V/5A 0.1µF 0.22µF
PHASE1 PHASE2
Q3b
C11 LGATE2 Q1b SI4816BDY C2
LGATE1
330µF 330µF
9m 4m
6.3V OUT1 PGND 6.3V
VCC
EN1 OUT2
3.3V BYP ISL6236 VCC

EN2
VCC
FB1 TIED TO GND = 5V FB1 REFIN2: DYNAMIC 0V TO 2.5V
FB1 TIED TO VCC = 1.5V REFIN2 TIED TO VREF3 = 1.05V
REFIN2 VREF3 REFIN2 TIED TO VCC = 3.3V
AGND
R3 R5
200k 200k
ILIM1 ILIM2
C3 VCC VCC
0.01µF
SKIP VREF3
ON C7 R4 R6
EN LDO 0.1µF 200k
REF 200k
OFF
VCC SECFB POK1
VCC TON POK2

PAD
1.5V/1.05V SMPS tON = VCC

SWITCHING
FREQUENCY 200kHz/300kHz
L1 3.3µH
L2 2.7µH
C2 330µF
C11 330µF
FIGURE 67. ISL6236 TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITHOUT CHARGE PUMP
FN6373 Rev 6.00 Page 22 of 36

April 29, 2010
ISL6236
VIN: 5.5V TO 25V
C5
1µF
LDOREFIN TIED TO GND = 5V
LDOREFIN TIED TO VCC = 3.3V
VCC LDO
PVCC LDO
C6
VIN LDOREFIN
4.7µF
C10 C1
10µF BOOT1 BOOT2 10µF
10
Q3 Q1
IRF7807V UGATE1 UGATE2 IRF7821
OUT1 C9 C4 OUT2
L1: 4.7µH 0.1µF L2: 4.7µH 3.3V/11A
5V/7A 0.1µF
PHASE1 PHASE2
Q4 Q2
C11 LGATE1 LGATE2 C2
IRF7811AV IRF7832
330µF 330µF
9m 9m
6.3V OUT1 PGND 4V
VCC
D3 EN1 ISL6236 OUT2
BYP EN2 VCC

D1 REFIN2: DYNAMIC 0 TO 2V
C8 FB1 REFIN2 TIED TO VREF3 = 1.05V
C12 0.1µF FB1 TIED TO GND = 5V
D1a FB1 TIED TO VCC = 1.5V REFIN2 TIED TO VCC = 3.3V
0.1µF AGND REFIN2 VCC
D1b R3 R5
200k 150k
ILIM1 ILIM2
C3 VCC VCC
C14
OPEN
0.1µF SKIP VREF3
CP D2a
14V/10mA ON C7 R4 R6
D2b 0.1µF
EN LDO 200k 200k
REF
D2 OFF
C15
0.1µF SECFB POK1
R1 GND
200k R2 TON POK2
39.2k
PAD
tON = REF
5V/3.3V SMPS tON = VCC (OR OPEN) tON = GND
SWITCHING
FREQUENCY 200kHz/300kHz 400kHz/300kHz 400kHz/500kHz
L1 6.8µH 6.8µH 4.7µH
L2 7.6µH 4.7µH 4.7µH
C2 2x470µF 2x330µF 2x330µF
C11 330µF 330µF 330µF
FIGURE 68. ISL6236 TYPICAL SYSTEM REGULATOR APPLICATION CIRCUIT WITH 14V CHARGE PUMP
I
FN6373 Rev 6.00 Page 23 of 36

April 29, 2010
ISL6236
TON SKIP
BOOT1 BOOT2
UGATE1 UGATE2
PHASE1 PHASE2
PVCC PVCC
LGATE1 SMPS1 SMPS2

LGATE2
SYNCHRONOUS SYNCHRONOUS
PWM BUCK PWM BUCK
GND CONTROLLER CONTROLLER
PGND
ILIM1 ILIM2
EN1 EN2
SECFB
FB1 POK1 POK2 REFIN2
OUT1 OUT2
OUT1 OUT2
BYP POK2
SW THRESHOLD
-
POK1
LDO
LDO
VCC
LDOREFIN INTERNAL
LOGIC
10
VIN
PVCC
EN LDO
POWER-ON VREF3
POWER-ON VREF3
EN1 SQUENCE
SEQUENCE
CLEARFAULT
CLEAR FAULT
LATCH
EN2 LATCH THERMAL
THERMAL REF
SHUTDOWN
SHUTDOWN REF
FIGURE 69. DETAILED FUNCTIONAL DIAGRAM ISL6236
FN6373 Rev 6.00 Page 24 of 36

April 29, 2010
ISL6236
tON
MIN. tOFF
VIN Q TRIG
ONE SHOT
+ TO UGATE DRIVER
OUT R QQ
S Q
Q
REFIN2 (SMPS2)
+
+
VREF +
ILIM +
COMP
+ SLOPE COMP +
BOOT BOOT
UV
5µA DETECT
VCC +
TO LGATE DRIVER
Â
S
+
PHASE
OUT
+ Q
S Q
R Q
Q
SKIP ONE-SHOT
SECFB
+
2V
FB + SMSP1 ONLY
DECODER PGOOD
0.9VREF
FB
OV LATCH
+
1.1VREF FAULT
FAULT
LATCH
UV LATCH LATCH
LOGIC
+
20ms
0.7VREF
BLANKING
FIGURE 70. PWM CONTROLLER (ONE SIDE ONLY)
Automatic Pulse-Skipping Switchover (Idle

Mode) I V IN -V OUT
=
In Idle Mode (SKIP = GND), an inherent automatic switchover to t L
I PEAK
PFM takes place at light loads. This switchover is affected by a
INDUCTOR CURRENT
comparator that truncates the low-side switch ON-time at the

inductor current's zero crossing. This mechanism causes the
threshold between pulse-skipping PFM and non-skipping PWM
ILOAD = IPEAK/2
operation to coincide with the boundary between continuous and
discontinuous inductor-current operation (also known as the
critical conduction point):
K  V OUT V IN – V OUT
I LOAD  SKIP  = ------------------------ -------------------------------- (EQ. 3)
2L V IN
where K is the ON-time scale factor (see “ON-TIME ONE- 0 ON-TIME TIME
SHOT (tON)” on page 20). The load-current level at which FIGURE 71. ULTRASONIC CURRENT WAVEFORMS
PFM/PWM crossover occurs, ILOAD(SKIP), is equal to half the
peak-to-peak ripple current, which is a function of the inductor The switching waveforms may appear noisy and asynchronous
value (Figure 71). For example, in the ISL6236 typical when light loading causes pulse-skipping operation, but this is
application circuit with VOUT1 = 5V, VIN = 12V, L = 7.6µH, and a normal operating condition that results in high light-load
K = 5µs, switchover to pulse-skipping operation occurs at efficiency. Trade-offs in PFM noise vs light-load efficiency are
ILOAD = 0.96A or about on-fifth full load. The crossover point made by varying the inductor value. Generally, low inductor
occurs at an even lower value if a swinging (soft-saturation) values produce a broader efficiency vs load curve, while higher
inductor is used. values result in higher full-load efficiency (assuming that the
FN6373 Rev 6.00 Page 25 of 36

April 29, 2010
ISL6236
coil resistance remains fixed) and less output voltage ripple. with a UGATE pulse, as long as VFB < VREF, LGATE is off
Penalties for using higher inductor values include larger and UGATE is on, similar to pure SKIP mode.
physical size and degraded load-transient response (especially
40µs (MAX)
at low input-voltage levels).
INDUCTOR
DC output accuracy specifications refer to the trip level of the CURRENT
error comparator. When the inductor is in continuous
conduction, the output voltage has a DC regulation higher than
the trip level by 50% of the ripple. In discontinuous conduction
(SKIP = GND, light load), the output voltage has a DC
ZERO-CROSSING
Zero-Crossing
regulation higher than the trip level by approximately 1.0% due DETECTION
Detection
to slope compensation.
0A
Forced-PWM Mode FB<REG.POINT
FB<Reg.Point
The low-noise, forced-PWM (SKIP = VCC) mode disables the
zero-crossing comparator, which controls the low-side switch
) )
ON-TIME (tON)ON
ON-time. Disabling the zero-crossing detector causes the low-
side, gate-drive waveform to become the complement of the FIGURE 72. ULTRASONIC CURRENT WAVEFORMS
high-side, gate-drive waveform. The inductor current reverses
at light loads as the PWM loop strives to maintain a duty ratio
Reference and Linear Regulators (VREF3,
of VOUT/VIN. The benefit of forced-PWM mode is to keep the
switching frequency fairly constant, but it comes at a cost: the
REF, LDO and 14V Charge Pump)
no-load battery current can be 10mA to 50mA, depending on The 3.3V reference (VREF3) is accurate to ±1.5%
switching frequency and the external MOSFETs. over-temperature, making VREF3 useful as a precision system
reference. VREF3 can supply up to 5mA for external loads.
Forced-PWM mode is most useful for reducing Bypass VREF3 to GND with a 0.01µF capacitor. Leave it open
audio-frequency noise, improving load-transient response, if there is no load.
providing sink-current capability for dynamic output voltage
adjustment, and improving the cross-regulation of The 2V reference (REF) is accurate to ±1% over-temperature,
multiple-output applications that use a flyback transformer or also making REF useful as a precision system reference.
coupled inductor. Bypass REF to GND with a 0.1µF (min) capacitor. REF can
supply up to 50µA for external loads.
Enhanced Ultrasonic Mode An internal regulator produces a fixed 5V (LDOREFIN < 0.2V)
(25kHz (min) Pulse Skipping) or 3.3V (LDOREFIN > VCC - 1V). In an adjustable mode, the
Leaving SKIP unconnected or connecting SKIP to REF LDO output can be set from 0.7V to 4.5V. The LDO output
activates a unique pulse-skipping mode with a minimum voltage is equal to two times the LDOREFIN voltage. The LDO
switching frequency of 25kHz. This ultrasonic pulse-skipping regulator can supply up to 100mA for external loads. Bypass
mode eliminates audio-frequency modulation that would LDO with a minimum 4.7µF ceramic capacitor. When the
otherwise be present when a lightly loaded controller LDOREFIN < 0.2V and BYP voltage is 5V, the LDO bootstrap-
automatically skips pulses. In ultrasonic mode, the controller switchover to an internal 0.7 P-Channel MOSFET switch
automatically transitions to fixed-frequency PWM operation connects BYP to LDO pin while simultaneously shutting down
when the load reaches the same critical conduction point the internal linear regulator. These actions bootstrap the
(ILOAD(SKIP)). device, powering the loads from the BYP input voltages, rather
than through internal linear regulators from the battery.
An ultrasonic pulse occurs when the controller detects that no
Similarly, when the BYP = 3.3V and LDOREFIN = VCC, the
switching has occurred within the last 20µs. Once triggered,
LDO bootstrap-switchover to an internal 1.5 P-Channel
the ultrasonic controller pulls LGATE high, turning on the low-
MOSFET switch connects BYP to LDO pin while
side MOSFET to induce a negative inductor current. After FB
simultaneously shutting down the internal linear regulator. No
drops below the regulation point, the controller turns off the
switchover action in adjustable mode.
low-side MOSFET (LGATE pulled low) and triggers a constant
ON-time (UGATE driven high). When the ON-time has expired, In Figure 68, the external 14V charge pump is driven by
the controller re-enables the low-side MOSFET until the LGATE1. When LGATE1 is low, D1a charged C8 sourced from
controller detects that the inductor current dropped below the OUT1. C8 voltage is equal to OUT1 minus a diode drop. When
zero-crossing threshold. Starting with a LGATE pulse greatly LGATE1 transitions to high, the charges from C8 will transfer to
reduces the peak output voltage when compared to starting C12 through D1b and charge it to VLGATE1 plus VC8. As
LGATE1 transitions low on the next cycle, C12 will charge C14
to its voltage minus a diode drop through D2a. Finally, C14
FN6373 Rev 6.00 Page 26 of 36

April 29, 2010
ISL6236
charges C15 through D2b when LAGET1 switched to high. CP current-sense element. Use the worst-case maximum value for
output voltage is: rDS(ON) from the MOSFET data sheet. Add some margin for
the rise in rDS(ON) with temperature. A good general rule is to
CP = V OUT1 + 2  V LGATE1 – 4  V D (EQ. 4)
allow 0.5% additional resistance for each °C of temperature
rise. The ISL6236 controller has a built-in 5µA current source,
where: as shown in Figure 74. Place the hottest power MOSEFTs as
• VLGATE1 is the peak voltage of the LGATE1 driver close to the IC as possible for best thermal coupling. The
current limit varies with the ON-resistance of the synchronous
• VD is the forward diode dropped across the Schottkys rectifier. When combined with the undervoltage-protection
SECFB is used to monitor the charge pump through resistive circuit, this current-limit method is effective in almost every
divider. In an event when SECFB dropped below 2V, the circumstance.
detection circuit force the highside MOSFET (SMPS1) off and
the low-side MOSFET (SMPS1) on for 300ns to allow CP to
recharge and SECFB rise above 2V. In the event of an
ILIM
overload on CP where SECFB can not reach more than 2V, the +
monitor will be deactivated. Special care should be taken to
ensure enough normal voltage ripple on each cycle as to
5
5µA
prevent CP shut-down. The SECFB pin has ~17mV of +
hysteresis, so the ripple should be enough to bring the SECFB
RILIM VILIM 9R TO CURRENT
voltage above the threshold by ~3x the hysteresis, or (2V + VCC LIMIT LOGIC
3*17mV) = 2.051V. Reducing the CP decoupling capacitor and
placing a small ceramic capacitor (10pF to 47pF) in parallel R
with the upper leg of the SECFB resistor feedback network (R1
of Figure 68), will also increase the robustness of the charge
pump.
Current-Limit Circuit (ILIM) with rDS(ON) FIGURE 74. CURRENT LIMIT BLOCK DIAGRAM
Temperature Compensation
A negative current limit prevents excessive reverse inductor
The current-limit circuit employs a "valley" current-sensing currents when VOUT sinks current. The negative current-limit
algorithm. The ISL6236 uses the ON-resistance of the threshold is set to approximately 120% of the positive current
synchronous rectifier as a current-sensing element. If the limit and therefore tracks the positive current limit when ILIM is
magnitude of the current-sense signal at PHASE is above the adjusted. The current-limit threshold is adjusted with an
current-limit threshold, the PWM is not allowed to initiate a new external resistor for ISL6236 at ILIM. The current-limit
cycle. The actual peak current is greater than the current-limit threshold adjustment range is from 20mV to 200mV. In the
threshold by an amount equal to the inductor ripple current. adjustable mode, the current-limit threshold voltage is 1/10th
Therefore, the exact current-limit characteristic and maximum the voltage at ILIM. The voltage at ILIM pin is the product of
load capability are a function of the current-limit threshold, 5µA*RILIM. The threshold defaults to 100mV when ILIM is
inductor value and input and output voltage. connected to VCC. The logic threshold for switch-over to the
100mV default value is approximately VCC -1V.
The PC board layout guidelines should be carefully observed

I PEAK
to ensure that noise and DC errors do not corrupt the current-
sense signals at PHASE.
INDUCTOR CURRENT
I LOAD
I
MOSFET Gate Drivers (UGATE, LGATE)
I LIMIT The UGATE and LGATE gate drivers sink 2.0A and 3.3A
I LOAD(MAX) respectively of gate drive, ensuring robust gate drive for high-
current applications. The UGATE floating high-side MOSFET
ILIM (VAL) = I I drivers are powered by diode-capacitor charge pumps at
LOAD - 2 BOOT. The LGATE synchronous-rectifier drivers are powered
by PVCC.
TIME
FIGURE 73. “VALLEY” CURRENT LIMIT THRESHOLD POINT
For lower power dissipation, the ISL6236 uses the

ON-resistance of the synchronous rectifier as the
FN6373 Rev 6.00 Page 27 of 36

April 29, 2010
ISL6236
where:
5V
5V • PVCC is 5V
BOOT
10
10 • CGS is the gate capacitance of the high-side MOSFET
VIN
UGATE
Boost-Supply Refresh Monitor
Q1
In pure skip mode, the converter frequency can be very low
C BOOT with little to no output loading. This produces very long off
OUT
times, where leakage can bleed down the BOOT capacitor
PHASE voltage. If the voltage falls too low, the converter may not be
ISL88732 able to turn on UGATE when the output voltage falls to the
ISL88733
ISL6236
ISL6236 reference. To prevent this, the ISL6236 monitors the BOOT
ISL88734
capacitor voltage, and if it falls below 3V, it initiates an LGATE
FIGURE 75. REDUCING THE SWITCHING-NODE RISE TIME pulse, which will refresh the BOOT voltage.
The internal pull-down transistors that drive LGATE low have a POR, UVLO and Internal Digital Soft-Start
0.6 typical ON-resistance. These low ON-resistance
Power-on reset (POR) occurs when VIN rises above
pull-down transistors prevent LGATE from being pulled up
approximately 3V, resetting the undervoltage, overvoltage, and
during the fast rise time of the inductor nodes due to capacitive
thermal-shutdown fault latches. PVCC undervoltage-lockout
coupling from the drain to the gate of the low-side
(UVLO) circuitry inhibits switching when PVCC is below 4V.
synchronous-rectifier MOSFETs. However, for high-current
LGATE is low during UVLO. The output voltages begin to ramp
applications, some combinations of high- and low-side
up once PVCC exceeds its 4V UVLO and REF is in regulation.
MOSFETs may cause excessive gate-drain coupling, which
The internal digital soft-start timer begins to ramp up the
leads to poor efficiency and EMI-producing shoot-through
maximum-allowed current limit during start-up. The 1.7ms
currents. Adding a 1 resistor in series with BOOT increases
ramp occurs in five steps. The step size are 20%, 40%, 60%,
the turn-on time of the high-side MOSFETs at the expense of
80% and 100% of the positive current limit value.
efficiency, without degrading the turn-off time (Figure 75).
Adaptive dead-time circuits monitor the LGATE and UGATE Power-Good Output (POK)
drivers and prevent either FET from turning on until the other is The POK comparator continuously monitors both output
fully off. This algorithm allows operation without shoot-through voltages for undervoltage conditions. POK is actively held low
with a wide range of MOSFETs, minimizing delays and in shutdown, standby, and soft-start. POK1 releases and digital
maintaining efficiency. There must be low resistance, low soft-start terminates when VOUT1 outputs reach the error-
inductance paths from the gate drivers to the MOSFET gates for comparator threshold. POK1 goes low if VOUT1 output turns off
the adaptive dead-time circuit to work properly. Otherwise, the or is 10% below its nominal regulation point. POK1 is a true
sense circuitry interprets the MOSFET gate as "off" when there is open-drain output. Likewise, POK2 is used to monitor VOUT2.
actually charge left on the gate. Use very short, wide traces
measuring 10 to 20 squares (50 mils to 100 mils wide if the Fault Protection
MOSFET is 1” from the device). The ISL6236 provides overvoltage/undervoltage fault
protection in the buck controllers. Once activated, the
Boost-Supply Capacitor Selection (Buck) controller continuously monitors the output for undervoltage
The boost capacitor should be 0.1µF to 4.7µF, depending on and overvoltage fault conditions.
the input and output voltages, external components, and PC OUT-OF-BOUND CONDITION
board layout. The boost capacitance should be as large as
When the output voltage is 5% above the set voltage, the out-
possible to prevent it from charging to excessive voltage, but
of-bound condition activates. LGATE turns on until output
small enough to adequately charge during the minimum
reaches within regulation. Once the output is within regulation,
low-side MOSFET conduction time, which happens at
the controller will operate as normal. It is the "first line of
maximum operating duty cycle (this occurs at minimum input
defense" before OVP. The output voltage ripple must be sized
voltage). The minimum gate to source voltage (VGS(MIN)) is
low enough as to not nuisance trip the OOB threshold. The
determined by:
equations in “Output Capacitor Selection” on page 31 should
C BOOT
V GS  MIN  = PVCC  --------------------------------------- (EQ. 5) be used to size the output voltage ripple below 3% of the
C BOOT + C GS
nominal output voltage set point.
OVERVOLTAGE PROTECTION
When the output voltage of VOUT1 is 11% (16% for VOUT2)
above the set voltage, the overvoltage fault protection
FN6373 Rev 6.00 Page 28 of 36

April 29, 2010
ISL6236
activates. This latches on the synchronous rectifier MOSFET thermal shutdown. Cycling EN, EN LDO, or VIN (POR) ends
with 100% duty cycle, rapidly discharging the output capacitor the thermal-shutdown state.
until the negative current limit is achieved. Once negative
Discharge Mode (Soft-Stop)
current limit is met, UGATE is turned on for a minimum ON-
time, followed by another LGATE pulse until negative current When a transition to standby or shutdown mode occurs, or the
limit. This effectively regulates the discharge current at the output undervoltage fault latch is set, the outputs discharge to
negative current limit in an effort to prevent excessively large GND through an internal 25 switch. The reference remains
negative currents that cause potentially damaging negative active to provide an accurate threshold and to provide
voltages on the load. Once an overvoltage fault condition is overvoltage protection.
set, it can only be reset by toggling SHDN, EN, or cycling VIN Shutdown Mode
(POR).
The ISL6236 SMPS1, SMPS2 and LDO have independent
UNDERVOLTAGE PROTECTION enabling control. Drive EN1, EN2 and EN LDO below the
When the output voltage drops below 70% of its regulation precise input falling-edge trip level to place the ISL6236 in its
voltage for at least 100µs, the controller sets the fault latch and low-power shutdown state. The ISL6236 consumes only 20µA
begins the discharge mode (see “Shutdown Mode” on page 29 of quiescent current while in shutdown. When shutdown mode
and “Discharge Mode (Soft-Stop)” on page 29). UVP is ignored activates, the 3.3V VREF3 remain on. Both SMPS outputs are
for at least 20ms (typical), after start-up or after a rising edge discharged to 0V through a 25 switch.
on EN. Toggle EN or cycle VIN (POR) to clear the undervoltage Power-Up Sequencing and On/Off Controls (EN)
fault latch and restart the controller. UVP only applies to the
EN1 and EN2 control SMPS power-up sequencing. EN1 or
buck outputs.
EN2 rising above 2.4V enables the respective outputs. EN1 or
THERMAL PROTECTION EN2 falling below 1.6V disables the respective outputs.
The ISL6236 has thermal shutdown to protect the devices from Connecting EN1 or EN2 to REF will force its outputs off while
overheating. Thermal shutdown occurs when the die the other output is below regulation. The sequenced SMPS will
temperature exceeds +150°C. All internal circuitry shuts down start once the other SMPS reaches regulation. The second
during thermal shutdown. The ISL6236 may trigger thermal SMPS remains on until the first SMPS turns off, the device
shutdown if LDO is not bootstrapped from OUT while applying shuts down, a fault occurs or PVCC goes into undervoltage
a high input voltage on VIN and drawing the maximum current lockout. Both supplies begin their power-down sequence
(including short circuit) from LDO. Even if LDO is bootstrapped immediately when the first supply turns off. Driving EN below
from OUT, overloading the LDO causes large power 0.8V clears the overvoltage, undervoltage and thermal fault
dissipation on the bootstrap switches, which may result in latches.
TABLE 3. OPERATING-MODE TRUTH TABLE
MODE CONDITION COMMENT

Power-Up PVCC < UVLO threshold. Transitions to discharge mode after a VIN POR and after REF becomes valid. LDO,
VREF3, and REF remain active.
Run EN LDO = high, EN1 or EN2 Normal operation

enabled.
Overvoltage Either output > 111% (VOUT1) or LGATE is forced high. LDO, VREF3 and REF active. Exited by a VIN POR, or by
Protection 116% (VOUT2) of nominal level. toggling EN1 or EN2.
Undervoltage Either output < 70% of nominal after The internal 25 switch turns on. LDO, VREF3 and REF are active. Exited by a VIN
Protection 20ms time-out expires and output is POR or by toggling EN1 or EN2.
enabled.
Discharge Either SMPS output is still high in Discharge switch (25) connects OUT to GND. One output may still run while the
either standby mode or shutdown other is in discharge mode. Activates when PVCC is in UVLO, or transition to UVLO,
mode standby, or shutdown has begun. LDO, VREF3 and REF active.
Standby EN1, EN2 < startup threshold, EN LDO, VREF3 and REF active.
LDO = High
Shutdown EN1, EN2, EN LDO = low Discharge switch (25) connects OUT to PGND. All circuitry off except VREF3.
Thermal Shutdown TJ > +150°C All circuitry off. Exited by VIN POR or cycling EN. VREF3 remain active.
FN6373 Rev 6.00 Page 29 of 36

April 29, 2010
ISL6236
TABLE 4. SHUTDOWN AND STANDBY CONTROL LOGIS
VEN LDO VEN1 (V) VEN2 (V) LDO SMPS1 SMPS2

Low Low Low Off Off Off
“>2.5”  High Low Low On Off Off
“>2.5”  High High High On On On
“>2.5”  High High Low On On Off
“>2.5”  High Low High On Off On
“>2.5”  High High REF On On On (after SMPS1 is up)
“>2.5”  High REF High On On (after SMPS2 is up) On
Adjustable-Output Feedback (Dual-Mode FB) the selection of input capacitors, MOSFETs and other
Connect FB1 to GND to enable the fixed 5V or tie FB1 to VCC critical heat-contributing components.
to set the fixed 1.5V output. Connect a resistive voltage-divider 3. Switching Frequency. This choice determines the basic
at FB1 between OUT1 and GND to adjust the respective trade-off between size and efficiency. The optimal
output voltage between 0.7V and 5.5V (Figure 76). Choose R2 frequency is largely a function of maximum input voltage
and MOSFET switching losses.
to be approximately 10k and solve for R1 using Equation 6.
4. Inductor Ripple Current Ratio (LIR). LIR is the ratio of the
 V OUT1  peak-peak ripple current to the average inductor current.
R 1 = R 2   ------------------- – 1
 V FB1  Size and efficiency trade-offs must be considered when
(EQ. 6)
setting the inductor ripple current ratio. Low inductor values
where VFB1 = 0.7V nominal. cause large ripple currents, resulting in the smallest size,
but poor efficiency and high output noise. Also, total output
Likewise, connect REFIN2 to VCC to enable the fixed 3.3V or ripple above 3.5% of the output regulation will cause the
tie REFIN2 to VREF3 to set the fixed 1.05V output. Set controller to trigger out-of-bound condition. The minimum
REFIN2 from 0V to 2.50V for SMPS2 tracking mode practical inductor value is one that causes the circuit to
(Figure 77). operate at critical conduction (where the inductor current
VR just touches zero with every cycle at maximum load).
R 3 = R 4   ------------------- – 1 Inductor values lower than this grant no further size-
V 
OUT2 (EQ. 7) reduction benefit.
where: The ISL6236 pulse-skipping algorithm (SKIP = GND)
initiates skip mode at the critical conduction point, so the
• VR = 2V nominal (if tied to REF) inductor's operating point also determines the load current
or at which PWM/PFM switchover occurs. The optimum LIR
point is usually found between 25% and 50% ripple
• VR = 3.3V nominal (if tied to VREF3) current.
Design Procedure VIN

Establish the input voltage range and maximum load current
before choosing an inductor and its associated ripple current UGATE1 Q3
ratio (LIR). The following four factors dictate the rest of the
design: OUT1
1. Input Voltage Range. The maximum value (VIN(MAX)) ISL6236

must accommodate the maximum AC adapter voltage. The
LGATE1 Q4
minimum value (VIN(MIN)) must account for the lowest input
voltage after drops due to connectors, fuses and battery
selector switches. Lower input voltages result in better
efficiency. OUT1 R1
2. Maximum Load Current. The peak load current FB1

(ILOAD(MAX)) determines the instantaneous component
stress and filtering requirements and thus drives output R2
capacitor selection, inductor saturation rating and the
design of the current-limit circuit. The continuous load
current (ILOAD) determines the thermal stress and drives
FIGURE 76. SETTING VOUT1 WITH A RESISTOR DIVIDER
FN6373 Rev 6.00 Page 30 of 36

April 29, 2010
ISL6236
VIN Determining the Current Limit

The minimum current-limit threshold must be great enough to
Q1
support the maximum load current when the current limit is at
UGATE2
UGATE
UGATE2 the minimum tolerance value. The valley of the inductor current
ISL88732 occurs at ILOAD(MAX) minus half of the ripple current;
OUT2 therefore:
ISL6236
ISL88733
ISL88734
I LIMIT  LOW   I LOAD  MAX  –   LIR  2   I LOAD  MAX   (EQ. 12)
LGATE
LGATE2
LGATE2 Q2
where: ILIMIT(LOW) = minimum current-limit threshold voltage
divided by the rDS(ON) of Q2/Q4.
VOUT
OUT2
OUT2
Use the worst-case maximum value for rDS(ON) from the
FB
REFIN2
REFIN2 VR MOSFET Q2/Q4 data sheet and add some margin for the rise
R3 in rDS(ON) with temperature. A good general rule is to allow
R4 0.2% additional resistance for each °C of temperature rise.
Examining the 5A circuit example with a maximum

rDS(ON) = 5m at room temperature. At +125°C reveals the
FIGURE 77. SETTING VOUT2 WITH A VOLTAGE DIVIDER FOR following:
TRACKING
I LIMIT  LOW  =  25mV     5m  1.2   5A –  0.35  2 5A 
Inductor Selection
The switching frequency (ON-time) and operating point (% ripple (EQ. 13)
or LIR) determine the inductor value as follows:
4.17A  4.12A (EQ. 14)
V OUT_  V IN + V OUT_ 
L = --------------------------------------------------------------------- (EQ. 8)
V IN  f  LIR  I LOAD  MAX 
4.17A is greater than the valley current of 4.12A, so the circuit
can easily deliver the full-rated 5A using the 30mV nominal
Example: ILOAD(MAX) = 5A, VIN = 12V, VOUT2 = 5V,
current-limit threshold voltage.
f = 200kHz, 35% ripple current or LIR = 0.35:
Output Capacitor Selection
5V  12V – 5V  (EQ. 9)
L = ----------------------------------------------------------------- = 8.3H The output filter capacitor must have low enough equivalent
12V  200kHz  0.35  5A
series resistance (ESR) to meet output ripple and
Find a low-loss inductor having the lowest possible DC load-transient requirements, yet have high enough ESR to
resistance that fits in the allotted dimensions. Ferrite cores are satisfy stability requirements. The output capacitance must
often the best choice. The core must be large enough not to also be high enough to absorb the inductor energy while
saturate at the peak inductor current (IPEAK): transitioning from full-load to no-load conditions without
tripping the overvoltage fault latch. In applications where the
IPEAK = I LOAD  MAX  +   LIR  2   I LOAD  MAX   (EQ. 10)
output is subject to large load transients, the output capacitor's
size depends on how much ESR is needed to prevent the
The inductor ripple current also impacts transient response
output from dipping too low under a load transient. Ignoring the
performance, especially at low VIN - VOUT differences. Low
sag due to finite capacitance:
inductor values allow the inductor current to slew faster,
V DIP
replenishing charge removed from the output filter capacitors R SER  ---------------------------------- (EQ. 15)
I LOAD  MAX 
by a sudden load step. The peak amplitude of the output
transient (VSAG) is also a function of the maximum duty factor,
where VDIP is the maximum-tolerable transient voltage drop. In
which can be calculated from the ON-time and minimum OFF-
non-CPU applications, the output capacitor's size depends on
time:
how much ESR is needed to maintain an acceptable level of
2   V OUT_ 
 I LOAD  MAX    L  K  ------------------- + t OFF  MIN   output voltage ripple:
  V IN 
VSAG = ---------------------------------------------------------------------------------------------------------------------------- VP – P
 V IN – V OUT R ESR  ----------------------------------------------- (EQ. 16)
2  C OUT  V OUT K  -------------------------------- - t L IR  I LOAD  MAX 
 V IN  OFF  MIN 
(EQ. 11) where VP-P is the peak-to-peak output voltage ripple. The
actual capacitance value required relates to the physical size
where minimum OFF-time = 0.35µs (max) and K is from needed to achieve low ESR, as well as to the chemistry of the
Table 2. capacitor technology. Thus, the capacitor is usually selected by
ESR and voltage rating rather than by capacitance value (this
FN6373 Rev 6.00 Page 31 of 36

April 29, 2010
ISL6236
is true of tantalum, OS-CON, and other electrolytic-type maximum input voltage do not exceed the package ratings or
capacitors). violate the overall thermal budget.
When using low-capacity filter capacitors such as polymer Choose a synchronous rectifier (Q2/Q4) with the lowest
types, capacitor size is usually determined by the capacity possible rDS(ON). Ensure the gate is not pulled up by the high-
required to prevent VSAG and VSOAR from tripping the side switch turning on due to parasitic drain-to-gate
undervoltage and overvoltage fault latches during load capacitance, causing cross-conduction problems. Switching
transients in ultrasonic mode. losses are not an issue for the synchronous rectifier in the buck
topology since it is a zero-voltage switched device when using
For low input-to-output voltage differentials (VIN/VOUT < 2),
the buck topology.
additional output capacitance is required to maintain stability and
good efficiency in ultrasonic mode. The amount of overshoot MOSFET Power Dissipation
due to stored inductor energy can be calculated as: Worst-case conduction losses occur at the duty-factor
2
I PEAK  L extremes. For the high-side MOSFET, the worst-case power
V SOAR = ------------------------------------------------ (EQ. 17)
2  C OUT  V OUT_ dissipation (PD) due to the MOSFET's rDS(ON) occurs at the
minimum battery voltage:
where IPEAK is the peak inductor current.  V OUT_  2
PD  Q H Resistance  =  ------------------------  I LOAD   r DS  ON 
Input Capacitor Selection  V IN  MIN 
(EQ. 19)
The input capacitors must meet the input-ripple-current (IRMS)
requirement imposed by the switching current. The ISL6236 Generally, a small high-side MOSFET reduces switching
dual switching regulator operates at different frequencies. This losses at high input voltage. However, the rDS(ON) required to
interleaves the current pulses drawn by the two switches and stay within package power-dissipation limits often limits how
reduces the overlap time where they add together. The input small the MOSFET can be. The optimum situation occurs
RMS current is much smaller in comparison than with both when the switching (AC) losses equal the conduction (rDS(ON))
SMPSs operating in phase. The input RMS current varies with losses.
load and the input voltage. Switching losses in the high-side MOSFET can become an
The maximum input capacitor RMS current for a single SMPS insidious heat problem when maximum battery voltage is
is given by: applied, due to the squared term in the CV2f switching-loss
equation. Reconsider the high-side MOSFET chosen for
 V OUT  V IN – V OUT_  adequate rDS(ON) at low battery voltages if it becomes
I RMS  I LOAD  ------------------------------------------------------------ (EQ. 18)
 V IN  extraordinarily hot when subjected to VIN(MAX).
When V IN = 2  V OUT_  D = 50%  , IRMS has maximum current Calculating the power dissipation in NH (Q1/Q3) due to
of I LOAD  2 . switching losses is difficult since it must allow for quantifying
factors that influence the turn-on and turn-off times. These
The ESR of the input-capacitor is important for determining factors include the internal gate resistance, gate charge,
capacitor power dissipation. All the power (IRMS2 x ESR) heats threshold voltage, source inductance, and PC board layout
up the capacitor and reduces efficiency. Nontantalum characteristics. The following switching-loss calculation
chemistries (ceramic or OS-CON) are preferred due to their provides only a very rough estimate and is no substitute for
low ESR and resilience to power-up surge currents. Choose bench evaluation, preferably including verification using a
input capacitors that exhibit less than +10°C temperature rise thermocouple mounted on NH (Q1/Q3):
at the RMS input current for optimal circuit longevity. Place the
drains of the high-side switches close to each other to share 2  C RSS  f SW  I LOAD
PD  Q H Switching  =  V IN  MAX    -----------------------------------------------------
common input bypass capacitors.  I GATE 
(EQ. 20)
Power MOSFET Selection
Most of the following MOSFET guidelines focus on the where CRSS is the reverse transfer capacitance of QH (Q1/Q3)
challenge of obtaining high load-current capability (>5A) when and IGATE is the peak gate-drive source/sink current.
using high-voltage (>20V) AC adapters. Low-current For the synchronous rectifier, the worst-case power dissipation
applications usually require less attention. always occurs at maximum battery voltage:
Choose a high-side MOSFET (Q1/Q3) that has conduction  V OUT  2
PD  Q L  =  1 – -------------------------- I LOAD  r DS  ON  (EQ. 21)
losses equal to the switching losses at the typical battery  V IN  MAX 
voltage for maximum efficiency. Ensure that the conduction
losses at the minimum input voltage do not exceed the The absolute worst case for MOSFET power dissipation
package thermal limits or violate the overall thermal budget. occurs under heavy overloads that are greater than
Ensure that conduction losses plus switching losses at the ILOAD(MAX) but are not quite high enough to exceed the
FN6373 Rev 6.00 Page 32 of 36

April 29, 2010
ISL6236
current limit and cause the fault latch to trip. To protect against absolute minimum dropout point, the inductor current is less
this possibility, "overdesign" the circuit to tolerate: able to increase during each switching cycle and VSAG greatly
increases unless additional output capacitance is used.
I LOAD = I LIMIT  HIGH  +   LIR   2   I LOAD  MAX  (EQ. 22)
A reasonable minimum value for h is 1.5, but this can be
where ILIMIT(HIGH) is the maximum valley current allowed by adjusted up or down to allow trade-offs between VSAG, output
the current-limit circuit, including threshold tolerance and capacitance and minimum operating voltage. For a given value
resistance variation. of h, the minimum operating voltage can be calculated as:
Rectifier Selection  V OUT_ + V DROP 

V IN  MIN  = --------------------------------------------------- + V DROP2 – V DROP1 (EQ. 23)
t OFF  MIN   h
Current circulates from ground to the junction of both MOSFETs 1 –  ------------------------------------
 K 
and the inductor when the high-side switch is off. As a
consequence, the polarity of the switching node is negative with where VDROP1 and VDROP2 are the parasitic voltage drops in
respect to ground. This voltage is approximately -0.7V (a diode the discharge and charge paths (see “ON-TIME ONE-SHOT
drop) at both transition edges while both switches are off (dead (tON)” on page 20), tOFF(MIN) is from the “Electrical
time). The drop is IL x rDS(ON) when the low-side switch Specifications” table, which starts on page 3 and K is taken from
conducts. Table 2. The absolute minimum input voltage is calculated with
The rectifier is a clamp across the synchronous rectifier that h = 1.
catches the negative inductor swing during the dead time Operating frequency must be reduced or h must be increased
between turning the high-side MOSFET off and the and output capacitance added to obtain an acceptable VSAG if
synchronous rectifier on. The MOSFETs incorporate a calculated VIN(MIN) is greater than the required minimum input
high-speed silicon body diode as an adequate clamp diode if voltage. Calculate VSAG to be sure of adequate transient
efficiency is not of primary importance. Place a Schottky diode response if operation near dropout is anticipated.
in parallel with the body diode to reduce the forward voltage
drop and prevent the Q2/Q4 MOSFET body diodes from DROPOUT DESIGN EXAMPLE
turning on during the dead time. Typically, the external diode ISL6236: With VOUT2 = 5V, fSW = 400kHz, K = 2.25µs,
improves the efficiency by 1% to 2%. Use a Schottky diode tOFF(MIN) = 350ns, VDROP1 = VDROP2 = 100mV, and h = 1.5,
with a DC current rating equal to one-third of the load current. the minimum VIN is:
For example, use an MBR0530 (500mA-rated) type for loads
up to 1.5A, a 1N5817 type for loads up to 3A, or a 1N5821 type  5V + 0.1V  (EQ. 24)
V IN  MIN  = ---------------------------------------------- + 0.1V – 0.1V = 6.65V
0.35s  1.5
for loads up to 10A. The rectifier's rated reverse breakdown 1 –  -------------------------------
 2.25s 
voltage must be at least equal to the maximum input voltage,
preferably with a 20% derating factor.
Calculating with h = 1 yields:
Applications Information  5V + 0.1V 
V IN  MIN  = ----------------------------------------- + 0.1V – 0.1V = 6.04V (EQ. 25)
0.35s  1
Dropout Performance 1 –  --------------------------
 2.25s 
The output voltage-adjust range for continuous-conduction
operation is restricted by the nonadjustable 350ns (max) Therefore, VIN must be greater than 6.65V. A practical input
minimum OFF-time one-shot. Use the slower 5V SMPS for the voltage with reasonable output capacitance would be 7.5V.
higher of the two output voltages for best dropout performance
PC Board Layout Guidelines
in adjustable feedback mode. The duty-factor limit must be
Careful PC board layout is critical to achieve minimal switching
calculated using worst-case values for on - and OFF-times,
losses and clean, stable operation. This is especially true when
when working with low input voltages. Manufacturing
multiple converters are on the same PC board where one circuit
tolerances and internal propagation delays introduce an error
can affect the other. Refer to the ISL6236 Evaluation Kit
to the tON K-factor. Also, keep in mind that transient-response
Application Notes (AN1271 and AN1272) for a specific layout
performance of buck regulators operated close to dropout is
example.
poor, and bulk output capacitance must often be added (see
Equation 11 on page 31). Mount all of the power components on the top side of the board
with their ground terminals flush against one another, if possible.
The absolute point of dropout occurs when the inductor current
Follow these guidelines for good PC board layout:
ramps down during the minimum OFF-time (IDOWN) as much
as it ramps up during the ON-time • Isolate the power components on the top side from the
sensitive analog components on the bottom side with a
( IUP). The ratio h = IUP/IDOWN indicates the ability to slew
ground shield. Use a separate PGND plane under the OUT1
the inductor current higher in response to increased load, and and OUT2 sides (called PGND1 and PGND2). Avoid the
must always be greater than 1. As h approaches 1, the introduction of AC currents into the PGND1 and PGND2
FN6373 Rev 6.00 Page 33 of 36

April 29, 2010
ISL6236
ground planes. Run the power plane ground currents on the

top side only, if possible.
• Use a star ground connection on the power plane to
minimize the crosstalk between OUT1 and OUT2.
• Keep the high-current paths short, especially at the ground
terminals. This practice is essential for stable, jitter-free
operation.
• Keep the power traces and load connections short. This
practice is essential for high efficiency. Using thick copper
PC boards (2oz vs 1oz) can enhance full-load efficiency by
1% or more. Correctly routing PC board traces must be
approached in terms of fractions of centimeters, where a
single mof excess trace resistance causes a measurable
efficiency penalty.
• PHASE (ISL6236) and GND connections to the synchronous
rectifiers for current limiting must be made using Kelvin-
sense connections to guarantee the current-limit accuracy
with 8 Ld SO MOSFETs. This is best done by routing power
to the MOSFETs from outside using the top copper layer,
while connecting PHASE traces inside (underneath) the
MOSFETs.
• When trade-offs in trace lengths must be made, it is
preferable to allow the inductor charging path to be made
longer than the discharge path. For example, it is better to
allow some extra distance between the input capacitors and
the high-side MOSFET than to allow distance between the
inductor and the synchronous rectifier or between the
inductor and the output filter capacitor.
• Ensure that the OUT connection to COUT is short and direct.
However, in some cases it may be desirable to deliberately
introduce some trace length between the OUT connector
node and the output filter capacitor.
• Route high-speed switching nodes (BOOT, UGATE, PHASE,
and LGATE) away from sensitive analog areas (REF, ILIM,
and FB). Use PGND1 and PGND2 as an EMI shield to keep
radiated switching noise away from the IC's feedback divider
and analog bypass capacitors.
• Make all pin-strap control input connections (SKIP, ILIM,
etc.) to GND or VCC of the device.
FN6373 Rev 6.00 Page 34 of 36

April 29, 2010
ISL6236
Layout Procedure On the board's top side (power planes), make a star ground to
Place the power components first with ground terminals minimize crosstalk between the two sides. The top-side star
adjacent (Q2/Q4 source, CIN, COUT). If possible, make all ground is a star connection of the input capacitors and
these connections on the top layer with wide, copper-filled synchronous rectifiers. Keep the resistance low between the
areas. star ground and the source of the synchronous rectifiers for
accurate current limit. Connect the top-side star ground (used
Mount the controller IC adjacent to the synchronous rectifier for MOSFET, input, and output capacitors) to the small island
MOSFETs close to the hottest spot, preferably on the back side with a single short, wide connection (preferably just a via).
in order to keep UGATE, GND, and the LGATE gate drive lines Create PGND islands on the layer just below the topside layer
short and wide. The LGATE gate trace must be short and wide, (refer to the ISL6236 Evaluation Kit Application Notes, AN1271
measuring 50 mils to 100 mils wide if the MOSFET is 1” from and AN1272) to act as an EMI shield if multiple layers are
the controller device. available (highly recommended). Connect each of these
Group the gate-drive components (BOOT capacitor, VIN individually to the star ground via, which connects the top side
bypass capacitor) together near the controller device. to the PGND plane. Add one more solid ground plane under
the device to act as an additional shield, and also connect the
Make the DC/DC controller ground connections as follows: solid ground plane to the star ground via.
1. Near the device, create a small analog ground plane. Connect the output power planes (VCORE and system ground
2. Connect the small analog ground plane to GND and use the planes) directly to the output filter capacitor positive and
plane for the ground connection for the REF and VCC negative terminals with multiple vias.
bypass capacitors, FB dividers and ILIM resistors (if any).
3. Create another small ground island for PGND and use the
plane for the VIN bypass capacitor, placed very close to the
device.
4. Connect the GND and PGND planes together at the metal
tab under device.
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For additional products, see www.intersil.com/en/products.html

Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
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otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6373 Rev 6.00 Page 35 of 36

April 29, 2010
ISL6236
Package Outline Drawing

L32.5x5B
32 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 11/07
4X 3.5
5.00 A 28X 0.50
6
B
25 32 PIN #1 INDEX AREA
6
PIN 1 24 1
INDEX AREA
5.00
3 .30 ± 0 . 15
17 8
(4X) 0.15
16 9
0.10 M C A B
+ 0.07
32X 0.40 ± 0.10 4 32X 0.23 - 0.05
TOP VIEW BOTTOM VIEW
SEE DETAIL "X"
0.10 C
0 . 90 ± 0.1 C
BASE PLANE
SEATING PLANE
0.08 C
( 4. 80 TYP )
( 28X 0 . 5 )
SIDE VIEW
( 3. 30 )
(32X 0 . 23 )
C 0 . 2 REF 5
( 32X 0 . 60)
0 . 00 MIN.
0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"
NOTES:
1. Dimensions are in millimeters.

Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured

between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be

located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
FN6373 Rev 6.00 Page 36 of 36

April 29, 2010

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DATASHEET

The ISL6236 dual step-down, switch-mode power-supply Features

FN6373 Rev 6.00 Page 1 of 36

FN6373 Rev 6.00 Page 2 of 36

Absolute Voltage Ratings Thermal Information

FN6373 Rev 6.00 Page 3 of 36

INTERNAL REGULATOR AND REFERENCE

FN6373 Rev 6.00 Page 4 of 36

FN6373 Rev 6.00 Page 5 of 36

FN6373 Rev 6.00 Page 6 of 36

FN6373 Rev 6.00 Page 7 of 36

Pin Descriptions (Continued)

7VIN SKIP MODE 12VIN ULTRA SKIP MODE

FN6373 Rev 6.00 Page 8 of 36

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

FN6373 Rev 6.00 Page 9 of 36

POWER DISSIPATION (W)

OUTPUT VOLTAGE (V)

1.054 MID LOAD PWM 1.056

FN6373 Rev 6.00 Page 10 of 36

OUTPUT VOLTAGE (V)

OUTPUT VOLTAGE (V)

3.325 3.34 MAX LOAD PWM

OUTPUT VOLTAGE (V)

MAX LOAD PWM 5.10

FN6373 Rev 6.00 Page 11 of 36

FN6373 Rev 6.00 Page 12 of 36

OUTPUT VOLTAGE (V)

4.90 BYP = 3.3V

OUTPUT VOLTAGE (V)

FN6373 Rev 6.00 Page 13 of 36

INPUT CURRENT (µA)

INPUT CURRENT (µA)

REF 1V/DIV IL1 2A/DIV

FN6373 Rev 6.00 Page 14 of 36

EN1 5V/DIV EN1 5V/DIV

VOUT1 2V/DIV VOUT1 2V/DIV

IL1 2A/DIV IL1 5A/DIV

POK1 2V/DIV POK1 2V/DIV

EN2 5V/DIV EN2 5V/DIV

VOUT2 2V/DIV VOUT2 2V/DIV

VOUT2 2V/DIV VOUT1 2V/DIV

IL2 5A/DIV POK2 5V/DIV

POK2 2V/DIV POK1 5V/DIV

FN6373 Rev 6.00 Page 15 of 36

VOUT1 2V/DIV VOUT2 2V/DIV

POK1 5V/DIV VOUT1 2V/DIV

POK2 5V/DIV POK1 OR POK2 5V/DIV

LGATE1 5V/DIV LGATE1 5V/DIV

VOUT1 RIPPLE 50mV/DIV

VOUT1 RIPPLE 100mV/DIV

IL1 5A/DIV IL1 5A/DIV

VOUT2 RIPPLE 50mV/DIV VOUT2 RIPPLE 50mV/DIV

LGATE1 5V/DIV LGATE2 5V/DIV

VOUT1 RIPPLE 20mV/DIV

VOUT1 RIPPLE 20mV/DIV

IL2 5A/DIV VOUT2 RIPPLE 50mV/DIV

VOUT2 RIPPLE 50mV/DIV