TPS54627

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4.5V to 18V Input, 6-A Synchronous Step-Down Converter

Check for Samples: TPS54627

1FEATURES DESCRIPTION
23 • D-CAP2™ Mode Enables Fast Transient The TPS54627 is an adaptive on-time D-CAP2™
Response mode synchronous buck converter. The TPS54627
enables system designers to complete the suite of
• Low Output Ripple and Allows Ceramic Output various end-equipment power bus regulators with a
Capacitor cost effective, low component count, low standby
• Wide VIN Input Voltage Range: 4.5 V to 18 V current solution. The main control loop for the
• Output Voltage Range: 0.76 V to 5.5 V TPS54627 uses the D-CAP2™ mode control that
provides a fast transient response with no external
• Highly Efficient Integrated FETs Optimized compensation components. The TPS54627 also has
for Lower Duty Cycle Applications a proprietary circuit that enables the device to adopt
– 36 mΩ (High Side) and 28 mΩ (Low Side) to both low equivalent series resistance (ESR) output
• High Efficiency, less than 10 μA at shutdown capacitors, such as POSCAP or SP-CAP, and ultra-
low ESR ceramic capacitors. The device operates
• High Initial Bandgap Reference Accuracy
from 4.5-V to 18-V VIN input. The output voltage can
• Adjustable Soft Start be programmed between 0.76 V and 5.5 V. The
• Pre-Biased Soft Start device also features an adjustable soft start time. The
• 650-kHz Switching Frequency (fSW) TPS54627 is available in the 8-pin DDA package,
and designed to operate from –40°C to 85°C.
• Cycle By Cycle Over Current Limit
• Auto-Skip Eco-mode™ for High Efficiency at
Light Load

APPLICATIONS
• Wide Range of Applications for Low Voltage
System
– Digital TV Power Supply
– High Definition Blu-ray Disc™ Players
– Networking Home Terminal
– Digital Set Top Box (STB)

Vout(50mV/div)
TPS54627

Iout(2A/div)

100us/div

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 D-CAP2, Eco-mode are trademarks of Texas Instruments.
3 Blu-ray Disc is a trademark of Blu-ray Disc Association.
PRODUCTION DATA information is current as of publication date. Copyright © 2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION (1)

TRANSPORT
TA PACKAGE (2) (3)
ORDERABLE PART NUMBER PIN
MEDIA
TPS54627DDA Tube
–40°C to 85°C DDA 8
TPS54627DDAR Tape and Reel

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) All package options have Cu NIPDAU lead/ball finish.

ABSOLUTE MAXIMUM RATINGS

(1)
over operating free-air temperature range (unless otherwise noted)
VALUE
UNIT
MIN MAX
VIN, EN –0.3 20
VBST –0.3 26
VBST (10 ns transient) –0.3 28
Input voltage range VBST (vs SW) –0.3 6.5 V
VFB, SS –0.3 6.5
SW –2 20
SW (10 ns transient) –3 22
VREG5 –0.3 6.5
Output voltage range V
GND –0.3 0.3
Voltage from GND to thermal pad, Vdiff –0.2 0.2 V
Human Body Model (HBM) 2 kV
Electrostatic discharge
Charged Device Model (CDM) 500 V
Operating junction temperature, TJ –40 150
°C
Storage temperature, Tstg –55 150

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION
TPS54627
THERMAL METRIC (1) UNITS
DDA (8 PINS)
θJA Junction-to-ambient thermal resistance 43.5
θJCtop Junction-to-case (top) thermal resistance 49.4
θJB Junction-to-board thermal resistance 25.6
°C/W
ψJT Junction-to-top characterization parameter 7.4
ψJB Junction-to-board characterization parameter 25.5
θJCbot Junction-to-case (bottom) thermal resistance 5.2

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

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RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range, (unless otherwise noted)
MIN MAX UNIT
VIN Supply input voltage range 4.5 18 V
VBST –0.1 24
VBST (10 ns transient) –0.1 27
VBST(vs SW) –0.1 6.0
SS –0.1 5.7
VI Input voltage range EN –0.1 18 V
VFB –0.1 5.5
SW –1.8 18
SW (10 ns transient) –3 21
GND –0.1 0.1
VO Output voltage range VREG5 –0.1 5.7 V
IO Output Current range IVREG5 0 5 mA
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature –40 150 °C

ELECTRICAL CHARACTERISTICS
over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
VIN current, TA = 25°C, EN = 5 V,
IVIN Operating - non-switching supply current 950 1400 μA
VFB = 0.8 V
IVINSDN Shutdown supply current VIN current, TA = 25°C, EN = 0 V 3 10 μA
LOGIC THRESHOLD
EN high-level input voltage EN 1.6 V
VEN
EN low-level input voltage EN 0.6 V
REN EN pin resistance to GND VEN = 12 V 200 400 800 kΩ
VFB VOLTAGE AND DISCHARGE RESISTANCE
TA = 25°C, VO = 1.05 V, continuous
757 765 773 mV
mode operation
VFBTH VFB threshold voltage
TA = -40 to 85°C, VO = 1.05 V,
751 765 779 mV
continuous mode operation (1)
IVFB VFB input current VFB = 0.8 V, TA = 25°C 0 ±0.15 μA
VREG5 OUTPUT
TA = 25°C, 6.0 V < VIN < 18 V,
VVREG5 VREG5 output voltage 5.2 5.5 5.7 V
0 < IVREG5 < 5 mA
IVREG5 Output current VIN = 6 V, VREG5 = 4.0 V, TA = 25°C 20 mA
VOUT DISCHARGE
RDISCHG VOUT discharge resistance EN = 0 V, SW = 0.5 V, TA = 25°C 500 800 Ω
MOSFET
High side switch resistance 25°C, VBST - SW = 5.5 V 36 mΩ
RDS(on)
Low side switch resistance 25°C 28 mΩ
CURRENT LIMIT
IOCL Current limit L out = 1.5 μH (1) 6.7 7.3 8.9 A

(1) Not production tested.

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ELECTRICAL CHARACTERISTICS (continued)

over operating free-air temperature range, VIN = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
THERMAL SHUTDOWN
(2)
Shutdown temperature 165
TSDN Thermal shutdown threshold (2)
°C
Hysteresis 35
ON-TIME TIMER CONTROL
tON On time VIN = 12 V, VO = 1.05 V 150 ns
tOFF(MIN) Minimum off time TA = 25°C, VFB = 0.7 V 260 310 ns
SOFT START
SS charge current VSS = 1 V 4.2 6 7.8 μA
ISS
SS discharge current VSS = 0.5 V 1.5 3.3 mA
HICCUP AND OVER-VOLTAGE PROTECTION
VOVP Output OVP threshold OVP Detect (L > H) 125%
VHICCUP Output Hiccup threshold Hiccup detect (H > L) 65%
THICCUPDELAY Output Hiccup delay To hiccup state 250 µsec
THICCUPENDELAY Output Hiccup Enable delay Relative to soft-start time x1.7
UVLO
Wake up VREG5 voltage 3.45 3.75 4.05
UVLO UVLO threshold V
Hysteresis VREG5 voltage 0.13 0.32 0.48

(2) Not production tested.

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DEVICE INFORMATION

DDA PACKAGE
(TOP VIEW)

1 EN VIN 8

EXPOSED
THERMAL PAD
2 VFB VBST 7
TPS54627

DDA

3 VREG5 HSOP8
SW 6

4 SS GND 5

PIN FUNCTIONS
PIN
DESCRIPTION
NAME NO.
EN 1 Enable input control. EN is active high and must be pulled up to enable the device.
VFB 2 Converter feedback input. Connect to output voltage with feedback resistor divider.
5.5 V power supply output. A capacitor (typical 1 µF) should be connected to GND. VREG5 is not active
VREG5 3
when EN is low.
SS 4 Soft-start control. An external capacitor should be connected to GND.
Ground pin. Power ground return for switching circuit. Connect sensitive SS and VFB returns to GND at
GND 5
a single point.
SW 6 Switch node connection between high-side NFET and low-side NFET.
Supply input for the high-side FET gate drive circuit. Connect 0.1µF capacitor between VBST and SW
VBST 7
pins. An internal diode is connected between VREG5 and VBST.
VIN 8 Input voltage supply pin.
Exposed Thermal Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to
Back side
Pad GND.

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FUNCTIONAL BLOCK DIAGRAM

EN EN
1
Logic
VIN

VIN
-35% + 8
HICCUP
-
VREG5
VBST
Control Logic 7
+
OV
+25% -
1 shot
SW VO
6
Ref + XCON
ON
VREG5
SS + PWM Ceramic
Capacitor
VFB
2 -
5
GND

SGND
VREG5
3
+ SW
OCP
- PGND
SS SS VIN
PGND 4 Softstart

HICCUP
VREG5 OV Protection
SGND UVLO Logic
UVLO
TSD

REF Ref

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OVERVIEW
The TPS54627 is a 6-A synchronous step-down (buck) converter with two integrated N-channel MOSFETs. It
operates using D-CAP2™ mode control. The fast transient response of D-CAP2™ control reduces the output
capacitance required to meet a specific level of performance. Proprietary internal circuitry allows the use of low
ESR output capacitors including ceramic and special polymer types.

DETAILED DESCRIPTION

PWM Operation
The main control loop of the TPS54627 is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with
an internal compensation circuit for pseudo-fixed frequency and low external component count configuration with
both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one
shot timer expires. This one shot is set by the converter input voltage, VIN, and the output voltage, VO, to
maintain a pseudo-fixed frequency over the input voltage range, hence it is called adaptive on-time control. The
one-shot timer is reset and the high-side MOSFET is turned on again when the feedback voltage falls below the
reference voltage. An internal ramp is added to reference voltage to simulate output ripple, eliminating the need
for ESR induced output ripple from D-CAP2™ mode control.

PWM Frequency and Adaptive On-Time Control

TPS54627 uses an adaptive on-time control scheme and does not have a dedicated on board oscillator. The
TPS54627 runs with a pseudo-constant frequency of 650 kHz by using the input voltage and output voltage to
set the on-time one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the
output voltage; therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

Soft Start and Pre-Biased Soft Start

The soft start function is adjustable. When the EN pin becomes high, 6μA current begins charging the capacitor
which is connected from the SS pin to GND. Smooth control of the output voltage is maintained during start up.
The equation for the slow start time is shown in Equation 1. VFB voltage is 0.765 V and SS pin source current is
6μA.
C6(nF) ´ VFB ´ 1.1 C6(nF) ´ 0.765 ´ 1.1
t SS (ms) = =
ISS (μA) 6 (1)
The TPS54627 contains a unique circuit to prevent current from being pulled from the output during startup if the
output is pre-biased. When the soft-start commands a voltage higher than the pre-bias level (internal soft start
becomes greater than feedback voltage VFB), the controller slowly activates synchronous rectification by starting
the first low side FET gate driver pulses with a narrow on-time. It then increments that on-time on a cycle-by-
cycle basis until it coincides with the time dictated by (1-D), where D is the duty cycle of the converter. This
scheme prevents the initial sinking of the pre-bias output, and ensure that the out voltage (VO) starts and ramps
up smoothly into regulation and the control loop is given time to transition from pre-biased start-up to normal
mode operation.

Output Discharge Control

TPS54627 discharges the output when EN is low, or the controller is turned off by the UVLO protection. The
internal low-side MOSFET is not turned on for the output discharge operation to avoid the possibility of causing
negative voltage at the output.

Current Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle valley detect control circuit. The
switch current is monitored by measuring the low-side FET switch voltage between the SW pin and GND. This
voltage is proportional to the switch current. To improve accuracy, the voltage sensing is temperature
compensated.

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During the on time of the high-side FET switch, the switch current increases at a linear rate determined by VIN,
VOUT, the on-time and the output inductor value. During the on time of the low-side FET switch, this current
decreases linearly. The average value of the switch current is the load current IOUT. The TPS54627 constantly
monitors the low-side FET switch voltage, which is proportional to the switch current, during the low-side on-time.
If the measured voltage is above the voltage proportional to the current limit, an internal counter is incremented
per each SW cycle and the converter maintains the low-side switch on until the measured voltage is below the
voltage corresponding to the current limit at which time the switching cycle is terminated and a new switching
cycle begins. In subsequent switching cycles, the on-time is set to a fixed value and the current is monitored in
the same manner. If the over current condition exists for 7 consecutive switching cycles, the internal OCL
threshold is set to a lower level, reducing the available output current. When a switching cycle occurs where the
switch current is not above the lower OCL threshold, the counter is reset and the OCL limit is returned to the
higher value.
There are some important considerations for this type of over-current protection. The peak current is the average
load current plus one half of the peak-to-peak inductor current. The valley current is the average load current
minus one half of the peak-to-peak inductor current. Since the valley current is used to detect the over-current
threshold, the load current is higher than the over-current threshold. Also, when the current is being limited, the
output voltage tends to fall. When the VFB voltage becomes lower than 65% of the target voltage, the UVP
comparator detects it. If the under-voltage condition persists for 250 µs, the device will shut down and re-start in
hiccup mode after 7 times the SS period. When the over current condition is removed, the output voltage will
return to the regulated value. This protection is non-latching.

Over Voltage Protection

TPS54627 detects over and under voltage conditions by monitoring the feedback voltage (VFB). This function is
enabled after approximately 1.7 x times the soft start time. When the feedback voltage becomes higher than
125% of the target voltage, the OVP comparator output goes high and both the high-side MOSFET driver and
the low-side MOSFET driver turn off. This function is non-latch operation.

UVLO Protection
Undervoltage lock out protection (UVLO) monitors the voltage of the VREG5 pin. When the VREG5 voltage is lower
than UVLO threshold voltage, the TPS54627 is shut off. This protection is non-latching.

Thermal Shutdown
TPS54627 monitors the temperature of itself. If the temperature exceeds the threshold value (typically 165°C),
the device is shut off. This is non-latch protection.

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TYPICAL CHARACTERISTICS
VIN = 12 V, TA = 25°C (unless otherwise noted).

1,400 10
9

Ivccsdn - Shutdown Current (µA)

1,200
8
ICC - Supply Current (µA)

1,000 7
6
800
5
600
4

400 3
2
200
1
0 0
±50 0 50 100 150 ±50 0 50 100 150
TJ Junction Temperature (ƒC) C001 TJ Junction Temperature (ƒC) C002

Figure 1. SUPPLY CURRENT vs JUNCTION TEMPERATURE Figure 2. SHUTDOWN CURRENT vs

JUNCTION TEMPERATURE

50 1.100
VIN = 18 V

40 VOUT - Output Voltage (V)

EN Input Current (µA)

1.075

30
1.050
20

1.025
10 V IN = 5 V
Vin=5V
V IN = 12 V
Vin=12V
V IN = 18 V
Vin=18V
0 1.000
0 5 10 15 20 0.0 1.0 2.0 3.0 4.0 5.0 6.0
EN Input Voltage (V) C003 IOUT - Output Current (A) C004

Figure 3. EN INPUT CURRENT vs EN INPUT VOLTAGE Figure 4. 1.05-V OUTPUT VOLTAGE vs OUTPUT CURRENT

1.080

1.070 Vout(50mV/div)
VOUT - Output Voltage (V)

1.060

1.050 Iout(2A/div)

1.040

1.030 IIo=0A
OUT = 0 A

IIo=1A
OUT = 1 A
1.020 100us/div
0 5 10 15 20
VIN - Input Voltage (V) C005

Figure 5. 1.05-V OUTPUT VOLTAGE vs INPUT VOLTAGE Figure 6. 1.05-V, LOAD TRANSIENT RESPONSE

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V, TA = 25°C (unless otherwise noted).
100
VIN = 12 V

EN(10V/div) 90

80

Efficiency (%)
VREG5(5V/div) 70

60
Vout(0.5V/div)
Vo=1.8V
50
Vo=3.3V
Vo=5V
40
0.0 1.0 2.0 3.0 4.0 5.0 6.0
IOUT - Output Current (A) C008

Figure 7. START-UP WAVE FORM Figure 8. EFFICIENCY vs OUTPUT CURRENT

900 900
850
IOUT = 1 A 850

fsw - Switching Frequency (kHz)

Switching Frequency (kHz)

800 800
750 750
700 700
650 Vo=1.05V 650
V O = 1.05 V
600 Vo=1.2V
V O = 1.2 V 600
Vo=1.5V
V O = 1.5 V
550 550
Vo=1.8V
V O = 1.8 V
500 V 500 V O = 1.05 V
Vo=1.05V
O = 2.5 V
Vo=2.5V
450 V O = 3.3 V
Vo=3.3V 450 V O = 1.8 V
Vo=1.8V
V O= 5 V
Vo=5V V O = 3.3 V
Vo=3.3V
400 400
0 5 10 15 20 0.0 1.0 2.0 3.0 4.0 5.0 6.0
VIN - Input Voltage (V) C009 IO - Output Current (A) C010

Figure 9. SWITCHING FREQUENCY vs INPUT VOLTAGE Figure 10. SWITCHING FREQUENCY vs OUTPUT CURRENT

0.780
IO = 1 A
0.775

0.770
VFB Voltage (V)

0.765

0.760

0.755

0.750
±50 0 50 100 150
TJ Junction Temperature (ƒC) C011

Figure 11. VFB VOLTAGE vs JUNCTION TEMPERATURE Figure 12. VOLTAGE RIPPLE AT OUTPUT (IO = 6 A)

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TYPICAL CHARACTERISTICS (continued)

VIN = 12 V, TA = 25°C (unless otherwise noted).
7.00

Vo=1.05V VIN(50mV/div) 6.00

5.00

Output Current (A)

4.00

SW(5V/div) 3.00
VO=1.05V
2.00 VO=1.8V

1.00 VO=3.3V
VO=5V
400ns/div 0.00
-50 0 50 100
Ta Ambient Temperature (ºC) C012

Figure 13. VOLTAGE RIPPLE AT INPUT (IO = 6 A) Figure 14. OUTPUT CURRENT vs AMBIENT TEMPERATURE

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DESIGN GUIDE

Step-By-Step Design Procedure

To begin the design process, the user must know a few application parameters:
• Input voltage range
• Output voltage
• Output current
• Output voltage ripple
• Input voltage ripple

U1
TPS54627DDA

Figure 15. Shows the schematic diagram for this design example.

Output Voltage Resistors Selection

The output voltage is set with a resistor divider from the output node to the VFB pin. It is recommended to use
1% tolerance or better divider resistors. Start by using Equation 2 to calculate VOUT.
To improve efficiency at light loads consider using larger value resistors, high resistance is more susceptible to
noise, and the voltage errors from the VFB input current are more noticeable.
æ R1÷ ö
V = 0.765 x çç1 + ÷
OUT çè R2 ÷ø (2)

Output Filter Selection

The output filter used with the TPS54627 is an LC circuit. This LC filter has double pole at:
1
F =
P 2p L x COUT
OUT (3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the TPS54627. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls
off at a –40 dB per decade rate and the phase drops rapidly. D-CAP2™ introduces a high frequency zero that
reduces the gain roll off to –20 dB per decade and increases the phase to 90 degrees one decade above the
zero frequency. The inductor and capacitor selected for the output filter must be selected so that the double pole
of Equation 3 is located below the high frequency zero but close enough that the phase boost provided be the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement use the
values recommended in Table 1

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Table 1. Recommended Component Values

Output C4 (pF) (1) L1 (µH) C8 + C9 (µF)
Voltage R1 (kΩ) R2 (kΩ)
(V) MIN TYP MAX MIN TYP MAX MIN MAX

1 6.81 22.1 5 150 220 1.0 1.5 4.7 22 68

1.05 8.25 22.1 5 150 220 1.0 1.5 4.7 22 68
1.2 12.7 22.1 5 100 1.0 1.5 4.7 22 68
1.5 21.5 22.1 5 68 1.0 1.5 4.7 22 68
1.8 30.1 22.1 5 22 1.2 1.5 4.7 22 68
2.5 49.9 22.1 5 22 1.5 2.2 4.7 22 68
3.3 73.2 22.1 2 22 1.8 2.2 4.7 22 68
5 124 22.1 2 22 2.2 3.3 4.7 22 68

(1) Optional

Since the DC gain is dependent on the output voltage, the required inductor value increases as the output
voltage increases. Additional phase boost can be achieved by adding a feed forward capacitor (C4) in parallel
with R1. The feed forward capacitor is most effective for output voltages at or above 1.8 V.
The inductor peak-to-peak ripple current, peak current and RMS current are calculated using Equation 4,
Equation 5 and Equation 6. The inductor saturation current rating must be greater than the calculated peak
current and the RMS or heating current rating must be greater than the calculated RMS current. Use 650 kHz for
fSW.
Use 650 kHz for fSW. Make sure the chosen inductor is rated for the peak current of Equation 5 and the RMS
current of Equation 6.
V V - VOUT
I = OUT x IN(max)
IPP V L x f
IN(max) O SW (4)
I
lpp
I =I +
Ipeak O 2 (5)
2 1 2
I = I + I
Lo(RMS) O 12 IPP (6)
For this design example, the calculated peak current is 6.51 A and the calculated RMS current is 6.01 A. The
inductor used is a TDK SPM6530-1R5M100 with a peak current rating of 11.5 A and an RMS current rating of 11
A.
The capacitor value and ESR determines the amount of output voltage ripple. The TPS54627 is intended for use
with ceramic or other low ESR capacitors. Recommended values range from 22µF to 68µF. Use Equation 7 to
determine the required RMS current rating for the output capacitor.
VOUT x (VIN - VOUT )
I =
Co(RMS) 12 x VIN x LO x fSW
(7)
For this design two TDK C3216X5R0J226M 22µF output capacitors are used. The typical ESR is 2 mΩ each.
The calculated RMS current is 0.284 A and each output capacitor is rated for 4A.

Input Capacitor Selection

The TPS54627 requires an input decoupling capacitor and a bulk capacitor is needed depending on the
application. A ceramic capacitor over 10 μF is recommended for the decoupling capacitor. An additional 0.1 µF
capacitor (C3) from pin 8 to ground is optional to provide additional high frequency filtering. The capacitor voltage
rating needs to be greater than the maximum input voltage.

Bootstrap Capacitor Selection

A 0.1 µF. ceramic capacitor must be connected between the VBST to SW pin for proper operation. It is
recommended to use a ceramic capacitor.

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VREG5 Capacitor Selection

A 1-µF. ceramic capacitor must be connected between the VREG5 to GND pin for proper operation. It is
recommended to use a ceramic capacitor.

THERMAL INFORMATION
This 8-pin DDA package incorporates an exposed thermal pad that is designed to be directly to an external
heartsick. The thermal pad must be soldered directly to the printed board (PCB). After soldering, the PCB can be
used as a heartsick. In addition, through the use of thermal vias, the thermal pad can be attached directly to the
appropriate copper plane shown in the electrical schematic for the device, or alternatively, can be attached to a
special heartsick structure designed into the PCB. This design optimizes the heat transfer from the integrated
circuit (IC).
For additional information on the exposed thermal pad and how to use the advantage of its heat dissipating
abilities, see the Technical Brief, PowerPAD™ Thermally Enhanced Package, Texas Instruments Literature No.
SLMA002 and Application Brief, PowerPAD™ Made Easy, Texas Instruments Literature No. SLMA004.
The exposed thermal pad dimensions for this package are shown in the following illustration.

Figure 16. Thermal Pad Dimensions

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LAYOUT CONSIDERATIONS
1. The TPS54627 can supply large load currents up to 6 A, so heat dissipation may be a concern. The top side
area adjacent to the TPS54627 should be filled with ground as much as possible to dissipate heat.
2. The bottom side area directly below the IC should a dedicated ground area. It should be directly connected
to the thermal pad of the device using vias as shown. The ground area should be as large as practical.
Additional internal layers can be dedicated as ground planes and connected to the vias as well.
3. Keep the input switching current loop as small as possible.
4. Keep the SW node as physically small and short as possible to minimize parasitic capacitance and
inductance and to minimize radiated emissions. Kelvin connections should be brought from the output to the
feedback pin of the device.
5. Keep analog and non-switching components away from switching components.
6. Make a single point connection from the signal ground to power ground.
7. Do not allow switching current to flow under the device.
8. Keep the pattern lines for VIN and PGND broad.
9. Exposed pad of device must be connected to PGND with solder.
10. VREG5 capacitor should be placed near the device, and connected PGND.
11. Output capacitor should be connected to a broad pattern of the PGND.
12. Voltage feedback loop should be as short as possible, and preferably with ground shield.
13. Lower resistor of the voltage divider which is connected to the VFB pin should be tied to SGND.
14. Providing sufficient via is preferable for VIN, SW and PGND connection.
15. PCB pattern for VIN, SW, and PGND should be as broad as possible.
16. VIN Capacitor should be placed as near as possible to the device.

VIN
VIN
INPUT
BYPASS
CAPACITOR
VIN
HIGH FREQENCY
BYPASS
CAPACITOR

TO ENABLE EN VIN
CONTROL BOOST
FEEDBACK
RESISTORS VFB VBST CAPACITOR

VREG5 SW
BIAS SS GND
OUTPUT
INDUCTOR
VOUT
CAP
SLOW
START
CAP
EXPOSED
THERMAL PAD
Connection to
AREA OUTPUT
POWER GROUND FILTER
on internal or CAPACITOR
bottom layer

ANALOG
GROUND
TRACE POWER GROUND

VIA to Ground Plane

Figure 17. PCB Layout

Copyright © 2013, Texas Instruments Incorporated 15

Product Folder Links :TPS54627
 PACKAGE OPTION ADDENDUM

www.ti.com 19-May-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (3) (4/5)

TPS54627DDA ACTIVE SO PowerPAD DDA 8 75 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54627
& no Sb/Br)
TPS54627DDAR ACTIVE SO PowerPAD DDA 8 2500 Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR -40 to 125 54627
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-May-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS54627DDAR SO DDA 8 2500 330.0 12.8 6.4 5.2 2.1 8.0 12.0 Q1
Power
PAD

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 18-May-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS54627DDAR SO PowerPAD DDA 8 2500 366.0 364.0 50.0

Pack Materials-Page 2
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