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Low Power RTL Design Techniques

Low Power RTL Design techniques

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153 views20 pages

Low Power RTL Design Techniques

Low Power RTL Design techniques

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muhammedayman350
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Website: https://www.sites.google.

com/view/learnvlsi
Outline LinkedIn: https://www.linkedin.com/company/learnvlsi

⚫ Low Power RTL Design


 Clock Gating
 State machines encoding
 Minimize transitions on data path
 Control over free running counters
 Gray encoding for memory address
 Gray Coding for counters
 Bus invert coding
 Operand Isolation
 Precomputation
 Shift Register Vs Circular Buffer
 Sequential Gating

Udit Kumar, PhD, IIT Delhi.


17+ years experience, Author
https://www.linkedin.com/in/udit-kumar-phd-iit-delhi
Disclaimer
⚫ The intention of this presentation is information sharing. So
consider this material as information purpose only.
⚫ We explicitly disclaim any liability for mistakes and omissions in the
material presented.
⚫ We have done our best to ensure the correctness of the material and
have no obligation or duty to any person or organization for any loss or
damages stemming from the contents.
⚫ We make no claim, promises, or guarantees regarding the correctness,
completeness, patent infringement, copyright violation or sufficiency of
the same.
⚫ Some of materials were copied from the sources freely available on
the internet. When possible, these sources have been cited;
however, some references may have been cited incorrectly or
overlooked. If you feel that a picture, graph, or code example has
been copied from you and either needs to be cited or removed,
please feel free to email: elearn.vlsi@gmail.com and I will address
this as soon as possible.
⚫ Take prior approval for Commercial usage of this information.
⚫ Views expressed here are personal views and not endorsed by
present or past employer.
Clock Gating
⚫ Clock Gating
 Pros: Simple, Cons: Increases area and leakage

Reference: https://www.electronicsforu.com/electronics-projects/electronics-design-guides/clock-gating-iot
Glitch free clock gating

Reference: https://www.semanticscholar.org/paper/A-novel-circuit-topology-for-clock-gating-cell-for-Nejat-Abdevand/b330dc84b66e7d087d3b0c6191083b28dadcd865
Integrated Clock Gating Cell (ICG) with DFT
Multi level and Ex-OR Clock gating
⚫ Multi level clock gating

⚫ Ex-OR based clock gating

CK CK
Clock Gating Efficiency
17 Clock Cycles

Clock Gate (2 cycles) Clock Gate (7 cycles)

Left on table (3 cycles)


CG efficiency = = 100*(9/18) = 50%

Data aware gating (DAG) efficiency =


= 100* (9+5)/17 = 82.3%
(Gives an idea how much is left on the table)
State Machines encoding
⚫ Use state encoding in such a manner so that number of
transitions are reduced.
 Use one hot encoding if there are more transitions between all
FSM state.
 Use gray coding for sequential kind of state changes.

A B C D F

typedef enum {A=0, B=1, C=2, D=3, E=4} fsm_state;


A typedef enum {A=0, B=1, C=3, D=2, E=6} fsm_state; // Gray encoding

D The design is having large number of


B C
transition between D and E state.

typedef enum {A=0, B=1, C=2, D=3, E=4} fsm_state; // 3 Bit change
E typedef enum {A=0, B=4, C=3, D=2, E=1} fsm_state; // 3 Bit change
Minimize transitions on data path
⚫ Minimizing data transitions on bus
⚫ Example: Read the memory location on each rd_enable
reg [31:0] mem [64]; reg [31:0] mem [64];
always @ (posedge clk or negedge rst_n) begin always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin if (!rst_n) begin
dout <= 1’b0; dout <= 1’b0;
end else begin end else begin
if (rd_enable) begin if (rd_enable) begin
dout <= mem[rd_ptr]; dout <= mem[rd_ptr];
end else begin end
dout <= 32’b0; end
end
end // Logic for rd_ptr
..
// Logic for rd_ptr
.. end
end

With rd_enable low the value is changed. No change with rd_enable low.
Control over free running counters
⚫ Counters are used to count number to a predefined threshold
and not used further and left free running.

Once the required condition is achieved, stop the


unnecessary free running counter.
Gray encoding for memory address
⚫ For sequential memory access use gray coding for address.
⚫ Application: Memories to access chunk of data, FIFO
memories
Gray Coded
Gray Coding for counters
⚫ Using Gray code for counting to predefined values.

// 3-Bit Gray counter


reg [2:0] count;
always @ (posedge clk or negedge rst_n) begin
if (!rst_n) begin
count <= 1’b0;
end else begin
case (count)
3’b000 : count <= 3’b001;
3’b001: count <= 3’b011;
3’b011: count <= 3’b010;
3’b010: count <= 3’b110;
3’b110: count <= 3’b111;
3’b111: count <= 3’b101;
3’b101: count <= 3’b100;
3’b100: count <= 3’b000;
endcase
end
end

Assignment: Make a generic Gray counter supporting large number of bits.


Bus invert coding
⚫ Add additional line INV
 When INV=0: Data is same as on data bus
 When INV=1: Invert the data using XOR logic
⚫ At each cycle decide whether sending the true or compliment
signal leads to fewer toggles.

Data bus

Polarity
decision INV
logic
Operand Isolation
⚫ Reduce switching activity in the non active path.

+ EN +
EN

+ EN

EN
+
sel
sel
Precomputation Logic
⚫ Break down the overall operation in sub parts, and use partial
results to enable/disable remaining computation

Binary Comparator
Shift Register Vs Circular Buffer
⚫ In a shift register, values are constantly being ‘shifted’ in the
full chain, taking huge power.
⚫ Replace shift registers with circular buffers.

Reference: https://semiengineering.com/micro-architectural-exploration-for-low-power-design-2/
Sequential Gating: Observability based

⚫ Sequential Gating helps in increasing clock gating efficiency.


Sequential Gating: Stability based
Link for other presentations
⚫ Low Power Design:
 https://www.linkedin.com/feed/update/urn:li:activity:6913837834302
885888
⚫ HDL Design using Verilog
 https://www.linkedin.com/feed/update/urn:li:activity:6901101173491
798016
⚫ RTL Design Guidelines
 https://www.linkedin.com/feed/update/urn:li:activity:6903289386536
968192
⚫ Clock domain crossing:
 https://www.linkedin.com/feed/update/urn:li:activity:6906226196003
061760
⚫ VLSI Design Flows and Open source tools:
 https://www.linkedin.com/feed/update/urn:li:activity:6886886690405
924864
Thank you
Telegram Channel: https://t.me/elearnvlsi

Next webinars:
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Feedback/Errata: Please send email to elearnvlsi@gmail.com


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